PGM.cpp@ 22349

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1	/* $Id: PGM.cpp 22327 2009-08-18 14:52:08Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include <VBox/hwaccm.h>
592	#include "PGMInternal.h"
593	#include <VBox/vm.h>
594
595	#include <VBox/dbg.h>
596	#include <VBox/param.h>
597	#include <VBox/err.h>
598
599	#include <iprt/asm.h>
600	#include <iprt/assert.h>
601	#include <iprt/env.h>
602	#include <iprt/mem.h>
603	#include <iprt/file.h>
604	#include <iprt/string.h>
605	#include <iprt/thread.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
652	#endif
653
654
655	/*******************************************************************************
656	* Global Variables *
657	*******************************************************************************/
658	#ifdef VBOX_WITH_DEBUGGER
659	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
660	static const DBGCVARDESC g_aPgmErrorArgs[] =
661	{
662	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
663	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
664	};
665
666	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
667	{
668	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
669	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
670	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
671	};
672
673	/** Command descriptors. */
674	static const DBGCCMD g_aCmds[] =
675	{
676	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
677	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
678	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
679	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
680	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
681	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
682	#ifdef VBOX_STRICT
683	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
684	#endif
685	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
686	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
687	};
688	#endif
689
690
691
692
693	/*
694	* Shadow - 32-bit mode
695	*/
696	#define PGM_SHW_TYPE PGM_TYPE_32BIT
697	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
698	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
699	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
700	#include "PGMShw.h"
701
702	/* Guest - real mode */
703	#define PGM_GST_TYPE PGM_TYPE_REAL
704	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
705	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
706	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
707	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
708	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
709	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
710	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
711	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
712	#include "PGMBth.h"
713	#include "PGMGstDefs.h"
714	#include "PGMGst.h"
715	#undef BTH_PGMPOOLKIND_PT_FOR_PT
716	#undef BTH_PGMPOOLKIND_ROOT
717	#undef PGM_BTH_NAME
718	#undef PGM_BTH_NAME_RC_STR
719	#undef PGM_BTH_NAME_R0_STR
720	#undef PGM_GST_TYPE
721	#undef PGM_GST_NAME
722	#undef PGM_GST_NAME_RC_STR
723	#undef PGM_GST_NAME_R0_STR
724
725	/* Guest - protected mode */
726	#define PGM_GST_TYPE PGM_TYPE_PROT
727	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
728	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
729	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
730	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
731	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
732	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
733	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_PT
739	#undef BTH_PGMPOOLKIND_ROOT
740	#undef PGM_BTH_NAME
741	#undef PGM_BTH_NAME_RC_STR
742	#undef PGM_BTH_NAME_R0_STR
743	#undef PGM_GST_TYPE
744	#undef PGM_GST_NAME
745	#undef PGM_GST_NAME_RC_STR
746	#undef PGM_GST_NAME_R0_STR
747
748	/* Guest - 32-bit mode */
749	#define PGM_GST_TYPE PGM_TYPE_32BIT
750	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
751	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
752	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
754	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
755	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
756	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
757	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
758	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
759	#include "PGMBth.h"
760	#include "PGMGstDefs.h"
761	#include "PGMGst.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
763	#undef BTH_PGMPOOLKIND_PT_FOR_PT
764	#undef BTH_PGMPOOLKIND_ROOT
765	#undef PGM_BTH_NAME
766	#undef PGM_BTH_NAME_RC_STR
767	#undef PGM_BTH_NAME_R0_STR
768	#undef PGM_GST_TYPE
769	#undef PGM_GST_NAME
770	#undef PGM_GST_NAME_RC_STR
771	#undef PGM_GST_NAME_R0_STR
772
773	#undef PGM_SHW_TYPE
774	#undef PGM_SHW_NAME
775	#undef PGM_SHW_NAME_RC_STR
776	#undef PGM_SHW_NAME_R0_STR
777
778
779	/*
780	* Shadow - PAE mode
781	*/
782	#define PGM_SHW_TYPE PGM_TYPE_PAE
783	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
784	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
785	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
786	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
787	#include "PGMShw.h"
788
789	/* Guest - real mode */
790	#define PGM_GST_TYPE PGM_TYPE_REAL
791	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
792	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
793	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
794	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
795	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
796	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
797	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
798	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
799	#include "PGMGstDefs.h"
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_PT
802	#undef BTH_PGMPOOLKIND_ROOT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - protected mode */
812	#define PGM_GST_TYPE PGM_TYPE_PROT
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
820	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
821	#include "PGMGstDefs.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - 32-bit mode */
834	#define PGM_GST_TYPE PGM_TYPE_32BIT
835	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
844	#include "PGMGstDefs.h"
845	#include "PGMBth.h"
846	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
847	#undef BTH_PGMPOOLKIND_PT_FOR_PT
848	#undef BTH_PGMPOOLKIND_ROOT
849	#undef PGM_BTH_NAME
850	#undef PGM_BTH_NAME_RC_STR
851	#undef PGM_BTH_NAME_R0_STR
852	#undef PGM_GST_TYPE
853	#undef PGM_GST_NAME
854	#undef PGM_GST_NAME_RC_STR
855	#undef PGM_GST_NAME_R0_STR
856
857	/* Guest - PAE mode */
858	#define PGM_GST_TYPE PGM_TYPE_PAE
859	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
860	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
861	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
862	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
863	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
864	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
865	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
866	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
867	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
868	#include "PGMBth.h"
869	#include "PGMGstDefs.h"
870	#include "PGMGst.h"
871	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
872	#undef BTH_PGMPOOLKIND_PT_FOR_PT
873	#undef BTH_PGMPOOLKIND_ROOT
874	#undef PGM_BTH_NAME
875	#undef PGM_BTH_NAME_RC_STR
876	#undef PGM_BTH_NAME_R0_STR
877	#undef PGM_GST_TYPE
878	#undef PGM_GST_NAME
879	#undef PGM_GST_NAME_RC_STR
880	#undef PGM_GST_NAME_R0_STR
881
882	#undef PGM_SHW_TYPE
883	#undef PGM_SHW_NAME
884	#undef PGM_SHW_NAME_RC_STR
885	#undef PGM_SHW_NAME_R0_STR
886
887
888	/*
889	* Shadow - AMD64 mode
890	*/
891	#define PGM_SHW_TYPE PGM_TYPE_AMD64
892	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
893	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
894	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
895	#include "PGMShw.h"
896
897	#ifdef VBOX_WITH_64_BITS_GUESTS
898	/* Guest - AMD64 mode */
899	# define PGM_GST_TYPE PGM_TYPE_AMD64
900	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
901	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
902	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
903	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
904	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
905	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
906	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
907	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
908	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
909	# include "PGMBth.h"
910	# include "PGMGstDefs.h"
911	# include "PGMGst.h"
912	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
913	# undef BTH_PGMPOOLKIND_PT_FOR_PT
914	# undef BTH_PGMPOOLKIND_ROOT
915	# undef PGM_BTH_NAME
916	# undef PGM_BTH_NAME_RC_STR
917	# undef PGM_BTH_NAME_R0_STR
918	# undef PGM_GST_TYPE
919	# undef PGM_GST_NAME
920	# undef PGM_GST_NAME_RC_STR
921	# undef PGM_GST_NAME_R0_STR
922	#endif /* VBOX_WITH_64_BITS_GUESTS */
923
924	#undef PGM_SHW_TYPE
925	#undef PGM_SHW_NAME
926	#undef PGM_SHW_NAME_RC_STR
927	#undef PGM_SHW_NAME_R0_STR
928
929
930	/*
931	* Shadow - Nested paging mode
932	*/
933	#define PGM_SHW_TYPE PGM_TYPE_NESTED
934	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
935	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
936	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
937	#include "PGMShw.h"
938
939	/* Guest - real mode */
940	#define PGM_GST_TYPE PGM_TYPE_REAL
941	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
942	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
943	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
944	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
945	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
946	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
947	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
948	#include "PGMGstDefs.h"
949	#include "PGMBth.h"
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_RC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_RC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - protected mode */
960	#define PGM_GST_TYPE PGM_TYPE_PROT
961	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
962	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
965	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
968	#include "PGMGstDefs.h"
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_PT
971	#undef PGM_BTH_NAME
972	#undef PGM_BTH_NAME_RC_STR
973	#undef PGM_BTH_NAME_R0_STR
974	#undef PGM_GST_TYPE
975	#undef PGM_GST_NAME
976	#undef PGM_GST_NAME_RC_STR
977	#undef PGM_GST_NAME_R0_STR
978
979	/* Guest - 32-bit mode */
980	#define PGM_GST_TYPE PGM_TYPE_32BIT
981	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
982	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
983	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
984	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
985	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
986	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
987	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
988	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
989	#include "PGMGstDefs.h"
990	#include "PGMBth.h"
991	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
992	#undef BTH_PGMPOOLKIND_PT_FOR_PT
993	#undef PGM_BTH_NAME
994	#undef PGM_BTH_NAME_RC_STR
995	#undef PGM_BTH_NAME_R0_STR
996	#undef PGM_GST_TYPE
997	#undef PGM_GST_NAME
998	#undef PGM_GST_NAME_RC_STR
999	#undef PGM_GST_NAME_R0_STR
1000
1001	/* Guest - PAE mode */
1002	#define PGM_GST_TYPE PGM_TYPE_PAE
1003	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1004	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1005	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1006	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1007	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1008	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1009	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1010	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1011	#include "PGMGstDefs.h"
1012	#include "PGMBth.h"
1013	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1014	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1015	#undef PGM_BTH_NAME
1016	#undef PGM_BTH_NAME_RC_STR
1017	#undef PGM_BTH_NAME_R0_STR
1018	#undef PGM_GST_TYPE
1019	#undef PGM_GST_NAME
1020	#undef PGM_GST_NAME_RC_STR
1021	#undef PGM_GST_NAME_R0_STR
1022
1023	#ifdef VBOX_WITH_64_BITS_GUESTS
1024	/* Guest - AMD64 mode */
1025	# define PGM_GST_TYPE PGM_TYPE_AMD64
1026	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1027	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1028	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1029	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1030	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1031	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1032	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1033	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1034	# include "PGMGstDefs.h"
1035	# include "PGMBth.h"
1036	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1037	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	# undef PGM_BTH_NAME
1039	# undef PGM_BTH_NAME_RC_STR
1040	# undef PGM_BTH_NAME_R0_STR
1041	# undef PGM_GST_TYPE
1042	# undef PGM_GST_NAME
1043	# undef PGM_GST_NAME_RC_STR
1044	# undef PGM_GST_NAME_R0_STR
1045	#endif /* VBOX_WITH_64_BITS_GUESTS */
1046
1047	#undef PGM_SHW_TYPE
1048	#undef PGM_SHW_NAME
1049	#undef PGM_SHW_NAME_RC_STR
1050	#undef PGM_SHW_NAME_R0_STR
1051
1052
1053	/*
1054	* Shadow - EPT
1055	*/
1056	#define PGM_SHW_TYPE PGM_TYPE_EPT
1057	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1058	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1059	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1060	#include "PGMShw.h"
1061
1062	/* Guest - real mode */
1063	#define PGM_GST_TYPE PGM_TYPE_REAL
1064	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1065	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1066	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1067	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1068	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1069	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1070	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1071	#include "PGMGstDefs.h"
1072	#include "PGMBth.h"
1073	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1074	#undef PGM_BTH_NAME
1075	#undef PGM_BTH_NAME_RC_STR
1076	#undef PGM_BTH_NAME_R0_STR
1077	#undef PGM_GST_TYPE
1078	#undef PGM_GST_NAME
1079	#undef PGM_GST_NAME_RC_STR
1080	#undef PGM_GST_NAME_R0_STR
1081
1082	/* Guest - protected mode */
1083	#define PGM_GST_TYPE PGM_TYPE_PROT
1084	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1085	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1086	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1087	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1088	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1089	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1090	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1091	#include "PGMGstDefs.h"
1092	#include "PGMBth.h"
1093	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1094	#undef PGM_BTH_NAME
1095	#undef PGM_BTH_NAME_RC_STR
1096	#undef PGM_BTH_NAME_R0_STR
1097	#undef PGM_GST_TYPE
1098	#undef PGM_GST_NAME
1099	#undef PGM_GST_NAME_RC_STR
1100	#undef PGM_GST_NAME_R0_STR
1101
1102	/* Guest - 32-bit mode */
1103	#define PGM_GST_TYPE PGM_TYPE_32BIT
1104	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1105	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1106	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1107	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1108	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1109	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1111	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1112	#include "PGMGstDefs.h"
1113	#include "PGMBth.h"
1114	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1115	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1116	#undef PGM_BTH_NAME
1117	#undef PGM_BTH_NAME_RC_STR
1118	#undef PGM_BTH_NAME_R0_STR
1119	#undef PGM_GST_TYPE
1120	#undef PGM_GST_NAME
1121	#undef PGM_GST_NAME_RC_STR
1122	#undef PGM_GST_NAME_R0_STR
1123
1124	/* Guest - PAE mode */
1125	#define PGM_GST_TYPE PGM_TYPE_PAE
1126	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1127	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1128	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1129	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1130	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1131	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1132	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1133	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1134	#include "PGMGstDefs.h"
1135	#include "PGMBth.h"
1136	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1137	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1138	#undef PGM_BTH_NAME
1139	#undef PGM_BTH_NAME_RC_STR
1140	#undef PGM_BTH_NAME_R0_STR
1141	#undef PGM_GST_TYPE
1142	#undef PGM_GST_NAME
1143	#undef PGM_GST_NAME_RC_STR
1144	#undef PGM_GST_NAME_R0_STR
1145
1146	#ifdef VBOX_WITH_64_BITS_GUESTS
1147	/* Guest - AMD64 mode */
1148	# define PGM_GST_TYPE PGM_TYPE_AMD64
1149	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1150	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1151	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1152	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1153	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1154	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1155	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1156	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1157	# include "PGMGstDefs.h"
1158	# include "PGMBth.h"
1159	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1160	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1161	# undef PGM_BTH_NAME
1162	# undef PGM_BTH_NAME_RC_STR
1163	# undef PGM_BTH_NAME_R0_STR
1164	# undef PGM_GST_TYPE
1165	# undef PGM_GST_NAME
1166	# undef PGM_GST_NAME_RC_STR
1167	# undef PGM_GST_NAME_R0_STR
1168	#endif /* VBOX_WITH_64_BITS_GUESTS */
1169
1170	#undef PGM_SHW_TYPE
1171	#undef PGM_SHW_NAME
1172	#undef PGM_SHW_NAME_RC_STR
1173	#undef PGM_SHW_NAME_R0_STR
1174
1175
1176
1177	/**
1178	* Initiates the paging of VM.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM Pointer to VM structure.
1182	*/
1183	VMMR3DECL(int) PGMR3Init(PVM pVM)
1184	{
1185	LogFlow(("PGMR3Init:\n"));
1186	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1187	int rc;
1188
1189	/*
1190	* Assert alignment and sizes.
1191	*/
1192	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1193	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1194
1195	/*
1196	* Init the structure.
1197	*/
1198	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1199	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1200
1201	/* Init the per-CPU part. */
1202	for (unsigned i=0;i<pVM->cCPUs;i++)
1203	{
1204	PVMCPU pVCpu = &pVM->aCpus[i];
1205	PPGMCPU pPGM = &pVCpu->pgm.s;
1206
1207	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1208	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1209	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1210
1211	pPGM->enmShadowMode = PGMMODE_INVALID;
1212	pPGM->enmGuestMode = PGMMODE_INVALID;
1213
1214	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1215
1216	pPGM->pGstPaePdptR3 = NULL;
1217	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1218	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1219	#endif
1220	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1221	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1222	{
1223	pPGM->apGstPaePDsR3[i] = NULL;
1224	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1226	#endif
1227	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1228	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1229	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1230	}
1231
1232	pPGM->fA20Enabled = true;
1233	}
1234
1235	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1236	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1237	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1238
1239	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1240	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1241	true
1242	#else
1243	false
1244	#endif
1245	);
1246	AssertLogRelRCReturn(rc, rc);
1247
1248	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1249	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1250	#else
1251	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1252	#endif
1253	AssertLogRelRCReturn(rc, rc);
1254	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1255	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1256
1257	/*
1258	* Get the configured RAM size - to estimate saved state size.
1259	*/
1260	uint64_t cbRam;
1261	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1262	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1263	cbRam = 0;
1264	else if (RT_SUCCESS(rc))
1265	{
1266	if (cbRam < PAGE_SIZE)
1267	cbRam = 0;
1268	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1269	}
1270	else
1271	{
1272	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1273	return rc;
1274	}
1275
1276	/*
1277	* Register callbacks, string formatters and the saved state data unit.
1278	*/
1279	#ifdef VBOX_STRICT
1280	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1281	#endif
1282	PGMRegisterStringFormatTypes();
1283
1284	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1285	NULL, pgmR3Save, NULL,
1286	NULL, pgmR3Load, NULL);
1287	if (RT_FAILURE(rc))
1288	return rc;
1289
1290	/*
1291	* Initialize the PGM critical section and flush the phys TLBs
1292	*/
1293	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1294	AssertRCReturn(rc, rc);
1295
1296	PGMR3PhysChunkInvalidateTLB(pVM);
1297	PGMPhysInvalidatePageR3MapTLB(pVM);
1298	PGMPhysInvalidatePageR0MapTLB(pVM);
1299	PGMPhysInvalidatePageGCMapTLB(pVM);
1300
1301	/*
1302	* For the time being we sport a full set of handy pages in addition to the base
1303	* memory to simplify things.
1304	*/
1305	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1306	AssertRCReturn(rc, rc);
1307
1308	/*
1309	* Trees
1310	*/
1311	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1312	if (RT_SUCCESS(rc))
1313	{
1314	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1315	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1316
1317	/*
1318	* Alocate the zero page.
1319	*/
1320	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1321	}
1322	if (RT_SUCCESS(rc))
1323	{
1324	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1325	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1326	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1327	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1328
1329	/*
1330	* Init the paging.
1331	*/
1332	rc = pgmR3InitPaging(pVM);
1333	}
1334	if (RT_SUCCESS(rc))
1335	{
1336	/*
1337	* Init the page pool.
1338	*/
1339	rc = pgmR3PoolInit(pVM);
1340	}
1341	if (RT_SUCCESS(rc))
1342	{
1343	for (unsigned i=0;i<pVM->cCPUs;i++)
1344	{
1345	PVMCPU pVCpu = &pVM->aCpus[i];
1346
1347	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1348	if (RT_FAILURE(rc))
1349	break;
1350	}
1351	}
1352
1353	if (RT_SUCCESS(rc))
1354	{
1355	/*
1356	* Info & statistics
1357	*/
1358	DBGFR3InfoRegisterInternal(pVM, "mode",
1359	"Shows the current paging mode. "
1360	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1361	pgmR3InfoMode);
1362	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1363	"Dumps all the entries in the top level paging table. No arguments.",
1364	pgmR3InfoCr3);
1365	DBGFR3InfoRegisterInternal(pVM, "phys",
1366	"Dumps all the physical address ranges. No arguments.",
1367	pgmR3PhysInfo);
1368	DBGFR3InfoRegisterInternal(pVM, "handlers",
1369	"Dumps physical, virtual and hyper virtual handlers. "
1370	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1371	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1372	pgmR3InfoHandlers);
1373	DBGFR3InfoRegisterInternal(pVM, "mappings",
1374	"Dumps guest mappings.",
1375	pgmR3MapInfo);
1376
1377	pgmR3InitStats(pVM);
1378
1379	#ifdef VBOX_WITH_DEBUGGER
1380	/*
1381	* Debugger commands.
1382	*/
1383	static bool s_fRegisteredCmds = false;
1384	if (!s_fRegisteredCmds)
1385	{
1386	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1387	if (RT_SUCCESS(rc))
1388	s_fRegisteredCmds = true;
1389	}
1390	#endif
1391	return VINF_SUCCESS;
1392	}
1393
1394	/* Almost no cleanup necessary, MM frees all memory. */
1395	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1396
1397	return rc;
1398	}
1399
1400
1401	/**
1402	* Initializes the per-VCPU PGM.
1403	*
1404	* @returns VBox status code.
1405	* @param pVM The VM to operate on.
1406	*/
1407	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1408	{
1409	LogFlow(("PGMR3InitCPU\n"));
1410	return VINF_SUCCESS;
1411	}
1412
1413
1414	/**
1415	* Init paging.
1416	*
1417	* Since we need to check what mode the host is operating in before we can choose
1418	* the right paging functions for the host we have to delay this until R0 has
1419	* been initialized.
1420	*
1421	* @returns VBox status code.
1422	* @param pVM VM handle.
1423	*/
1424	static int pgmR3InitPaging(PVM pVM)
1425	{
1426	/*
1427	* Force a recalculation of modes and switcher so everyone gets notified.
1428	*/
1429	for (unsigned i=0;i<pVM->cCPUs;i++)
1430	{
1431	PVMCPU pVCpu = &pVM->aCpus[i];
1432
1433	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1434	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1435	}
1436
1437	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1438
1439	/*
1440	* Allocate static mapping space for whatever the cr3 register
1441	* points to and in the case of PAE mode to the 4 PDs.
1442	*/
1443	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1444	if (RT_FAILURE(rc))
1445	{
1446	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1447	return rc;
1448	}
1449	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1450
1451	/*
1452	* Allocate pages for the three possible intermediate contexts
1453	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1454	* for the sake of simplicity. The AMD64 uses the PAE for the
1455	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1456	*
1457	* We assume that two page tables will be enought for the core code
1458	* mappings (HC virtual and identity).
1459	*/
1460	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1471	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1472
1473	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1474	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1475	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1476	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1477	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1478	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1479
1480	/*
1481	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1482	*/
1483	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1485	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1486
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1488	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1489
1490	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1491	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1492	{
1493	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1494	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1495	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1496	}
1497
1498	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1499	{
1500	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1501	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1502	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1503	}
1504
1505	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1506	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1507	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1508	\| HCPhysInterPaePDPT64;
1509
1510	/*
1511	* Initialize paging workers and mode from current host mode
1512	* and the guest running in real mode.
1513	*/
1514	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1515	switch (pVM->pgm.s.enmHostMode)
1516	{
1517	case SUPPAGINGMODE_32_BIT:
1518	case SUPPAGINGMODE_32_BIT_GLOBAL:
1519	case SUPPAGINGMODE_PAE:
1520	case SUPPAGINGMODE_PAE_GLOBAL:
1521	case SUPPAGINGMODE_PAE_NX:
1522	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1523	break;
1524
1525	case SUPPAGINGMODE_AMD64:
1526	case SUPPAGINGMODE_AMD64_GLOBAL:
1527	case SUPPAGINGMODE_AMD64_NX:
1528	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1529	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1530	if (ARCH_BITS != 64)
1531	{
1532	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1533	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1534	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1535	}
1536	#endif
1537	break;
1538	default:
1539	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1540	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1541	}
1542	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1543	if (RT_SUCCESS(rc))
1544	{
1545	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1546	#if HC_ARCH_BITS == 64
1547	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1548	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1549	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1550	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1552	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1553	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1554	#endif
1555
1556	return VINF_SUCCESS;
1557	}
1558
1559	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1560	return rc;
1561	}
1562
1563
1564	/**
1565	* Init statistics
1566	*/
1567	static void pgmR3InitStats(PVM pVM)
1568	{
1569	PPGM pPGM = &pVM->pgm.s;
1570	int rc;
1571
1572	/* Common - misc variables */
1573	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1574	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1575	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1576	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1577	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1578	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1579	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1580	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1581
1582	#ifdef VBOX_WITH_STATISTICS
1583
1584	# define PGM_REG_COUNTER(a, b, c) \
1585	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1586	AssertRC(rc);
1587
1588	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1589	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1590	AssertRC(rc);
1591
1592	# define PGM_REG_PROFILE(a, b, c) \
1593	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1594	AssertRC(rc);
1595
1596	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1597	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1598	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1599	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1600	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1601	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1602	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1603	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1604	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1605	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1606
1607	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1608	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1609	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1610	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1611	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1612	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1613	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1614	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1615
1616	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1617	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1618	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1619	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1620
1621	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1622	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1623	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1624	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1625
1626	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1627	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1628	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1629	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1630	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1631	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1632
1633	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1635	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1636	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1637	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1638	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1639	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1640	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1641
1642	/* GC only: */
1643	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1644	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1645	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1646	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1647
1648	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1649	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1650	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1651	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1652	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1653	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1654	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1655	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1656
1657	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1658	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1659	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1660	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1661	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1662	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1663	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1664	# endif
1665
1666	# undef PGM_REG_COUNTER
1667	# undef PGM_REG_PROFILE
1668	#endif
1669
1670	/*
1671	* Note! The layout below matches the member layout exactly!
1672	*/
1673
1674	/*
1675	* Common - stats
1676	*/
1677	for (unsigned i=0;i<pVM->cCPUs;i++)
1678	{
1679	PVMCPU pVCpu = &pVM->aCpus[i];
1680	PPGMCPU pPGM = &pVCpu->pgm.s;
1681
1682	#define PGM_REG_COUNTER(a, b, c) \
1683	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1684	AssertRC(rc);
1685	#define PGM_REG_PROFILE(a, b, c) \
1686	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1687	AssertRC(rc);
1688
1689	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1690
1691	#ifdef VBOX_WITH_STATISTICS
1692
1693	# if 0 /* rarely useful; leave for debugging. */
1694	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1695	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1696	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1697	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1698	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1699	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1700	# endif
1701	/* R0 only: */
1702	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1703	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1704	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1705	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1706	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1707	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1708	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1709	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1713	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1714	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1715	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1716	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1717	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1718	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1719	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1720	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1721	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1722	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1723	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1724	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1725	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1726	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1727	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1728	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1729	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1730	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1731	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1732	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1733	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1734	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1735	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1736	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1737	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1738
1739	/* RZ only: */
1740	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1747	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1748	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1749	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1750	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1751	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1752	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1753	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1754	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1755	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1756	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1757	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1772	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1773	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1774	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1775	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1776	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1777	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1778	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1779	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1780	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1781	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1782	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1783	#if 0 /* rarely useful; leave for debugging. */
1784	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1785	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1786	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1787	#endif
1788	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1789	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1790	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1791	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1792	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1793
1794	/* HC only: */
1795
1796	/* RZ & R3: */
1797	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1798	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1799	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1801	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1802	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1803	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1804	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1805	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1806	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1807	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1808	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1809	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1810	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1811	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1812	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1813	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1814	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1815	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1816	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1817	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1818	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1819	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1820	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1821	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1822	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1823	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1824	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1825	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1826	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1827	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1828	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1829	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1830	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1831	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1832	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1833	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1834	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1835	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1836	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1837	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1838	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1839	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1840	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1841
1842	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1843	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1844	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1846	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1847	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1848	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1849	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1850	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1851	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1852	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1853	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1854	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1855	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1856	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1857	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1858	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1859	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1860	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1861	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1862	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1863	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1864	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1865	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1866	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1867	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1868	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1869	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1870	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1871	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1872	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1873	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1874	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1875	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1876	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1877	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1878	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1879	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1880	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1881	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1882	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1883	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1884	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1885	#endif /* VBOX_WITH_STATISTICS */
1886
1887	#undef PGM_REG_PROFILE
1888	#undef PGM_REG_COUNTER
1889
1890	}
1891	}
1892
1893
1894	/**
1895	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1896	*
1897	* The dynamic mapping area will also be allocated and initialized at this
1898	* time. We could allocate it during PGMR3Init of course, but the mapping
1899	* wouldn't be allocated at that time preventing us from setting up the
1900	* page table entries with the dummy page.
1901	*
1902	* @returns VBox status code.
1903	* @param pVM VM handle.
1904	*/
1905	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1906	{
1907	RTGCPTR GCPtr;
1908	int rc;
1909
1910	/*
1911	* Reserve space for the dynamic mappings.
1912	*/
1913	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1914	if (RT_SUCCESS(rc))
1915	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1916
1917	if ( RT_SUCCESS(rc)
1918	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1919	{
1920	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1921	if (RT_SUCCESS(rc))
1922	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1923	}
1924	if (RT_SUCCESS(rc))
1925	{
1926	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1927	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1928	}
1929	return rc;
1930	}
1931
1932
1933	/**
1934	* Ring-3 init finalizing.
1935	*
1936	* @returns VBox status code.
1937	* @param pVM The VM handle.
1938	*/
1939	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1940	{
1941	int rc;
1942
1943	/*
1944	* Reserve space for the dynamic mappings.
1945	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1946	*/
1947	/* get the pointer to the page table entries. */
1948	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1949	AssertRelease(pMapping);
1950	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1951	const unsigned iPT = off >> X86_PD_SHIFT;
1952	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1953	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1954	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1955
1956	/* init cache */
1957	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1958	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1959	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1960
1961	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1962	{
1963	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1964	AssertRCReturn(rc, rc);
1965	}
1966
1967	/*
1968	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1969	* Intel only goes up to 36 bits, so we stick to 36 as well.
1970	*/
1971	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1972	uint32_t u32Dummy, u32Features;
1973	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1974
1975	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1976	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1977	else
1978	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1979
1980	/*
1981	* Allocate memory if we're supposed to do that.
1982	*/
1983	if (pVM->pgm.s.fRamPreAlloc)
1984	rc = pgmR3PhysRamPreAllocate(pVM);
1985
1986	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1987	return rc;
1988	}
1989
1990
1991	/**
1992	* Applies relocations to data and code managed by this component.
1993	*
1994	* This function will be called at init and whenever the VMM need to relocate it
1995	* self inside the GC.
1996	*
1997	* @param pVM The VM.
1998	* @param offDelta Relocation delta relative to old location.
1999	*/
2000	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2001	{
2002	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2003
2004	/*
2005	* Paging stuff.
2006	*/
2007	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2008
2009	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2010
2011	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2012	for (unsigned i=0;i<pVM->cCPUs;i++)
2013	{
2014	PVMCPU pVCpu = &pVM->aCpus[i];
2015
2016	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2017
2018	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2019	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2020	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2021	}
2022
2023	/*
2024	* Trees.
2025	*/
2026	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2027
2028	/*
2029	* Ram ranges.
2030	*/
2031	if (pVM->pgm.s.pRamRangesR3)
2032	{
2033	/* Update the pSelfRC pointers and relink them. */
2034	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2035	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2036	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2037	pgmR3PhysRelinkRamRanges(pVM);
2038	}
2039
2040	/*
2041	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2042	* be mapped and thus not included in the above exercise.
2043	*/
2044	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2045	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2046	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2047
2048	/*
2049	* Update the two page directories with all page table mappings.
2050	* (One or more of them have changed, that's why we're here.)
2051	*/
2052	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2053	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2054	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2055
2056	/* Relocate GC addresses of Page Tables. */
2057	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2058	{
2059	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2060	{
2061	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2062	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2063	}
2064	}
2065
2066	/*
2067	* Dynamic page mapping area.
2068	*/
2069	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2070	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2071	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2072
2073	/*
2074	* The Zero page.
2075	*/
2076	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2077	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2078	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2079	#else
2080	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2081	#endif
2082
2083	/*
2084	* Physical and virtual handlers.
2085	*/
2086	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2087	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2088	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2089
2090	/*
2091	* The page pool.
2092	*/
2093	pgmR3PoolRelocate(pVM);
2094	}
2095
2096
2097	/**
2098	* Callback function for relocating a physical access handler.
2099	*
2100	* @returns 0 (continue enum)
2101	* @param pNode Pointer to a PGMPHYSHANDLER node.
2102	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2103	* not certain the delta will fit in a void pointer for all possible configs.
2104	*/
2105	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2106	{
2107	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2108	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2109	if (pHandler->pfnHandlerRC)
2110	pHandler->pfnHandlerRC += offDelta;
2111	if (pHandler->pvUserRC >= 0x10000)
2112	pHandler->pvUserRC += offDelta;
2113	return 0;
2114	}
2115
2116
2117	/**
2118	* Callback function for relocating a virtual access handler.
2119	*
2120	* @returns 0 (continue enum)
2121	* @param pNode Pointer to a PGMVIRTHANDLER node.
2122	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2123	* not certain the delta will fit in a void pointer for all possible configs.
2124	*/
2125	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2126	{
2127	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2128	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2129	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2130	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2131	Assert(pHandler->pfnHandlerRC);
2132	pHandler->pfnHandlerRC += offDelta;
2133	return 0;
2134	}
2135
2136
2137	/**
2138	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2139	*
2140	* @returns 0 (continue enum)
2141	* @param pNode Pointer to a PGMVIRTHANDLER node.
2142	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2143	* not certain the delta will fit in a void pointer for all possible configs.
2144	*/
2145	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2146	{
2147	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2148	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2149	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2150	Assert(pHandler->pfnHandlerRC);
2151	pHandler->pfnHandlerRC += offDelta;
2152	return 0;
2153	}
2154
2155
2156	/**
2157	* The VM is being reset.
2158	*
2159	* For the PGM component this means that any PD write monitors
2160	* needs to be removed.
2161	*
2162	* @param pVM VM handle.
2163	*/
2164	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2165	{
2166	int rc;
2167
2168	LogFlow(("PGMR3Reset:\n"));
2169	VM_ASSERT_EMT(pVM);
2170
2171	pgmLock(pVM);
2172
2173	/*
2174	* Unfix any fixed mappings and disable CR3 monitoring.
2175	*/
2176	pVM->pgm.s.fMappingsFixed = false;
2177	pVM->pgm.s.GCPtrMappingFixed = 0;
2178	pVM->pgm.s.cbMappingFixed = 0;
2179
2180	/* Exit the guest paging mode before the pgm pool gets reset.
2181	* Important to clean up the amd64 case.
2182	*/
2183	for (unsigned i=0;i<pVM->cCPUs;i++)
2184	{
2185	PVMCPU pVCpu = &pVM->aCpus[i];
2186
2187	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2188	AssertRC(rc);
2189	}
2190
2191	#ifdef DEBUG
2192	DBGFR3InfoLog(pVM, "mappings", NULL);
2193	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2194	#endif
2195
2196	/*
2197	* Switch mode back to real mode. (before resetting the pgm pool!)
2198	*/
2199	for (unsigned i=0;i<pVM->cCPUs;i++)
2200	{
2201	PVMCPU pVCpu = &pVM->aCpus[i];
2202
2203	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2204	AssertRC(rc);
2205
2206	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2207	}
2208
2209	/*
2210	* Reset the shadow page pool.
2211	*/
2212	pgmR3PoolReset(pVM);
2213
2214	for (unsigned i=0;i<pVM->cCPUs;i++)
2215	{
2216	PVMCPU pVCpu = &pVM->aCpus[i];
2217
2218	/*
2219	* Re-init other members.
2220	*/
2221	pVCpu->pgm.s.fA20Enabled = true;
2222
2223	/*
2224	* Clear the FFs PGM owns.
2225	*/
2226	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2227	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2228	}
2229
2230	/*
2231	* Reset (zero) RAM pages.
2232	*/
2233	rc = pgmR3PhysRamReset(pVM);
2234	if (RT_SUCCESS(rc))
2235	{
2236	/*
2237	* Reset (zero) shadow ROM pages.
2238	*/
2239	rc = pgmR3PhysRomReset(pVM);
2240	}
2241
2242	pgmUnlock(pVM);
2243	//return rc;
2244	AssertReleaseRC(rc);
2245	}
2246
2247
2248	#ifdef VBOX_STRICT
2249	/**
2250	* VM state change callback for clearing fNoMorePhysWrites after
2251	* a snapshot has been created.
2252	*/
2253	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2254	{
2255	if (enmState == VMSTATE_RUNNING)
2256	pVM->pgm.s.fNoMorePhysWrites = false;
2257	}
2258	#endif
2259
2260
2261	/**
2262	* Terminates the PGM.
2263	*
2264	* @returns VBox status code.
2265	* @param pVM Pointer to VM structure.
2266	*/
2267	VMMR3DECL(int) PGMR3Term(PVM pVM)
2268	{
2269	PGMDeregisterStringFormatTypes();
2270	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2271	}
2272
2273
2274	/**
2275	* Terminates the per-VCPU PGM.
2276	*
2277	* Termination means cleaning up and freeing all resources,
2278	* the VM it self is at this point powered off or suspended.
2279	*
2280	* @returns VBox status code.
2281	* @param pVM The VM to operate on.
2282	*/
2283	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2284	{
2285	return 0;
2286	}
2287
2288
2289	/**
2290	* Find the ROM tracking structure for the given page.
2291	*
2292	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2293	* that it's a ROM page.
2294	* @param pVM The VM handle.
2295	* @param GCPhys The address of the ROM page.
2296	*/
2297	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2298	{
2299	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2300	pRomRange;
2301	pRomRange = pRomRange->CTX_SUFF(pNext))
2302	{
2303	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2304	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2305	return &pRomRange->aPages[off >> PAGE_SHIFT];
2306	}
2307	return NULL;
2308	}
2309
2310
2311	/**
2312	* Save zero indicator + bits for the specified page.
2313	*
2314	* @returns VBox status code, errors are logged/asserted before returning.
2315	* @param pVM The VM handle.
2316	* @param pSSH The saved state handle.
2317	* @param pPage The page to save.
2318	* @param GCPhys The address of the page.
2319	* @param pRam The ram range (for error logging).
2320	*/
2321	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2322	{
2323	int rc;
2324	if (PGM_PAGE_IS_ZERO(pPage))
2325	rc = SSMR3PutU8(pSSM, 0);
2326	else
2327	{
2328	void const *pvPage;
2329	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2330	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2331
2332	SSMR3PutU8(pSSM, 1);
2333	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2334	}
2335	return rc;
2336	}
2337
2338
2339	/**
2340	* Save a shadowed ROM page.
2341	*
2342	* Format: Type, protection, and two pages with zero indicators.
2343	*
2344	* @returns VBox status code, errors are logged/asserted before returning.
2345	* @param pVM The VM handle.
2346	* @param pSSH The saved state handle.
2347	* @param pPage The page to save.
2348	* @param GCPhys The address of the page.
2349	* @param pRam The ram range (for error logging).
2350	*/
2351	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2352	{
2353	/* Need to save both pages and the current state. */
2354	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2355	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2356
2357	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2358	SSMR3PutU8(pSSM, pRomPage->enmProt);
2359
2360	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2361	if (RT_SUCCESS(rc))
2362	{
2363	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2364	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2365	}
2366	return rc;
2367	}
2368
2369	/** PGM fields to save/load. */
2370	static const SSMFIELD s_aPGMFields[] =
2371	{
2372	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2373	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2374	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2375	SSMFIELD_ENTRY_TERM()
2376	};
2377
2378	static const SSMFIELD s_aPGMCpuFields[] =
2379	{
2380	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2381	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2382	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2383	SSMFIELD_ENTRY_TERM()
2384	};
2385
2386	/* For loading old saved states. (pre-smp) */
2387	typedef struct
2388	{
2389	/** If set no conflict checks are required. (boolean) */
2390	bool fMappingsFixed;
2391	/** Size of fixed mapping */
2392	uint32_t cbMappingFixed;
2393	/** Base address (GC) of fixed mapping */
2394	RTGCPTR GCPtrMappingFixed;
2395	/** A20 gate mask.
2396	* Our current approach to A20 emulation is to let REM do it and don't bother
2397	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2398	* But whould need arrise, we'll subject physical addresses to this mask. */
2399	RTGCPHYS GCPhysA20Mask;
2400	/** A20 gate state - boolean! */
2401	bool fA20Enabled;
2402	/** The guest paging mode. */
2403	PGMMODE enmGuestMode;
2404	} PGMOLD;
2405
2406	static const SSMFIELD s_aPGMFields_Old[] =
2407	{
2408	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2409	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2410	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2411	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2412	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2413	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2414	SSMFIELD_ENTRY_TERM()
2415	};
2416
2417
2418	/**
2419	* Execute state save operation.
2420	*
2421	* @returns VBox status code.
2422	* @param pVM VM Handle.
2423	* @param pSSM SSM operation handle.
2424	*/
2425	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2426	{
2427	int rc;
2428	unsigned i;
2429	PPGM pPGM = &pVM->pgm.s;
2430
2431	/*
2432	* Lock PGM and set the no-more-writes indicator.
2433	*/
2434	pgmLock(pVM);
2435	pVM->pgm.s.fNoMorePhysWrites = true;
2436
2437	/*
2438	* Save basic data (required / unaffected by relocation).
2439	*/
2440	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2441
2442	for (i=0;i<pVM->cCPUs;i++)
2443	{
2444	PVMCPU pVCpu = &pVM->aCpus[i];
2445
2446	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2447	}
2448
2449	/*
2450	* The guest mappings.
2451	*/
2452	i = 0;
2453	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2454	{
2455	SSMR3PutU32( pSSM, i);
2456	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2457	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2458	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2459	}
2460	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2461
2462	/*
2463	* Ram ranges and the memory they describe.
2464	*/
2465	i = 0;
2466	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2467	{
2468	/*
2469	* Save the ram range details.
2470	*/
2471	SSMR3PutU32(pSSM, i);
2472	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2473	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2474	SSMR3PutGCPhys(pSSM, pRam->cb);
2475	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2476	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2477
2478	/*
2479	* Iterate the pages, only two special case.
2480	*/
2481	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2482	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2483	{
2484	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2485	PPGMPAGE pPage = &pRam->aPages[iPage];
2486	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2487
2488	if (uType == PGMPAGETYPE_ROM_SHADOW)
2489	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2490	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2491	{
2492	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2493	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2494	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2495	}
2496	else
2497	{
2498	SSMR3PutU8(pSSM, uType);
2499	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2500	}
2501	if (RT_FAILURE(rc))
2502	break;
2503	}
2504	if (RT_FAILURE(rc))
2505	break;
2506	}
2507
2508	pgmUnlock(pVM);
2509	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2510	}
2511
2512
2513	/**
2514	* Load an ignored page.
2515	*
2516	* @returns VBox status code.
2517	* @param pSSM The saved state handle.
2518	*/
2519	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2520	{
2521	uint8_t abPage[PAGE_SIZE];
2522	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2523	}
2524
2525
2526	/**
2527	* Loads a page without any bits in the saved state, i.e. making sure it's
2528	* really zero.
2529	*
2530	* @returns VBox status code.
2531	* @param pVM The VM handle.
2532	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2533	* state).
2534	* @param pPage The guest page tracking structure.
2535	* @param GCPhys The page address.
2536	* @param pRam The ram range (logging).
2537	*/
2538	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2539	{
2540	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2541	&& uType != PGMPAGETYPE_INVALID)
2542	return VERR_SSM_UNEXPECTED_DATA;
2543
2544	/* I think this should be sufficient. */
2545	if (!PGM_PAGE_IS_ZERO(pPage))
2546	return VERR_SSM_UNEXPECTED_DATA;
2547
2548	NOREF(pVM);
2549	NOREF(GCPhys);
2550	NOREF(pRam);
2551	return VINF_SUCCESS;
2552	}
2553
2554
2555	/**
2556	* Loads a page from the saved state.
2557	*
2558	* @returns VBox status code.
2559	* @param pVM The VM handle.
2560	* @param pSSM The SSM handle.
2561	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2562	* state).
2563	* @param pPage The guest page tracking structure.
2564	* @param GCPhys The page address.
2565	* @param pRam The ram range (logging).
2566	*/
2567	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2568	{
2569	int rc;
2570
2571	/*
2572	* Match up the type, dealing with MMIO2 aliases (dropped).
2573	*/
2574	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2575	\|\| uType == PGMPAGETYPE_INVALID,
2576	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2577	VERR_SSM_UNEXPECTED_DATA);
2578
2579	/*
2580	* Load the page.
2581	*/
2582	void *pvPage;
2583	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2584	if (RT_SUCCESS(rc))
2585	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2586
2587	return rc;
2588	}
2589
2590
2591	/**
2592	* Loads a page (counter part to pgmR3SavePage).
2593	*
2594	* @returns VBox status code, fully bitched errors.
2595	* @param pVM The VM handle.
2596	* @param pSSM The SSM handle.
2597	* @param uType The page type.
2598	* @param pPage The page.
2599	* @param GCPhys The page address.
2600	* @param pRam The RAM range (for error messages).
2601	*/
2602	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2603	{
2604	uint8_t uState;
2605	int rc = SSMR3GetU8(pSSM, &uState);
2606	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2607	if (uState == 0 /* zero */)
2608	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2609	else if (uState == 1)
2610	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2611	else
2612	rc = VERR_INTERNAL_ERROR;
2613	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2614	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2615	rc);
2616	return VINF_SUCCESS;
2617	}
2618
2619
2620	/**
2621	* Loads a shadowed ROM page.
2622	*
2623	* @returns VBox status code, errors are fully bitched.
2624	* @param pVM The VM handle.
2625	* @param pSSM The saved state handle.
2626	* @param pPage The page.
2627	* @param GCPhys The page address.
2628	* @param pRam The RAM range (for error messages).
2629	*/
2630	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2631	{
2632	/*
2633	* Load and set the protection first, then load the two pages, the first
2634	* one is the active the other is the passive.
2635	*/
2636	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2637	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2638
2639	uint8_t uProt;
2640	int rc = SSMR3GetU8(pSSM, &uProt);
2641	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2642	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2643	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2644	&& enmProt < PGMROMPROT_END,
2645	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2646	VERR_SSM_UNEXPECTED_DATA);
2647
2648	if (pRomPage->enmProt != enmProt)
2649	{
2650	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2651	AssertLogRelRCReturn(rc, rc);
2652	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2653	}
2654
2655	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2656	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2657	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2658	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2659
2660	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2661	if (RT_SUCCESS(rc))
2662	{
2663	pPageActive = pPage;
2664	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2665	}
2666	return rc;
2667	}
2668
2669
2670	/**
2671	* Worker for pgmR3Load.
2672	*
2673	* @returns VBox status code.
2674	*
2675	* @param pVM The VM handle.
2676	* @param pSSM The SSM handle.
2677	* @param u32Version The saved state version.
2678	*/
2679	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2680	{
2681	PPGM pPGM = &pVM->pgm.s;
2682	int rc;
2683	uint32_t u32Sep;
2684
2685	/*
2686	* Load basic data (required / unaffected by relocation).
2687	*/
2688	if (u32Version >= PGM_SAVED_STATE_VERSION)
2689	{
2690	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2691	AssertLogRelRCReturn(rc, rc);
2692
2693	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2694	{
2695	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2696	AssertLogRelRCReturn(rc, rc);
2697	}
2698	}
2699	else if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2700	{
2701	AssertRelease(pVM->cCPUs == 1);
2702
2703	PGMOLD pgmOld;
2704	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2705	AssertLogRelRCReturn(rc, rc);
2706
2707	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2708	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2709	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2710
2711	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2712	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2713	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2714	}
2715	else
2716	{
2717	AssertRelease(pVM->cCPUs == 1);
2718
2719	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2720	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2721	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2722
2723	uint32_t cbRamSizeIgnored;
2724	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2725	if (RT_FAILURE(rc))
2726	return rc;
2727	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2728
2729	uint32_t u32 = 0;
2730	SSMR3GetUInt(pSSM, &u32);
2731	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2732	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2733	RTUINT uGuestMode;
2734	SSMR3GetUInt(pSSM, &uGuestMode);
2735	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2736
2737	/* check separator. */
2738	SSMR3GetU32(pSSM, &u32Sep);
2739	if (RT_FAILURE(rc))
2740	return rc;
2741	if (u32Sep != (uint32_t)~0)
2742	{
2743	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2744	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2745	}
2746	}
2747
2748	/*
2749	* The guest mappings.
2750	*/
2751	uint32_t i = 0;
2752	for (;; i++)
2753	{
2754	/* Check the seqence number / separator. */
2755	rc = SSMR3GetU32(pSSM, &u32Sep);
2756	if (RT_FAILURE(rc))
2757	return rc;
2758	if (u32Sep == ~0U)
2759	break;
2760	if (u32Sep != i)
2761	{
2762	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2763	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2764	}
2765
2766	/* get the mapping details. */
2767	char szDesc[256];
2768	szDesc[0] = '\0';
2769	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2770	if (RT_FAILURE(rc))
2771	return rc;
2772	RTGCPTR GCPtr;
2773	SSMR3GetGCPtr(pSSM, &GCPtr);
2774	RTGCPTR cPTs;
2775	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2776	if (RT_FAILURE(rc))
2777	return rc;
2778
2779	/* find matching range. */
2780	PPGMMAPPING pMapping;
2781	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2782	if ( pMapping->cPTs == cPTs
2783	&& !strcmp(pMapping->pszDesc, szDesc))
2784	break;
2785	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2786	cPTs, szDesc, GCPtr),
2787	VERR_SSM_LOAD_CONFIG_MISMATCH);
2788
2789	/* relocate it. */
2790	if (pMapping->GCPtr != GCPtr)
2791	{
2792	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2793	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2794	}
2795	else
2796	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2797	}
2798
2799	/*
2800	* Ram range flags and bits.
2801	*/
2802	i = 0;
2803	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2804	{
2805	/* Check the seqence number / separator. */
2806	rc = SSMR3GetU32(pSSM, &u32Sep);
2807	if (RT_FAILURE(rc))
2808	return rc;
2809	if (u32Sep == ~0U)
2810	break;
2811	if (u32Sep != i)
2812	{
2813	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2814	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2815	}
2816	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2817
2818	/* Get the range details. */
2819	RTGCPHYS GCPhys;
2820	SSMR3GetGCPhys(pSSM, &GCPhys);
2821	RTGCPHYS GCPhysLast;
2822	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2823	RTGCPHYS cb;
2824	SSMR3GetGCPhys(pSSM, &cb);
2825	uint8_t fHaveBits;
2826	rc = SSMR3GetU8(pSSM, &fHaveBits);
2827	if (RT_FAILURE(rc))
2828	return rc;
2829	if (fHaveBits & ~1)
2830	{
2831	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2832	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2833	}
2834	size_t cchDesc = 0;
2835	char szDesc[256];
2836	szDesc[0] = '\0';
2837	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2838	{
2839	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2840	if (RT_FAILURE(rc))
2841	return rc;
2842	/* Since we've modified the description strings in r45878, only compare
2843	them if the saved state is more recent. */
2844	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2845	cchDesc = strlen(szDesc);
2846	}
2847
2848	/*
2849	* Match it up with the current range.
2850	*
2851	* Note there is a hack for dealing with the high BIOS mapping
2852	* in the old saved state format, this means we might not have
2853	* a 1:1 match on success.
2854	*/
2855	if ( ( GCPhys != pRam->GCPhys
2856	\|\| GCPhysLast != pRam->GCPhysLast
2857	\|\| cb != pRam->cb
2858	\|\| ( cchDesc
2859	&& strcmp(szDesc, pRam->pszDesc)) )
2860	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2861	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2862	\|\| GCPhys != UINT32_C(0xfff80000)
2863	\|\| GCPhysLast != UINT32_C(0xffffffff)
2864	\|\| pRam->GCPhysLast != GCPhysLast
2865	\|\| pRam->GCPhys < GCPhys
2866	\|\| !fHaveBits)
2867	)
2868	{
2869	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2870	"State : %RGp-%RGp %RGp bytes %s %s\n",
2871	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2872	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2873	/*
2874	* If we're loading a state for debugging purpose, don't make a fuss if
2875	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2876	*/
2877	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2878	\|\| GCPhys < 8 * _1M)
2879	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2880
2881	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2882	continue;
2883	}
2884
2885	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2886	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2887	{
2888	/*
2889	* Load the pages one by one.
2890	*/
2891	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2892	{
2893	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2894	PPGMPAGE pPage = &pRam->aPages[iPage];
2895	uint8_t uType;
2896	rc = SSMR3GetU8(pSSM, &uType);
2897	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2898	if (uType == PGMPAGETYPE_ROM_SHADOW)
2899	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2900	else
2901	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2902	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2903	}
2904	}
2905	else
2906	{
2907	/*
2908	* Old format.
2909	*/
2910	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2911
2912	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2913	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2914	uint32_t fFlags = 0;
2915	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2916	{
2917	uint16_t u16Flags;
2918	rc = SSMR3GetU16(pSSM, &u16Flags);
2919	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2920	fFlags \|= u16Flags;
2921	}
2922
2923	/* Load the bits */
2924	if ( !fHaveBits
2925	&& GCPhysLast < UINT32_C(0xe0000000))
2926	{
2927	/*
2928	* Dynamic chunks.
2929	*/
2930	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2931	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2932	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2933	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2934
2935	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2936	{
2937	uint8_t fPresent;
2938	rc = SSMR3GetU8(pSSM, &fPresent);
2939	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2940	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2941	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2942	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2943
2944	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2945	{
2946	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2947	PPGMPAGE pPage = &pRam->aPages[iPage];
2948	if (fPresent)
2949	{
2950	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2951	rc = pgmR3LoadPageToDevNull(pSSM);
2952	else
2953	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2954	}
2955	else
2956	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2957	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2958	}
2959	}
2960	}
2961	else if (pRam->pvR3)
2962	{
2963	/*
2964	* MMIO2.
2965	*/
2966	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2967	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2968	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2969	AssertLogRelMsgReturn(pRam->pvR3,
2970	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2971	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2972
2973	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2974	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2975	}
2976	else if (GCPhysLast < UINT32_C(0xfff80000))
2977	{
2978	/*
2979	* PCI MMIO, no pages saved.
2980	*/
2981	}
2982	else
2983	{
2984	/*
2985	* Load the 0xfff80000..0xffffffff BIOS range.
2986	* It starts with X reserved pages that we have to skip over since
2987	* the RAMRANGE create by the new code won't include those.
2988	*/
2989	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2990	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2991	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2992	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2993	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2994	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2995	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2996
2997	/* Skip wasted reserved pages before the ROM. */
2998	while (GCPhys < pRam->GCPhys)
2999	{
3000	rc = pgmR3LoadPageToDevNull(pSSM);
3001	GCPhys += PAGE_SIZE;
3002	}
3003
3004	/* Load the bios pages. */
3005	cPages = pRam->cb >> PAGE_SHIFT;
3006	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3007	{
3008	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
3009	PPGMPAGE pPage = &pRam->aPages[iPage];
3010
3011	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
3012	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
3013	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3014	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
3015	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
3016	}
3017	}
3018	}
3019	}
3020
3021	return rc;
3022	}
3023
3024
3025	/**
3026	* Execute state load operation.
3027	*
3028	* @returns VBox status code.
3029	* @param pVM VM Handle.
3030	* @param pSSM SSM operation handle.
3031	* @param u32Version Data layout version.
3032	*/
3033	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
3034	{
3035	int rc;
3036	PPGM pPGM = &pVM->pgm.s;
3037
3038	/*
3039	* Validate version.
3040	*/
3041	if ( u32Version != PGM_SAVED_STATE_VERSION
3042	&& u32Version != PGM_SAVED_STATE_VERSION_2_2_2
3043	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
3044	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3045	{
3046	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
3047	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3048	}
3049
3050	/*
3051	* Call the reset function to make sure all the memory is cleared.
3052	*/
3053	PGMR3Reset(pVM);
3054
3055	/*
3056	* Do the loading while owning the lock because a bunch of the functions
3057	* we're using requires this.
3058	*/
3059	pgmLock(pVM);
3060	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
3061	pgmUnlock(pVM);
3062	if (RT_SUCCESS(rc))
3063	{
3064	/*
3065	* We require a full resync now.
3066	*/
3067	for (unsigned i=0;i<pVM->cCPUs;i++)
3068	{
3069	PVMCPU pVCpu = &pVM->aCpus[i];
3070	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3071	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3072
3073	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3074	}
3075
3076	pgmR3HandlerPhysicalUpdateAll(pVM);
3077
3078	for (unsigned i=0;i<pVM->cCPUs;i++)
3079	{
3080	PVMCPU pVCpu = &pVM->aCpus[i];
3081
3082	/*
3083	* Change the paging mode.
3084	*/
3085	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3086
3087	/* Restore pVM->pgm.s.GCPhysCR3. */
3088	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3089	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3090	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3091	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3092	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3093	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3094	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3095	else
3096	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3097	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3098	}
3099	}
3100
3101	return rc;
3102	}
3103
3104
3105	/**
3106	* Show paging mode.
3107	*
3108	* @param pVM VM Handle.
3109	* @param pHlp The info helpers.
3110	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3111	*/
3112	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3113	{
3114	/* digest argument. */
3115	bool fGuest, fShadow, fHost;
3116	if (pszArgs)
3117	pszArgs = RTStrStripL(pszArgs);
3118	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3119	fShadow = fHost = fGuest = true;
3120	else
3121	{
3122	fShadow = fHost = fGuest = false;
3123	if (strstr(pszArgs, "guest"))
3124	fGuest = true;
3125	if (strstr(pszArgs, "shadow"))
3126	fShadow = true;
3127	if (strstr(pszArgs, "host"))
3128	fHost = true;
3129	}
3130
3131	/** @todo SMP support! */
3132	/* print info. */
3133	if (fGuest)
3134	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3135	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3136	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3137	if (fShadow)
3138	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3139	if (fHost)
3140	{
3141	const char *psz;
3142	switch (pVM->pgm.s.enmHostMode)
3143	{
3144	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3145	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3146	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3147	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3148	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3149	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3150	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3151	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3152	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3153	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3154	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3155	default: psz = "unknown"; break;
3156	}
3157	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3158	}
3159	}
3160
3161
3162	/**
3163	* Dump registered MMIO ranges to the log.
3164	*
3165	* @param pVM VM Handle.
3166	* @param pHlp The info helpers.
3167	* @param pszArgs Arguments, ignored.
3168	*/
3169	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3170	{
3171	NOREF(pszArgs);
3172	pHlp->pfnPrintf(pHlp,
3173	"RAM ranges (pVM=%p)\n"
3174	"%.s %.s\n",
3175	pVM,
3176	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3177	sizeof(RTHCPTR) * 2, "pvHC ");
3178
3179	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3180	pHlp->pfnPrintf(pHlp,
3181	"%RGp-%RGp %RHv %s\n",
3182	pCur->GCPhys,
3183	pCur->GCPhysLast,
3184	pCur->pvR3,
3185	pCur->pszDesc);
3186	}
3187
3188	/**
3189	* Dump the page directory to the log.
3190	*
3191	* @param pVM VM Handle.
3192	* @param pHlp The info helpers.
3193	* @param pszArgs Arguments, ignored.
3194	*/
3195	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3196	{
3197	/** @todo SMP support!! */
3198	PVMCPU pVCpu = &pVM->aCpus[0];
3199
3200	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3201	/* Big pages supported? */
3202	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3203
3204	/* Global pages supported? */
3205	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3206
3207	NOREF(pszArgs);
3208
3209	/*
3210	* Get page directory addresses.
3211	*/
3212	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3213	Assert(pPDSrc);
3214	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3215
3216	/*
3217	* Iterate the page directory.
3218	*/
3219	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3220	{
3221	X86PDE PdeSrc = pPDSrc->a[iPD];
3222	if (PdeSrc.n.u1Present)
3223	{
3224	if (PdeSrc.b.u1Size && fPSE)
3225	pHlp->pfnPrintf(pHlp,
3226	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3227	iPD,
3228	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3229	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3230	else
3231	pHlp->pfnPrintf(pHlp,
3232	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3233	iPD,
3234	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3235	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3236	}
3237	}
3238	}
3239
3240
3241	/**
3242	* Service a VMMCALLRING3_PGM_LOCK call.
3243	*
3244	* @returns VBox status code.
3245	* @param pVM The VM handle.
3246	*/
3247	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3248	{
3249	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3250	AssertRC(rc);
3251	return rc;
3252	}
3253
3254
3255	/**
3256	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3257	*
3258	* @returns PGM_TYPE_*.
3259	* @param pgmMode The mode value to convert.
3260	*/
3261	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3262	{
3263	switch (pgmMode)
3264	{
3265	case PGMMODE_REAL: return PGM_TYPE_REAL;
3266	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3267	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3268	case PGMMODE_PAE:
3269	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3270	case PGMMODE_AMD64:
3271	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3272	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3273	case PGMMODE_EPT: return PGM_TYPE_EPT;
3274	default:
3275	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3276	}
3277	}
3278
3279
3280	/**
3281	* Gets the index into the paging mode data array of a SHW+GST mode.
3282	*
3283	* @returns PGM::paPagingData index.
3284	* @param uShwType The shadow paging mode type.
3285	* @param uGstType The guest paging mode type.
3286	*/
3287	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3288	{
3289	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3290	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3291	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3292	+ (uGstType - PGM_TYPE_REAL);
3293	}
3294
3295
3296	/**
3297	* Gets the index into the paging mode data array of a SHW+GST mode.
3298	*
3299	* @returns PGM::paPagingData index.
3300	* @param enmShw The shadow paging mode.
3301	* @param enmGst The guest paging mode.
3302	*/
3303	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3304	{
3305	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3306	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3307	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3308	}
3309
3310
3311	/**
3312	* Calculates the max data index.
3313	* @returns The number of entries in the paging data array.
3314	*/
3315	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3316	{
3317	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3318	}
3319
3320
3321	/**
3322	* Initializes the paging mode data kept in PGM::paModeData.
3323	*
3324	* @param pVM The VM handle.
3325	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3326	* This is used early in the init process to avoid trouble with PDM
3327	* not being initialized yet.
3328	*/
3329	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3330	{
3331	PPGMMODEDATA pModeData;
3332	int rc;
3333
3334	/*
3335	* Allocate the array on the first call.
3336	*/
3337	if (!pVM->pgm.s.paModeData)
3338	{
3339	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3340	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3341	}
3342
3343	/*
3344	* Initialize the array entries.
3345	*/
3346	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3347	pModeData->uShwType = PGM_TYPE_32BIT;
3348	pModeData->uGstType = PGM_TYPE_REAL;
3349	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3350	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3351	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3352
3353	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3354	pModeData->uShwType = PGM_TYPE_32BIT;
3355	pModeData->uGstType = PGM_TYPE_PROT;
3356	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3357	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3358	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3359
3360	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3361	pModeData->uShwType = PGM_TYPE_32BIT;
3362	pModeData->uGstType = PGM_TYPE_32BIT;
3363	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3364	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3365	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3366
3367	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3368	pModeData->uShwType = PGM_TYPE_PAE;
3369	pModeData->uGstType = PGM_TYPE_REAL;
3370	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3371	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3372	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3373
3374	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3375	pModeData->uShwType = PGM_TYPE_PAE;
3376	pModeData->uGstType = PGM_TYPE_PROT;
3377	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3378	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3379	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3380
3381	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3382	pModeData->uShwType = PGM_TYPE_PAE;
3383	pModeData->uGstType = PGM_TYPE_32BIT;
3384	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3385	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3386	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3387
3388	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3389	pModeData->uShwType = PGM_TYPE_PAE;
3390	pModeData->uGstType = PGM_TYPE_PAE;
3391	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3392	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3393	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3394
3395	#ifdef VBOX_WITH_64_BITS_GUESTS
3396	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3397	pModeData->uShwType = PGM_TYPE_AMD64;
3398	pModeData->uGstType = PGM_TYPE_AMD64;
3399	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3400	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3401	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3402	#endif
3403
3404	/* The nested paging mode. */
3405	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3406	pModeData->uShwType = PGM_TYPE_NESTED;
3407	pModeData->uGstType = PGM_TYPE_REAL;
3408	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3409	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3410
3411	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3412	pModeData->uShwType = PGM_TYPE_NESTED;
3413	pModeData->uGstType = PGM_TYPE_PROT;
3414	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3415	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3416
3417	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3418	pModeData->uShwType = PGM_TYPE_NESTED;
3419	pModeData->uGstType = PGM_TYPE_32BIT;
3420	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3421	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3422
3423	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3424	pModeData->uShwType = PGM_TYPE_NESTED;
3425	pModeData->uGstType = PGM_TYPE_PAE;
3426	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3427	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3428
3429	#ifdef VBOX_WITH_64_BITS_GUESTS
3430	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3431	pModeData->uShwType = PGM_TYPE_NESTED;
3432	pModeData->uGstType = PGM_TYPE_AMD64;
3433	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3434	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3435	#endif
3436
3437	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3438	switch (pVM->pgm.s.enmHostMode)
3439	{
3440	#if HC_ARCH_BITS == 32
3441	case SUPPAGINGMODE_32_BIT:
3442	case SUPPAGINGMODE_32_BIT_GLOBAL:
3443	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3444	{
3445	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3446	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3447	}
3448	# ifdef VBOX_WITH_64_BITS_GUESTS
3449	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3450	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3451	# endif
3452	break;
3453
3454	case SUPPAGINGMODE_PAE:
3455	case SUPPAGINGMODE_PAE_NX:
3456	case SUPPAGINGMODE_PAE_GLOBAL:
3457	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3458	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3459	{
3460	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3461	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3462	}
3463	# ifdef VBOX_WITH_64_BITS_GUESTS
3464	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3465	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3466	# endif
3467	break;
3468	#endif /* HC_ARCH_BITS == 32 */
3469
3470	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3471	case SUPPAGINGMODE_AMD64:
3472	case SUPPAGINGMODE_AMD64_GLOBAL:
3473	case SUPPAGINGMODE_AMD64_NX:
3474	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3475	# ifdef VBOX_WITH_64_BITS_GUESTS
3476	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3477	# else
3478	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3479	# endif
3480	{
3481	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3482	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3483	}
3484	break;
3485	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3486
3487	default:
3488	AssertFailed();
3489	break;
3490	}
3491
3492	/* Extended paging (EPT) / Intel VT-x */
3493	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3494	pModeData->uShwType = PGM_TYPE_EPT;
3495	pModeData->uGstType = PGM_TYPE_REAL;
3496	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3497	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3498	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3499
3500	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3501	pModeData->uShwType = PGM_TYPE_EPT;
3502	pModeData->uGstType = PGM_TYPE_PROT;
3503	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3504	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3505	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3506
3507	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3508	pModeData->uShwType = PGM_TYPE_EPT;
3509	pModeData->uGstType = PGM_TYPE_32BIT;
3510	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3511	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3512	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3513
3514	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3515	pModeData->uShwType = PGM_TYPE_EPT;
3516	pModeData->uGstType = PGM_TYPE_PAE;
3517	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3518	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3519	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3520
3521	#ifdef VBOX_WITH_64_BITS_GUESTS
3522	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3523	pModeData->uShwType = PGM_TYPE_EPT;
3524	pModeData->uGstType = PGM_TYPE_AMD64;
3525	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3526	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3527	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3528	#endif
3529	return VINF_SUCCESS;
3530	}
3531
3532
3533	/**
3534	* Switch to different (or relocated in the relocate case) mode data.
3535	*
3536	* @param pVM The VM handle.
3537	* @param pVCpu The VMCPU to operate on.
3538	* @param enmShw The the shadow paging mode.
3539	* @param enmGst The the guest paging mode.
3540	*/
3541	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3542	{
3543	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3544
3545	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3546	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3547
3548	/* shadow */
3549	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3550	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3551	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3552	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3553	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3554
3555	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3556	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3557
3558	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3559	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3560
3561
3562	/* guest */
3563	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3564	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3565	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3566	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3567	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3568	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3569	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3570	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3571	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3572	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3573	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3574	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3575
3576	/* both */
3577	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3578	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3579	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3580	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3581	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3582	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3583	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3584	#ifdef VBOX_STRICT
3585	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3586	#endif
3587	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3588	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3589
3590	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3591	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3592	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3593	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3594	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3595	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3596	#ifdef VBOX_STRICT
3597	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3598	#endif
3599	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3600	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3601
3602	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3603	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3604	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3605	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3606	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3607	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3608	#ifdef VBOX_STRICT
3609	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3610	#endif
3611	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3612	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3613	}
3614
3615
3616	/**
3617	* Calculates the shadow paging mode.
3618	*
3619	* @returns The shadow paging mode.
3620	* @param pVM VM handle.
3621	* @param enmGuestMode The guest mode.
3622	* @param enmHostMode The host mode.
3623	* @param enmShadowMode The current shadow mode.
3624	* @param penmSwitcher Where to store the switcher to use.
3625	* VMMSWITCHER_INVALID means no change.
3626	*/
3627	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3628	{
3629	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3630	switch (enmGuestMode)
3631	{
3632	/*
3633	* When switching to real or protected mode we don't change
3634	* anything since it's likely that we'll switch back pretty soon.
3635	*
3636	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3637	* and is supposed to determine which shadow paging and switcher to
3638	* use during init.
3639	*/
3640	case PGMMODE_REAL:
3641	case PGMMODE_PROTECTED:
3642	if ( enmShadowMode != PGMMODE_INVALID
3643	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3644	break; /* (no change) */
3645
3646	switch (enmHostMode)
3647	{
3648	case SUPPAGINGMODE_32_BIT:
3649	case SUPPAGINGMODE_32_BIT_GLOBAL:
3650	enmShadowMode = PGMMODE_32_BIT;
3651	enmSwitcher = VMMSWITCHER_32_TO_32;
3652	break;
3653
3654	case SUPPAGINGMODE_PAE:
3655	case SUPPAGINGMODE_PAE_NX:
3656	case SUPPAGINGMODE_PAE_GLOBAL:
3657	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3658	enmShadowMode = PGMMODE_PAE;
3659	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3660	#ifdef DEBUG_bird
3661	if (RTEnvExist("VBOX_32BIT"))
3662	{
3663	enmShadowMode = PGMMODE_32_BIT;
3664	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3665	}
3666	#endif
3667	break;
3668
3669	case SUPPAGINGMODE_AMD64:
3670	case SUPPAGINGMODE_AMD64_GLOBAL:
3671	case SUPPAGINGMODE_AMD64_NX:
3672	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3673	enmShadowMode = PGMMODE_PAE;
3674	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3675	#ifdef DEBUG_bird
3676	if (RTEnvExist("VBOX_32BIT"))
3677	{
3678	enmShadowMode = PGMMODE_32_BIT;
3679	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3680	}
3681	#endif
3682	break;
3683
3684	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3685	}
3686	break;
3687
3688	case PGMMODE_32_BIT:
3689	switch (enmHostMode)
3690	{
3691	case SUPPAGINGMODE_32_BIT:
3692	case SUPPAGINGMODE_32_BIT_GLOBAL:
3693	enmShadowMode = PGMMODE_32_BIT;
3694	enmSwitcher = VMMSWITCHER_32_TO_32;
3695	break;
3696
3697	case SUPPAGINGMODE_PAE:
3698	case SUPPAGINGMODE_PAE_NX:
3699	case SUPPAGINGMODE_PAE_GLOBAL:
3700	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3701	enmShadowMode = PGMMODE_PAE;
3702	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3703	#ifdef DEBUG_bird
3704	if (RTEnvExist("VBOX_32BIT"))
3705	{
3706	enmShadowMode = PGMMODE_32_BIT;
3707	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3708	}
3709	#endif
3710	break;
3711
3712	case SUPPAGINGMODE_AMD64:
3713	case SUPPAGINGMODE_AMD64_GLOBAL:
3714	case SUPPAGINGMODE_AMD64_NX:
3715	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3716	enmShadowMode = PGMMODE_PAE;
3717	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3718	#ifdef DEBUG_bird
3719	if (RTEnvExist("VBOX_32BIT"))
3720	{
3721	enmShadowMode = PGMMODE_32_BIT;
3722	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3723	}
3724	#endif
3725	break;
3726
3727	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3728	}
3729	break;
3730
3731	case PGMMODE_PAE:
3732	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3733	switch (enmHostMode)
3734	{
3735	case SUPPAGINGMODE_32_BIT:
3736	case SUPPAGINGMODE_32_BIT_GLOBAL:
3737	enmShadowMode = PGMMODE_PAE;
3738	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3739	break;
3740
3741	case SUPPAGINGMODE_PAE:
3742	case SUPPAGINGMODE_PAE_NX:
3743	case SUPPAGINGMODE_PAE_GLOBAL:
3744	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3745	enmShadowMode = PGMMODE_PAE;
3746	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3747	break;
3748
3749	case SUPPAGINGMODE_AMD64:
3750	case SUPPAGINGMODE_AMD64_GLOBAL:
3751	case SUPPAGINGMODE_AMD64_NX:
3752	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3753	enmShadowMode = PGMMODE_PAE;
3754	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3755	break;
3756
3757	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3758	}
3759	break;
3760
3761	case PGMMODE_AMD64:
3762	case PGMMODE_AMD64_NX:
3763	switch (enmHostMode)
3764	{
3765	case SUPPAGINGMODE_32_BIT:
3766	case SUPPAGINGMODE_32_BIT_GLOBAL:
3767	enmShadowMode = PGMMODE_AMD64;
3768	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3769	break;
3770
3771	case SUPPAGINGMODE_PAE:
3772	case SUPPAGINGMODE_PAE_NX:
3773	case SUPPAGINGMODE_PAE_GLOBAL:
3774	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3775	enmShadowMode = PGMMODE_AMD64;
3776	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3777	break;
3778
3779	case SUPPAGINGMODE_AMD64:
3780	case SUPPAGINGMODE_AMD64_GLOBAL:
3781	case SUPPAGINGMODE_AMD64_NX:
3782	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3783	enmShadowMode = PGMMODE_AMD64;
3784	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3785	break;
3786
3787	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3788	}
3789	break;
3790
3791
3792	default:
3793	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3794	return PGMMODE_INVALID;
3795	}
3796	/* Override the shadow mode is nested paging is active. */
3797	if (HWACCMIsNestedPagingActive(pVM))
3798	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3799
3800	*penmSwitcher = enmSwitcher;
3801	return enmShadowMode;
3802	}
3803
3804
3805	/**
3806	* Performs the actual mode change.
3807	* This is called by PGMChangeMode and pgmR3InitPaging().
3808	*
3809	* @returns VBox status code. May suspend or power off the VM on error, but this
3810	* will trigger using FFs and not status codes.
3811	*
3812	* @param pVM VM handle.
3813	* @param pVCpu The VMCPU to operate on.
3814	* @param enmGuestMode The new guest mode. This is assumed to be different from
3815	* the current mode.
3816	*/
3817	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3818	{
3819	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3820	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3821
3822	/*
3823	* Calc the shadow mode and switcher.
3824	*/
3825	VMMSWITCHER enmSwitcher;
3826	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3827	if (enmSwitcher != VMMSWITCHER_INVALID)
3828	{
3829	/*
3830	* Select new switcher.
3831	*/
3832	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3833	if (RT_FAILURE(rc))
3834	{
3835	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3836	return rc;
3837	}
3838	}
3839
3840	/*
3841	* Exit old mode(s).
3842	*/
3843	/* shadow */
3844	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3845	{
3846	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3847	if (PGM_SHW_PFN(Exit, pVCpu))
3848	{
3849	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3850	if (RT_FAILURE(rc))
3851	{
3852	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3853	return rc;
3854	}
3855	}
3856
3857	}
3858	else
3859	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3860
3861	/* guest */
3862	if (PGM_GST_PFN(Exit, pVCpu))
3863	{
3864	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3865	if (RT_FAILURE(rc))
3866	{
3867	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3868	return rc;
3869	}
3870	}
3871
3872	/*
3873	* Load new paging mode data.
3874	*/
3875	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3876
3877	/*
3878	* Enter new shadow mode (if changed).
3879	*/
3880	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3881	{
3882	int rc;
3883	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3884	switch (enmShadowMode)
3885	{
3886	case PGMMODE_32_BIT:
3887	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3888	break;
3889	case PGMMODE_PAE:
3890	case PGMMODE_PAE_NX:
3891	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3892	break;
3893	case PGMMODE_AMD64:
3894	case PGMMODE_AMD64_NX:
3895	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3896	break;
3897	case PGMMODE_NESTED:
3898	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3899	break;
3900	case PGMMODE_EPT:
3901	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3902	break;
3903	case PGMMODE_REAL:
3904	case PGMMODE_PROTECTED:
3905	default:
3906	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3907	return VERR_INTERNAL_ERROR;
3908	}
3909	if (RT_FAILURE(rc))
3910	{
3911	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3912	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3913	return rc;
3914	}
3915	}
3916
3917	/*
3918	* Always flag the necessary updates
3919	*/
3920	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3921
3922	/*
3923	* Enter the new guest and shadow+guest modes.
3924	*/
3925	int rc = -1;
3926	int rc2 = -1;
3927	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3928	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3929	switch (enmGuestMode)
3930	{
3931	case PGMMODE_REAL:
3932	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3933	switch (pVCpu->pgm.s.enmShadowMode)
3934	{
3935	case PGMMODE_32_BIT:
3936	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3937	break;
3938	case PGMMODE_PAE:
3939	case PGMMODE_PAE_NX:
3940	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3941	break;
3942	case PGMMODE_NESTED:
3943	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3944	break;
3945	case PGMMODE_EPT:
3946	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3947	break;
3948	case PGMMODE_AMD64:
3949	case PGMMODE_AMD64_NX:
3950	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3951	default: AssertFailed(); break;
3952	}
3953	break;
3954
3955	case PGMMODE_PROTECTED:
3956	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3957	switch (pVCpu->pgm.s.enmShadowMode)
3958	{
3959	case PGMMODE_32_BIT:
3960	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3961	break;
3962	case PGMMODE_PAE:
3963	case PGMMODE_PAE_NX:
3964	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3965	break;
3966	case PGMMODE_NESTED:
3967	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3968	break;
3969	case PGMMODE_EPT:
3970	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3971	break;
3972	case PGMMODE_AMD64:
3973	case PGMMODE_AMD64_NX:
3974	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3975	default: AssertFailed(); break;
3976	}
3977	break;
3978
3979	case PGMMODE_32_BIT:
3980	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3981	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3982	switch (pVCpu->pgm.s.enmShadowMode)
3983	{
3984	case PGMMODE_32_BIT:
3985	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3986	break;
3987	case PGMMODE_PAE:
3988	case PGMMODE_PAE_NX:
3989	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3990	break;
3991	case PGMMODE_NESTED:
3992	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3993	break;
3994	case PGMMODE_EPT:
3995	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3996	break;
3997	case PGMMODE_AMD64:
3998	case PGMMODE_AMD64_NX:
3999	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4000	default: AssertFailed(); break;
4001	}
4002	break;
4003
4004	case PGMMODE_PAE_NX:
4005	case PGMMODE_PAE:
4006	{
4007	uint32_t u32Dummy, u32Features;
4008
4009	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
4010	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
4011	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
4012	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
4013
4014	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
4015	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
4016	switch (pVCpu->pgm.s.enmShadowMode)
4017	{
4018	case PGMMODE_PAE:
4019	case PGMMODE_PAE_NX:
4020	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4021	break;
4022	case PGMMODE_NESTED:
4023	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4024	break;
4025	case PGMMODE_EPT:
4026	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4027	break;
4028	case PGMMODE_32_BIT:
4029	case PGMMODE_AMD64:
4030	case PGMMODE_AMD64_NX:
4031	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4032	default: AssertFailed(); break;
4033	}
4034	break;
4035	}
4036
4037	#ifdef VBOX_WITH_64_BITS_GUESTS
4038	case PGMMODE_AMD64_NX:
4039	case PGMMODE_AMD64:
4040	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4041	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4042	switch (pVCpu->pgm.s.enmShadowMode)
4043	{
4044	case PGMMODE_AMD64:
4045	case PGMMODE_AMD64_NX:
4046	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4047	break;
4048	case PGMMODE_NESTED:
4049	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4050	break;
4051	case PGMMODE_EPT:
4052	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4053	break;
4054	case PGMMODE_32_BIT:
4055	case PGMMODE_PAE:
4056	case PGMMODE_PAE_NX:
4057	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4058	default: AssertFailed(); break;
4059	}
4060	break;
4061	#endif
4062
4063	default:
4064	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4065	rc = VERR_NOT_IMPLEMENTED;
4066	break;
4067	}
4068
4069	/* status codes. */
4070	AssertRC(rc);
4071	AssertRC(rc2);
4072	if (RT_SUCCESS(rc))
4073	{
4074	rc = rc2;
4075	if (RT_SUCCESS(rc)) /* no informational status codes. */
4076	rc = VINF_SUCCESS;
4077	}
4078
4079	/* Notify HWACCM as well. */
4080	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4081	return rc;
4082	}
4083
4084	/**
4085	* Release the pgm lock if owned by the current VCPU
4086	*
4087	* @param pVM The VM to operate on.
4088	*/
4089	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4090	{
4091	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4092	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4093	}
4094
4095	/**
4096	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4097	*
4098	* @returns VBox status code, fully asserted.
4099	* @param pVM The VM handle.
4100	* @param pVCpu The VMCPU to operate on.
4101	*/
4102	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4103	{
4104	/* Unmap the old CR3 value before flushing everything. */
4105	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4106	AssertRC(rc);
4107
4108	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4109	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4110	AssertRC(rc);
4111	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4112	return rc;
4113	}
4114
4115
4116	/**
4117	* Called by pgmPoolFlushAllInt after flushing the pool.
4118	*
4119	* @returns VBox status code, fully asserted.
4120	* @param pVM The VM handle.
4121	* @param pVCpu The VMCPU to operate on.
4122	*/
4123	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4124	{
4125	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4126	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4127	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4128	AssertRCReturn(rc, rc);
4129	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4130
4131	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4132	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4133	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4134	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4135	return rc;
4136	}
4137
4138
4139	/**
4140	* Dumps a PAE shadow page table.
4141	*
4142	* @returns VBox status code (VINF_SUCCESS).
4143	* @param pVM The VM handle.
4144	* @param pPT Pointer to the page table.
4145	* @param u64Address The virtual address of the page table starts.
4146	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4147	* @param cMaxDepth The maxium depth.
4148	* @param pHlp Pointer to the output functions.
4149	*/
4150	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4151	{
4152	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4153	{
4154	X86PTEPAE Pte = pPT->a[i];
4155	if (Pte.n.u1Present)
4156	{
4157	pHlp->pfnPrintf(pHlp,
4158	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4159	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4160	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4161	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4162	Pte.n.u1Write ? 'W' : 'R',
4163	Pte.n.u1User ? 'U' : 'S',
4164	Pte.n.u1Accessed ? 'A' : '-',
4165	Pte.n.u1Dirty ? 'D' : '-',
4166	Pte.n.u1Global ? 'G' : '-',
4167	Pte.n.u1WriteThru ? "WT" : "--",
4168	Pte.n.u1CacheDisable? "CD" : "--",
4169	Pte.n.u1PAT ? "AT" : "--",
4170	Pte.n.u1NoExecute ? "NX" : "--",
4171	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4172	Pte.u & RT_BIT(10) ? '1' : '0',
4173	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4174	Pte.u & X86_PTE_PAE_PG_MASK);
4175	}
4176	}
4177	return VINF_SUCCESS;
4178	}
4179
4180
4181	/**
4182	* Dumps a PAE shadow page directory table.
4183	*
4184	* @returns VBox status code (VINF_SUCCESS).
4185	* @param pVM The VM handle.
4186	* @param HCPhys The physical address of the page directory table.
4187	* @param u64Address The virtual address of the page table starts.
4188	* @param cr4 The CR4, PSE is currently used.
4189	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4190	* @param cMaxDepth The maxium depth.
4191	* @param pHlp Pointer to the output functions.
4192	*/
4193	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4194	{
4195	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4196	if (!pPD)
4197	{
4198	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4199	fLongMode ? 16 : 8, u64Address, HCPhys);
4200	return VERR_INVALID_PARAMETER;
4201	}
4202	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4203
4204	int rc = VINF_SUCCESS;
4205	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4206	{
4207	X86PDEPAE Pde = pPD->a[i];
4208	if (Pde.n.u1Present)
4209	{
4210	if (fBigPagesSupported && Pde.b.u1Size)
4211	pHlp->pfnPrintf(pHlp,
4212	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4213	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4214	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4215	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4216	Pde.b.u1Write ? 'W' : 'R',
4217	Pde.b.u1User ? 'U' : 'S',
4218	Pde.b.u1Accessed ? 'A' : '-',
4219	Pde.b.u1Dirty ? 'D' : '-',
4220	Pde.b.u1Global ? 'G' : '-',
4221	Pde.b.u1WriteThru ? "WT" : "--",
4222	Pde.b.u1CacheDisable? "CD" : "--",
4223	Pde.b.u1PAT ? "AT" : "--",
4224	Pde.b.u1NoExecute ? "NX" : "--",
4225	Pde.u & RT_BIT_64(9) ? '1' : '0',
4226	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4227	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4228	Pde.u & X86_PDE_PAE_PG_MASK);
4229	else
4230	{
4231	pHlp->pfnPrintf(pHlp,
4232	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4233	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4234	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4235	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4236	Pde.n.u1Write ? 'W' : 'R',
4237	Pde.n.u1User ? 'U' : 'S',
4238	Pde.n.u1Accessed ? 'A' : '-',
4239	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4240	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4241	Pde.n.u1WriteThru ? "WT" : "--",
4242	Pde.n.u1CacheDisable? "CD" : "--",
4243	Pde.n.u1NoExecute ? "NX" : "--",
4244	Pde.u & RT_BIT_64(9) ? '1' : '0',
4245	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4246	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4247	Pde.u & X86_PDE_PAE_PG_MASK);
4248	if (cMaxDepth >= 1)
4249	{
4250	/** @todo what about using the page pool for mapping PTs? */
4251	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4252	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4253	PX86PTPAE pPT = NULL;
4254	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4255	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4256	else
4257	{
4258	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4259	{
4260	uint64_t off = u64AddressPT - pMap->GCPtr;
4261	if (off < pMap->cb)
4262	{
4263	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4264	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4265	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4266	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4267	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4268	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4269	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4270	}
4271	}
4272	}
4273	int rc2 = VERR_INVALID_PARAMETER;
4274	if (pPT)
4275	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4276	else
4277	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4278	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4279	if (rc2 < rc && RT_SUCCESS(rc))
4280	rc = rc2;
4281	}
4282	}
4283	}
4284	}
4285	return rc;
4286	}
4287
4288
4289	/**
4290	* Dumps a PAE shadow page directory pointer table.
4291	*
4292	* @returns VBox status code (VINF_SUCCESS).
4293	* @param pVM The VM handle.
4294	* @param HCPhys The physical address of the page directory pointer table.
4295	* @param u64Address The virtual address of the page table starts.
4296	* @param cr4 The CR4, PSE is currently used.
4297	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4298	* @param cMaxDepth The maxium depth.
4299	* @param pHlp Pointer to the output functions.
4300	*/
4301	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4302	{
4303	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4304	if (!pPDPT)
4305	{
4306	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4307	fLongMode ? 16 : 8, u64Address, HCPhys);
4308	return VERR_INVALID_PARAMETER;
4309	}
4310
4311	int rc = VINF_SUCCESS;
4312	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4313	for (unsigned i = 0; i < c; i++)
4314	{
4315	X86PDPE Pdpe = pPDPT->a[i];
4316	if (Pdpe.n.u1Present)
4317	{
4318	if (fLongMode)
4319	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4320	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4321	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4322	Pdpe.lm.u1Write ? 'W' : 'R',
4323	Pdpe.lm.u1User ? 'U' : 'S',
4324	Pdpe.lm.u1Accessed ? 'A' : '-',
4325	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4326	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4327	Pdpe.lm.u1WriteThru ? "WT" : "--",
4328	Pdpe.lm.u1CacheDisable? "CD" : "--",
4329	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4330	Pdpe.lm.u1NoExecute ? "NX" : "--",
4331	Pdpe.u & RT_BIT(9) ? '1' : '0',
4332	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4333	Pdpe.u & RT_BIT(11) ? '1' : '0',
4334	Pdpe.u & X86_PDPE_PG_MASK);
4335	else
4336	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4337	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4338	i << X86_PDPT_SHIFT,
4339	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4340	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4341	Pdpe.n.u1WriteThru ? "WT" : "--",
4342	Pdpe.n.u1CacheDisable? "CD" : "--",
4343	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4344	Pdpe.u & RT_BIT(9) ? '1' : '0',
4345	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4346	Pdpe.u & RT_BIT(11) ? '1' : '0',
4347	Pdpe.u & X86_PDPE_PG_MASK);
4348	if (cMaxDepth >= 1)
4349	{
4350	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4351	cr4, fLongMode, cMaxDepth - 1, pHlp);
4352	if (rc2 < rc && RT_SUCCESS(rc))
4353	rc = rc2;
4354	}
4355	}
4356	}
4357	return rc;
4358	}
4359
4360
4361	/**
4362	* Dumps a 32-bit shadow page table.
4363	*
4364	* @returns VBox status code (VINF_SUCCESS).
4365	* @param pVM The VM handle.
4366	* @param HCPhys The physical address of the table.
4367	* @param cr4 The CR4, PSE is currently used.
4368	* @param cMaxDepth The maxium depth.
4369	* @param pHlp Pointer to the output functions.
4370	*/
4371	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4372	{
4373	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4374	if (!pPML4)
4375	{
4376	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4377	return VERR_INVALID_PARAMETER;
4378	}
4379
4380	int rc = VINF_SUCCESS;
4381	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4382	{
4383	X86PML4E Pml4e = pPML4->a[i];
4384	if (Pml4e.n.u1Present)
4385	{
4386	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4387	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4388	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4389	u64Address,
4390	Pml4e.n.u1Write ? 'W' : 'R',
4391	Pml4e.n.u1User ? 'U' : 'S',
4392	Pml4e.n.u1Accessed ? 'A' : '-',
4393	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4394	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4395	Pml4e.n.u1WriteThru ? "WT" : "--",
4396	Pml4e.n.u1CacheDisable? "CD" : "--",
4397	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4398	Pml4e.n.u1NoExecute ? "NX" : "--",
4399	Pml4e.u & RT_BIT(9) ? '1' : '0',
4400	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4401	Pml4e.u & RT_BIT(11) ? '1' : '0',
4402	Pml4e.u & X86_PML4E_PG_MASK);
4403
4404	if (cMaxDepth >= 1)
4405	{
4406	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4407	if (rc2 < rc && RT_SUCCESS(rc))
4408	rc = rc2;
4409	}
4410	}
4411	}
4412	return rc;
4413	}
4414
4415
4416	/**
4417	* Dumps a 32-bit shadow page table.
4418	*
4419	* @returns VBox status code (VINF_SUCCESS).
4420	* @param pVM The VM handle.
4421	* @param pPT Pointer to the page table.
4422	* @param u32Address The virtual address this table starts at.
4423	* @param pHlp Pointer to the output functions.
4424	*/
4425	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4426	{
4427	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4428	{
4429	X86PTE Pte = pPT->a[i];
4430	if (Pte.n.u1Present)
4431	{
4432	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4433	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4434	u32Address + (i << X86_PT_SHIFT),
4435	Pte.n.u1Write ? 'W' : 'R',
4436	Pte.n.u1User ? 'U' : 'S',
4437	Pte.n.u1Accessed ? 'A' : '-',
4438	Pte.n.u1Dirty ? 'D' : '-',
4439	Pte.n.u1Global ? 'G' : '-',
4440	Pte.n.u1WriteThru ? "WT" : "--",
4441	Pte.n.u1CacheDisable? "CD" : "--",
4442	Pte.n.u1PAT ? "AT" : "--",
4443	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4444	Pte.u & RT_BIT(10) ? '1' : '0',
4445	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4446	Pte.u & X86_PDE_PG_MASK);
4447	}
4448	}
4449	return VINF_SUCCESS;
4450	}
4451
4452
4453	/**
4454	* Dumps a 32-bit shadow page directory and page tables.
4455	*
4456	* @returns VBox status code (VINF_SUCCESS).
4457	* @param pVM The VM handle.
4458	* @param cr3 The root of the hierarchy.
4459	* @param cr4 The CR4, PSE is currently used.
4460	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4461	* @param pHlp Pointer to the output functions.
4462	*/
4463	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4464	{
4465	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4466	if (!pPD)
4467	{
4468	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4469	return VERR_INVALID_PARAMETER;
4470	}
4471
4472	int rc = VINF_SUCCESS;
4473	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4474	{
4475	X86PDE Pde = pPD->a[i];
4476	if (Pde.n.u1Present)
4477	{
4478	const uint32_t u32Address = i << X86_PD_SHIFT;
4479	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4480	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4481	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4482	u32Address,
4483	Pde.b.u1Write ? 'W' : 'R',
4484	Pde.b.u1User ? 'U' : 'S',
4485	Pde.b.u1Accessed ? 'A' : '-',
4486	Pde.b.u1Dirty ? 'D' : '-',
4487	Pde.b.u1Global ? 'G' : '-',
4488	Pde.b.u1WriteThru ? "WT" : "--",
4489	Pde.b.u1CacheDisable? "CD" : "--",
4490	Pde.b.u1PAT ? "AT" : "--",
4491	Pde.u & RT_BIT_64(9) ? '1' : '0',
4492	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4493	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4494	Pde.u & X86_PDE4M_PG_MASK);
4495	else
4496	{
4497	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4498	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4499	u32Address,
4500	Pde.n.u1Write ? 'W' : 'R',
4501	Pde.n.u1User ? 'U' : 'S',
4502	Pde.n.u1Accessed ? 'A' : '-',
4503	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4504	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4505	Pde.n.u1WriteThru ? "WT" : "--",
4506	Pde.n.u1CacheDisable? "CD" : "--",
4507	Pde.u & RT_BIT_64(9) ? '1' : '0',
4508	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4509	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4510	Pde.u & X86_PDE_PG_MASK);
4511	if (cMaxDepth >= 1)
4512	{
4513	/** @todo what about using the page pool for mapping PTs? */
4514	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4515	PX86PT pPT = NULL;
4516	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4517	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4518	else
4519	{
4520	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4521	if (u32Address - pMap->GCPtr < pMap->cb)
4522	{
4523	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4524	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4525	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4526	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4527	pPT = pMap->aPTs[iPDE].pPTR3;
4528	}
4529	}
4530	int rc2 = VERR_INVALID_PARAMETER;
4531	if (pPT)
4532	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4533	else
4534	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4535	if (rc2 < rc && RT_SUCCESS(rc))
4536	rc = rc2;
4537	}
4538	}
4539	}
4540	}
4541
4542	return rc;
4543	}
4544
4545
4546	/**
4547	* Dumps a 32-bit shadow page table.
4548	*
4549	* @returns VBox status code (VINF_SUCCESS).
4550	* @param pVM The VM handle.
4551	* @param pPT Pointer to the page table.
4552	* @param u32Address The virtual address this table starts at.
4553	* @param PhysSearch Address to search for.
4554	*/
4555	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4556	{
4557	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4558	{
4559	X86PTE Pte = pPT->a[i];
4560	if (Pte.n.u1Present)
4561	{
4562	Log(( /P R S A D G WT CD AT NX 4M a m d /
4563	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4564	u32Address + (i << X86_PT_SHIFT),
4565	Pte.n.u1Write ? 'W' : 'R',
4566	Pte.n.u1User ? 'U' : 'S',
4567	Pte.n.u1Accessed ? 'A' : '-',
4568	Pte.n.u1Dirty ? 'D' : '-',
4569	Pte.n.u1Global ? 'G' : '-',
4570	Pte.n.u1WriteThru ? "WT" : "--",
4571	Pte.n.u1CacheDisable? "CD" : "--",
4572	Pte.n.u1PAT ? "AT" : "--",
4573	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4574	Pte.u & RT_BIT(10) ? '1' : '0',
4575	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4576	Pte.u & X86_PDE_PG_MASK));
4577
4578	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4579	{
4580	uint64_t fPageShw = 0;
4581	RTHCPHYS pPhysHC = 0;
4582
4583	/** @todo SMP support!! */
4584	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4585	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4586	}
4587	}
4588	}
4589	return VINF_SUCCESS;
4590	}
4591
4592
4593	/**
4594	* Dumps a 32-bit guest page directory and page tables.
4595	*
4596	* @returns VBox status code (VINF_SUCCESS).
4597	* @param pVM The VM handle.
4598	* @param cr3 The root of the hierarchy.
4599	* @param cr4 The CR4, PSE is currently used.
4600	* @param PhysSearch Address to search for.
4601	*/
4602	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4603	{
4604	bool fLongMode = false;
4605	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4606	PX86PD pPD = 0;
4607
4608	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4609	if (RT_FAILURE(rc) \|\| !pPD)
4610	{
4611	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4612	return VERR_INVALID_PARAMETER;
4613	}
4614
4615	Log(("cr3=%08x cr4=%08x%s\n"
4616	"%-*s P - Present\n"
4617	"%-*s \| R/W - Read (0) / Write (1)\n"
4618	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4619	"%-*s \| \| \| A - Accessed\n"
4620	"%-*s \| \| \| \| D - Dirty\n"
4621	"%-*s \| \| \| \| \| G - Global\n"
4622	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4623	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4624	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4625	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4626	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4627	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4628	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4629	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4630	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4631	- W U - - - -- -- -- -- -- 010 */
4632	, cr3, cr4, fLongMode ? " Long Mode" : "",
4633	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4634	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4635
4636	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4637	{
4638	X86PDE Pde = pPD->a[i];
4639	if (Pde.n.u1Present)
4640	{
4641	const uint32_t u32Address = i << X86_PD_SHIFT;
4642
4643	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4644	Log(( /P R S A D G WT CD AT NX 4M a m d /
4645	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4646	u32Address,
4647	Pde.b.u1Write ? 'W' : 'R',
4648	Pde.b.u1User ? 'U' : 'S',
4649	Pde.b.u1Accessed ? 'A' : '-',
4650	Pde.b.u1Dirty ? 'D' : '-',
4651	Pde.b.u1Global ? 'G' : '-',
4652	Pde.b.u1WriteThru ? "WT" : "--",
4653	Pde.b.u1CacheDisable? "CD" : "--",
4654	Pde.b.u1PAT ? "AT" : "--",
4655	Pde.u & RT_BIT(9) ? '1' : '0',
4656	Pde.u & RT_BIT(10) ? '1' : '0',
4657	Pde.u & RT_BIT(11) ? '1' : '0',
4658	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4659	/** @todo PhysSearch */
4660	else
4661	{
4662	Log(( /P R S A D G WT CD AT NX 4M a m d /
4663	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4664	u32Address,
4665	Pde.n.u1Write ? 'W' : 'R',
4666	Pde.n.u1User ? 'U' : 'S',
4667	Pde.n.u1Accessed ? 'A' : '-',
4668	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4669	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4670	Pde.n.u1WriteThru ? "WT" : "--",
4671	Pde.n.u1CacheDisable? "CD" : "--",
4672	Pde.u & RT_BIT(9) ? '1' : '0',
4673	Pde.u & RT_BIT(10) ? '1' : '0',
4674	Pde.u & RT_BIT(11) ? '1' : '0',
4675	Pde.u & X86_PDE_PG_MASK));
4676	////if (cMaxDepth >= 1)
4677	{
4678	/** @todo what about using the page pool for mapping PTs? */
4679	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4680	PX86PT pPT = NULL;
4681
4682	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4683
4684	int rc2 = VERR_INVALID_PARAMETER;
4685	if (pPT)
4686	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4687	else
4688	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4689	if (rc2 < rc && RT_SUCCESS(rc))
4690	rc = rc2;
4691	}
4692	}
4693	}
4694	}
4695
4696	return rc;
4697	}
4698
4699
4700	/**
4701	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4702	*
4703	* @returns VBox status code (VINF_SUCCESS).
4704	* @param pVM The VM handle.
4705	* @param cr3 The root of the hierarchy.
4706	* @param cr4 The cr4, only PAE and PSE is currently used.
4707	* @param fLongMode Set if long mode, false if not long mode.
4708	* @param cMaxDepth Number of levels to dump.
4709	* @param pHlp Pointer to the output functions.
4710	*/
4711	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4712	{
4713	if (!pHlp)
4714	pHlp = DBGFR3InfoLogHlp();
4715	if (!cMaxDepth)
4716	return VINF_SUCCESS;
4717	const unsigned cch = fLongMode ? 16 : 8;
4718	pHlp->pfnPrintf(pHlp,
4719	"cr3=%08x cr4=%08x%s\n"
4720	"%-*s P - Present\n"
4721	"%-*s \| R/W - Read (0) / Write (1)\n"
4722	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4723	"%-*s \| \| \| A - Accessed\n"
4724	"%-*s \| \| \| \| D - Dirty\n"
4725	"%-*s \| \| \| \| \| G - Global\n"
4726	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4727	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4728	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4729	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4730	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4731	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4732	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4733	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4734	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4735	- W U - - - -- -- -- -- -- 010 */
4736	, cr3, cr4, fLongMode ? " Long Mode" : "",
4737	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4738	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4739	if (cr4 & X86_CR4_PAE)
4740	{
4741	if (fLongMode)
4742	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4743	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4744	}
4745	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4746	}
4747
4748	#ifdef VBOX_WITH_DEBUGGER
4749
4750	/**
4751	* The '.pgmram' command.
4752	*
4753	* @returns VBox status.
4754	* @param pCmd Pointer to the command descriptor (as registered).
4755	* @param pCmdHlp Pointer to command helper functions.
4756	* @param pVM Pointer to the current VM (if any).
4757	* @param paArgs Pointer to (readonly) array of arguments.
4758	* @param cArgs Number of arguments in the array.
4759	*/
4760	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4761	{
4762	/*
4763	* Validate input.
4764	*/
4765	if (!pVM)
4766	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4767	if (!pVM->pgm.s.pRamRangesRC)
4768	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4769
4770	/*
4771	* Dump the ranges.
4772	*/
4773	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4774	PPGMRAMRANGE pRam;
4775	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4776	{
4777	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4778	"%RGp - %RGp %p\n",
4779	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4780	if (RT_FAILURE(rc))
4781	return rc;
4782	}
4783
4784	return VINF_SUCCESS;
4785	}
4786
4787
4788	/**
4789	* The '.pgmmap' command.
4790	*
4791	* @returns VBox status.
4792	* @param pCmd Pointer to the command descriptor (as registered).
4793	* @param pCmdHlp Pointer to command helper functions.
4794	* @param pVM Pointer to the current VM (if any).
4795	* @param paArgs Pointer to (readonly) array of arguments.
4796	* @param cArgs Number of arguments in the array.
4797	*/
4798	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4799	{
4800	/*
4801	* Validate input.
4802	*/
4803	if (!pVM)
4804	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4805	if (!pVM->pgm.s.pMappingsR3)
4806	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4807
4808	/*
4809	* Print message about the fixedness of the mappings.
4810	*/
4811	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4812	if (RT_FAILURE(rc))
4813	return rc;
4814
4815	/*
4816	* Dump the ranges.
4817	*/
4818	PPGMMAPPING pCur;
4819	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4820	{
4821	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4822	"%08x - %08x %s\n",
4823	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4824	if (RT_FAILURE(rc))
4825	return rc;
4826	}
4827
4828	return VINF_SUCCESS;
4829	}
4830
4831
4832	/**
4833	* The '.pgmerror' and '.pgmerroroff' commands.
4834	*
4835	* @returns VBox status.
4836	* @param pCmd Pointer to the command descriptor (as registered).
4837	* @param pCmdHlp Pointer to command helper functions.
4838	* @param pVM Pointer to the current VM (if any).
4839	* @param paArgs Pointer to (readonly) array of arguments.
4840	* @param cArgs Number of arguments in the array.
4841	*/
4842	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4843	{
4844	/*
4845	* Validate input.
4846	*/
4847	if (!pVM)
4848	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4849	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4850	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4851
4852	if (!cArgs)
4853	{
4854	/*
4855	* Print the list of error injection locations with status.
4856	*/
4857	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4858	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4859	}
4860	else
4861	{
4862
4863	/*
4864	* String switch on where to inject the error.
4865	*/
4866	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4867	const char *pszWhere = paArgs[0].u.pszString;
4868	if (!strcmp(pszWhere, "handy"))
4869	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4870	else
4871	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4872	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4873	}
4874	return VINF_SUCCESS;
4875	}
4876
4877
4878	/**
4879	* The '.pgmsync' command.
4880	*
4881	* @returns VBox status.
4882	* @param pCmd Pointer to the command descriptor (as registered).
4883	* @param pCmdHlp Pointer to command helper functions.
4884	* @param pVM Pointer to the current VM (if any).
4885	* @param paArgs Pointer to (readonly) array of arguments.
4886	* @param cArgs Number of arguments in the array.
4887	*/
4888	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4889	{
4890	/** @todo SMP support */
4891	PVMCPU pVCpu = &pVM->aCpus[0];
4892
4893	/*
4894	* Validate input.
4895	*/
4896	if (!pVM)
4897	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4898
4899	/*
4900	* Force page directory sync.
4901	*/
4902	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4903
4904	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4905	if (RT_FAILURE(rc))
4906	return rc;
4907
4908	return VINF_SUCCESS;
4909	}
4910
4911
4912	#ifdef VBOX_STRICT
4913	/**
4914	* The '.pgmassertcr3' command.
4915	*
4916	* @returns VBox status.
4917	* @param pCmd Pointer to the command descriptor (as registered).
4918	* @param pCmdHlp Pointer to command helper functions.
4919	* @param pVM Pointer to the current VM (if any).
4920	* @param paArgs Pointer to (readonly) array of arguments.
4921	* @param cArgs Number of arguments in the array.
4922	*/
4923	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4924	{
4925	/** @todo SMP support!! */
4926	PVMCPU pVCpu = &pVM->aCpus[0];
4927
4928	/*
4929	* Validate input.
4930	*/
4931	if (!pVM)
4932	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4933
4934	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4935	if (RT_FAILURE(rc))
4936	return rc;
4937
4938	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4939
4940	return VINF_SUCCESS;
4941	}
4942	#endif /* VBOX_STRICT */
4943
4944
4945	/**
4946	* The '.pgmsyncalways' command.
4947	*
4948	* @returns VBox status.
4949	* @param pCmd Pointer to the command descriptor (as registered).
4950	* @param pCmdHlp Pointer to command helper functions.
4951	* @param pVM Pointer to the current VM (if any).
4952	* @param paArgs Pointer to (readonly) array of arguments.
4953	* @param cArgs Number of arguments in the array.
4954	*/
4955	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4956	{
4957	/** @todo SMP support!! */
4958	PVMCPU pVCpu = &pVM->aCpus[0];
4959
4960	/*
4961	* Validate input.
4962	*/
4963	if (!pVM)
4964	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4965
4966	/*
4967	* Force page directory sync.
4968	*/
4969	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4970	{
4971	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4972	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4973	}
4974	else
4975	{
4976	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4977	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4978	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4979	}
4980	}
4981
4982
4983	/**
4984	* The '.pgmsyncalways' command.
4985	*
4986	* @returns VBox status.
4987	* @param pCmd Pointer to the command descriptor (as registered).
4988	* @param pCmdHlp Pointer to command helper functions.
4989	* @param pVM Pointer to the current VM (if any).
4990	* @param paArgs Pointer to (readonly) array of arguments.
4991	* @param cArgs Number of arguments in the array.
4992	*/
4993	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4994	{
4995	/*
4996	* Validate input.
4997	*/
4998	if (!pVM)
4999	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
5000	if ( cArgs < 1
5001	\|\| cArgs > 2
5002	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
5003	\|\| ( cArgs > 1
5004	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
5005	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
5006	if ( cArgs >= 2
5007	&& strcmp(paArgs[1].u.pszString, "nozero"))
5008	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
5009	bool fIncZeroPgs = cArgs < 2;
5010
5011	/*
5012	* Open the output file and get the ram parameters.
5013	*/
5014	RTFILE hFile;
5015	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
5016	if (RT_FAILURE(rc))
5017	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
5018
5019	uint32_t cbRamHole = 0;
5020	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
5021	uint64_t cbRam = 0;
5022	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
5023	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
5024
5025	/*
5026	* Dump the physical memory, page by page.
5027	*/
5028	RTGCPHYS GCPhys = 0;
5029	char abZeroPg[PAGE_SIZE];
5030	RT_ZERO(abZeroPg);
5031
5032	pgmLock(pVM);
5033	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
5034	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
5035	pRam = pRam->pNextR3)
5036	{
5037	/* fill the gap */
5038	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
5039	{
5040	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
5041	{
5042	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5043	GCPhys += PAGE_SIZE;
5044	}
5045	}
5046
5047	PCPGMPAGE pPage = &pRam->aPages[0];
5048	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
5049	{
5050	if (PGM_PAGE_IS_ZERO(pPage))
5051	{
5052	if (fIncZeroPgs)
5053	{
5054	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5055	if (RT_FAILURE(rc))
5056	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5057	}
5058	}
5059	else
5060	{
5061	switch (PGM_PAGE_GET_TYPE(pPage))
5062	{
5063	case PGMPAGETYPE_RAM:
5064	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
5065	case PGMPAGETYPE_ROM:
5066	case PGMPAGETYPE_MMIO2:
5067	{
5068	void const *pvPage;
5069	PGMPAGEMAPLOCK Lock;
5070	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
5071	if (RT_SUCCESS(rc))
5072	{
5073	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
5074	PGMPhysReleasePageMappingLock(pVM, &Lock);
5075	if (RT_FAILURE(rc))
5076	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5077	}
5078	else
5079	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5080	break;
5081	}
5082
5083	default:
5084	AssertFailed();
5085	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
5086	case PGMPAGETYPE_MMIO:
5087	if (fIncZeroPgs)
5088	{
5089	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5090	if (RT_FAILURE(rc))
5091	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5092	}
5093	break;
5094	}
5095	}
5096
5097
5098	/* advance */
5099	GCPhys += PAGE_SIZE;
5100	pPage++;
5101	}
5102	}
5103	pgmUnlock(pVM);
5104
5105	RTFileClose(hFile);
5106	if (RT_SUCCESS(rc))
5107	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
5108	return VINF_SUCCESS;
5109	}
5110
5111	#endif /* VBOX_WITH_DEBUGGER */
5112
5113	/**
5114	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
5115	*/
5116	typedef struct PGMCHECKINTARGS
5117	{
5118	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
5119	PPGMPHYSHANDLER pPrevPhys;
5120	PPGMVIRTHANDLER pPrevVirt;
5121	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
5122	PVM pVM;
5123	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
5124
5125	/**
5126	* Validate a node in the physical handler tree.
5127	*
5128	* @returns 0 on if ok, other wise 1.
5129	* @param pNode The handler node.
5130	* @param pvUser pVM.
5131	*/
5132	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5133	{
5134	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5135	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
5136	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5137	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5138	AssertReleaseMsg( !pArgs->pPrevPhys
5139	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
5140	("pPrevPhys=%p %RGp-%RGp %s\n"
5141	" pCur=%p %RGp-%RGp %s\n",
5142	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
5143	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5144	pArgs->pPrevPhys = pCur;
5145	return 0;
5146	}
5147
5148
5149	/**
5150	* Validate a node in the virtual handler tree.
5151	*
5152	* @returns 0 on if ok, other wise 1.
5153	* @param pNode The handler node.
5154	* @param pvUser pVM.
5155	*/
5156	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5157	{
5158	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5159	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5160	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5161	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5162	AssertReleaseMsg( !pArgs->pPrevVirt
5163	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5164	("pPrevVirt=%p %RGv-%RGv %s\n"
5165	" pCur=%p %RGv-%RGv %s\n",
5166	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5167	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5168	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5169	{
5170	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5171	("pCur=%p %RGv-%RGv %s\n"
5172	"iPage=%d offVirtHandle=%#x expected %#x\n",
5173	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5174	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5175	}
5176	pArgs->pPrevVirt = pCur;
5177	return 0;
5178	}
5179
5180
5181	/**
5182	* Validate a node in the virtual handler tree.
5183	*
5184	* @returns 0 on if ok, other wise 1.
5185	* @param pNode The handler node.
5186	* @param pvUser pVM.
5187	*/
5188	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5189	{
5190	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5191	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5192	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5193	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5194	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5195	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5196	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5197	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5198	" pCur=%p %RGp-%RGp\n",
5199	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5200	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5201	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5202	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5203	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5204	" pCur=%p %RGp-%RGp\n",
5205	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5206	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5207	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5208	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5209	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5210	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5211	{
5212	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5213	for (;;)
5214	{
5215	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5216	AssertReleaseMsg(pCur2 != pCur,
5217	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5218	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5219	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5220	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5221	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5222	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5223	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5224	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5225	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5226	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5227	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5228	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5229	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5230	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5231	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5232	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5233	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5234	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5235	break;
5236	}
5237	}
5238
5239	pArgs->pPrevPhys2Virt = pCur;
5240	return 0;
5241	}
5242
5243
5244	/**
5245	* Perform an integrity check on the PGM component.
5246	*
5247	* @returns VINF_SUCCESS if everything is fine.
5248	* @returns VBox error status after asserting on integrity breach.
5249	* @param pVM The VM handle.
5250	*/
5251	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5252	{
5253	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5254
5255	/*
5256	* Check the trees.
5257	*/
5258	int cErrors = 0;
5259	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5260	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5261	PGMCHECKINTARGS Args = s_LeftToRight;
5262	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5263	Args = s_RightToLeft;
5264	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5265	Args = s_LeftToRight;
5266	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5267	Args = s_RightToLeft;
5268	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5269	Args = s_LeftToRight;
5270	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5271	Args = s_RightToLeft;
5272	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5273	Args = s_LeftToRight;
5274	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5275	Args = s_RightToLeft;
5276	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5277
5278	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5279	}
5280
5281

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 22349

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