PGM.cpp@ 22544

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SSM,VMM,Devices,Main,VBoxBFE: Live snapshot/migration SSM API adjustments.
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1	/* $Id: PGM.cpp 22480 2009-08-26 17:14:13Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include <VBox/hwaccm.h>
592	#include "PGMInternal.h"
593	#include <VBox/vm.h>
594
595	#include <VBox/dbg.h>
596	#include <VBox/param.h>
597	#include <VBox/err.h>
598
599	#include <iprt/asm.h>
600	#include <iprt/assert.h>
601	#include <iprt/env.h>
602	#include <iprt/mem.h>
603	#include <iprt/file.h>
604	#include <iprt/string.h>
605	#include <iprt/thread.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
652	#endif
653
654
655	/*******************************************************************************
656	* Global Variables *
657	*******************************************************************************/
658	#ifdef VBOX_WITH_DEBUGGER
659	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
660	static const DBGCVARDESC g_aPgmErrorArgs[] =
661	{
662	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
663	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
664	};
665
666	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
667	{
668	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
669	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
670	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
671	};
672
673	/** Command descriptors. */
674	static const DBGCCMD g_aCmds[] =
675	{
676	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
677	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
678	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
679	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
680	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
681	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
682	#ifdef VBOX_STRICT
683	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
684	#endif
685	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
686	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
687	};
688	#endif
689
690
691
692
693	/*
694	* Shadow - 32-bit mode
695	*/
696	#define PGM_SHW_TYPE PGM_TYPE_32BIT
697	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
698	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
699	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
700	#include "PGMShw.h"
701
702	/* Guest - real mode */
703	#define PGM_GST_TYPE PGM_TYPE_REAL
704	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
705	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
706	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
707	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
708	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
709	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
710	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
711	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
712	#include "PGMBth.h"
713	#include "PGMGstDefs.h"
714	#include "PGMGst.h"
715	#undef BTH_PGMPOOLKIND_PT_FOR_PT
716	#undef BTH_PGMPOOLKIND_ROOT
717	#undef PGM_BTH_NAME
718	#undef PGM_BTH_NAME_RC_STR
719	#undef PGM_BTH_NAME_R0_STR
720	#undef PGM_GST_TYPE
721	#undef PGM_GST_NAME
722	#undef PGM_GST_NAME_RC_STR
723	#undef PGM_GST_NAME_R0_STR
724
725	/* Guest - protected mode */
726	#define PGM_GST_TYPE PGM_TYPE_PROT
727	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
728	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
729	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
730	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
731	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
732	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
733	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_PT
739	#undef BTH_PGMPOOLKIND_ROOT
740	#undef PGM_BTH_NAME
741	#undef PGM_BTH_NAME_RC_STR
742	#undef PGM_BTH_NAME_R0_STR
743	#undef PGM_GST_TYPE
744	#undef PGM_GST_NAME
745	#undef PGM_GST_NAME_RC_STR
746	#undef PGM_GST_NAME_R0_STR
747
748	/* Guest - 32-bit mode */
749	#define PGM_GST_TYPE PGM_TYPE_32BIT
750	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
751	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
752	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
754	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
755	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
756	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
757	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
758	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
759	#include "PGMBth.h"
760	#include "PGMGstDefs.h"
761	#include "PGMGst.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
763	#undef BTH_PGMPOOLKIND_PT_FOR_PT
764	#undef BTH_PGMPOOLKIND_ROOT
765	#undef PGM_BTH_NAME
766	#undef PGM_BTH_NAME_RC_STR
767	#undef PGM_BTH_NAME_R0_STR
768	#undef PGM_GST_TYPE
769	#undef PGM_GST_NAME
770	#undef PGM_GST_NAME_RC_STR
771	#undef PGM_GST_NAME_R0_STR
772
773	#undef PGM_SHW_TYPE
774	#undef PGM_SHW_NAME
775	#undef PGM_SHW_NAME_RC_STR
776	#undef PGM_SHW_NAME_R0_STR
777
778
779	/*
780	* Shadow - PAE mode
781	*/
782	#define PGM_SHW_TYPE PGM_TYPE_PAE
783	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
784	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
785	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
786	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
787	#include "PGMShw.h"
788
789	/* Guest - real mode */
790	#define PGM_GST_TYPE PGM_TYPE_REAL
791	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
792	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
793	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
794	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
795	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
796	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
797	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
798	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
799	#include "PGMGstDefs.h"
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_PT
802	#undef BTH_PGMPOOLKIND_ROOT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - protected mode */
812	#define PGM_GST_TYPE PGM_TYPE_PROT
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
820	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
821	#include "PGMGstDefs.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - 32-bit mode */
834	#define PGM_GST_TYPE PGM_TYPE_32BIT
835	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
844	#include "PGMGstDefs.h"
845	#include "PGMBth.h"
846	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
847	#undef BTH_PGMPOOLKIND_PT_FOR_PT
848	#undef BTH_PGMPOOLKIND_ROOT
849	#undef PGM_BTH_NAME
850	#undef PGM_BTH_NAME_RC_STR
851	#undef PGM_BTH_NAME_R0_STR
852	#undef PGM_GST_TYPE
853	#undef PGM_GST_NAME
854	#undef PGM_GST_NAME_RC_STR
855	#undef PGM_GST_NAME_R0_STR
856
857	/* Guest - PAE mode */
858	#define PGM_GST_TYPE PGM_TYPE_PAE
859	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
860	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
861	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
862	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
863	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
864	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
865	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
866	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
867	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
868	#include "PGMBth.h"
869	#include "PGMGstDefs.h"
870	#include "PGMGst.h"
871	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
872	#undef BTH_PGMPOOLKIND_PT_FOR_PT
873	#undef BTH_PGMPOOLKIND_ROOT
874	#undef PGM_BTH_NAME
875	#undef PGM_BTH_NAME_RC_STR
876	#undef PGM_BTH_NAME_R0_STR
877	#undef PGM_GST_TYPE
878	#undef PGM_GST_NAME
879	#undef PGM_GST_NAME_RC_STR
880	#undef PGM_GST_NAME_R0_STR
881
882	#undef PGM_SHW_TYPE
883	#undef PGM_SHW_NAME
884	#undef PGM_SHW_NAME_RC_STR
885	#undef PGM_SHW_NAME_R0_STR
886
887
888	/*
889	* Shadow - AMD64 mode
890	*/
891	#define PGM_SHW_TYPE PGM_TYPE_AMD64
892	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
893	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
894	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
895	#include "PGMShw.h"
896
897	#ifdef VBOX_WITH_64_BITS_GUESTS
898	/* Guest - AMD64 mode */
899	# define PGM_GST_TYPE PGM_TYPE_AMD64
900	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
901	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
902	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
903	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
904	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
905	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
906	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
907	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
908	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
909	# include "PGMBth.h"
910	# include "PGMGstDefs.h"
911	# include "PGMGst.h"
912	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
913	# undef BTH_PGMPOOLKIND_PT_FOR_PT
914	# undef BTH_PGMPOOLKIND_ROOT
915	# undef PGM_BTH_NAME
916	# undef PGM_BTH_NAME_RC_STR
917	# undef PGM_BTH_NAME_R0_STR
918	# undef PGM_GST_TYPE
919	# undef PGM_GST_NAME
920	# undef PGM_GST_NAME_RC_STR
921	# undef PGM_GST_NAME_R0_STR
922	#endif /* VBOX_WITH_64_BITS_GUESTS */
923
924	#undef PGM_SHW_TYPE
925	#undef PGM_SHW_NAME
926	#undef PGM_SHW_NAME_RC_STR
927	#undef PGM_SHW_NAME_R0_STR
928
929
930	/*
931	* Shadow - Nested paging mode
932	*/
933	#define PGM_SHW_TYPE PGM_TYPE_NESTED
934	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
935	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
936	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
937	#include "PGMShw.h"
938
939	/* Guest - real mode */
940	#define PGM_GST_TYPE PGM_TYPE_REAL
941	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
942	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
943	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
944	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
945	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
946	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
947	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
948	#include "PGMGstDefs.h"
949	#include "PGMBth.h"
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_RC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_RC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - protected mode */
960	#define PGM_GST_TYPE PGM_TYPE_PROT
961	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
962	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
965	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
968	#include "PGMGstDefs.h"
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_PT
971	#undef PGM_BTH_NAME
972	#undef PGM_BTH_NAME_RC_STR
973	#undef PGM_BTH_NAME_R0_STR
974	#undef PGM_GST_TYPE
975	#undef PGM_GST_NAME
976	#undef PGM_GST_NAME_RC_STR
977	#undef PGM_GST_NAME_R0_STR
978
979	/* Guest - 32-bit mode */
980	#define PGM_GST_TYPE PGM_TYPE_32BIT
981	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
982	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
983	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
984	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
985	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
986	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
987	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
988	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
989	#include "PGMGstDefs.h"
990	#include "PGMBth.h"
991	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
992	#undef BTH_PGMPOOLKIND_PT_FOR_PT
993	#undef PGM_BTH_NAME
994	#undef PGM_BTH_NAME_RC_STR
995	#undef PGM_BTH_NAME_R0_STR
996	#undef PGM_GST_TYPE
997	#undef PGM_GST_NAME
998	#undef PGM_GST_NAME_RC_STR
999	#undef PGM_GST_NAME_R0_STR
1000
1001	/* Guest - PAE mode */
1002	#define PGM_GST_TYPE PGM_TYPE_PAE
1003	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1004	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1005	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1006	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1007	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1008	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1009	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1010	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1011	#include "PGMGstDefs.h"
1012	#include "PGMBth.h"
1013	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1014	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1015	#undef PGM_BTH_NAME
1016	#undef PGM_BTH_NAME_RC_STR
1017	#undef PGM_BTH_NAME_R0_STR
1018	#undef PGM_GST_TYPE
1019	#undef PGM_GST_NAME
1020	#undef PGM_GST_NAME_RC_STR
1021	#undef PGM_GST_NAME_R0_STR
1022
1023	#ifdef VBOX_WITH_64_BITS_GUESTS
1024	/* Guest - AMD64 mode */
1025	# define PGM_GST_TYPE PGM_TYPE_AMD64
1026	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1027	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1028	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1029	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1030	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1031	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1032	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1033	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1034	# include "PGMGstDefs.h"
1035	# include "PGMBth.h"
1036	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1037	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	# undef PGM_BTH_NAME
1039	# undef PGM_BTH_NAME_RC_STR
1040	# undef PGM_BTH_NAME_R0_STR
1041	# undef PGM_GST_TYPE
1042	# undef PGM_GST_NAME
1043	# undef PGM_GST_NAME_RC_STR
1044	# undef PGM_GST_NAME_R0_STR
1045	#endif /* VBOX_WITH_64_BITS_GUESTS */
1046
1047	#undef PGM_SHW_TYPE
1048	#undef PGM_SHW_NAME
1049	#undef PGM_SHW_NAME_RC_STR
1050	#undef PGM_SHW_NAME_R0_STR
1051
1052
1053	/*
1054	* Shadow - EPT
1055	*/
1056	#define PGM_SHW_TYPE PGM_TYPE_EPT
1057	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1058	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1059	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1060	#include "PGMShw.h"
1061
1062	/* Guest - real mode */
1063	#define PGM_GST_TYPE PGM_TYPE_REAL
1064	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1065	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1066	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1067	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1068	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1069	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1070	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1071	#include "PGMGstDefs.h"
1072	#include "PGMBth.h"
1073	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1074	#undef PGM_BTH_NAME
1075	#undef PGM_BTH_NAME_RC_STR
1076	#undef PGM_BTH_NAME_R0_STR
1077	#undef PGM_GST_TYPE
1078	#undef PGM_GST_NAME
1079	#undef PGM_GST_NAME_RC_STR
1080	#undef PGM_GST_NAME_R0_STR
1081
1082	/* Guest - protected mode */
1083	#define PGM_GST_TYPE PGM_TYPE_PROT
1084	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1085	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1086	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1087	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1088	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1089	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1090	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1091	#include "PGMGstDefs.h"
1092	#include "PGMBth.h"
1093	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1094	#undef PGM_BTH_NAME
1095	#undef PGM_BTH_NAME_RC_STR
1096	#undef PGM_BTH_NAME_R0_STR
1097	#undef PGM_GST_TYPE
1098	#undef PGM_GST_NAME
1099	#undef PGM_GST_NAME_RC_STR
1100	#undef PGM_GST_NAME_R0_STR
1101
1102	/* Guest - 32-bit mode */
1103	#define PGM_GST_TYPE PGM_TYPE_32BIT
1104	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1105	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1106	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1107	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1108	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1109	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1111	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1112	#include "PGMGstDefs.h"
1113	#include "PGMBth.h"
1114	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1115	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1116	#undef PGM_BTH_NAME
1117	#undef PGM_BTH_NAME_RC_STR
1118	#undef PGM_BTH_NAME_R0_STR
1119	#undef PGM_GST_TYPE
1120	#undef PGM_GST_NAME
1121	#undef PGM_GST_NAME_RC_STR
1122	#undef PGM_GST_NAME_R0_STR
1123
1124	/* Guest - PAE mode */
1125	#define PGM_GST_TYPE PGM_TYPE_PAE
1126	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1127	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1128	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1129	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1130	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1131	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1132	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1133	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1134	#include "PGMGstDefs.h"
1135	#include "PGMBth.h"
1136	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1137	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1138	#undef PGM_BTH_NAME
1139	#undef PGM_BTH_NAME_RC_STR
1140	#undef PGM_BTH_NAME_R0_STR
1141	#undef PGM_GST_TYPE
1142	#undef PGM_GST_NAME
1143	#undef PGM_GST_NAME_RC_STR
1144	#undef PGM_GST_NAME_R0_STR
1145
1146	#ifdef VBOX_WITH_64_BITS_GUESTS
1147	/* Guest - AMD64 mode */
1148	# define PGM_GST_TYPE PGM_TYPE_AMD64
1149	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1150	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1151	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1152	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1153	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1154	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1155	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1156	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1157	# include "PGMGstDefs.h"
1158	# include "PGMBth.h"
1159	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1160	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1161	# undef PGM_BTH_NAME
1162	# undef PGM_BTH_NAME_RC_STR
1163	# undef PGM_BTH_NAME_R0_STR
1164	# undef PGM_GST_TYPE
1165	# undef PGM_GST_NAME
1166	# undef PGM_GST_NAME_RC_STR
1167	# undef PGM_GST_NAME_R0_STR
1168	#endif /* VBOX_WITH_64_BITS_GUESTS */
1169
1170	#undef PGM_SHW_TYPE
1171	#undef PGM_SHW_NAME
1172	#undef PGM_SHW_NAME_RC_STR
1173	#undef PGM_SHW_NAME_R0_STR
1174
1175
1176
1177	/**
1178	* Initiates the paging of VM.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM Pointer to VM structure.
1182	*/
1183	VMMR3DECL(int) PGMR3Init(PVM pVM)
1184	{
1185	LogFlow(("PGMR3Init:\n"));
1186	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1187	int rc;
1188
1189	/*
1190	* Assert alignment and sizes.
1191	*/
1192	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1193	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1194
1195	/*
1196	* Init the structure.
1197	*/
1198	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1199	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1200
1201	/* Init the per-CPU part. */
1202	for (unsigned i=0;i<pVM->cCPUs;i++)
1203	{
1204	PVMCPU pVCpu = &pVM->aCpus[i];
1205	PPGMCPU pPGM = &pVCpu->pgm.s;
1206
1207	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1208	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1209	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1210
1211	pPGM->enmShadowMode = PGMMODE_INVALID;
1212	pPGM->enmGuestMode = PGMMODE_INVALID;
1213
1214	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1215
1216	pPGM->pGstPaePdptR3 = NULL;
1217	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1218	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1219	#endif
1220	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1221	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1222	{
1223	pPGM->apGstPaePDsR3[i] = NULL;
1224	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1226	#endif
1227	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1228	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1229	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1230	}
1231
1232	pPGM->fA20Enabled = true;
1233	}
1234
1235	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1236	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1237	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1238
1239	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1240	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1241	true
1242	#else
1243	false
1244	#endif
1245	);
1246	AssertLogRelRCReturn(rc, rc);
1247
1248	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1249	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1250	#else
1251	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1252	#endif
1253	AssertLogRelRCReturn(rc, rc);
1254	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1255	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1256
1257	/*
1258	* Get the configured RAM size - to estimate saved state size.
1259	*/
1260	uint64_t cbRam;
1261	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1262	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1263	cbRam = 0;
1264	else if (RT_SUCCESS(rc))
1265	{
1266	if (cbRam < PAGE_SIZE)
1267	cbRam = 0;
1268	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1269	}
1270	else
1271	{
1272	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1273	return rc;
1274	}
1275
1276	/*
1277	* Register callbacks, string formatters and the saved state data unit.
1278	*/
1279	#ifdef VBOX_STRICT
1280	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1281	#endif
1282	PGMRegisterStringFormatTypes();
1283
1284	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1285	NULL, NULL, NULL,
1286	NULL, pgmR3Save, NULL,
1287	NULL, pgmR3Load, NULL);
1288	if (RT_FAILURE(rc))
1289	return rc;
1290
1291	/*
1292	* Initialize the PGM critical section and flush the phys TLBs
1293	*/
1294	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1295	AssertRCReturn(rc, rc);
1296
1297	PGMR3PhysChunkInvalidateTLB(pVM);
1298	PGMPhysInvalidatePageR3MapTLB(pVM);
1299	PGMPhysInvalidatePageR0MapTLB(pVM);
1300	PGMPhysInvalidatePageGCMapTLB(pVM);
1301
1302	/*
1303	* For the time being we sport a full set of handy pages in addition to the base
1304	* memory to simplify things.
1305	*/
1306	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1307	AssertRCReturn(rc, rc);
1308
1309	/*
1310	* Trees
1311	*/
1312	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1313	if (RT_SUCCESS(rc))
1314	{
1315	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1316	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1317
1318	/*
1319	* Alocate the zero page.
1320	*/
1321	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1322	}
1323	if (RT_SUCCESS(rc))
1324	{
1325	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1326	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1327	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1328	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1329
1330	/*
1331	* Init the paging.
1332	*/
1333	rc = pgmR3InitPaging(pVM);
1334	}
1335	if (RT_SUCCESS(rc))
1336	{
1337	/*
1338	* Init the page pool.
1339	*/
1340	rc = pgmR3PoolInit(pVM);
1341	}
1342	if (RT_SUCCESS(rc))
1343	{
1344	for (unsigned i=0;i<pVM->cCPUs;i++)
1345	{
1346	PVMCPU pVCpu = &pVM->aCpus[i];
1347
1348	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1349	if (RT_FAILURE(rc))
1350	break;
1351	}
1352	}
1353
1354	if (RT_SUCCESS(rc))
1355	{
1356	/*
1357	* Info & statistics
1358	*/
1359	DBGFR3InfoRegisterInternal(pVM, "mode",
1360	"Shows the current paging mode. "
1361	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1362	pgmR3InfoMode);
1363	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1364	"Dumps all the entries in the top level paging table. No arguments.",
1365	pgmR3InfoCr3);
1366	DBGFR3InfoRegisterInternal(pVM, "phys",
1367	"Dumps all the physical address ranges. No arguments.",
1368	pgmR3PhysInfo);
1369	DBGFR3InfoRegisterInternal(pVM, "handlers",
1370	"Dumps physical, virtual and hyper virtual handlers. "
1371	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1372	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1373	pgmR3InfoHandlers);
1374	DBGFR3InfoRegisterInternal(pVM, "mappings",
1375	"Dumps guest mappings.",
1376	pgmR3MapInfo);
1377
1378	pgmR3InitStats(pVM);
1379
1380	#ifdef VBOX_WITH_DEBUGGER
1381	/*
1382	* Debugger commands.
1383	*/
1384	static bool s_fRegisteredCmds = false;
1385	if (!s_fRegisteredCmds)
1386	{
1387	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1388	if (RT_SUCCESS(rc))
1389	s_fRegisteredCmds = true;
1390	}
1391	#endif
1392	return VINF_SUCCESS;
1393	}
1394
1395	/* Almost no cleanup necessary, MM frees all memory. */
1396	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1397
1398	return rc;
1399	}
1400
1401
1402	/**
1403	* Initializes the per-VCPU PGM.
1404	*
1405	* @returns VBox status code.
1406	* @param pVM The VM to operate on.
1407	*/
1408	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1409	{
1410	LogFlow(("PGMR3InitCPU\n"));
1411	return VINF_SUCCESS;
1412	}
1413
1414
1415	/**
1416	* Init paging.
1417	*
1418	* Since we need to check what mode the host is operating in before we can choose
1419	* the right paging functions for the host we have to delay this until R0 has
1420	* been initialized.
1421	*
1422	* @returns VBox status code.
1423	* @param pVM VM handle.
1424	*/
1425	static int pgmR3InitPaging(PVM pVM)
1426	{
1427	/*
1428	* Force a recalculation of modes and switcher so everyone gets notified.
1429	*/
1430	for (unsigned i=0;i<pVM->cCPUs;i++)
1431	{
1432	PVMCPU pVCpu = &pVM->aCpus[i];
1433
1434	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1435	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1436	}
1437
1438	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1439
1440	/*
1441	* Allocate static mapping space for whatever the cr3 register
1442	* points to and in the case of PAE mode to the 4 PDs.
1443	*/
1444	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1445	if (RT_FAILURE(rc))
1446	{
1447	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1448	return rc;
1449	}
1450	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1451
1452	/*
1453	* Allocate pages for the three possible intermediate contexts
1454	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1455	* for the sake of simplicity. The AMD64 uses the PAE for the
1456	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1457	*
1458	* We assume that two page tables will be enought for the core code
1459	* mappings (HC virtual and identity).
1460	*/
1461	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1471	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1472	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1473
1474	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1475	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1476	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1477	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1478	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1479	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1480
1481	/*
1482	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1483	*/
1484	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1485	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1486	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1487
1488	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1489	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1490
1491	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1492	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1493	{
1494	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1495	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1496	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1497	}
1498
1499	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1500	{
1501	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1502	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1503	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1504	}
1505
1506	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1507	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1508	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1509	\| HCPhysInterPaePDPT64;
1510
1511	/*
1512	* Initialize paging workers and mode from current host mode
1513	* and the guest running in real mode.
1514	*/
1515	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1516	switch (pVM->pgm.s.enmHostMode)
1517	{
1518	case SUPPAGINGMODE_32_BIT:
1519	case SUPPAGINGMODE_32_BIT_GLOBAL:
1520	case SUPPAGINGMODE_PAE:
1521	case SUPPAGINGMODE_PAE_GLOBAL:
1522	case SUPPAGINGMODE_PAE_NX:
1523	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1524	break;
1525
1526	case SUPPAGINGMODE_AMD64:
1527	case SUPPAGINGMODE_AMD64_GLOBAL:
1528	case SUPPAGINGMODE_AMD64_NX:
1529	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1530	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1531	if (ARCH_BITS != 64)
1532	{
1533	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1534	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1535	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1536	}
1537	#endif
1538	break;
1539	default:
1540	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1541	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1542	}
1543	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1544	if (RT_SUCCESS(rc))
1545	{
1546	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1547	#if HC_ARCH_BITS == 64
1548	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1549	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1550	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1552	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1553	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1554	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1555	#endif
1556
1557	return VINF_SUCCESS;
1558	}
1559
1560	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1561	return rc;
1562	}
1563
1564
1565	/**
1566	* Init statistics
1567	*/
1568	static void pgmR3InitStats(PVM pVM)
1569	{
1570	PPGM pPGM = &pVM->pgm.s;
1571	int rc;
1572
1573	/* Common - misc variables */
1574	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1575	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1576	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1577	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1578	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1579	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1580	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1581	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1582
1583	#ifdef VBOX_WITH_STATISTICS
1584
1585	# define PGM_REG_COUNTER(a, b, c) \
1586	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1587	AssertRC(rc);
1588
1589	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1590	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1591	AssertRC(rc);
1592
1593	# define PGM_REG_PROFILE(a, b, c) \
1594	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1595	AssertRC(rc);
1596
1597	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1598	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1599	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1600	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1601	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1602	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1603	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1604	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1605	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1606	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1607
1608	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1609	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1610	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1611	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1612	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1613	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1614	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1615	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1616
1617	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1618	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1619	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1620	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1621
1622	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1623	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1624	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1625	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1626
1627	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1628	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1629	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1630	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1631	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1632	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1633
1634	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1635	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1636	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1637	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1638	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1639	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1640	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1641	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1642
1643	/* GC only: */
1644	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1645	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1646	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1647	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1648
1649	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1650	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1651	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1652	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1653	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1654	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1655	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1656	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1657
1658	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1659	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1660	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1661	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1662	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1663	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1664	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1665	# endif
1666
1667	# undef PGM_REG_COUNTER
1668	# undef PGM_REG_PROFILE
1669	#endif
1670
1671	/*
1672	* Note! The layout below matches the member layout exactly!
1673	*/
1674
1675	/*
1676	* Common - stats
1677	*/
1678	for (unsigned i=0;i<pVM->cCPUs;i++)
1679	{
1680	PVMCPU pVCpu = &pVM->aCpus[i];
1681	PPGMCPU pPGM = &pVCpu->pgm.s;
1682
1683	#define PGM_REG_COUNTER(a, b, c) \
1684	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1685	AssertRC(rc);
1686	#define PGM_REG_PROFILE(a, b, c) \
1687	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1688	AssertRC(rc);
1689
1690	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1691
1692	#ifdef VBOX_WITH_STATISTICS
1693
1694	# if 0 /* rarely useful; leave for debugging. */
1695	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1696	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1697	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1698	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1699	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1700	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1701	# endif
1702	/* R0 only: */
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1704	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1705	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1706	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1707	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1708	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1709	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1713	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1714	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1715	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1716	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1717	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1718	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1719	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1720	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1721	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1722	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1723	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1724	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1725	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1726	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1727	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1728	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1729	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1730	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1731	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1732	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1733	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1734	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1735	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1736	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1737	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1738	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1739
1740	/* RZ only: */
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1747	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1748	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1749	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1750	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1751	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1752	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1753	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1754	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1755	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1756	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1757	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1758	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1772	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1773	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1774	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1775	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1776	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1777	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1778	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1779	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1780	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1781	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1782	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1783	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1784	#if 0 /* rarely useful; leave for debugging. */
1785	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1786	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1787	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1788	#endif
1789	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1790	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1791	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1792	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1793	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1794
1795	/* HC only: */
1796
1797	/* RZ & R3: */
1798	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1799	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1801	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1802	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1803	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1804	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1805	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1806	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1807	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1808	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1809	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1810	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1811	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1812	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1813	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1814	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1815	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1816	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1817	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1818	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1819	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1820	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1821	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1822	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1823	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1824	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1825	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1826	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1827	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1828	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1829	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1830	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1831	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1832	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1833	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1834	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1835	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1836	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1837	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1838	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1839	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1840	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1841	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1842
1843	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1844	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1846	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1847	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1848	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1849	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1850	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1851	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1852	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1853	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1854	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1855	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1856	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1857	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1858	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1859	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1860	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1861	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1862	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1863	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1864	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1865	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1866	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1867	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1868	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1869	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1870	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1871	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1872	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1873	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1874	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1875	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1876	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1877	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1878	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1879	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1880	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1881	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1882	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1883	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1884	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1885	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1886	#endif /* VBOX_WITH_STATISTICS */
1887
1888	#undef PGM_REG_PROFILE
1889	#undef PGM_REG_COUNTER
1890
1891	}
1892	}
1893
1894
1895	/**
1896	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1897	*
1898	* The dynamic mapping area will also be allocated and initialized at this
1899	* time. We could allocate it during PGMR3Init of course, but the mapping
1900	* wouldn't be allocated at that time preventing us from setting up the
1901	* page table entries with the dummy page.
1902	*
1903	* @returns VBox status code.
1904	* @param pVM VM handle.
1905	*/
1906	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1907	{
1908	RTGCPTR GCPtr;
1909	int rc;
1910
1911	/*
1912	* Reserve space for the dynamic mappings.
1913	*/
1914	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1915	if (RT_SUCCESS(rc))
1916	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1917
1918	if ( RT_SUCCESS(rc)
1919	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1920	{
1921	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1922	if (RT_SUCCESS(rc))
1923	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1924	}
1925	if (RT_SUCCESS(rc))
1926	{
1927	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1928	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1929	}
1930	return rc;
1931	}
1932
1933
1934	/**
1935	* Ring-3 init finalizing.
1936	*
1937	* @returns VBox status code.
1938	* @param pVM The VM handle.
1939	*/
1940	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1941	{
1942	int rc;
1943
1944	/*
1945	* Reserve space for the dynamic mappings.
1946	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1947	*/
1948	/* get the pointer to the page table entries. */
1949	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1950	AssertRelease(pMapping);
1951	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1952	const unsigned iPT = off >> X86_PD_SHIFT;
1953	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1954	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1955	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1956
1957	/* init cache */
1958	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1959	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1960	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1961
1962	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1963	{
1964	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1965	AssertRCReturn(rc, rc);
1966	}
1967
1968	/*
1969	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1970	* Intel only goes up to 36 bits, so we stick to 36 as well.
1971	*/
1972	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1973	uint32_t u32Dummy, u32Features;
1974	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1975
1976	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1977	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1978	else
1979	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1980
1981	/*
1982	* Allocate memory if we're supposed to do that.
1983	*/
1984	if (pVM->pgm.s.fRamPreAlloc)
1985	rc = pgmR3PhysRamPreAllocate(pVM);
1986
1987	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1988	return rc;
1989	}
1990
1991
1992	/**
1993	* Applies relocations to data and code managed by this component.
1994	*
1995	* This function will be called at init and whenever the VMM need to relocate it
1996	* self inside the GC.
1997	*
1998	* @param pVM The VM.
1999	* @param offDelta Relocation delta relative to old location.
2000	*/
2001	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2002	{
2003	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2004
2005	/*
2006	* Paging stuff.
2007	*/
2008	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2009
2010	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2011
2012	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2013	for (unsigned i=0;i<pVM->cCPUs;i++)
2014	{
2015	PVMCPU pVCpu = &pVM->aCpus[i];
2016
2017	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2018
2019	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2020	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2021	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2022	}
2023
2024	/*
2025	* Trees.
2026	*/
2027	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2028
2029	/*
2030	* Ram ranges.
2031	*/
2032	if (pVM->pgm.s.pRamRangesR3)
2033	{
2034	/* Update the pSelfRC pointers and relink them. */
2035	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2036	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2037	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2038	pgmR3PhysRelinkRamRanges(pVM);
2039	}
2040
2041	/*
2042	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2043	* be mapped and thus not included in the above exercise.
2044	*/
2045	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2046	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2047	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2048
2049	/*
2050	* Update the two page directories with all page table mappings.
2051	* (One or more of them have changed, that's why we're here.)
2052	*/
2053	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2054	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2055	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2056
2057	/* Relocate GC addresses of Page Tables. */
2058	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2059	{
2060	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2061	{
2062	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2063	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2064	}
2065	}
2066
2067	/*
2068	* Dynamic page mapping area.
2069	*/
2070	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2071	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2072	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2073
2074	/*
2075	* The Zero page.
2076	*/
2077	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2078	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2079	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2080	#else
2081	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2082	#endif
2083
2084	/*
2085	* Physical and virtual handlers.
2086	*/
2087	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2088	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2089	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2090
2091	/*
2092	* The page pool.
2093	*/
2094	pgmR3PoolRelocate(pVM);
2095	}
2096
2097
2098	/**
2099	* Callback function for relocating a physical access handler.
2100	*
2101	* @returns 0 (continue enum)
2102	* @param pNode Pointer to a PGMPHYSHANDLER node.
2103	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2104	* not certain the delta will fit in a void pointer for all possible configs.
2105	*/
2106	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2107	{
2108	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2109	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2110	if (pHandler->pfnHandlerRC)
2111	pHandler->pfnHandlerRC += offDelta;
2112	if (pHandler->pvUserRC >= 0x10000)
2113	pHandler->pvUserRC += offDelta;
2114	return 0;
2115	}
2116
2117
2118	/**
2119	* Callback function for relocating a virtual access handler.
2120	*
2121	* @returns 0 (continue enum)
2122	* @param pNode Pointer to a PGMVIRTHANDLER node.
2123	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2124	* not certain the delta will fit in a void pointer for all possible configs.
2125	*/
2126	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2127	{
2128	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2129	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2130	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2131	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2132	Assert(pHandler->pfnHandlerRC);
2133	pHandler->pfnHandlerRC += offDelta;
2134	return 0;
2135	}
2136
2137
2138	/**
2139	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2140	*
2141	* @returns 0 (continue enum)
2142	* @param pNode Pointer to a PGMVIRTHANDLER node.
2143	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2144	* not certain the delta will fit in a void pointer for all possible configs.
2145	*/
2146	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2147	{
2148	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2149	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2150	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2151	Assert(pHandler->pfnHandlerRC);
2152	pHandler->pfnHandlerRC += offDelta;
2153	return 0;
2154	}
2155
2156
2157	/**
2158	* The VM is being reset.
2159	*
2160	* For the PGM component this means that any PD write monitors
2161	* needs to be removed.
2162	*
2163	* @param pVM VM handle.
2164	*/
2165	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2166	{
2167	int rc;
2168
2169	LogFlow(("PGMR3Reset:\n"));
2170	VM_ASSERT_EMT(pVM);
2171
2172	pgmLock(pVM);
2173
2174	/*
2175	* Unfix any fixed mappings and disable CR3 monitoring.
2176	*/
2177	pVM->pgm.s.fMappingsFixed = false;
2178	pVM->pgm.s.GCPtrMappingFixed = 0;
2179	pVM->pgm.s.cbMappingFixed = 0;
2180
2181	/* Exit the guest paging mode before the pgm pool gets reset.
2182	* Important to clean up the amd64 case.
2183	*/
2184	for (unsigned i=0;i<pVM->cCPUs;i++)
2185	{
2186	PVMCPU pVCpu = &pVM->aCpus[i];
2187
2188	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2189	AssertRC(rc);
2190	}
2191
2192	#ifdef DEBUG
2193	DBGFR3InfoLog(pVM, "mappings", NULL);
2194	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2195	#endif
2196
2197	/*
2198	* Switch mode back to real mode. (before resetting the pgm pool!)
2199	*/
2200	for (unsigned i=0;i<pVM->cCPUs;i++)
2201	{
2202	PVMCPU pVCpu = &pVM->aCpus[i];
2203
2204	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2205	AssertRC(rc);
2206
2207	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2208	}
2209
2210	/*
2211	* Reset the shadow page pool.
2212	*/
2213	pgmR3PoolReset(pVM);
2214
2215	for (unsigned i=0;i<pVM->cCPUs;i++)
2216	{
2217	PVMCPU pVCpu = &pVM->aCpus[i];
2218
2219	/*
2220	* Re-init other members.
2221	*/
2222	pVCpu->pgm.s.fA20Enabled = true;
2223
2224	/*
2225	* Clear the FFs PGM owns.
2226	*/
2227	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2228	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2229	}
2230
2231	/*
2232	* Reset (zero) RAM pages.
2233	*/
2234	rc = pgmR3PhysRamReset(pVM);
2235	if (RT_SUCCESS(rc))
2236	{
2237	/*
2238	* Reset (zero) shadow ROM pages.
2239	*/
2240	rc = pgmR3PhysRomReset(pVM);
2241	}
2242
2243	pgmUnlock(pVM);
2244	//return rc;
2245	AssertReleaseRC(rc);
2246	}
2247
2248
2249	#ifdef VBOX_STRICT
2250	/**
2251	* VM state change callback for clearing fNoMorePhysWrites after
2252	* a snapshot has been created.
2253	*/
2254	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2255	{
2256	if (enmState == VMSTATE_RUNNING)
2257	pVM->pgm.s.fNoMorePhysWrites = false;
2258	}
2259	#endif
2260
2261
2262	/**
2263	* Terminates the PGM.
2264	*
2265	* @returns VBox status code.
2266	* @param pVM Pointer to VM structure.
2267	*/
2268	VMMR3DECL(int) PGMR3Term(PVM pVM)
2269	{
2270	PGMDeregisterStringFormatTypes();
2271	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2272	}
2273
2274
2275	/**
2276	* Terminates the per-VCPU PGM.
2277	*
2278	* Termination means cleaning up and freeing all resources,
2279	* the VM it self is at this point powered off or suspended.
2280	*
2281	* @returns VBox status code.
2282	* @param pVM The VM to operate on.
2283	*/
2284	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2285	{
2286	return 0;
2287	}
2288
2289
2290	/**
2291	* Find the ROM tracking structure for the given page.
2292	*
2293	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2294	* that it's a ROM page.
2295	* @param pVM The VM handle.
2296	* @param GCPhys The address of the ROM page.
2297	*/
2298	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2299	{
2300	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2301	pRomRange;
2302	pRomRange = pRomRange->CTX_SUFF(pNext))
2303	{
2304	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2305	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2306	return &pRomRange->aPages[off >> PAGE_SHIFT];
2307	}
2308	return NULL;
2309	}
2310
2311
2312	/**
2313	* Save zero indicator + bits for the specified page.
2314	*
2315	* @returns VBox status code, errors are logged/asserted before returning.
2316	* @param pVM The VM handle.
2317	* @param pSSH The saved state handle.
2318	* @param pPage The page to save.
2319	* @param GCPhys The address of the page.
2320	* @param pRam The ram range (for error logging).
2321	*/
2322	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2323	{
2324	int rc;
2325	if (PGM_PAGE_IS_ZERO(pPage))
2326	rc = SSMR3PutU8(pSSM, 0);
2327	else
2328	{
2329	void const *pvPage;
2330	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2331	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2332
2333	SSMR3PutU8(pSSM, 1);
2334	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2335	}
2336	return rc;
2337	}
2338
2339
2340	/**
2341	* Save a shadowed ROM page.
2342	*
2343	* Format: Type, protection, and two pages with zero indicators.
2344	*
2345	* @returns VBox status code, errors are logged/asserted before returning.
2346	* @param pVM The VM handle.
2347	* @param pSSH The saved state handle.
2348	* @param pPage The page to save.
2349	* @param GCPhys The address of the page.
2350	* @param pRam The ram range (for error logging).
2351	*/
2352	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2353	{
2354	/* Need to save both pages and the current state. */
2355	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2356	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2357
2358	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2359	SSMR3PutU8(pSSM, pRomPage->enmProt);
2360
2361	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2362	if (RT_SUCCESS(rc))
2363	{
2364	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2365	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2366	}
2367	return rc;
2368	}
2369
2370	/** PGM fields to save/load. */
2371	static const SSMFIELD s_aPGMFields[] =
2372	{
2373	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2374	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2375	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2376	SSMFIELD_ENTRY_TERM()
2377	};
2378
2379	static const SSMFIELD s_aPGMCpuFields[] =
2380	{
2381	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2382	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2383	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2384	SSMFIELD_ENTRY_TERM()
2385	};
2386
2387	/* For loading old saved states. (pre-smp) */
2388	typedef struct
2389	{
2390	/** If set no conflict checks are required. (boolean) */
2391	bool fMappingsFixed;
2392	/** Size of fixed mapping */
2393	uint32_t cbMappingFixed;
2394	/** Base address (GC) of fixed mapping */
2395	RTGCPTR GCPtrMappingFixed;
2396	/** A20 gate mask.
2397	* Our current approach to A20 emulation is to let REM do it and don't bother
2398	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2399	* But whould need arrise, we'll subject physical addresses to this mask. */
2400	RTGCPHYS GCPhysA20Mask;
2401	/** A20 gate state - boolean! */
2402	bool fA20Enabled;
2403	/** The guest paging mode. */
2404	PGMMODE enmGuestMode;
2405	} PGMOLD;
2406
2407	static const SSMFIELD s_aPGMFields_Old[] =
2408	{
2409	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2410	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2411	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2412	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2413	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2414	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2415	SSMFIELD_ENTRY_TERM()
2416	};
2417
2418
2419	/**
2420	* Execute state save operation.
2421	*
2422	* @returns VBox status code.
2423	* @param pVM VM Handle.
2424	* @param pSSM SSM operation handle.
2425	*/
2426	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2427	{
2428	int rc;
2429	unsigned i;
2430	PPGM pPGM = &pVM->pgm.s;
2431
2432	/*
2433	* Lock PGM and set the no-more-writes indicator.
2434	*/
2435	pgmLock(pVM);
2436	pVM->pgm.s.fNoMorePhysWrites = true;
2437
2438	/*
2439	* Save basic data (required / unaffected by relocation).
2440	*/
2441	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2442
2443	for (i=0;i<pVM->cCPUs;i++)
2444	{
2445	PVMCPU pVCpu = &pVM->aCpus[i];
2446
2447	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2448	}
2449
2450	/*
2451	* The guest mappings.
2452	*/
2453	i = 0;
2454	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2455	{
2456	SSMR3PutU32( pSSM, i);
2457	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2458	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2459	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2460	}
2461	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2462
2463	/*
2464	* Ram ranges and the memory they describe.
2465	*/
2466	i = 0;
2467	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2468	{
2469	/*
2470	* Save the ram range details.
2471	*/
2472	SSMR3PutU32(pSSM, i);
2473	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2474	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2475	SSMR3PutGCPhys(pSSM, pRam->cb);
2476	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2477	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2478
2479	/*
2480	* Iterate the pages, only two special case.
2481	*/
2482	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2483	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2484	{
2485	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2486	PPGMPAGE pPage = &pRam->aPages[iPage];
2487	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2488
2489	if (uType == PGMPAGETYPE_ROM_SHADOW)
2490	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2491	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2492	{
2493	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2494	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2495	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2496	}
2497	else
2498	{
2499	SSMR3PutU8(pSSM, uType);
2500	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2501	}
2502	if (RT_FAILURE(rc))
2503	break;
2504	}
2505	if (RT_FAILURE(rc))
2506	break;
2507	}
2508
2509	pgmUnlock(pVM);
2510	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2511	}
2512
2513
2514	/**
2515	* Load an ignored page.
2516	*
2517	* @returns VBox status code.
2518	* @param pSSM The saved state handle.
2519	*/
2520	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2521	{
2522	uint8_t abPage[PAGE_SIZE];
2523	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2524	}
2525
2526
2527	/**
2528	* Loads a page without any bits in the saved state, i.e. making sure it's
2529	* really zero.
2530	*
2531	* @returns VBox status code.
2532	* @param pVM The VM handle.
2533	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2534	* state).
2535	* @param pPage The guest page tracking structure.
2536	* @param GCPhys The page address.
2537	* @param pRam The ram range (logging).
2538	*/
2539	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2540	{
2541	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2542	&& uType != PGMPAGETYPE_INVALID)
2543	return VERR_SSM_UNEXPECTED_DATA;
2544
2545	/* I think this should be sufficient. */
2546	if (!PGM_PAGE_IS_ZERO(pPage))
2547	return VERR_SSM_UNEXPECTED_DATA;
2548
2549	NOREF(pVM);
2550	NOREF(GCPhys);
2551	NOREF(pRam);
2552	return VINF_SUCCESS;
2553	}
2554
2555
2556	/**
2557	* Loads a page from the saved state.
2558	*
2559	* @returns VBox status code.
2560	* @param pVM The VM handle.
2561	* @param pSSM The SSM handle.
2562	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2563	* state).
2564	* @param pPage The guest page tracking structure.
2565	* @param GCPhys The page address.
2566	* @param pRam The ram range (logging).
2567	*/
2568	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2569	{
2570	int rc;
2571
2572	/*
2573	* Match up the type, dealing with MMIO2 aliases (dropped).
2574	*/
2575	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2576	\|\| uType == PGMPAGETYPE_INVALID,
2577	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2578	VERR_SSM_UNEXPECTED_DATA);
2579
2580	/*
2581	* Load the page.
2582	*/
2583	void *pvPage;
2584	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2585	if (RT_SUCCESS(rc))
2586	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2587
2588	return rc;
2589	}
2590
2591
2592	/**
2593	* Loads a page (counter part to pgmR3SavePage).
2594	*
2595	* @returns VBox status code, fully bitched errors.
2596	* @param pVM The VM handle.
2597	* @param pSSM The SSM handle.
2598	* @param uType The page type.
2599	* @param pPage The page.
2600	* @param GCPhys The page address.
2601	* @param pRam The RAM range (for error messages).
2602	*/
2603	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2604	{
2605	uint8_t uState;
2606	int rc = SSMR3GetU8(pSSM, &uState);
2607	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2608	if (uState == 0 /* zero */)
2609	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2610	else if (uState == 1)
2611	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2612	else
2613	rc = VERR_INTERNAL_ERROR;
2614	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2615	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2616	rc);
2617	return VINF_SUCCESS;
2618	}
2619
2620
2621	/**
2622	* Loads a shadowed ROM page.
2623	*
2624	* @returns VBox status code, errors are fully bitched.
2625	* @param pVM The VM handle.
2626	* @param pSSM The saved state handle.
2627	* @param pPage The page.
2628	* @param GCPhys The page address.
2629	* @param pRam The RAM range (for error messages).
2630	*/
2631	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2632	{
2633	/*
2634	* Load and set the protection first, then load the two pages, the first
2635	* one is the active the other is the passive.
2636	*/
2637	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2638	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2639
2640	uint8_t uProt;
2641	int rc = SSMR3GetU8(pSSM, &uProt);
2642	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2643	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2644	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2645	&& enmProt < PGMROMPROT_END,
2646	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2647	VERR_SSM_UNEXPECTED_DATA);
2648
2649	if (pRomPage->enmProt != enmProt)
2650	{
2651	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2652	AssertLogRelRCReturn(rc, rc);
2653	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2654	}
2655
2656	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2657	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2658	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2659	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2660
2661	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2662	if (RT_SUCCESS(rc))
2663	{
2664	pPageActive = pPage;
2665	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2666	}
2667	return rc;
2668	}
2669
2670
2671	/**
2672	* Worker for pgmR3Load.
2673	*
2674	* @returns VBox status code.
2675	*
2676	* @param pVM The VM handle.
2677	* @param pSSM The SSM handle.
2678	* @param uVersion The saved state version.
2679	*/
2680	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2681	{
2682	PPGM pPGM = &pVM->pgm.s;
2683	int rc;
2684	uint32_t u32Sep;
2685
2686	/*
2687	* Load basic data (required / unaffected by relocation).
2688	*/
2689	if (uVersion >= PGM_SAVED_STATE_VERSION)
2690	{
2691	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2692	AssertLogRelRCReturn(rc, rc);
2693
2694	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2695	{
2696	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2697	AssertLogRelRCReturn(rc, rc);
2698	}
2699	}
2700	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2701	{
2702	AssertRelease(pVM->cCPUs == 1);
2703
2704	PGMOLD pgmOld;
2705	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2706	AssertLogRelRCReturn(rc, rc);
2707
2708	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2709	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2710	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2711
2712	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2713	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2714	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2715	}
2716	else
2717	{
2718	AssertRelease(pVM->cCPUs == 1);
2719
2720	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2721	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2722	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2723
2724	uint32_t cbRamSizeIgnored;
2725	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2726	if (RT_FAILURE(rc))
2727	return rc;
2728	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2729
2730	uint32_t u32 = 0;
2731	SSMR3GetUInt(pSSM, &u32);
2732	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2733	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2734	RTUINT uGuestMode;
2735	SSMR3GetUInt(pSSM, &uGuestMode);
2736	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2737
2738	/* check separator. */
2739	SSMR3GetU32(pSSM, &u32Sep);
2740	if (RT_FAILURE(rc))
2741	return rc;
2742	if (u32Sep != (uint32_t)~0)
2743	{
2744	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2745	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2746	}
2747	}
2748
2749	/*
2750	* The guest mappings.
2751	*/
2752	uint32_t i = 0;
2753	for (;; i++)
2754	{
2755	/* Check the seqence number / separator. */
2756	rc = SSMR3GetU32(pSSM, &u32Sep);
2757	if (RT_FAILURE(rc))
2758	return rc;
2759	if (u32Sep == ~0U)
2760	break;
2761	if (u32Sep != i)
2762	{
2763	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2764	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2765	}
2766
2767	/* get the mapping details. */
2768	char szDesc[256];
2769	szDesc[0] = '\0';
2770	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2771	if (RT_FAILURE(rc))
2772	return rc;
2773	RTGCPTR GCPtr;
2774	SSMR3GetGCPtr(pSSM, &GCPtr);
2775	RTGCPTR cPTs;
2776	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2777	if (RT_FAILURE(rc))
2778	return rc;
2779
2780	/* find matching range. */
2781	PPGMMAPPING pMapping;
2782	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2783	if ( pMapping->cPTs == cPTs
2784	&& !strcmp(pMapping->pszDesc, szDesc))
2785	break;
2786	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2787	cPTs, szDesc, GCPtr),
2788	VERR_SSM_LOAD_CONFIG_MISMATCH);
2789
2790	/* relocate it. */
2791	if (pMapping->GCPtr != GCPtr)
2792	{
2793	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2794	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2795	}
2796	else
2797	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2798	}
2799
2800	/*
2801	* Ram range flags and bits.
2802	*/
2803	i = 0;
2804	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2805	{
2806	/* Check the seqence number / separator. */
2807	rc = SSMR3GetU32(pSSM, &u32Sep);
2808	if (RT_FAILURE(rc))
2809	return rc;
2810	if (u32Sep == ~0U)
2811	break;
2812	if (u32Sep != i)
2813	{
2814	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2815	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2816	}
2817	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2818
2819	/* Get the range details. */
2820	RTGCPHYS GCPhys;
2821	SSMR3GetGCPhys(pSSM, &GCPhys);
2822	RTGCPHYS GCPhysLast;
2823	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2824	RTGCPHYS cb;
2825	SSMR3GetGCPhys(pSSM, &cb);
2826	uint8_t fHaveBits;
2827	rc = SSMR3GetU8(pSSM, &fHaveBits);
2828	if (RT_FAILURE(rc))
2829	return rc;
2830	if (fHaveBits & ~1)
2831	{
2832	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2833	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2834	}
2835	size_t cchDesc = 0;
2836	char szDesc[256];
2837	szDesc[0] = '\0';
2838	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2839	{
2840	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2841	if (RT_FAILURE(rc))
2842	return rc;
2843	/* Since we've modified the description strings in r45878, only compare
2844	them if the saved state is more recent. */
2845	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2846	cchDesc = strlen(szDesc);
2847	}
2848
2849	/*
2850	* Match it up with the current range.
2851	*
2852	* Note there is a hack for dealing with the high BIOS mapping
2853	* in the old saved state format, this means we might not have
2854	* a 1:1 match on success.
2855	*/
2856	if ( ( GCPhys != pRam->GCPhys
2857	\|\| GCPhysLast != pRam->GCPhysLast
2858	\|\| cb != pRam->cb
2859	\|\| ( cchDesc
2860	&& strcmp(szDesc, pRam->pszDesc)) )
2861	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2862	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2863	\|\| GCPhys != UINT32_C(0xfff80000)
2864	\|\| GCPhysLast != UINT32_C(0xffffffff)
2865	\|\| pRam->GCPhysLast != GCPhysLast
2866	\|\| pRam->GCPhys < GCPhys
2867	\|\| !fHaveBits)
2868	)
2869	{
2870	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2871	"State : %RGp-%RGp %RGp bytes %s %s\n",
2872	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2873	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2874	/*
2875	* If we're loading a state for debugging purpose, don't make a fuss if
2876	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2877	*/
2878	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2879	\|\| GCPhys < 8 * _1M)
2880	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2881
2882	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2883	continue;
2884	}
2885
2886	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2887	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2888	{
2889	/*
2890	* Load the pages one by one.
2891	*/
2892	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2893	{
2894	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2895	PPGMPAGE pPage = &pRam->aPages[iPage];
2896	uint8_t uType;
2897	rc = SSMR3GetU8(pSSM, &uType);
2898	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2899	if (uType == PGMPAGETYPE_ROM_SHADOW)
2900	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2901	else
2902	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2903	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2904	}
2905	}
2906	else
2907	{
2908	/*
2909	* Old format.
2910	*/
2911	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2912
2913	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2914	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2915	uint32_t fFlags = 0;
2916	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2917	{
2918	uint16_t u16Flags;
2919	rc = SSMR3GetU16(pSSM, &u16Flags);
2920	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2921	fFlags \|= u16Flags;
2922	}
2923
2924	/* Load the bits */
2925	if ( !fHaveBits
2926	&& GCPhysLast < UINT32_C(0xe0000000))
2927	{
2928	/*
2929	* Dynamic chunks.
2930	*/
2931	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2932	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2933	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2934	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2935
2936	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2937	{
2938	uint8_t fPresent;
2939	rc = SSMR3GetU8(pSSM, &fPresent);
2940	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2941	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2942	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2943	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2944
2945	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2946	{
2947	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2948	PPGMPAGE pPage = &pRam->aPages[iPage];
2949	if (fPresent)
2950	{
2951	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2952	rc = pgmR3LoadPageToDevNull(pSSM);
2953	else
2954	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2955	}
2956	else
2957	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2958	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2959	}
2960	}
2961	}
2962	else if (pRam->pvR3)
2963	{
2964	/*
2965	* MMIO2.
2966	*/
2967	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2968	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2969	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2970	AssertLogRelMsgReturn(pRam->pvR3,
2971	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2972	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2973
2974	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2975	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2976	}
2977	else if (GCPhysLast < UINT32_C(0xfff80000))
2978	{
2979	/*
2980	* PCI MMIO, no pages saved.
2981	*/
2982	}
2983	else
2984	{
2985	/*
2986	* Load the 0xfff80000..0xffffffff BIOS range.
2987	* It starts with X reserved pages that we have to skip over since
2988	* the RAMRANGE create by the new code won't include those.
2989	*/
2990	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2991	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2992	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2993	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2994	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2995	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2996	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2997
2998	/* Skip wasted reserved pages before the ROM. */
2999	while (GCPhys < pRam->GCPhys)
3000	{
3001	rc = pgmR3LoadPageToDevNull(pSSM);
3002	GCPhys += PAGE_SIZE;
3003	}
3004
3005	/* Load the bios pages. */
3006	cPages = pRam->cb >> PAGE_SHIFT;
3007	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3008	{
3009	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
3010	PPGMPAGE pPage = &pRam->aPages[iPage];
3011
3012	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
3013	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
3014	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3015	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
3016	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
3017	}
3018	}
3019	}
3020	}
3021
3022	return rc;
3023	}
3024
3025
3026	/**
3027	* Execute state load operation.
3028	*
3029	* @returns VBox status code.
3030	* @param pVM VM Handle.
3031	* @param pSSM SSM operation handle.
3032	* @param uVersion Data layout version.
3033	* @param uPhase The data phase.
3034	*/
3035	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase)
3036	{
3037	int rc;
3038	PPGM pPGM = &pVM->pgm.s;
3039	Assert(uPhase == SSM_PHASE_FINAL); NOREF(uPhase);
3040
3041	/*
3042	* Validate version.
3043	*/
3044	if ( uVersion != PGM_SAVED_STATE_VERSION
3045	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3046	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3047	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3048	{
3049	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3050	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3051	}
3052
3053	/*
3054	* Call the reset function to make sure all the memory is cleared.
3055	*/
3056	PGMR3Reset(pVM);
3057
3058	/*
3059	* Do the loading while owning the lock because a bunch of the functions
3060	* we're using requires this.
3061	*/
3062	pgmLock(pVM);
3063	rc = pgmR3LoadLocked(pVM, pSSM, uVersion);
3064	pgmUnlock(pVM);
3065	if (RT_SUCCESS(rc))
3066	{
3067	/*
3068	* We require a full resync now.
3069	*/
3070	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
3071	{
3072	PVMCPU pVCpu = &pVM->aCpus[i];
3073	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3074	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3075
3076	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3077	}
3078
3079	pgmR3HandlerPhysicalUpdateAll(pVM);
3080
3081	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
3082	{
3083	PVMCPU pVCpu = &pVM->aCpus[i];
3084
3085	/*
3086	* Change the paging mode.
3087	*/
3088	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3089
3090	/* Restore pVM->pgm.s.GCPhysCR3. */
3091	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3092	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3093	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3094	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3095	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3096	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3097	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3098	else
3099	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3100	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3101	}
3102	}
3103
3104	return rc;
3105	}
3106
3107
3108	/**
3109	* Show paging mode.
3110	*
3111	* @param pVM VM Handle.
3112	* @param pHlp The info helpers.
3113	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3114	*/
3115	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3116	{
3117	/* digest argument. */
3118	bool fGuest, fShadow, fHost;
3119	if (pszArgs)
3120	pszArgs = RTStrStripL(pszArgs);
3121	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3122	fShadow = fHost = fGuest = true;
3123	else
3124	{
3125	fShadow = fHost = fGuest = false;
3126	if (strstr(pszArgs, "guest"))
3127	fGuest = true;
3128	if (strstr(pszArgs, "shadow"))
3129	fShadow = true;
3130	if (strstr(pszArgs, "host"))
3131	fHost = true;
3132	}
3133
3134	/** @todo SMP support! */
3135	/* print info. */
3136	if (fGuest)
3137	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3138	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3139	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3140	if (fShadow)
3141	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3142	if (fHost)
3143	{
3144	const char *psz;
3145	switch (pVM->pgm.s.enmHostMode)
3146	{
3147	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3148	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3149	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3150	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3151	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3152	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3153	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3154	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3155	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3156	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3157	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3158	default: psz = "unknown"; break;
3159	}
3160	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3161	}
3162	}
3163
3164
3165	/**
3166	* Dump registered MMIO ranges to the log.
3167	*
3168	* @param pVM VM Handle.
3169	* @param pHlp The info helpers.
3170	* @param pszArgs Arguments, ignored.
3171	*/
3172	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3173	{
3174	NOREF(pszArgs);
3175	pHlp->pfnPrintf(pHlp,
3176	"RAM ranges (pVM=%p)\n"
3177	"%.s %.s\n",
3178	pVM,
3179	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3180	sizeof(RTHCPTR) * 2, "pvHC ");
3181
3182	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3183	pHlp->pfnPrintf(pHlp,
3184	"%RGp-%RGp %RHv %s\n",
3185	pCur->GCPhys,
3186	pCur->GCPhysLast,
3187	pCur->pvR3,
3188	pCur->pszDesc);
3189	}
3190
3191	/**
3192	* Dump the page directory to the log.
3193	*
3194	* @param pVM VM Handle.
3195	* @param pHlp The info helpers.
3196	* @param pszArgs Arguments, ignored.
3197	*/
3198	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3199	{
3200	/** @todo SMP support!! */
3201	PVMCPU pVCpu = &pVM->aCpus[0];
3202
3203	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3204	/* Big pages supported? */
3205	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3206
3207	/* Global pages supported? */
3208	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3209
3210	NOREF(pszArgs);
3211
3212	/*
3213	* Get page directory addresses.
3214	*/
3215	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3216	Assert(pPDSrc);
3217	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3218
3219	/*
3220	* Iterate the page directory.
3221	*/
3222	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3223	{
3224	X86PDE PdeSrc = pPDSrc->a[iPD];
3225	if (PdeSrc.n.u1Present)
3226	{
3227	if (PdeSrc.b.u1Size && fPSE)
3228	pHlp->pfnPrintf(pHlp,
3229	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3230	iPD,
3231	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3232	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3233	else
3234	pHlp->pfnPrintf(pHlp,
3235	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3236	iPD,
3237	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3238	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3239	}
3240	}
3241	}
3242
3243
3244	/**
3245	* Service a VMMCALLRING3_PGM_LOCK call.
3246	*
3247	* @returns VBox status code.
3248	* @param pVM The VM handle.
3249	*/
3250	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3251	{
3252	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3253	AssertRC(rc);
3254	return rc;
3255	}
3256
3257
3258	/**
3259	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3260	*
3261	* @returns PGM_TYPE_*.
3262	* @param pgmMode The mode value to convert.
3263	*/
3264	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3265	{
3266	switch (pgmMode)
3267	{
3268	case PGMMODE_REAL: return PGM_TYPE_REAL;
3269	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3270	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3271	case PGMMODE_PAE:
3272	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3273	case PGMMODE_AMD64:
3274	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3275	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3276	case PGMMODE_EPT: return PGM_TYPE_EPT;
3277	default:
3278	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3279	}
3280	}
3281
3282
3283	/**
3284	* Gets the index into the paging mode data array of a SHW+GST mode.
3285	*
3286	* @returns PGM::paPagingData index.
3287	* @param uShwType The shadow paging mode type.
3288	* @param uGstType The guest paging mode type.
3289	*/
3290	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3291	{
3292	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3293	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3294	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3295	+ (uGstType - PGM_TYPE_REAL);
3296	}
3297
3298
3299	/**
3300	* Gets the index into the paging mode data array of a SHW+GST mode.
3301	*
3302	* @returns PGM::paPagingData index.
3303	* @param enmShw The shadow paging mode.
3304	* @param enmGst The guest paging mode.
3305	*/
3306	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3307	{
3308	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3309	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3310	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3311	}
3312
3313
3314	/**
3315	* Calculates the max data index.
3316	* @returns The number of entries in the paging data array.
3317	*/
3318	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3319	{
3320	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3321	}
3322
3323
3324	/**
3325	* Initializes the paging mode data kept in PGM::paModeData.
3326	*
3327	* @param pVM The VM handle.
3328	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3329	* This is used early in the init process to avoid trouble with PDM
3330	* not being initialized yet.
3331	*/
3332	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3333	{
3334	PPGMMODEDATA pModeData;
3335	int rc;
3336
3337	/*
3338	* Allocate the array on the first call.
3339	*/
3340	if (!pVM->pgm.s.paModeData)
3341	{
3342	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3343	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3344	}
3345
3346	/*
3347	* Initialize the array entries.
3348	*/
3349	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3350	pModeData->uShwType = PGM_TYPE_32BIT;
3351	pModeData->uGstType = PGM_TYPE_REAL;
3352	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3354	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3355
3356	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3357	pModeData->uShwType = PGM_TYPE_32BIT;
3358	pModeData->uGstType = PGM_TYPE_PROT;
3359	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3360	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3361	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3362
3363	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3364	pModeData->uShwType = PGM_TYPE_32BIT;
3365	pModeData->uGstType = PGM_TYPE_32BIT;
3366	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3367	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3368	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3369
3370	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3371	pModeData->uShwType = PGM_TYPE_PAE;
3372	pModeData->uGstType = PGM_TYPE_REAL;
3373	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3374	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3375	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3376
3377	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3378	pModeData->uShwType = PGM_TYPE_PAE;
3379	pModeData->uGstType = PGM_TYPE_PROT;
3380	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3381	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3382	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3383
3384	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3385	pModeData->uShwType = PGM_TYPE_PAE;
3386	pModeData->uGstType = PGM_TYPE_32BIT;
3387	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3388	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3389	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3390
3391	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3392	pModeData->uShwType = PGM_TYPE_PAE;
3393	pModeData->uGstType = PGM_TYPE_PAE;
3394	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3395	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3396	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3397
3398	#ifdef VBOX_WITH_64_BITS_GUESTS
3399	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3400	pModeData->uShwType = PGM_TYPE_AMD64;
3401	pModeData->uGstType = PGM_TYPE_AMD64;
3402	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3403	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3404	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3405	#endif
3406
3407	/* The nested paging mode. */
3408	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3409	pModeData->uShwType = PGM_TYPE_NESTED;
3410	pModeData->uGstType = PGM_TYPE_REAL;
3411	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3412	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3413
3414	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3415	pModeData->uShwType = PGM_TYPE_NESTED;
3416	pModeData->uGstType = PGM_TYPE_PROT;
3417	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3418	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3419
3420	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3421	pModeData->uShwType = PGM_TYPE_NESTED;
3422	pModeData->uGstType = PGM_TYPE_32BIT;
3423	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3424	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3425
3426	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3427	pModeData->uShwType = PGM_TYPE_NESTED;
3428	pModeData->uGstType = PGM_TYPE_PAE;
3429	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3430	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3431
3432	#ifdef VBOX_WITH_64_BITS_GUESTS
3433	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3434	pModeData->uShwType = PGM_TYPE_NESTED;
3435	pModeData->uGstType = PGM_TYPE_AMD64;
3436	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3437	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3438	#endif
3439
3440	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3441	switch (pVM->pgm.s.enmHostMode)
3442	{
3443	#if HC_ARCH_BITS == 32
3444	case SUPPAGINGMODE_32_BIT:
3445	case SUPPAGINGMODE_32_BIT_GLOBAL:
3446	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3447	{
3448	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3449	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3450	}
3451	# ifdef VBOX_WITH_64_BITS_GUESTS
3452	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3453	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3454	# endif
3455	break;
3456
3457	case SUPPAGINGMODE_PAE:
3458	case SUPPAGINGMODE_PAE_NX:
3459	case SUPPAGINGMODE_PAE_GLOBAL:
3460	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3461	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3462	{
3463	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3464	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3465	}
3466	# ifdef VBOX_WITH_64_BITS_GUESTS
3467	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3468	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3469	# endif
3470	break;
3471	#endif /* HC_ARCH_BITS == 32 */
3472
3473	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3474	case SUPPAGINGMODE_AMD64:
3475	case SUPPAGINGMODE_AMD64_GLOBAL:
3476	case SUPPAGINGMODE_AMD64_NX:
3477	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3478	# ifdef VBOX_WITH_64_BITS_GUESTS
3479	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3480	# else
3481	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3482	# endif
3483	{
3484	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3485	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3486	}
3487	break;
3488	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3489
3490	default:
3491	AssertFailed();
3492	break;
3493	}
3494
3495	/* Extended paging (EPT) / Intel VT-x */
3496	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3497	pModeData->uShwType = PGM_TYPE_EPT;
3498	pModeData->uGstType = PGM_TYPE_REAL;
3499	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3500	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3501	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3502
3503	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3504	pModeData->uShwType = PGM_TYPE_EPT;
3505	pModeData->uGstType = PGM_TYPE_PROT;
3506	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3507	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3508	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3509
3510	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3511	pModeData->uShwType = PGM_TYPE_EPT;
3512	pModeData->uGstType = PGM_TYPE_32BIT;
3513	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3514	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3515	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3516
3517	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3518	pModeData->uShwType = PGM_TYPE_EPT;
3519	pModeData->uGstType = PGM_TYPE_PAE;
3520	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3521	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3522	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3523
3524	#ifdef VBOX_WITH_64_BITS_GUESTS
3525	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3526	pModeData->uShwType = PGM_TYPE_EPT;
3527	pModeData->uGstType = PGM_TYPE_AMD64;
3528	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3529	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3530	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3531	#endif
3532	return VINF_SUCCESS;
3533	}
3534
3535
3536	/**
3537	* Switch to different (or relocated in the relocate case) mode data.
3538	*
3539	* @param pVM The VM handle.
3540	* @param pVCpu The VMCPU to operate on.
3541	* @param enmShw The the shadow paging mode.
3542	* @param enmGst The the guest paging mode.
3543	*/
3544	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3545	{
3546	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3547
3548	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3549	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3550
3551	/* shadow */
3552	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3553	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3554	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3555	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3556	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3557
3558	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3559	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3560
3561	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3562	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3563
3564
3565	/* guest */
3566	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3567	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3568	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3569	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3570	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3571	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3572	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3573	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3574	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3575	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3576	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3577	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3578
3579	/* both */
3580	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3581	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3582	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3583	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3584	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3585	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3586	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3587	#ifdef VBOX_STRICT
3588	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3589	#endif
3590	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3591	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3592
3593	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3594	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3595	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3596	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3597	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3598	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3599	#ifdef VBOX_STRICT
3600	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3601	#endif
3602	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3603	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3604
3605	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3606	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3607	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3608	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3609	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3610	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3611	#ifdef VBOX_STRICT
3612	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3613	#endif
3614	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3615	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3616	}
3617
3618
3619	/**
3620	* Calculates the shadow paging mode.
3621	*
3622	* @returns The shadow paging mode.
3623	* @param pVM VM handle.
3624	* @param enmGuestMode The guest mode.
3625	* @param enmHostMode The host mode.
3626	* @param enmShadowMode The current shadow mode.
3627	* @param penmSwitcher Where to store the switcher to use.
3628	* VMMSWITCHER_INVALID means no change.
3629	*/
3630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3631	{
3632	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3633	switch (enmGuestMode)
3634	{
3635	/*
3636	* When switching to real or protected mode we don't change
3637	* anything since it's likely that we'll switch back pretty soon.
3638	*
3639	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3640	* and is supposed to determine which shadow paging and switcher to
3641	* use during init.
3642	*/
3643	case PGMMODE_REAL:
3644	case PGMMODE_PROTECTED:
3645	if ( enmShadowMode != PGMMODE_INVALID
3646	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3647	break; /* (no change) */
3648
3649	switch (enmHostMode)
3650	{
3651	case SUPPAGINGMODE_32_BIT:
3652	case SUPPAGINGMODE_32_BIT_GLOBAL:
3653	enmShadowMode = PGMMODE_32_BIT;
3654	enmSwitcher = VMMSWITCHER_32_TO_32;
3655	break;
3656
3657	case SUPPAGINGMODE_PAE:
3658	case SUPPAGINGMODE_PAE_NX:
3659	case SUPPAGINGMODE_PAE_GLOBAL:
3660	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3661	enmShadowMode = PGMMODE_PAE;
3662	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3663	#ifdef DEBUG_bird
3664	if (RTEnvExist("VBOX_32BIT"))
3665	{
3666	enmShadowMode = PGMMODE_32_BIT;
3667	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3668	}
3669	#endif
3670	break;
3671
3672	case SUPPAGINGMODE_AMD64:
3673	case SUPPAGINGMODE_AMD64_GLOBAL:
3674	case SUPPAGINGMODE_AMD64_NX:
3675	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3676	enmShadowMode = PGMMODE_PAE;
3677	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3678	#ifdef DEBUG_bird
3679	if (RTEnvExist("VBOX_32BIT"))
3680	{
3681	enmShadowMode = PGMMODE_32_BIT;
3682	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3683	}
3684	#endif
3685	break;
3686
3687	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3688	}
3689	break;
3690
3691	case PGMMODE_32_BIT:
3692	switch (enmHostMode)
3693	{
3694	case SUPPAGINGMODE_32_BIT:
3695	case SUPPAGINGMODE_32_BIT_GLOBAL:
3696	enmShadowMode = PGMMODE_32_BIT;
3697	enmSwitcher = VMMSWITCHER_32_TO_32;
3698	break;
3699
3700	case SUPPAGINGMODE_PAE:
3701	case SUPPAGINGMODE_PAE_NX:
3702	case SUPPAGINGMODE_PAE_GLOBAL:
3703	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3704	enmShadowMode = PGMMODE_PAE;
3705	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3706	#ifdef DEBUG_bird
3707	if (RTEnvExist("VBOX_32BIT"))
3708	{
3709	enmShadowMode = PGMMODE_32_BIT;
3710	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3711	}
3712	#endif
3713	break;
3714
3715	case SUPPAGINGMODE_AMD64:
3716	case SUPPAGINGMODE_AMD64_GLOBAL:
3717	case SUPPAGINGMODE_AMD64_NX:
3718	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3719	enmShadowMode = PGMMODE_PAE;
3720	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3721	#ifdef DEBUG_bird
3722	if (RTEnvExist("VBOX_32BIT"))
3723	{
3724	enmShadowMode = PGMMODE_32_BIT;
3725	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3726	}
3727	#endif
3728	break;
3729
3730	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3731	}
3732	break;
3733
3734	case PGMMODE_PAE:
3735	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3736	switch (enmHostMode)
3737	{
3738	case SUPPAGINGMODE_32_BIT:
3739	case SUPPAGINGMODE_32_BIT_GLOBAL:
3740	enmShadowMode = PGMMODE_PAE;
3741	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3742	break;
3743
3744	case SUPPAGINGMODE_PAE:
3745	case SUPPAGINGMODE_PAE_NX:
3746	case SUPPAGINGMODE_PAE_GLOBAL:
3747	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3748	enmShadowMode = PGMMODE_PAE;
3749	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3750	break;
3751
3752	case SUPPAGINGMODE_AMD64:
3753	case SUPPAGINGMODE_AMD64_GLOBAL:
3754	case SUPPAGINGMODE_AMD64_NX:
3755	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3756	enmShadowMode = PGMMODE_PAE;
3757	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3758	break;
3759
3760	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3761	}
3762	break;
3763
3764	case PGMMODE_AMD64:
3765	case PGMMODE_AMD64_NX:
3766	switch (enmHostMode)
3767	{
3768	case SUPPAGINGMODE_32_BIT:
3769	case SUPPAGINGMODE_32_BIT_GLOBAL:
3770	enmShadowMode = PGMMODE_AMD64;
3771	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3772	break;
3773
3774	case SUPPAGINGMODE_PAE:
3775	case SUPPAGINGMODE_PAE_NX:
3776	case SUPPAGINGMODE_PAE_GLOBAL:
3777	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3778	enmShadowMode = PGMMODE_AMD64;
3779	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3780	break;
3781
3782	case SUPPAGINGMODE_AMD64:
3783	case SUPPAGINGMODE_AMD64_GLOBAL:
3784	case SUPPAGINGMODE_AMD64_NX:
3785	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3786	enmShadowMode = PGMMODE_AMD64;
3787	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3788	break;
3789
3790	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3791	}
3792	break;
3793
3794
3795	default:
3796	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3797	return PGMMODE_INVALID;
3798	}
3799	/* Override the shadow mode is nested paging is active. */
3800	if (HWACCMIsNestedPagingActive(pVM))
3801	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3802
3803	*penmSwitcher = enmSwitcher;
3804	return enmShadowMode;
3805	}
3806
3807
3808	/**
3809	* Performs the actual mode change.
3810	* This is called by PGMChangeMode and pgmR3InitPaging().
3811	*
3812	* @returns VBox status code. May suspend or power off the VM on error, but this
3813	* will trigger using FFs and not status codes.
3814	*
3815	* @param pVM VM handle.
3816	* @param pVCpu The VMCPU to operate on.
3817	* @param enmGuestMode The new guest mode. This is assumed to be different from
3818	* the current mode.
3819	*/
3820	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3821	{
3822	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3823	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3824
3825	/*
3826	* Calc the shadow mode and switcher.
3827	*/
3828	VMMSWITCHER enmSwitcher;
3829	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3830	if (enmSwitcher != VMMSWITCHER_INVALID)
3831	{
3832	/*
3833	* Select new switcher.
3834	*/
3835	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3836	if (RT_FAILURE(rc))
3837	{
3838	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3839	return rc;
3840	}
3841	}
3842
3843	/*
3844	* Exit old mode(s).
3845	*/
3846	/* shadow */
3847	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3848	{
3849	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3850	if (PGM_SHW_PFN(Exit, pVCpu))
3851	{
3852	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3853	if (RT_FAILURE(rc))
3854	{
3855	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3856	return rc;
3857	}
3858	}
3859
3860	}
3861	else
3862	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3863
3864	/* guest */
3865	if (PGM_GST_PFN(Exit, pVCpu))
3866	{
3867	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3868	if (RT_FAILURE(rc))
3869	{
3870	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3871	return rc;
3872	}
3873	}
3874
3875	/*
3876	* Load new paging mode data.
3877	*/
3878	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3879
3880	/*
3881	* Enter new shadow mode (if changed).
3882	*/
3883	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3884	{
3885	int rc;
3886	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3887	switch (enmShadowMode)
3888	{
3889	case PGMMODE_32_BIT:
3890	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3891	break;
3892	case PGMMODE_PAE:
3893	case PGMMODE_PAE_NX:
3894	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3895	break;
3896	case PGMMODE_AMD64:
3897	case PGMMODE_AMD64_NX:
3898	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3899	break;
3900	case PGMMODE_NESTED:
3901	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3902	break;
3903	case PGMMODE_EPT:
3904	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3905	break;
3906	case PGMMODE_REAL:
3907	case PGMMODE_PROTECTED:
3908	default:
3909	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3910	return VERR_INTERNAL_ERROR;
3911	}
3912	if (RT_FAILURE(rc))
3913	{
3914	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3915	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3916	return rc;
3917	}
3918	}
3919
3920	/*
3921	* Always flag the necessary updates
3922	*/
3923	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3924
3925	/*
3926	* Enter the new guest and shadow+guest modes.
3927	*/
3928	int rc = -1;
3929	int rc2 = -1;
3930	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3931	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3932	switch (enmGuestMode)
3933	{
3934	case PGMMODE_REAL:
3935	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3936	switch (pVCpu->pgm.s.enmShadowMode)
3937	{
3938	case PGMMODE_32_BIT:
3939	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3940	break;
3941	case PGMMODE_PAE:
3942	case PGMMODE_PAE_NX:
3943	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3944	break;
3945	case PGMMODE_NESTED:
3946	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3947	break;
3948	case PGMMODE_EPT:
3949	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3950	break;
3951	case PGMMODE_AMD64:
3952	case PGMMODE_AMD64_NX:
3953	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3954	default: AssertFailed(); break;
3955	}
3956	break;
3957
3958	case PGMMODE_PROTECTED:
3959	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3960	switch (pVCpu->pgm.s.enmShadowMode)
3961	{
3962	case PGMMODE_32_BIT:
3963	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3964	break;
3965	case PGMMODE_PAE:
3966	case PGMMODE_PAE_NX:
3967	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3968	break;
3969	case PGMMODE_NESTED:
3970	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3971	break;
3972	case PGMMODE_EPT:
3973	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3974	break;
3975	case PGMMODE_AMD64:
3976	case PGMMODE_AMD64_NX:
3977	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3978	default: AssertFailed(); break;
3979	}
3980	break;
3981
3982	case PGMMODE_32_BIT:
3983	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3984	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3985	switch (pVCpu->pgm.s.enmShadowMode)
3986	{
3987	case PGMMODE_32_BIT:
3988	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3989	break;
3990	case PGMMODE_PAE:
3991	case PGMMODE_PAE_NX:
3992	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3993	break;
3994	case PGMMODE_NESTED:
3995	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3996	break;
3997	case PGMMODE_EPT:
3998	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3999	break;
4000	case PGMMODE_AMD64:
4001	case PGMMODE_AMD64_NX:
4002	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4003	default: AssertFailed(); break;
4004	}
4005	break;
4006
4007	case PGMMODE_PAE_NX:
4008	case PGMMODE_PAE:
4009	{
4010	uint32_t u32Dummy, u32Features;
4011
4012	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
4013	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
4014	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
4015	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
4016
4017	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
4018	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
4019	switch (pVCpu->pgm.s.enmShadowMode)
4020	{
4021	case PGMMODE_PAE:
4022	case PGMMODE_PAE_NX:
4023	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4024	break;
4025	case PGMMODE_NESTED:
4026	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4027	break;
4028	case PGMMODE_EPT:
4029	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4030	break;
4031	case PGMMODE_32_BIT:
4032	case PGMMODE_AMD64:
4033	case PGMMODE_AMD64_NX:
4034	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4035	default: AssertFailed(); break;
4036	}
4037	break;
4038	}
4039
4040	#ifdef VBOX_WITH_64_BITS_GUESTS
4041	case PGMMODE_AMD64_NX:
4042	case PGMMODE_AMD64:
4043	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4044	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4045	switch (pVCpu->pgm.s.enmShadowMode)
4046	{
4047	case PGMMODE_AMD64:
4048	case PGMMODE_AMD64_NX:
4049	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4050	break;
4051	case PGMMODE_NESTED:
4052	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4053	break;
4054	case PGMMODE_EPT:
4055	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4056	break;
4057	case PGMMODE_32_BIT:
4058	case PGMMODE_PAE:
4059	case PGMMODE_PAE_NX:
4060	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4061	default: AssertFailed(); break;
4062	}
4063	break;
4064	#endif
4065
4066	default:
4067	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4068	rc = VERR_NOT_IMPLEMENTED;
4069	break;
4070	}
4071
4072	/* status codes. */
4073	AssertRC(rc);
4074	AssertRC(rc2);
4075	if (RT_SUCCESS(rc))
4076	{
4077	rc = rc2;
4078	if (RT_SUCCESS(rc)) /* no informational status codes. */
4079	rc = VINF_SUCCESS;
4080	}
4081
4082	/* Notify HWACCM as well. */
4083	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4084	return rc;
4085	}
4086
4087	/**
4088	* Release the pgm lock if owned by the current VCPU
4089	*
4090	* @param pVM The VM to operate on.
4091	*/
4092	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4093	{
4094	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4095	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4096	}
4097
4098	/**
4099	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4100	*
4101	* @returns VBox status code, fully asserted.
4102	* @param pVM The VM handle.
4103	* @param pVCpu The VMCPU to operate on.
4104	*/
4105	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4106	{
4107	/* Unmap the old CR3 value before flushing everything. */
4108	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4109	AssertRC(rc);
4110
4111	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4112	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4113	AssertRC(rc);
4114	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4115	return rc;
4116	}
4117
4118
4119	/**
4120	* Called by pgmPoolFlushAllInt after flushing the pool.
4121	*
4122	* @returns VBox status code, fully asserted.
4123	* @param pVM The VM handle.
4124	* @param pVCpu The VMCPU to operate on.
4125	*/
4126	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4127	{
4128	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4129	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4130	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4131	AssertRCReturn(rc, rc);
4132	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4133
4134	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4135	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4136	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4137	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4138	return rc;
4139	}
4140
4141
4142	/**
4143	* Dumps a PAE shadow page table.
4144	*
4145	* @returns VBox status code (VINF_SUCCESS).
4146	* @param pVM The VM handle.
4147	* @param pPT Pointer to the page table.
4148	* @param u64Address The virtual address of the page table starts.
4149	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4150	* @param cMaxDepth The maxium depth.
4151	* @param pHlp Pointer to the output functions.
4152	*/
4153	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4154	{
4155	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4156	{
4157	X86PTEPAE Pte = pPT->a[i];
4158	if (Pte.n.u1Present)
4159	{
4160	pHlp->pfnPrintf(pHlp,
4161	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4162	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4163	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4164	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4165	Pte.n.u1Write ? 'W' : 'R',
4166	Pte.n.u1User ? 'U' : 'S',
4167	Pte.n.u1Accessed ? 'A' : '-',
4168	Pte.n.u1Dirty ? 'D' : '-',
4169	Pte.n.u1Global ? 'G' : '-',
4170	Pte.n.u1WriteThru ? "WT" : "--",
4171	Pte.n.u1CacheDisable? "CD" : "--",
4172	Pte.n.u1PAT ? "AT" : "--",
4173	Pte.n.u1NoExecute ? "NX" : "--",
4174	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4175	Pte.u & RT_BIT(10) ? '1' : '0',
4176	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4177	Pte.u & X86_PTE_PAE_PG_MASK);
4178	}
4179	}
4180	return VINF_SUCCESS;
4181	}
4182
4183
4184	/**
4185	* Dumps a PAE shadow page directory table.
4186	*
4187	* @returns VBox status code (VINF_SUCCESS).
4188	* @param pVM The VM handle.
4189	* @param HCPhys The physical address of the page directory table.
4190	* @param u64Address The virtual address of the page table starts.
4191	* @param cr4 The CR4, PSE is currently used.
4192	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4193	* @param cMaxDepth The maxium depth.
4194	* @param pHlp Pointer to the output functions.
4195	*/
4196	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4197	{
4198	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4199	if (!pPD)
4200	{
4201	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4202	fLongMode ? 16 : 8, u64Address, HCPhys);
4203	return VERR_INVALID_PARAMETER;
4204	}
4205	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4206
4207	int rc = VINF_SUCCESS;
4208	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4209	{
4210	X86PDEPAE Pde = pPD->a[i];
4211	if (Pde.n.u1Present)
4212	{
4213	if (fBigPagesSupported && Pde.b.u1Size)
4214	pHlp->pfnPrintf(pHlp,
4215	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4216	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4217	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4218	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4219	Pde.b.u1Write ? 'W' : 'R',
4220	Pde.b.u1User ? 'U' : 'S',
4221	Pde.b.u1Accessed ? 'A' : '-',
4222	Pde.b.u1Dirty ? 'D' : '-',
4223	Pde.b.u1Global ? 'G' : '-',
4224	Pde.b.u1WriteThru ? "WT" : "--",
4225	Pde.b.u1CacheDisable? "CD" : "--",
4226	Pde.b.u1PAT ? "AT" : "--",
4227	Pde.b.u1NoExecute ? "NX" : "--",
4228	Pde.u & RT_BIT_64(9) ? '1' : '0',
4229	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4230	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4231	Pde.u & X86_PDE_PAE_PG_MASK);
4232	else
4233	{
4234	pHlp->pfnPrintf(pHlp,
4235	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4236	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4237	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4238	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4239	Pde.n.u1Write ? 'W' : 'R',
4240	Pde.n.u1User ? 'U' : 'S',
4241	Pde.n.u1Accessed ? 'A' : '-',
4242	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4243	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4244	Pde.n.u1WriteThru ? "WT" : "--",
4245	Pde.n.u1CacheDisable? "CD" : "--",
4246	Pde.n.u1NoExecute ? "NX" : "--",
4247	Pde.u & RT_BIT_64(9) ? '1' : '0',
4248	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4249	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4250	Pde.u & X86_PDE_PAE_PG_MASK);
4251	if (cMaxDepth >= 1)
4252	{
4253	/** @todo what about using the page pool for mapping PTs? */
4254	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4255	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4256	PX86PTPAE pPT = NULL;
4257	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4258	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4259	else
4260	{
4261	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4262	{
4263	uint64_t off = u64AddressPT - pMap->GCPtr;
4264	if (off < pMap->cb)
4265	{
4266	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4267	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4268	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4269	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4270	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4271	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4272	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4273	}
4274	}
4275	}
4276	int rc2 = VERR_INVALID_PARAMETER;
4277	if (pPT)
4278	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4279	else
4280	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4281	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4282	if (rc2 < rc && RT_SUCCESS(rc))
4283	rc = rc2;
4284	}
4285	}
4286	}
4287	}
4288	return rc;
4289	}
4290
4291
4292	/**
4293	* Dumps a PAE shadow page directory pointer table.
4294	*
4295	* @returns VBox status code (VINF_SUCCESS).
4296	* @param pVM The VM handle.
4297	* @param HCPhys The physical address of the page directory pointer table.
4298	* @param u64Address The virtual address of the page table starts.
4299	* @param cr4 The CR4, PSE is currently used.
4300	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4301	* @param cMaxDepth The maxium depth.
4302	* @param pHlp Pointer to the output functions.
4303	*/
4304	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4305	{
4306	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4307	if (!pPDPT)
4308	{
4309	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4310	fLongMode ? 16 : 8, u64Address, HCPhys);
4311	return VERR_INVALID_PARAMETER;
4312	}
4313
4314	int rc = VINF_SUCCESS;
4315	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4316	for (unsigned i = 0; i < c; i++)
4317	{
4318	X86PDPE Pdpe = pPDPT->a[i];
4319	if (Pdpe.n.u1Present)
4320	{
4321	if (fLongMode)
4322	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4323	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4324	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4325	Pdpe.lm.u1Write ? 'W' : 'R',
4326	Pdpe.lm.u1User ? 'U' : 'S',
4327	Pdpe.lm.u1Accessed ? 'A' : '-',
4328	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4329	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4330	Pdpe.lm.u1WriteThru ? "WT" : "--",
4331	Pdpe.lm.u1CacheDisable? "CD" : "--",
4332	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4333	Pdpe.lm.u1NoExecute ? "NX" : "--",
4334	Pdpe.u & RT_BIT(9) ? '1' : '0',
4335	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4336	Pdpe.u & RT_BIT(11) ? '1' : '0',
4337	Pdpe.u & X86_PDPE_PG_MASK);
4338	else
4339	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4340	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4341	i << X86_PDPT_SHIFT,
4342	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4343	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4344	Pdpe.n.u1WriteThru ? "WT" : "--",
4345	Pdpe.n.u1CacheDisable? "CD" : "--",
4346	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4347	Pdpe.u & RT_BIT(9) ? '1' : '0',
4348	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4349	Pdpe.u & RT_BIT(11) ? '1' : '0',
4350	Pdpe.u & X86_PDPE_PG_MASK);
4351	if (cMaxDepth >= 1)
4352	{
4353	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4354	cr4, fLongMode, cMaxDepth - 1, pHlp);
4355	if (rc2 < rc && RT_SUCCESS(rc))
4356	rc = rc2;
4357	}
4358	}
4359	}
4360	return rc;
4361	}
4362
4363
4364	/**
4365	* Dumps a 32-bit shadow page table.
4366	*
4367	* @returns VBox status code (VINF_SUCCESS).
4368	* @param pVM The VM handle.
4369	* @param HCPhys The physical address of the table.
4370	* @param cr4 The CR4, PSE is currently used.
4371	* @param cMaxDepth The maxium depth.
4372	* @param pHlp Pointer to the output functions.
4373	*/
4374	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4375	{
4376	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4377	if (!pPML4)
4378	{
4379	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4380	return VERR_INVALID_PARAMETER;
4381	}
4382
4383	int rc = VINF_SUCCESS;
4384	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4385	{
4386	X86PML4E Pml4e = pPML4->a[i];
4387	if (Pml4e.n.u1Present)
4388	{
4389	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4390	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4391	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4392	u64Address,
4393	Pml4e.n.u1Write ? 'W' : 'R',
4394	Pml4e.n.u1User ? 'U' : 'S',
4395	Pml4e.n.u1Accessed ? 'A' : '-',
4396	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4397	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4398	Pml4e.n.u1WriteThru ? "WT" : "--",
4399	Pml4e.n.u1CacheDisable? "CD" : "--",
4400	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4401	Pml4e.n.u1NoExecute ? "NX" : "--",
4402	Pml4e.u & RT_BIT(9) ? '1' : '0',
4403	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4404	Pml4e.u & RT_BIT(11) ? '1' : '0',
4405	Pml4e.u & X86_PML4E_PG_MASK);
4406
4407	if (cMaxDepth >= 1)
4408	{
4409	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4410	if (rc2 < rc && RT_SUCCESS(rc))
4411	rc = rc2;
4412	}
4413	}
4414	}
4415	return rc;
4416	}
4417
4418
4419	/**
4420	* Dumps a 32-bit shadow page table.
4421	*
4422	* @returns VBox status code (VINF_SUCCESS).
4423	* @param pVM The VM handle.
4424	* @param pPT Pointer to the page table.
4425	* @param u32Address The virtual address this table starts at.
4426	* @param pHlp Pointer to the output functions.
4427	*/
4428	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4429	{
4430	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4431	{
4432	X86PTE Pte = pPT->a[i];
4433	if (Pte.n.u1Present)
4434	{
4435	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4436	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4437	u32Address + (i << X86_PT_SHIFT),
4438	Pte.n.u1Write ? 'W' : 'R',
4439	Pte.n.u1User ? 'U' : 'S',
4440	Pte.n.u1Accessed ? 'A' : '-',
4441	Pte.n.u1Dirty ? 'D' : '-',
4442	Pte.n.u1Global ? 'G' : '-',
4443	Pte.n.u1WriteThru ? "WT" : "--",
4444	Pte.n.u1CacheDisable? "CD" : "--",
4445	Pte.n.u1PAT ? "AT" : "--",
4446	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4447	Pte.u & RT_BIT(10) ? '1' : '0',
4448	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4449	Pte.u & X86_PDE_PG_MASK);
4450	}
4451	}
4452	return VINF_SUCCESS;
4453	}
4454
4455
4456	/**
4457	* Dumps a 32-bit shadow page directory and page tables.
4458	*
4459	* @returns VBox status code (VINF_SUCCESS).
4460	* @param pVM The VM handle.
4461	* @param cr3 The root of the hierarchy.
4462	* @param cr4 The CR4, PSE is currently used.
4463	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4464	* @param pHlp Pointer to the output functions.
4465	*/
4466	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4467	{
4468	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4469	if (!pPD)
4470	{
4471	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4472	return VERR_INVALID_PARAMETER;
4473	}
4474
4475	int rc = VINF_SUCCESS;
4476	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4477	{
4478	X86PDE Pde = pPD->a[i];
4479	if (Pde.n.u1Present)
4480	{
4481	const uint32_t u32Address = i << X86_PD_SHIFT;
4482	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4483	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4484	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4485	u32Address,
4486	Pde.b.u1Write ? 'W' : 'R',
4487	Pde.b.u1User ? 'U' : 'S',
4488	Pde.b.u1Accessed ? 'A' : '-',
4489	Pde.b.u1Dirty ? 'D' : '-',
4490	Pde.b.u1Global ? 'G' : '-',
4491	Pde.b.u1WriteThru ? "WT" : "--",
4492	Pde.b.u1CacheDisable? "CD" : "--",
4493	Pde.b.u1PAT ? "AT" : "--",
4494	Pde.u & RT_BIT_64(9) ? '1' : '0',
4495	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4496	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4497	Pde.u & X86_PDE4M_PG_MASK);
4498	else
4499	{
4500	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4501	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4502	u32Address,
4503	Pde.n.u1Write ? 'W' : 'R',
4504	Pde.n.u1User ? 'U' : 'S',
4505	Pde.n.u1Accessed ? 'A' : '-',
4506	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4507	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4508	Pde.n.u1WriteThru ? "WT" : "--",
4509	Pde.n.u1CacheDisable? "CD" : "--",
4510	Pde.u & RT_BIT_64(9) ? '1' : '0',
4511	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4512	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4513	Pde.u & X86_PDE_PG_MASK);
4514	if (cMaxDepth >= 1)
4515	{
4516	/** @todo what about using the page pool for mapping PTs? */
4517	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4518	PX86PT pPT = NULL;
4519	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4520	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4521	else
4522	{
4523	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4524	if (u32Address - pMap->GCPtr < pMap->cb)
4525	{
4526	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4527	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4528	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4529	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4530	pPT = pMap->aPTs[iPDE].pPTR3;
4531	}
4532	}
4533	int rc2 = VERR_INVALID_PARAMETER;
4534	if (pPT)
4535	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4536	else
4537	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4538	if (rc2 < rc && RT_SUCCESS(rc))
4539	rc = rc2;
4540	}
4541	}
4542	}
4543	}
4544
4545	return rc;
4546	}
4547
4548
4549	/**
4550	* Dumps a 32-bit shadow page table.
4551	*
4552	* @returns VBox status code (VINF_SUCCESS).
4553	* @param pVM The VM handle.
4554	* @param pPT Pointer to the page table.
4555	* @param u32Address The virtual address this table starts at.
4556	* @param PhysSearch Address to search for.
4557	*/
4558	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4559	{
4560	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4561	{
4562	X86PTE Pte = pPT->a[i];
4563	if (Pte.n.u1Present)
4564	{
4565	Log(( /P R S A D G WT CD AT NX 4M a m d /
4566	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4567	u32Address + (i << X86_PT_SHIFT),
4568	Pte.n.u1Write ? 'W' : 'R',
4569	Pte.n.u1User ? 'U' : 'S',
4570	Pte.n.u1Accessed ? 'A' : '-',
4571	Pte.n.u1Dirty ? 'D' : '-',
4572	Pte.n.u1Global ? 'G' : '-',
4573	Pte.n.u1WriteThru ? "WT" : "--",
4574	Pte.n.u1CacheDisable? "CD" : "--",
4575	Pte.n.u1PAT ? "AT" : "--",
4576	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4577	Pte.u & RT_BIT(10) ? '1' : '0',
4578	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4579	Pte.u & X86_PDE_PG_MASK));
4580
4581	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4582	{
4583	uint64_t fPageShw = 0;
4584	RTHCPHYS pPhysHC = 0;
4585
4586	/** @todo SMP support!! */
4587	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4588	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4589	}
4590	}
4591	}
4592	return VINF_SUCCESS;
4593	}
4594
4595
4596	/**
4597	* Dumps a 32-bit guest page directory and page tables.
4598	*
4599	* @returns VBox status code (VINF_SUCCESS).
4600	* @param pVM The VM handle.
4601	* @param cr3 The root of the hierarchy.
4602	* @param cr4 The CR4, PSE is currently used.
4603	* @param PhysSearch Address to search for.
4604	*/
4605	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4606	{
4607	bool fLongMode = false;
4608	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4609	PX86PD pPD = 0;
4610
4611	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4612	if (RT_FAILURE(rc) \|\| !pPD)
4613	{
4614	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4615	return VERR_INVALID_PARAMETER;
4616	}
4617
4618	Log(("cr3=%08x cr4=%08x%s\n"
4619	"%-*s P - Present\n"
4620	"%-*s \| R/W - Read (0) / Write (1)\n"
4621	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4622	"%-*s \| \| \| A - Accessed\n"
4623	"%-*s \| \| \| \| D - Dirty\n"
4624	"%-*s \| \| \| \| \| G - Global\n"
4625	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4626	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4627	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4628	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4629	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4630	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4631	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4632	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4633	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4634	- W U - - - -- -- -- -- -- 010 */
4635	, cr3, cr4, fLongMode ? " Long Mode" : "",
4636	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4637	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4638
4639	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4640	{
4641	X86PDE Pde = pPD->a[i];
4642	if (Pde.n.u1Present)
4643	{
4644	const uint32_t u32Address = i << X86_PD_SHIFT;
4645
4646	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4647	Log(( /P R S A D G WT CD AT NX 4M a m d /
4648	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4649	u32Address,
4650	Pde.b.u1Write ? 'W' : 'R',
4651	Pde.b.u1User ? 'U' : 'S',
4652	Pde.b.u1Accessed ? 'A' : '-',
4653	Pde.b.u1Dirty ? 'D' : '-',
4654	Pde.b.u1Global ? 'G' : '-',
4655	Pde.b.u1WriteThru ? "WT" : "--",
4656	Pde.b.u1CacheDisable? "CD" : "--",
4657	Pde.b.u1PAT ? "AT" : "--",
4658	Pde.u & RT_BIT(9) ? '1' : '0',
4659	Pde.u & RT_BIT(10) ? '1' : '0',
4660	Pde.u & RT_BIT(11) ? '1' : '0',
4661	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4662	/** @todo PhysSearch */
4663	else
4664	{
4665	Log(( /P R S A D G WT CD AT NX 4M a m d /
4666	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4667	u32Address,
4668	Pde.n.u1Write ? 'W' : 'R',
4669	Pde.n.u1User ? 'U' : 'S',
4670	Pde.n.u1Accessed ? 'A' : '-',
4671	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4672	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4673	Pde.n.u1WriteThru ? "WT" : "--",
4674	Pde.n.u1CacheDisable? "CD" : "--",
4675	Pde.u & RT_BIT(9) ? '1' : '0',
4676	Pde.u & RT_BIT(10) ? '1' : '0',
4677	Pde.u & RT_BIT(11) ? '1' : '0',
4678	Pde.u & X86_PDE_PG_MASK));
4679	////if (cMaxDepth >= 1)
4680	{
4681	/** @todo what about using the page pool for mapping PTs? */
4682	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4683	PX86PT pPT = NULL;
4684
4685	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4686
4687	int rc2 = VERR_INVALID_PARAMETER;
4688	if (pPT)
4689	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4690	else
4691	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4692	if (rc2 < rc && RT_SUCCESS(rc))
4693	rc = rc2;
4694	}
4695	}
4696	}
4697	}
4698
4699	return rc;
4700	}
4701
4702
4703	/**
4704	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4705	*
4706	* @returns VBox status code (VINF_SUCCESS).
4707	* @param pVM The VM handle.
4708	* @param cr3 The root of the hierarchy.
4709	* @param cr4 The cr4, only PAE and PSE is currently used.
4710	* @param fLongMode Set if long mode, false if not long mode.
4711	* @param cMaxDepth Number of levels to dump.
4712	* @param pHlp Pointer to the output functions.
4713	*/
4714	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4715	{
4716	if (!pHlp)
4717	pHlp = DBGFR3InfoLogHlp();
4718	if (!cMaxDepth)
4719	return VINF_SUCCESS;
4720	const unsigned cch = fLongMode ? 16 : 8;
4721	pHlp->pfnPrintf(pHlp,
4722	"cr3=%08x cr4=%08x%s\n"
4723	"%-*s P - Present\n"
4724	"%-*s \| R/W - Read (0) / Write (1)\n"
4725	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4726	"%-*s \| \| \| A - Accessed\n"
4727	"%-*s \| \| \| \| D - Dirty\n"
4728	"%-*s \| \| \| \| \| G - Global\n"
4729	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4730	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4731	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4732	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4733	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4734	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4735	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4736	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4737	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4738	- W U - - - -- -- -- -- -- 010 */
4739	, cr3, cr4, fLongMode ? " Long Mode" : "",
4740	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4741	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4742	if (cr4 & X86_CR4_PAE)
4743	{
4744	if (fLongMode)
4745	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4746	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4747	}
4748	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4749	}
4750
4751	#ifdef VBOX_WITH_DEBUGGER
4752
4753	/**
4754	* The '.pgmram' command.
4755	*
4756	* @returns VBox status.
4757	* @param pCmd Pointer to the command descriptor (as registered).
4758	* @param pCmdHlp Pointer to command helper functions.
4759	* @param pVM Pointer to the current VM (if any).
4760	* @param paArgs Pointer to (readonly) array of arguments.
4761	* @param cArgs Number of arguments in the array.
4762	*/
4763	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4764	{
4765	/*
4766	* Validate input.
4767	*/
4768	if (!pVM)
4769	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4770	if (!pVM->pgm.s.pRamRangesRC)
4771	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4772
4773	/*
4774	* Dump the ranges.
4775	*/
4776	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4777	PPGMRAMRANGE pRam;
4778	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4779	{
4780	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4781	"%RGp - %RGp %p\n",
4782	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4783	if (RT_FAILURE(rc))
4784	return rc;
4785	}
4786
4787	return VINF_SUCCESS;
4788	}
4789
4790
4791	/**
4792	* The '.pgmmap' command.
4793	*
4794	* @returns VBox status.
4795	* @param pCmd Pointer to the command descriptor (as registered).
4796	* @param pCmdHlp Pointer to command helper functions.
4797	* @param pVM Pointer to the current VM (if any).
4798	* @param paArgs Pointer to (readonly) array of arguments.
4799	* @param cArgs Number of arguments in the array.
4800	*/
4801	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4802	{
4803	/*
4804	* Validate input.
4805	*/
4806	if (!pVM)
4807	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4808	if (!pVM->pgm.s.pMappingsR3)
4809	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4810
4811	/*
4812	* Print message about the fixedness of the mappings.
4813	*/
4814	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4815	if (RT_FAILURE(rc))
4816	return rc;
4817
4818	/*
4819	* Dump the ranges.
4820	*/
4821	PPGMMAPPING pCur;
4822	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4823	{
4824	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4825	"%08x - %08x %s\n",
4826	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4827	if (RT_FAILURE(rc))
4828	return rc;
4829	}
4830
4831	return VINF_SUCCESS;
4832	}
4833
4834
4835	/**
4836	* The '.pgmerror' and '.pgmerroroff' commands.
4837	*
4838	* @returns VBox status.
4839	* @param pCmd Pointer to the command descriptor (as registered).
4840	* @param pCmdHlp Pointer to command helper functions.
4841	* @param pVM Pointer to the current VM (if any).
4842	* @param paArgs Pointer to (readonly) array of arguments.
4843	* @param cArgs Number of arguments in the array.
4844	*/
4845	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4846	{
4847	/*
4848	* Validate input.
4849	*/
4850	if (!pVM)
4851	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4852	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4853	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4854
4855	if (!cArgs)
4856	{
4857	/*
4858	* Print the list of error injection locations with status.
4859	*/
4860	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4861	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4862	}
4863	else
4864	{
4865
4866	/*
4867	* String switch on where to inject the error.
4868	*/
4869	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4870	const char *pszWhere = paArgs[0].u.pszString;
4871	if (!strcmp(pszWhere, "handy"))
4872	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4873	else
4874	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4875	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4876	}
4877	return VINF_SUCCESS;
4878	}
4879
4880
4881	/**
4882	* The '.pgmsync' command.
4883	*
4884	* @returns VBox status.
4885	* @param pCmd Pointer to the command descriptor (as registered).
4886	* @param pCmdHlp Pointer to command helper functions.
4887	* @param pVM Pointer to the current VM (if any).
4888	* @param paArgs Pointer to (readonly) array of arguments.
4889	* @param cArgs Number of arguments in the array.
4890	*/
4891	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4892	{
4893	/** @todo SMP support */
4894	PVMCPU pVCpu = &pVM->aCpus[0];
4895
4896	/*
4897	* Validate input.
4898	*/
4899	if (!pVM)
4900	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4901
4902	/*
4903	* Force page directory sync.
4904	*/
4905	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4906
4907	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4908	if (RT_FAILURE(rc))
4909	return rc;
4910
4911	return VINF_SUCCESS;
4912	}
4913
4914
4915	#ifdef VBOX_STRICT
4916	/**
4917	* The '.pgmassertcr3' command.
4918	*
4919	* @returns VBox status.
4920	* @param pCmd Pointer to the command descriptor (as registered).
4921	* @param pCmdHlp Pointer to command helper functions.
4922	* @param pVM Pointer to the current VM (if any).
4923	* @param paArgs Pointer to (readonly) array of arguments.
4924	* @param cArgs Number of arguments in the array.
4925	*/
4926	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4927	{
4928	/** @todo SMP support!! */
4929	PVMCPU pVCpu = &pVM->aCpus[0];
4930
4931	/*
4932	* Validate input.
4933	*/
4934	if (!pVM)
4935	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4936
4937	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4938	if (RT_FAILURE(rc))
4939	return rc;
4940
4941	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4942
4943	return VINF_SUCCESS;
4944	}
4945	#endif /* VBOX_STRICT */
4946
4947
4948	/**
4949	* The '.pgmsyncalways' command.
4950	*
4951	* @returns VBox status.
4952	* @param pCmd Pointer to the command descriptor (as registered).
4953	* @param pCmdHlp Pointer to command helper functions.
4954	* @param pVM Pointer to the current VM (if any).
4955	* @param paArgs Pointer to (readonly) array of arguments.
4956	* @param cArgs Number of arguments in the array.
4957	*/
4958	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4959	{
4960	/** @todo SMP support!! */
4961	PVMCPU pVCpu = &pVM->aCpus[0];
4962
4963	/*
4964	* Validate input.
4965	*/
4966	if (!pVM)
4967	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4968
4969	/*
4970	* Force page directory sync.
4971	*/
4972	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4973	{
4974	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4975	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4976	}
4977	else
4978	{
4979	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4980	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4981	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4982	}
4983	}
4984
4985
4986	/**
4987	* The '.pgmsyncalways' command.
4988	*
4989	* @returns VBox status.
4990	* @param pCmd Pointer to the command descriptor (as registered).
4991	* @param pCmdHlp Pointer to command helper functions.
4992	* @param pVM Pointer to the current VM (if any).
4993	* @param paArgs Pointer to (readonly) array of arguments.
4994	* @param cArgs Number of arguments in the array.
4995	*/
4996	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4997	{
4998	/*
4999	* Validate input.
5000	*/
5001	if (!pVM)
5002	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
5003	if ( cArgs < 1
5004	\|\| cArgs > 2
5005	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
5006	\|\| ( cArgs > 1
5007	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
5008	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
5009	if ( cArgs >= 2
5010	&& strcmp(paArgs[1].u.pszString, "nozero"))
5011	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
5012	bool fIncZeroPgs = cArgs < 2;
5013
5014	/*
5015	* Open the output file and get the ram parameters.
5016	*/
5017	RTFILE hFile;
5018	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
5019	if (RT_FAILURE(rc))
5020	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
5021
5022	uint32_t cbRamHole = 0;
5023	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
5024	uint64_t cbRam = 0;
5025	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
5026	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
5027
5028	/*
5029	* Dump the physical memory, page by page.
5030	*/
5031	RTGCPHYS GCPhys = 0;
5032	char abZeroPg[PAGE_SIZE];
5033	RT_ZERO(abZeroPg);
5034
5035	pgmLock(pVM);
5036	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
5037	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
5038	pRam = pRam->pNextR3)
5039	{
5040	/* fill the gap */
5041	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
5042	{
5043	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
5044	{
5045	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5046	GCPhys += PAGE_SIZE;
5047	}
5048	}
5049
5050	PCPGMPAGE pPage = &pRam->aPages[0];
5051	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
5052	{
5053	if (PGM_PAGE_IS_ZERO(pPage))
5054	{
5055	if (fIncZeroPgs)
5056	{
5057	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5058	if (RT_FAILURE(rc))
5059	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5060	}
5061	}
5062	else
5063	{
5064	switch (PGM_PAGE_GET_TYPE(pPage))
5065	{
5066	case PGMPAGETYPE_RAM:
5067	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
5068	case PGMPAGETYPE_ROM:
5069	case PGMPAGETYPE_MMIO2:
5070	{
5071	void const *pvPage;
5072	PGMPAGEMAPLOCK Lock;
5073	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
5074	if (RT_SUCCESS(rc))
5075	{
5076	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
5077	PGMPhysReleasePageMappingLock(pVM, &Lock);
5078	if (RT_FAILURE(rc))
5079	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5080	}
5081	else
5082	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5083	break;
5084	}
5085
5086	default:
5087	AssertFailed();
5088	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
5089	case PGMPAGETYPE_MMIO:
5090	if (fIncZeroPgs)
5091	{
5092	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5093	if (RT_FAILURE(rc))
5094	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5095	}
5096	break;
5097	}
5098	}
5099
5100
5101	/* advance */
5102	GCPhys += PAGE_SIZE;
5103	pPage++;
5104	}
5105	}
5106	pgmUnlock(pVM);
5107
5108	RTFileClose(hFile);
5109	if (RT_SUCCESS(rc))
5110	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
5111	return VINF_SUCCESS;
5112	}
5113
5114	#endif /* VBOX_WITH_DEBUGGER */
5115
5116	/**
5117	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
5118	*/
5119	typedef struct PGMCHECKINTARGS
5120	{
5121	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
5122	PPGMPHYSHANDLER pPrevPhys;
5123	PPGMVIRTHANDLER pPrevVirt;
5124	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
5125	PVM pVM;
5126	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
5127
5128	/**
5129	* Validate a node in the physical handler tree.
5130	*
5131	* @returns 0 on if ok, other wise 1.
5132	* @param pNode The handler node.
5133	* @param pvUser pVM.
5134	*/
5135	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5136	{
5137	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5138	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
5139	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5140	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5141	AssertReleaseMsg( !pArgs->pPrevPhys
5142	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
5143	("pPrevPhys=%p %RGp-%RGp %s\n"
5144	" pCur=%p %RGp-%RGp %s\n",
5145	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
5146	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5147	pArgs->pPrevPhys = pCur;
5148	return 0;
5149	}
5150
5151
5152	/**
5153	* Validate a node in the virtual handler tree.
5154	*
5155	* @returns 0 on if ok, other wise 1.
5156	* @param pNode The handler node.
5157	* @param pvUser pVM.
5158	*/
5159	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5160	{
5161	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5162	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5163	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5164	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5165	AssertReleaseMsg( !pArgs->pPrevVirt
5166	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5167	("pPrevVirt=%p %RGv-%RGv %s\n"
5168	" pCur=%p %RGv-%RGv %s\n",
5169	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5170	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5171	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5172	{
5173	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5174	("pCur=%p %RGv-%RGv %s\n"
5175	"iPage=%d offVirtHandle=%#x expected %#x\n",
5176	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5177	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5178	}
5179	pArgs->pPrevVirt = pCur;
5180	return 0;
5181	}
5182
5183
5184	/**
5185	* Validate a node in the virtual handler tree.
5186	*
5187	* @returns 0 on if ok, other wise 1.
5188	* @param pNode The handler node.
5189	* @param pvUser pVM.
5190	*/
5191	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5192	{
5193	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5194	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5195	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5196	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5197	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5198	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5199	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5200	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5201	" pCur=%p %RGp-%RGp\n",
5202	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5203	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5204	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5205	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5206	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5207	" pCur=%p %RGp-%RGp\n",
5208	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5209	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5210	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5211	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5212	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5213	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5214	{
5215	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5216	for (;;)
5217	{
5218	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5219	AssertReleaseMsg(pCur2 != pCur,
5220	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5221	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5222	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5223	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5224	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5225	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5226	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5227	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5228	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5229	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5230	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5231	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5232	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5233	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5234	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5235	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5236	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5237	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5238	break;
5239	}
5240	}
5241
5242	pArgs->pPrevPhys2Virt = pCur;
5243	return 0;
5244	}
5245
5246
5247	/**
5248	* Perform an integrity check on the PGM component.
5249	*
5250	* @returns VINF_SUCCESS if everything is fine.
5251	* @returns VBox error status after asserting on integrity breach.
5252	* @param pVM The VM handle.
5253	*/
5254	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5255	{
5256	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5257
5258	/*
5259	* Check the trees.
5260	*/
5261	int cErrors = 0;
5262	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5263	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5264	PGMCHECKINTARGS Args = s_LeftToRight;
5265	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5266	Args = s_RightToLeft;
5267	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5268	Args = s_LeftToRight;
5269	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5270	Args = s_RightToLeft;
5271	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5272	Args = s_LeftToRight;
5273	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5274	Args = s_RightToLeft;
5275	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5276	Args = s_LeftToRight;
5277	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5278	Args = s_RightToLeft;
5279	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5280
5281	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5282	}
5283
5284

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 22544

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