VirtualBox

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 25045

Last change on this file since 25045 was 25015, checked in by vboxsync, 15 years ago

VMM: a few more -Wshadow fixes.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 216.2 KB
Line 
1/* $Id: PGM.cpp 25015 2009-11-26 15:27:42Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/** @page pg_pgm PGM - The Page Manager and Monitor
24 *
25 * @see grp_pgm,
26 * @ref pg_pgm_pool,
27 * @ref pg_pgm_phys.
28 *
29 *
30 * @section sec_pgm_modes Paging Modes
31 *
32 * There are three memory contexts: Host Context (HC), Guest Context (GC)
33 * and intermediate context. When talking about paging HC can also be refered to
34 * as "host paging", and GC refered to as "shadow paging".
35 *
36 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37 * is defined by the host operating system. The mode used in the shadow paging mode
38 * depends on the host paging mode and what the mode the guest is currently in. The
39 * following relation between the two is defined:
40 *
41 * @verbatim
42 Host > 32-bit | PAE | AMD64 |
43 Guest | | | |
44 ==v================================
45 32-bit 32-bit PAE PAE
46 -------|--------|--------|--------|
47 PAE PAE PAE PAE
48 -------|--------|--------|--------|
49 AMD64 AMD64 AMD64 AMD64
50 -------|--------|--------|--------| @endverbatim
51 *
52 * All configuration except those in the diagonal (upper left) are expected to
53 * require special effort from the switcher (i.e. a bit slower).
54 *
55 *
56 *
57 *
58 * @section sec_pgm_shw The Shadow Memory Context
59 *
60 *
61 * [..]
62 *
63 * Because of guest context mappings requires PDPT and PML4 entries to allow
64 * writing on AMD64, the two upper levels will have fixed flags whatever the
65 * guest is thinking of using there. So, when shadowing the PD level we will
66 * calculate the effective flags of PD and all the higher levels. In legacy
67 * PAE mode this only applies to the PWT and PCD bits (the rest are
68 * ignored/reserved/MBZ). We will ignore those bits for the present.
69 *
70 *
71 *
72 * @section sec_pgm_int The Intermediate Memory Context
73 *
74 * The world switch goes thru an intermediate memory context which purpose it is
75 * to provide different mappings of the switcher code. All guest mappings are also
76 * present in this context.
77 *
78 * The switcher code is mapped at the same location as on the host, at an
79 * identity mapped location (physical equals virtual address), and at the
80 * hypervisor location. The identity mapped location is for when the world
81 * switches that involves disabling paging.
82 *
83 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84 * simplifies switching guest CPU mode and consistency at the cost of more
85 * code to do the work. All memory use for those page tables is located below
86 * 4GB (this includes page tables for guest context mappings).
87 *
88 *
89 * @subsection subsec_pgm_int_gc Guest Context Mappings
90 *
91 * During assignment and relocation of a guest context mapping the intermediate
92 * memory context is used to verify the new location.
93 *
94 * Guest context mappings are currently restricted to below 4GB, for reasons
95 * of simplicity. This may change when we implement AMD64 support.
96 *
97 *
98 *
99 *
100 * @section sec_pgm_misc Misc
101 *
102 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103 *
104 * The differences between legacy PAE and long mode PAE are:
105 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107 * usual meanings while 6 is ignored (AMD). This means that upon switching to
108 * legacy PAE mode we'll have to clear these bits and when going to long mode
109 * they must be set. This applies to both intermediate and shadow contexts,
110 * however we don't need to do it for the intermediate one since we're
111 * executing with CR0.WP at that time.
112 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113 * a page aligned one is required.
114 *
115 *
116 * @section sec_pgm_handlers Access Handlers
117 *
118 * Placeholder.
119 *
120 *
121 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
122 *
123 * Placeholder.
124 *
125 *
126 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
127 *
128 * We currently implement three types of virtual access handlers: ALL, WRITE
129 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130 *
131 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134 * rest of this section is going to be about these handlers.
135 *
136 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
137 * how successfull this is gonna be...
138 *
139 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141 * and create a new node that is inserted into the AVL tree (range key). Then
142 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143 *
144 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145 *
146 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147 * via the current guest CR3 and update the physical page -> virtual handler
148 * translation. Needless to say, this doesn't exactly scale very well. If any changes
149 * are detected, it will flag a virtual bit update just like we did on registration.
150 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151 *
152 * 2b. The virtual bit update process will iterate all the pages covered by all the
153 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
154 * virtual handlers on that page.
155 *
156 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157 * we don't miss any alias mappings of the monitored pages.
158 *
159 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
160 *
161 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163 * will call the handlers like in the next step. If the physical mapping has
164 * changed we will - some time in the future - perform a handler callback
165 * (optional) and update the physical -> virtual handler cache.
166 *
167 * 4. \#PF(,write) on a page in the range. This will cause the handler to
168 * be invoked.
169 *
170 * 5. The guest invalidates the page and changes the physical backing or
171 * unmaps it. This should cause the invalidation callback to be invoked
172 * (it might not yet be 100% perfect). Exactly what happens next... is
173 * this where we mess up and end up out of sync for a while?
174 *
175 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
177 * this handler to NONE and trigger a full PGM resync (basically the same
178 * as int step 1). Which means 2 is executed again.
179 *
180 *
181 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182 *
183 * There is a bunch of things that needs to be done to make the virtual handlers
184 * work 100% correctly and work more efficiently.
185 *
186 * The first bit hasn't been implemented yet because it's going to slow the
187 * whole mess down even more, and besides it seems to be working reliably for
188 * our current uses. OTOH, some of the optimizations might end up more or less
189 * implementing the missing bits, so we'll see.
190 *
191 * On the optimization side, the first thing to do is to try avoid unnecessary
192 * cache flushing. Then try team up with the shadowing code to track changes
193 * in mappings by means of access to them (shadow in), updates to shadows pages,
194 * invlpg, and shadow PT discarding (perhaps).
195 *
196 * Some idea that have popped up for optimization for current and new features:
197 * - bitmap indicating where there are virtual handlers installed.
198 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
199 * - Further optimize this by min/max (needs min/max avl getters).
200 * - Shadow page table entry bit (if any left)?
201 *
202 */
203
204
205/** @page pg_pgm_phys PGM Physical Guest Memory Management
206 *
207 *
208 * Objectives:
209 * - Guest RAM over-commitment using memory ballooning,
210 * zero pages and general page sharing.
211 * - Moving or mirroring a VM onto a different physical machine.
212 *
213 *
214 * @subsection subsec_pgmPhys_Definitions Definitions
215 *
216 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217 * machinery assoicated with it.
218 *
219 *
220 *
221 *
222 * @subsection subsec_pgmPhys_AllocPage Allocating a page.
223 *
224 * Initially we map *all* guest memory to the (per VM) zero page, which
225 * means that none of the read functions will cause pages to be allocated.
226 *
227 * Exception, access bit in page tables that have been shared. This must
228 * be handled, but we must also make sure PGMGst*Modify doesn't make
229 * unnecessary modifications.
230 *
231 * Allocation points:
232 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233 * - Replacing a zero page mapping at \#PF.
234 * - Replacing a shared page mapping at \#PF.
235 * - ROM registration (currently MMR3RomRegister).
236 * - VM restore (pgmR3Load).
237 *
238 * For the first three it would make sense to keep a few pages handy
239 * until we've reached the max memory commitment for the VM.
240 *
241 * For the ROM registration, we know exactly how many pages we need
242 * and will request these from ring-0. For restore, we will save
243 * the number of non-zero pages in the saved state and allocate
244 * them up front. This would allow the ring-0 component to refuse
245 * the request if the isn't sufficient memory available for VM use.
246 *
247 * Btw. for both ROM and restore allocations we won't be requiring
248 * zeroed pages as they are going to be filled instantly.
249 *
250 *
251 * @subsection subsec_pgmPhys_FreePage Freeing a page
252 *
253 * There are a few points where a page can be freed:
254 * - After being replaced by the zero page.
255 * - After being replaced by a shared page.
256 * - After being ballooned by the guest additions.
257 * - At reset.
258 * - At restore.
259 *
260 * When freeing one or more pages they will be returned to the ring-0
261 * component and replaced by the zero page.
262 *
263 * The reasoning for clearing out all the pages on reset is that it will
264 * return us to the exact same state as on power on, and may thereby help
265 * us reduce the memory load on the system. Further it might have a
266 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267 *
268 * On restore, as mention under the allocation topic, pages should be
269 * freed / allocated depending on how many is actually required by the
270 * new VM state. The simplest approach is to do like on reset, and free
271 * all non-ROM pages and then allocate what we need.
272 *
273 * A measure to prevent some fragmentation, would be to let each allocation
274 * chunk have some affinity towards the VM having allocated the most pages
275 * from it. Also, try make sure to allocate from allocation chunks that
276 * are almost full. Admittedly, both these measures might work counter to
277 * our intentions and its probably not worth putting a lot of effort,
278 * cpu time or memory into this.
279 *
280 *
281 * @subsection subsec_pgmPhys_SharePage Sharing a page
282 *
283 * The basic idea is that there there will be a idle priority kernel
284 * thread walking the non-shared VM pages hashing them and looking for
285 * pages with the same checksum. If such pages are found, it will compare
286 * them byte-by-byte to see if they actually are identical. If found to be
287 * identical it will allocate a shared page, copy the content, check that
288 * the page didn't change while doing this, and finally request both the
289 * VMs to use the shared page instead. If the page is all zeros (special
290 * checksum and byte-by-byte check) it will request the VM that owns it
291 * to replace it with the zero page.
292 *
293 * To make this efficient, we will have to make sure not to try share a page
294 * that will change its contents soon. This part requires the most work.
295 * A simple idea would be to request the VM to write monitor the page for
296 * a while to make sure it isn't modified any time soon. Also, it may
297 * make sense to skip pages that are being write monitored since this
298 * information is readily available to the thread if it works on the
299 * per-VM guest memory structures (presently called PGMRAMRANGE).
300 *
301 *
302 * @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303 *
304 * The pages are organized in allocation chunks in ring-0, this is a necessity
305 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306 * could easily work on a page-by-page basis if we liked. Whether this is possible
307 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
308 * become a problem as part of the idea here is that we wish to return memory to
309 * the host system.
310 *
311 * For instance, starting two VMs at the same time, they will both allocate the
312 * guest memory on-demand and if permitted their page allocations will be
313 * intermixed. Shut down one of the two VMs and it will be difficult to return
314 * any memory to the host system because the page allocation for the two VMs are
315 * mixed up in the same allocation chunks.
316 *
317 * To further complicate matters, when pages are freed because they have been
318 * ballooned or become shared/zero the whole idea is that the page is supposed
319 * to be reused by another VM or returned to the host system. This will cause
320 * allocation chunks to contain pages belonging to different VMs and prevent
321 * returning memory to the host when one of those VM shuts down.
322 *
323 * The only way to really deal with this problem is to move pages. This can
324 * either be done at VM shutdown and or by the idle priority worker thread
325 * that will be responsible for finding sharable/zero pages. The mechanisms
326 * involved for coercing a VM to move a page (or to do it for it) will be
327 * the same as when telling it to share/zero a page.
328 *
329 *
330 * @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331 *
332 * There's a difficult balance between keeping the per-page tracking structures
333 * (global and guest page) easy to use and keeping them from eating too much
334 * memory. We have limited virtual memory resources available when operating in
335 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336 * tracking structures will be attemted designed such that we can deal with up
337 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338 *
339 *
340 * @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341 *
342 * @see pg_GMM
343 *
344 * @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345 *
346 * Fixed info is the physical address of the page (HCPhys) and the page id
347 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348 * Today we've restricting ourselves to 40(-12) bits because this is the current
349 * restrictions of all AMD64 implementations (I think Barcelona will up this
350 * to 48(-12) bits, not that it really matters) and I needed the bits for
351 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352 * decent range for the page id: 2^(28+12) = 1024TB.
353 *
354 * In additions to these, we'll have to keep maintaining the page flags as we
355 * currently do. Although it wouldn't harm to optimize these quite a bit, like
356 * for instance the ROM shouldn't depend on having a write handler installed
357 * in order for it to become read-only. A RO/RW bit should be considered so
358 * that the page syncing code doesn't have to mess about checking multiple
359 * flag combinations (ROM || RW handler || write monitored) in order to
360 * figure out how to setup a shadow PTE. But this of course, is second
361 * priority at present. Current this requires 12 bits, but could probably
362 * be optimized to ~8.
363 *
364 * Then there's the 24 bits used to track which shadow page tables are
365 * currently mapping a page for the purpose of speeding up physical
366 * access handlers, and thereby the page pool cache. More bit for this
367 * purpose wouldn't hurt IIRC.
368 *
369 * Then there is a new bit in which we need to record what kind of page
370 * this is, shared, zero, normal or write-monitored-normal. This'll
371 * require 2 bits. One bit might be needed for indicating whether a
372 * write monitored page has been written to. And yet another one or
373 * two for tracking migration status. 3-4 bits total then.
374 *
375 * Whatever is left will can be used to record the sharabilitiy of a
376 * page. The page checksum will not be stored in the per-VM table as
377 * the idle thread will not be permitted to do modifications to it.
378 * It will instead have to keep its own working set of potentially
379 * shareable pages and their check sums and stuff.
380 *
381 * For the present we'll keep the current packing of the
382 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383 * we'll have to change it to a struct with a total of 128-bits at
384 * our disposal.
385 *
386 * The initial layout will be like this:
387 * @verbatim
388 RTHCPHYS HCPhys; The current stuff.
389 63:40 Current shadow PT tracking stuff.
390 39:12 The physical page frame number.
391 11:0 The current flags.
392 uint32_t u28PageId : 28; The page id.
393 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395 uint32_t u1Reserved : 1; Reserved for later.
396 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397 @endverbatim
398 *
399 * The final layout will be something like this:
400 * @verbatim
401 RTHCPHYS HCPhys; The current stuff.
402 63:48 High page id (12+).
403 47:12 The physical page frame number.
404 11:0 Low page id.
405 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413 @endverbatim
414 *
415 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
417 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419 *
420 * A couple of cost examples for the total cost per-VM + kernel.
421 * 32-bit Windows and 32-bit linux:
422 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425 * 64-bit Windows and 64-bit linux:
426 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429 *
430 * UPDATE - 2007-09-27:
431 * Will need a ballooned flag/state too because we cannot
432 * trust the guest 100% and reporting the same page as ballooned more
433 * than once will put the GMM off balance.
434 *
435 *
436 * @subsection subsec_pgmPhys_Serializing Serializing Access
437 *
438 * Initially, we'll try a simple scheme:
439 *
440 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441 * by the EMT thread of that VM while in the pgm critsect.
442 * - Other threads in the VM process that needs to make reliable use of
443 * the per-VM RAM tracking structures will enter the critsect.
444 * - No process external thread or kernel thread will ever try enter
445 * the pgm critical section, as that just won't work.
446 * - The idle thread (and similar threads) doesn't not need 100% reliable
447 * data when performing it tasks as the EMT thread will be the one to
448 * do the actual changes later anyway. So, as long as it only accesses
449 * the main ram range, it can do so by somehow preventing the VM from
450 * being destroyed while it works on it...
451 *
452 * - The over-commitment management, including the allocating/freeing
453 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
454 * more mundane mutex implementation is broken on Linux).
455 * - A separeate mutex is protecting the set of allocation chunks so
456 * that pages can be shared or/and freed up while some other VM is
457 * allocating more chunks. This mutex can be take from under the other
458 * one, but not the otherway around.
459 *
460 *
461 * @subsection subsec_pgmPhys_Request VM Request interface
462 *
463 * When in ring-0 it will become necessary to send requests to a VM so it can
464 * for instance move a page while defragmenting during VM destroy. The idle
465 * thread will make use of this interface to request VMs to setup shared
466 * pages and to perform write monitoring of pages.
467 *
468 * I would propose an interface similar to the current VMReq interface, similar
469 * in that it doesn't require locking and that the one sending the request may
470 * wait for completion if it wishes to. This shouldn't be very difficult to
471 * realize.
472 *
473 * The requests themselves are also pretty simple. They are basically:
474 * -# Check that some precondition is still true.
475 * -# Do the update.
476 * -# Update all shadow page tables involved with the page.
477 *
478 * The 3rd step is identical to what we're already doing when updating a
479 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480 *
481 *
482 *
483 * @section sec_pgmPhys_MappingCaches Mapping Caches
484 *
485 * In order to be able to map in and out memory and to be able to support
486 * guest with more RAM than we've got virtual address space, we'll employing
487 * a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488 * and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489 * memory context for the HWACCM execution.
490 *
491 *
492 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493 *
494 * We've considered implementing the ring-3 mapping cache page based but found
495 * that this was bother some when one had to take into account TLBs+SMP and
496 * portability (missing the necessary APIs on several platforms). There were
497 * also some performance concerns with this approach which hadn't quite been
498 * worked out.
499 *
500 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504 * costly than a single page, although how much more costly is uncertain. We'll
505 * try address this by using a very big cache, preferably bigger than the actual
506 * VM RAM size if possible. The current VM RAM sizes should give some idea for
507 * 32-bit boxes, while on 64-bit we can probably get away with employing an
508 * unlimited cache.
509 *
510 * The cache have to parts, as already indicated, the ring-3 side and the
511 * ring-0 side.
512 *
513 * The ring-0 will be tied to the page allocator since it will operate on the
514 * memory objects it contains. It will therefore require the first ring-0 mutex
515 * discussed in @ref subsec_pgmPhys_Serializing. We
516 * some double house keeping wrt to who has mapped what I think, since both
517 * VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518 *
519 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520 * require anyone that desires to do changes to the mapping cache to do that
521 * from within this critsect. Alternatively, we could employ a separate critsect
522 * for serializing changes to the mapping cache as this would reduce potential
523 * contention with other threads accessing mappings unrelated to the changes
524 * that are in process. We can see about this later, contention will show
525 * up in the statistics anyway, so it'll be simple to tell.
526 *
527 * The organization of the ring-3 part will be very much like how the allocation
528 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529 * having to walk the tree all the time, we'll have a couple of lookaside entries
530 * like in we do for I/O ports and MMIO in IOM.
531 *
532 * The simplified flow of a PGMPhysRead/Write function:
533 * -# Enter the PGM critsect.
534 * -# Lookup GCPhys in the ram ranges and get the Page ID.
535 * -# Calc the Allocation Chunk ID from the Page ID.
536 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537 * If not found in cache:
538 * -# Call ring-0 and request it to be mapped and supply
539 * a chunk to be unmapped if the cache is maxed out already.
540 * -# Insert the new mapping into the AVL tree (id + R3 address).
541 * -# Update the relevant lookaside entry and return the mapping address.
542 * -# Do the read/write according to monitoring flags and everything.
543 * -# Leave the critsect.
544 *
545 *
546 * @section sec_pgmPhys_Fallback Fallback
547 *
548 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549 * API and thus require a fallback.
550 *
551 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552 * will return to the ring-3 caller (and later ring-0) and asking it to seed
553 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555 * "SeededAllocPages" call to ring-0.
556 *
557 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558 * all page sharing (zero page detection will continue). It will also force
559 * all allocations to come from the VM which seeded the page. Both these
560 * measures are taken to make sure that there will never be any need for
561 * mapping anything into ring-3 - everything will be mapped already.
562 *
563 * Whether we'll continue to use the current MM locked memory management
564 * for this I don't quite know (I'd prefer not to and just ditch that all
565 * togther), we'll see what's simplest to do.
566 *
567 *
568 *
569 * @section sec_pgmPhys_Changes Changes
570 *
571 * Breakdown of the changes involved?
572 */
573
574/*******************************************************************************
575* Header Files *
576*******************************************************************************/
577#define LOG_GROUP LOG_GROUP_PGM
578#include <VBox/dbgf.h>
579#include <VBox/pgm.h>
580#include <VBox/cpum.h>
581#include <VBox/iom.h>
582#include <VBox/sup.h>
583#include <VBox/mm.h>
584#include <VBox/em.h>
585#include <VBox/stam.h>
586#include <VBox/rem.h>
587#include <VBox/selm.h>
588#include <VBox/ssm.h>
589#include <VBox/hwaccm.h>
590#include "PGMInternal.h"
591#include <VBox/vm.h>
592
593#include <VBox/dbg.h>
594#include <VBox/param.h>
595#include <VBox/err.h>
596
597#include <iprt/asm.h>
598#include <iprt/assert.h>
599#include <iprt/env.h>
600#include <iprt/mem.h>
601#include <iprt/file.h>
602#include <iprt/string.h>
603#include <iprt/thread.h>
604
605
606/*******************************************************************************
607* Defined Constants And Macros *
608*******************************************************************************/
609/** Saved state data unit version for 2.5.x and later. */
610#define PGM_SAVED_STATE_VERSION 9
611/** Saved state data unit version for 2.2.2 and later. */
612#define PGM_SAVED_STATE_VERSION_2_2_2 8
613/** Saved state data unit version for 2.2.0. */
614#define PGM_SAVED_STATE_VERSION_RR_DESC 7
615/** Saved state data unit version. */
616#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
617
618
619/*******************************************************************************
620* Internal Functions *
621*******************************************************************************/
622static int pgmR3InitPaging(PVM pVM);
623static void pgmR3InitStats(PVM pVM);
624static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
625static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
628static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
629static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630#ifdef VBOX_STRICT
631static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
632#endif
633static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
634static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
635static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
636
637#ifdef VBOX_WITH_DEBUGGER
638/** @todo Convert the first two commands to 'info' items. */
639static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644# ifdef VBOX_STRICT
645static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646# endif
647static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648#endif
649
650
651/*******************************************************************************
652* Global Variables *
653*******************************************************************************/
654#ifdef VBOX_WITH_DEBUGGER
655/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
656static const DBGCVARDESC g_aPgmErrorArgs[] =
657{
658 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
659 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
660};
661
662static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
663{
664 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
665 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
666 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
667};
668
669/** Command descriptors. */
670static const DBGCCMD g_aCmds[] =
671{
672 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
673 { "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
674 { "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
675 { "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
676 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
677 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
678#ifdef VBOX_STRICT
679 { "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
680#endif
681 { "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
682 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
683};
684#endif
685
686
687
688
689/*
690 * Shadow - 32-bit mode
691 */
692#define PGM_SHW_TYPE PGM_TYPE_32BIT
693#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
694#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
695#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
696#include "PGMShw.h"
697
698/* Guest - real mode */
699#define PGM_GST_TYPE PGM_TYPE_REAL
700#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
701#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
702#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
703#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
704#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
705#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
706#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
708#include "PGMBth.h"
709#include "PGMGstDefs.h"
710#include "PGMGst.h"
711#undef BTH_PGMPOOLKIND_PT_FOR_PT
712#undef BTH_PGMPOOLKIND_ROOT
713#undef PGM_BTH_NAME
714#undef PGM_BTH_NAME_RC_STR
715#undef PGM_BTH_NAME_R0_STR
716#undef PGM_GST_TYPE
717#undef PGM_GST_NAME
718#undef PGM_GST_NAME_RC_STR
719#undef PGM_GST_NAME_R0_STR
720
721/* Guest - protected mode */
722#define PGM_GST_TYPE PGM_TYPE_PROT
723#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
724#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
725#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
726#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
727#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
728#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
729#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
730#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
731#include "PGMBth.h"
732#include "PGMGstDefs.h"
733#include "PGMGst.h"
734#undef BTH_PGMPOOLKIND_PT_FOR_PT
735#undef BTH_PGMPOOLKIND_ROOT
736#undef PGM_BTH_NAME
737#undef PGM_BTH_NAME_RC_STR
738#undef PGM_BTH_NAME_R0_STR
739#undef PGM_GST_TYPE
740#undef PGM_GST_NAME
741#undef PGM_GST_NAME_RC_STR
742#undef PGM_GST_NAME_R0_STR
743
744/* Guest - 32-bit mode */
745#define PGM_GST_TYPE PGM_TYPE_32BIT
746#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
747#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
748#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
749#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
750#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
751#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
752#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
753#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
754#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
755#include "PGMBth.h"
756#include "PGMGstDefs.h"
757#include "PGMGst.h"
758#undef BTH_PGMPOOLKIND_PT_FOR_BIG
759#undef BTH_PGMPOOLKIND_PT_FOR_PT
760#undef BTH_PGMPOOLKIND_ROOT
761#undef PGM_BTH_NAME
762#undef PGM_BTH_NAME_RC_STR
763#undef PGM_BTH_NAME_R0_STR
764#undef PGM_GST_TYPE
765#undef PGM_GST_NAME
766#undef PGM_GST_NAME_RC_STR
767#undef PGM_GST_NAME_R0_STR
768
769#undef PGM_SHW_TYPE
770#undef PGM_SHW_NAME
771#undef PGM_SHW_NAME_RC_STR
772#undef PGM_SHW_NAME_R0_STR
773
774
775/*
776 * Shadow - PAE mode
777 */
778#define PGM_SHW_TYPE PGM_TYPE_PAE
779#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
780#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
781#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
782#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
783#include "PGMShw.h"
784
785/* Guest - real mode */
786#define PGM_GST_TYPE PGM_TYPE_REAL
787#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
788#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
789#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
790#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
791#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
792#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
793#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
794#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
795#include "PGMGstDefs.h"
796#include "PGMBth.h"
797#undef BTH_PGMPOOLKIND_PT_FOR_PT
798#undef BTH_PGMPOOLKIND_ROOT
799#undef PGM_BTH_NAME
800#undef PGM_BTH_NAME_RC_STR
801#undef PGM_BTH_NAME_R0_STR
802#undef PGM_GST_TYPE
803#undef PGM_GST_NAME
804#undef PGM_GST_NAME_RC_STR
805#undef PGM_GST_NAME_R0_STR
806
807/* Guest - protected mode */
808#define PGM_GST_TYPE PGM_TYPE_PROT
809#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
810#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
811#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
812#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
813#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
814#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
815#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
816#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
817#include "PGMGstDefs.h"
818#include "PGMBth.h"
819#undef BTH_PGMPOOLKIND_PT_FOR_PT
820#undef BTH_PGMPOOLKIND_ROOT
821#undef PGM_BTH_NAME
822#undef PGM_BTH_NAME_RC_STR
823#undef PGM_BTH_NAME_R0_STR
824#undef PGM_GST_TYPE
825#undef PGM_GST_NAME
826#undef PGM_GST_NAME_RC_STR
827#undef PGM_GST_NAME_R0_STR
828
829/* Guest - 32-bit mode */
830#define PGM_GST_TYPE PGM_TYPE_32BIT
831#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
832#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
833#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
834#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
835#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
836#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
837#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
838#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
839#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
840#include "PGMGstDefs.h"
841#include "PGMBth.h"
842#undef BTH_PGMPOOLKIND_PT_FOR_BIG
843#undef BTH_PGMPOOLKIND_PT_FOR_PT
844#undef BTH_PGMPOOLKIND_ROOT
845#undef PGM_BTH_NAME
846#undef PGM_BTH_NAME_RC_STR
847#undef PGM_BTH_NAME_R0_STR
848#undef PGM_GST_TYPE
849#undef PGM_GST_NAME
850#undef PGM_GST_NAME_RC_STR
851#undef PGM_GST_NAME_R0_STR
852
853/* Guest - PAE mode */
854#define PGM_GST_TYPE PGM_TYPE_PAE
855#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
856#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
857#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
858#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
859#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
860#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
861#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
864#include "PGMBth.h"
865#include "PGMGstDefs.h"
866#include "PGMGst.h"
867#undef BTH_PGMPOOLKIND_PT_FOR_BIG
868#undef BTH_PGMPOOLKIND_PT_FOR_PT
869#undef BTH_PGMPOOLKIND_ROOT
870#undef PGM_BTH_NAME
871#undef PGM_BTH_NAME_RC_STR
872#undef PGM_BTH_NAME_R0_STR
873#undef PGM_GST_TYPE
874#undef PGM_GST_NAME
875#undef PGM_GST_NAME_RC_STR
876#undef PGM_GST_NAME_R0_STR
877
878#undef PGM_SHW_TYPE
879#undef PGM_SHW_NAME
880#undef PGM_SHW_NAME_RC_STR
881#undef PGM_SHW_NAME_R0_STR
882
883
884/*
885 * Shadow - AMD64 mode
886 */
887#define PGM_SHW_TYPE PGM_TYPE_AMD64
888#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
889#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
890#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
891#include "PGMShw.h"
892
893#ifdef VBOX_WITH_64_BITS_GUESTS
894/* Guest - AMD64 mode */
895# define PGM_GST_TYPE PGM_TYPE_AMD64
896# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
897# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
898# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
899# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
900# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
901# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
902# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
903# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
904# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
905# include "PGMBth.h"
906# include "PGMGstDefs.h"
907# include "PGMGst.h"
908# undef BTH_PGMPOOLKIND_PT_FOR_BIG
909# undef BTH_PGMPOOLKIND_PT_FOR_PT
910# undef BTH_PGMPOOLKIND_ROOT
911# undef PGM_BTH_NAME
912# undef PGM_BTH_NAME_RC_STR
913# undef PGM_BTH_NAME_R0_STR
914# undef PGM_GST_TYPE
915# undef PGM_GST_NAME
916# undef PGM_GST_NAME_RC_STR
917# undef PGM_GST_NAME_R0_STR
918#endif /* VBOX_WITH_64_BITS_GUESTS */
919
920#undef PGM_SHW_TYPE
921#undef PGM_SHW_NAME
922#undef PGM_SHW_NAME_RC_STR
923#undef PGM_SHW_NAME_R0_STR
924
925
926/*
927 * Shadow - Nested paging mode
928 */
929#define PGM_SHW_TYPE PGM_TYPE_NESTED
930#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
931#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
932#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
933#include "PGMShw.h"
934
935/* Guest - real mode */
936#define PGM_GST_TYPE PGM_TYPE_REAL
937#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
938#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
939#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
940#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
941#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
942#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
943#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
944#include "PGMGstDefs.h"
945#include "PGMBth.h"
946#undef BTH_PGMPOOLKIND_PT_FOR_PT
947#undef PGM_BTH_NAME
948#undef PGM_BTH_NAME_RC_STR
949#undef PGM_BTH_NAME_R0_STR
950#undef PGM_GST_TYPE
951#undef PGM_GST_NAME
952#undef PGM_GST_NAME_RC_STR
953#undef PGM_GST_NAME_R0_STR
954
955/* Guest - protected mode */
956#define PGM_GST_TYPE PGM_TYPE_PROT
957#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
958#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
959#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
960#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
961#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
962#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
963#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
964#include "PGMGstDefs.h"
965#include "PGMBth.h"
966#undef BTH_PGMPOOLKIND_PT_FOR_PT
967#undef PGM_BTH_NAME
968#undef PGM_BTH_NAME_RC_STR
969#undef PGM_BTH_NAME_R0_STR
970#undef PGM_GST_TYPE
971#undef PGM_GST_NAME
972#undef PGM_GST_NAME_RC_STR
973#undef PGM_GST_NAME_R0_STR
974
975/* Guest - 32-bit mode */
976#define PGM_GST_TYPE PGM_TYPE_32BIT
977#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
978#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
979#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
980#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
981#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
982#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
983#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
984#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
985#include "PGMGstDefs.h"
986#include "PGMBth.h"
987#undef BTH_PGMPOOLKIND_PT_FOR_BIG
988#undef BTH_PGMPOOLKIND_PT_FOR_PT
989#undef PGM_BTH_NAME
990#undef PGM_BTH_NAME_RC_STR
991#undef PGM_BTH_NAME_R0_STR
992#undef PGM_GST_TYPE
993#undef PGM_GST_NAME
994#undef PGM_GST_NAME_RC_STR
995#undef PGM_GST_NAME_R0_STR
996
997/* Guest - PAE mode */
998#define PGM_GST_TYPE PGM_TYPE_PAE
999#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1000#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1001#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1002#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1003#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1004#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1005#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1006#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1007#include "PGMGstDefs.h"
1008#include "PGMBth.h"
1009#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1010#undef BTH_PGMPOOLKIND_PT_FOR_PT
1011#undef PGM_BTH_NAME
1012#undef PGM_BTH_NAME_RC_STR
1013#undef PGM_BTH_NAME_R0_STR
1014#undef PGM_GST_TYPE
1015#undef PGM_GST_NAME
1016#undef PGM_GST_NAME_RC_STR
1017#undef PGM_GST_NAME_R0_STR
1018
1019#ifdef VBOX_WITH_64_BITS_GUESTS
1020/* Guest - AMD64 mode */
1021# define PGM_GST_TYPE PGM_TYPE_AMD64
1022# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1023# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1024# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1025# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1026# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1027# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1028# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1029# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1030# include "PGMGstDefs.h"
1031# include "PGMBth.h"
1032# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1033# undef BTH_PGMPOOLKIND_PT_FOR_PT
1034# undef PGM_BTH_NAME
1035# undef PGM_BTH_NAME_RC_STR
1036# undef PGM_BTH_NAME_R0_STR
1037# undef PGM_GST_TYPE
1038# undef PGM_GST_NAME
1039# undef PGM_GST_NAME_RC_STR
1040# undef PGM_GST_NAME_R0_STR
1041#endif /* VBOX_WITH_64_BITS_GUESTS */
1042
1043#undef PGM_SHW_TYPE
1044#undef PGM_SHW_NAME
1045#undef PGM_SHW_NAME_RC_STR
1046#undef PGM_SHW_NAME_R0_STR
1047
1048
1049/*
1050 * Shadow - EPT
1051 */
1052#define PGM_SHW_TYPE PGM_TYPE_EPT
1053#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1054#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1055#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1056#include "PGMShw.h"
1057
1058/* Guest - real mode */
1059#define PGM_GST_TYPE PGM_TYPE_REAL
1060#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1061#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1062#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1063#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1064#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1065#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1066#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1067#include "PGMGstDefs.h"
1068#include "PGMBth.h"
1069#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070#undef PGM_BTH_NAME
1071#undef PGM_BTH_NAME_RC_STR
1072#undef PGM_BTH_NAME_R0_STR
1073#undef PGM_GST_TYPE
1074#undef PGM_GST_NAME
1075#undef PGM_GST_NAME_RC_STR
1076#undef PGM_GST_NAME_R0_STR
1077
1078/* Guest - protected mode */
1079#define PGM_GST_TYPE PGM_TYPE_PROT
1080#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1081#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1082#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1083#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1084#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1085#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1086#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1087#include "PGMGstDefs.h"
1088#include "PGMBth.h"
1089#undef BTH_PGMPOOLKIND_PT_FOR_PT
1090#undef PGM_BTH_NAME
1091#undef PGM_BTH_NAME_RC_STR
1092#undef PGM_BTH_NAME_R0_STR
1093#undef PGM_GST_TYPE
1094#undef PGM_GST_NAME
1095#undef PGM_GST_NAME_RC_STR
1096#undef PGM_GST_NAME_R0_STR
1097
1098/* Guest - 32-bit mode */
1099#define PGM_GST_TYPE PGM_TYPE_32BIT
1100#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1101#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1102#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1103#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1104#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1105#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1107#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1108#include "PGMGstDefs.h"
1109#include "PGMBth.h"
1110#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1111#undef BTH_PGMPOOLKIND_PT_FOR_PT
1112#undef PGM_BTH_NAME
1113#undef PGM_BTH_NAME_RC_STR
1114#undef PGM_BTH_NAME_R0_STR
1115#undef PGM_GST_TYPE
1116#undef PGM_GST_NAME
1117#undef PGM_GST_NAME_RC_STR
1118#undef PGM_GST_NAME_R0_STR
1119
1120/* Guest - PAE mode */
1121#define PGM_GST_TYPE PGM_TYPE_PAE
1122#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1123#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1124#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1125#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1126#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1127#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1128#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1129#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1130#include "PGMGstDefs.h"
1131#include "PGMBth.h"
1132#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1133#undef BTH_PGMPOOLKIND_PT_FOR_PT
1134#undef PGM_BTH_NAME
1135#undef PGM_BTH_NAME_RC_STR
1136#undef PGM_BTH_NAME_R0_STR
1137#undef PGM_GST_TYPE
1138#undef PGM_GST_NAME
1139#undef PGM_GST_NAME_RC_STR
1140#undef PGM_GST_NAME_R0_STR
1141
1142#ifdef VBOX_WITH_64_BITS_GUESTS
1143/* Guest - AMD64 mode */
1144# define PGM_GST_TYPE PGM_TYPE_AMD64
1145# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1146# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1147# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1148# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1149# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1150# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1151# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1152# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1153# include "PGMGstDefs.h"
1154# include "PGMBth.h"
1155# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1156# undef BTH_PGMPOOLKIND_PT_FOR_PT
1157# undef PGM_BTH_NAME
1158# undef PGM_BTH_NAME_RC_STR
1159# undef PGM_BTH_NAME_R0_STR
1160# undef PGM_GST_TYPE
1161# undef PGM_GST_NAME
1162# undef PGM_GST_NAME_RC_STR
1163# undef PGM_GST_NAME_R0_STR
1164#endif /* VBOX_WITH_64_BITS_GUESTS */
1165
1166#undef PGM_SHW_TYPE
1167#undef PGM_SHW_NAME
1168#undef PGM_SHW_NAME_RC_STR
1169#undef PGM_SHW_NAME_R0_STR
1170
1171
1172
1173/**
1174 * Initiates the paging of VM.
1175 *
1176 * @returns VBox status code.
1177 * @param pVM Pointer to VM structure.
1178 */
1179VMMR3DECL(int) PGMR3Init(PVM pVM)
1180{
1181 LogFlow(("PGMR3Init:\n"));
1182 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1183 int rc;
1184
1185 /*
1186 * Assert alignment and sizes.
1187 */
1188 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1189 AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1190 AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1191
1192 /*
1193 * Init the structure.
1194 */
1195 pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1196 pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1197
1198 /* Init the per-CPU part. */
1199 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1200 {
1201 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1202 PPGMCPU pPGM = &pVCpu->pgm.s;
1203
1204 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1205 pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1206 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1207
1208 pPGM->enmShadowMode = PGMMODE_INVALID;
1209 pPGM->enmGuestMode = PGMMODE_INVALID;
1210
1211 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1212
1213 pPGM->pGstPaePdptR3 = NULL;
1214#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1215 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1216#endif
1217 pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1218 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1219 {
1220 pPGM->apGstPaePDsR3[i] = NULL;
1221#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1222 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1223#endif
1224 pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1225 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1226 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1227 }
1228
1229 pPGM->fA20Enabled = true;
1230 }
1231
1232 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1233 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1234 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1235
1236 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1237#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1238 true
1239#else
1240 false
1241#endif
1242 );
1243 AssertLogRelRCReturn(rc, rc);
1244
1245#if HC_ARCH_BITS == 64 || 1 /** @todo 4GB/32-bit: remove || 1 later and adjust the limit. */
1246 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1247#else
1248 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1249#endif
1250 AssertLogRelRCReturn(rc, rc);
1251 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1252 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1253
1254 /*
1255 * Get the configured RAM size - to estimate saved state size.
1256 */
1257 uint64_t cbRam;
1258 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1259 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1260 cbRam = 0;
1261 else if (RT_SUCCESS(rc))
1262 {
1263 if (cbRam < PAGE_SIZE)
1264 cbRam = 0;
1265 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1266 }
1267 else
1268 {
1269 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1270 return rc;
1271 }
1272
1273 /*
1274 * Register callbacks, string formatters and the saved state data unit.
1275 */
1276#ifdef VBOX_STRICT
1277 VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1278#endif
1279 PGMRegisterStringFormatTypes();
1280
1281 rc = pgmR3InitSavedState(pVM, cbRam);
1282 if (RT_FAILURE(rc))
1283 return rc;
1284
1285 /*
1286 * Initialize the PGM critical section and flush the phys TLBs
1287 */
1288 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1289 AssertRCReturn(rc, rc);
1290
1291 PGMR3PhysChunkInvalidateTLB(pVM);
1292 PGMPhysInvalidatePageMapTLB(pVM);
1293
1294 /*
1295 * For the time being we sport a full set of handy pages in addition to the base
1296 * memory to simplify things.
1297 */
1298 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1299 AssertRCReturn(rc, rc);
1300
1301 /*
1302 * Trees
1303 */
1304 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1305 if (RT_SUCCESS(rc))
1306 {
1307 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1308 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1309
1310 /*
1311 * Alocate the zero page.
1312 */
1313 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1314 }
1315 if (RT_SUCCESS(rc))
1316 {
1317 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1318 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1319 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1320 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1321
1322 /*
1323 * Init the paging.
1324 */
1325 rc = pgmR3InitPaging(pVM);
1326 }
1327 if (RT_SUCCESS(rc))
1328 {
1329 /*
1330 * Init the page pool.
1331 */
1332 rc = pgmR3PoolInit(pVM);
1333 }
1334 if (RT_SUCCESS(rc))
1335 {
1336 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1337 {
1338 PVMCPU pVCpu = &pVM->aCpus[i];
1339 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1340 if (RT_FAILURE(rc))
1341 break;
1342 }
1343 }
1344
1345 if (RT_SUCCESS(rc))
1346 {
1347 /*
1348 * Info & statistics
1349 */
1350 DBGFR3InfoRegisterInternal(pVM, "mode",
1351 "Shows the current paging mode. "
1352 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1353 pgmR3InfoMode);
1354 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1355 "Dumps all the entries in the top level paging table. No arguments.",
1356 pgmR3InfoCr3);
1357 DBGFR3InfoRegisterInternal(pVM, "phys",
1358 "Dumps all the physical address ranges. No arguments.",
1359 pgmR3PhysInfo);
1360 DBGFR3InfoRegisterInternal(pVM, "handlers",
1361 "Dumps physical, virtual and hyper virtual handlers. "
1362 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1363 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1364 pgmR3InfoHandlers);
1365 DBGFR3InfoRegisterInternal(pVM, "mappings",
1366 "Dumps guest mappings.",
1367 pgmR3MapInfo);
1368
1369 pgmR3InitStats(pVM);
1370
1371#ifdef VBOX_WITH_DEBUGGER
1372 /*
1373 * Debugger commands.
1374 */
1375 static bool s_fRegisteredCmds = false;
1376 if (!s_fRegisteredCmds)
1377 {
1378 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1379 if (RT_SUCCESS(rc2))
1380 s_fRegisteredCmds = true;
1381 }
1382#endif
1383 return VINF_SUCCESS;
1384 }
1385
1386 /* Almost no cleanup necessary, MM frees all memory. */
1387 PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1388
1389 return rc;
1390}
1391
1392
1393/**
1394 * Initializes the per-VCPU PGM.
1395 *
1396 * @returns VBox status code.
1397 * @param pVM The VM to operate on.
1398 */
1399VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1400{
1401 LogFlow(("PGMR3InitCPU\n"));
1402 return VINF_SUCCESS;
1403}
1404
1405
1406/**
1407 * Init paging.
1408 *
1409 * Since we need to check what mode the host is operating in before we can choose
1410 * the right paging functions for the host we have to delay this until R0 has
1411 * been initialized.
1412 *
1413 * @returns VBox status code.
1414 * @param pVM VM handle.
1415 */
1416static int pgmR3InitPaging(PVM pVM)
1417{
1418 /*
1419 * Force a recalculation of modes and switcher so everyone gets notified.
1420 */
1421 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1422 {
1423 PVMCPU pVCpu = &pVM->aCpus[i];
1424
1425 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1426 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1427 }
1428
1429 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1430
1431 /*
1432 * Allocate static mapping space for whatever the cr3 register
1433 * points to and in the case of PAE mode to the 4 PDs.
1434 */
1435 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1436 if (RT_FAILURE(rc))
1437 {
1438 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1439 return rc;
1440 }
1441 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1442
1443 /*
1444 * Allocate pages for the three possible intermediate contexts
1445 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1446 * for the sake of simplicity. The AMD64 uses the PAE for the
1447 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1448 *
1449 * We assume that two page tables will be enought for the core code
1450 * mappings (HC virtual and identity).
1451 */
1452 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1453 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1454 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1455 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1456 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1457 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1458 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1459 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1460 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1461 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1462 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1463 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1464
1465 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1466 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1467 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1468 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1469 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1470 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1471
1472 /*
1473 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1474 */
1475 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1476 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1477 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1478
1479 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1480 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1481
1482 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1483 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1484 {
1485 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1486 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1487 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1488 }
1489
1490 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1491 {
1492 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1493 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1494 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1495 }
1496
1497 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1498 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1499 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1500 | HCPhysInterPaePDPT64;
1501
1502 /*
1503 * Initialize paging workers and mode from current host mode
1504 * and the guest running in real mode.
1505 */
1506 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1507 switch (pVM->pgm.s.enmHostMode)
1508 {
1509 case SUPPAGINGMODE_32_BIT:
1510 case SUPPAGINGMODE_32_BIT_GLOBAL:
1511 case SUPPAGINGMODE_PAE:
1512 case SUPPAGINGMODE_PAE_GLOBAL:
1513 case SUPPAGINGMODE_PAE_NX:
1514 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1515 break;
1516
1517 case SUPPAGINGMODE_AMD64:
1518 case SUPPAGINGMODE_AMD64_GLOBAL:
1519 case SUPPAGINGMODE_AMD64_NX:
1520 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1521#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1522 if (ARCH_BITS != 64)
1523 {
1524 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1525 LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1526 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1527 }
1528#endif
1529 break;
1530 default:
1531 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1532 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1533 }
1534 rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1535 if (RT_SUCCESS(rc))
1536 {
1537 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1538#if HC_ARCH_BITS == 64
1539 LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1540 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1541 LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1542 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1543 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1544 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1545 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1546#endif
1547
1548 return VINF_SUCCESS;
1549 }
1550
1551 LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1552 return rc;
1553}
1554
1555
1556/**
1557 * Init statistics
1558 */
1559static void pgmR3InitStats(PVM pVM)
1560{
1561 PPGM pPGM = &pVM->pgm.s;
1562 int rc;
1563
1564 /* Common - misc variables */
1565 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1566 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1567 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1568 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1569 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1570 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1571 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1572 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1573 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1574 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1575 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1576 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1577
1578 /* Live save */
1579 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1580 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1581 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1582 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1583 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1584 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1585 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1586 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1587 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1588 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1589 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1590 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1591 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1592 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1593 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1594 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1595 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1596 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1597
1598#ifdef VBOX_WITH_STATISTICS
1599
1600# define PGM_REG_COUNTER(a, b, c) \
1601 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1602 AssertRC(rc);
1603
1604# define PGM_REG_COUNTER_BYTES(a, b, c) \
1605 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1606 AssertRC(rc);
1607
1608# define PGM_REG_PROFILE(a, b, c) \
1609 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1610 AssertRC(rc);
1611
1612 PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1613 PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1614 PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1615 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1616 PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1617 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1618 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1619 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1620 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1621 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1622
1623 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1624 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1625 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1626 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1627 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1628 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1629 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1630 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1631 PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1632 PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1633
1634 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1635 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1636 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1637 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1638
1639 PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1640 PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1641 PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1642 PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1643
1644 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1645 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1646/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1647 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1648 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1649/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1650
1651 PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1652 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1653 PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1654 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1655 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1656 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1657 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1658 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1659
1660 /* GC only: */
1661 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1662 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1663 PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1664 PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1665
1666 PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1667 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1668 PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1669 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1670 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1671 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1672 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1673 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1674
1675# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1676 PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1677 PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1678 PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1679 PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1680 PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1681 PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1682# endif
1683
1684# undef PGM_REG_COUNTER
1685# undef PGM_REG_PROFILE
1686#endif
1687
1688 /*
1689 * Note! The layout below matches the member layout exactly!
1690 */
1691
1692 /*
1693 * Common - stats
1694 */
1695 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1696 {
1697 PVMCPU pVCpu = &pVM->aCpus[i];
1698 PPGMCPU pPGM = &pVCpu->pgm.s;
1699
1700#define PGM_REG_COUNTER(a, b, c) \
1701 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1702 AssertRC(rc);
1703#define PGM_REG_PROFILE(a, b, c) \
1704 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1705 AssertRC(rc);
1706
1707 PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1708
1709#ifdef VBOX_WITH_STATISTICS
1710
1711# if 0 /* rarely useful; leave for debugging. */
1712 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1713 STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1714 "The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1715 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1716 STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1717 "The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1718# endif
1719 /* R0 only: */
1720 PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1721 PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1722 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1723 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1724 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1725 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1726 PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1727 PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1728 PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1729 PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1730 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1731 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1732 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1733 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1734 PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1735 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1736 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1737 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1738 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1739 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1740 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1741 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1742 //PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1743 PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1744 PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1745 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1746 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1747 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1748 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1749 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1750 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1751 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1752 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1753 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1754 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1755 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1756
1757 /* RZ only: */
1758 PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1759 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1760 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1761 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1762 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1763 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1764 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1765 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1766 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1767 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1768 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1769 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1770 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1771 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1772 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1773 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1774 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1775 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1776 PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1777 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1778 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1779 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1780 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1781 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1782 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1783 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1784 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1785 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1786 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1787 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1788 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1789 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1790 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1791 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1792 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1793 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1794 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1795 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1796 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1797 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1798 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1799 PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1800 PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1801#if 0 /* rarely useful; leave for debugging. */
1802 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1803 STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1804 "The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1805#endif
1806 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1807 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1808 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1809 PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1810 PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1811
1812 /* HC only: */
1813
1814 /* RZ & R3: */
1815 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1816 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1817 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1818 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1819 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1820 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1821 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1822 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1823 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1824 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1825 PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1826 PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1827 PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1828 PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1829 PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1830 PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1831 PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1832 PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1833 PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1834 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1835 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1836 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1837 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1838 PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1839 PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1840 PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1841 PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1842 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1843 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1844 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1845 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1846 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1847 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1848 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1849 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1850 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1851 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1852 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%d/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1853 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%d/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1854 PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1855 PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1856 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1857 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1858 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1859 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1860 PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1861
1862 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1863 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1864 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1865 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1866 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1867 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1868 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1869 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1870 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1871 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1872 PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1873 PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1874 PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1875 PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1876 PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1877 PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1878 PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1879 PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1880 PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1881 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1882 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1883 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1884 PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1885 PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1886 PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1887 PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1888 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1889 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1890 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1891 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1892 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1893 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1894 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1895 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1896 PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1897 PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1898 PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1899 PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1900 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1901 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1902 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1903 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1904 PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1905#endif /* VBOX_WITH_STATISTICS */
1906
1907#undef PGM_REG_PROFILE
1908#undef PGM_REG_COUNTER
1909
1910 }
1911}
1912
1913
1914/**
1915 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1916 *
1917 * The dynamic mapping area will also be allocated and initialized at this
1918 * time. We could allocate it during PGMR3Init of course, but the mapping
1919 * wouldn't be allocated at that time preventing us from setting up the
1920 * page table entries with the dummy page.
1921 *
1922 * @returns VBox status code.
1923 * @param pVM VM handle.
1924 */
1925VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1926{
1927 RTGCPTR GCPtr;
1928 int rc;
1929
1930 /*
1931 * Reserve space for the dynamic mappings.
1932 */
1933 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1934 if (RT_SUCCESS(rc))
1935 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1936
1937 if ( RT_SUCCESS(rc)
1938 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1939 {
1940 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1941 if (RT_SUCCESS(rc))
1942 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1943 }
1944 if (RT_SUCCESS(rc))
1945 {
1946 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1947 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1948 }
1949 return rc;
1950}
1951
1952
1953/**
1954 * Ring-3 init finalizing.
1955 *
1956 * @returns VBox status code.
1957 * @param pVM The VM handle.
1958 */
1959VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1960{
1961 int rc;
1962
1963 /*
1964 * Reserve space for the dynamic mappings.
1965 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
1966 */
1967 /* get the pointer to the page table entries. */
1968 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1969 AssertRelease(pMapping);
1970 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1971 const unsigned iPT = off >> X86_PD_SHIFT;
1972 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1973 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1974 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1975
1976 /* init cache */
1977 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1978 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1979 pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1980
1981 for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1982 {
1983 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1984 AssertRCReturn(rc, rc);
1985 }
1986
1987 /*
1988 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1989 * Intel only goes up to 36 bits, so we stick to 36 as well.
1990 */
1991 /** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1992 uint32_t u32Dummy, u32Features;
1993 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1994
1995 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1996 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1997 else
1998 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1999
2000 /*
2001 * Allocate memory if we're supposed to do that.
2002 */
2003 if (pVM->pgm.s.fRamPreAlloc)
2004 rc = pgmR3PhysRamPreAllocate(pVM);
2005
2006 LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2007 return rc;
2008}
2009
2010
2011/**
2012 * Applies relocations to data and code managed by this component.
2013 *
2014 * This function will be called at init and whenever the VMM need to relocate it
2015 * self inside the GC.
2016 *
2017 * @param pVM The VM.
2018 * @param offDelta Relocation delta relative to old location.
2019 */
2020VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2021{
2022 LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2023
2024 /*
2025 * Paging stuff.
2026 */
2027 pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2028
2029 pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2030
2031 /* Shadow, guest and both mode switch & relocation for each VCPU. */
2032 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2033 {
2034 PVMCPU pVCpu = &pVM->aCpus[i];
2035
2036 pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2037
2038 PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2039 PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2040 PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2041 }
2042
2043 /*
2044 * Trees.
2045 */
2046 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2047
2048 /*
2049 * Ram ranges.
2050 */
2051 if (pVM->pgm.s.pRamRangesR3)
2052 {
2053 /* Update the pSelfRC pointers and relink them. */
2054 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2055 if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2056 pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2057 pgmR3PhysRelinkRamRanges(pVM);
2058 }
2059
2060 /*
2061 * Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2062 * be mapped and thus not included in the above exercise.
2063 */
2064 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2065 if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2066 pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2067
2068 /*
2069 * Update the two page directories with all page table mappings.
2070 * (One or more of them have changed, that's why we're here.)
2071 */
2072 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2073 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2074 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2075
2076 /* Relocate GC addresses of Page Tables. */
2077 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2078 {
2079 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2080 {
2081 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2082 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2083 }
2084 }
2085
2086 /*
2087 * Dynamic page mapping area.
2088 */
2089 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2090 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2091 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2092
2093 /*
2094 * The Zero page.
2095 */
2096 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2097#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2098 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
2099#else
2100 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2101#endif
2102
2103 /*
2104 * Physical and virtual handlers.
2105 */
2106 RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2107 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2108 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2109
2110 /*
2111 * The page pool.
2112 */
2113 pgmR3PoolRelocate(pVM);
2114}
2115
2116
2117/**
2118 * Callback function for relocating a physical access handler.
2119 *
2120 * @returns 0 (continue enum)
2121 * @param pNode Pointer to a PGMPHYSHANDLER node.
2122 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2123 * not certain the delta will fit in a void pointer for all possible configs.
2124 */
2125static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2126{
2127 PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2128 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2129 if (pHandler->pfnHandlerRC)
2130 pHandler->pfnHandlerRC += offDelta;
2131 if (pHandler->pvUserRC >= 0x10000)
2132 pHandler->pvUserRC += offDelta;
2133 return 0;
2134}
2135
2136
2137/**
2138 * Callback function for relocating a virtual access handler.
2139 *
2140 * @returns 0 (continue enum)
2141 * @param pNode Pointer to a PGMVIRTHANDLER node.
2142 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2143 * not certain the delta will fit in a void pointer for all possible configs.
2144 */
2145static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2146{
2147 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2148 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2149 Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2150 || pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2151 Assert(pHandler->pfnHandlerRC);
2152 pHandler->pfnHandlerRC += offDelta;
2153 return 0;
2154}
2155
2156
2157/**
2158 * Callback function for relocating a virtual access handler for the hypervisor mapping.
2159 *
2160 * @returns 0 (continue enum)
2161 * @param pNode Pointer to a PGMVIRTHANDLER node.
2162 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2163 * not certain the delta will fit in a void pointer for all possible configs.
2164 */
2165static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2166{
2167 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2168 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2169 Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2170 Assert(pHandler->pfnHandlerRC);
2171 pHandler->pfnHandlerRC += offDelta;
2172 return 0;
2173}
2174
2175
2176/**
2177 * The VM is being reset.
2178 *
2179 * For the PGM component this means that any PD write monitors
2180 * needs to be removed.
2181 *
2182 * @param pVM VM handle.
2183 */
2184VMMR3DECL(void) PGMR3Reset(PVM pVM)
2185{
2186 int rc;
2187
2188 LogFlow(("PGMR3Reset:\n"));
2189 VM_ASSERT_EMT(pVM);
2190
2191 pgmLock(pVM);
2192
2193 /*
2194 * Unfix any fixed mappings and disable CR3 monitoring.
2195 */
2196 pVM->pgm.s.fMappingsFixed = false;
2197 pVM->pgm.s.GCPtrMappingFixed = 0;
2198 pVM->pgm.s.cbMappingFixed = 0;
2199
2200 /* Exit the guest paging mode before the pgm pool gets reset.
2201 * Important to clean up the amd64 case.
2202 */
2203 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2204 {
2205 PVMCPU pVCpu = &pVM->aCpus[i];
2206 rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2207 AssertRC(rc);
2208 }
2209
2210#ifdef DEBUG
2211 DBGFR3InfoLog(pVM, "mappings", NULL);
2212 DBGFR3InfoLog(pVM, "handlers", "all nostat");
2213#endif
2214
2215 /*
2216 * Switch mode back to real mode. (before resetting the pgm pool!)
2217 */
2218 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2219 {
2220 PVMCPU pVCpu = &pVM->aCpus[i];
2221
2222 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2223 AssertRC(rc);
2224
2225 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2226 }
2227
2228 /*
2229 * Reset the shadow page pool.
2230 */
2231 pgmR3PoolReset(pVM);
2232
2233 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2234 {
2235 PVMCPU pVCpu = &pVM->aCpus[i];
2236
2237 /*
2238 * Re-init other members.
2239 */
2240 pVCpu->pgm.s.fA20Enabled = true;
2241
2242 /*
2243 * Clear the FFs PGM owns.
2244 */
2245 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2246 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2247 }
2248
2249 /*
2250 * Reset (zero) RAM pages.
2251 */
2252 rc = pgmR3PhysRamReset(pVM);
2253 if (RT_SUCCESS(rc))
2254 {
2255 /*
2256 * Reset (zero) shadow ROM pages.
2257 */
2258 rc = pgmR3PhysRomReset(pVM);
2259 }
2260
2261 pgmUnlock(pVM);
2262 //return rc;
2263 AssertReleaseRC(rc);
2264}
2265
2266
2267#ifdef VBOX_STRICT
2268/**
2269 * VM state change callback for clearing fNoMorePhysWrites after
2270 * a snapshot has been created.
2271 */
2272static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2273{
2274 if ( enmState == VMSTATE_RUNNING
2275 || enmState == VMSTATE_RESUMING)
2276 pVM->pgm.s.fNoMorePhysWrites = false;
2277}
2278#endif
2279
2280
2281/**
2282 * Terminates the PGM.
2283 *
2284 * @returns VBox status code.
2285 * @param pVM Pointer to VM structure.
2286 */
2287VMMR3DECL(int) PGMR3Term(PVM pVM)
2288{
2289 PGMDeregisterStringFormatTypes();
2290 return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2291}
2292
2293
2294/**
2295 * Terminates the per-VCPU PGM.
2296 *
2297 * Termination means cleaning up and freeing all resources,
2298 * the VM it self is at this point powered off or suspended.
2299 *
2300 * @returns VBox status code.
2301 * @param pVM The VM to operate on.
2302 */
2303VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2304{
2305 return 0;
2306}
2307
2308
2309/**
2310 * Show paging mode.
2311 *
2312 * @param pVM VM Handle.
2313 * @param pHlp The info helpers.
2314 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2315 */
2316static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2317{
2318 /* digest argument. */
2319 bool fGuest, fShadow, fHost;
2320 if (pszArgs)
2321 pszArgs = RTStrStripL(pszArgs);
2322 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2323 fShadow = fHost = fGuest = true;
2324 else
2325 {
2326 fShadow = fHost = fGuest = false;
2327 if (strstr(pszArgs, "guest"))
2328 fGuest = true;
2329 if (strstr(pszArgs, "shadow"))
2330 fShadow = true;
2331 if (strstr(pszArgs, "host"))
2332 fHost = true;
2333 }
2334
2335 /** @todo SMP support! */
2336 /* print info. */
2337 if (fGuest)
2338 pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2339 PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2340 pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2341 if (fShadow)
2342 pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2343 if (fHost)
2344 {
2345 const char *psz;
2346 switch (pVM->pgm.s.enmHostMode)
2347 {
2348 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2349 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2350 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2351 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2352 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2353 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2354 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2355 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2356 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2357 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2358 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2359 default: psz = "unknown"; break;
2360 }
2361 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2362 }
2363}
2364
2365
2366/**
2367 * Dump registered MMIO ranges to the log.
2368 *
2369 * @param pVM VM Handle.
2370 * @param pHlp The info helpers.
2371 * @param pszArgs Arguments, ignored.
2372 */
2373static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2374{
2375 NOREF(pszArgs);
2376 pHlp->pfnPrintf(pHlp,
2377 "RAM ranges (pVM=%p)\n"
2378 "%.*s %.*s\n",
2379 pVM,
2380 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2381 sizeof(RTHCPTR) * 2, "pvHC ");
2382
2383 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2384 pHlp->pfnPrintf(pHlp,
2385 "%RGp-%RGp %RHv %s\n",
2386 pCur->GCPhys,
2387 pCur->GCPhysLast,
2388 pCur->pvR3,
2389 pCur->pszDesc);
2390}
2391
2392/**
2393 * Dump the page directory to the log.
2394 *
2395 * @param pVM VM Handle.
2396 * @param pHlp The info helpers.
2397 * @param pszArgs Arguments, ignored.
2398 */
2399static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2400{
2401 /** @todo SMP support!! */
2402 PVMCPU pVCpu = &pVM->aCpus[0];
2403
2404/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2405 /* Big pages supported? */
2406 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2407
2408 /* Global pages supported? */
2409 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2410
2411 NOREF(pszArgs);
2412
2413 /*
2414 * Get page directory addresses.
2415 */
2416 PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2417 Assert(pPDSrc);
2418 Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2419
2420 /*
2421 * Iterate the page directory.
2422 */
2423 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2424 {
2425 X86PDE PdeSrc = pPDSrc->a[iPD];
2426 if (PdeSrc.n.u1Present)
2427 {
2428 if (PdeSrc.b.u1Size && fPSE)
2429 pHlp->pfnPrintf(pHlp,
2430 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2431 iPD,
2432 pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2433 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2434 else
2435 pHlp->pfnPrintf(pHlp,
2436 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2437 iPD,
2438 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2439 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2440 }
2441 }
2442}
2443
2444
2445/**
2446 * Service a VMMCALLRING3_PGM_LOCK call.
2447 *
2448 * @returns VBox status code.
2449 * @param pVM The VM handle.
2450 */
2451VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2452{
2453 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2454 AssertRC(rc);
2455 return rc;
2456}
2457
2458
2459/**
2460 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2461 *
2462 * @returns PGM_TYPE_*.
2463 * @param pgmMode The mode value to convert.
2464 */
2465DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2466{
2467 switch (pgmMode)
2468 {
2469 case PGMMODE_REAL: return PGM_TYPE_REAL;
2470 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2471 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2472 case PGMMODE_PAE:
2473 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2474 case PGMMODE_AMD64:
2475 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2476 case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2477 case PGMMODE_EPT: return PGM_TYPE_EPT;
2478 default:
2479 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2480 }
2481}
2482
2483
2484/**
2485 * Gets the index into the paging mode data array of a SHW+GST mode.
2486 *
2487 * @returns PGM::paPagingData index.
2488 * @param uShwType The shadow paging mode type.
2489 * @param uGstType The guest paging mode type.
2490 */
2491DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2492{
2493 Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2494 Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2495 return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2496 + (uGstType - PGM_TYPE_REAL);
2497}
2498
2499
2500/**
2501 * Gets the index into the paging mode data array of a SHW+GST mode.
2502 *
2503 * @returns PGM::paPagingData index.
2504 * @param enmShw The shadow paging mode.
2505 * @param enmGst The guest paging mode.
2506 */
2507DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2508{
2509 Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2510 Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2511 return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2512}
2513
2514
2515/**
2516 * Calculates the max data index.
2517 * @returns The number of entries in the paging data array.
2518 */
2519DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2520{
2521 return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2522}
2523
2524
2525/**
2526 * Initializes the paging mode data kept in PGM::paModeData.
2527 *
2528 * @param pVM The VM handle.
2529 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2530 * This is used early in the init process to avoid trouble with PDM
2531 * not being initialized yet.
2532 */
2533static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2534{
2535 PPGMMODEDATA pModeData;
2536 int rc;
2537
2538 /*
2539 * Allocate the array on the first call.
2540 */
2541 if (!pVM->pgm.s.paModeData)
2542 {
2543 pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2544 AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2545 }
2546
2547 /*
2548 * Initialize the array entries.
2549 */
2550 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2551 pModeData->uShwType = PGM_TYPE_32BIT;
2552 pModeData->uGstType = PGM_TYPE_REAL;
2553 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2554 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2555 rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2556
2557 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2558 pModeData->uShwType = PGM_TYPE_32BIT;
2559 pModeData->uGstType = PGM_TYPE_PROT;
2560 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2561 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2562 rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2563
2564 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2565 pModeData->uShwType = PGM_TYPE_32BIT;
2566 pModeData->uGstType = PGM_TYPE_32BIT;
2567 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2568 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2569 rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2570
2571 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2572 pModeData->uShwType = PGM_TYPE_PAE;
2573 pModeData->uGstType = PGM_TYPE_REAL;
2574 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2575 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2576 rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2577
2578 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2579 pModeData->uShwType = PGM_TYPE_PAE;
2580 pModeData->uGstType = PGM_TYPE_PROT;
2581 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2582 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2583 rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2584
2585 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2586 pModeData->uShwType = PGM_TYPE_PAE;
2587 pModeData->uGstType = PGM_TYPE_32BIT;
2588 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2589 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2590 rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2591
2592 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2593 pModeData->uShwType = PGM_TYPE_PAE;
2594 pModeData->uGstType = PGM_TYPE_PAE;
2595 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2596 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2597 rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2598
2599#ifdef VBOX_WITH_64_BITS_GUESTS
2600 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2601 pModeData->uShwType = PGM_TYPE_AMD64;
2602 pModeData->uGstType = PGM_TYPE_AMD64;
2603 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2604 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2605 rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2606#endif
2607
2608 /* The nested paging mode. */
2609 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2610 pModeData->uShwType = PGM_TYPE_NESTED;
2611 pModeData->uGstType = PGM_TYPE_REAL;
2612 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2613 rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2614
2615 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2616 pModeData->uShwType = PGM_TYPE_NESTED;
2617 pModeData->uGstType = PGM_TYPE_PROT;
2618 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2619 rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2620
2621 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2622 pModeData->uShwType = PGM_TYPE_NESTED;
2623 pModeData->uGstType = PGM_TYPE_32BIT;
2624 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2625 rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2626
2627 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2628 pModeData->uShwType = PGM_TYPE_NESTED;
2629 pModeData->uGstType = PGM_TYPE_PAE;
2630 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2631 rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2632
2633#ifdef VBOX_WITH_64_BITS_GUESTS
2634 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2635 pModeData->uShwType = PGM_TYPE_NESTED;
2636 pModeData->uGstType = PGM_TYPE_AMD64;
2637 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2638 rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2639#endif
2640
2641 /* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2642 switch (pVM->pgm.s.enmHostMode)
2643 {
2644#if HC_ARCH_BITS == 32
2645 case SUPPAGINGMODE_32_BIT:
2646 case SUPPAGINGMODE_32_BIT_GLOBAL:
2647 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2648 {
2649 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2650 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2651 }
2652# ifdef VBOX_WITH_64_BITS_GUESTS
2653 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2654 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2655# endif
2656 break;
2657
2658 case SUPPAGINGMODE_PAE:
2659 case SUPPAGINGMODE_PAE_NX:
2660 case SUPPAGINGMODE_PAE_GLOBAL:
2661 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2662 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2663 {
2664 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2665 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2666 }
2667# ifdef VBOX_WITH_64_BITS_GUESTS
2668 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2669 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670# endif
2671 break;
2672#endif /* HC_ARCH_BITS == 32 */
2673
2674#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
2675 case SUPPAGINGMODE_AMD64:
2676 case SUPPAGINGMODE_AMD64_GLOBAL:
2677 case SUPPAGINGMODE_AMD64_NX:
2678 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2679# ifdef VBOX_WITH_64_BITS_GUESTS
2680 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2681# else
2682 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2683# endif
2684 {
2685 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2686 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2687 }
2688 break;
2689#endif /* HC_ARCH_BITS == 64 || RT_OS_DARWIN */
2690
2691 default:
2692 AssertFailed();
2693 break;
2694 }
2695
2696 /* Extended paging (EPT) / Intel VT-x */
2697 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2698 pModeData->uShwType = PGM_TYPE_EPT;
2699 pModeData->uGstType = PGM_TYPE_REAL;
2700 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2701 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702 rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703
2704 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2705 pModeData->uShwType = PGM_TYPE_EPT;
2706 pModeData->uGstType = PGM_TYPE_PROT;
2707 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2708 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709 rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2710
2711 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2712 pModeData->uShwType = PGM_TYPE_EPT;
2713 pModeData->uGstType = PGM_TYPE_32BIT;
2714 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2716 rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2717
2718 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2719 pModeData->uShwType = PGM_TYPE_EPT;
2720 pModeData->uGstType = PGM_TYPE_PAE;
2721 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2723 rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2724
2725#ifdef VBOX_WITH_64_BITS_GUESTS
2726 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2727 pModeData->uShwType = PGM_TYPE_EPT;
2728 pModeData->uGstType = PGM_TYPE_AMD64;
2729 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2730 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2731 rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732#endif
2733 return VINF_SUCCESS;
2734}
2735
2736
2737/**
2738 * Switch to different (or relocated in the relocate case) mode data.
2739 *
2740 * @param pVM The VM handle.
2741 * @param pVCpu The VMCPU to operate on.
2742 * @param enmShw The the shadow paging mode.
2743 * @param enmGst The the guest paging mode.
2744 */
2745static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2746{
2747 PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2748
2749 Assert(pModeData->uGstType == pgmModeToType(enmGst));
2750 Assert(pModeData->uShwType == pgmModeToType(enmShw));
2751
2752 /* shadow */
2753 pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2754 pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2755 pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2756 Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2757 pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2758
2759 pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2760 pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2761
2762 pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2763 pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2764
2765
2766 /* guest */
2767 pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2768 pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2769 pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2770 Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2771 pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2772 pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2773 pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2774 pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2775 pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2776 pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2777 pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2778 pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2779
2780 /* both */
2781 pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2782 pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2783 pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2784 Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2785 pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2786 pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2787 pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2788#ifdef VBOX_STRICT
2789 pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2790#endif
2791 pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2792 pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2793
2794 pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2795 pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2796 pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2797 pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2798 pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2799 pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2800#ifdef VBOX_STRICT
2801 pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2802#endif
2803 pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2804 pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2805
2806 pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2807 pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2808 pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2809 pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2810 pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2811 pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2812#ifdef VBOX_STRICT
2813 pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2814#endif
2815 pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2816 pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2817}
2818
2819
2820/**
2821 * Calculates the shadow paging mode.
2822 *
2823 * @returns The shadow paging mode.
2824 * @param pVM VM handle.
2825 * @param enmGuestMode The guest mode.
2826 * @param enmHostMode The host mode.
2827 * @param enmShadowMode The current shadow mode.
2828 * @param penmSwitcher Where to store the switcher to use.
2829 * VMMSWITCHER_INVALID means no change.
2830 */
2831static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2832{
2833 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2834 switch (enmGuestMode)
2835 {
2836 /*
2837 * When switching to real or protected mode we don't change
2838 * anything since it's likely that we'll switch back pretty soon.
2839 *
2840 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2841 * and is supposed to determine which shadow paging and switcher to
2842 * use during init.
2843 */
2844 case PGMMODE_REAL:
2845 case PGMMODE_PROTECTED:
2846 if ( enmShadowMode != PGMMODE_INVALID
2847 && !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2848 break; /* (no change) */
2849
2850 switch (enmHostMode)
2851 {
2852 case SUPPAGINGMODE_32_BIT:
2853 case SUPPAGINGMODE_32_BIT_GLOBAL:
2854 enmShadowMode = PGMMODE_32_BIT;
2855 enmSwitcher = VMMSWITCHER_32_TO_32;
2856 break;
2857
2858 case SUPPAGINGMODE_PAE:
2859 case SUPPAGINGMODE_PAE_NX:
2860 case SUPPAGINGMODE_PAE_GLOBAL:
2861 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2862 enmShadowMode = PGMMODE_PAE;
2863 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2864#ifdef DEBUG_bird
2865 if (RTEnvExist("VBOX_32BIT"))
2866 {
2867 enmShadowMode = PGMMODE_32_BIT;
2868 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2869 }
2870#endif
2871 break;
2872
2873 case SUPPAGINGMODE_AMD64:
2874 case SUPPAGINGMODE_AMD64_GLOBAL:
2875 case SUPPAGINGMODE_AMD64_NX:
2876 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2877 enmShadowMode = PGMMODE_PAE;
2878 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2879#ifdef DEBUG_bird
2880 if (RTEnvExist("VBOX_32BIT"))
2881 {
2882 enmShadowMode = PGMMODE_32_BIT;
2883 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2884 }
2885#endif
2886 break;
2887
2888 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2889 }
2890 break;
2891
2892 case PGMMODE_32_BIT:
2893 switch (enmHostMode)
2894 {
2895 case SUPPAGINGMODE_32_BIT:
2896 case SUPPAGINGMODE_32_BIT_GLOBAL:
2897 enmShadowMode = PGMMODE_32_BIT;
2898 enmSwitcher = VMMSWITCHER_32_TO_32;
2899 break;
2900
2901 case SUPPAGINGMODE_PAE:
2902 case SUPPAGINGMODE_PAE_NX:
2903 case SUPPAGINGMODE_PAE_GLOBAL:
2904 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2905 enmShadowMode = PGMMODE_PAE;
2906 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2907#ifdef DEBUG_bird
2908 if (RTEnvExist("VBOX_32BIT"))
2909 {
2910 enmShadowMode = PGMMODE_32_BIT;
2911 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2912 }
2913#endif
2914 break;
2915
2916 case SUPPAGINGMODE_AMD64:
2917 case SUPPAGINGMODE_AMD64_GLOBAL:
2918 case SUPPAGINGMODE_AMD64_NX:
2919 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2920 enmShadowMode = PGMMODE_PAE;
2921 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2922#ifdef DEBUG_bird
2923 if (RTEnvExist("VBOX_32BIT"))
2924 {
2925 enmShadowMode = PGMMODE_32_BIT;
2926 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2927 }
2928#endif
2929 break;
2930
2931 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2932 }
2933 break;
2934
2935 case PGMMODE_PAE:
2936 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2937 switch (enmHostMode)
2938 {
2939 case SUPPAGINGMODE_32_BIT:
2940 case SUPPAGINGMODE_32_BIT_GLOBAL:
2941 enmShadowMode = PGMMODE_PAE;
2942 enmSwitcher = VMMSWITCHER_32_TO_PAE;
2943 break;
2944
2945 case SUPPAGINGMODE_PAE:
2946 case SUPPAGINGMODE_PAE_NX:
2947 case SUPPAGINGMODE_PAE_GLOBAL:
2948 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2949 enmShadowMode = PGMMODE_PAE;
2950 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2951 break;
2952
2953 case SUPPAGINGMODE_AMD64:
2954 case SUPPAGINGMODE_AMD64_GLOBAL:
2955 case SUPPAGINGMODE_AMD64_NX:
2956 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2957 enmShadowMode = PGMMODE_PAE;
2958 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2959 break;
2960
2961 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2962 }
2963 break;
2964
2965 case PGMMODE_AMD64:
2966 case PGMMODE_AMD64_NX:
2967 switch (enmHostMode)
2968 {
2969 case SUPPAGINGMODE_32_BIT:
2970 case SUPPAGINGMODE_32_BIT_GLOBAL:
2971 enmShadowMode = PGMMODE_AMD64;
2972 enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2973 break;
2974
2975 case SUPPAGINGMODE_PAE:
2976 case SUPPAGINGMODE_PAE_NX:
2977 case SUPPAGINGMODE_PAE_GLOBAL:
2978 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2979 enmShadowMode = PGMMODE_AMD64;
2980 enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2981 break;
2982
2983 case SUPPAGINGMODE_AMD64:
2984 case SUPPAGINGMODE_AMD64_GLOBAL:
2985 case SUPPAGINGMODE_AMD64_NX:
2986 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2987 enmShadowMode = PGMMODE_AMD64;
2988 enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2989 break;
2990
2991 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2992 }
2993 break;
2994
2995
2996 default:
2997 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2998 return PGMMODE_INVALID;
2999 }
3000 /* Override the shadow mode is nested paging is active. */
3001 if (HWACCMIsNestedPagingActive(pVM))
3002 enmShadowMode = HWACCMGetShwPagingMode(pVM);
3003
3004 *penmSwitcher = enmSwitcher;
3005 return enmShadowMode;
3006}
3007
3008
3009/**
3010 * Performs the actual mode change.
3011 * This is called by PGMChangeMode and pgmR3InitPaging().
3012 *
3013 * @returns VBox status code. May suspend or power off the VM on error, but this
3014 * will trigger using FFs and not status codes.
3015 *
3016 * @param pVM VM handle.
3017 * @param pVCpu The VMCPU to operate on.
3018 * @param enmGuestMode The new guest mode. This is assumed to be different from
3019 * the current mode.
3020 */
3021VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3022{
3023 bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3024 bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3025
3026 Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3027 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3028
3029 /*
3030 * Calc the shadow mode and switcher.
3031 */
3032 VMMSWITCHER enmSwitcher;
3033 PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3034 if (enmSwitcher != VMMSWITCHER_INVALID)
3035 {
3036 /*
3037 * Select new switcher.
3038 */
3039 int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3040 if (RT_FAILURE(rc))
3041 {
3042 AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3043 return rc;
3044 }
3045 }
3046
3047 /*
3048 * Exit old mode(s).
3049 */
3050#if HC_ARCH_BITS == 32
3051 /* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3052 const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3053 && enmShadowMode == PGMMODE_NESTED);
3054#else
3055 const bool fForceShwEnterExit = false;
3056#endif
3057 /* shadow */
3058 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3059 || fForceShwEnterExit)
3060 {
3061 LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3062 if (PGM_SHW_PFN(Exit, pVCpu))
3063 {
3064 int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3065 if (RT_FAILURE(rc))
3066 {
3067 AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3068 return rc;
3069 }
3070 }
3071
3072 }
3073 else
3074 LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3075
3076 /* guest */
3077 if (PGM_GST_PFN(Exit, pVCpu))
3078 {
3079 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3080 if (RT_FAILURE(rc))
3081 {
3082 AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3083 return rc;
3084 }
3085 }
3086
3087 /*
3088 * Load new paging mode data.
3089 */
3090 pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3091
3092 /*
3093 * Enter new shadow mode (if changed).
3094 */
3095 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3096 || fForceShwEnterExit)
3097 {
3098 int rc;
3099 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3100 switch (enmShadowMode)
3101 {
3102 case PGMMODE_32_BIT:
3103 rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3104 break;
3105 case PGMMODE_PAE:
3106 case PGMMODE_PAE_NX:
3107 rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3108 break;
3109 case PGMMODE_AMD64:
3110 case PGMMODE_AMD64_NX:
3111 rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3112 break;
3113 case PGMMODE_NESTED:
3114 rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3115 break;
3116 case PGMMODE_EPT:
3117 rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3118 break;
3119 case PGMMODE_REAL:
3120 case PGMMODE_PROTECTED:
3121 default:
3122 AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3123 return VERR_INTERNAL_ERROR;
3124 }
3125 if (RT_FAILURE(rc))
3126 {
3127 AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3128 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3129 return rc;
3130 }
3131 }
3132
3133 /*
3134 * Always flag the necessary updates
3135 */
3136 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3137
3138 /*
3139 * Enter the new guest and shadow+guest modes.
3140 */
3141 int rc = -1;
3142 int rc2 = -1;
3143 RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3144 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3145 switch (enmGuestMode)
3146 {
3147 case PGMMODE_REAL:
3148 rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3149 switch (pVCpu->pgm.s.enmShadowMode)
3150 {
3151 case PGMMODE_32_BIT:
3152 rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3153 break;
3154 case PGMMODE_PAE:
3155 case PGMMODE_PAE_NX:
3156 rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3157 break;
3158 case PGMMODE_NESTED:
3159 rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3160 break;
3161 case PGMMODE_EPT:
3162 rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3163 break;
3164 case PGMMODE_AMD64:
3165 case PGMMODE_AMD64_NX:
3166 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3167 default: AssertFailed(); break;
3168 }
3169 break;
3170
3171 case PGMMODE_PROTECTED:
3172 rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3173 switch (pVCpu->pgm.s.enmShadowMode)
3174 {
3175 case PGMMODE_32_BIT:
3176 rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3177 break;
3178 case PGMMODE_PAE:
3179 case PGMMODE_PAE_NX:
3180 rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3181 break;
3182 case PGMMODE_NESTED:
3183 rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3184 break;
3185 case PGMMODE_EPT:
3186 rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3187 break;
3188 case PGMMODE_AMD64:
3189 case PGMMODE_AMD64_NX:
3190 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3191 default: AssertFailed(); break;
3192 }
3193 break;
3194
3195 case PGMMODE_32_BIT:
3196 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3197 rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3198 switch (pVCpu->pgm.s.enmShadowMode)
3199 {
3200 case PGMMODE_32_BIT:
3201 rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3202 break;
3203 case PGMMODE_PAE:
3204 case PGMMODE_PAE_NX:
3205 rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3206 break;
3207 case PGMMODE_NESTED:
3208 rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3209 break;
3210 case PGMMODE_EPT:
3211 rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3212 break;
3213 case PGMMODE_AMD64:
3214 case PGMMODE_AMD64_NX:
3215 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3216 default: AssertFailed(); break;
3217 }
3218 break;
3219
3220 case PGMMODE_PAE_NX:
3221 case PGMMODE_PAE:
3222 {
3223 uint32_t u32Dummy, u32Features;
3224
3225 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3226 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3227 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3228 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3229
3230 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3231 rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3232 switch (pVCpu->pgm.s.enmShadowMode)
3233 {
3234 case PGMMODE_PAE:
3235 case PGMMODE_PAE_NX:
3236 rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3237 break;
3238 case PGMMODE_NESTED:
3239 rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3240 break;
3241 case PGMMODE_EPT:
3242 rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3243 break;
3244 case PGMMODE_32_BIT:
3245 case PGMMODE_AMD64:
3246 case PGMMODE_AMD64_NX:
3247 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3248 default: AssertFailed(); break;
3249 }
3250 break;
3251 }
3252
3253#ifdef VBOX_WITH_64_BITS_GUESTS
3254 case PGMMODE_AMD64_NX:
3255 case PGMMODE_AMD64:
3256 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3257 rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3258 switch (pVCpu->pgm.s.enmShadowMode)
3259 {
3260 case PGMMODE_AMD64:
3261 case PGMMODE_AMD64_NX:
3262 rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3263 break;
3264 case PGMMODE_NESTED:
3265 rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3266 break;
3267 case PGMMODE_EPT:
3268 rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3269 break;
3270 case PGMMODE_32_BIT:
3271 case PGMMODE_PAE:
3272 case PGMMODE_PAE_NX:
3273 AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3274 default: AssertFailed(); break;
3275 }
3276 break;
3277#endif
3278
3279 default:
3280 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3281 rc = VERR_NOT_IMPLEMENTED;
3282 break;
3283 }
3284
3285 /* status codes. */
3286 AssertRC(rc);
3287 AssertRC(rc2);
3288 if (RT_SUCCESS(rc))
3289 {
3290 rc = rc2;
3291 if (RT_SUCCESS(rc)) /* no informational status codes. */
3292 rc = VINF_SUCCESS;
3293 }
3294
3295 /* Notify HWACCM as well. */
3296 HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3297 return rc;
3298}
3299
3300/**
3301 * Release the pgm lock if owned by the current VCPU
3302 *
3303 * @param pVM The VM to operate on.
3304 */
3305VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
3306{
3307 while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
3308 PDMCritSectLeave(&pVM->pgm.s.CritSect);
3309}
3310
3311/**
3312 * Called by pgmPoolFlushAllInt prior to flushing the pool.
3313 *
3314 * @returns VBox status code, fully asserted.
3315 * @param pVM The VM handle.
3316 * @param pVCpu The VMCPU to operate on.
3317 */
3318int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3319{
3320 /* Unmap the old CR3 value before flushing everything. */
3321 int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3322 AssertRC(rc);
3323
3324 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3325 rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3326 AssertRC(rc);
3327 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3328 return rc;
3329}
3330
3331
3332/**
3333 * Called by pgmPoolFlushAllInt after flushing the pool.
3334 *
3335 * @returns VBox status code, fully asserted.
3336 * @param pVM The VM handle.
3337 * @param pVCpu The VMCPU to operate on.
3338 */
3339int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3340{
3341 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3342 int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3343 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3344 AssertRCReturn(rc, rc);
3345 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3346
3347 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3348 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3349 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3350 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3351 return rc;
3352}
3353
3354
3355/**
3356 * Dumps a PAE shadow page table.
3357 *
3358 * @returns VBox status code (VINF_SUCCESS).
3359 * @param pVM The VM handle.
3360 * @param pPT Pointer to the page table.
3361 * @param u64Address The virtual address of the page table starts.
3362 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3363 * @param cMaxDepth The maxium depth.
3364 * @param pHlp Pointer to the output functions.
3365 */
3366static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3367{
3368 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3369 {
3370 X86PTEPAE Pte = pPT->a[i];
3371 if (Pte.n.u1Present)
3372 {
3373 pHlp->pfnPrintf(pHlp,
3374 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3375 ? "%016llx 3 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3376 : "%08llx 2 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3377 u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3378 Pte.n.u1Write ? 'W' : 'R',
3379 Pte.n.u1User ? 'U' : 'S',
3380 Pte.n.u1Accessed ? 'A' : '-',
3381 Pte.n.u1Dirty ? 'D' : '-',
3382 Pte.n.u1Global ? 'G' : '-',
3383 Pte.n.u1WriteThru ? "WT" : "--",
3384 Pte.n.u1CacheDisable? "CD" : "--",
3385 Pte.n.u1PAT ? "AT" : "--",
3386 Pte.n.u1NoExecute ? "NX" : "--",
3387 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3388 Pte.u & RT_BIT(10) ? '1' : '0',
3389 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3390 Pte.u & X86_PTE_PAE_PG_MASK);
3391 }
3392 }
3393 return VINF_SUCCESS;
3394}
3395
3396
3397/**
3398 * Dumps a PAE shadow page directory table.
3399 *
3400 * @returns VBox status code (VINF_SUCCESS).
3401 * @param pVM The VM handle.
3402 * @param HCPhys The physical address of the page directory table.
3403 * @param u64Address The virtual address of the page table starts.
3404 * @param cr4 The CR4, PSE is currently used.
3405 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3406 * @param cMaxDepth The maxium depth.
3407 * @param pHlp Pointer to the output functions.
3408 */
3409static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3410{
3411 PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3412 if (!pPD)
3413 {
3414 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3415 fLongMode ? 16 : 8, u64Address, HCPhys);
3416 return VERR_INVALID_PARAMETER;
3417 }
3418 const bool fBigPagesSupported = fLongMode || !!(cr4 & X86_CR4_PSE);
3419
3420 int rc = VINF_SUCCESS;
3421 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3422 {
3423 X86PDEPAE Pde = pPD->a[i];
3424 if (Pde.n.u1Present)
3425 {
3426 if (fBigPagesSupported && Pde.b.u1Size)
3427 pHlp->pfnPrintf(pHlp,
3428 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3429 ? "%016llx 2 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3430 : "%08llx 1 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3431 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3432 Pde.b.u1Write ? 'W' : 'R',
3433 Pde.b.u1User ? 'U' : 'S',
3434 Pde.b.u1Accessed ? 'A' : '-',
3435 Pde.b.u1Dirty ? 'D' : '-',
3436 Pde.b.u1Global ? 'G' : '-',
3437 Pde.b.u1WriteThru ? "WT" : "--",
3438 Pde.b.u1CacheDisable? "CD" : "--",
3439 Pde.b.u1PAT ? "AT" : "--",
3440 Pde.b.u1NoExecute ? "NX" : "--",
3441 Pde.u & RT_BIT_64(9) ? '1' : '0',
3442 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3443 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3444 Pde.u & X86_PDE_PAE_PG_MASK);
3445 else
3446 {
3447 pHlp->pfnPrintf(pHlp,
3448 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3449 ? "%016llx 2 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3450 : "%08llx 1 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3451 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3452 Pde.n.u1Write ? 'W' : 'R',
3453 Pde.n.u1User ? 'U' : 'S',
3454 Pde.n.u1Accessed ? 'A' : '-',
3455 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3456 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3457 Pde.n.u1WriteThru ? "WT" : "--",
3458 Pde.n.u1CacheDisable? "CD" : "--",
3459 Pde.n.u1NoExecute ? "NX" : "--",
3460 Pde.u & RT_BIT_64(9) ? '1' : '0',
3461 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3462 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3463 Pde.u & X86_PDE_PAE_PG_MASK);
3464 if (cMaxDepth >= 1)
3465 {
3466 /** @todo what about using the page pool for mapping PTs? */
3467 uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3468 RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3469 PX86PTPAE pPT = NULL;
3470 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3471 pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3472 else
3473 {
3474 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3475 {
3476 uint64_t off = u64AddressPT - pMap->GCPtr;
3477 if (off < pMap->cb)
3478 {
3479 const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3480 const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3481 if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3482 pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3483 fLongMode ? 16 : 8, u64AddressPT, iPDE,
3484 iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3485 pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3486 }
3487 }
3488 }
3489 int rc2 = VERR_INVALID_PARAMETER;
3490 if (pPT)
3491 rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3492 else
3493 pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3494 fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3495 if (rc2 < rc && RT_SUCCESS(rc))
3496 rc = rc2;
3497 }
3498 }
3499 }
3500 }
3501 return rc;
3502}
3503
3504
3505/**
3506 * Dumps a PAE shadow page directory pointer table.
3507 *
3508 * @returns VBox status code (VINF_SUCCESS).
3509 * @param pVM The VM handle.
3510 * @param HCPhys The physical address of the page directory pointer table.
3511 * @param u64Address The virtual address of the page table starts.
3512 * @param cr4 The CR4, PSE is currently used.
3513 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3514 * @param cMaxDepth The maxium depth.
3515 * @param pHlp Pointer to the output functions.
3516 */
3517static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3518{
3519 PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3520 if (!pPDPT)
3521 {
3522 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3523 fLongMode ? 16 : 8, u64Address, HCPhys);
3524 return VERR_INVALID_PARAMETER;
3525 }
3526
3527 int rc = VINF_SUCCESS;
3528 const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3529 for (unsigned i = 0; i < c; i++)
3530 {
3531 X86PDPE Pdpe = pPDPT->a[i];
3532 if (Pdpe.n.u1Present)
3533 {
3534 if (fLongMode)
3535 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3536 "%016llx 1 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3537 u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3538 Pdpe.lm.u1Write ? 'W' : 'R',
3539 Pdpe.lm.u1User ? 'U' : 'S',
3540 Pdpe.lm.u1Accessed ? 'A' : '-',
3541 Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3542 Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3543 Pdpe.lm.u1WriteThru ? "WT" : "--",
3544 Pdpe.lm.u1CacheDisable? "CD" : "--",
3545 Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3546 Pdpe.lm.u1NoExecute ? "NX" : "--",
3547 Pdpe.u & RT_BIT(9) ? '1' : '0',
3548 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3549 Pdpe.u & RT_BIT(11) ? '1' : '0',
3550 Pdpe.u & X86_PDPE_PG_MASK);
3551 else
3552 pHlp->pfnPrintf(pHlp, /*P G WT CD AT NX 4M a p ? */
3553 "%08x 0 | P %c %s %s %s %s .. %c%c%c %016llx\n",
3554 i << X86_PDPT_SHIFT,
3555 Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3556 Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3557 Pdpe.n.u1WriteThru ? "WT" : "--",
3558 Pdpe.n.u1CacheDisable? "CD" : "--",
3559 Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3560 Pdpe.u & RT_BIT(9) ? '1' : '0',
3561 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3562 Pdpe.u & RT_BIT(11) ? '1' : '0',
3563 Pdpe.u & X86_PDPE_PG_MASK);
3564 if (cMaxDepth >= 1)
3565 {
3566 int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3567 cr4, fLongMode, cMaxDepth - 1, pHlp);
3568 if (rc2 < rc && RT_SUCCESS(rc))
3569 rc = rc2;
3570 }
3571 }
3572 }
3573 return rc;
3574}
3575
3576
3577/**
3578 * Dumps a 32-bit shadow page table.
3579 *
3580 * @returns VBox status code (VINF_SUCCESS).
3581 * @param pVM The VM handle.
3582 * @param HCPhys The physical address of the table.
3583 * @param cr4 The CR4, PSE is currently used.
3584 * @param cMaxDepth The maxium depth.
3585 * @param pHlp Pointer to the output functions.
3586 */
3587static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3588{
3589 PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3590 if (!pPML4)
3591 {
3592 pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3593 return VERR_INVALID_PARAMETER;
3594 }
3595
3596 int rc = VINF_SUCCESS;
3597 for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3598 {
3599 X86PML4E Pml4e = pPML4->a[i];
3600 if (Pml4e.n.u1Present)
3601 {
3602 uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) | (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3603 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3604 "%016llx 0 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3605 u64Address,
3606 Pml4e.n.u1Write ? 'W' : 'R',
3607 Pml4e.n.u1User ? 'U' : 'S',
3608 Pml4e.n.u1Accessed ? 'A' : '-',
3609 Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3610 Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3611 Pml4e.n.u1WriteThru ? "WT" : "--",
3612 Pml4e.n.u1CacheDisable? "CD" : "--",
3613 Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3614 Pml4e.n.u1NoExecute ? "NX" : "--",
3615 Pml4e.u & RT_BIT(9) ? '1' : '0',
3616 Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3617 Pml4e.u & RT_BIT(11) ? '1' : '0',
3618 Pml4e.u & X86_PML4E_PG_MASK);
3619
3620 if (cMaxDepth >= 1)
3621 {
3622 int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3623 if (rc2 < rc && RT_SUCCESS(rc))
3624 rc = rc2;
3625 }
3626 }
3627 }
3628 return rc;
3629}
3630
3631
3632/**
3633 * Dumps a 32-bit shadow page table.
3634 *
3635 * @returns VBox status code (VINF_SUCCESS).
3636 * @param pVM The VM handle.
3637 * @param pPT Pointer to the page table.
3638 * @param u32Address The virtual address this table starts at.
3639 * @param pHlp Pointer to the output functions.
3640 */
3641int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3642{
3643 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3644 {
3645 X86PTE Pte = pPT->a[i];
3646 if (Pte.n.u1Present)
3647 {
3648 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3649 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3650 u32Address + (i << X86_PT_SHIFT),
3651 Pte.n.u1Write ? 'W' : 'R',
3652 Pte.n.u1User ? 'U' : 'S',
3653 Pte.n.u1Accessed ? 'A' : '-',
3654 Pte.n.u1Dirty ? 'D' : '-',
3655 Pte.n.u1Global ? 'G' : '-',
3656 Pte.n.u1WriteThru ? "WT" : "--",
3657 Pte.n.u1CacheDisable? "CD" : "--",
3658 Pte.n.u1PAT ? "AT" : "--",
3659 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3660 Pte.u & RT_BIT(10) ? '1' : '0',
3661 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3662 Pte.u & X86_PDE_PG_MASK);
3663 }
3664 }
3665 return VINF_SUCCESS;
3666}
3667
3668
3669/**
3670 * Dumps a 32-bit shadow page directory and page tables.
3671 *
3672 * @returns VBox status code (VINF_SUCCESS).
3673 * @param pVM The VM handle.
3674 * @param cr3 The root of the hierarchy.
3675 * @param cr4 The CR4, PSE is currently used.
3676 * @param cMaxDepth How deep into the hierarchy the dumper should go.
3677 * @param pHlp Pointer to the output functions.
3678 */
3679int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3680{
3681 PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3682 if (!pPD)
3683 {
3684 pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3685 return VERR_INVALID_PARAMETER;
3686 }
3687
3688 int rc = VINF_SUCCESS;
3689 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3690 {
3691 X86PDE Pde = pPD->a[i];
3692 if (Pde.n.u1Present)
3693 {
3694 const uint32_t u32Address = i << X86_PD_SHIFT;
3695 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3696 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3697 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3698 u32Address,
3699 Pde.b.u1Write ? 'W' : 'R',
3700 Pde.b.u1User ? 'U' : 'S',
3701 Pde.b.u1Accessed ? 'A' : '-',
3702 Pde.b.u1Dirty ? 'D' : '-',
3703 Pde.b.u1Global ? 'G' : '-',
3704 Pde.b.u1WriteThru ? "WT" : "--",
3705 Pde.b.u1CacheDisable? "CD" : "--",
3706 Pde.b.u1PAT ? "AT" : "--",
3707 Pde.u & RT_BIT_64(9) ? '1' : '0',
3708 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3709 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3710 Pde.u & X86_PDE4M_PG_MASK);
3711 else
3712 {
3713 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3714 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3715 u32Address,
3716 Pde.n.u1Write ? 'W' : 'R',
3717 Pde.n.u1User ? 'U' : 'S',
3718 Pde.n.u1Accessed ? 'A' : '-',
3719 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3720 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3721 Pde.n.u1WriteThru ? "WT" : "--",
3722 Pde.n.u1CacheDisable? "CD" : "--",
3723 Pde.u & RT_BIT_64(9) ? '1' : '0',
3724 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3725 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3726 Pde.u & X86_PDE_PG_MASK);
3727 if (cMaxDepth >= 1)
3728 {
3729 /** @todo what about using the page pool for mapping PTs? */
3730 RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3731 PX86PT pPT = NULL;
3732 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3733 pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3734 else
3735 {
3736 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3737 if (u32Address - pMap->GCPtr < pMap->cb)
3738 {
3739 int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3740 if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3741 pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3742 u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3743 pPT = pMap->aPTs[iPDE].pPTR3;
3744 }
3745 }
3746 int rc2 = VERR_INVALID_PARAMETER;
3747 if (pPT)
3748 rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3749 else
3750 pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3751 if (rc2 < rc && RT_SUCCESS(rc))
3752 rc = rc2;
3753 }
3754 }
3755 }
3756 }
3757
3758 return rc;
3759}
3760
3761
3762/**
3763 * Dumps a 32-bit shadow page table.
3764 *
3765 * @returns VBox status code (VINF_SUCCESS).
3766 * @param pVM The VM handle.
3767 * @param pPT Pointer to the page table.
3768 * @param u32Address The virtual address this table starts at.
3769 * @param PhysSearch Address to search for.
3770 */
3771int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3772{
3773 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3774 {
3775 X86PTE Pte = pPT->a[i];
3776 if (Pte.n.u1Present)
3777 {
3778 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3779 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3780 u32Address + (i << X86_PT_SHIFT),
3781 Pte.n.u1Write ? 'W' : 'R',
3782 Pte.n.u1User ? 'U' : 'S',
3783 Pte.n.u1Accessed ? 'A' : '-',
3784 Pte.n.u1Dirty ? 'D' : '-',
3785 Pte.n.u1Global ? 'G' : '-',
3786 Pte.n.u1WriteThru ? "WT" : "--",
3787 Pte.n.u1CacheDisable? "CD" : "--",
3788 Pte.n.u1PAT ? "AT" : "--",
3789 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3790 Pte.u & RT_BIT(10) ? '1' : '0',
3791 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3792 Pte.u & X86_PDE_PG_MASK));
3793
3794 if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3795 {
3796 uint64_t fPageShw = 0;
3797 RTHCPHYS pPhysHC = 0;
3798
3799 /** @todo SMP support!! */
3800 PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3801 Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3802 }
3803 }
3804 }
3805 return VINF_SUCCESS;
3806}
3807
3808
3809/**
3810 * Dumps a 32-bit guest page directory and page tables.
3811 *
3812 * @returns VBox status code (VINF_SUCCESS).
3813 * @param pVM The VM handle.
3814 * @param cr3 The root of the hierarchy.
3815 * @param cr4 The CR4, PSE is currently used.
3816 * @param PhysSearch Address to search for.
3817 */
3818VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3819{
3820 bool fLongMode = false;
3821 const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3822 PX86PD pPD = 0;
3823
3824 int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3825 if (RT_FAILURE(rc) || !pPD)
3826 {
3827 Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3828 return VERR_INVALID_PARAMETER;
3829 }
3830
3831 Log(("cr3=%08x cr4=%08x%s\n"
3832 "%-*s P - Present\n"
3833 "%-*s | R/W - Read (0) / Write (1)\n"
3834 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3835 "%-*s | | | A - Accessed\n"
3836 "%-*s | | | | D - Dirty\n"
3837 "%-*s | | | | | G - Global\n"
3838 "%-*s | | | | | | WT - Write thru\n"
3839 "%-*s | | | | | | | CD - Cache disable\n"
3840 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3841 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3842 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3843 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
3844 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
3845 "%-*s Level | | | | | | | | | | | | Page\n"
3846 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3847 - W U - - - -- -- -- -- -- 010 */
3848 , cr3, cr4, fLongMode ? " Long Mode" : "",
3849 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3850 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3851
3852 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3853 {
3854 X86PDE Pde = pPD->a[i];
3855 if (Pde.n.u1Present)
3856 {
3857 const uint32_t u32Address = i << X86_PD_SHIFT;
3858
3859 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3860 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3861 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3862 u32Address,
3863 Pde.b.u1Write ? 'W' : 'R',
3864 Pde.b.u1User ? 'U' : 'S',
3865 Pde.b.u1Accessed ? 'A' : '-',
3866 Pde.b.u1Dirty ? 'D' : '-',
3867 Pde.b.u1Global ? 'G' : '-',
3868 Pde.b.u1WriteThru ? "WT" : "--",
3869 Pde.b.u1CacheDisable? "CD" : "--",
3870 Pde.b.u1PAT ? "AT" : "--",
3871 Pde.u & RT_BIT(9) ? '1' : '0',
3872 Pde.u & RT_BIT(10) ? '1' : '0',
3873 Pde.u & RT_BIT(11) ? '1' : '0',
3874 pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3875 /** @todo PhysSearch */
3876 else
3877 {
3878 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3879 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3880 u32Address,
3881 Pde.n.u1Write ? 'W' : 'R',
3882 Pde.n.u1User ? 'U' : 'S',
3883 Pde.n.u1Accessed ? 'A' : '-',
3884 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3885 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3886 Pde.n.u1WriteThru ? "WT" : "--",
3887 Pde.n.u1CacheDisable? "CD" : "--",
3888 Pde.u & RT_BIT(9) ? '1' : '0',
3889 Pde.u & RT_BIT(10) ? '1' : '0',
3890 Pde.u & RT_BIT(11) ? '1' : '0',
3891 Pde.u & X86_PDE_PG_MASK));
3892 ////if (cMaxDepth >= 1)
3893 {
3894 /** @todo what about using the page pool for mapping PTs? */
3895 RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3896 PX86PT pPT = NULL;
3897
3898 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3899
3900 int rc2 = VERR_INVALID_PARAMETER;
3901 if (pPT)
3902 rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3903 else
3904 Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3905 if (rc2 < rc && RT_SUCCESS(rc))
3906 rc = rc2;
3907 }
3908 }
3909 }
3910 }
3911
3912 return rc;
3913}
3914
3915
3916/**
3917 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3918 *
3919 * @returns VBox status code (VINF_SUCCESS).
3920 * @param pVM The VM handle.
3921 * @param cr3 The root of the hierarchy.
3922 * @param cr4 The cr4, only PAE and PSE is currently used.
3923 * @param fLongMode Set if long mode, false if not long mode.
3924 * @param cMaxDepth Number of levels to dump.
3925 * @param pHlp Pointer to the output functions.
3926 */
3927VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3928{
3929 if (!pHlp)
3930 pHlp = DBGFR3InfoLogHlp();
3931 if (!cMaxDepth)
3932 return VINF_SUCCESS;
3933 const unsigned cch = fLongMode ? 16 : 8;
3934 pHlp->pfnPrintf(pHlp,
3935 "cr3=%08x cr4=%08x%s\n"
3936 "%-*s P - Present\n"
3937 "%-*s | R/W - Read (0) / Write (1)\n"
3938 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3939 "%-*s | | | A - Accessed\n"
3940 "%-*s | | | | D - Dirty\n"
3941 "%-*s | | | | | G - Global\n"
3942 "%-*s | | | | | | WT - Write thru\n"
3943 "%-*s | | | | | | | CD - Cache disable\n"
3944 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3945 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3946 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3947 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
3948 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
3949 "%-*s Level | | | | | | | | | | | | Page\n"
3950 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3951 - W U - - - -- -- -- -- -- 010 */
3952 , cr3, cr4, fLongMode ? " Long Mode" : "",
3953 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3954 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3955 if (cr4 & X86_CR4_PAE)
3956 {
3957 if (fLongMode)
3958 return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3959 return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3960 }
3961 return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3962}
3963
3964#ifdef VBOX_WITH_DEBUGGER
3965
3966/**
3967 * The '.pgmram' command.
3968 *
3969 * @returns VBox status.
3970 * @param pCmd Pointer to the command descriptor (as registered).
3971 * @param pCmdHlp Pointer to command helper functions.
3972 * @param pVM Pointer to the current VM (if any).
3973 * @param paArgs Pointer to (readonly) array of arguments.
3974 * @param cArgs Number of arguments in the array.
3975 */
3976static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3977{
3978 /*
3979 * Validate input.
3980 */
3981 if (!pVM)
3982 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3983 if (!pVM->pgm.s.pRamRangesRC)
3984 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3985
3986 /*
3987 * Dump the ranges.
3988 */
3989 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3990 PPGMRAMRANGE pRam;
3991 for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
3992 {
3993 rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3994 "%RGp - %RGp %p\n",
3995 pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
3996 if (RT_FAILURE(rc))
3997 return rc;
3998 }
3999
4000 return VINF_SUCCESS;
4001}
4002
4003
4004/**
4005 * The '.pgmmap' command.
4006 *
4007 * @returns VBox status.
4008 * @param pCmd Pointer to the command descriptor (as registered).
4009 * @param pCmdHlp Pointer to command helper functions.
4010 * @param pVM Pointer to the current VM (if any).
4011 * @param paArgs Pointer to (readonly) array of arguments.
4012 * @param cArgs Number of arguments in the array.
4013 */
4014static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4015{
4016 /*
4017 * Validate input.
4018 */
4019 if (!pVM)
4020 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4021 if (!pVM->pgm.s.pMappingsR3)
4022 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4023
4024 /*
4025 * Print message about the fixedness of the mappings.
4026 */
4027 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4028 if (RT_FAILURE(rc))
4029 return rc;
4030
4031 /*
4032 * Dump the ranges.
4033 */
4034 PPGMMAPPING pCur;
4035 for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4036 {
4037 rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4038 "%08x - %08x %s\n",
4039 pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4040 if (RT_FAILURE(rc))
4041 return rc;
4042 }
4043
4044 return VINF_SUCCESS;
4045}
4046
4047
4048/**
4049 * The '.pgmerror' and '.pgmerroroff' commands.
4050 *
4051 * @returns VBox status.
4052 * @param pCmd Pointer to the command descriptor (as registered).
4053 * @param pCmdHlp Pointer to command helper functions.
4054 * @param pVM Pointer to the current VM (if any).
4055 * @param paArgs Pointer to (readonly) array of arguments.
4056 * @param cArgs Number of arguments in the array.
4057 */
4058static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4059{
4060 /*
4061 * Validate input.
4062 */
4063 if (!pVM)
4064 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4065 AssertReturn(cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4066 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4067
4068 if (!cArgs)
4069 {
4070 /*
4071 * Print the list of error injection locations with status.
4072 */
4073 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4074 pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4075 }
4076 else
4077 {
4078
4079 /*
4080 * String switch on where to inject the error.
4081 */
4082 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4083 const char *pszWhere = paArgs[0].u.pszString;
4084 if (!strcmp(pszWhere, "handy"))
4085 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4086 else
4087 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4088 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4089 }
4090 return VINF_SUCCESS;
4091}
4092
4093
4094/**
4095 * The '.pgmsync' command.
4096 *
4097 * @returns VBox status.
4098 * @param pCmd Pointer to the command descriptor (as registered).
4099 * @param pCmdHlp Pointer to command helper functions.
4100 * @param pVM Pointer to the current VM (if any).
4101 * @param paArgs Pointer to (readonly) array of arguments.
4102 * @param cArgs Number of arguments in the array.
4103 */
4104static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4105{
4106 /** @todo SMP support */
4107 PVMCPU pVCpu = &pVM->aCpus[0];
4108
4109 /*
4110 * Validate input.
4111 */
4112 if (!pVM)
4113 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4114
4115 /*
4116 * Force page directory sync.
4117 */
4118 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4119
4120 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4121 if (RT_FAILURE(rc))
4122 return rc;
4123
4124 return VINF_SUCCESS;
4125}
4126
4127
4128#ifdef VBOX_STRICT
4129/**
4130 * The '.pgmassertcr3' command.
4131 *
4132 * @returns VBox status.
4133 * @param pCmd Pointer to the command descriptor (as registered).
4134 * @param pCmdHlp Pointer to command helper functions.
4135 * @param pVM Pointer to the current VM (if any).
4136 * @param paArgs Pointer to (readonly) array of arguments.
4137 * @param cArgs Number of arguments in the array.
4138 */
4139static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4140{
4141 /** @todo SMP support!! */
4142 PVMCPU pVCpu = &pVM->aCpus[0];
4143
4144 /*
4145 * Validate input.
4146 */
4147 if (!pVM)
4148 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4149
4150 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4151 if (RT_FAILURE(rc))
4152 return rc;
4153
4154 PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4155
4156 return VINF_SUCCESS;
4157}
4158#endif /* VBOX_STRICT */
4159
4160
4161/**
4162 * The '.pgmsyncalways' command.
4163 *
4164 * @returns VBox status.
4165 * @param pCmd Pointer to the command descriptor (as registered).
4166 * @param pCmdHlp Pointer to command helper functions.
4167 * @param pVM Pointer to the current VM (if any).
4168 * @param paArgs Pointer to (readonly) array of arguments.
4169 * @param cArgs Number of arguments in the array.
4170 */
4171static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4172{
4173 /** @todo SMP support!! */
4174 PVMCPU pVCpu = &pVM->aCpus[0];
4175
4176 /*
4177 * Validate input.
4178 */
4179 if (!pVM)
4180 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4181
4182 /*
4183 * Force page directory sync.
4184 */
4185 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4186 {
4187 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4188 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4189 }
4190 else
4191 {
4192 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4193 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4194 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4195 }
4196}
4197
4198
4199/**
4200 * The '.pgmsyncalways' command.
4201 *
4202 * @returns VBox status.
4203 * @param pCmd Pointer to the command descriptor (as registered).
4204 * @param pCmdHlp Pointer to command helper functions.
4205 * @param pVM Pointer to the current VM (if any).
4206 * @param paArgs Pointer to (readonly) array of arguments.
4207 * @param cArgs Number of arguments in the array.
4208 */
4209static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4210{
4211 /*
4212 * Validate input.
4213 */
4214 if (!pVM)
4215 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4216 if ( cArgs < 1
4217 || cArgs > 2
4218 || paArgs[0].enmType != DBGCVAR_TYPE_STRING
4219 || ( cArgs > 1
4220 && paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4221 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4222 if ( cArgs >= 2
4223 && strcmp(paArgs[1].u.pszString, "nozero"))
4224 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4225 bool fIncZeroPgs = cArgs < 2;
4226
4227 /*
4228 * Open the output file and get the ram parameters.
4229 */
4230 RTFILE hFile;
4231 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
4232 if (RT_FAILURE(rc))
4233 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4234
4235 uint32_t cbRamHole = 0;
4236 CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4237 uint64_t cbRam = 0;
4238 CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4239 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4240
4241 /*
4242 * Dump the physical memory, page by page.
4243 */
4244 RTGCPHYS GCPhys = 0;
4245 char abZeroPg[PAGE_SIZE];
4246 RT_ZERO(abZeroPg);
4247
4248 pgmLock(pVM);
4249 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4250 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4251 pRam = pRam->pNextR3)
4252 {
4253 /* fill the gap */
4254 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4255 {
4256 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4257 {
4258 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4259 GCPhys += PAGE_SIZE;
4260 }
4261 }
4262
4263 PCPGMPAGE pPage = &pRam->aPages[0];
4264 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4265 {
4266 if (PGM_PAGE_IS_ZERO(pPage))
4267 {
4268 if (fIncZeroPgs)
4269 {
4270 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4271 if (RT_FAILURE(rc))
4272 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4273 }
4274 }
4275 else
4276 {
4277 switch (PGM_PAGE_GET_TYPE(pPage))
4278 {
4279 case PGMPAGETYPE_RAM:
4280 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4281 case PGMPAGETYPE_ROM:
4282 case PGMPAGETYPE_MMIO2:
4283 {
4284 void const *pvPage;
4285 PGMPAGEMAPLOCK Lock;
4286 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4287 if (RT_SUCCESS(rc))
4288 {
4289 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4290 PGMPhysReleasePageMappingLock(pVM, &Lock);
4291 if (RT_FAILURE(rc))
4292 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4293 }
4294 else
4295 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4296 break;
4297 }
4298
4299 default:
4300 AssertFailed();
4301 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4302 case PGMPAGETYPE_MMIO:
4303 if (fIncZeroPgs)
4304 {
4305 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4306 if (RT_FAILURE(rc))
4307 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4308 }
4309 break;
4310 }
4311 }
4312
4313
4314 /* advance */
4315 GCPhys += PAGE_SIZE;
4316 pPage++;
4317 }
4318 }
4319 pgmUnlock(pVM);
4320
4321 RTFileClose(hFile);
4322 if (RT_SUCCESS(rc))
4323 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4324 return VINF_SUCCESS;
4325}
4326
4327#endif /* VBOX_WITH_DEBUGGER */
4328
4329/**
4330 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4331 */
4332typedef struct PGMCHECKINTARGS
4333{
4334 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
4335 PPGMPHYSHANDLER pPrevPhys;
4336 PPGMVIRTHANDLER pPrevVirt;
4337 PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4338 PVM pVM;
4339} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4340
4341/**
4342 * Validate a node in the physical handler tree.
4343 *
4344 * @returns 0 on if ok, other wise 1.
4345 * @param pNode The handler node.
4346 * @param pvUser pVM.
4347 */
4348static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4349{
4350 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4351 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4352 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4353 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4354 AssertReleaseMsg( !pArgs->pPrevPhys
4355 || (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4356 ("pPrevPhys=%p %RGp-%RGp %s\n"
4357 " pCur=%p %RGp-%RGp %s\n",
4358 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4359 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4360 pArgs->pPrevPhys = pCur;
4361 return 0;
4362}
4363
4364
4365/**
4366 * Validate a node in the virtual handler tree.
4367 *
4368 * @returns 0 on if ok, other wise 1.
4369 * @param pNode The handler node.
4370 * @param pvUser pVM.
4371 */
4372static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4373{
4374 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4375 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4376 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4377 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4378 AssertReleaseMsg( !pArgs->pPrevVirt
4379 || (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4380 ("pPrevVirt=%p %RGv-%RGv %s\n"
4381 " pCur=%p %RGv-%RGv %s\n",
4382 pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4383 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4384 for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4385 {
4386 AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4387 ("pCur=%p %RGv-%RGv %s\n"
4388 "iPage=%d offVirtHandle=%#x expected %#x\n",
4389 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4390 iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4391 }
4392 pArgs->pPrevVirt = pCur;
4393 return 0;
4394}
4395
4396
4397/**
4398 * Validate a node in the virtual handler tree.
4399 *
4400 * @returns 0 on if ok, other wise 1.
4401 * @param pNode The handler node.
4402 * @param pvUser pVM.
4403 */
4404static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4405{
4406 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4407 PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4408 AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4409 AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4410 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4411 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4412 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4413 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4414 " pCur=%p %RGp-%RGp\n",
4415 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4416 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4417 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4418 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4419 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4420 " pCur=%p %RGp-%RGp\n",
4421 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4422 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4423 AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
4424 ("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4425 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4426 if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4427 {
4428 PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4429 for (;;)
4430 {
4431 pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4432 AssertReleaseMsg(pCur2 != pCur,
4433 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4434 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4435 AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4436 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4437 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4438 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4439 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4440 AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4441 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4442 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4443 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4444 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4445 AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4446 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4447 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4448 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4449 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4450 if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4451 break;
4452 }
4453 }
4454
4455 pArgs->pPrevPhys2Virt = pCur;
4456 return 0;
4457}
4458
4459
4460/**
4461 * Perform an integrity check on the PGM component.
4462 *
4463 * @returns VINF_SUCCESS if everything is fine.
4464 * @returns VBox error status after asserting on integrity breach.
4465 * @param pVM The VM handle.
4466 */
4467VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4468{
4469 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4470
4471 /*
4472 * Check the trees.
4473 */
4474 int cErrors = 0;
4475 const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4476 const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4477 PGMCHECKINTARGS Args = s_LeftToRight;
4478 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4479 Args = s_RightToLeft;
4480 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4481 Args = s_LeftToRight;
4482 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4483 Args = s_RightToLeft;
4484 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4485 Args = s_LeftToRight;
4486 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4487 Args = s_RightToLeft;
4488 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4489 Args = s_LeftToRight;
4490 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4491 Args = s_RightToLeft;
4492 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4493
4494 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4495}
4496
4497
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette