PGM.cpp@ 2584

Last change on this file since 2584 was 2559, checked in by vboxsync, 18 years ago
Allow ring-3 only access handlers (phys).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 157.4 KB

Line
1	/* $Id: PGM.cpp 2559 2007-05-09 14:00:38Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pg_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pg_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPTR and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pg_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pg_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pg_misc Misc
97	*
98	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*/
111
112
113
114	/** Saved state data unit version. */
115	#define PGM_SAVED_STATE_VERSION 5
116
117	/*******************************************************************************
118	* Header Files *
119	*******************************************************************************/
120	#define LOG_GROUP LOG_GROUP_PGM
121	#include <VBox/dbgf.h>
122	#include <VBox/pgm.h>
123	#include <VBox/cpum.h>
124	#include <VBox/iom.h>
125	#include <VBox/sup.h>
126	#include <VBox/mm.h>
127	#include <VBox/pdm.h>
128	#include <VBox/em.h>
129	#include <VBox/stam.h>
130	#include <VBox/rem.h>
131	#include <VBox/dbgf.h>
132	#include <VBox/rem.h>
133	#include <VBox/selm.h>
134	#include <VBox/ssm.h>
135	#include "PGMInternal.h"
136	#include <VBox/vm.h>
137	#include <VBox/dbg.h>
138	#include <VBox/hwaccm.h>
139
140	#include <VBox/log.h>
141	#include <iprt/assert.h>
142	#include <iprt/alloc.h>
143	#include <iprt/asm.h>
144	#include <iprt/thread.h>
145	#include <iprt/string.h>
146	#include <VBox/param.h>
147	#include <VBox/err.h>
148
149
150
151	/*******************************************************************************
152	* Internal Functions *
153	*******************************************************************************/
154	static int pgmR3InitPaging(PVM pVM);
155	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
157	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
158	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
159	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
160	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
161	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
162	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
163	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
164	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
165
166	#ifdef VBOX_WITH_STATISTICS
167	static void pgmR3InitStats(PVM pVM);
168	#endif
169
170	#ifdef VBOX_WITH_DEBUGGER
171	/** @todo all but the two last commands must be converted to 'info'. */
172	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
173	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
174	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
175	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
176	#endif
177
178
179	/*******************************************************************************
180	* Global Variables *
181	*******************************************************************************/
182	#ifdef VBOX_WITH_DEBUGGER
183	/** Command descriptors. */
184	static const DBGCCMD g_aCmds[] =
185	{
186	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
187	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
188	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
189	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
190	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
191	};
192	#endif
193
194
195
196
197	#if 1/// @todo ndef __AMD64__
198	/*
199	* Shadow - 32-bit mode
200	*/
201	#define PGM_SHW_TYPE PGM_TYPE_32BIT
202	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
203	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
204	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
205	#include "PGMShw.h"
206
207	/* Guest - real mode */
208	#define PGM_GST_TYPE PGM_TYPE_REAL
209	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
210	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
211	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
212	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
213	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
214	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
215	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
216	#include "PGMGst.h"
217	#include "PGMBth.h"
218	#undef BTH_PGMPOOLKIND_PT_FOR_PT
219	#undef PGM_BTH_NAME
220	#undef PGM_BTH_NAME_GC_STR
221	#undef PGM_BTH_NAME_R0_STR
222	#undef PGM_GST_TYPE
223	#undef PGM_GST_NAME
224	#undef PGM_GST_NAME_GC_STR
225	#undef PGM_GST_NAME_R0_STR
226
227	/* Guest - protected mode */
228	#define PGM_GST_TYPE PGM_TYPE_PROT
229	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
230	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
231	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
232	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
233	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
234	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
235	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
236	#include "PGMGst.h"
237	#include "PGMBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef PGM_BTH_NAME
240	#undef PGM_BTH_NAME_GC_STR
241	#undef PGM_BTH_NAME_R0_STR
242	#undef PGM_GST_TYPE
243	#undef PGM_GST_NAME
244	#undef PGM_GST_NAME_GC_STR
245	#undef PGM_GST_NAME_R0_STR
246
247	/* Guest - 32-bit mode */
248	#define PGM_GST_TYPE PGM_TYPE_32BIT
249	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
251	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
252	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
253	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
254	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
255	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
256	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
257	#include "PGMGst.h"
258	#include "PGMBth.h"
259	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
260	#undef BTH_PGMPOOLKIND_PT_FOR_PT
261	#undef PGM_BTH_NAME
262	#undef PGM_BTH_NAME_GC_STR
263	#undef PGM_BTH_NAME_R0_STR
264	#undef PGM_GST_TYPE
265	#undef PGM_GST_NAME
266	#undef PGM_GST_NAME_GC_STR
267	#undef PGM_GST_NAME_R0_STR
268
269	#undef PGM_SHW_TYPE
270	#undef PGM_SHW_NAME
271	#undef PGM_SHW_NAME_GC_STR
272	#undef PGM_SHW_NAME_R0_STR
273	#endif /* !__AMD64__ */
274
275
276	/*
277	* Shadow - PAE mode
278	*/
279	#define PGM_SHW_TYPE PGM_TYPE_PAE
280	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
281	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
282	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
283	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
284	#include "PGMShw.h"
285
286	/* Guest - real mode */
287	#define PGM_GST_TYPE PGM_TYPE_REAL
288	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
289	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
290	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
291	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
292	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
293	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
294	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
295	#include "PGMBth.h"
296	#undef BTH_PGMPOOLKIND_PT_FOR_PT
297	#undef PGM_BTH_NAME
298	#undef PGM_BTH_NAME_GC_STR
299	#undef PGM_BTH_NAME_R0_STR
300	#undef PGM_GST_TYPE
301	#undef PGM_GST_NAME
302	#undef PGM_GST_NAME_GC_STR
303	#undef PGM_GST_NAME_R0_STR
304
305	/* Guest - protected mode */
306	#define PGM_GST_TYPE PGM_TYPE_PROT
307	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
308	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
309	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
310	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
311	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
312	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
313	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
314	#include "PGMBth.h"
315	#undef BTH_PGMPOOLKIND_PT_FOR_PT
316	#undef PGM_BTH_NAME
317	#undef PGM_BTH_NAME_GC_STR
318	#undef PGM_BTH_NAME_R0_STR
319	#undef PGM_GST_TYPE
320	#undef PGM_GST_NAME
321	#undef PGM_GST_NAME_GC_STR
322	#undef PGM_GST_NAME_R0_STR
323
324	/* Guest - 32-bit mode */
325	#define PGM_GST_TYPE PGM_TYPE_32BIT
326	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
327	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
328	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
329	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
330	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
331	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
332	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
333	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
334	#include "PGMBth.h"
335	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
336	#undef BTH_PGMPOOLKIND_PT_FOR_PT
337	#undef PGM_BTH_NAME
338	#undef PGM_BTH_NAME_GC_STR
339	#undef PGM_BTH_NAME_R0_STR
340	#undef PGM_GST_TYPE
341	#undef PGM_GST_NAME
342	#undef PGM_GST_NAME_GC_STR
343	#undef PGM_GST_NAME_R0_STR
344
345	/* Guest - PAE mode */
346	#define PGM_GST_TYPE PGM_TYPE_PAE
347	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
348	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
349	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
351	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
352	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
353	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
354	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
355	#include "PGMGst.h"
356	#include "PGMBth.h"
357	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
358	#undef BTH_PGMPOOLKIND_PT_FOR_PT
359	#undef PGM_BTH_NAME
360	#undef PGM_BTH_NAME_GC_STR
361	#undef PGM_BTH_NAME_R0_STR
362	#undef PGM_GST_TYPE
363	#undef PGM_GST_NAME
364	#undef PGM_GST_NAME_GC_STR
365	#undef PGM_GST_NAME_R0_STR
366
367	#undef PGM_SHW_TYPE
368	#undef PGM_SHW_NAME
369	#undef PGM_SHW_NAME_GC_STR
370	#undef PGM_SHW_NAME_R0_STR
371
372
373	/*
374	* Shadow - AMD64 mode
375	*/
376	#define PGM_SHW_TYPE PGM_TYPE_AMD64
377	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
378	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
379	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
380	#include "PGMShw.h"
381
382	/* Guest - real mode */
383	#define PGM_GST_TYPE PGM_TYPE_REAL
384	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
385	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
386	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
387	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
388	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
389	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
390	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
391	#include "PGMBth.h"
392	#undef BTH_PGMPOOLKIND_PT_FOR_PT
393	#undef PGM_BTH_NAME
394	#undef PGM_BTH_NAME_GC_STR
395	#undef PGM_BTH_NAME_R0_STR
396	#undef PGM_GST_TYPE
397	#undef PGM_GST_NAME
398	#undef PGM_GST_NAME_GC_STR
399	#undef PGM_GST_NAME_R0_STR
400
401	/* Guest - protected mode */
402	#define PGM_GST_TYPE PGM_TYPE_PROT
403	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
404	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
405	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
406	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
407	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
408	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
409	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
410	#include "PGMBth.h"
411	#undef BTH_PGMPOOLKIND_PT_FOR_PT
412	#undef PGM_BTH_NAME
413	#undef PGM_BTH_NAME_GC_STR
414	#undef PGM_BTH_NAME_R0_STR
415	#undef PGM_GST_TYPE
416	#undef PGM_GST_NAME
417	#undef PGM_GST_NAME_GC_STR
418	#undef PGM_GST_NAME_R0_STR
419
420	/* Guest - AMD64 mode */
421	#define PGM_GST_TYPE PGM_TYPE_AMD64
422	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
423	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
424	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
425	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
426	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
427	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
428	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
429	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
430	#include "PGMGst.h"
431	#include "PGMBth.h"
432	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
433	#undef BTH_PGMPOOLKIND_PT_FOR_PT
434	#undef PGM_BTH_NAME
435	#undef PGM_BTH_NAME_GC_STR
436	#undef PGM_BTH_NAME_R0_STR
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439	#undef PGM_GST_NAME_GC_STR
440	#undef PGM_GST_NAME_R0_STR
441
442	#undef PGM_SHW_TYPE
443	#undef PGM_SHW_NAME
444	#undef PGM_SHW_NAME_GC_STR
445	#undef PGM_SHW_NAME_R0_STR
446
447
448
449
450	/**
451	* Initiates the paging of VM.
452	*
453	* @returns VBox status code.
454	* @param pVM Pointer to VM structure.
455	*/
456	PGMR3DECL(int) PGMR3Init(PVM pVM)
457	{
458	LogFlow(("PGMR3Init:\n"));
459
460	/*
461	* Assert alignment and sizes.
462	*/
463	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
464
465	/*
466	* Init the structure.
467	*/
468	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
469	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
470	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
471	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
472	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
473	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
474	pVM->pgm.s.fA20Enabled = true;
475	pVM->pgm.s.pGstPaePDPTRHC = NULL;
476	pVM->pgm.s.pGstPaePDPTRGC = 0;
477	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
478	{
479	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
480	pVM->pgm.s.apGstPaePDsGC[i] = 0;
481	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
482	}
483
484	/*
485	* Get the configured RAM size - to estimate saved state size.
486	*/
487	uint64_t cbRam;
488	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
489	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
490	cbRam = pVM->pgm.s.cbRamSize = 0;
491	else if (VBOX_SUCCESS(rc))
492	{
493	if (cbRam < PAGE_SIZE)
494	cbRam = 0;
495	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
496	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
497	}
498	else
499	{
500	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
501	return rc;
502	}
503
504	/*
505	* Register saved state data unit.
506	*/
507	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
508	NULL, pgmR3Save, NULL,
509	NULL, pgmR3Load, NULL);
510	if (VBOX_FAILURE(rc))
511	return rc;
512
513	/* Initialise PGM critical section. */
514	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
515	AssertRCReturn(rc, rc);
516
517	/*
518	* Trees
519	*/
520	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
521	if (VBOX_SUCCESS(rc))
522	{
523	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
524
525	/*
526	* Init the paging.
527	*/
528	rc = pgmR3InitPaging(pVM);
529	}
530	if (VBOX_SUCCESS(rc))
531	{
532	/*
533	* Init the page pool.
534	*/
535	rc = pgmR3PoolInit(pVM);
536	}
537	if (VBOX_SUCCESS(rc))
538	{
539	/*
540	* Info & statistics
541	*/
542	DBGFR3InfoRegisterInternal(pVM, "mode",
543	"Shows the current paging mode. "
544	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
545	pgmR3InfoMode);
546	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
547	"Dumps all the entries in the top level paging table. No arguments.",
548	pgmR3InfoCr3);
549	DBGFR3InfoRegisterInternal(pVM, "phys",
550	"Dumps all the physical address ranges. No arguments.",
551	pgmR3PhysInfo);
552	DBGFR3InfoRegisterInternal(pVM, "handlers",
553	"Dumps physical and virtual handlers. "
554	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
555	pgmR3InfoHandlers);
556
557	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
558	#ifdef VBOX_WITH_STATISTICS
559	pgmR3InitStats(pVM);
560	#endif
561	#ifdef VBOX_WITH_DEBUGGER
562	/*
563	* Debugger commands.
564	*/
565	static bool fRegisteredCmds = false;
566	if (!fRegisteredCmds)
567	{
568	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
569	if (VBOX_SUCCESS(rc))
570	fRegisteredCmds = true;
571	}
572	#endif
573	return VINF_SUCCESS;
574	}
575	/* No cleanup necessary, MM frees all memory. */
576
577	return rc;
578	}
579
580
581	/**
582	* Init paging.
583	*
584	* Since we need to check what mode the host is operating in before we can choose
585	* the right paging functions for the host we have to delay this until R0 has
586	* been initialized.
587	*
588	* @returns VBox status code.
589	* @param pVM VM handle.
590	*/
591	static int pgmR3InitPaging(PVM pVM)
592	{
593	/*
594	* Force a recalculation of modes and switcher so everyone gets notified.
595	*/
596	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
597	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
598	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
599
600	/*
601	* Allocate static mapping space for whatever the cr3 register
602	* points to and in the case of PAE mode to the 4 PDs.
603	*/
604	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
605	if (VBOX_FAILURE(rc))
606	{
607	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
608	return rc;
609	}
610	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
611
612	/*
613	* Allocate pages for the three possible intermediate contexts
614	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
615	* for the sake of simplicity. The AMD64 uses the PAE for the
616	* lower levels, making the total number of pages 11 (3 + 7 + 1).
617	*
618	* We assume that two page tables will be enought for the core code
619	* mappings (HC virtual and identity).
620	*/
621	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
622	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
623	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
624	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
625	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
626	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
627	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
628	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
629	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
630	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
631	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
632	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
633	if ( !pVM->pgm.s.pInterPD
634	\|\| !pVM->pgm.s.apInterPTs[0]
635	\|\| !pVM->pgm.s.apInterPTs[1]
636	\|\| !pVM->pgm.s.apInterPaePTs[0]
637	\|\| !pVM->pgm.s.apInterPaePTs[1]
638	\|\| !pVM->pgm.s.apInterPaePDs[0]
639	\|\| !pVM->pgm.s.apInterPaePDs[1]
640	\|\| !pVM->pgm.s.apInterPaePDs[2]
641	\|\| !pVM->pgm.s.apInterPaePDs[3]
642	\|\| !pVM->pgm.s.pInterPaePDPTR
643	\|\| !pVM->pgm.s.pInterPaePDPTR64
644	\|\| !pVM->pgm.s.pInterPaePML4)
645	{
646	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
647	return VERR_NO_PAGE_MEMORY;
648	}
649
650	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
651	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
652	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
653	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
654	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
655	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
656
657	/*
658	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
659	*/
660	ASMMemZeroPage(pVM->pgm.s.pInterPD);
661	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
662	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
663
664	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
665	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
666
667	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
668	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
669	{
670	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
671	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
672	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
673	}
674
675	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
676	{
677	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
678	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
679	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
680	}
681
682	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
683	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
684	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
685	\| HCPhysInterPaePDPTR64;
686
687	/*
688	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
689	* We allocate pages for all three posibilities to in order to simplify mappings and
690	* avoid resource failure during mode switches. So, we need to cover all levels of the
691	* of the first 4GB down to PD level.
692	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
693	*/
694	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
695	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
696	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
697	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
698	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
699	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
700	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
701	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
702	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
703	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
704	if ( !pVM->pgm.s.pHC32BitPD
705	\|\| !pVM->pgm.s.apHCPaePDs[0]
706	\|\| !pVM->pgm.s.apHCPaePDs[1]
707	\|\| !pVM->pgm.s.apHCPaePDs[2]
708	\|\| !pVM->pgm.s.apHCPaePDs[3]
709	\|\| !pVM->pgm.s.pHCPaePDPTR
710	\|\| !pVM->pgm.s.pHCPaePML4)
711	{
712	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
713	return VERR_NO_PAGE_MEMORY;
714	}
715
716	/* get physical addresses. */
717	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
718	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
719	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
720	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
721	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
722	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
723	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
724	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
725
726	/*
727	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
728	*/
729	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
730
731	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
732	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
733	{
734	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
735	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
736	/* The flags will be corrected when entering and leaving long mode. */
737	}
738
739	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
740	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
741	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
742
743	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
744
745	/*
746	* Initialize paging workers and mode from current host mode
747	* and the guest running in real mode.
748	*/
749	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
750	switch (pVM->pgm.s.enmHostMode)
751	{
752	case SUPPAGINGMODE_32_BIT:
753	case SUPPAGINGMODE_32_BIT_GLOBAL:
754	case SUPPAGINGMODE_PAE:
755	case SUPPAGINGMODE_PAE_GLOBAL:
756	case SUPPAGINGMODE_PAE_NX:
757	case SUPPAGINGMODE_PAE_GLOBAL_NX:
758	break;
759
760	case SUPPAGINGMODE_AMD64:
761	case SUPPAGINGMODE_AMD64_GLOBAL:
762	case SUPPAGINGMODE_AMD64_NX:
763	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
764	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
765	if (ARCH_BITS != 64)
766	{
767	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
768	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
769	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
770	}
771	#endif
772	break;
773	default:
774	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
775	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
776	}
777	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
778	if (VBOX_SUCCESS(rc))
779	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
780	if (VBOX_SUCCESS(rc))
781	{
782	LogFlow(("pgmR3InitPaging: returns successfully\n"));
783	#if HC_ARCH_BITS == 64
784	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
785	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
786	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
787	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
788	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
789	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
790	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
791	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
792	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
793	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
794	#endif
795
796	return VINF_SUCCESS;
797	}
798
799	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
800	return rc;
801	}
802
803
804	#ifdef VBOX_WITH_STATISTICS
805	/**
806	* Init statistics
807	*/
808	static void pgmR3InitStats(PVM pVM)
809	{
810	PPGM pPGM = &pVM->pgm.s;
811	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
812	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
813	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
814	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
815	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
816	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
817	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
818	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
819	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
820	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
821	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
822	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
823	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
824	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
825	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
826	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
827	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
828	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
829	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
830	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
831	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
832	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
833
834	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
835	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
836	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
837	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
838	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
839	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
840	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
841	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
842	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
843	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
844	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
845	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
846	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
847	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
848	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
849	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
850	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
851	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
852	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
853
854	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
855	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
856	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
857	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
858	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
859	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
860	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
861
862	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
863	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
864	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
865	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
866	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
867	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
868
869	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
870	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
871	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
872	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
873	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
874	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
875
876
877	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
878	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
879	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
880
881	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
882	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
883
884	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
885	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
886
887	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
888	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
889
890	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
891	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
892	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
893
894	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
895	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
896	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
897	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
898	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
899	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
900	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
901	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
902	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
903	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
904	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
905
906	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
907	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
908	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
909	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
910	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
911	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
912	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
913
914	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
915	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
916	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
917	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
918
919	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
920	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
921	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
922	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
923	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
924
925	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
926	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
927	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
928	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
929	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
930	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
931	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
932	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
933	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
934	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
935	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
936	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
937
938	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
939	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
940	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
941	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
942	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
943	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
944	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
945	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
946	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
947	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
948	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
949	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
950
951	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
952	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
953	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
954
955	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
956	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
957
958	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
959	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
960	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
961	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
962
963	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
964	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
965
966	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
967	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
968	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
969	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
970	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
971	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
972	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
973	#endif
974
975	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
976	{
977	/** @todo r=bird: We need a STAMR3RegisterF()! */
978	char szName[32];
979
980	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
981	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
982	AssertRC(rc);
983
984	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
985	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
986	AssertRC(rc);
987
988	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
989	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
990	AssertRC(rc);
991	}
992	}
993	#endif /* VBOX_WITH_STATISTICS */
994
995	/**
996	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
997	*
998	* The dynamic mapping area will also be allocated and initialized at this
999	* time. We could allocate it during PGMR3Init of course, but the mapping
1000	* wouldn't be allocated at that time preventing us from setting up the
1001	* page table entries with the dummy page.
1002	*
1003	* @returns VBox status code.
1004	* @param pVM VM handle.
1005	*/
1006	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1007	{
1008	/*
1009	* Reserve space for mapping the paging pages into guest context.
1010	*/
1011	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1012	AssertRCReturn(rc, rc);
1013	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1014
1015	/*
1016	* Reserve space for the dynamic mappings.
1017	*/
1018	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1019	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1020	if ( VBOX_SUCCESS(rc)
1021	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1022	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1023	if (VBOX_SUCCESS(rc))
1024	{
1025	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1026	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1027	}
1028	return rc;
1029	}
1030
1031
1032	/**
1033	* Ring-3 init finalizing.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The VM handle.
1037	*/
1038	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1039	{
1040	/*
1041	* Map the paging pages into the guest context.
1042	*/
1043	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1044	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1045
1046	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1047	AssertRCReturn(rc, rc);
1048	pVM->pgm.s.pGC32BitPD = GCPtr;
1049	GCPtr += PAGE_SIZE;
1050	GCPtr += PAGE_SIZE; /* reserved page */
1051
1052	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1053	{
1054	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1055	AssertRCReturn(rc, rc);
1056	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1057	GCPtr += PAGE_SIZE;
1058	}
1059	/* A bit of paranoia is justified. */
1060	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1061	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1062	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1063	GCPtr += PAGE_SIZE; /* reserved page */
1064
1065	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1066	AssertRCReturn(rc, rc);
1067	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1068	GCPtr += PAGE_SIZE;
1069	GCPtr += PAGE_SIZE; /* reserved page */
1070
1071	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1072	AssertRCReturn(rc, rc);
1073	pVM->pgm.s.pGCPaePML4 = GCPtr;
1074	GCPtr += PAGE_SIZE;
1075	GCPtr += PAGE_SIZE; /* reserved page */
1076
1077
1078	/*
1079	* Reserve space for the dynamic mappings.
1080	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1081	*/
1082	/* get the pointer to the page table entries. */
1083	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1084	AssertRelease(pMapping);
1085	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1086	const unsigned iPT = off >> X86_PD_SHIFT;
1087	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1088	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1089	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1090
1091	/* init cache */
1092	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1093	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1094	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1095
1096	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1097	{
1098	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1099	AssertRCReturn(rc, rc);
1100	}
1101
1102	return rc;
1103	}
1104
1105
1106	/**
1107	* Applies relocations to data and code managed by this
1108	* component. This function will be called at init and
1109	* whenever the VMM need to relocate it self inside the GC.
1110	*
1111	* @param pVM The VM.
1112	* @param offDelta Relocation delta relative to old location.
1113	*/
1114	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1115	{
1116	LogFlow(("PGMR3Relocate\n"));
1117
1118	/*
1119	* Paging stuff.
1120	*/
1121	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1122	/** @todo move this into shadow and guest specific relocation functions. */
1123	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1124	pVM->pgm.s.pGC32BitPD += offDelta;
1125	pVM->pgm.s.pGuestPDGC += offDelta;
1126	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1127	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1128	pVM->pgm.s.pGCPaePDPTR += offDelta;
1129	pVM->pgm.s.pGCPaePML4 += offDelta;
1130
1131	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1132	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1133
1134	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1135	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1136	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1137
1138	/*
1139	* Trees.
1140	*/
1141	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1142
1143	/*
1144	* Ram ranges.
1145	*/
1146	if (pVM->pgm.s.pRamRangesHC)
1147	{
1148	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1149	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1150	{
1151	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1152	if (pCur->pavHCChunkGC)
1153	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1154	}
1155	}
1156
1157	/*
1158	* Update the two page directories with all page table mappings.
1159	* (One or more of them have changed, that's why we're here.)
1160	*/
1161	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1162	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1163	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1164
1165	/* Relocate GC addresses of Page Tables. */
1166	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1167	{
1168	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1169	{
1170	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1171	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1172	}
1173	}
1174
1175	/*
1176	* Dynamic page mapping area.
1177	*/
1178	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1179	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1180	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1181
1182	/*
1183	* Physical and virtual handlers.
1184	*/
1185	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1186	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1187
1188	/*
1189	* The page pool.
1190	*/
1191	pgmR3PoolRelocate(pVM);
1192	}
1193
1194
1195	/**
1196	* Callback function for relocating a physical access handler.
1197	*
1198	* @returns 0 (continue enum)
1199	* @param pNode Pointer to a PGMPHYSHANDLER node.
1200	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1201	* not certain the delta will fit in a void pointer for all possible configs.
1202	*/
1203	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1204	{
1205	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1206	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1207	if (pHandler->pfnHandlerGC)
1208	pHandler->pfnHandlerGC += offDelta;
1209	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1210	pHandler->pvUserGC += offDelta;
1211	return 0;
1212	}
1213
1214
1215	/**
1216	* Callback function for relocating a virtual access handler.
1217	*
1218	* @returns 0 (continue enum)
1219	* @param pNode Pointer to a PGMVIRTHANDLER node.
1220	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1221	* not certain the delta will fit in a void pointer for all possible configs.
1222	*/
1223	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1224	{
1225	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1226	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1227	Assert(pHandler->pfnHandlerGC);
1228	pHandler->pfnHandlerGC += offDelta;
1229	return 0;
1230	}
1231
1232
1233	/**
1234	* The VM is being reset.
1235	*
1236	* For the PGM component this means that any PD write monitors
1237	* needs to be removed.
1238	*
1239	* @param pVM VM handle.
1240	*/
1241	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1242	{
1243	LogFlow(("PGMR3Reset:\n"));
1244	VM_ASSERT_EMT(pVM);
1245
1246	/*
1247	* Unfix any fixed mappings and disable CR3 monitoring.
1248	*/
1249	pVM->pgm.s.fMappingsFixed = false;
1250	pVM->pgm.s.GCPtrMappingFixed = 0;
1251	pVM->pgm.s.cbMappingFixed = 0;
1252
1253	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1254	AssertRC(rc);
1255	#ifdef DEBUG
1256	PGMR3DumpMappings(pVM);
1257	#endif
1258
1259	/*
1260	* Reset the shadow page pool.
1261	*/
1262	pgmR3PoolReset(pVM);
1263
1264	/*
1265	* Re-init other members.
1266	*/
1267	pVM->pgm.s.fA20Enabled = true;
1268
1269	/*
1270	* Clear the FFs PGM owns.
1271	*/
1272	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1273	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1274
1275	/*
1276	* Zero memory.
1277	*/
1278	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1279	{
1280	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1281	while (iPage-- > 0)
1282	{
1283	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1284	{
1285	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1286	continue;
1287	}
1288	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1289	{
1290	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1291	if (pRam->pavHCChunkHC[iChunk])
1292	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1293	}
1294	else
1295	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1296	}
1297	}
1298
1299	/*
1300	* Switch mode back to real mode.
1301	*/
1302	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1303	AssertReleaseRC(rc);
1304	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1305	}
1306
1307
1308	/**
1309	* Terminates the PGM.
1310	*
1311	* @returns VBox status code.
1312	* @param pVM Pointer to VM structure.
1313	*/
1314	PGMR3DECL(int) PGMR3Term(PVM pVM)
1315	{
1316	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1317	}
1318
1319
1320	/**
1321	* Execute state save operation.
1322	*
1323	* @returns VBox status code.
1324	* @param pVM VM Handle.
1325	* @param pSSM SSM operation handle.
1326	*/
1327	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1328	{
1329	PPGM pPGM = &pVM->pgm.s;
1330
1331	/*
1332	* Save basic data (required / unaffected by relocation).
1333	*/
1334	#if 1
1335	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1336	#else
1337	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1338	#endif
1339	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1340	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1341	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1342	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1343	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1344	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1345	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1346	SSMR3PutU32(pSSM, ~0); /* Separator. */
1347
1348	/*
1349	* The guest mappings.
1350	*/
1351	uint32_t i = 0;
1352	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1353	{
1354	SSMR3PutU32(pSSM, i);
1355	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1356	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1357	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1358	/* flags are done by the mapping owners! */
1359	}
1360	SSMR3PutU32(pSSM, ~0); /* terminator. */
1361
1362	/*
1363	* Ram range flags and bits.
1364	*/
1365	i = 0;
1366	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1367	{
1368	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1369
1370	SSMR3PutU32(pSSM, i);
1371	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1372	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1373	SSMR3PutGCPhys(pSSM, pRam->cb);
1374	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1375
1376	/* Flags. */
1377	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1378	for (unsigned iPage = 0; iPage < cPages; iPage++)
1379	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1380
1381	/* any memory associated with the range. */
1382	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1383	{
1384	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1385	{
1386	if (pRam->pavHCChunkHC[iChunk])
1387	{
1388	SSMR3PutU8(pSSM, 1); /* chunk present */
1389	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1390	}
1391	else
1392	SSMR3PutU8(pSSM, 0); /* no chunk present */
1393	}
1394	}
1395	else if (pRam->pvHC)
1396	{
1397	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1398	if (VBOX_FAILURE(rc))
1399	{
1400	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1401	return rc;
1402	}
1403	}
1404	}
1405	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1406	}
1407
1408
1409	/**
1410	* Execute state load operation.
1411	*
1412	* @returns VBox status code.
1413	* @param pVM VM Handle.
1414	* @param pSSM SSM operation handle.
1415	* @param u32Version Data layout version.
1416	*/
1417	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1418	{
1419	/*
1420	* Validate version.
1421	*/
1422	if (u32Version != PGM_SAVED_STATE_VERSION)
1423	{
1424	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1425	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1426	}
1427
1428	/*
1429	* Call the reset function to make sure all the memory is cleared.
1430	*/
1431	PGMR3Reset(pVM);
1432
1433	/*
1434	* Load basic data (required / unaffected by relocation).
1435	*/
1436	PPGM pPGM = &pVM->pgm.s;
1437	#if 1
1438	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1439	#else
1440	uint32_t u;
1441	SSMR3GetU32(pSSM, &u);
1442	pPGM->fMappingsFixed = u;
1443	#endif
1444	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1445	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1446
1447	RTUINT cbRamSize;
1448	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1449	if (VBOX_FAILURE(rc))
1450	return rc;
1451	if (cbRamSize != pPGM->cbRamSize)
1452	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1453	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1454	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1455	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1456	RTUINT uGuestMode;
1457	SSMR3GetUInt(pSSM, &uGuestMode);
1458	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1459
1460	/* check separator. */
1461	uint32_t u32Sep;
1462	SSMR3GetU32(pSSM, &u32Sep);
1463	if (VBOX_FAILURE(rc))
1464	return rc;
1465	if (u32Sep != (uint32_t)~0)
1466	{
1467	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1468	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1469	}
1470
1471	/*
1472	* The guest mappings.
1473	*/
1474	uint32_t i = 0;
1475	for (;; i++)
1476	{
1477	/* Check the seqence number / separator. */
1478	rc = SSMR3GetU32(pSSM, &u32Sep);
1479	if (VBOX_FAILURE(rc))
1480	return rc;
1481	if (u32Sep == ~0U)
1482	break;
1483	if (u32Sep != i)
1484	{
1485	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1486	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1487	}
1488
1489	/* get the mapping details. */
1490	char szDesc[256];
1491	szDesc[0] = '\0';
1492	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1493	if (VBOX_FAILURE(rc))
1494	return rc;
1495	RTGCPTR GCPtr;
1496	SSMR3GetGCPtr(pSSM, &GCPtr);
1497	RTGCUINTPTR cPTs;
1498	rc = SSMR3GetU32(pSSM, &cPTs);
1499	if (VBOX_FAILURE(rc))
1500	return rc;
1501
1502	/* find matching range. */
1503	PPGMMAPPING pMapping;
1504	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
1505	if ( pMapping->cPTs == cPTs
1506	&& !strcmp(pMapping->pszDesc, szDesc))
1507	break;
1508	if (!pMapping)
1509	{
1510	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1511	cPTs, szDesc, GCPtr));
1512	AssertFailed();
1513	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1514	}
1515
1516	/* relocate it. */
1517	if (pMapping->GCPtr != GCPtr)
1518	{
1519	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1520	#if HC_ARCH_BITS == 64
1521	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1522	#endif
1523	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1524	}
1525	else
1526	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1527	}
1528
1529	/*
1530	* Ram range flags and bits.
1531	*/
1532	i = 0;
1533	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1534	{
1535	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1536	/* Check the seqence number / separator. */
1537	rc = SSMR3GetU32(pSSM, &u32Sep);
1538	if (VBOX_FAILURE(rc))
1539	return rc;
1540	if (u32Sep == ~0U)
1541	break;
1542	if (u32Sep != i)
1543	{
1544	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1545	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1546	}
1547
1548	/* Get the range details. */
1549	RTGCPHYS GCPhys;
1550	SSMR3GetGCPhys(pSSM, &GCPhys);
1551	RTGCPHYS GCPhysLast;
1552	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1553	RTGCPHYS cb;
1554	SSMR3GetGCPhys(pSSM, &cb);
1555	uint8_t fHaveBits;
1556	rc = SSMR3GetU8(pSSM, &fHaveBits);
1557	if (VBOX_FAILURE(rc))
1558	return rc;
1559	if (fHaveBits & ~1)
1560	{
1561	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1562	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1563	}
1564
1565	/* Match it up with the current range. */
1566	if ( GCPhys != pRam->GCPhys
1567	\|\| GCPhysLast != pRam->GCPhysLast
1568	\|\| cb != pRam->cb
1569	\|\| fHaveBits != !!pRam->pvHC)
1570	{
1571	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1572	"State : %VGp-%VGp %VGp bytes %s\n",
1573	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1574	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1575	AssertFailed();
1576	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1577	}
1578
1579	/* Flags. */
1580	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1581	for (unsigned iPage = 0; iPage < cPages; iPage++)
1582	{
1583	uint16_t u16 = 0;
1584	SSMR3GetU16(pSSM, &u16);
1585	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1586	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1587	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1588	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1589	}
1590
1591	/* any memory associated with the range. */
1592	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1593	{
1594	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1595	{
1596	uint8_t fValidChunk;
1597
1598	rc = SSMR3GetU8(pSSM, &fValidChunk);
1599	if (VBOX_FAILURE(rc))
1600	return rc;
1601	if (fValidChunk > 1)
1602	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1603
1604	if (fValidChunk)
1605	{
1606	if (!pRam->pavHCChunkHC[iChunk])
1607	{
1608	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1609	if (VBOX_FAILURE(rc))
1610	return rc;
1611	}
1612	Assert(pRam->pavHCChunkHC[iChunk]);
1613
1614	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1615	}
1616	/* else nothing to do */
1617	}
1618	}
1619	else if (pRam->pvHC)
1620	{
1621	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1622	if (VBOX_FAILURE(rc))
1623	{
1624	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1625	return rc;
1626	}
1627	}
1628	}
1629
1630	/*
1631	* We require a full resync now.
1632	*/
1633	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1634	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1635	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1636	pPGM->fPhysCacheFlushPending = true;
1637	pgmR3HandlerPhysicalUpdateAll(pVM);
1638
1639	/*
1640	* Change the paging mode.
1641	*/
1642	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1643	}
1644
1645
1646	/**
1647	* Show paging mode.
1648	*
1649	* @param pVM VM Handle.
1650	* @param pHlp The info helpers.
1651	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1652	*/
1653	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1654	{
1655	/* digest argument. */
1656	bool fGuest, fShadow, fHost;
1657	if (pszArgs)
1658	pszArgs = RTStrStripL(pszArgs);
1659	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1660	fShadow = fHost = fGuest = true;
1661	else
1662	{
1663	fShadow = fHost = fGuest = false;
1664	if (strstr(pszArgs, "guest"))
1665	fGuest = true;
1666	if (strstr(pszArgs, "shadow"))
1667	fShadow = true;
1668	if (strstr(pszArgs, "host"))
1669	fHost = true;
1670	}
1671
1672	/* print info. */
1673	if (fGuest)
1674	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1675	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1676	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1677	if (fShadow)
1678	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1679	if (fHost)
1680	{
1681	const char *psz;
1682	switch (pVM->pgm.s.enmHostMode)
1683	{
1684	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1685	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1686	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1687	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1688	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1689	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1690	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1691	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1692	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1693	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1694	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1695	default: psz = "unknown"; break;
1696	}
1697	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1698	}
1699	}
1700
1701
1702	/**
1703	* Dump registered MMIO ranges to the log.
1704	*
1705	* @param pVM VM Handle.
1706	* @param pHlp The info helpers.
1707	* @param pszArgs Arguments, ignored.
1708	*/
1709	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1710	{
1711	NOREF(pszArgs);
1712	pHlp->pfnPrintf(pHlp,
1713	"RAM ranges (pVM=%p)\n"
1714	"%.s %.s\n",
1715	pVM,
1716	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1717	sizeof(RTHCPTR) * 2, "pvHC ");
1718
1719	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1720	pHlp->pfnPrintf(pHlp,
1721	"%VGp-%VGp %VHv\n",
1722	pCur->GCPhys,
1723	pCur->GCPhysLast,
1724	pCur->pvHC);
1725	}
1726
1727	/**
1728	* Dump the page directory to the log.
1729	*
1730	* @param pVM VM Handle.
1731	* @param pHlp The info helpers.
1732	* @param pszArgs Arguments, ignored.
1733	*/
1734	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1735	{
1736	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1737	/* Big pages supported? */
1738	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1739	/* Global pages supported? */
1740	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1741
1742	NOREF(pszArgs);
1743
1744	/*
1745	* Get page directory addresses.
1746	*/
1747	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1748	Assert(pPDSrc);
1749	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
1750
1751	/*
1752	* Iterate the page directory.
1753	*/
1754	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1755	{
1756	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1757	if (PdeSrc.n.u1Present)
1758	{
1759	if (PdeSrc.b.u1Size && fPSE)
1760	{
1761	pHlp->pfnPrintf(pHlp,
1762	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1763	iPD,
1764	PdeSrc.u & X86_PDE_PG_MASK,
1765	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1766	}
1767	else
1768	{
1769	pHlp->pfnPrintf(pHlp,
1770	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1771	iPD,
1772	PdeSrc.u & X86_PDE4M_PG_MASK,
1773	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1774	}
1775	}
1776	}
1777	}
1778
1779
1780	/**
1781	* Serivce a VMMCALLHOST_PGM_LOCK call.
1782	*
1783	* @returns VBox status code.
1784	* @param pVM The VM handle.
1785	*/
1786	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1787	{
1788	return pgmLock(pVM);
1789	}
1790
1791
1792	/**
1793	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1794	*
1795	* @returns PGM_TYPE_*.
1796	* @param pgmMode The mode value to convert.
1797	*/
1798	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1799	{
1800	switch (pgmMode)
1801	{
1802	case PGMMODE_REAL: return PGM_TYPE_REAL;
1803	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1804	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1805	case PGMMODE_PAE:
1806	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1807	case PGMMODE_AMD64:
1808	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1809	default:
1810	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1811	}
1812	}
1813
1814
1815	/**
1816	* Gets the index into the paging mode data array of a SHW+GST mode.
1817	*
1818	* @returns PGM::paPagingData index.
1819	* @param uShwType The shadow paging mode type.
1820	* @param uGstType The guest paging mode type.
1821	*/
1822	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1823	{
1824	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1825	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1826	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1827	+ (uGstType - PGM_TYPE_REAL);
1828	}
1829
1830
1831	/**
1832	* Gets the index into the paging mode data array of a SHW+GST mode.
1833	*
1834	* @returns PGM::paPagingData index.
1835	* @param enmShw The shadow paging mode.
1836	* @param enmGst The guest paging mode.
1837	*/
1838	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1839	{
1840	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1841	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1842	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1843	}
1844
1845
1846	/**
1847	* Calculates the max data index.
1848	* @returns The number of entries in the pagaing data array.
1849	*/
1850	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1851	{
1852	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1853	}
1854
1855
1856	/**
1857	* Initializes the paging mode data kept in PGM::paModeData.
1858	*
1859	* @param pVM The VM handle.
1860	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1861	* This is used early in the init process to avoid trouble with PDM
1862	* not being initialized yet.
1863	*/
1864	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1865	{
1866	PPGMMODEDATA pModeData;
1867	int rc;
1868
1869	/*
1870	* Allocate the array on the first call.
1871	*/
1872	if (!pVM->pgm.s.paModeData)
1873	{
1874	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1875	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1876	}
1877
1878	/*
1879	* Initialize the array entries.
1880	*/
1881	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1882	pModeData->uShwType = PGM_TYPE_32BIT;
1883	pModeData->uGstType = PGM_TYPE_REAL;
1884	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1885	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1886	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1887
1888	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1889	pModeData->uShwType = PGM_TYPE_32BIT;
1890	pModeData->uGstType = PGM_TYPE_PROT;
1891	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1892	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1893	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1894
1895	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1896	pModeData->uShwType = PGM_TYPE_32BIT;
1897	pModeData->uGstType = PGM_TYPE_32BIT;
1898	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1899	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1900	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1901
1902	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1903	pModeData->uShwType = PGM_TYPE_PAE;
1904	pModeData->uGstType = PGM_TYPE_REAL;
1905	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1906	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1907	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1908
1909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1910	pModeData->uShwType = PGM_TYPE_PAE;
1911	pModeData->uGstType = PGM_TYPE_PROT;
1912	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1913	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1914	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1915
1916	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1917	pModeData->uShwType = PGM_TYPE_PAE;
1918	pModeData->uGstType = PGM_TYPE_32BIT;
1919	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1920	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1921	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1922
1923	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1924	pModeData->uShwType = PGM_TYPE_PAE;
1925	pModeData->uGstType = PGM_TYPE_PAE;
1926	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1927	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1928	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1929
1930	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1931	pModeData->uShwType = PGM_TYPE_AMD64;
1932	pModeData->uGstType = PGM_TYPE_REAL;
1933	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1934	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1935	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1936
1937	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1938	pModeData->uShwType = PGM_TYPE_AMD64;
1939	pModeData->uGstType = PGM_TYPE_PROT;
1940	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1941	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1942	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1943
1944	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1945	pModeData->uShwType = PGM_TYPE_AMD64;
1946	pModeData->uGstType = PGM_TYPE_AMD64;
1947	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1948	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1949	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1950
1951	return VINF_SUCCESS;
1952	}
1953
1954
1955	/**
1956	* Swtich to different (or relocated in the relocate case) mode data.
1957	*
1958	* @param pVM The VM handle.
1959	* @param enmShw The the shadow paging mode.
1960	* @param enmGst The the guest paging mode.
1961	*/
1962	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1963	{
1964	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1965
1966	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1967	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1968
1969	/* shadow */
1970	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
1971	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
1972	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
1973	Assert(pVM->pgm.s.pfnR3ShwGetPage);
1974	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
1975	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
1976	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
1977	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
1978
1979	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
1980	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
1981	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
1982	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
1983	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
1984
1985	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
1986	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
1987	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
1988	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
1989	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
1990
1991
1992	/* guest */
1993	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
1994	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
1995	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
1996	Assert(pVM->pgm.s.pfnR3GstGetPage);
1997	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
1998	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
1999	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2000	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2001	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2002	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2003	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2004	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2005
2006	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2007	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2008	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2009	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2010	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2011	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2012	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2013	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2014
2015	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2016	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2017	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2018	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2019	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2020	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2021	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2022	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2023
2024
2025	/* both */
2026	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2027	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2028	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2029	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2030	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2031	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2032	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2033	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2034	#ifdef VBOX_STRICT
2035	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2036	#endif
2037
2038	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2039	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2040	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2041	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2042	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2043	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2044	#ifdef VBOX_STRICT
2045	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2046	#endif
2047
2048	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2049	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2050	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2051	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2052	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2053	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2054	#ifdef VBOX_STRICT
2055	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2056	#endif
2057	}
2058
2059
2060	#ifdef DEBUG_bird
2061	#include <stdlib.h> /* getenv() remove me! */
2062	#endif
2063
2064	/**
2065	* Calculates the shadow paging mode.
2066	*
2067	* @returns The shadow paging mode.
2068	* @param enmGuestMode The guest mode.
2069	* @param enmHostMode The host mode.
2070	* @param enmShadowMode The current shadow mode.
2071	* @param penmSwitcher Where to store the switcher to use.
2072	* VMMSWITCHER_INVALID means no change.
2073	*/
2074	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2075	{
2076	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2077	switch (enmGuestMode)
2078	{
2079	/*
2080	* When switching to real or protected mode we don't change
2081	* anything since it's likely that we'll switch back pretty soon.
2082	*
2083	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2084	* and is supposed to determin which shadow paging and switcher to
2085	* use during init.
2086	*/
2087	case PGMMODE_REAL:
2088	case PGMMODE_PROTECTED:
2089	if (enmShadowMode != PGMMODE_INVALID)
2090	break; /* (no change) */
2091	switch (enmHostMode)
2092	{
2093	case SUPPAGINGMODE_32_BIT:
2094	case SUPPAGINGMODE_32_BIT_GLOBAL:
2095	enmShadowMode = PGMMODE_32_BIT;
2096	enmSwitcher = VMMSWITCHER_32_TO_32;
2097	break;
2098
2099	case SUPPAGINGMODE_PAE:
2100	case SUPPAGINGMODE_PAE_NX:
2101	case SUPPAGINGMODE_PAE_GLOBAL:
2102	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2103	enmShadowMode = PGMMODE_PAE;
2104	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2105	#ifdef DEBUG_bird
2106	if (getenv("VBOX_32BIT"))
2107	{
2108	enmShadowMode = PGMMODE_32_BIT;
2109	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2110	}
2111	#endif
2112	break;
2113
2114	case SUPPAGINGMODE_AMD64:
2115	case SUPPAGINGMODE_AMD64_GLOBAL:
2116	case SUPPAGINGMODE_AMD64_NX:
2117	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2118	enmShadowMode = PGMMODE_PAE;
2119	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2120	break;
2121
2122	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2123	}
2124	break;
2125
2126	case PGMMODE_32_BIT:
2127	switch (enmHostMode)
2128	{
2129	case SUPPAGINGMODE_32_BIT:
2130	case SUPPAGINGMODE_32_BIT_GLOBAL:
2131	enmShadowMode = PGMMODE_32_BIT;
2132	enmSwitcher = VMMSWITCHER_32_TO_32;
2133	break;
2134
2135	case SUPPAGINGMODE_PAE:
2136	case SUPPAGINGMODE_PAE_NX:
2137	case SUPPAGINGMODE_PAE_GLOBAL:
2138	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2139	enmShadowMode = PGMMODE_PAE;
2140	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2141	#ifdef DEBUG_bird
2142	if (getenv("VBOX_32BIT"))
2143	{
2144	enmShadowMode = PGMMODE_32_BIT;
2145	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2146	}
2147	#endif
2148	break;
2149
2150	case SUPPAGINGMODE_AMD64:
2151	case SUPPAGINGMODE_AMD64_GLOBAL:
2152	case SUPPAGINGMODE_AMD64_NX:
2153	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2154	enmShadowMode = PGMMODE_PAE;
2155	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2156	break;
2157
2158	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2159	}
2160	break;
2161
2162	case PGMMODE_PAE:
2163	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2164	switch (enmHostMode)
2165	{
2166	case SUPPAGINGMODE_32_BIT:
2167	case SUPPAGINGMODE_32_BIT_GLOBAL:
2168	enmShadowMode = PGMMODE_PAE;
2169	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2170	break;
2171
2172	case SUPPAGINGMODE_PAE:
2173	case SUPPAGINGMODE_PAE_NX:
2174	case SUPPAGINGMODE_PAE_GLOBAL:
2175	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2176	enmShadowMode = PGMMODE_PAE;
2177	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2178	break;
2179
2180	case SUPPAGINGMODE_AMD64:
2181	case SUPPAGINGMODE_AMD64_GLOBAL:
2182	case SUPPAGINGMODE_AMD64_NX:
2183	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2184	enmShadowMode = PGMMODE_PAE;
2185	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2186	break;
2187
2188	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2189	}
2190	break;
2191
2192	case PGMMODE_AMD64:
2193	case PGMMODE_AMD64_NX:
2194	switch (enmHostMode)
2195	{
2196	case SUPPAGINGMODE_32_BIT:
2197	case SUPPAGINGMODE_32_BIT_GLOBAL:
2198	enmShadowMode = PGMMODE_PAE;
2199	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2200	break;
2201
2202	case SUPPAGINGMODE_PAE:
2203	case SUPPAGINGMODE_PAE_NX:
2204	case SUPPAGINGMODE_PAE_GLOBAL:
2205	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2206	enmShadowMode = PGMMODE_PAE;
2207	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2208	break;
2209
2210	case SUPPAGINGMODE_AMD64:
2211	case SUPPAGINGMODE_AMD64_GLOBAL:
2212	case SUPPAGINGMODE_AMD64_NX:
2213	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2214	enmShadowMode = PGMMODE_PAE;
2215	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2216	break;
2217
2218	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2219	}
2220	break;
2221
2222
2223	default:
2224	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2225	return PGMMODE_INVALID;
2226	}
2227
2228	*penmSwitcher = enmSwitcher;
2229	return enmShadowMode;
2230	}
2231
2232
2233	/**
2234	* Performs the actual mode change.
2235	* This is called by PGMChangeMode and pgmR3InitPaging().
2236	*
2237	* @returns VBox status code.
2238	* @param pVM VM handle.
2239	* @param enmGuestMode The new guest mode. This is assumed to be different from
2240	* the current mode.
2241	*/
2242	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2243	{
2244	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2245	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2246
2247	/*
2248	* Calc the shadow mode and switcher.
2249	*/
2250	VMMSWITCHER enmSwitcher;
2251	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2252	if (enmSwitcher != VMMSWITCHER_INVALID)
2253	{
2254	/*
2255	* Select new switcher.
2256	*/
2257	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2258	if (VBOX_FAILURE(rc))
2259	{
2260	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2261	return rc;
2262	}
2263	}
2264
2265	/*
2266	* Exit old mode(s).
2267	*/
2268	/* shadow */
2269	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2270	{
2271	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2272	if (PGM_SHW_PFN(Exit, pVM))
2273	{
2274	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2275	if (VBOX_FAILURE(rc))
2276	{
2277	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2278	return rc;
2279	}
2280	}
2281
2282	}
2283
2284	/* guest */
2285	if (PGM_GST_PFN(Exit, pVM))
2286	{
2287	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2288	if (VBOX_FAILURE(rc))
2289	{
2290	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2291	return rc;
2292	}
2293	}
2294
2295	/*
2296	* Load new paging mode data.
2297	*/
2298	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2299
2300	/*
2301	* Enter new shadow mode (if changed).
2302	*/
2303	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2304	{
2305	int rc;
2306	pVM->pgm.s.enmShadowMode = enmShadowMode;
2307	switch (enmShadowMode)
2308	{
2309	case PGMMODE_32_BIT:
2310	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2311	break;
2312	case PGMMODE_PAE:
2313	case PGMMODE_PAE_NX:
2314	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2315	break;
2316	case PGMMODE_AMD64:
2317	case PGMMODE_AMD64_NX:
2318	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2319	break;
2320	case PGMMODE_REAL:
2321	case PGMMODE_PROTECTED:
2322	default:
2323	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2324	return VERR_INTERNAL_ERROR;
2325	}
2326	if (VBOX_FAILURE(rc))
2327	{
2328	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2329	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2330	return rc;
2331	}
2332	}
2333
2334	/*
2335	* Enter the new guest and shadow+guest modes.
2336	*/
2337	int rc = -1;
2338	int rc2 = -1;
2339	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2340	pVM->pgm.s.enmGuestMode = enmGuestMode;
2341	switch (enmGuestMode)
2342	{
2343	case PGMMODE_REAL:
2344	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2345	switch (pVM->pgm.s.enmShadowMode)
2346	{
2347	case PGMMODE_32_BIT:
2348	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2349	break;
2350	case PGMMODE_PAE:
2351	case PGMMODE_PAE_NX:
2352	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2353	break;
2354	case PGMMODE_AMD64:
2355	case PGMMODE_AMD64_NX:
2356	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2357	break;
2358	default: AssertFailed(); break;
2359	}
2360	break;
2361
2362	case PGMMODE_PROTECTED:
2363	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2364	switch (pVM->pgm.s.enmShadowMode)
2365	{
2366	case PGMMODE_32_BIT:
2367	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2368	break;
2369	case PGMMODE_PAE:
2370	case PGMMODE_PAE_NX:
2371	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2372	break;
2373	case PGMMODE_AMD64:
2374	case PGMMODE_AMD64_NX:
2375	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2376	break;
2377	default: AssertFailed(); break;
2378	}
2379	break;
2380
2381	case PGMMODE_32_BIT:
2382	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2383	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2384	switch (pVM->pgm.s.enmShadowMode)
2385	{
2386	case PGMMODE_32_BIT:
2387	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2388	break;
2389	case PGMMODE_PAE:
2390	case PGMMODE_PAE_NX:
2391	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2392	break;
2393	case PGMMODE_AMD64:
2394	case PGMMODE_AMD64_NX:
2395	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2396	default: AssertFailed(); break;
2397	}
2398	break;
2399
2400	//case PGMMODE_PAE_NX:
2401	case PGMMODE_PAE:
2402	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2403	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2404	switch (pVM->pgm.s.enmShadowMode)
2405	{
2406	case PGMMODE_PAE:
2407	case PGMMODE_PAE_NX:
2408	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2409	break;
2410	case PGMMODE_32_BIT:
2411	case PGMMODE_AMD64:
2412	case PGMMODE_AMD64_NX:
2413	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2414	default: AssertFailed(); break;
2415	}
2416	break;
2417
2418	//case PGMMODE_AMD64_NX:
2419	case PGMMODE_AMD64:
2420	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2421	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2422	switch (pVM->pgm.s.enmShadowMode)
2423	{
2424	case PGMMODE_AMD64:
2425	case PGMMODE_AMD64_NX:
2426	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2427	break;
2428	case PGMMODE_32_BIT:
2429	case PGMMODE_PAE:
2430	case PGMMODE_PAE_NX:
2431	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2432	default: AssertFailed(); break;
2433	}
2434	break;
2435
2436	default:
2437	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2438	rc = VERR_NOT_IMPLEMENTED;
2439	break;
2440	}
2441
2442	/* status codes. */
2443	AssertRC(rc);
2444	AssertRC(rc2);
2445	if (VBOX_SUCCESS(rc))
2446	{
2447	rc = rc2;
2448	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2449	rc = VINF_SUCCESS;
2450	}
2451
2452	/*
2453	* Notify SELM so it can update the TSSes with correct CR3s.
2454	*/
2455	SELMR3PagingModeChanged(pVM);
2456
2457	/* Notify HWACCM as well. */
2458	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2459	return rc;
2460	}
2461
2462
2463	/**
2464	* Dumps a PAE shadow page table.
2465	*
2466	* @returns VBox status code (VINF_SUCCESS).
2467	* @param pVM The VM handle.
2468	* @param pPT Pointer to the page table.
2469	* @param u64Address The virtual address of the page table starts.
2470	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2471	* @param cMaxDepth The maxium depth.
2472	* @param pHlp Pointer to the output functions.
2473	*/
2474	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2475	{
2476	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2477	{
2478	X86PTEPAE Pte = pPT->a[i];
2479	if (Pte.n.u1Present)
2480	{
2481	pHlp->pfnPrintf(pHlp,
2482	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2483	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2484	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2485	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2486	Pte.n.u1Write ? 'W' : 'R',
2487	Pte.n.u1User ? 'U' : 'S',
2488	Pte.n.u1Accessed ? 'A' : '-',
2489	Pte.n.u1Dirty ? 'D' : '-',
2490	Pte.n.u1Global ? 'G' : '-',
2491	Pte.n.u1WriteThru ? "WT" : "--",
2492	Pte.n.u1CacheDisable? "CD" : "--",
2493	Pte.n.u1PAT ? "AT" : "--",
2494	Pte.n.u1NoExecute ? "NX" : "--",
2495	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2496	Pte.u & BIT(10) ? '1' : '0',
2497	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2498	Pte.u & X86_PTE_PAE_PG_MASK);
2499	}
2500	}
2501	return VINF_SUCCESS;
2502	}
2503
2504
2505	/**
2506	* Dumps a PAE shadow page directory table.
2507	*
2508	* @returns VBox status code (VINF_SUCCESS).
2509	* @param pVM The VM handle.
2510	* @param HCPhys The physical address of the page directory table.
2511	* @param u64Address The virtual address of the page table starts.
2512	* @param cr4 The CR4, PSE is currently used.
2513	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2514	* @param cMaxDepth The maxium depth.
2515	* @param pHlp Pointer to the output functions.
2516	*/
2517	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2518	{
2519	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2520	if (!pPD)
2521	{
2522	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2523	fLongMode ? 16 : 8, u64Address, HCPhys);
2524	return VERR_INVALID_PARAMETER;
2525	}
2526	int rc = VINF_SUCCESS;
2527	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2528	{
2529	X86PDEPAE Pde = pPD->a[i];
2530	if (Pde.n.u1Present)
2531	{
2532	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2533	pHlp->pfnPrintf(pHlp,
2534	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2535	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2536	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2537	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2538	Pde.b.u1Write ? 'W' : 'R',
2539	Pde.b.u1User ? 'U' : 'S',
2540	Pde.b.u1Accessed ? 'A' : '-',
2541	Pde.b.u1Dirty ? 'D' : '-',
2542	Pde.b.u1Global ? 'G' : '-',
2543	Pde.b.u1WriteThru ? "WT" : "--",
2544	Pde.b.u1CacheDisable? "CD" : "--",
2545	Pde.b.u1PAT ? "AT" : "--",
2546	Pde.b.u1NoExecute ? "NX" : "--",
2547	Pde.u & BIT64(9) ? '1' : '0',
2548	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2549	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2550	Pde.u & X86_PDE_PAE_PG_MASK);
2551	else
2552	{
2553	pHlp->pfnPrintf(pHlp,
2554	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2555	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2556	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2557	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2558	Pde.n.u1Write ? 'W' : 'R',
2559	Pde.n.u1User ? 'U' : 'S',
2560	Pde.n.u1Accessed ? 'A' : '-',
2561	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2562	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2563	Pde.n.u1WriteThru ? "WT" : "--",
2564	Pde.n.u1CacheDisable? "CD" : "--",
2565	Pde.n.u1NoExecute ? "NX" : "--",
2566	Pde.u & BIT64(9) ? '1' : '0',
2567	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2568	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2569	Pde.u & X86_PDE_PAE_PG_MASK);
2570	if (cMaxDepth >= 1)
2571	{
2572	/** @todo what about using the page pool for mapping PTs? */
2573	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2574	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2575	PX86PTPAE pPT = NULL;
2576	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2577	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2578	else
2579	{
2580	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2581	{
2582	uint64_t off = u64AddressPT - pMap->GCPtr;
2583	if (off < pMap->cb)
2584	{
2585	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2586	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2587	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2588	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2589	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2590	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2591	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
2592	}
2593	}
2594	}
2595	int rc2 = VERR_INVALID_PARAMETER;
2596	if (pPT)
2597	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2598	else
2599	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2600	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2601	if (rc2 < rc && VBOX_SUCCESS(rc))
2602	rc = rc2;
2603	}
2604	}
2605	}
2606	}
2607	return rc;
2608	}
2609
2610
2611	/**
2612	* Dumps a PAE shadow page directory pointer table.
2613	*
2614	* @returns VBox status code (VINF_SUCCESS).
2615	* @param pVM The VM handle.
2616	* @param HCPhys The physical address of the page directory pointer table.
2617	* @param u64Address The virtual address of the page table starts.
2618	* @param cr4 The CR4, PSE is currently used.
2619	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2620	* @param cMaxDepth The maxium depth.
2621	* @param pHlp Pointer to the output functions.
2622	*/
2623	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2624	{
2625	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2626	if (!pPDPTR)
2627	{
2628	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2629	fLongMode ? 16 : 8, u64Address, HCPhys);
2630	return VERR_INVALID_PARAMETER;
2631	}
2632
2633	int rc = VINF_SUCCESS;
2634	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2635	for (unsigned i = 0; i < c; i++)
2636	{
2637	X86PDPE Pdpe = pPDPTR->a[i];
2638	if (Pdpe.n.u1Present)
2639	{
2640	if (fLongMode)
2641	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2642	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2643	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2644	Pdpe.n.u1Write ? 'W' : 'R',
2645	Pdpe.n.u1User ? 'U' : 'S',
2646	Pdpe.n.u1Accessed ? 'A' : '-',
2647	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2648	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2649	Pdpe.n.u1WriteThru ? "WT" : "--",
2650	Pdpe.n.u1CacheDisable? "CD" : "--",
2651	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2652	Pdpe.n.u1NoExecute ? "NX" : "--",
2653	Pdpe.u & BIT(9) ? '1' : '0',
2654	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2655	Pdpe.u & BIT(11) ? '1' : '0',
2656	Pdpe.u & X86_PDPE_PG_MASK);
2657	else
2658	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2659	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2660	i << X86_PDPTR_SHIFT,
2661	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2662	Pdpe.n.u1User ? '!' : '.', /* mbz */
2663	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2664	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2665	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2666	Pdpe.n.u1WriteThru ? "WT" : "--",
2667	Pdpe.n.u1CacheDisable? "CD" : "--",
2668	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2669	Pdpe.n.u1NoExecute ? "NX" : "--",
2670	Pdpe.u & BIT(9) ? '1' : '0',
2671	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2672	Pdpe.u & BIT(11) ? '1' : '0',
2673	Pdpe.u & X86_PDPE_PG_MASK);
2674	if (cMaxDepth >= 1)
2675	{
2676	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2677	cr4, fLongMode, cMaxDepth - 1, pHlp);
2678	if (rc2 < rc && VBOX_SUCCESS(rc))
2679	rc = rc2;
2680	}
2681	}
2682	}
2683	return rc;
2684	}
2685
2686
2687	/**
2688	* Dumps a 32-bit shadow page table.
2689	*
2690	* @returns VBox status code (VINF_SUCCESS).
2691	* @param pVM The VM handle.
2692	* @param HCPhys The physical address of the table.
2693	* @param cr4 The CR4, PSE is currently used.
2694	* @param cMaxDepth The maxium depth.
2695	* @param pHlp Pointer to the output functions.
2696	*/
2697	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2698	{
2699	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2700	if (!pPML4)
2701	{
2702	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2703	return VERR_INVALID_PARAMETER;
2704	}
2705
2706	int rc = VINF_SUCCESS;
2707	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2708	{
2709	X86PML4E Pml4e = pPML4->a[i];
2710	if (Pml4e.n.u1Present)
2711	{
2712	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2713	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2714	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2715	u64Address,
2716	Pml4e.n.u1Write ? 'W' : 'R',
2717	Pml4e.n.u1User ? 'U' : 'S',
2718	Pml4e.n.u1Accessed ? 'A' : '-',
2719	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2720	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2721	Pml4e.n.u1WriteThru ? "WT" : "--",
2722	Pml4e.n.u1CacheDisable? "CD" : "--",
2723	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2724	Pml4e.n.u1NoExecute ? "NX" : "--",
2725	Pml4e.u & BIT(9) ? '1' : '0',
2726	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2727	Pml4e.u & BIT(11) ? '1' : '0',
2728	Pml4e.u & X86_PML4E_PG_MASK);
2729
2730	if (cMaxDepth >= 1)
2731	{
2732	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2733	if (rc2 < rc && VBOX_SUCCESS(rc))
2734	rc = rc2;
2735	}
2736	}
2737	}
2738	return rc;
2739	}
2740
2741
2742	/**
2743	* Dumps a 32-bit shadow page table.
2744	*
2745	* @returns VBox status code (VINF_SUCCESS).
2746	* @param pVM The VM handle.
2747	* @param pPT Pointer to the page table.
2748	* @param u32Address The virtual address this table starts at.
2749	* @param pHlp Pointer to the output functions.
2750	*/
2751	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2752	{
2753	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2754	{
2755	X86PTE Pte = pPT->a[i];
2756	if (Pte.n.u1Present)
2757	{
2758	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2759	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2760	u32Address + (i << X86_PT_SHIFT),
2761	Pte.n.u1Write ? 'W' : 'R',
2762	Pte.n.u1User ? 'U' : 'S',
2763	Pte.n.u1Accessed ? 'A' : '-',
2764	Pte.n.u1Dirty ? 'D' : '-',
2765	Pte.n.u1Global ? 'G' : '-',
2766	Pte.n.u1WriteThru ? "WT" : "--",
2767	Pte.n.u1CacheDisable? "CD" : "--",
2768	Pte.n.u1PAT ? "AT" : "--",
2769	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2770	Pte.u & BIT(10) ? '1' : '0',
2771	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2772	Pte.u & X86_PDE_PG_MASK);
2773	}
2774	}
2775	return VINF_SUCCESS;
2776	}
2777
2778
2779	/**
2780	* Dumps a 32-bit shadow page directory and page tables.
2781	*
2782	* @returns VBox status code (VINF_SUCCESS).
2783	* @param pVM The VM handle.
2784	* @param cr3 The root of the hierarchy.
2785	* @param cr4 The CR4, PSE is currently used.
2786	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2787	* @param pHlp Pointer to the output functions.
2788	*/
2789	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2790	{
2791	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2792	if (!pPD)
2793	{
2794	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2795	return VERR_INVALID_PARAMETER;
2796	}
2797
2798	int rc = VINF_SUCCESS;
2799	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2800	{
2801	X86PDE Pde = pPD->a[i];
2802	if (Pde.n.u1Present)
2803	{
2804	const uint32_t u32Address = i << X86_PD_SHIFT;
2805	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2806	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2807	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2808	u32Address,
2809	Pde.b.u1Write ? 'W' : 'R',
2810	Pde.b.u1User ? 'U' : 'S',
2811	Pde.b.u1Accessed ? 'A' : '-',
2812	Pde.b.u1Dirty ? 'D' : '-',
2813	Pde.b.u1Global ? 'G' : '-',
2814	Pde.b.u1WriteThru ? "WT" : "--",
2815	Pde.b.u1CacheDisable? "CD" : "--",
2816	Pde.b.u1PAT ? "AT" : "--",
2817	Pde.u & BIT64(9) ? '1' : '0',
2818	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2819	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2820	Pde.u & X86_PDE4M_PG_MASK);
2821	else
2822	{
2823	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2824	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2825	u32Address,
2826	Pde.n.u1Write ? 'W' : 'R',
2827	Pde.n.u1User ? 'U' : 'S',
2828	Pde.n.u1Accessed ? 'A' : '-',
2829	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2830	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2831	Pde.n.u1WriteThru ? "WT" : "--",
2832	Pde.n.u1CacheDisable? "CD" : "--",
2833	Pde.u & BIT64(9) ? '1' : '0',
2834	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2835	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2836	Pde.u & X86_PDE_PG_MASK);
2837	if (cMaxDepth >= 1)
2838	{
2839	/** @todo what about using the page pool for mapping PTs? */
2840	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2841	PX86PT pPT = NULL;
2842	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2843	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2844	else
2845	{
2846	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2847	if (u32Address - pMap->GCPtr < pMap->cb)
2848	{
2849	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2850	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2851	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2852	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2853	pPT = pMap->aPTs[iPDE].pPTR3;
2854	}
2855	}
2856	int rc2 = VERR_INVALID_PARAMETER;
2857	if (pPT)
2858	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2859	else
2860	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2861	if (rc2 < rc && VBOX_SUCCESS(rc))
2862	rc = rc2;
2863	}
2864	}
2865	}
2866	}
2867
2868	return rc;
2869	}
2870
2871
2872	/**
2873	* Dumps a 32-bit shadow page table.
2874	*
2875	* @returns VBox status code (VINF_SUCCESS).
2876	* @param pVM The VM handle.
2877	* @param pPT Pointer to the page table.
2878	* @param u32Address The virtual address this table starts at.
2879	* @param PhysSearch Address to search for.
2880	*/
2881	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2882	{
2883	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2884	{
2885	X86PTE Pte = pPT->a[i];
2886	if (Pte.n.u1Present)
2887	{
2888	Log(( /P R S A D G WT CD AT NX 4M a m d /
2889	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2890	u32Address + (i << X86_PT_SHIFT),
2891	Pte.n.u1Write ? 'W' : 'R',
2892	Pte.n.u1User ? 'U' : 'S',
2893	Pte.n.u1Accessed ? 'A' : '-',
2894	Pte.n.u1Dirty ? 'D' : '-',
2895	Pte.n.u1Global ? 'G' : '-',
2896	Pte.n.u1WriteThru ? "WT" : "--",
2897	Pte.n.u1CacheDisable? "CD" : "--",
2898	Pte.n.u1PAT ? "AT" : "--",
2899	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2900	Pte.u & BIT(10) ? '1' : '0',
2901	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2902	Pte.u & X86_PDE_PG_MASK));
2903
2904	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2905	{
2906	uint64_t fPageShw = 0;
2907	RTHCPHYS pPhysHC = 0;
2908
2909	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2910	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2911	}
2912	}
2913	}
2914	return VINF_SUCCESS;
2915	}
2916
2917
2918	/**
2919	* Dumps a 32-bit guest page directory and page tables.
2920	*
2921	* @returns VBox status code (VINF_SUCCESS).
2922	* @param pVM The VM handle.
2923	* @param cr3 The root of the hierarchy.
2924	* @param cr4 The CR4, PSE is currently used.
2925	* @param PhysSearch Address to search for.
2926	*/
2927	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2928	{
2929	bool fLongMode = false;
2930	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2931	PX86PD pPD = 0;
2932
2933	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2934	if (VBOX_FAILURE(rc) \|\| !pPD)
2935	{
2936	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2937	return VERR_INVALID_PARAMETER;
2938	}
2939
2940	Log(("cr3=%08x cr4=%08x%s\n"
2941	"%-*s P - Present\n"
2942	"%-*s \| R/W - Read (0) / Write (1)\n"
2943	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2944	"%-*s \| \| \| A - Accessed\n"
2945	"%-*s \| \| \| \| D - Dirty\n"
2946	"%-*s \| \| \| \| \| G - Global\n"
2947	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2948	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2949	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2950	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2951	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2952	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2953	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2954	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2955	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2956	- W U - - - -- -- -- -- -- 010 */
2957	, cr3, cr4, fLongMode ? " Long Mode" : "",
2958	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2959	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2960
2961	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2962	{
2963	X86PDE Pde = pPD->a[i];
2964	if (Pde.n.u1Present)
2965	{
2966	const uint32_t u32Address = i << X86_PD_SHIFT;
2967
2968	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2969	Log(( /P R S A D G WT CD AT NX 4M a m d /
2970	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2971	u32Address,
2972	Pde.b.u1Write ? 'W' : 'R',
2973	Pde.b.u1User ? 'U' : 'S',
2974	Pde.b.u1Accessed ? 'A' : '-',
2975	Pde.b.u1Dirty ? 'D' : '-',
2976	Pde.b.u1Global ? 'G' : '-',
2977	Pde.b.u1WriteThru ? "WT" : "--",
2978	Pde.b.u1CacheDisable? "CD" : "--",
2979	Pde.b.u1PAT ? "AT" : "--",
2980	Pde.u & BIT(9) ? '1' : '0',
2981	Pde.u & BIT(10) ? '1' : '0',
2982	Pde.u & BIT(11) ? '1' : '0',
2983	Pde.u & X86_PDE4M_PG_MASK));
2984	/** @todo PhysSearch */
2985	else
2986	{
2987	Log(( /P R S A D G WT CD AT NX 4M a m d /
2988	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2989	u32Address,
2990	Pde.n.u1Write ? 'W' : 'R',
2991	Pde.n.u1User ? 'U' : 'S',
2992	Pde.n.u1Accessed ? 'A' : '-',
2993	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2994	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2995	Pde.n.u1WriteThru ? "WT" : "--",
2996	Pde.n.u1CacheDisable? "CD" : "--",
2997	Pde.u & BIT(9) ? '1' : '0',
2998	Pde.u & BIT(10) ? '1' : '0',
2999	Pde.u & BIT(11) ? '1' : '0',
3000	Pde.u & X86_PDE_PG_MASK));
3001	////if (cMaxDepth >= 1)
3002	{
3003	/** @todo what about using the page pool for mapping PTs? */
3004	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3005	PX86PT pPT = NULL;
3006
3007	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3008
3009	int rc2 = VERR_INVALID_PARAMETER;
3010	if (pPT)
3011	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3012	else
3013	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3014	if (rc2 < rc && VBOX_SUCCESS(rc))
3015	rc = rc2;
3016	}
3017	}
3018	}
3019	}
3020
3021	return rc;
3022	}
3023
3024
3025	/**
3026	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3027	*
3028	* @returns VBox status code (VINF_SUCCESS).
3029	* @param pVM The VM handle.
3030	* @param cr3 The root of the hierarchy.
3031	* @param cr4 The cr4, only PAE and PSE is currently used.
3032	* @param fLongMode Set if long mode, false if not long mode.
3033	* @param cMaxDepth Number of levels to dump.
3034	* @param pHlp Pointer to the output functions.
3035	*/
3036	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3037	{
3038	if (!pHlp)
3039	pHlp = DBGFR3InfoLogHlp();
3040	if (!cMaxDepth)
3041	return VINF_SUCCESS;
3042	const unsigned cch = fLongMode ? 16 : 8;
3043	pHlp->pfnPrintf(pHlp,
3044	"cr3=%08x cr4=%08x%s\n"
3045	"%-*s P - Present\n"
3046	"%-*s \| R/W - Read (0) / Write (1)\n"
3047	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3048	"%-*s \| \| \| A - Accessed\n"
3049	"%-*s \| \| \| \| D - Dirty\n"
3050	"%-*s \| \| \| \| \| G - Global\n"
3051	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3052	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3053	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3054	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3055	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3056	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3057	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3058	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3059	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3060	- W U - - - -- -- -- -- -- 010 */
3061	, cr3, cr4, fLongMode ? " Long Mode" : "",
3062	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3063	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3064	if (cr4 & X86_CR4_PAE)
3065	{
3066	if (fLongMode)
3067	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3068	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3069	}
3070	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3071	}
3072
3073
3074
3075	#ifdef VBOX_WITH_DEBUGGER
3076	/**
3077	* The '.pgmram' command.
3078	*
3079	* @returns VBox status.
3080	* @param pCmd Pointer to the command descriptor (as registered).
3081	* @param pCmdHlp Pointer to command helper functions.
3082	* @param pVM Pointer to the current VM (if any).
3083	* @param paArgs Pointer to (readonly) array of arguments.
3084	* @param cArgs Number of arguments in the array.
3085	*/
3086	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3087	{
3088	/*
3089	* Validate input.
3090	*/
3091	if (!pVM)
3092	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3093	if (!pVM->pgm.s.pRamRangesGC)
3094	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3095
3096	/*
3097	* Dump the ranges.
3098	*/
3099	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3100	PPGMRAMRANGE pRam;
3101	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3102	{
3103	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3104	"%VGp - %VGp %p\n",
3105	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3106	if (VBOX_FAILURE(rc))
3107	return rc;
3108	}
3109
3110	return VINF_SUCCESS;
3111	}
3112
3113
3114	/**
3115	* The '.pgmmap' command.
3116	*
3117	* @returns VBox status.
3118	* @param pCmd Pointer to the command descriptor (as registered).
3119	* @param pCmdHlp Pointer to command helper functions.
3120	* @param pVM Pointer to the current VM (if any).
3121	* @param paArgs Pointer to (readonly) array of arguments.
3122	* @param cArgs Number of arguments in the array.
3123	*/
3124	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3125	{
3126	/*
3127	* Validate input.
3128	*/
3129	if (!pVM)
3130	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3131	if (!pVM->pgm.s.pMappingsR3)
3132	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3133
3134	/*
3135	* Print message about the fixedness of the mappings.
3136	*/
3137	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3138	if (VBOX_FAILURE(rc))
3139	return rc;
3140
3141	/*
3142	* Dump the ranges.
3143	*/
3144	PPGMMAPPING pCur;
3145	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3146	{
3147	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3148	"%08x - %08x %s\n",
3149	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3150	if (VBOX_FAILURE(rc))
3151	return rc;
3152	}
3153
3154	return VINF_SUCCESS;
3155	}
3156
3157
3158	/**
3159	* The '.pgmsync' command.
3160	*
3161	* @returns VBox status.
3162	* @param pCmd Pointer to the command descriptor (as registered).
3163	* @param pCmdHlp Pointer to command helper functions.
3164	* @param pVM Pointer to the current VM (if any).
3165	* @param paArgs Pointer to (readonly) array of arguments.
3166	* @param cArgs Number of arguments in the array.
3167	*/
3168	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3169	{
3170	/*
3171	* Validate input.
3172	*/
3173	if (!pVM)
3174	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3175
3176	/*
3177	* Force page directory sync.
3178	*/
3179	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3180
3181	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3182	if (VBOX_FAILURE(rc))
3183	return rc;
3184
3185	return VINF_SUCCESS;
3186	}
3187
3188
3189	/**
3190	* The '.pgmsyncalways' command.
3191	*
3192	* @returns VBox status.
3193	* @param pCmd Pointer to the command descriptor (as registered).
3194	* @param pCmdHlp Pointer to command helper functions.
3195	* @param pVM Pointer to the current VM (if any).
3196	* @param paArgs Pointer to (readonly) array of arguments.
3197	* @param cArgs Number of arguments in the array.
3198	*/
3199	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3200	{
3201	/*
3202	* Validate input.
3203	*/
3204	if (!pVM)
3205	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3206
3207	/*
3208	* Force page directory sync.
3209	*/
3210	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3211	{
3212	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3213	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3214	}
3215	else
3216	{
3217	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3218	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3219	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3220	}
3221	}
3222
3223	#endif
3224
3225	/**
3226	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3227	*/
3228	typedef struct PGMCHECKINTARGS
3229	{
3230	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3231	PPGMPHYSHANDLER pPrevPhys;
3232	PPGMVIRTHANDLER pPrevVirt;
3233	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3234	PVM pVM;
3235	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3236
3237	/**
3238	* Validate a node in the physical handler tree.
3239	*
3240	* @returns 0 on if ok, other wise 1.
3241	* @param pNode The handler node.
3242	* @param pvUser pVM.
3243	*/
3244	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3245	{
3246	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3247	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3248	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3249	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3250	AssertReleaseMsg( !pArgs->pPrevPhys
3251	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3252	("pPrevPhys=%p %VGp-%VGp %s\n"
3253	" pCur=%p %VGp-%VGp %s\n",
3254	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3255	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3256	pArgs->pPrevPhys = pCur;
3257	return 0;
3258	}
3259
3260
3261	/**
3262	* Validate a node in the virtual handler tree.
3263	*
3264	* @returns 0 on if ok, other wise 1.
3265	* @param pNode The handler node.
3266	* @param pvUser pVM.
3267	*/
3268	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3269	{
3270	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3271	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3272	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3273	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3274	AssertReleaseMsg( !pArgs->pPrevVirt
3275	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3276	("pPrevVirt=%p %VGv-%VGv %s\n"
3277	" pCur=%p %VGv-%VGv %s\n",
3278	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3279	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3280	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3281	{
3282	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3283	("pCur=%p %VGv-%VGv %s\n"
3284	"iPage=%d offVirtHandle=%#x expected %#x\n",
3285	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3286	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3287	}
3288	pArgs->pPrevVirt = pCur;
3289	return 0;
3290	}
3291
3292
3293	/**
3294	* Validate a node in the virtual handler tree.
3295	*
3296	* @returns 0 on if ok, other wise 1.
3297	* @param pNode The handler node.
3298	* @param pvUser pVM.
3299	*/
3300	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3301	{
3302	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3303	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3304	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3305	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3306	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3307	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3308	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3309	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3310	" pCur=%p %VGp-%VGp\n",
3311	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3312	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3313	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3314	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3315	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3316	" pCur=%p %VGp-%VGp\n",
3317	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3318	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3319	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3320	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3321	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3322	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3323	{
3324	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3325	for (;;)
3326	{
3327	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3328	AssertReleaseMsg(pCur2 != pCur,
3329	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3330	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3331	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3332	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3333	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3334	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3335	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3336	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3337	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3338	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3339	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3340	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3341	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3342	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3343	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3344	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3345	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3346	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3347	break;
3348	}
3349	}
3350
3351	pArgs->pPrevPhys2Virt = pCur;
3352	return 0;
3353	}
3354
3355
3356	/**
3357	* Perform an integrity check on the PGM component.
3358	*
3359	* @returns VINF_SUCCESS if everything is fine.
3360	* @returns VBox error status after asserting on integrity breach.
3361	* @param pVM The VM handle.
3362	*/
3363	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3364	{
3365	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3366
3367	/*
3368	* Check the trees.
3369	*/
3370	int cErrors = 0;
3371	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3372	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3373	Args.fLeftToRight = false;
3374	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3375	Args.fLeftToRight = true;
3376	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3377	Args.fLeftToRight = false;
3378	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3379	Args.fLeftToRight = true;
3380	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3381	Args.fLeftToRight = false;
3382	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3383
3384	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3385	}
3386
3387
3388	/**
3389	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3390	*
3391	* @returns VBox status code.
3392	* @param pVM VM handle.
3393	* @param fEnable Enable or disable shadow mappings
3394	*/
3395	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3396	{
3397	pVM->pgm.s.fDisableMappings = !fEnable;
3398
3399	size_t cb;
3400	int rc = PGMR3MappingsSize(pVM, &cb);
3401	AssertRCReturn(rc, rc);
3402
3403	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3404	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3405	AssertRCReturn(rc, rc);
3406
3407	return VINF_SUCCESS;
3408	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 2584

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