PGM.cpp@ 27046

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1	/* $Id: PGM.cpp 27038 2010-03-04 14:48:14Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/selm.h>
588	#include <VBox/ssm.h>
589	#include <VBox/hwaccm.h>
590	#include "PGMInternal.h"
591	#include <VBox/vm.h>
592	#include "PGMInline.h"
593
594	#include <VBox/dbg.h>
595	#include <VBox/param.h>
596	#include <VBox/err.h>
597
598	#include <iprt/asm.h>
599	#include <iprt/assert.h>
600	#include <iprt/env.h>
601	#include <iprt/mem.h>
602	#include <iprt/file.h>
603	#include <iprt/string.h>
604	#include <iprt/thread.h>
605
606
607	/*******************************************************************************
608	* Defined Constants And Macros *
609	*******************************************************************************/
610	/** Saved state data unit version for 2.5.x and later. */
611	#define PGM_SAVED_STATE_VERSION 9
612	/** Saved state data unit version for 2.2.2 and later. */
613	#define PGM_SAVED_STATE_VERSION_2_2_2 8
614	/** Saved state data unit version for 2.2.0. */
615	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
616	/** Saved state data unit version. */
617	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
618
619
620	/*******************************************************************************
621	* Internal Functions *
622	*******************************************************************************/
623	static int pgmR3InitPaging(PVM pVM);
624	static void pgmR3InitStats(PVM pVM);
625	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	#ifdef VBOX_STRICT
632	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
633	#endif
634	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
635	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
636	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
637
638	#ifdef VBOX_WITH_DEBUGGER
639	/** @todo Convert the first two commands to 'info' items. */
640	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# ifdef VBOX_STRICT
645	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	# endif
647	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	#endif
649
650
651	/*******************************************************************************
652	* Global Variables *
653	*******************************************************************************/
654	#ifdef VBOX_WITH_DEBUGGER
655	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
656	static const DBGCVARDESC g_aPgmErrorArgs[] =
657	{
658	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
659	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
660	};
661
662	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
663	{
664	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
665	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
666	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
667	};
668
669	/** Command descriptors. */
670	static const DBGCCMD g_aCmds[] =
671	{
672	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
673	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
674	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
675	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
676	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
677	#ifdef VBOX_STRICT
678	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
679	#endif
680	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
681	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
682	};
683	#endif
684
685
686
687
688	/*
689	* Shadow - 32-bit mode
690	*/
691	#define PGM_SHW_TYPE PGM_TYPE_32BIT
692	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
693	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
694	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
695	#include "PGMShw.h"
696
697	/* Guest - real mode */
698	#define PGM_GST_TYPE PGM_TYPE_REAL
699	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
707	#include "PGMBth.h"
708	#include "PGMGstDefs.h"
709	#include "PGMGst.h"
710	#undef BTH_PGMPOOLKIND_PT_FOR_PT
711	#undef BTH_PGMPOOLKIND_ROOT
712	#undef PGM_BTH_NAME
713	#undef PGM_BTH_NAME_RC_STR
714	#undef PGM_BTH_NAME_R0_STR
715	#undef PGM_GST_TYPE
716	#undef PGM_GST_NAME
717	#undef PGM_GST_NAME_RC_STR
718	#undef PGM_GST_NAME_R0_STR
719
720	/* Guest - protected mode */
721	#define PGM_GST_TYPE PGM_TYPE_PROT
722	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
723	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
724	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
725	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
726	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
727	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
728	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
729	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
730	#include "PGMBth.h"
731	#include "PGMGstDefs.h"
732	#include "PGMGst.h"
733	#undef BTH_PGMPOOLKIND_PT_FOR_PT
734	#undef BTH_PGMPOOLKIND_ROOT
735	#undef PGM_BTH_NAME
736	#undef PGM_BTH_NAME_RC_STR
737	#undef PGM_BTH_NAME_R0_STR
738	#undef PGM_GST_TYPE
739	#undef PGM_GST_NAME
740	#undef PGM_GST_NAME_RC_STR
741	#undef PGM_GST_NAME_R0_STR
742
743	/* Guest - 32-bit mode */
744	#define PGM_GST_TYPE PGM_TYPE_32BIT
745	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
746	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
747	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
748	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
749	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
750	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
751	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
752	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
753	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
754	#include "PGMBth.h"
755	#include "PGMGstDefs.h"
756	#include "PGMGst.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
758	#undef BTH_PGMPOOLKIND_PT_FOR_PT
759	#undef BTH_PGMPOOLKIND_ROOT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_RC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_RC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	#undef PGM_SHW_TYPE
769	#undef PGM_SHW_NAME
770	#undef PGM_SHW_NAME_RC_STR
771	#undef PGM_SHW_NAME_R0_STR
772
773
774	/*
775	* Shadow - PAE mode
776	*/
777	#define PGM_SHW_TYPE PGM_TYPE_PAE
778	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
779	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
780	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
782	#include "PGMShw.h"
783
784	/* Guest - real mode */
785	#define PGM_GST_TYPE PGM_TYPE_REAL
786	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
787	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
788	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
789	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
790	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
791	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
792	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
793	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
794	#include "PGMGstDefs.h"
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_PT
797	#undef BTH_PGMPOOLKIND_ROOT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_RC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_RC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - protected mode */
807	#define PGM_GST_TYPE PGM_TYPE_PROT
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
809	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
812	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
815	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
816	#include "PGMGstDefs.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_PT
819	#undef BTH_PGMPOOLKIND_ROOT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_RC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_RC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	/* Guest - 32-bit mode */
829	#define PGM_GST_TYPE PGM_TYPE_32BIT
830	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
831	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
832	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
833	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
834	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
835	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
836	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
837	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
838	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
839	#include "PGMGstDefs.h"
840	#include "PGMBth.h"
841	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
842	#undef BTH_PGMPOOLKIND_PT_FOR_PT
843	#undef BTH_PGMPOOLKIND_ROOT
844	#undef PGM_BTH_NAME
845	#undef PGM_BTH_NAME_RC_STR
846	#undef PGM_BTH_NAME_R0_STR
847	#undef PGM_GST_TYPE
848	#undef PGM_GST_NAME
849	#undef PGM_GST_NAME_RC_STR
850	#undef PGM_GST_NAME_R0_STR
851
852	/* Guest - PAE mode */
853	#define PGM_GST_TYPE PGM_TYPE_PAE
854	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
855	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
856	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
857	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
858	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
859	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
860	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
863	#include "PGMBth.h"
864	#include "PGMGstDefs.h"
865	#include "PGMGst.h"
866	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
867	#undef BTH_PGMPOOLKIND_PT_FOR_PT
868	#undef BTH_PGMPOOLKIND_ROOT
869	#undef PGM_BTH_NAME
870	#undef PGM_BTH_NAME_RC_STR
871	#undef PGM_BTH_NAME_R0_STR
872	#undef PGM_GST_TYPE
873	#undef PGM_GST_NAME
874	#undef PGM_GST_NAME_RC_STR
875	#undef PGM_GST_NAME_R0_STR
876
877	#undef PGM_SHW_TYPE
878	#undef PGM_SHW_NAME
879	#undef PGM_SHW_NAME_RC_STR
880	#undef PGM_SHW_NAME_R0_STR
881
882
883	/*
884	* Shadow - AMD64 mode
885	*/
886	#define PGM_SHW_TYPE PGM_TYPE_AMD64
887	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
888	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
889	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
890	#include "PGMShw.h"
891
892	#ifdef VBOX_WITH_64_BITS_GUESTS
893	/* Guest - AMD64 mode */
894	# define PGM_GST_TYPE PGM_TYPE_AMD64
895	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
896	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
897	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
898	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
899	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
900	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
901	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
902	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
903	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
904	# include "PGMBth.h"
905	# include "PGMGstDefs.h"
906	# include "PGMGst.h"
907	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
908	# undef BTH_PGMPOOLKIND_PT_FOR_PT
909	# undef BTH_PGMPOOLKIND_ROOT
910	# undef PGM_BTH_NAME
911	# undef PGM_BTH_NAME_RC_STR
912	# undef PGM_BTH_NAME_R0_STR
913	# undef PGM_GST_TYPE
914	# undef PGM_GST_NAME
915	# undef PGM_GST_NAME_RC_STR
916	# undef PGM_GST_NAME_R0_STR
917	#endif /* VBOX_WITH_64_BITS_GUESTS */
918
919	#undef PGM_SHW_TYPE
920	#undef PGM_SHW_NAME
921	#undef PGM_SHW_NAME_RC_STR
922	#undef PGM_SHW_NAME_R0_STR
923
924
925	/*
926	* Shadow - Nested paging mode
927	*/
928	#define PGM_SHW_TYPE PGM_TYPE_NESTED
929	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
930	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
931	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
932	#include "PGMShw.h"
933
934	/* Guest - real mode */
935	#define PGM_GST_TYPE PGM_TYPE_REAL
936	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
937	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
938	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
939	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
940	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
941	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
942	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
943	#include "PGMGstDefs.h"
944	#include "PGMBth.h"
945	#undef BTH_PGMPOOLKIND_PT_FOR_PT
946	#undef PGM_BTH_NAME
947	#undef PGM_BTH_NAME_RC_STR
948	#undef PGM_BTH_NAME_R0_STR
949	#undef PGM_GST_TYPE
950	#undef PGM_GST_NAME
951	#undef PGM_GST_NAME_RC_STR
952	#undef PGM_GST_NAME_R0_STR
953
954	/* Guest - protected mode */
955	#define PGM_GST_TYPE PGM_TYPE_PROT
956	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
957	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
958	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
959	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
960	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
961	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
962	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
963	#include "PGMGstDefs.h"
964	#include "PGMBth.h"
965	#undef BTH_PGMPOOLKIND_PT_FOR_PT
966	#undef PGM_BTH_NAME
967	#undef PGM_BTH_NAME_RC_STR
968	#undef PGM_BTH_NAME_R0_STR
969	#undef PGM_GST_TYPE
970	#undef PGM_GST_NAME
971	#undef PGM_GST_NAME_RC_STR
972	#undef PGM_GST_NAME_R0_STR
973
974	/* Guest - 32-bit mode */
975	#define PGM_GST_TYPE PGM_TYPE_32BIT
976	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
977	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
978	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
979	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
980	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
981	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
982	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
983	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
984	#include "PGMGstDefs.h"
985	#include "PGMBth.h"
986	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
987	#undef BTH_PGMPOOLKIND_PT_FOR_PT
988	#undef PGM_BTH_NAME
989	#undef PGM_BTH_NAME_RC_STR
990	#undef PGM_BTH_NAME_R0_STR
991	#undef PGM_GST_TYPE
992	#undef PGM_GST_NAME
993	#undef PGM_GST_NAME_RC_STR
994	#undef PGM_GST_NAME_R0_STR
995
996	/* Guest - PAE mode */
997	#define PGM_GST_TYPE PGM_TYPE_PAE
998	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
999	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1000	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1001	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1002	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1003	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1004	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1005	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1006	#include "PGMGstDefs.h"
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	#ifdef VBOX_WITH_64_BITS_GUESTS
1019	/* Guest - AMD64 mode */
1020	# define PGM_GST_TYPE PGM_TYPE_AMD64
1021	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1022	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1023	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1024	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1025	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1026	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1027	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1028	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1029	# include "PGMGstDefs.h"
1030	# include "PGMBth.h"
1031	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1032	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1033	# undef PGM_BTH_NAME
1034	# undef PGM_BTH_NAME_RC_STR
1035	# undef PGM_BTH_NAME_R0_STR
1036	# undef PGM_GST_TYPE
1037	# undef PGM_GST_NAME
1038	# undef PGM_GST_NAME_RC_STR
1039	# undef PGM_GST_NAME_R0_STR
1040	#endif /* VBOX_WITH_64_BITS_GUESTS */
1041
1042	#undef PGM_SHW_TYPE
1043	#undef PGM_SHW_NAME
1044	#undef PGM_SHW_NAME_RC_STR
1045	#undef PGM_SHW_NAME_R0_STR
1046
1047
1048	/*
1049	* Shadow - EPT
1050	*/
1051	#define PGM_SHW_TYPE PGM_TYPE_EPT
1052	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1053	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1054	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1055	#include "PGMShw.h"
1056
1057	/* Guest - real mode */
1058	#define PGM_GST_TYPE PGM_TYPE_REAL
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1060	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1063	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1066	#include "PGMGstDefs.h"
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1069	#undef PGM_BTH_NAME
1070	#undef PGM_BTH_NAME_RC_STR
1071	#undef PGM_BTH_NAME_R0_STR
1072	#undef PGM_GST_TYPE
1073	#undef PGM_GST_NAME
1074	#undef PGM_GST_NAME_RC_STR
1075	#undef PGM_GST_NAME_R0_STR
1076
1077	/* Guest - protected mode */
1078	#define PGM_GST_TYPE PGM_TYPE_PROT
1079	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1080	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1081	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1082	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1083	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1084	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1085	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1086	#include "PGMGstDefs.h"
1087	#include "PGMBth.h"
1088	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	#undef PGM_BTH_NAME
1090	#undef PGM_BTH_NAME_RC_STR
1091	#undef PGM_BTH_NAME_R0_STR
1092	#undef PGM_GST_TYPE
1093	#undef PGM_GST_NAME
1094	#undef PGM_GST_NAME_RC_STR
1095	#undef PGM_GST_NAME_R0_STR
1096
1097	/* Guest - 32-bit mode */
1098	#define PGM_GST_TYPE PGM_TYPE_32BIT
1099	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1100	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1101	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1102	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1103	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1104	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1105	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1106	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1107	#include "PGMGstDefs.h"
1108	#include "PGMBth.h"
1109	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1110	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1111	#undef PGM_BTH_NAME
1112	#undef PGM_BTH_NAME_RC_STR
1113	#undef PGM_BTH_NAME_R0_STR
1114	#undef PGM_GST_TYPE
1115	#undef PGM_GST_NAME
1116	#undef PGM_GST_NAME_RC_STR
1117	#undef PGM_GST_NAME_R0_STR
1118
1119	/* Guest - PAE mode */
1120	#define PGM_GST_TYPE PGM_TYPE_PAE
1121	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1122	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1123	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1124	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1125	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1126	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1127	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1128	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1129	#include "PGMGstDefs.h"
1130	#include "PGMBth.h"
1131	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1132	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1133	#undef PGM_BTH_NAME
1134	#undef PGM_BTH_NAME_RC_STR
1135	#undef PGM_BTH_NAME_R0_STR
1136	#undef PGM_GST_TYPE
1137	#undef PGM_GST_NAME
1138	#undef PGM_GST_NAME_RC_STR
1139	#undef PGM_GST_NAME_R0_STR
1140
1141	#ifdef VBOX_WITH_64_BITS_GUESTS
1142	/* Guest - AMD64 mode */
1143	# define PGM_GST_TYPE PGM_TYPE_AMD64
1144	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1145	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1146	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1147	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1148	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1149	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1150	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1151	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1152	# include "PGMGstDefs.h"
1153	# include "PGMBth.h"
1154	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1155	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1156	# undef PGM_BTH_NAME
1157	# undef PGM_BTH_NAME_RC_STR
1158	# undef PGM_BTH_NAME_R0_STR
1159	# undef PGM_GST_TYPE
1160	# undef PGM_GST_NAME
1161	# undef PGM_GST_NAME_RC_STR
1162	# undef PGM_GST_NAME_R0_STR
1163	#endif /* VBOX_WITH_64_BITS_GUESTS */
1164
1165	#undef PGM_SHW_TYPE
1166	#undef PGM_SHW_NAME
1167	#undef PGM_SHW_NAME_RC_STR
1168	#undef PGM_SHW_NAME_R0_STR
1169
1170
1171
1172	/**
1173	* Initiates the paging of VM.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM Pointer to VM structure.
1177	*/
1178	VMMR3DECL(int) PGMR3Init(PVM pVM)
1179	{
1180	LogFlow(("PGMR3Init:\n"));
1181	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1182	int rc;
1183
1184	/*
1185	* Assert alignment and sizes.
1186	*/
1187	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1188	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1189	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1190
1191	/*
1192	* Init the structure.
1193	*/
1194	#ifdef PGM_WITHOUT_MAPPINGS
1195	pVM->pgm.s.fMappingsDisabled = true;
1196	#endif
1197	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1198	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1199
1200	/* Init the per-CPU part. */
1201	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1202	{
1203	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1204	PPGMCPU pPGM = &pVCpu->pgm.s;
1205
1206	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1207	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1208	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1209
1210	pPGM->enmShadowMode = PGMMODE_INVALID;
1211	pPGM->enmGuestMode = PGMMODE_INVALID;
1212
1213	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1214
1215	pPGM->pGstPaePdptR3 = NULL;
1216	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1217	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1218	#endif
1219	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1220	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1221	{
1222	pPGM->apGstPaePDsR3[i] = NULL;
1223	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1224	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1225	#endif
1226	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1227	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1228	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1229	}
1230
1231	pPGM->fA20Enabled = true;
1232	}
1233
1234	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1235	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1236	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1237
1238	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1239	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1240	true
1241	#else
1242	false
1243	#endif
1244	);
1245	AssertLogRelRCReturn(rc, rc);
1246
1247	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1248	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1249	#else
1250	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1251	#endif
1252	AssertLogRelRCReturn(rc, rc);
1253	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1254	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1255
1256	/*
1257	* Get the configured RAM size - to estimate saved state size.
1258	*/
1259	uint64_t cbRam;
1260	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1261	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1262	cbRam = 0;
1263	else if (RT_SUCCESS(rc))
1264	{
1265	if (cbRam < PAGE_SIZE)
1266	cbRam = 0;
1267	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1268	}
1269	else
1270	{
1271	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1272	return rc;
1273	}
1274
1275	/*
1276	* Register callbacks, string formatters and the saved state data unit.
1277	*/
1278	#ifdef VBOX_STRICT
1279	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1280	#endif
1281	PGMRegisterStringFormatTypes();
1282
1283	rc = pgmR3InitSavedState(pVM, cbRam);
1284	if (RT_FAILURE(rc))
1285	return rc;
1286
1287	/*
1288	* Initialize the PGM critical section and flush the phys TLBs
1289	*/
1290	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1291	AssertRCReturn(rc, rc);
1292
1293	PGMR3PhysChunkInvalidateTLB(pVM);
1294	PGMPhysInvalidatePageMapTLB(pVM);
1295
1296	/*
1297	* For the time being we sport a full set of handy pages in addition to the base
1298	* memory to simplify things.
1299	*/
1300	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1301	AssertRCReturn(rc, rc);
1302
1303	/*
1304	* Trees
1305	*/
1306	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1307	if (RT_SUCCESS(rc))
1308	{
1309	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1310	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1311
1312	/*
1313	* Alocate the zero page.
1314	*/
1315	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1316	}
1317	if (RT_SUCCESS(rc))
1318	{
1319	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1320	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1321	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1322	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1323
1324	/*
1325	* Init the paging.
1326	*/
1327	rc = pgmR3InitPaging(pVM);
1328	}
1329	if (RT_SUCCESS(rc))
1330	{
1331	/*
1332	* Init the page pool.
1333	*/
1334	rc = pgmR3PoolInit(pVM);
1335	}
1336	if (RT_SUCCESS(rc))
1337	{
1338	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1339	{
1340	PVMCPU pVCpu = &pVM->aCpus[i];
1341	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1342	if (RT_FAILURE(rc))
1343	break;
1344	}
1345	}
1346
1347	if (RT_SUCCESS(rc))
1348	{
1349	/*
1350	* Info & statistics
1351	*/
1352	DBGFR3InfoRegisterInternal(pVM, "mode",
1353	"Shows the current paging mode. "
1354	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1355	pgmR3InfoMode);
1356	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1357	"Dumps all the entries in the top level paging table. No arguments.",
1358	pgmR3InfoCr3);
1359	DBGFR3InfoRegisterInternal(pVM, "phys",
1360	"Dumps all the physical address ranges. No arguments.",
1361	pgmR3PhysInfo);
1362	DBGFR3InfoRegisterInternal(pVM, "handlers",
1363	"Dumps physical, virtual and hyper virtual handlers. "
1364	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1365	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1366	pgmR3InfoHandlers);
1367	DBGFR3InfoRegisterInternal(pVM, "mappings",
1368	"Dumps guest mappings.",
1369	pgmR3MapInfo);
1370
1371	pgmR3InitStats(pVM);
1372
1373	#ifdef VBOX_WITH_DEBUGGER
1374	/*
1375	* Debugger commands.
1376	*/
1377	static bool s_fRegisteredCmds = false;
1378	if (!s_fRegisteredCmds)
1379	{
1380	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1381	if (RT_SUCCESS(rc2))
1382	s_fRegisteredCmds = true;
1383	}
1384	#endif
1385	return VINF_SUCCESS;
1386	}
1387
1388	/* Almost no cleanup necessary, MM frees all memory. */
1389	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1390
1391	return rc;
1392	}
1393
1394
1395	/**
1396	* Initializes the per-VCPU PGM.
1397	*
1398	* @returns VBox status code.
1399	* @param pVM The VM to operate on.
1400	*/
1401	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1402	{
1403	LogFlow(("PGMR3InitCPU\n"));
1404	return VINF_SUCCESS;
1405	}
1406
1407
1408	/**
1409	* Init paging.
1410	*
1411	* Since we need to check what mode the host is operating in before we can choose
1412	* the right paging functions for the host we have to delay this until R0 has
1413	* been initialized.
1414	*
1415	* @returns VBox status code.
1416	* @param pVM VM handle.
1417	*/
1418	static int pgmR3InitPaging(PVM pVM)
1419	{
1420	/*
1421	* Force a recalculation of modes and switcher so everyone gets notified.
1422	*/
1423	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1424	{
1425	PVMCPU pVCpu = &pVM->aCpus[i];
1426
1427	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1428	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1429	}
1430
1431	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1432
1433	/*
1434	* Allocate static mapping space for whatever the cr3 register
1435	* points to and in the case of PAE mode to the 4 PDs.
1436	*/
1437	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1438	if (RT_FAILURE(rc))
1439	{
1440	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1441	return rc;
1442	}
1443	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1444
1445	/*
1446	* Allocate pages for the three possible intermediate contexts
1447	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1448	* for the sake of simplicity. The AMD64 uses the PAE for the
1449	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1450	*
1451	* We assume that two page tables will be enought for the core code
1452	* mappings (HC virtual and identity).
1453	*/
1454	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1455	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1456	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1466
1467	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1468	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1469	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1470	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1471	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1472	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1473
1474	/*
1475	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1476	*/
1477	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1478	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1479	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1480
1481	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1482	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1483
1484	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1485	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1486	{
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1488	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1489	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1490	}
1491
1492	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1493	{
1494	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1495	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1496	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1497	}
1498
1499	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1500	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1501	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1502	\| HCPhysInterPaePDPT64;
1503
1504	/*
1505	* Initialize paging workers and mode from current host mode
1506	* and the guest running in real mode.
1507	*/
1508	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1509	switch (pVM->pgm.s.enmHostMode)
1510	{
1511	case SUPPAGINGMODE_32_BIT:
1512	case SUPPAGINGMODE_32_BIT_GLOBAL:
1513	case SUPPAGINGMODE_PAE:
1514	case SUPPAGINGMODE_PAE_GLOBAL:
1515	case SUPPAGINGMODE_PAE_NX:
1516	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1517	break;
1518
1519	case SUPPAGINGMODE_AMD64:
1520	case SUPPAGINGMODE_AMD64_GLOBAL:
1521	case SUPPAGINGMODE_AMD64_NX:
1522	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1523	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1524	if (ARCH_BITS != 64)
1525	{
1526	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1527	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1528	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1529	}
1530	#endif
1531	break;
1532	default:
1533	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1534	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1535	}
1536	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1537	if (RT_SUCCESS(rc))
1538	{
1539	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1540	#if HC_ARCH_BITS == 64
1541	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1542	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1543	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1544	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1545	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1546	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1547	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1548	#endif
1549
1550	return VINF_SUCCESS;
1551	}
1552
1553	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1554	return rc;
1555	}
1556
1557
1558	/**
1559	* Init statistics
1560	*/
1561	static void pgmR3InitStats(PVM pVM)
1562	{
1563	PPGM pPGM = &pVM->pgm.s;
1564	int rc;
1565
1566	/* Common - misc variables */
1567	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1568	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1569	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1570	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1571	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1572	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1573	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1574	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1575	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1576	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1577	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1578	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1579	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1580
1581	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1582	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1583	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1584	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1585
1586	/* Live save */
1587	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1588	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1589	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1590	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1591	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1592	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1593	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1594	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1595	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1596	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1597	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1598	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1599	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1600	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1601	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1602	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1603	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1604	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1605
1606	#ifdef VBOX_WITH_STATISTICS
1607
1608	# define PGM_REG_COUNTER(a, b, c) \
1609	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1610	AssertRC(rc);
1611
1612	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1613	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1614	AssertRC(rc);
1615
1616	# define PGM_REG_PROFILE(a, b, c) \
1617	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1618	AssertRC(rc);
1619
1620	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1621	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1622	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1623	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1624	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1625	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1626	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1627	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1628	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1629	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1630
1631	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1632	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1633	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1634	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1635	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1636	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1637	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1638	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1639	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1640	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1641
1642	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1643	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1644	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1645	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1646
1647	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1648	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1649	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1650	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1651
1652	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1653	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1654	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1655	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1656	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1657	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1658
1659	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1660	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1661	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1662	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1663	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1664	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1665	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1666	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1667
1668	/* GC only: */
1669	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1670	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1671	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1672	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1673
1674	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1675	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1676	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1677	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1678	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1679	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1680	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1681	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1682
1683	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1684	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1685	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1686	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1687	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1688	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1689	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1690	# endif
1691
1692	# undef PGM_REG_COUNTER
1693	# undef PGM_REG_PROFILE
1694	#endif
1695
1696	/*
1697	* Note! The layout below matches the member layout exactly!
1698	*/
1699
1700	/*
1701	* Common - stats
1702	*/
1703	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1704	{
1705	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1706
1707	#define PGM_REG_COUNTER(a, b, c) \
1708	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1709	AssertRC(rc);
1710	#define PGM_REG_PROFILE(a, b, c) \
1711	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1712	AssertRC(rc);
1713
1714	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1715
1716	#ifdef VBOX_WITH_STATISTICS
1717
1718	# if 0 /* rarely useful; leave for debugging. */
1719	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1720	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1721	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1722	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1723	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1724	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1725	# endif
1726	/* R0 only: */
1727	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1728	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1729	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1730	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1731	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1732	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1733	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1734	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1735	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1736	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1737	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1738	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1739	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1740	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1741	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1742	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1743	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1744	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1745	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1746	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1747	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1748	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1749	//PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1750	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1751	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1752	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1753	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1754	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1755	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1756	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1757	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1758	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1759	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1760	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1761	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1762	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1763
1764	/* RZ only: */
1765	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1766	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1767	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1768	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1769	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1770	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1771	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1772	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1773	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1774	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1775	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1776	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1777	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1778	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1779	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1780	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1781	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1782	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1783	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1784	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1785	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1786	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1787	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1788	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1789	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1790	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1791	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1792	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1793	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1794	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1795	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1796	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1797	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1798	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1799	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1800	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1801	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1802	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1803	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1804	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1805	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1806	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1807	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1808	#if 0 /* rarely useful; leave for debugging. */
1809	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1810	STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1811	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1812	#endif
1813	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1814	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1815	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1816	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1817	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1818
1819	/* HC only: */
1820
1821	/* RZ & R3: */
1822	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1823	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1824	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1825	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1826	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1827	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1828	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1829	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1830	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1831	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1832	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1833	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1834	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1835	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1836	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1837	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1838	PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1839	PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1840	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1841	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1842	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1843	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1844	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1845	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1846	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1847	PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1848	PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1849	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1850	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1851	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1852	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1853	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1854	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1855	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1856	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1857	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1858	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1859	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1860	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1861	PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1862	PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1863	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1864	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1865	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1866	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1867	PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1868
1869	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1870	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1871	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1872	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1873	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1874	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1875	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1876	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1877	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1878	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1879	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1880	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1881	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1882	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1883	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1884	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1885	PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1886	PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1887	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1888	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1889	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1890	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1891	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1892	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1893	PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1894	PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1895	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1896	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1897	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1898	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1899	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1900	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1901	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1902	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1903	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1904	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1905	PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1906	PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1907	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1908	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1909	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1910	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1911	PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1912	#endif /* VBOX_WITH_STATISTICS */
1913
1914	#undef PGM_REG_PROFILE
1915	#undef PGM_REG_COUNTER
1916
1917	}
1918	}
1919
1920
1921	/**
1922	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1923	*
1924	* The dynamic mapping area will also be allocated and initialized at this
1925	* time. We could allocate it during PGMR3Init of course, but the mapping
1926	* wouldn't be allocated at that time preventing us from setting up the
1927	* page table entries with the dummy page.
1928	*
1929	* @returns VBox status code.
1930	* @param pVM VM handle.
1931	*/
1932	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1933	{
1934	RTGCPTR GCPtr;
1935	int rc;
1936
1937	/*
1938	* Reserve space for the dynamic mappings.
1939	*/
1940	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1941	if (RT_SUCCESS(rc))
1942	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1943
1944	if ( RT_SUCCESS(rc)
1945	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1946	{
1947	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1948	if (RT_SUCCESS(rc))
1949	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1950	}
1951	if (RT_SUCCESS(rc))
1952	{
1953	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1954	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1955	}
1956	return rc;
1957	}
1958
1959
1960	/**
1961	* Ring-3 init finalizing.
1962	*
1963	* @returns VBox status code.
1964	* @param pVM The VM handle.
1965	*/
1966	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1967	{
1968	int rc;
1969
1970	/*
1971	* Reserve space for the dynamic mappings.
1972	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1973	*/
1974	/* get the pointer to the page table entries. */
1975	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1976	AssertRelease(pMapping);
1977	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1978	const unsigned iPT = off >> X86_PD_SHIFT;
1979	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1980	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1981	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1982
1983	/* init cache */
1984	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1985	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1986	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1987
1988	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1989	{
1990	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1991	AssertRCReturn(rc, rc);
1992	}
1993
1994	/*
1995	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1996	* Intel only goes up to 36 bits, so we stick to 36 as well.
1997	*/
1998	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1999	uint32_t u32Dummy, u32Features;
2000	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2001
2002	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2003	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
2004	else
2005	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2006
2007	/*
2008	* Allocate memory if we're supposed to do that.
2009	*/
2010	if (pVM->pgm.s.fRamPreAlloc)
2011	rc = pgmR3PhysRamPreAllocate(pVM);
2012
2013	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2014	return rc;
2015	}
2016
2017
2018	/**
2019	* Applies relocations to data and code managed by this component.
2020	*
2021	* This function will be called at init and whenever the VMM need to relocate it
2022	* self inside the GC.
2023	*
2024	* @param pVM The VM.
2025	* @param offDelta Relocation delta relative to old location.
2026	*/
2027	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2028	{
2029	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2030
2031	/*
2032	* Paging stuff.
2033	*/
2034	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2035
2036	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2037
2038	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2039	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2040	{
2041	PVMCPU pVCpu = &pVM->aCpus[i];
2042
2043	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2044
2045	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2046	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2047	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2048	}
2049
2050	/*
2051	* Trees.
2052	*/
2053	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2054
2055	/*
2056	* Ram ranges.
2057	*/
2058	if (pVM->pgm.s.pRamRangesR3)
2059	{
2060	/* Update the pSelfRC pointers and relink them. */
2061	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2062	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2063	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2064	pgmR3PhysRelinkRamRanges(pVM);
2065	}
2066
2067	/*
2068	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2069	* be mapped and thus not included in the above exercise.
2070	*/
2071	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2072	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2073	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2074
2075	/*
2076	* Update the two page directories with all page table mappings.
2077	* (One or more of them have changed, that's why we're here.)
2078	*/
2079	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2080	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2081	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2082
2083	/* Relocate GC addresses of Page Tables. */
2084	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2085	{
2086	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2087	{
2088	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2089	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2090	}
2091	}
2092
2093	/*
2094	* Dynamic page mapping area.
2095	*/
2096	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2097	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2098	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2099
2100	/*
2101	* The Zero page.
2102	*/
2103	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2104	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2105	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2106	#else
2107	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2108	#endif
2109
2110	/*
2111	* Physical and virtual handlers.
2112	*/
2113	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2114	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2115	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2116
2117	/*
2118	* The page pool.
2119	*/
2120	pgmR3PoolRelocate(pVM);
2121	}
2122
2123
2124	/**
2125	* Callback function for relocating a physical access handler.
2126	*
2127	* @returns 0 (continue enum)
2128	* @param pNode Pointer to a PGMPHYSHANDLER node.
2129	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2130	* not certain the delta will fit in a void pointer for all possible configs.
2131	*/
2132	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2133	{
2134	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2135	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2136	if (pHandler->pfnHandlerRC)
2137	pHandler->pfnHandlerRC += offDelta;
2138	if (pHandler->pvUserRC >= 0x10000)
2139	pHandler->pvUserRC += offDelta;
2140	return 0;
2141	}
2142
2143
2144	/**
2145	* Callback function for relocating a virtual access handler.
2146	*
2147	* @returns 0 (continue enum)
2148	* @param pNode Pointer to a PGMVIRTHANDLER node.
2149	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2150	* not certain the delta will fit in a void pointer for all possible configs.
2151	*/
2152	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2153	{
2154	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2155	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2156	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2157	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2158	Assert(pHandler->pfnHandlerRC);
2159	pHandler->pfnHandlerRC += offDelta;
2160	return 0;
2161	}
2162
2163
2164	/**
2165	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2166	*
2167	* @returns 0 (continue enum)
2168	* @param pNode Pointer to a PGMVIRTHANDLER node.
2169	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2170	* not certain the delta will fit in a void pointer for all possible configs.
2171	*/
2172	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2173	{
2174	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2175	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2176	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2177	Assert(pHandler->pfnHandlerRC);
2178	pHandler->pfnHandlerRC += offDelta;
2179	return 0;
2180	}
2181
2182
2183	/**
2184	* Resets a virtual CPU when unplugged.
2185	*
2186	* @param pVM The VM handle.
2187	* @param pVCpu The virtual CPU handle.
2188	*/
2189	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2190	{
2191	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2192	AssertRC(rc);
2193
2194	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2195	AssertRC(rc);
2196
2197	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2198
2199	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2200
2201	/*
2202	* Re-init other members.
2203	*/
2204	pVCpu->pgm.s.fA20Enabled = true;
2205
2206	/*
2207	* Clear the FFs PGM owns.
2208	*/
2209	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2210	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2211	}
2212
2213
2214	/**
2215	* The VM is being reset.
2216	*
2217	* For the PGM component this means that any PD write monitors
2218	* needs to be removed.
2219	*
2220	* @param pVM VM handle.
2221	*/
2222	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2223	{
2224	int rc;
2225
2226	LogFlow(("PGMR3Reset:\n"));
2227	VM_ASSERT_EMT(pVM);
2228
2229	pgmLock(pVM);
2230
2231	/*
2232	* Unfix any fixed mappings and disable CR3 monitoring.
2233	*/
2234	pVM->pgm.s.fMappingsFixed = false;
2235	pVM->pgm.s.fMappingsFixedRestored = false;
2236	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2237	pVM->pgm.s.cbMappingFixed = 0;
2238
2239	/*
2240	* Exit the guest paging mode before the pgm pool gets reset.
2241	* Important to clean up the amd64 case.
2242	*/
2243	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2244	{
2245	PVMCPU pVCpu = &pVM->aCpus[i];
2246	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2247	AssertRC(rc);
2248	}
2249
2250	#ifdef DEBUG
2251	DBGFR3InfoLog(pVM, "mappings", NULL);
2252	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2253	#endif
2254
2255	/*
2256	* Switch mode back to real mode. (before resetting the pgm pool!)
2257	*/
2258	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2259	{
2260	PVMCPU pVCpu = &pVM->aCpus[i];
2261
2262	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2263	AssertRC(rc);
2264
2265	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2266	}
2267
2268	/*
2269	* Reset the shadow page pool.
2270	*/
2271	pgmR3PoolReset(pVM);
2272
2273	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2274	{
2275	PVMCPU pVCpu = &pVM->aCpus[i];
2276
2277	/*
2278	* Re-init other members.
2279	*/
2280	pVCpu->pgm.s.fA20Enabled = true;
2281
2282	/*
2283	* Clear the FFs PGM owns.
2284	*/
2285	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2286	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2287	}
2288
2289	/*
2290	* Reset (zero) RAM pages.
2291	*/
2292	rc = pgmR3PhysRamReset(pVM);
2293	if (RT_SUCCESS(rc))
2294	{
2295	/*
2296	* Reset (zero) shadow ROM pages.
2297	*/
2298	rc = pgmR3PhysRomReset(pVM);
2299	}
2300
2301	pgmUnlock(pVM);
2302	AssertReleaseRC(rc);
2303	}
2304
2305
2306	#ifdef VBOX_STRICT
2307	/**
2308	* VM state change callback for clearing fNoMorePhysWrites after
2309	* a snapshot has been created.
2310	*/
2311	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2312	{
2313	if ( enmState == VMSTATE_RUNNING
2314	\|\| enmState == VMSTATE_RESUMING)
2315	pVM->pgm.s.fNoMorePhysWrites = false;
2316	}
2317	#endif
2318
2319
2320	/**
2321	* Terminates the PGM.
2322	*
2323	* @returns VBox status code.
2324	* @param pVM Pointer to VM structure.
2325	*/
2326	VMMR3DECL(int) PGMR3Term(PVM pVM)
2327	{
2328	PGMDeregisterStringFormatTypes();
2329	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2330	}
2331
2332
2333	/**
2334	* Terminates the per-VCPU PGM.
2335	*
2336	* Termination means cleaning up and freeing all resources,
2337	* the VM it self is at this point powered off or suspended.
2338	*
2339	* @returns VBox status code.
2340	* @param pVM The VM to operate on.
2341	*/
2342	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2343	{
2344	return 0;
2345	}
2346
2347
2348	/**
2349	* Show paging mode.
2350	*
2351	* @param pVM VM Handle.
2352	* @param pHlp The info helpers.
2353	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2354	*/
2355	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2356	{
2357	/* digest argument. */
2358	bool fGuest, fShadow, fHost;
2359	if (pszArgs)
2360	pszArgs = RTStrStripL(pszArgs);
2361	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2362	fShadow = fHost = fGuest = true;
2363	else
2364	{
2365	fShadow = fHost = fGuest = false;
2366	if (strstr(pszArgs, "guest"))
2367	fGuest = true;
2368	if (strstr(pszArgs, "shadow"))
2369	fShadow = true;
2370	if (strstr(pszArgs, "host"))
2371	fHost = true;
2372	}
2373
2374	/** @todo SMP support! */
2375	/* print info. */
2376	if (fGuest)
2377	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2378	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2379	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2380	if (fShadow)
2381	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2382	if (fHost)
2383	{
2384	const char *psz;
2385	switch (pVM->pgm.s.enmHostMode)
2386	{
2387	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2388	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2389	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2390	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2391	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2392	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2393	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2394	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2395	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2396	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2397	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2398	default: psz = "unknown"; break;
2399	}
2400	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2401	}
2402	}
2403
2404
2405	/**
2406	* Dump registered MMIO ranges to the log.
2407	*
2408	* @param pVM VM Handle.
2409	* @param pHlp The info helpers.
2410	* @param pszArgs Arguments, ignored.
2411	*/
2412	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2413	{
2414	NOREF(pszArgs);
2415	pHlp->pfnPrintf(pHlp,
2416	"RAM ranges (pVM=%p)\n"
2417	"%.s %.s\n",
2418	pVM,
2419	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2420	sizeof(RTHCPTR) * 2, "pvHC ");
2421
2422	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2423	pHlp->pfnPrintf(pHlp,
2424	"%RGp-%RGp %RHv %s\n",
2425	pCur->GCPhys,
2426	pCur->GCPhysLast,
2427	pCur->pvR3,
2428	pCur->pszDesc);
2429	}
2430
2431	/**
2432	* Dump the page directory to the log.
2433	*
2434	* @param pVM VM Handle.
2435	* @param pHlp The info helpers.
2436	* @param pszArgs Arguments, ignored.
2437	*/
2438	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2439	{
2440	/** @todo SMP support!! */
2441	PVMCPU pVCpu = &pVM->aCpus[0];
2442
2443	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2444	/* Big pages supported? */
2445	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2446
2447	/* Global pages supported? */
2448	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2449
2450	NOREF(pszArgs);
2451
2452	/*
2453	* Get page directory addresses.
2454	*/
2455	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2456	Assert(pPDSrc);
2457	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2458
2459	/*
2460	* Iterate the page directory.
2461	*/
2462	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2463	{
2464	X86PDE PdeSrc = pPDSrc->a[iPD];
2465	if (PdeSrc.n.u1Present)
2466	{
2467	if (PdeSrc.b.u1Size && fPSE)
2468	pHlp->pfnPrintf(pHlp,
2469	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2470	iPD,
2471	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2472	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2473	else
2474	pHlp->pfnPrintf(pHlp,
2475	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2476	iPD,
2477	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2478	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2479	}
2480	}
2481	}
2482
2483
2484	/**
2485	* Service a VMMCALLRING3_PGM_LOCK call.
2486	*
2487	* @returns VBox status code.
2488	* @param pVM The VM handle.
2489	*/
2490	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2491	{
2492	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2493	AssertRC(rc);
2494	return rc;
2495	}
2496
2497
2498	/**
2499	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2500	*
2501	* @returns PGM_TYPE_*.
2502	* @param pgmMode The mode value to convert.
2503	*/
2504	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2505	{
2506	switch (pgmMode)
2507	{
2508	case PGMMODE_REAL: return PGM_TYPE_REAL;
2509	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2510	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2511	case PGMMODE_PAE:
2512	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2513	case PGMMODE_AMD64:
2514	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2515	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2516	case PGMMODE_EPT: return PGM_TYPE_EPT;
2517	default:
2518	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2519	}
2520	}
2521
2522
2523	/**
2524	* Gets the index into the paging mode data array of a SHW+GST mode.
2525	*
2526	* @returns PGM::paPagingData index.
2527	* @param uShwType The shadow paging mode type.
2528	* @param uGstType The guest paging mode type.
2529	*/
2530	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2531	{
2532	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2533	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2534	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2535	+ (uGstType - PGM_TYPE_REAL);
2536	}
2537
2538
2539	/**
2540	* Gets the index into the paging mode data array of a SHW+GST mode.
2541	*
2542	* @returns PGM::paPagingData index.
2543	* @param enmShw The shadow paging mode.
2544	* @param enmGst The guest paging mode.
2545	*/
2546	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2547	{
2548	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2549	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2550	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2551	}
2552
2553
2554	/**
2555	* Calculates the max data index.
2556	* @returns The number of entries in the paging data array.
2557	*/
2558	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2559	{
2560	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2561	}
2562
2563
2564	/**
2565	* Initializes the paging mode data kept in PGM::paModeData.
2566	*
2567	* @param pVM The VM handle.
2568	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2569	* This is used early in the init process to avoid trouble with PDM
2570	* not being initialized yet.
2571	*/
2572	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2573	{
2574	PPGMMODEDATA pModeData;
2575	int rc;
2576
2577	/*
2578	* Allocate the array on the first call.
2579	*/
2580	if (!pVM->pgm.s.paModeData)
2581	{
2582	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2583	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2584	}
2585
2586	/*
2587	* Initialize the array entries.
2588	*/
2589	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2590	pModeData->uShwType = PGM_TYPE_32BIT;
2591	pModeData->uGstType = PGM_TYPE_REAL;
2592	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2593	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2594	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2595
2596	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2597	pModeData->uShwType = PGM_TYPE_32BIT;
2598	pModeData->uGstType = PGM_TYPE_PROT;
2599	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2600	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2601	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2602
2603	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2604	pModeData->uShwType = PGM_TYPE_32BIT;
2605	pModeData->uGstType = PGM_TYPE_32BIT;
2606	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2607	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2608	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2609
2610	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2611	pModeData->uShwType = PGM_TYPE_PAE;
2612	pModeData->uGstType = PGM_TYPE_REAL;
2613	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2614	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2615	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2616
2617	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2618	pModeData->uShwType = PGM_TYPE_PAE;
2619	pModeData->uGstType = PGM_TYPE_PROT;
2620	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2621	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2622	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2623
2624	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2625	pModeData->uShwType = PGM_TYPE_PAE;
2626	pModeData->uGstType = PGM_TYPE_32BIT;
2627	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2628	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2629	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2630
2631	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2632	pModeData->uShwType = PGM_TYPE_PAE;
2633	pModeData->uGstType = PGM_TYPE_PAE;
2634	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2635	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2636	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2637
2638	#ifdef VBOX_WITH_64_BITS_GUESTS
2639	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2640	pModeData->uShwType = PGM_TYPE_AMD64;
2641	pModeData->uGstType = PGM_TYPE_AMD64;
2642	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2643	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2644	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2645	#endif
2646
2647	/* The nested paging mode. */
2648	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2649	pModeData->uShwType = PGM_TYPE_NESTED;
2650	pModeData->uGstType = PGM_TYPE_REAL;
2651	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2652	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2653
2654	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2655	pModeData->uShwType = PGM_TYPE_NESTED;
2656	pModeData->uGstType = PGM_TYPE_PROT;
2657	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2658	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2659
2660	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2661	pModeData->uShwType = PGM_TYPE_NESTED;
2662	pModeData->uGstType = PGM_TYPE_32BIT;
2663	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2664	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2665
2666	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2667	pModeData->uShwType = PGM_TYPE_NESTED;
2668	pModeData->uGstType = PGM_TYPE_PAE;
2669	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2671
2672	#ifdef VBOX_WITH_64_BITS_GUESTS
2673	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2674	pModeData->uShwType = PGM_TYPE_NESTED;
2675	pModeData->uGstType = PGM_TYPE_AMD64;
2676	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2677	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678	#endif
2679
2680	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2681	switch (pVM->pgm.s.enmHostMode)
2682	{
2683	#if HC_ARCH_BITS == 32
2684	case SUPPAGINGMODE_32_BIT:
2685	case SUPPAGINGMODE_32_BIT_GLOBAL:
2686	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2687	{
2688	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2689	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2690	}
2691	# ifdef VBOX_WITH_64_BITS_GUESTS
2692	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2693	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2694	# endif
2695	break;
2696
2697	case SUPPAGINGMODE_PAE:
2698	case SUPPAGINGMODE_PAE_NX:
2699	case SUPPAGINGMODE_PAE_GLOBAL:
2700	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2701	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2702	{
2703	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2704	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705	}
2706	# ifdef VBOX_WITH_64_BITS_GUESTS
2707	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2708	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709	# endif
2710	break;
2711	#endif /* HC_ARCH_BITS == 32 */
2712
2713	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2714	case SUPPAGINGMODE_AMD64:
2715	case SUPPAGINGMODE_AMD64_GLOBAL:
2716	case SUPPAGINGMODE_AMD64_NX:
2717	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2718	# ifdef VBOX_WITH_64_BITS_GUESTS
2719	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2720	# else
2721	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2722	# endif
2723	{
2724	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2725	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726	}
2727	break;
2728	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2729
2730	default:
2731	AssertFailed();
2732	break;
2733	}
2734
2735	/* Extended paging (EPT) / Intel VT-x */
2736	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2737	pModeData->uShwType = PGM_TYPE_EPT;
2738	pModeData->uGstType = PGM_TYPE_REAL;
2739	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742
2743	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2744	pModeData->uShwType = PGM_TYPE_EPT;
2745	pModeData->uGstType = PGM_TYPE_PROT;
2746	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749
2750	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2751	pModeData->uShwType = PGM_TYPE_EPT;
2752	pModeData->uGstType = PGM_TYPE_32BIT;
2753	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756
2757	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2758	pModeData->uShwType = PGM_TYPE_EPT;
2759	pModeData->uGstType = PGM_TYPE_PAE;
2760	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763
2764	#ifdef VBOX_WITH_64_BITS_GUESTS
2765	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2766	pModeData->uShwType = PGM_TYPE_EPT;
2767	pModeData->uGstType = PGM_TYPE_AMD64;
2768	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	#endif
2772	return VINF_SUCCESS;
2773	}
2774
2775
2776	/**
2777	* Switch to different (or relocated in the relocate case) mode data.
2778	*
2779	* @param pVM The VM handle.
2780	* @param pVCpu The VMCPU to operate on.
2781	* @param enmShw The the shadow paging mode.
2782	* @param enmGst The the guest paging mode.
2783	*/
2784	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2785	{
2786	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2787
2788	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2789	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2790
2791	/* shadow */
2792	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2793	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2794	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2795	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2796	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2797
2798	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2799	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2800
2801	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2802	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2803
2804
2805	/* guest */
2806	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2807	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2808	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2809	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2810	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2811	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2812	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2813	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2814	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2815	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2816	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2817	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2818
2819	/* both */
2820	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2821	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2822	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2823	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2824	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2825	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2826	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2827	#ifdef VBOX_STRICT
2828	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2829	#endif
2830	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2831	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2832
2833	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2834	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2835	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2836	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2837	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2838	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2839	#ifdef VBOX_STRICT
2840	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2841	#endif
2842	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2843	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2844
2845	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2846	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2847	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2848	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2849	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2850	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2851	#ifdef VBOX_STRICT
2852	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2853	#endif
2854	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2855	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2856	}
2857
2858
2859	/**
2860	* Calculates the shadow paging mode.
2861	*
2862	* @returns The shadow paging mode.
2863	* @param pVM VM handle.
2864	* @param enmGuestMode The guest mode.
2865	* @param enmHostMode The host mode.
2866	* @param enmShadowMode The current shadow mode.
2867	* @param penmSwitcher Where to store the switcher to use.
2868	* VMMSWITCHER_INVALID means no change.
2869	*/
2870	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2871	{
2872	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2873	switch (enmGuestMode)
2874	{
2875	/*
2876	* When switching to real or protected mode we don't change
2877	* anything since it's likely that we'll switch back pretty soon.
2878	*
2879	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2880	* and is supposed to determine which shadow paging and switcher to
2881	* use during init.
2882	*/
2883	case PGMMODE_REAL:
2884	case PGMMODE_PROTECTED:
2885	if ( enmShadowMode != PGMMODE_INVALID
2886	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2887	break; /* (no change) */
2888
2889	switch (enmHostMode)
2890	{
2891	case SUPPAGINGMODE_32_BIT:
2892	case SUPPAGINGMODE_32_BIT_GLOBAL:
2893	enmShadowMode = PGMMODE_32_BIT;
2894	enmSwitcher = VMMSWITCHER_32_TO_32;
2895	break;
2896
2897	case SUPPAGINGMODE_PAE:
2898	case SUPPAGINGMODE_PAE_NX:
2899	case SUPPAGINGMODE_PAE_GLOBAL:
2900	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2901	enmShadowMode = PGMMODE_PAE;
2902	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2903	#ifdef DEBUG_bird
2904	if (RTEnvExist("VBOX_32BIT"))
2905	{
2906	enmShadowMode = PGMMODE_32_BIT;
2907	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2908	}
2909	#endif
2910	break;
2911
2912	case SUPPAGINGMODE_AMD64:
2913	case SUPPAGINGMODE_AMD64_GLOBAL:
2914	case SUPPAGINGMODE_AMD64_NX:
2915	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2916	enmShadowMode = PGMMODE_PAE;
2917	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2918	#ifdef DEBUG_bird
2919	if (RTEnvExist("VBOX_32BIT"))
2920	{
2921	enmShadowMode = PGMMODE_32_BIT;
2922	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2923	}
2924	#endif
2925	break;
2926
2927	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2928	}
2929	break;
2930
2931	case PGMMODE_32_BIT:
2932	switch (enmHostMode)
2933	{
2934	case SUPPAGINGMODE_32_BIT:
2935	case SUPPAGINGMODE_32_BIT_GLOBAL:
2936	enmShadowMode = PGMMODE_32_BIT;
2937	enmSwitcher = VMMSWITCHER_32_TO_32;
2938	break;
2939
2940	case SUPPAGINGMODE_PAE:
2941	case SUPPAGINGMODE_PAE_NX:
2942	case SUPPAGINGMODE_PAE_GLOBAL:
2943	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2944	enmShadowMode = PGMMODE_PAE;
2945	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2946	#ifdef DEBUG_bird
2947	if (RTEnvExist("VBOX_32BIT"))
2948	{
2949	enmShadowMode = PGMMODE_32_BIT;
2950	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2951	}
2952	#endif
2953	break;
2954
2955	case SUPPAGINGMODE_AMD64:
2956	case SUPPAGINGMODE_AMD64_GLOBAL:
2957	case SUPPAGINGMODE_AMD64_NX:
2958	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2959	enmShadowMode = PGMMODE_PAE;
2960	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2961	#ifdef DEBUG_bird
2962	if (RTEnvExist("VBOX_32BIT"))
2963	{
2964	enmShadowMode = PGMMODE_32_BIT;
2965	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2966	}
2967	#endif
2968	break;
2969
2970	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2971	}
2972	break;
2973
2974	case PGMMODE_PAE:
2975	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2976	switch (enmHostMode)
2977	{
2978	case SUPPAGINGMODE_32_BIT:
2979	case SUPPAGINGMODE_32_BIT_GLOBAL:
2980	enmShadowMode = PGMMODE_PAE;
2981	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2982	break;
2983
2984	case SUPPAGINGMODE_PAE:
2985	case SUPPAGINGMODE_PAE_NX:
2986	case SUPPAGINGMODE_PAE_GLOBAL:
2987	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2988	enmShadowMode = PGMMODE_PAE;
2989	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2990	break;
2991
2992	case SUPPAGINGMODE_AMD64:
2993	case SUPPAGINGMODE_AMD64_GLOBAL:
2994	case SUPPAGINGMODE_AMD64_NX:
2995	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2996	enmShadowMode = PGMMODE_PAE;
2997	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2998	break;
2999
3000	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3001	}
3002	break;
3003
3004	case PGMMODE_AMD64:
3005	case PGMMODE_AMD64_NX:
3006	switch (enmHostMode)
3007	{
3008	case SUPPAGINGMODE_32_BIT:
3009	case SUPPAGINGMODE_32_BIT_GLOBAL:
3010	enmShadowMode = PGMMODE_AMD64;
3011	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3012	break;
3013
3014	case SUPPAGINGMODE_PAE:
3015	case SUPPAGINGMODE_PAE_NX:
3016	case SUPPAGINGMODE_PAE_GLOBAL:
3017	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3018	enmShadowMode = PGMMODE_AMD64;
3019	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3020	break;
3021
3022	case SUPPAGINGMODE_AMD64:
3023	case SUPPAGINGMODE_AMD64_GLOBAL:
3024	case SUPPAGINGMODE_AMD64_NX:
3025	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3026	enmShadowMode = PGMMODE_AMD64;
3027	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3028	break;
3029
3030	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3031	}
3032	break;
3033
3034
3035	default:
3036	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3037	*penmSwitcher = VMMSWITCHER_INVALID;
3038	return PGMMODE_INVALID;
3039	}
3040	/* Override the shadow mode is nested paging is active. */
3041	if (HWACCMIsNestedPagingActive(pVM))
3042	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3043
3044	*penmSwitcher = enmSwitcher;
3045	return enmShadowMode;
3046	}
3047
3048
3049	/**
3050	* Performs the actual mode change.
3051	* This is called by PGMChangeMode and pgmR3InitPaging().
3052	*
3053	* @returns VBox status code. May suspend or power off the VM on error, but this
3054	* will trigger using FFs and not status codes.
3055	*
3056	* @param pVM VM handle.
3057	* @param pVCpu The VMCPU to operate on.
3058	* @param enmGuestMode The new guest mode. This is assumed to be different from
3059	* the current mode.
3060	*/
3061	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3062	{
3063	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3064	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3065
3066	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3067	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3068
3069	/*
3070	* Calc the shadow mode and switcher.
3071	*/
3072	VMMSWITCHER enmSwitcher;
3073	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3074
3075	#ifdef VBOX_WITH_RAW_MODE
3076	if (enmSwitcher != VMMSWITCHER_INVALID)
3077	{
3078	/*
3079	* Select new switcher.
3080	*/
3081	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3082	if (RT_FAILURE(rc))
3083	{
3084	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3085	return rc;
3086	}
3087	}
3088	#endif
3089
3090	/*
3091	* Exit old mode(s).
3092	*/
3093	#if HC_ARCH_BITS == 32
3094	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3095	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3096	&& enmShadowMode == PGMMODE_NESTED);
3097	#else
3098	const bool fForceShwEnterExit = false;
3099	#endif
3100	/* shadow */
3101	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3102	\|\| fForceShwEnterExit)
3103	{
3104	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3105	if (PGM_SHW_PFN(Exit, pVCpu))
3106	{
3107	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3108	if (RT_FAILURE(rc))
3109	{
3110	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3111	return rc;
3112	}
3113	}
3114
3115	}
3116	else
3117	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3118
3119	/* guest */
3120	if (PGM_GST_PFN(Exit, pVCpu))
3121	{
3122	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3123	if (RT_FAILURE(rc))
3124	{
3125	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3126	return rc;
3127	}
3128	}
3129
3130	/*
3131	* Load new paging mode data.
3132	*/
3133	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3134
3135	/*
3136	* Enter new shadow mode (if changed).
3137	*/
3138	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3139	\|\| fForceShwEnterExit)
3140	{
3141	int rc;
3142	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3143	switch (enmShadowMode)
3144	{
3145	case PGMMODE_32_BIT:
3146	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3147	break;
3148	case PGMMODE_PAE:
3149	case PGMMODE_PAE_NX:
3150	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3151	break;
3152	case PGMMODE_AMD64:
3153	case PGMMODE_AMD64_NX:
3154	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3155	break;
3156	case PGMMODE_NESTED:
3157	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3158	break;
3159	case PGMMODE_EPT:
3160	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3161	break;
3162	case PGMMODE_REAL:
3163	case PGMMODE_PROTECTED:
3164	default:
3165	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3166	return VERR_INTERNAL_ERROR;
3167	}
3168	if (RT_FAILURE(rc))
3169	{
3170	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3171	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3172	return rc;
3173	}
3174	}
3175
3176	/*
3177	* Always flag the necessary updates
3178	*/
3179	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3180
3181	/*
3182	* Enter the new guest and shadow+guest modes.
3183	*/
3184	int rc = -1;
3185	int rc2 = -1;
3186	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3187	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3188	switch (enmGuestMode)
3189	{
3190	case PGMMODE_REAL:
3191	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3192	switch (pVCpu->pgm.s.enmShadowMode)
3193	{
3194	case PGMMODE_32_BIT:
3195	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3196	break;
3197	case PGMMODE_PAE:
3198	case PGMMODE_PAE_NX:
3199	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3200	break;
3201	case PGMMODE_NESTED:
3202	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3203	break;
3204	case PGMMODE_EPT:
3205	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3206	break;
3207	case PGMMODE_AMD64:
3208	case PGMMODE_AMD64_NX:
3209	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3210	default: AssertFailed(); break;
3211	}
3212	break;
3213
3214	case PGMMODE_PROTECTED:
3215	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3216	switch (pVCpu->pgm.s.enmShadowMode)
3217	{
3218	case PGMMODE_32_BIT:
3219	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3220	break;
3221	case PGMMODE_PAE:
3222	case PGMMODE_PAE_NX:
3223	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3224	break;
3225	case PGMMODE_NESTED:
3226	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3227	break;
3228	case PGMMODE_EPT:
3229	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3230	break;
3231	case PGMMODE_AMD64:
3232	case PGMMODE_AMD64_NX:
3233	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3234	default: AssertFailed(); break;
3235	}
3236	break;
3237
3238	case PGMMODE_32_BIT:
3239	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3240	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3241	switch (pVCpu->pgm.s.enmShadowMode)
3242	{
3243	case PGMMODE_32_BIT:
3244	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3245	break;
3246	case PGMMODE_PAE:
3247	case PGMMODE_PAE_NX:
3248	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3249	break;
3250	case PGMMODE_NESTED:
3251	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3252	break;
3253	case PGMMODE_EPT:
3254	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3255	break;
3256	case PGMMODE_AMD64:
3257	case PGMMODE_AMD64_NX:
3258	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3259	default: AssertFailed(); break;
3260	}
3261	break;
3262
3263	case PGMMODE_PAE_NX:
3264	case PGMMODE_PAE:
3265	{
3266	uint32_t u32Dummy, u32Features;
3267
3268	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3269	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3270	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3271	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3272
3273	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3274	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3275	switch (pVCpu->pgm.s.enmShadowMode)
3276	{
3277	case PGMMODE_PAE:
3278	case PGMMODE_PAE_NX:
3279	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3280	break;
3281	case PGMMODE_NESTED:
3282	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3283	break;
3284	case PGMMODE_EPT:
3285	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3286	break;
3287	case PGMMODE_32_BIT:
3288	case PGMMODE_AMD64:
3289	case PGMMODE_AMD64_NX:
3290	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3291	default: AssertFailed(); break;
3292	}
3293	break;
3294	}
3295
3296	#ifdef VBOX_WITH_64_BITS_GUESTS
3297	case PGMMODE_AMD64_NX:
3298	case PGMMODE_AMD64:
3299	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3300	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3301	switch (pVCpu->pgm.s.enmShadowMode)
3302	{
3303	case PGMMODE_AMD64:
3304	case PGMMODE_AMD64_NX:
3305	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3306	break;
3307	case PGMMODE_NESTED:
3308	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3309	break;
3310	case PGMMODE_EPT:
3311	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3312	break;
3313	case PGMMODE_32_BIT:
3314	case PGMMODE_PAE:
3315	case PGMMODE_PAE_NX:
3316	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3317	default: AssertFailed(); break;
3318	}
3319	break;
3320	#endif
3321
3322	default:
3323	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3324	rc = VERR_NOT_IMPLEMENTED;
3325	break;
3326	}
3327
3328	/* status codes. */
3329	AssertRC(rc);
3330	AssertRC(rc2);
3331	if (RT_SUCCESS(rc))
3332	{
3333	rc = rc2;
3334	if (RT_SUCCESS(rc)) /* no informational status codes. */
3335	rc = VINF_SUCCESS;
3336	}
3337
3338	/* Notify HWACCM as well. */
3339	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3340	return rc;
3341	}
3342
3343	/**
3344	* Release the pgm lock if owned by the current VCPU
3345	*
3346	* @param pVM The VM to operate on.
3347	*/
3348	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
3349	{
3350	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
3351	PDMCritSectLeave(&pVM->pgm.s.CritSect);
3352	}
3353
3354	/**
3355	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3356	*
3357	* @returns VBox status code, fully asserted.
3358	* @param pVM The VM handle.
3359	* @param pVCpu The VMCPU to operate on.
3360	*/
3361	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3362	{
3363	/* Unmap the old CR3 value before flushing everything. */
3364	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3365	AssertRC(rc);
3366
3367	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3368	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3369	AssertRC(rc);
3370	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3371	return rc;
3372	}
3373
3374
3375	/**
3376	* Called by pgmPoolFlushAllInt after flushing the pool.
3377	*
3378	* @returns VBox status code, fully asserted.
3379	* @param pVM The VM handle.
3380	* @param pVCpu The VMCPU to operate on.
3381	*/
3382	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3383	{
3384	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3385	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3386	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3387	AssertRCReturn(rc, rc);
3388	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3389
3390	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3391	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3392	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3393	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3394	return rc;
3395	}
3396
3397
3398	/**
3399	* Dumps a PAE shadow page table.
3400	*
3401	* @returns VBox status code (VINF_SUCCESS).
3402	* @param pVM The VM handle.
3403	* @param pPT Pointer to the page table.
3404	* @param u64Address The virtual address of the page table starts.
3405	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3406	* @param cMaxDepth The maxium depth.
3407	* @param pHlp Pointer to the output functions.
3408	*/
3409	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3410	{
3411	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3412	{
3413	X86PTEPAE Pte = pPT->a[i];
3414	if (Pte.n.u1Present)
3415	{
3416	pHlp->pfnPrintf(pHlp,
3417	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3418	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3419	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3420	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3421	Pte.n.u1Write ? 'W' : 'R',
3422	Pte.n.u1User ? 'U' : 'S',
3423	Pte.n.u1Accessed ? 'A' : '-',
3424	Pte.n.u1Dirty ? 'D' : '-',
3425	Pte.n.u1Global ? 'G' : '-',
3426	Pte.n.u1WriteThru ? "WT" : "--",
3427	Pte.n.u1CacheDisable? "CD" : "--",
3428	Pte.n.u1PAT ? "AT" : "--",
3429	Pte.n.u1NoExecute ? "NX" : "--",
3430	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3431	Pte.u & RT_BIT(10) ? '1' : '0',
3432	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3433	Pte.u & X86_PTE_PAE_PG_MASK);
3434	}
3435	}
3436	return VINF_SUCCESS;
3437	}
3438
3439
3440	/**
3441	* Dumps a PAE shadow page directory table.
3442	*
3443	* @returns VBox status code (VINF_SUCCESS).
3444	* @param pVM The VM handle.
3445	* @param HCPhys The physical address of the page directory table.
3446	* @param u64Address The virtual address of the page table starts.
3447	* @param cr4 The CR4, PSE is currently used.
3448	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3449	* @param cMaxDepth The maxium depth.
3450	* @param pHlp Pointer to the output functions.
3451	*/
3452	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3453	{
3454	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3455	if (!pPD)
3456	{
3457	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3458	fLongMode ? 16 : 8, u64Address, HCPhys);
3459	return VERR_INVALID_PARAMETER;
3460	}
3461	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3462
3463	int rc = VINF_SUCCESS;
3464	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3465	{
3466	X86PDEPAE Pde = pPD->a[i];
3467	if (Pde.n.u1Present)
3468	{
3469	if (fBigPagesSupported && Pde.b.u1Size)
3470	pHlp->pfnPrintf(pHlp,
3471	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3472	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3473	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3474	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3475	Pde.b.u1Write ? 'W' : 'R',
3476	Pde.b.u1User ? 'U' : 'S',
3477	Pde.b.u1Accessed ? 'A' : '-',
3478	Pde.b.u1Dirty ? 'D' : '-',
3479	Pde.b.u1Global ? 'G' : '-',
3480	Pde.b.u1WriteThru ? "WT" : "--",
3481	Pde.b.u1CacheDisable? "CD" : "--",
3482	Pde.b.u1PAT ? "AT" : "--",
3483	Pde.b.u1NoExecute ? "NX" : "--",
3484	Pde.u & RT_BIT_64(9) ? '1' : '0',
3485	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3486	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3487	Pde.u & X86_PDE_PAE_PG_MASK);
3488	else
3489	{
3490	pHlp->pfnPrintf(pHlp,
3491	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3492	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3493	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3494	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3495	Pde.n.u1Write ? 'W' : 'R',
3496	Pde.n.u1User ? 'U' : 'S',
3497	Pde.n.u1Accessed ? 'A' : '-',
3498	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3499	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3500	Pde.n.u1WriteThru ? "WT" : "--",
3501	Pde.n.u1CacheDisable? "CD" : "--",
3502	Pde.n.u1NoExecute ? "NX" : "--",
3503	Pde.u & RT_BIT_64(9) ? '1' : '0',
3504	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3505	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3506	Pde.u & X86_PDE_PAE_PG_MASK);
3507	if (cMaxDepth >= 1)
3508	{
3509	/** @todo what about using the page pool for mapping PTs? */
3510	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3511	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3512	PX86PTPAE pPT = NULL;
3513	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3514	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3515	else
3516	{
3517	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3518	{
3519	uint64_t off = u64AddressPT - pMap->GCPtr;
3520	if (off < pMap->cb)
3521	{
3522	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3523	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3524	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3525	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3526	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3527	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3528	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3529	}
3530	}
3531	}
3532	int rc2 = VERR_INVALID_PARAMETER;
3533	if (pPT)
3534	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3535	else
3536	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3537	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3538	if (rc2 < rc && RT_SUCCESS(rc))
3539	rc = rc2;
3540	}
3541	}
3542	}
3543	}
3544	return rc;
3545	}
3546
3547
3548	/**
3549	* Dumps a PAE shadow page directory pointer table.
3550	*
3551	* @returns VBox status code (VINF_SUCCESS).
3552	* @param pVM The VM handle.
3553	* @param HCPhys The physical address of the page directory pointer table.
3554	* @param u64Address The virtual address of the page table starts.
3555	* @param cr4 The CR4, PSE is currently used.
3556	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3557	* @param cMaxDepth The maxium depth.
3558	* @param pHlp Pointer to the output functions.
3559	*/
3560	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3561	{
3562	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3563	if (!pPDPT)
3564	{
3565	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3566	fLongMode ? 16 : 8, u64Address, HCPhys);
3567	return VERR_INVALID_PARAMETER;
3568	}
3569
3570	int rc = VINF_SUCCESS;
3571	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3572	for (unsigned i = 0; i < c; i++)
3573	{
3574	X86PDPE Pdpe = pPDPT->a[i];
3575	if (Pdpe.n.u1Present)
3576	{
3577	if (fLongMode)
3578	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3579	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3580	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3581	Pdpe.lm.u1Write ? 'W' : 'R',
3582	Pdpe.lm.u1User ? 'U' : 'S',
3583	Pdpe.lm.u1Accessed ? 'A' : '-',
3584	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3585	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3586	Pdpe.lm.u1WriteThru ? "WT" : "--",
3587	Pdpe.lm.u1CacheDisable? "CD" : "--",
3588	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3589	Pdpe.lm.u1NoExecute ? "NX" : "--",
3590	Pdpe.u & RT_BIT(9) ? '1' : '0',
3591	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3592	Pdpe.u & RT_BIT(11) ? '1' : '0',
3593	Pdpe.u & X86_PDPE_PG_MASK);
3594	else
3595	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3596	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3597	i << X86_PDPT_SHIFT,
3598	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3599	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3600	Pdpe.n.u1WriteThru ? "WT" : "--",
3601	Pdpe.n.u1CacheDisable? "CD" : "--",
3602	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3603	Pdpe.u & RT_BIT(9) ? '1' : '0',
3604	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3605	Pdpe.u & RT_BIT(11) ? '1' : '0',
3606	Pdpe.u & X86_PDPE_PG_MASK);
3607	if (cMaxDepth >= 1)
3608	{
3609	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3610	cr4, fLongMode, cMaxDepth - 1, pHlp);
3611	if (rc2 < rc && RT_SUCCESS(rc))
3612	rc = rc2;
3613	}
3614	}
3615	}
3616	return rc;
3617	}
3618
3619
3620	/**
3621	* Dumps a 32-bit shadow page table.
3622	*
3623	* @returns VBox status code (VINF_SUCCESS).
3624	* @param pVM The VM handle.
3625	* @param HCPhys The physical address of the table.
3626	* @param cr4 The CR4, PSE is currently used.
3627	* @param cMaxDepth The maxium depth.
3628	* @param pHlp Pointer to the output functions.
3629	*/
3630	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3631	{
3632	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3633	if (!pPML4)
3634	{
3635	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3636	return VERR_INVALID_PARAMETER;
3637	}
3638
3639	int rc = VINF_SUCCESS;
3640	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3641	{
3642	X86PML4E Pml4e = pPML4->a[i];
3643	if (Pml4e.n.u1Present)
3644	{
3645	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3646	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3647	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3648	u64Address,
3649	Pml4e.n.u1Write ? 'W' : 'R',
3650	Pml4e.n.u1User ? 'U' : 'S',
3651	Pml4e.n.u1Accessed ? 'A' : '-',
3652	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3653	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3654	Pml4e.n.u1WriteThru ? "WT" : "--",
3655	Pml4e.n.u1CacheDisable? "CD" : "--",
3656	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3657	Pml4e.n.u1NoExecute ? "NX" : "--",
3658	Pml4e.u & RT_BIT(9) ? '1' : '0',
3659	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3660	Pml4e.u & RT_BIT(11) ? '1' : '0',
3661	Pml4e.u & X86_PML4E_PG_MASK);
3662
3663	if (cMaxDepth >= 1)
3664	{
3665	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3666	if (rc2 < rc && RT_SUCCESS(rc))
3667	rc = rc2;
3668	}
3669	}
3670	}
3671	return rc;
3672	}
3673
3674
3675	/**
3676	* Dumps a 32-bit shadow page table.
3677	*
3678	* @returns VBox status code (VINF_SUCCESS).
3679	* @param pVM The VM handle.
3680	* @param pPT Pointer to the page table.
3681	* @param u32Address The virtual address this table starts at.
3682	* @param pHlp Pointer to the output functions.
3683	*/
3684	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3685	{
3686	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3687	{
3688	X86PTE Pte = pPT->a[i];
3689	if (Pte.n.u1Present)
3690	{
3691	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3692	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3693	u32Address + (i << X86_PT_SHIFT),
3694	Pte.n.u1Write ? 'W' : 'R',
3695	Pte.n.u1User ? 'U' : 'S',
3696	Pte.n.u1Accessed ? 'A' : '-',
3697	Pte.n.u1Dirty ? 'D' : '-',
3698	Pte.n.u1Global ? 'G' : '-',
3699	Pte.n.u1WriteThru ? "WT" : "--",
3700	Pte.n.u1CacheDisable? "CD" : "--",
3701	Pte.n.u1PAT ? "AT" : "--",
3702	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3703	Pte.u & RT_BIT(10) ? '1' : '0',
3704	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3705	Pte.u & X86_PDE_PG_MASK);
3706	}
3707	}
3708	return VINF_SUCCESS;
3709	}
3710
3711
3712	/**
3713	* Dumps a 32-bit shadow page directory and page tables.
3714	*
3715	* @returns VBox status code (VINF_SUCCESS).
3716	* @param pVM The VM handle.
3717	* @param cr3 The root of the hierarchy.
3718	* @param cr4 The CR4, PSE is currently used.
3719	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3720	* @param pHlp Pointer to the output functions.
3721	*/
3722	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3723	{
3724	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3725	if (!pPD)
3726	{
3727	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3728	return VERR_INVALID_PARAMETER;
3729	}
3730
3731	int rc = VINF_SUCCESS;
3732	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3733	{
3734	X86PDE Pde = pPD->a[i];
3735	if (Pde.n.u1Present)
3736	{
3737	const uint32_t u32Address = i << X86_PD_SHIFT;
3738	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3739	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3740	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3741	u32Address,
3742	Pde.b.u1Write ? 'W' : 'R',
3743	Pde.b.u1User ? 'U' : 'S',
3744	Pde.b.u1Accessed ? 'A' : '-',
3745	Pde.b.u1Dirty ? 'D' : '-',
3746	Pde.b.u1Global ? 'G' : '-',
3747	Pde.b.u1WriteThru ? "WT" : "--",
3748	Pde.b.u1CacheDisable? "CD" : "--",
3749	Pde.b.u1PAT ? "AT" : "--",
3750	Pde.u & RT_BIT_64(9) ? '1' : '0',
3751	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3752	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3753	Pde.u & X86_PDE4M_PG_MASK);
3754	else
3755	{
3756	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3757	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3758	u32Address,
3759	Pde.n.u1Write ? 'W' : 'R',
3760	Pde.n.u1User ? 'U' : 'S',
3761	Pde.n.u1Accessed ? 'A' : '-',
3762	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3763	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3764	Pde.n.u1WriteThru ? "WT" : "--",
3765	Pde.n.u1CacheDisable? "CD" : "--",
3766	Pde.u & RT_BIT_64(9) ? '1' : '0',
3767	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3768	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3769	Pde.u & X86_PDE_PG_MASK);
3770	if (cMaxDepth >= 1)
3771	{
3772	/** @todo what about using the page pool for mapping PTs? */
3773	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3774	PX86PT pPT = NULL;
3775	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3776	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3777	else
3778	{
3779	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3780	if (u32Address - pMap->GCPtr < pMap->cb)
3781	{
3782	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3783	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3784	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3785	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3786	pPT = pMap->aPTs[iPDE].pPTR3;
3787	}
3788	}
3789	int rc2 = VERR_INVALID_PARAMETER;
3790	if (pPT)
3791	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3792	else
3793	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3794	if (rc2 < rc && RT_SUCCESS(rc))
3795	rc = rc2;
3796	}
3797	}
3798	}
3799	}
3800
3801	return rc;
3802	}
3803
3804
3805	/**
3806	* Dumps a 32-bit shadow page table.
3807	*
3808	* @returns VBox status code (VINF_SUCCESS).
3809	* @param pVM The VM handle.
3810	* @param pPT Pointer to the page table.
3811	* @param u32Address The virtual address this table starts at.
3812	* @param PhysSearch Address to search for.
3813	*/
3814	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3815	{
3816	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3817	{
3818	X86PTE Pte = pPT->a[i];
3819	if (Pte.n.u1Present)
3820	{
3821	Log(( /P R S A D G WT CD AT NX 4M a m d /
3822	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3823	u32Address + (i << X86_PT_SHIFT),
3824	Pte.n.u1Write ? 'W' : 'R',
3825	Pte.n.u1User ? 'U' : 'S',
3826	Pte.n.u1Accessed ? 'A' : '-',
3827	Pte.n.u1Dirty ? 'D' : '-',
3828	Pte.n.u1Global ? 'G' : '-',
3829	Pte.n.u1WriteThru ? "WT" : "--",
3830	Pte.n.u1CacheDisable? "CD" : "--",
3831	Pte.n.u1PAT ? "AT" : "--",
3832	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3833	Pte.u & RT_BIT(10) ? '1' : '0',
3834	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3835	Pte.u & X86_PDE_PG_MASK));
3836
3837	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3838	{
3839	uint64_t fPageShw = 0;
3840	RTHCPHYS pPhysHC = 0;
3841
3842	/** @todo SMP support!! */
3843	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3844	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3845	}
3846	}
3847	}
3848	return VINF_SUCCESS;
3849	}
3850
3851
3852	/**
3853	* Dumps a 32-bit guest page directory and page tables.
3854	*
3855	* @returns VBox status code (VINF_SUCCESS).
3856	* @param pVM The VM handle.
3857	* @param cr3 The root of the hierarchy.
3858	* @param cr4 The CR4, PSE is currently used.
3859	* @param PhysSearch Address to search for.
3860	*/
3861	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3862	{
3863	bool fLongMode = false;
3864	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3865	PX86PD pPD = 0;
3866
3867	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3868	if (RT_FAILURE(rc) \|\| !pPD)
3869	{
3870	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3871	return VERR_INVALID_PARAMETER;
3872	}
3873
3874	Log(("cr3=%08x cr4=%08x%s\n"
3875	"%-*s P - Present\n"
3876	"%-*s \| R/W - Read (0) / Write (1)\n"
3877	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3878	"%-*s \| \| \| A - Accessed\n"
3879	"%-*s \| \| \| \| D - Dirty\n"
3880	"%-*s \| \| \| \| \| G - Global\n"
3881	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3882	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3883	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3884	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3885	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3886	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3887	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3888	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3889	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3890	- W U - - - -- -- -- -- -- 010 */
3891	, cr3, cr4, fLongMode ? " Long Mode" : "",
3892	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3893	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3894
3895	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3896	{
3897	X86PDE Pde = pPD->a[i];
3898	if (Pde.n.u1Present)
3899	{
3900	const uint32_t u32Address = i << X86_PD_SHIFT;
3901
3902	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3903	Log(( /P R S A D G WT CD AT NX 4M a m d /
3904	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3905	u32Address,
3906	Pde.b.u1Write ? 'W' : 'R',
3907	Pde.b.u1User ? 'U' : 'S',
3908	Pde.b.u1Accessed ? 'A' : '-',
3909	Pde.b.u1Dirty ? 'D' : '-',
3910	Pde.b.u1Global ? 'G' : '-',
3911	Pde.b.u1WriteThru ? "WT" : "--",
3912	Pde.b.u1CacheDisable? "CD" : "--",
3913	Pde.b.u1PAT ? "AT" : "--",
3914	Pde.u & RT_BIT(9) ? '1' : '0',
3915	Pde.u & RT_BIT(10) ? '1' : '0',
3916	Pde.u & RT_BIT(11) ? '1' : '0',
3917	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3918	/** @todo PhysSearch */
3919	else
3920	{
3921	Log(( /P R S A D G WT CD AT NX 4M a m d /
3922	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3923	u32Address,
3924	Pde.n.u1Write ? 'W' : 'R',
3925	Pde.n.u1User ? 'U' : 'S',
3926	Pde.n.u1Accessed ? 'A' : '-',
3927	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3928	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3929	Pde.n.u1WriteThru ? "WT" : "--",
3930	Pde.n.u1CacheDisable? "CD" : "--",
3931	Pde.u & RT_BIT(9) ? '1' : '0',
3932	Pde.u & RT_BIT(10) ? '1' : '0',
3933	Pde.u & RT_BIT(11) ? '1' : '0',
3934	Pde.u & X86_PDE_PG_MASK));
3935	////if (cMaxDepth >= 1)
3936	{
3937	/** @todo what about using the page pool for mapping PTs? */
3938	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3939	PX86PT pPT = NULL;
3940
3941	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3942
3943	int rc2 = VERR_INVALID_PARAMETER;
3944	if (pPT)
3945	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3946	else
3947	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3948	if (rc2 < rc && RT_SUCCESS(rc))
3949	rc = rc2;
3950	}
3951	}
3952	}
3953	}
3954
3955	return rc;
3956	}
3957
3958
3959	/**
3960	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3961	*
3962	* @returns VBox status code (VINF_SUCCESS).
3963	* @param pVM The VM handle.
3964	* @param cr3 The root of the hierarchy.
3965	* @param cr4 The cr4, only PAE and PSE is currently used.
3966	* @param fLongMode Set if long mode, false if not long mode.
3967	* @param cMaxDepth Number of levels to dump.
3968	* @param pHlp Pointer to the output functions.
3969	*/
3970	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3971	{
3972	if (!pHlp)
3973	pHlp = DBGFR3InfoLogHlp();
3974	if (!cMaxDepth)
3975	return VINF_SUCCESS;
3976	const unsigned cch = fLongMode ? 16 : 8;
3977	pHlp->pfnPrintf(pHlp,
3978	"cr3=%08x cr4=%08x%s\n"
3979	"%-*s P - Present\n"
3980	"%-*s \| R/W - Read (0) / Write (1)\n"
3981	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3982	"%-*s \| \| \| A - Accessed\n"
3983	"%-*s \| \| \| \| D - Dirty\n"
3984	"%-*s \| \| \| \| \| G - Global\n"
3985	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3986	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3987	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3988	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3989	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3990	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3991	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3992	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3993	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3994	- W U - - - -- -- -- -- -- 010 */
3995	, cr3, cr4, fLongMode ? " Long Mode" : "",
3996	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3997	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3998	if (cr4 & X86_CR4_PAE)
3999	{
4000	if (fLongMode)
4001	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4002	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4003	}
4004	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4005	}
4006
4007	#ifdef VBOX_WITH_DEBUGGER
4008
4009	/**
4010	* The '.pgmram' command.
4011	*
4012	* @returns VBox status.
4013	* @param pCmd Pointer to the command descriptor (as registered).
4014	* @param pCmdHlp Pointer to command helper functions.
4015	* @param pVM Pointer to the current VM (if any).
4016	* @param paArgs Pointer to (readonly) array of arguments.
4017	* @param cArgs Number of arguments in the array.
4018	*/
4019	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4020	{
4021	/*
4022	* Validate input.
4023	*/
4024	if (!pVM)
4025	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4026	if (!pVM->pgm.s.pRamRangesRC)
4027	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4028
4029	/*
4030	* Dump the ranges.
4031	*/
4032	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4033	PPGMRAMRANGE pRam;
4034	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4035	{
4036	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4037	"%RGp - %RGp %p\n",
4038	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4039	if (RT_FAILURE(rc))
4040	return rc;
4041	}
4042
4043	return VINF_SUCCESS;
4044	}
4045
4046
4047	/**
4048	* The '.pgmerror' and '.pgmerroroff' commands.
4049	*
4050	* @returns VBox status.
4051	* @param pCmd Pointer to the command descriptor (as registered).
4052	* @param pCmdHlp Pointer to command helper functions.
4053	* @param pVM Pointer to the current VM (if any).
4054	* @param paArgs Pointer to (readonly) array of arguments.
4055	* @param cArgs Number of arguments in the array.
4056	*/
4057	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4058	{
4059	/*
4060	* Validate input.
4061	*/
4062	if (!pVM)
4063	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4064	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4065	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4066
4067	if (!cArgs)
4068	{
4069	/*
4070	* Print the list of error injection locations with status.
4071	*/
4072	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4073	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4074	}
4075	else
4076	{
4077
4078	/*
4079	* String switch on where to inject the error.
4080	*/
4081	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4082	const char *pszWhere = paArgs[0].u.pszString;
4083	if (!strcmp(pszWhere, "handy"))
4084	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4085	else
4086	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4087	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4088	}
4089	return VINF_SUCCESS;
4090	}
4091
4092
4093	/**
4094	* The '.pgmsync' command.
4095	*
4096	* @returns VBox status.
4097	* @param pCmd Pointer to the command descriptor (as registered).
4098	* @param pCmdHlp Pointer to command helper functions.
4099	* @param pVM Pointer to the current VM (if any).
4100	* @param paArgs Pointer to (readonly) array of arguments.
4101	* @param cArgs Number of arguments in the array.
4102	*/
4103	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4104	{
4105	/** @todo SMP support */
4106	PVMCPU pVCpu = &pVM->aCpus[0];
4107
4108	/*
4109	* Validate input.
4110	*/
4111	if (!pVM)
4112	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4113
4114	/*
4115	* Force page directory sync.
4116	*/
4117	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4118
4119	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4120	if (RT_FAILURE(rc))
4121	return rc;
4122
4123	return VINF_SUCCESS;
4124	}
4125
4126
4127	#ifdef VBOX_STRICT
4128	/**
4129	* The '.pgmassertcr3' command.
4130	*
4131	* @returns VBox status.
4132	* @param pCmd Pointer to the command descriptor (as registered).
4133	* @param pCmdHlp Pointer to command helper functions.
4134	* @param pVM Pointer to the current VM (if any).
4135	* @param paArgs Pointer to (readonly) array of arguments.
4136	* @param cArgs Number of arguments in the array.
4137	*/
4138	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4139	{
4140	/** @todo SMP support!! */
4141	PVMCPU pVCpu = &pVM->aCpus[0];
4142
4143	/*
4144	* Validate input.
4145	*/
4146	if (!pVM)
4147	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4148
4149	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4150	if (RT_FAILURE(rc))
4151	return rc;
4152
4153	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4154
4155	return VINF_SUCCESS;
4156	}
4157	#endif /* VBOX_STRICT */
4158
4159
4160	/**
4161	* The '.pgmsyncalways' command.
4162	*
4163	* @returns VBox status.
4164	* @param pCmd Pointer to the command descriptor (as registered).
4165	* @param pCmdHlp Pointer to command helper functions.
4166	* @param pVM Pointer to the current VM (if any).
4167	* @param paArgs Pointer to (readonly) array of arguments.
4168	* @param cArgs Number of arguments in the array.
4169	*/
4170	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4171	{
4172	/** @todo SMP support!! */
4173	PVMCPU pVCpu = &pVM->aCpus[0];
4174
4175	/*
4176	* Validate input.
4177	*/
4178	if (!pVM)
4179	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4180
4181	/*
4182	* Force page directory sync.
4183	*/
4184	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4185	{
4186	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4187	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4188	}
4189	else
4190	{
4191	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4192	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4193	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4194	}
4195	}
4196
4197
4198	/**
4199	* The '.pgmsyncalways' command.
4200	*
4201	* @returns VBox status.
4202	* @param pCmd Pointer to the command descriptor (as registered).
4203	* @param pCmdHlp Pointer to command helper functions.
4204	* @param pVM Pointer to the current VM (if any).
4205	* @param paArgs Pointer to (readonly) array of arguments.
4206	* @param cArgs Number of arguments in the array.
4207	*/
4208	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4209	{
4210	/*
4211	* Validate input.
4212	*/
4213	if (!pVM)
4214	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4215	if ( cArgs < 1
4216	\|\| cArgs > 2
4217	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4218	\|\| ( cArgs > 1
4219	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4220	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4221	if ( cArgs >= 2
4222	&& strcmp(paArgs[1].u.pszString, "nozero"))
4223	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4224	bool fIncZeroPgs = cArgs < 2;
4225
4226	/*
4227	* Open the output file and get the ram parameters.
4228	*/
4229	RTFILE hFile;
4230	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4231	if (RT_FAILURE(rc))
4232	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4233
4234	uint32_t cbRamHole = 0;
4235	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4236	uint64_t cbRam = 0;
4237	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4238	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4239
4240	/*
4241	* Dump the physical memory, page by page.
4242	*/
4243	RTGCPHYS GCPhys = 0;
4244	char abZeroPg[PAGE_SIZE];
4245	RT_ZERO(abZeroPg);
4246
4247	pgmLock(pVM);
4248	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4249	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4250	pRam = pRam->pNextR3)
4251	{
4252	/* fill the gap */
4253	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4254	{
4255	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4256	{
4257	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4258	GCPhys += PAGE_SIZE;
4259	}
4260	}
4261
4262	PCPGMPAGE pPage = &pRam->aPages[0];
4263	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4264	{
4265	if (PGM_PAGE_IS_ZERO(pPage))
4266	{
4267	if (fIncZeroPgs)
4268	{
4269	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4270	if (RT_FAILURE(rc))
4271	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4272	}
4273	}
4274	else
4275	{
4276	switch (PGM_PAGE_GET_TYPE(pPage))
4277	{
4278	case PGMPAGETYPE_RAM:
4279	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4280	case PGMPAGETYPE_ROM:
4281	case PGMPAGETYPE_MMIO2:
4282	{
4283	void const *pvPage;
4284	PGMPAGEMAPLOCK Lock;
4285	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4286	if (RT_SUCCESS(rc))
4287	{
4288	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4289	PGMPhysReleasePageMappingLock(pVM, &Lock);
4290	if (RT_FAILURE(rc))
4291	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4292	}
4293	else
4294	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4295	break;
4296	}
4297
4298	default:
4299	AssertFailed();
4300	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4301	case PGMPAGETYPE_MMIO:
4302	if (fIncZeroPgs)
4303	{
4304	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4305	if (RT_FAILURE(rc))
4306	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4307	}
4308	break;
4309	}
4310	}
4311
4312
4313	/* advance */
4314	GCPhys += PAGE_SIZE;
4315	pPage++;
4316	}
4317	}
4318	pgmUnlock(pVM);
4319
4320	RTFileClose(hFile);
4321	if (RT_SUCCESS(rc))
4322	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4323	return VINF_SUCCESS;
4324	}
4325
4326	#endif /* VBOX_WITH_DEBUGGER */
4327
4328	/**
4329	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4330	*/
4331	typedef struct PGMCHECKINTARGS
4332	{
4333	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4334	PPGMPHYSHANDLER pPrevPhys;
4335	PPGMVIRTHANDLER pPrevVirt;
4336	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4337	PVM pVM;
4338	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4339
4340	/**
4341	* Validate a node in the physical handler tree.
4342	*
4343	* @returns 0 on if ok, other wise 1.
4344	* @param pNode The handler node.
4345	* @param pvUser pVM.
4346	*/
4347	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4348	{
4349	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4350	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4351	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4352	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4353	AssertReleaseMsg( !pArgs->pPrevPhys
4354	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4355	("pPrevPhys=%p %RGp-%RGp %s\n"
4356	" pCur=%p %RGp-%RGp %s\n",
4357	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4358	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4359	pArgs->pPrevPhys = pCur;
4360	return 0;
4361	}
4362
4363
4364	/**
4365	* Validate a node in the virtual handler tree.
4366	*
4367	* @returns 0 on if ok, other wise 1.
4368	* @param pNode The handler node.
4369	* @param pvUser pVM.
4370	*/
4371	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4372	{
4373	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4374	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4375	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4376	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4377	AssertReleaseMsg( !pArgs->pPrevVirt
4378	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4379	("pPrevVirt=%p %RGv-%RGv %s\n"
4380	" pCur=%p %RGv-%RGv %s\n",
4381	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4382	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4383	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4384	{
4385	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4386	("pCur=%p %RGv-%RGv %s\n"
4387	"iPage=%d offVirtHandle=%#x expected %#x\n",
4388	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4389	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4390	}
4391	pArgs->pPrevVirt = pCur;
4392	return 0;
4393	}
4394
4395
4396	/**
4397	* Validate a node in the virtual handler tree.
4398	*
4399	* @returns 0 on if ok, other wise 1.
4400	* @param pNode The handler node.
4401	* @param pvUser pVM.
4402	*/
4403	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4404	{
4405	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4406	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4407	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4408	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4409	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4410	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4411	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4412	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4413	" pCur=%p %RGp-%RGp\n",
4414	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4415	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4416	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4417	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4418	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4419	" pCur=%p %RGp-%RGp\n",
4420	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4421	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4422	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4423	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4424	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4425	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4426	{
4427	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4428	for (;;)
4429	{
4430	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4431	AssertReleaseMsg(pCur2 != pCur,
4432	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4433	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4434	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4435	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4436	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4437	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4438	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4439	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4440	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4441	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4442	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4443	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4444	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4445	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4446	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4447	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4448	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4449	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4450	break;
4451	}
4452	}
4453
4454	pArgs->pPrevPhys2Virt = pCur;
4455	return 0;
4456	}
4457
4458
4459	/**
4460	* Perform an integrity check on the PGM component.
4461	*
4462	* @returns VINF_SUCCESS if everything is fine.
4463	* @returns VBox error status after asserting on integrity breach.
4464	* @param pVM The VM handle.
4465	*/
4466	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4467	{
4468	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4469
4470	/*
4471	* Check the trees.
4472	*/
4473	int cErrors = 0;
4474	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4475	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4476	PGMCHECKINTARGS Args = s_LeftToRight;
4477	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4478	Args = s_RightToLeft;
4479	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4480	Args = s_LeftToRight;
4481	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4482	Args = s_RightToLeft;
4483	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4484	Args = s_LeftToRight;
4485	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4486	Args = s_RightToLeft;
4487	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4488	Args = s_LeftToRight;
4489	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4490	Args = s_RightToLeft;
4491	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4492
4493	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4494	}
4495

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 27046

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