PGM.cpp@ 30791

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1	/* $Id: PGM.cpp 30761 2010-07-09 13:27:50Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570	/*******************************************************************************
571	* Header Files *
572	*******************************************************************************/
573	#define LOG_GROUP LOG_GROUP_PGM
574	#include <VBox/dbgf.h>
575	#include <VBox/pgm.h>
576	#include <VBox/cpum.h>
577	#include <VBox/iom.h>
578	#include <VBox/sup.h>
579	#include <VBox/mm.h>
580	#include <VBox/em.h>
581	#include <VBox/stam.h>
582	#include <VBox/rem.h>
583	#include <VBox/selm.h>
584	#include <VBox/ssm.h>
585	#include <VBox/hwaccm.h>
586	#include "PGMInternal.h"
587	#include <VBox/vm.h>
588	#include "PGMInline.h"
589
590	#include <VBox/dbg.h>
591	#include <VBox/param.h>
592	#include <VBox/err.h>
593
594	#include <iprt/asm.h>
595	#include <iprt/assert.h>
596	#include <iprt/env.h>
597	#include <iprt/mem.h>
598	#include <iprt/file.h>
599	#include <iprt/string.h>
600	#include <iprt/thread.h>
601
602
603	/*******************************************************************************
604	* Defined Constants And Macros *
605	*******************************************************************************/
606	/** Saved state data unit version for 2.5.x and later. */
607	#define PGM_SAVED_STATE_VERSION 9
608	/** Saved state data unit version for 2.2.2 and later. */
609	#define PGM_SAVED_STATE_VERSION_2_2_2 8
610	/** Saved state data unit version for 2.2.0. */
611	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
612	/** Saved state data unit version. */
613	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
614
615
616	/*******************************************************************************
617	* Internal Functions *
618	*******************************************************************************/
619	static int pgmR3InitPaging(PVM pVM);
620	static void pgmR3InitStats(PVM pVM);
621	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
622	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
623	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
624	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
625	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
626	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
627	#ifdef VBOX_STRICT
628	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
629	#endif
630	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
631	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
632	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
633
634	#ifdef VBOX_WITH_DEBUGGER
635	/** @todo Convert the first two commands to 'info' items. */
636	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# ifdef VBOX_STRICT
641	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# endif
643	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
652	static const DBGCVARDESC g_aPgmErrorArgs[] =
653	{
654	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
655	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
656	};
657
658	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
659	{
660	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
661	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
662	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
663	};
664
665	/** Command descriptors. */
666	static const DBGCCMD g_aCmds[] =
667	{
668	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
669	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
670	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
671	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
672	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
673	#ifdef VBOX_STRICT
674	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
675	#endif
676	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
677	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
678	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
679	#endif
680	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
681	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
682	};
683	#endif
684
685
686
687
688	/*
689	* Shadow - 32-bit mode
690	*/
691	#define PGM_SHW_TYPE PGM_TYPE_32BIT
692	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
693	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
694	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
695	#include "PGMShw.h"
696
697	/* Guest - real mode */
698	#define PGM_GST_TYPE PGM_TYPE_REAL
699	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
707	#include "PGMBth.h"
708	#include "PGMGstDefs.h"
709	#include "PGMGst.h"
710	#undef BTH_PGMPOOLKIND_PT_FOR_PT
711	#undef BTH_PGMPOOLKIND_ROOT
712	#undef PGM_BTH_NAME
713	#undef PGM_BTH_NAME_RC_STR
714	#undef PGM_BTH_NAME_R0_STR
715	#undef PGM_GST_TYPE
716	#undef PGM_GST_NAME
717	#undef PGM_GST_NAME_RC_STR
718	#undef PGM_GST_NAME_R0_STR
719
720	/* Guest - protected mode */
721	#define PGM_GST_TYPE PGM_TYPE_PROT
722	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
723	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
724	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
725	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
726	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
727	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
728	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
729	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
730	#include "PGMBth.h"
731	#include "PGMGstDefs.h"
732	#include "PGMGst.h"
733	#undef BTH_PGMPOOLKIND_PT_FOR_PT
734	#undef BTH_PGMPOOLKIND_ROOT
735	#undef PGM_BTH_NAME
736	#undef PGM_BTH_NAME_RC_STR
737	#undef PGM_BTH_NAME_R0_STR
738	#undef PGM_GST_TYPE
739	#undef PGM_GST_NAME
740	#undef PGM_GST_NAME_RC_STR
741	#undef PGM_GST_NAME_R0_STR
742
743	/* Guest - 32-bit mode */
744	#define PGM_GST_TYPE PGM_TYPE_32BIT
745	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
746	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
747	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
748	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
749	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
750	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
751	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
752	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
753	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
754	#include "PGMBth.h"
755	#include "PGMGstDefs.h"
756	#include "PGMGst.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
758	#undef BTH_PGMPOOLKIND_PT_FOR_PT
759	#undef BTH_PGMPOOLKIND_ROOT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_RC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_RC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	#undef PGM_SHW_TYPE
769	#undef PGM_SHW_NAME
770	#undef PGM_SHW_NAME_RC_STR
771	#undef PGM_SHW_NAME_R0_STR
772
773
774	/*
775	* Shadow - PAE mode
776	*/
777	#define PGM_SHW_TYPE PGM_TYPE_PAE
778	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
779	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
780	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
782	#include "PGMShw.h"
783
784	/* Guest - real mode */
785	#define PGM_GST_TYPE PGM_TYPE_REAL
786	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
787	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
788	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
789	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
790	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
791	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
792	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
793	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
794	#include "PGMGstDefs.h"
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_PT
797	#undef BTH_PGMPOOLKIND_ROOT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_RC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_RC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - protected mode */
807	#define PGM_GST_TYPE PGM_TYPE_PROT
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
809	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
812	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
815	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
816	#include "PGMGstDefs.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_PT
819	#undef BTH_PGMPOOLKIND_ROOT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_RC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_RC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	/* Guest - 32-bit mode */
829	#define PGM_GST_TYPE PGM_TYPE_32BIT
830	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
831	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
832	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
833	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
834	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
835	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
836	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
837	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
838	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
839	#include "PGMGstDefs.h"
840	#include "PGMBth.h"
841	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
842	#undef BTH_PGMPOOLKIND_PT_FOR_PT
843	#undef BTH_PGMPOOLKIND_ROOT
844	#undef PGM_BTH_NAME
845	#undef PGM_BTH_NAME_RC_STR
846	#undef PGM_BTH_NAME_R0_STR
847	#undef PGM_GST_TYPE
848	#undef PGM_GST_NAME
849	#undef PGM_GST_NAME_RC_STR
850	#undef PGM_GST_NAME_R0_STR
851
852	/* Guest - PAE mode */
853	#define PGM_GST_TYPE PGM_TYPE_PAE
854	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
855	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
856	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
857	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
858	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
859	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
860	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
863	#include "PGMBth.h"
864	#include "PGMGstDefs.h"
865	#include "PGMGst.h"
866	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
867	#undef BTH_PGMPOOLKIND_PT_FOR_PT
868	#undef BTH_PGMPOOLKIND_ROOT
869	#undef PGM_BTH_NAME
870	#undef PGM_BTH_NAME_RC_STR
871	#undef PGM_BTH_NAME_R0_STR
872	#undef PGM_GST_TYPE
873	#undef PGM_GST_NAME
874	#undef PGM_GST_NAME_RC_STR
875	#undef PGM_GST_NAME_R0_STR
876
877	#undef PGM_SHW_TYPE
878	#undef PGM_SHW_NAME
879	#undef PGM_SHW_NAME_RC_STR
880	#undef PGM_SHW_NAME_R0_STR
881
882
883	/*
884	* Shadow - AMD64 mode
885	*/
886	#define PGM_SHW_TYPE PGM_TYPE_AMD64
887	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
888	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
889	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
890	#include "PGMShw.h"
891
892	#ifdef VBOX_WITH_64_BITS_GUESTS
893	/* Guest - AMD64 mode */
894	# define PGM_GST_TYPE PGM_TYPE_AMD64
895	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
896	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
897	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
898	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
899	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
900	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
901	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
902	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
903	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
904	# include "PGMBth.h"
905	# include "PGMGstDefs.h"
906	# include "PGMGst.h"
907	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
908	# undef BTH_PGMPOOLKIND_PT_FOR_PT
909	# undef BTH_PGMPOOLKIND_ROOT
910	# undef PGM_BTH_NAME
911	# undef PGM_BTH_NAME_RC_STR
912	# undef PGM_BTH_NAME_R0_STR
913	# undef PGM_GST_TYPE
914	# undef PGM_GST_NAME
915	# undef PGM_GST_NAME_RC_STR
916	# undef PGM_GST_NAME_R0_STR
917	#endif /* VBOX_WITH_64_BITS_GUESTS */
918
919	#undef PGM_SHW_TYPE
920	#undef PGM_SHW_NAME
921	#undef PGM_SHW_NAME_RC_STR
922	#undef PGM_SHW_NAME_R0_STR
923
924
925	/*
926	* Shadow - Nested paging mode
927	*/
928	#define PGM_SHW_TYPE PGM_TYPE_NESTED
929	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
930	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
931	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
932	#include "PGMShw.h"
933
934	/* Guest - real mode */
935	#define PGM_GST_TYPE PGM_TYPE_REAL
936	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
937	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
938	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
939	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
940	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
941	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
942	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
943	#include "PGMGstDefs.h"
944	#include "PGMBth.h"
945	#undef BTH_PGMPOOLKIND_PT_FOR_PT
946	#undef PGM_BTH_NAME
947	#undef PGM_BTH_NAME_RC_STR
948	#undef PGM_BTH_NAME_R0_STR
949	#undef PGM_GST_TYPE
950	#undef PGM_GST_NAME
951	#undef PGM_GST_NAME_RC_STR
952	#undef PGM_GST_NAME_R0_STR
953
954	/* Guest - protected mode */
955	#define PGM_GST_TYPE PGM_TYPE_PROT
956	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
957	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
958	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
959	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
960	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
961	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
962	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
963	#include "PGMGstDefs.h"
964	#include "PGMBth.h"
965	#undef BTH_PGMPOOLKIND_PT_FOR_PT
966	#undef PGM_BTH_NAME
967	#undef PGM_BTH_NAME_RC_STR
968	#undef PGM_BTH_NAME_R0_STR
969	#undef PGM_GST_TYPE
970	#undef PGM_GST_NAME
971	#undef PGM_GST_NAME_RC_STR
972	#undef PGM_GST_NAME_R0_STR
973
974	/* Guest - 32-bit mode */
975	#define PGM_GST_TYPE PGM_TYPE_32BIT
976	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
977	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
978	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
979	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
980	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
981	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
982	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
983	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
984	#include "PGMGstDefs.h"
985	#include "PGMBth.h"
986	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
987	#undef BTH_PGMPOOLKIND_PT_FOR_PT
988	#undef PGM_BTH_NAME
989	#undef PGM_BTH_NAME_RC_STR
990	#undef PGM_BTH_NAME_R0_STR
991	#undef PGM_GST_TYPE
992	#undef PGM_GST_NAME
993	#undef PGM_GST_NAME_RC_STR
994	#undef PGM_GST_NAME_R0_STR
995
996	/* Guest - PAE mode */
997	#define PGM_GST_TYPE PGM_TYPE_PAE
998	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
999	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1000	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1001	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1002	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1003	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1004	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1005	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1006	#include "PGMGstDefs.h"
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	#ifdef VBOX_WITH_64_BITS_GUESTS
1019	/* Guest - AMD64 mode */
1020	# define PGM_GST_TYPE PGM_TYPE_AMD64
1021	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1022	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1023	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1024	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1025	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1026	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1027	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1028	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1029	# include "PGMGstDefs.h"
1030	# include "PGMBth.h"
1031	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1032	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1033	# undef PGM_BTH_NAME
1034	# undef PGM_BTH_NAME_RC_STR
1035	# undef PGM_BTH_NAME_R0_STR
1036	# undef PGM_GST_TYPE
1037	# undef PGM_GST_NAME
1038	# undef PGM_GST_NAME_RC_STR
1039	# undef PGM_GST_NAME_R0_STR
1040	#endif /* VBOX_WITH_64_BITS_GUESTS */
1041
1042	#undef PGM_SHW_TYPE
1043	#undef PGM_SHW_NAME
1044	#undef PGM_SHW_NAME_RC_STR
1045	#undef PGM_SHW_NAME_R0_STR
1046
1047
1048	/*
1049	* Shadow - EPT
1050	*/
1051	#define PGM_SHW_TYPE PGM_TYPE_EPT
1052	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1053	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1054	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1055	#include "PGMShw.h"
1056
1057	/* Guest - real mode */
1058	#define PGM_GST_TYPE PGM_TYPE_REAL
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1060	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1063	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1066	#include "PGMGstDefs.h"
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1069	#undef PGM_BTH_NAME
1070	#undef PGM_BTH_NAME_RC_STR
1071	#undef PGM_BTH_NAME_R0_STR
1072	#undef PGM_GST_TYPE
1073	#undef PGM_GST_NAME
1074	#undef PGM_GST_NAME_RC_STR
1075	#undef PGM_GST_NAME_R0_STR
1076
1077	/* Guest - protected mode */
1078	#define PGM_GST_TYPE PGM_TYPE_PROT
1079	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1080	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1081	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1082	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1083	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1084	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1085	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1086	#include "PGMGstDefs.h"
1087	#include "PGMBth.h"
1088	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	#undef PGM_BTH_NAME
1090	#undef PGM_BTH_NAME_RC_STR
1091	#undef PGM_BTH_NAME_R0_STR
1092	#undef PGM_GST_TYPE
1093	#undef PGM_GST_NAME
1094	#undef PGM_GST_NAME_RC_STR
1095	#undef PGM_GST_NAME_R0_STR
1096
1097	/* Guest - 32-bit mode */
1098	#define PGM_GST_TYPE PGM_TYPE_32BIT
1099	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1100	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1101	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1102	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1103	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1104	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1105	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1106	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1107	#include "PGMGstDefs.h"
1108	#include "PGMBth.h"
1109	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1110	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1111	#undef PGM_BTH_NAME
1112	#undef PGM_BTH_NAME_RC_STR
1113	#undef PGM_BTH_NAME_R0_STR
1114	#undef PGM_GST_TYPE
1115	#undef PGM_GST_NAME
1116	#undef PGM_GST_NAME_RC_STR
1117	#undef PGM_GST_NAME_R0_STR
1118
1119	/* Guest - PAE mode */
1120	#define PGM_GST_TYPE PGM_TYPE_PAE
1121	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1122	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1123	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1124	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1125	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1126	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1127	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1128	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1129	#include "PGMGstDefs.h"
1130	#include "PGMBth.h"
1131	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1132	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1133	#undef PGM_BTH_NAME
1134	#undef PGM_BTH_NAME_RC_STR
1135	#undef PGM_BTH_NAME_R0_STR
1136	#undef PGM_GST_TYPE
1137	#undef PGM_GST_NAME
1138	#undef PGM_GST_NAME_RC_STR
1139	#undef PGM_GST_NAME_R0_STR
1140
1141	#ifdef VBOX_WITH_64_BITS_GUESTS
1142	/* Guest - AMD64 mode */
1143	# define PGM_GST_TYPE PGM_TYPE_AMD64
1144	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1145	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1146	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1147	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1148	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1149	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1150	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1151	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1152	# include "PGMGstDefs.h"
1153	# include "PGMBth.h"
1154	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1155	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1156	# undef PGM_BTH_NAME
1157	# undef PGM_BTH_NAME_RC_STR
1158	# undef PGM_BTH_NAME_R0_STR
1159	# undef PGM_GST_TYPE
1160	# undef PGM_GST_NAME
1161	# undef PGM_GST_NAME_RC_STR
1162	# undef PGM_GST_NAME_R0_STR
1163	#endif /* VBOX_WITH_64_BITS_GUESTS */
1164
1165	#undef PGM_SHW_TYPE
1166	#undef PGM_SHW_NAME
1167	#undef PGM_SHW_NAME_RC_STR
1168	#undef PGM_SHW_NAME_R0_STR
1169
1170
1171
1172	/**
1173	* Initiates the paging of VM.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM Pointer to VM structure.
1177	*/
1178	VMMR3DECL(int) PGMR3Init(PVM pVM)
1179	{
1180	LogFlow(("PGMR3Init:\n"));
1181	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1182	int rc;
1183
1184	/*
1185	* Assert alignment and sizes.
1186	*/
1187	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1188	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1189	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1190
1191	/*
1192	* Init the structure.
1193	*/
1194	#ifdef PGM_WITHOUT_MAPPINGS
1195	pVM->pgm.s.fMappingsDisabled = true;
1196	#endif
1197	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1198	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1199
1200	/* Init the per-CPU part. */
1201	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1202	{
1203	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1204	PPGMCPU pPGM = &pVCpu->pgm.s;
1205
1206	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1207	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1208	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1209
1210	pPGM->enmShadowMode = PGMMODE_INVALID;
1211	pPGM->enmGuestMode = PGMMODE_INVALID;
1212
1213	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1214
1215	pPGM->pGstPaePdptR3 = NULL;
1216	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1217	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1218	#endif
1219	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1220	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1221	{
1222	pPGM->apGstPaePDsR3[i] = NULL;
1223	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1224	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1225	#endif
1226	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1227	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1228	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1229	}
1230
1231	pPGM->fA20Enabled = true;
1232	}
1233
1234	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1235	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1236	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1237
1238	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1239	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1240	true
1241	#else
1242	false
1243	#endif
1244	);
1245	AssertLogRelRCReturn(rc, rc);
1246
1247	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1248	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1249	#else
1250	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1251	#endif
1252	AssertLogRelRCReturn(rc, rc);
1253	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1254	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1255
1256	/*
1257	* Get the configured RAM size - to estimate saved state size.
1258	*/
1259	uint64_t cbRam;
1260	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1261	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1262	cbRam = 0;
1263	else if (RT_SUCCESS(rc))
1264	{
1265	if (cbRam < PAGE_SIZE)
1266	cbRam = 0;
1267	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1268	}
1269	else
1270	{
1271	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1272	return rc;
1273	}
1274
1275	/*
1276	* Register callbacks, string formatters and the saved state data unit.
1277	*/
1278	#ifdef VBOX_STRICT
1279	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1280	#endif
1281	PGMRegisterStringFormatTypes();
1282
1283	rc = pgmR3InitSavedState(pVM, cbRam);
1284	if (RT_FAILURE(rc))
1285	return rc;
1286
1287	/*
1288	* Initialize the PGM critical section and flush the phys TLBs
1289	*/
1290	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1291	AssertRCReturn(rc, rc);
1292
1293	PGMR3PhysChunkInvalidateTLB(pVM);
1294	PGMPhysInvalidatePageMapTLB(pVM);
1295
1296	/*
1297	* For the time being we sport a full set of handy pages in addition to the base
1298	* memory to simplify things.
1299	*/
1300	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1301	AssertRCReturn(rc, rc);
1302
1303	/*
1304	* Trees
1305	*/
1306	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1307	if (RT_SUCCESS(rc))
1308	{
1309	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1310	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1311
1312	/*
1313	* Alocate the zero page.
1314	*/
1315	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1316	}
1317	if (RT_SUCCESS(rc))
1318	{
1319	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1320	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1321	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1322	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1323
1324	/*
1325	* Init the paging.
1326	*/
1327	rc = pgmR3InitPaging(pVM);
1328	}
1329	if (RT_SUCCESS(rc))
1330	{
1331	/*
1332	* Init the page pool.
1333	*/
1334	rc = pgmR3PoolInit(pVM);
1335	}
1336	if (RT_SUCCESS(rc))
1337	{
1338	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1339	{
1340	PVMCPU pVCpu = &pVM->aCpus[i];
1341	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1342	if (RT_FAILURE(rc))
1343	break;
1344	}
1345	}
1346
1347	if (RT_SUCCESS(rc))
1348	{
1349	/*
1350	* Info & statistics
1351	*/
1352	DBGFR3InfoRegisterInternal(pVM, "mode",
1353	"Shows the current paging mode. "
1354	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1355	pgmR3InfoMode);
1356	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1357	"Dumps all the entries in the top level paging table. No arguments.",
1358	pgmR3InfoCr3);
1359	DBGFR3InfoRegisterInternal(pVM, "phys",
1360	"Dumps all the physical address ranges. No arguments.",
1361	pgmR3PhysInfo);
1362	DBGFR3InfoRegisterInternal(pVM, "handlers",
1363	"Dumps physical, virtual and hyper virtual handlers. "
1364	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1365	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1366	pgmR3InfoHandlers);
1367	DBGFR3InfoRegisterInternal(pVM, "mappings",
1368	"Dumps guest mappings.",
1369	pgmR3MapInfo);
1370
1371	pgmR3InitStats(pVM);
1372
1373	#ifdef VBOX_WITH_DEBUGGER
1374	/*
1375	* Debugger commands.
1376	*/
1377	static bool s_fRegisteredCmds = false;
1378	if (!s_fRegisteredCmds)
1379	{
1380	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1381	if (RT_SUCCESS(rc2))
1382	s_fRegisteredCmds = true;
1383	}
1384	#endif
1385	return VINF_SUCCESS;
1386	}
1387
1388	/* Almost no cleanup necessary, MM frees all memory. */
1389	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1390
1391	return rc;
1392	}
1393
1394
1395	/**
1396	* Initializes the per-VCPU PGM.
1397	*
1398	* @returns VBox status code.
1399	* @param pVM The VM to operate on.
1400	*/
1401	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1402	{
1403	LogFlow(("PGMR3InitCPU\n"));
1404	return VINF_SUCCESS;
1405	}
1406
1407
1408	/**
1409	* Init paging.
1410	*
1411	* Since we need to check what mode the host is operating in before we can choose
1412	* the right paging functions for the host we have to delay this until R0 has
1413	* been initialized.
1414	*
1415	* @returns VBox status code.
1416	* @param pVM VM handle.
1417	*/
1418	static int pgmR3InitPaging(PVM pVM)
1419	{
1420	/*
1421	* Force a recalculation of modes and switcher so everyone gets notified.
1422	*/
1423	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1424	{
1425	PVMCPU pVCpu = &pVM->aCpus[i];
1426
1427	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1428	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1429	}
1430
1431	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1432
1433	/*
1434	* Allocate static mapping space for whatever the cr3 register
1435	* points to and in the case of PAE mode to the 4 PDs.
1436	*/
1437	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1438	if (RT_FAILURE(rc))
1439	{
1440	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1441	return rc;
1442	}
1443	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1444
1445	/*
1446	* Allocate pages for the three possible intermediate contexts
1447	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1448	* for the sake of simplicity. The AMD64 uses the PAE for the
1449	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1450	*
1451	* We assume that two page tables will be enought for the core code
1452	* mappings (HC virtual and identity).
1453	*/
1454	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1455	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1456	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1466
1467	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1468	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1469	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1470	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1471	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1472	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1473
1474	/*
1475	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1476	*/
1477	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1478	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1479	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1480
1481	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1482	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1483
1484	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1485	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1486	{
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1488	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1489	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1490	}
1491
1492	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1493	{
1494	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1495	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1496	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1497	}
1498
1499	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1500	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1501	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1502	\| HCPhysInterPaePDPT64;
1503
1504	/*
1505	* Initialize paging workers and mode from current host mode
1506	* and the guest running in real mode.
1507	*/
1508	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1509	switch (pVM->pgm.s.enmHostMode)
1510	{
1511	case SUPPAGINGMODE_32_BIT:
1512	case SUPPAGINGMODE_32_BIT_GLOBAL:
1513	case SUPPAGINGMODE_PAE:
1514	case SUPPAGINGMODE_PAE_GLOBAL:
1515	case SUPPAGINGMODE_PAE_NX:
1516	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1517	break;
1518
1519	case SUPPAGINGMODE_AMD64:
1520	case SUPPAGINGMODE_AMD64_GLOBAL:
1521	case SUPPAGINGMODE_AMD64_NX:
1522	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1523	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1524	if (ARCH_BITS != 64)
1525	{
1526	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1527	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1528	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1529	}
1530	#endif
1531	break;
1532	default:
1533	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1534	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1535	}
1536	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1537	if (RT_SUCCESS(rc))
1538	{
1539	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1540	#if HC_ARCH_BITS == 64
1541	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1542	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1543	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1544	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1545	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1546	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1547	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1548	#endif
1549
1550	return VINF_SUCCESS;
1551	}
1552
1553	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1554	return rc;
1555	}
1556
1557
1558	/**
1559	* Init statistics
1560	*/
1561	static void pgmR3InitStats(PVM pVM)
1562	{
1563	PPGM pPGM = &pVM->pgm.s;
1564	int rc;
1565
1566	/* Common - misc variables */
1567	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1568	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1569	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1570	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1571	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1572	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1573	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1574	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1575	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1576	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1577	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1578	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1579	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1580	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1581	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1582
1583	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1584	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1585	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1586	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1587
1588	/* Live save */
1589	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1590	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1591	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1592	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1593	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1594	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1595	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1596	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1597	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1598	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1599	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1600	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1601	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1602	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1603	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1604	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1605	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1606	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1607
1608	#ifdef VBOX_WITH_STATISTICS
1609
1610	# define PGM_REG_COUNTER(a, b, c) \
1611	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1612	AssertRC(rc);
1613
1614	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1615	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1616	AssertRC(rc);
1617
1618	# define PGM_REG_PROFILE(a, b, c) \
1619	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1620	AssertRC(rc);
1621
1622	PGM_REG_PROFILE(&pPGM->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1623	PGM_REG_PROFILE(&pPGM->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1624	PGM_REG_PROFILE(&pPGM->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1625	PGM_REG_PROFILE(&pPGM->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1626
1627	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1628	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1629	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1630	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1631	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1632	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1633	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1635	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1636	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1637
1638	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1639	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1640	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1641	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1642	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1643	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1644	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1645	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1646	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1647	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1648
1649	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1650	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1651	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1652	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1653
1654	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1655	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1656	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1657	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1658
1659	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1660	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1661	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1662	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1663	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1664	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1665
1666	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1667	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1668	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1669	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1670	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1671	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1672	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1673	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1674
1675	/* GC only: */
1676	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1677	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1678	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1679	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1680
1681	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1682	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1683	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1684	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1685	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1686	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1687	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1688	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1689
1690	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1691	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1692	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1693	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1694	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1695	PGM_REG_COUNTER(&pPGM->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1696	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1697
1698	# undef PGM_REG_COUNTER
1699	# undef PGM_REG_PROFILE
1700	#endif
1701
1702	/*
1703	* Note! The layout below matches the member layout exactly!
1704	*/
1705
1706	/*
1707	* Common - stats
1708	*/
1709	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1710	{
1711	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1712
1713	#define PGM_REG_COUNTER(a, b, c) \
1714	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1715	AssertRC(rc);
1716	#define PGM_REG_PROFILE(a, b, c) \
1717	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1718	AssertRC(rc);
1719
1720	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1721
1722	#ifdef VBOX_WITH_STATISTICS
1723
1724	# if 0 /* rarely useful; leave for debugging. */
1725	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1726	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1727	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1728	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1729	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1730	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1731	# endif
1732	/* R0 only: */
1733	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1734	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1735	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1736	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1737	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1738	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1739	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1740	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1741	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1742	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1743	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1744	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1745	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1746	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1747	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1748	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1749	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1750	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1751	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1752	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1753	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1754	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1755	//PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1756	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1757	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1758	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1759	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1760	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1761	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1762	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1763	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1764	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1765	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1766	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1767	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1768	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1769
1770	/* RZ only: */
1771	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1772	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1773	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1774	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1775	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1776	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1777	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1778	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1779	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1780	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1781	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1782	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1783	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1784	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1785	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1786	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1787	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1788	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1789	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1790	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1791	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1792	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1793	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1794	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1795	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1796	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1797	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1798	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1799	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1800	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1801	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1802	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1803	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1804	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1805	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1806	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1807	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1808	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1809	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1810	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1811	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1812	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1813	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1814	#if 0 /* rarely useful; leave for debugging. */
1815	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1816	STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1817	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1818	#endif
1819	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1820	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1821	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1822	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1823	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1824
1825	/* HC only: */
1826
1827	/* RZ & R3: */
1828	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1829	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1830	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1831	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1832	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1833	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1834	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1835	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1836	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1837	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1838	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1839	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1840	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1841	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1842	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1843	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1844	PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1845	PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1846	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1847	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1848	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1849	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1850	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1851	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1852	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1853	PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1854	PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1855	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1856	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1857	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1858	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1859	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1860	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1861	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1862	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1863	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1864	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1865	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1866	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1867	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1868	PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1869	PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1870	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1871	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1872	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1873	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1874	PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1875
1876	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1877	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1878	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1879	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1880	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1881	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1882	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1883	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1884	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1885	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1886	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1887	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1888	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1889	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1890	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1891	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1892	PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1893	PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1894	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1895	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1896	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1897	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1898	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1899	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1900	PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1901	PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1902	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1903	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1904	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1905	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1906	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1907	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1908	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1909	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1910	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1911	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1912	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1913	PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1914	PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1915	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1916	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1917	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1918	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1919	PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1920	#endif /* VBOX_WITH_STATISTICS */
1921
1922	#undef PGM_REG_PROFILE
1923	#undef PGM_REG_COUNTER
1924
1925	}
1926	}
1927
1928
1929	/**
1930	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1931	*
1932	* The dynamic mapping area will also be allocated and initialized at this
1933	* time. We could allocate it during PGMR3Init of course, but the mapping
1934	* wouldn't be allocated at that time preventing us from setting up the
1935	* page table entries with the dummy page.
1936	*
1937	* @returns VBox status code.
1938	* @param pVM VM handle.
1939	*/
1940	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1941	{
1942	RTGCPTR GCPtr;
1943	int rc;
1944
1945	/*
1946	* Reserve space for the dynamic mappings.
1947	*/
1948	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1949	if (RT_SUCCESS(rc))
1950	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1951
1952	if ( RT_SUCCESS(rc)
1953	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1954	{
1955	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1956	if (RT_SUCCESS(rc))
1957	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1958	}
1959	if (RT_SUCCESS(rc))
1960	{
1961	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1962	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1963	}
1964	return rc;
1965	}
1966
1967
1968	/**
1969	* Ring-3 init finalizing.
1970	*
1971	* @returns VBox status code.
1972	* @param pVM The VM handle.
1973	*/
1974	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1975	{
1976	int rc;
1977
1978	/*
1979	* Reserve space for the dynamic mappings.
1980	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1981	*/
1982	/* get the pointer to the page table entries. */
1983	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1984	AssertRelease(pMapping);
1985	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1986	const unsigned iPT = off >> X86_PD_SHIFT;
1987	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1988	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1989	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1990
1991	/* init cache */
1992	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1993	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1994	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1995
1996	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1997	{
1998	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1999	AssertRCReturn(rc, rc);
2000	}
2001
2002	/*
2003	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2004	* Intel only goes up to 36 bits, so we stick to 36 as well.
2005	*/
2006	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
2007	uint32_t u32Dummy, u32Features;
2008	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2009
2010	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2011	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
2012	else
2013	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2014
2015	/*
2016	* Allocate memory if we're supposed to do that.
2017	*/
2018	if (pVM->pgm.s.fRamPreAlloc)
2019	rc = pgmR3PhysRamPreAllocate(pVM);
2020
2021	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2022	return rc;
2023	}
2024
2025
2026	/**
2027	* Applies relocations to data and code managed by this component.
2028	*
2029	* This function will be called at init and whenever the VMM need to relocate it
2030	* self inside the GC.
2031	*
2032	* @param pVM The VM.
2033	* @param offDelta Relocation delta relative to old location.
2034	*/
2035	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2036	{
2037	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2038
2039	/*
2040	* Paging stuff.
2041	*/
2042	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2043
2044	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2045
2046	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2047	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2048	{
2049	PVMCPU pVCpu = &pVM->aCpus[i];
2050
2051	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2052
2053	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2054	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2055	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2056	}
2057
2058	/*
2059	* Trees.
2060	*/
2061	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2062
2063	/*
2064	* Ram ranges.
2065	*/
2066	if (pVM->pgm.s.pRamRangesR3)
2067	{
2068	/* Update the pSelfRC pointers and relink them. */
2069	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2070	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2071	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2072	pgmR3PhysRelinkRamRanges(pVM);
2073	}
2074
2075	/*
2076	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2077	* be mapped and thus not included in the above exercise.
2078	*/
2079	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2080	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2081	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2082
2083	/*
2084	* Update the two page directories with all page table mappings.
2085	* (One or more of them have changed, that's why we're here.)
2086	*/
2087	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2088	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2089	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2090
2091	/* Relocate GC addresses of Page Tables. */
2092	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2093	{
2094	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2095	{
2096	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2097	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2098	}
2099	}
2100
2101	/*
2102	* Dynamic page mapping area.
2103	*/
2104	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2105	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2106	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2107
2108	/*
2109	* The Zero page.
2110	*/
2111	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2112	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2113	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2114	#else
2115	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2116	#endif
2117
2118	/*
2119	* Physical and virtual handlers.
2120	*/
2121	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2122	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2123	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2124
2125	/*
2126	* The page pool.
2127	*/
2128	pgmR3PoolRelocate(pVM);
2129	}
2130
2131
2132	/**
2133	* Callback function for relocating a physical access handler.
2134	*
2135	* @returns 0 (continue enum)
2136	* @param pNode Pointer to a PGMPHYSHANDLER node.
2137	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2138	* not certain the delta will fit in a void pointer for all possible configs.
2139	*/
2140	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2141	{
2142	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2143	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2144	if (pHandler->pfnHandlerRC)
2145	pHandler->pfnHandlerRC += offDelta;
2146	if (pHandler->pvUserRC >= 0x10000)
2147	pHandler->pvUserRC += offDelta;
2148	return 0;
2149	}
2150
2151
2152	/**
2153	* Callback function for relocating a virtual access handler.
2154	*
2155	* @returns 0 (continue enum)
2156	* @param pNode Pointer to a PGMVIRTHANDLER node.
2157	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2158	* not certain the delta will fit in a void pointer for all possible configs.
2159	*/
2160	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2161	{
2162	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2163	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2164	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2165	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2166	Assert(pHandler->pfnHandlerRC);
2167	pHandler->pfnHandlerRC += offDelta;
2168	return 0;
2169	}
2170
2171
2172	/**
2173	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2174	*
2175	* @returns 0 (continue enum)
2176	* @param pNode Pointer to a PGMVIRTHANDLER node.
2177	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2178	* not certain the delta will fit in a void pointer for all possible configs.
2179	*/
2180	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2181	{
2182	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2183	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2184	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2185	Assert(pHandler->pfnHandlerRC);
2186	pHandler->pfnHandlerRC += offDelta;
2187	return 0;
2188	}
2189
2190
2191	/**
2192	* Resets a virtual CPU when unplugged.
2193	*
2194	* @param pVM The VM handle.
2195	* @param pVCpu The virtual CPU handle.
2196	*/
2197	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2198	{
2199	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2200	AssertRC(rc);
2201
2202	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2203	AssertRC(rc);
2204
2205	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2206
2207	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2208
2209	/*
2210	* Re-init other members.
2211	*/
2212	pVCpu->pgm.s.fA20Enabled = true;
2213
2214	/*
2215	* Clear the FFs PGM owns.
2216	*/
2217	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2218	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2219	}
2220
2221
2222	/**
2223	* The VM is being reset.
2224	*
2225	* For the PGM component this means that any PD write monitors
2226	* needs to be removed.
2227	*
2228	* @param pVM VM handle.
2229	*/
2230	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2231	{
2232	int rc;
2233
2234	LogFlow(("PGMR3Reset:\n"));
2235	VM_ASSERT_EMT(pVM);
2236
2237	pgmLock(pVM);
2238
2239	/*
2240	* Unfix any fixed mappings and disable CR3 monitoring.
2241	*/
2242	pVM->pgm.s.fMappingsFixed = false;
2243	pVM->pgm.s.fMappingsFixedRestored = false;
2244	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2245	pVM->pgm.s.cbMappingFixed = 0;
2246
2247	/*
2248	* Exit the guest paging mode before the pgm pool gets reset.
2249	* Important to clean up the amd64 case.
2250	*/
2251	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2252	{
2253	PVMCPU pVCpu = &pVM->aCpus[i];
2254	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2255	AssertRC(rc);
2256	}
2257
2258	#ifdef DEBUG
2259	DBGFR3InfoLog(pVM, "mappings", NULL);
2260	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2261	#endif
2262
2263	/*
2264	* Switch mode back to real mode. (before resetting the pgm pool!)
2265	*/
2266	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2267	{
2268	PVMCPU pVCpu = &pVM->aCpus[i];
2269
2270	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2271	AssertRC(rc);
2272
2273	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2274	}
2275
2276	/*
2277	* Reset the shadow page pool.
2278	*/
2279	pgmR3PoolReset(pVM);
2280
2281	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2282	{
2283	PVMCPU pVCpu = &pVM->aCpus[i];
2284
2285	/*
2286	* Re-init other members.
2287	*/
2288	pVCpu->pgm.s.fA20Enabled = true;
2289
2290	/*
2291	* Clear the FFs PGM owns.
2292	*/
2293	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2294	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2295	}
2296
2297	/*
2298	* Reset (zero) RAM pages.
2299	*/
2300	rc = pgmR3PhysRamReset(pVM);
2301	if (RT_SUCCESS(rc))
2302	{
2303	/*
2304	* Reset (zero) shadow ROM pages.
2305	*/
2306	rc = pgmR3PhysRomReset(pVM);
2307	}
2308
2309	pgmUnlock(pVM);
2310	AssertReleaseRC(rc);
2311	}
2312
2313
2314	#ifdef VBOX_STRICT
2315	/**
2316	* VM state change callback for clearing fNoMorePhysWrites after
2317	* a snapshot has been created.
2318	*/
2319	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2320	{
2321	if ( enmState == VMSTATE_RUNNING
2322	\|\| enmState == VMSTATE_RESUMING)
2323	pVM->pgm.s.fNoMorePhysWrites = false;
2324	}
2325	#endif
2326
2327
2328	/**
2329	* Terminates the PGM.
2330	*
2331	* @returns VBox status code.
2332	* @param pVM Pointer to VM structure.
2333	*/
2334	VMMR3DECL(int) PGMR3Term(PVM pVM)
2335	{
2336	/* Must free shared pages here. */
2337	pgmLock(pVM);
2338	pgmR3PhysRamTerm(pVM);
2339	pgmUnlock(pVM);
2340
2341	PGMDeregisterStringFormatTypes();
2342	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2343	}
2344
2345
2346	/**
2347	* Terminates the per-VCPU PGM.
2348	*
2349	* Termination means cleaning up and freeing all resources,
2350	* the VM it self is at this point powered off or suspended.
2351	*
2352	* @returns VBox status code.
2353	* @param pVM The VM to operate on.
2354	*/
2355	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2356	{
2357	return 0;
2358	}
2359
2360
2361	/**
2362	* Show paging mode.
2363	*
2364	* @param pVM VM Handle.
2365	* @param pHlp The info helpers.
2366	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2367	*/
2368	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2369	{
2370	/* digest argument. */
2371	bool fGuest, fShadow, fHost;
2372	if (pszArgs)
2373	pszArgs = RTStrStripL(pszArgs);
2374	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2375	fShadow = fHost = fGuest = true;
2376	else
2377	{
2378	fShadow = fHost = fGuest = false;
2379	if (strstr(pszArgs, "guest"))
2380	fGuest = true;
2381	if (strstr(pszArgs, "shadow"))
2382	fShadow = true;
2383	if (strstr(pszArgs, "host"))
2384	fHost = true;
2385	}
2386
2387	/** @todo SMP support! */
2388	/* print info. */
2389	if (fGuest)
2390	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2391	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2392	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2393	if (fShadow)
2394	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2395	if (fHost)
2396	{
2397	const char *psz;
2398	switch (pVM->pgm.s.enmHostMode)
2399	{
2400	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2401	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2402	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2403	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2404	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2405	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2406	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2407	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2408	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2409	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2410	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2411	default: psz = "unknown"; break;
2412	}
2413	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2414	}
2415	}
2416
2417
2418	/**
2419	* Dump registered MMIO ranges to the log.
2420	*
2421	* @param pVM VM Handle.
2422	* @param pHlp The info helpers.
2423	* @param pszArgs Arguments, ignored.
2424	*/
2425	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2426	{
2427	NOREF(pszArgs);
2428	pHlp->pfnPrintf(pHlp,
2429	"RAM ranges (pVM=%p)\n"
2430	"%.s %.s\n",
2431	pVM,
2432	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2433	sizeof(RTHCPTR) * 2, "pvHC ");
2434
2435	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2436	pHlp->pfnPrintf(pHlp,
2437	"%RGp-%RGp %RHv %s\n",
2438	pCur->GCPhys,
2439	pCur->GCPhysLast,
2440	pCur->pvR3,
2441	pCur->pszDesc);
2442	}
2443
2444	/**
2445	* Dump the page directory to the log.
2446	*
2447	* @param pVM VM Handle.
2448	* @param pHlp The info helpers.
2449	* @param pszArgs Arguments, ignored.
2450	*/
2451	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2452	{
2453	/** @todo SMP support!! */
2454	PVMCPU pVCpu = &pVM->aCpus[0];
2455
2456	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2457	/* Big pages supported? */
2458	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2459
2460	/* Global pages supported? */
2461	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2462
2463	NOREF(pszArgs);
2464
2465	/*
2466	* Get page directory addresses.
2467	*/
2468	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2469	Assert(pPDSrc);
2470	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2471
2472	/*
2473	* Iterate the page directory.
2474	*/
2475	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2476	{
2477	X86PDE PdeSrc = pPDSrc->a[iPD];
2478	if (PdeSrc.n.u1Present)
2479	{
2480	if (PdeSrc.b.u1Size && fPSE)
2481	pHlp->pfnPrintf(pHlp,
2482	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2483	iPD,
2484	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2485	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2486	else
2487	pHlp->pfnPrintf(pHlp,
2488	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2489	iPD,
2490	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2491	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2492	}
2493	}
2494	}
2495
2496
2497	/**
2498	* Service a VMMCALLRING3_PGM_LOCK call.
2499	*
2500	* @returns VBox status code.
2501	* @param pVM The VM handle.
2502	*/
2503	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2504	{
2505	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2506	AssertRC(rc);
2507	return rc;
2508	}
2509
2510
2511	/**
2512	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2513	*
2514	* @returns PGM_TYPE_*.
2515	* @param pgmMode The mode value to convert.
2516	*/
2517	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2518	{
2519	switch (pgmMode)
2520	{
2521	case PGMMODE_REAL: return PGM_TYPE_REAL;
2522	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2523	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2524	case PGMMODE_PAE:
2525	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2526	case PGMMODE_AMD64:
2527	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2528	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2529	case PGMMODE_EPT: return PGM_TYPE_EPT;
2530	default:
2531	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2532	}
2533	}
2534
2535
2536	/**
2537	* Gets the index into the paging mode data array of a SHW+GST mode.
2538	*
2539	* @returns PGM::paPagingData index.
2540	* @param uShwType The shadow paging mode type.
2541	* @param uGstType The guest paging mode type.
2542	*/
2543	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2544	{
2545	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2546	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2547	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2548	+ (uGstType - PGM_TYPE_REAL);
2549	}
2550
2551
2552	/**
2553	* Gets the index into the paging mode data array of a SHW+GST mode.
2554	*
2555	* @returns PGM::paPagingData index.
2556	* @param enmShw The shadow paging mode.
2557	* @param enmGst The guest paging mode.
2558	*/
2559	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2560	{
2561	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2562	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2563	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2564	}
2565
2566
2567	/**
2568	* Calculates the max data index.
2569	* @returns The number of entries in the paging data array.
2570	*/
2571	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2572	{
2573	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2574	}
2575
2576
2577	/**
2578	* Initializes the paging mode data kept in PGM::paModeData.
2579	*
2580	* @param pVM The VM handle.
2581	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2582	* This is used early in the init process to avoid trouble with PDM
2583	* not being initialized yet.
2584	*/
2585	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2586	{
2587	PPGMMODEDATA pModeData;
2588	int rc;
2589
2590	/*
2591	* Allocate the array on the first call.
2592	*/
2593	if (!pVM->pgm.s.paModeData)
2594	{
2595	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2596	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2597	}
2598
2599	/*
2600	* Initialize the array entries.
2601	*/
2602	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2603	pModeData->uShwType = PGM_TYPE_32BIT;
2604	pModeData->uGstType = PGM_TYPE_REAL;
2605	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2606	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2607	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2608
2609	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2610	pModeData->uShwType = PGM_TYPE_32BIT;
2611	pModeData->uGstType = PGM_TYPE_PROT;
2612	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2613	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2614	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2615
2616	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2617	pModeData->uShwType = PGM_TYPE_32BIT;
2618	pModeData->uGstType = PGM_TYPE_32BIT;
2619	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2620	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2621	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2622
2623	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2624	pModeData->uShwType = PGM_TYPE_PAE;
2625	pModeData->uGstType = PGM_TYPE_REAL;
2626	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2627	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2628	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2629
2630	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2631	pModeData->uShwType = PGM_TYPE_PAE;
2632	pModeData->uGstType = PGM_TYPE_PROT;
2633	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2634	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2635	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2636
2637	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2638	pModeData->uShwType = PGM_TYPE_PAE;
2639	pModeData->uGstType = PGM_TYPE_32BIT;
2640	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2641	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2642	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2643
2644	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2645	pModeData->uShwType = PGM_TYPE_PAE;
2646	pModeData->uGstType = PGM_TYPE_PAE;
2647	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2648	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2649	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2650
2651	#ifdef VBOX_WITH_64_BITS_GUESTS
2652	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2653	pModeData->uShwType = PGM_TYPE_AMD64;
2654	pModeData->uGstType = PGM_TYPE_AMD64;
2655	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2656	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2657	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2658	#endif
2659
2660	/* The nested paging mode. */
2661	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2662	pModeData->uShwType = PGM_TYPE_NESTED;
2663	pModeData->uGstType = PGM_TYPE_REAL;
2664	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2665	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2666
2667	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2668	pModeData->uShwType = PGM_TYPE_NESTED;
2669	pModeData->uGstType = PGM_TYPE_PROT;
2670	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2671	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2672
2673	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2674	pModeData->uShwType = PGM_TYPE_NESTED;
2675	pModeData->uGstType = PGM_TYPE_32BIT;
2676	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2677	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678
2679	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2680	pModeData->uShwType = PGM_TYPE_NESTED;
2681	pModeData->uGstType = PGM_TYPE_PAE;
2682	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2683	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2684
2685	#ifdef VBOX_WITH_64_BITS_GUESTS
2686	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2687	pModeData->uShwType = PGM_TYPE_NESTED;
2688	pModeData->uGstType = PGM_TYPE_AMD64;
2689	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2690	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2691	#endif
2692
2693	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2694	switch (pVM->pgm.s.enmHostMode)
2695	{
2696	#if HC_ARCH_BITS == 32
2697	case SUPPAGINGMODE_32_BIT:
2698	case SUPPAGINGMODE_32_BIT_GLOBAL:
2699	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2700	{
2701	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2702	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703	}
2704	# ifdef VBOX_WITH_64_BITS_GUESTS
2705	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2706	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707	# endif
2708	break;
2709
2710	case SUPPAGINGMODE_PAE:
2711	case SUPPAGINGMODE_PAE_NX:
2712	case SUPPAGINGMODE_PAE_GLOBAL:
2713	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2714	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2715	{
2716	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2717	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718	}
2719	# ifdef VBOX_WITH_64_BITS_GUESTS
2720	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2721	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722	# endif
2723	break;
2724	#endif /* HC_ARCH_BITS == 32 */
2725
2726	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2727	case SUPPAGINGMODE_AMD64:
2728	case SUPPAGINGMODE_AMD64_GLOBAL:
2729	case SUPPAGINGMODE_AMD64_NX:
2730	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2731	# ifdef VBOX_WITH_64_BITS_GUESTS
2732	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2733	# else
2734	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2735	# endif
2736	{
2737	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2738	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739	}
2740	break;
2741	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2742
2743	default:
2744	AssertFailed();
2745	break;
2746	}
2747
2748	/* Extended paging (EPT) / Intel VT-x */
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2750	pModeData->uShwType = PGM_TYPE_EPT;
2751	pModeData->uGstType = PGM_TYPE_REAL;
2752	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755
2756	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2757	pModeData->uShwType = PGM_TYPE_EPT;
2758	pModeData->uGstType = PGM_TYPE_PROT;
2759	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762
2763	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2764	pModeData->uShwType = PGM_TYPE_EPT;
2765	pModeData->uGstType = PGM_TYPE_32BIT;
2766	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769
2770	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2771	pModeData->uShwType = PGM_TYPE_EPT;
2772	pModeData->uGstType = PGM_TYPE_PAE;
2773	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776
2777	#ifdef VBOX_WITH_64_BITS_GUESTS
2778	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2779	pModeData->uShwType = PGM_TYPE_EPT;
2780	pModeData->uGstType = PGM_TYPE_AMD64;
2781	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784	#endif
2785	return VINF_SUCCESS;
2786	}
2787
2788
2789	/**
2790	* Switch to different (or relocated in the relocate case) mode data.
2791	*
2792	* @param pVM The VM handle.
2793	* @param pVCpu The VMCPU to operate on.
2794	* @param enmShw The the shadow paging mode.
2795	* @param enmGst The the guest paging mode.
2796	*/
2797	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2798	{
2799	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2800
2801	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2802	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2803
2804	/* shadow */
2805	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2806	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2807	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2808	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2809	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2810
2811	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2812	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2813
2814	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2815	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2816
2817
2818	/* guest */
2819	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2820	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2821	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2822	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2823	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2824	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2825	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2826	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2827	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2828	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2829	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2830	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2831
2832	/* both */
2833	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2834	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2835	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2836	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2837	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2838	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2839	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2840	#ifdef VBOX_STRICT
2841	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2842	#endif
2843	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2844	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2845
2846	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2847	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2848	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2849	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2850	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2851	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2852	#ifdef VBOX_STRICT
2853	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2854	#endif
2855	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2856	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2857
2858	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2859	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2860	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2861	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2862	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2863	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2864	#ifdef VBOX_STRICT
2865	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2866	#endif
2867	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2868	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2869	}
2870
2871
2872	/**
2873	* Calculates the shadow paging mode.
2874	*
2875	* @returns The shadow paging mode.
2876	* @param pVM VM handle.
2877	* @param enmGuestMode The guest mode.
2878	* @param enmHostMode The host mode.
2879	* @param enmShadowMode The current shadow mode.
2880	* @param penmSwitcher Where to store the switcher to use.
2881	* VMMSWITCHER_INVALID means no change.
2882	*/
2883	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2884	{
2885	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2886	switch (enmGuestMode)
2887	{
2888	/*
2889	* When switching to real or protected mode we don't change
2890	* anything since it's likely that we'll switch back pretty soon.
2891	*
2892	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2893	* and is supposed to determine which shadow paging and switcher to
2894	* use during init.
2895	*/
2896	case PGMMODE_REAL:
2897	case PGMMODE_PROTECTED:
2898	if ( enmShadowMode != PGMMODE_INVALID
2899	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2900	break; /* (no change) */
2901
2902	switch (enmHostMode)
2903	{
2904	case SUPPAGINGMODE_32_BIT:
2905	case SUPPAGINGMODE_32_BIT_GLOBAL:
2906	enmShadowMode = PGMMODE_32_BIT;
2907	enmSwitcher = VMMSWITCHER_32_TO_32;
2908	break;
2909
2910	case SUPPAGINGMODE_PAE:
2911	case SUPPAGINGMODE_PAE_NX:
2912	case SUPPAGINGMODE_PAE_GLOBAL:
2913	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2914	enmShadowMode = PGMMODE_PAE;
2915	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2916	#ifdef DEBUG_bird
2917	if (RTEnvExist("VBOX_32BIT"))
2918	{
2919	enmShadowMode = PGMMODE_32_BIT;
2920	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2921	}
2922	#endif
2923	break;
2924
2925	case SUPPAGINGMODE_AMD64:
2926	case SUPPAGINGMODE_AMD64_GLOBAL:
2927	case SUPPAGINGMODE_AMD64_NX:
2928	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2929	enmShadowMode = PGMMODE_PAE;
2930	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2931	#ifdef DEBUG_bird
2932	if (RTEnvExist("VBOX_32BIT"))
2933	{
2934	enmShadowMode = PGMMODE_32_BIT;
2935	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2936	}
2937	#endif
2938	break;
2939
2940	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2941	}
2942	break;
2943
2944	case PGMMODE_32_BIT:
2945	switch (enmHostMode)
2946	{
2947	case SUPPAGINGMODE_32_BIT:
2948	case SUPPAGINGMODE_32_BIT_GLOBAL:
2949	enmShadowMode = PGMMODE_32_BIT;
2950	enmSwitcher = VMMSWITCHER_32_TO_32;
2951	break;
2952
2953	case SUPPAGINGMODE_PAE:
2954	case SUPPAGINGMODE_PAE_NX:
2955	case SUPPAGINGMODE_PAE_GLOBAL:
2956	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2957	enmShadowMode = PGMMODE_PAE;
2958	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2959	#ifdef DEBUG_bird
2960	if (RTEnvExist("VBOX_32BIT"))
2961	{
2962	enmShadowMode = PGMMODE_32_BIT;
2963	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2964	}
2965	#endif
2966	break;
2967
2968	case SUPPAGINGMODE_AMD64:
2969	case SUPPAGINGMODE_AMD64_GLOBAL:
2970	case SUPPAGINGMODE_AMD64_NX:
2971	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2972	enmShadowMode = PGMMODE_PAE;
2973	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2974	#ifdef DEBUG_bird
2975	if (RTEnvExist("VBOX_32BIT"))
2976	{
2977	enmShadowMode = PGMMODE_32_BIT;
2978	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2979	}
2980	#endif
2981	break;
2982
2983	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2984	}
2985	break;
2986
2987	case PGMMODE_PAE:
2988	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2989	switch (enmHostMode)
2990	{
2991	case SUPPAGINGMODE_32_BIT:
2992	case SUPPAGINGMODE_32_BIT_GLOBAL:
2993	enmShadowMode = PGMMODE_PAE;
2994	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2995	break;
2996
2997	case SUPPAGINGMODE_PAE:
2998	case SUPPAGINGMODE_PAE_NX:
2999	case SUPPAGINGMODE_PAE_GLOBAL:
3000	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3001	enmShadowMode = PGMMODE_PAE;
3002	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3003	break;
3004
3005	case SUPPAGINGMODE_AMD64:
3006	case SUPPAGINGMODE_AMD64_GLOBAL:
3007	case SUPPAGINGMODE_AMD64_NX:
3008	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3009	enmShadowMode = PGMMODE_PAE;
3010	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3011	break;
3012
3013	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3014	}
3015	break;
3016
3017	case PGMMODE_AMD64:
3018	case PGMMODE_AMD64_NX:
3019	switch (enmHostMode)
3020	{
3021	case SUPPAGINGMODE_32_BIT:
3022	case SUPPAGINGMODE_32_BIT_GLOBAL:
3023	enmShadowMode = PGMMODE_AMD64;
3024	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3025	break;
3026
3027	case SUPPAGINGMODE_PAE:
3028	case SUPPAGINGMODE_PAE_NX:
3029	case SUPPAGINGMODE_PAE_GLOBAL:
3030	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3031	enmShadowMode = PGMMODE_AMD64;
3032	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3033	break;
3034
3035	case SUPPAGINGMODE_AMD64:
3036	case SUPPAGINGMODE_AMD64_GLOBAL:
3037	case SUPPAGINGMODE_AMD64_NX:
3038	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3039	enmShadowMode = PGMMODE_AMD64;
3040	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3041	break;
3042
3043	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3044	}
3045	break;
3046
3047
3048	default:
3049	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3050	*penmSwitcher = VMMSWITCHER_INVALID;
3051	return PGMMODE_INVALID;
3052	}
3053	/* Override the shadow mode is nested paging is active. */
3054	if (HWACCMIsNestedPagingActive(pVM))
3055	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3056
3057	*penmSwitcher = enmSwitcher;
3058	return enmShadowMode;
3059	}
3060
3061
3062	/**
3063	* Performs the actual mode change.
3064	* This is called by PGMChangeMode and pgmR3InitPaging().
3065	*
3066	* @returns VBox status code. May suspend or power off the VM on error, but this
3067	* will trigger using FFs and not status codes.
3068	*
3069	* @param pVM VM handle.
3070	* @param pVCpu The VMCPU to operate on.
3071	* @param enmGuestMode The new guest mode. This is assumed to be different from
3072	* the current mode.
3073	*/
3074	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3075	{
3076	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3077	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3078
3079	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3080	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3081
3082	/*
3083	* Calc the shadow mode and switcher.
3084	*/
3085	VMMSWITCHER enmSwitcher;
3086	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3087
3088	#ifdef VBOX_WITH_RAW_MODE
3089	if (enmSwitcher != VMMSWITCHER_INVALID)
3090	{
3091	/*
3092	* Select new switcher.
3093	*/
3094	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3095	if (RT_FAILURE(rc))
3096	{
3097	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3098	return rc;
3099	}
3100	}
3101	#endif
3102
3103	/*
3104	* Exit old mode(s).
3105	*/
3106	#if HC_ARCH_BITS == 32
3107	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3108	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3109	&& enmShadowMode == PGMMODE_NESTED);
3110	#else
3111	const bool fForceShwEnterExit = false;
3112	#endif
3113	/* shadow */
3114	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3115	\|\| fForceShwEnterExit)
3116	{
3117	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3118	if (PGM_SHW_PFN(Exit, pVCpu))
3119	{
3120	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3121	if (RT_FAILURE(rc))
3122	{
3123	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3124	return rc;
3125	}
3126	}
3127
3128	}
3129	else
3130	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3131
3132	/* guest */
3133	if (PGM_GST_PFN(Exit, pVCpu))
3134	{
3135	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3136	if (RT_FAILURE(rc))
3137	{
3138	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3139	return rc;
3140	}
3141	}
3142
3143	/*
3144	* Load new paging mode data.
3145	*/
3146	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3147
3148	/*
3149	* Enter new shadow mode (if changed).
3150	*/
3151	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3152	\|\| fForceShwEnterExit)
3153	{
3154	int rc;
3155	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3156	switch (enmShadowMode)
3157	{
3158	case PGMMODE_32_BIT:
3159	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3160	break;
3161	case PGMMODE_PAE:
3162	case PGMMODE_PAE_NX:
3163	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3164	break;
3165	case PGMMODE_AMD64:
3166	case PGMMODE_AMD64_NX:
3167	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3168	break;
3169	case PGMMODE_NESTED:
3170	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3171	break;
3172	case PGMMODE_EPT:
3173	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3174	break;
3175	case PGMMODE_REAL:
3176	case PGMMODE_PROTECTED:
3177	default:
3178	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3179	return VERR_INTERNAL_ERROR;
3180	}
3181	if (RT_FAILURE(rc))
3182	{
3183	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3184	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3185	return rc;
3186	}
3187	}
3188
3189	/*
3190	* Always flag the necessary updates
3191	*/
3192	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3193
3194	/*
3195	* Enter the new guest and shadow+guest modes.
3196	*/
3197	int rc = -1;
3198	int rc2 = -1;
3199	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3200	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3201	switch (enmGuestMode)
3202	{
3203	case PGMMODE_REAL:
3204	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3205	switch (pVCpu->pgm.s.enmShadowMode)
3206	{
3207	case PGMMODE_32_BIT:
3208	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3209	break;
3210	case PGMMODE_PAE:
3211	case PGMMODE_PAE_NX:
3212	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3213	break;
3214	case PGMMODE_NESTED:
3215	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3216	break;
3217	case PGMMODE_EPT:
3218	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3219	break;
3220	case PGMMODE_AMD64:
3221	case PGMMODE_AMD64_NX:
3222	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3223	default: AssertFailed(); break;
3224	}
3225	break;
3226
3227	case PGMMODE_PROTECTED:
3228	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3229	switch (pVCpu->pgm.s.enmShadowMode)
3230	{
3231	case PGMMODE_32_BIT:
3232	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3233	break;
3234	case PGMMODE_PAE:
3235	case PGMMODE_PAE_NX:
3236	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3237	break;
3238	case PGMMODE_NESTED:
3239	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3240	break;
3241	case PGMMODE_EPT:
3242	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3243	break;
3244	case PGMMODE_AMD64:
3245	case PGMMODE_AMD64_NX:
3246	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3247	default: AssertFailed(); break;
3248	}
3249	break;
3250
3251	case PGMMODE_32_BIT:
3252	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3253	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3254	switch (pVCpu->pgm.s.enmShadowMode)
3255	{
3256	case PGMMODE_32_BIT:
3257	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3258	break;
3259	case PGMMODE_PAE:
3260	case PGMMODE_PAE_NX:
3261	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3262	break;
3263	case PGMMODE_NESTED:
3264	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3265	break;
3266	case PGMMODE_EPT:
3267	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3268	break;
3269	case PGMMODE_AMD64:
3270	case PGMMODE_AMD64_NX:
3271	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3272	default: AssertFailed(); break;
3273	}
3274	break;
3275
3276	case PGMMODE_PAE_NX:
3277	case PGMMODE_PAE:
3278	{
3279	uint32_t u32Dummy, u32Features;
3280
3281	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3282	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3283	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3284	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3285
3286	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3287	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3288	switch (pVCpu->pgm.s.enmShadowMode)
3289	{
3290	case PGMMODE_PAE:
3291	case PGMMODE_PAE_NX:
3292	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3293	break;
3294	case PGMMODE_NESTED:
3295	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3296	break;
3297	case PGMMODE_EPT:
3298	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3299	break;
3300	case PGMMODE_32_BIT:
3301	case PGMMODE_AMD64:
3302	case PGMMODE_AMD64_NX:
3303	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3304	default: AssertFailed(); break;
3305	}
3306	break;
3307	}
3308
3309	#ifdef VBOX_WITH_64_BITS_GUESTS
3310	case PGMMODE_AMD64_NX:
3311	case PGMMODE_AMD64:
3312	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3313	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3314	switch (pVCpu->pgm.s.enmShadowMode)
3315	{
3316	case PGMMODE_AMD64:
3317	case PGMMODE_AMD64_NX:
3318	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3319	break;
3320	case PGMMODE_NESTED:
3321	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3322	break;
3323	case PGMMODE_EPT:
3324	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3325	break;
3326	case PGMMODE_32_BIT:
3327	case PGMMODE_PAE:
3328	case PGMMODE_PAE_NX:
3329	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3330	default: AssertFailed(); break;
3331	}
3332	break;
3333	#endif
3334
3335	default:
3336	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3337	rc = VERR_NOT_IMPLEMENTED;
3338	break;
3339	}
3340
3341	/* status codes. */
3342	AssertRC(rc);
3343	AssertRC(rc2);
3344	if (RT_SUCCESS(rc))
3345	{
3346	rc = rc2;
3347	if (RT_SUCCESS(rc)) /* no informational status codes. */
3348	rc = VINF_SUCCESS;
3349	}
3350
3351	/* Notify HWACCM as well. */
3352	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3353	return rc;
3354	}
3355
3356
3357	/**
3358	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3359	*
3360	* @returns VBox status code, fully asserted.
3361	* @param pVM The VM handle.
3362	* @param pVCpu The VMCPU to operate on.
3363	*/
3364	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3365	{
3366	/* Unmap the old CR3 value before flushing everything. */
3367	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3368	AssertRC(rc);
3369
3370	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3371	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3372	AssertRC(rc);
3373	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3374	return rc;
3375	}
3376
3377
3378	/**
3379	* Called by pgmPoolFlushAllInt after flushing the pool.
3380	*
3381	* @returns VBox status code, fully asserted.
3382	* @param pVM The VM handle.
3383	* @param pVCpu The VMCPU to operate on.
3384	*/
3385	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3386	{
3387	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3388	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3389	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3390	AssertRCReturn(rc, rc);
3391	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3392
3393	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3394	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3395	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3396	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3397	return rc;
3398	}
3399
3400
3401	/**
3402	* Dumps a PAE shadow page table.
3403	*
3404	* @returns VBox status code (VINF_SUCCESS).
3405	* @param pVM The VM handle.
3406	* @param pPT Pointer to the page table.
3407	* @param u64Address The virtual address of the page table starts.
3408	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3409	* @param cMaxDepth The maxium depth.
3410	* @param pHlp Pointer to the output functions.
3411	*/
3412	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3413	{
3414	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3415	{
3416	X86PTEPAE Pte = pPT->a[i];
3417	if (Pte.n.u1Present)
3418	{
3419	pHlp->pfnPrintf(pHlp,
3420	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3421	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3422	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3423	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3424	Pte.n.u1Write ? 'W' : 'R',
3425	Pte.n.u1User ? 'U' : 'S',
3426	Pte.n.u1Accessed ? 'A' : '-',
3427	Pte.n.u1Dirty ? 'D' : '-',
3428	Pte.n.u1Global ? 'G' : '-',
3429	Pte.n.u1WriteThru ? "WT" : "--",
3430	Pte.n.u1CacheDisable? "CD" : "--",
3431	Pte.n.u1PAT ? "AT" : "--",
3432	Pte.n.u1NoExecute ? "NX" : "--",
3433	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3434	Pte.u & RT_BIT(10) ? '1' : '0',
3435	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3436	Pte.u & X86_PTE_PAE_PG_MASK);
3437	}
3438	}
3439	return VINF_SUCCESS;
3440	}
3441
3442
3443	/**
3444	* Dumps a PAE shadow page directory table.
3445	*
3446	* @returns VBox status code (VINF_SUCCESS).
3447	* @param pVM The VM handle.
3448	* @param HCPhys The physical address of the page directory table.
3449	* @param u64Address The virtual address of the page table starts.
3450	* @param cr4 The CR4, PSE is currently used.
3451	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3452	* @param cMaxDepth The maxium depth.
3453	* @param pHlp Pointer to the output functions.
3454	*/
3455	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3456	{
3457	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3458	if (!pPD)
3459	{
3460	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3461	fLongMode ? 16 : 8, u64Address, HCPhys);
3462	return VERR_INVALID_PARAMETER;
3463	}
3464	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3465
3466	int rc = VINF_SUCCESS;
3467	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3468	{
3469	X86PDEPAE Pde = pPD->a[i];
3470	if (Pde.n.u1Present)
3471	{
3472	if (fBigPagesSupported && Pde.b.u1Size)
3473	pHlp->pfnPrintf(pHlp,
3474	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3475	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3476	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3477	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3478	Pde.b.u1Write ? 'W' : 'R',
3479	Pde.b.u1User ? 'U' : 'S',
3480	Pde.b.u1Accessed ? 'A' : '-',
3481	Pde.b.u1Dirty ? 'D' : '-',
3482	Pde.b.u1Global ? 'G' : '-',
3483	Pde.b.u1WriteThru ? "WT" : "--",
3484	Pde.b.u1CacheDisable? "CD" : "--",
3485	Pde.b.u1PAT ? "AT" : "--",
3486	Pde.b.u1NoExecute ? "NX" : "--",
3487	Pde.u & RT_BIT_64(9) ? '1' : '0',
3488	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3489	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3490	Pde.u & X86_PDE_PAE_PG_MASK);
3491	else
3492	{
3493	pHlp->pfnPrintf(pHlp,
3494	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3495	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3496	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3497	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3498	Pde.n.u1Write ? 'W' : 'R',
3499	Pde.n.u1User ? 'U' : 'S',
3500	Pde.n.u1Accessed ? 'A' : '-',
3501	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3502	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3503	Pde.n.u1WriteThru ? "WT" : "--",
3504	Pde.n.u1CacheDisable? "CD" : "--",
3505	Pde.n.u1NoExecute ? "NX" : "--",
3506	Pde.u & RT_BIT_64(9) ? '1' : '0',
3507	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3508	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3509	Pde.u & X86_PDE_PAE_PG_MASK);
3510	if (cMaxDepth >= 1)
3511	{
3512	/** @todo what about using the page pool for mapping PTs? */
3513	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3514	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3515	PX86PTPAE pPT = NULL;
3516	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3517	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3518	else
3519	{
3520	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3521	{
3522	uint64_t off = u64AddressPT - pMap->GCPtr;
3523	if (off < pMap->cb)
3524	{
3525	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3526	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3527	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3528	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3529	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3530	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3531	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3532	}
3533	}
3534	}
3535	int rc2 = VERR_INVALID_PARAMETER;
3536	if (pPT)
3537	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3538	else
3539	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3540	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3541	if (rc2 < rc && RT_SUCCESS(rc))
3542	rc = rc2;
3543	}
3544	}
3545	}
3546	}
3547	return rc;
3548	}
3549
3550
3551	/**
3552	* Dumps a PAE shadow page directory pointer table.
3553	*
3554	* @returns VBox status code (VINF_SUCCESS).
3555	* @param pVM The VM handle.
3556	* @param HCPhys The physical address of the page directory pointer table.
3557	* @param u64Address The virtual address of the page table starts.
3558	* @param cr4 The CR4, PSE is currently used.
3559	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3560	* @param cMaxDepth The maxium depth.
3561	* @param pHlp Pointer to the output functions.
3562	*/
3563	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3564	{
3565	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3566	if (!pPDPT)
3567	{
3568	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3569	fLongMode ? 16 : 8, u64Address, HCPhys);
3570	return VERR_INVALID_PARAMETER;
3571	}
3572
3573	int rc = VINF_SUCCESS;
3574	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3575	for (unsigned i = 0; i < c; i++)
3576	{
3577	X86PDPE Pdpe = pPDPT->a[i];
3578	if (Pdpe.n.u1Present)
3579	{
3580	if (fLongMode)
3581	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3582	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3583	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3584	Pdpe.lm.u1Write ? 'W' : 'R',
3585	Pdpe.lm.u1User ? 'U' : 'S',
3586	Pdpe.lm.u1Accessed ? 'A' : '-',
3587	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3588	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3589	Pdpe.lm.u1WriteThru ? "WT" : "--",
3590	Pdpe.lm.u1CacheDisable? "CD" : "--",
3591	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3592	Pdpe.lm.u1NoExecute ? "NX" : "--",
3593	Pdpe.u & RT_BIT(9) ? '1' : '0',
3594	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3595	Pdpe.u & RT_BIT(11) ? '1' : '0',
3596	Pdpe.u & X86_PDPE_PG_MASK);
3597	else
3598	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3599	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3600	i << X86_PDPT_SHIFT,
3601	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3602	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3603	Pdpe.n.u1WriteThru ? "WT" : "--",
3604	Pdpe.n.u1CacheDisable? "CD" : "--",
3605	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3606	Pdpe.u & RT_BIT(9) ? '1' : '0',
3607	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3608	Pdpe.u & RT_BIT(11) ? '1' : '0',
3609	Pdpe.u & X86_PDPE_PG_MASK);
3610	if (cMaxDepth >= 1)
3611	{
3612	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3613	cr4, fLongMode, cMaxDepth - 1, pHlp);
3614	if (rc2 < rc && RT_SUCCESS(rc))
3615	rc = rc2;
3616	}
3617	}
3618	}
3619	return rc;
3620	}
3621
3622
3623	/**
3624	* Dumps a 32-bit shadow page table.
3625	*
3626	* @returns VBox status code (VINF_SUCCESS).
3627	* @param pVM The VM handle.
3628	* @param HCPhys The physical address of the table.
3629	* @param cr4 The CR4, PSE is currently used.
3630	* @param cMaxDepth The maxium depth.
3631	* @param pHlp Pointer to the output functions.
3632	*/
3633	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3634	{
3635	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3636	if (!pPML4)
3637	{
3638	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3639	return VERR_INVALID_PARAMETER;
3640	}
3641
3642	int rc = VINF_SUCCESS;
3643	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3644	{
3645	X86PML4E Pml4e = pPML4->a[i];
3646	if (Pml4e.n.u1Present)
3647	{
3648	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3649	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3650	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3651	u64Address,
3652	Pml4e.n.u1Write ? 'W' : 'R',
3653	Pml4e.n.u1User ? 'U' : 'S',
3654	Pml4e.n.u1Accessed ? 'A' : '-',
3655	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3656	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3657	Pml4e.n.u1WriteThru ? "WT" : "--",
3658	Pml4e.n.u1CacheDisable? "CD" : "--",
3659	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3660	Pml4e.n.u1NoExecute ? "NX" : "--",
3661	Pml4e.u & RT_BIT(9) ? '1' : '0',
3662	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3663	Pml4e.u & RT_BIT(11) ? '1' : '0',
3664	Pml4e.u & X86_PML4E_PG_MASK);
3665
3666	if (cMaxDepth >= 1)
3667	{
3668	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3669	if (rc2 < rc && RT_SUCCESS(rc))
3670	rc = rc2;
3671	}
3672	}
3673	}
3674	return rc;
3675	}
3676
3677
3678	/**
3679	* Dumps a 32-bit shadow page table.
3680	*
3681	* @returns VBox status code (VINF_SUCCESS).
3682	* @param pVM The VM handle.
3683	* @param pPT Pointer to the page table.
3684	* @param u32Address The virtual address this table starts at.
3685	* @param pHlp Pointer to the output functions.
3686	*/
3687	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3688	{
3689	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3690	{
3691	X86PTE Pte = pPT->a[i];
3692	if (Pte.n.u1Present)
3693	{
3694	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3695	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3696	u32Address + (i << X86_PT_SHIFT),
3697	Pte.n.u1Write ? 'W' : 'R',
3698	Pte.n.u1User ? 'U' : 'S',
3699	Pte.n.u1Accessed ? 'A' : '-',
3700	Pte.n.u1Dirty ? 'D' : '-',
3701	Pte.n.u1Global ? 'G' : '-',
3702	Pte.n.u1WriteThru ? "WT" : "--",
3703	Pte.n.u1CacheDisable? "CD" : "--",
3704	Pte.n.u1PAT ? "AT" : "--",
3705	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3706	Pte.u & RT_BIT(10) ? '1' : '0',
3707	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3708	Pte.u & X86_PDE_PG_MASK);
3709	}
3710	}
3711	return VINF_SUCCESS;
3712	}
3713
3714
3715	/**
3716	* Dumps a 32-bit shadow page directory and page tables.
3717	*
3718	* @returns VBox status code (VINF_SUCCESS).
3719	* @param pVM The VM handle.
3720	* @param cr3 The root of the hierarchy.
3721	* @param cr4 The CR4, PSE is currently used.
3722	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3723	* @param pHlp Pointer to the output functions.
3724	*/
3725	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3726	{
3727	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3728	if (!pPD)
3729	{
3730	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3731	return VERR_INVALID_PARAMETER;
3732	}
3733
3734	int rc = VINF_SUCCESS;
3735	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3736	{
3737	X86PDE Pde = pPD->a[i];
3738	if (Pde.n.u1Present)
3739	{
3740	const uint32_t u32Address = i << X86_PD_SHIFT;
3741	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3742	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3743	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3744	u32Address,
3745	Pde.b.u1Write ? 'W' : 'R',
3746	Pde.b.u1User ? 'U' : 'S',
3747	Pde.b.u1Accessed ? 'A' : '-',
3748	Pde.b.u1Dirty ? 'D' : '-',
3749	Pde.b.u1Global ? 'G' : '-',
3750	Pde.b.u1WriteThru ? "WT" : "--",
3751	Pde.b.u1CacheDisable? "CD" : "--",
3752	Pde.b.u1PAT ? "AT" : "--",
3753	Pde.u & RT_BIT_64(9) ? '1' : '0',
3754	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3755	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3756	Pde.u & X86_PDE4M_PG_MASK);
3757	else
3758	{
3759	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3760	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3761	u32Address,
3762	Pde.n.u1Write ? 'W' : 'R',
3763	Pde.n.u1User ? 'U' : 'S',
3764	Pde.n.u1Accessed ? 'A' : '-',
3765	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3766	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3767	Pde.n.u1WriteThru ? "WT" : "--",
3768	Pde.n.u1CacheDisable? "CD" : "--",
3769	Pde.u & RT_BIT_64(9) ? '1' : '0',
3770	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3771	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3772	Pde.u & X86_PDE_PG_MASK);
3773	if (cMaxDepth >= 1)
3774	{
3775	/** @todo what about using the page pool for mapping PTs? */
3776	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3777	PX86PT pPT = NULL;
3778	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3779	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3780	else
3781	{
3782	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3783	if (u32Address - pMap->GCPtr < pMap->cb)
3784	{
3785	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3786	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3787	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3788	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3789	pPT = pMap->aPTs[iPDE].pPTR3;
3790	}
3791	}
3792	int rc2 = VERR_INVALID_PARAMETER;
3793	if (pPT)
3794	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3795	else
3796	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3797	if (rc2 < rc && RT_SUCCESS(rc))
3798	rc = rc2;
3799	}
3800	}
3801	}
3802	}
3803
3804	return rc;
3805	}
3806
3807
3808	/**
3809	* Dumps a 32-bit shadow page table.
3810	*
3811	* @returns VBox status code (VINF_SUCCESS).
3812	* @param pVM The VM handle.
3813	* @param pPT Pointer to the page table.
3814	* @param u32Address The virtual address this table starts at.
3815	* @param PhysSearch Address to search for.
3816	*/
3817	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3818	{
3819	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3820	{
3821	X86PTE Pte = pPT->a[i];
3822	if (Pte.n.u1Present)
3823	{
3824	Log(( /P R S A D G WT CD AT NX 4M a m d /
3825	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3826	u32Address + (i << X86_PT_SHIFT),
3827	Pte.n.u1Write ? 'W' : 'R',
3828	Pte.n.u1User ? 'U' : 'S',
3829	Pte.n.u1Accessed ? 'A' : '-',
3830	Pte.n.u1Dirty ? 'D' : '-',
3831	Pte.n.u1Global ? 'G' : '-',
3832	Pte.n.u1WriteThru ? "WT" : "--",
3833	Pte.n.u1CacheDisable? "CD" : "--",
3834	Pte.n.u1PAT ? "AT" : "--",
3835	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3836	Pte.u & RT_BIT(10) ? '1' : '0',
3837	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3838	Pte.u & X86_PDE_PG_MASK));
3839
3840	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3841	{
3842	uint64_t fPageShw = 0;
3843	RTHCPHYS pPhysHC = 0;
3844
3845	/** @todo SMP support!! */
3846	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3847	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3848	}
3849	}
3850	}
3851	return VINF_SUCCESS;
3852	}
3853
3854
3855	/**
3856	* Dumps a 32-bit guest page directory and page tables.
3857	*
3858	* @returns VBox status code (VINF_SUCCESS).
3859	* @param pVM The VM handle.
3860	* @param cr3 The root of the hierarchy.
3861	* @param cr4 The CR4, PSE is currently used.
3862	* @param PhysSearch Address to search for.
3863	*/
3864	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3865	{
3866	bool fLongMode = false;
3867	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3868	PX86PD pPD = 0;
3869	PGMPAGEMAPLOCK LockCr3;
3870
3871	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
3872	if ( RT_FAILURE(rc)
3873	\|\| !pPD)
3874	{
3875	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3876	return VERR_INVALID_PARAMETER;
3877	}
3878
3879	Log(("cr3=%08x cr4=%08x%s\n"
3880	"%-*s P - Present\n"
3881	"%-*s \| R/W - Read (0) / Write (1)\n"
3882	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3883	"%-*s \| \| \| A - Accessed\n"
3884	"%-*s \| \| \| \| D - Dirty\n"
3885	"%-*s \| \| \| \| \| G - Global\n"
3886	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3887	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3888	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3889	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3890	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3891	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3892	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3893	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3894	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3895	- W U - - - -- -- -- -- -- 010 */
3896	, cr3, cr4, fLongMode ? " Long Mode" : "",
3897	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3898	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3899
3900	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3901	{
3902	X86PDE Pde = pPD->a[i];
3903	if (Pde.n.u1Present)
3904	{
3905	const uint32_t u32Address = i << X86_PD_SHIFT;
3906
3907	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3908	Log(( /P R S A D G WT CD AT NX 4M a m d /
3909	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3910	u32Address,
3911	Pde.b.u1Write ? 'W' : 'R',
3912	Pde.b.u1User ? 'U' : 'S',
3913	Pde.b.u1Accessed ? 'A' : '-',
3914	Pde.b.u1Dirty ? 'D' : '-',
3915	Pde.b.u1Global ? 'G' : '-',
3916	Pde.b.u1WriteThru ? "WT" : "--",
3917	Pde.b.u1CacheDisable? "CD" : "--",
3918	Pde.b.u1PAT ? "AT" : "--",
3919	Pde.u & RT_BIT(9) ? '1' : '0',
3920	Pde.u & RT_BIT(10) ? '1' : '0',
3921	Pde.u & RT_BIT(11) ? '1' : '0',
3922	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3923	/** @todo PhysSearch */
3924	else
3925	{
3926	Log(( /P R S A D G WT CD AT NX 4M a m d /
3927	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3928	u32Address,
3929	Pde.n.u1Write ? 'W' : 'R',
3930	Pde.n.u1User ? 'U' : 'S',
3931	Pde.n.u1Accessed ? 'A' : '-',
3932	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3933	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3934	Pde.n.u1WriteThru ? "WT" : "--",
3935	Pde.n.u1CacheDisable? "CD" : "--",
3936	Pde.u & RT_BIT(9) ? '1' : '0',
3937	Pde.u & RT_BIT(10) ? '1' : '0',
3938	Pde.u & RT_BIT(11) ? '1' : '0',
3939	Pde.u & X86_PDE_PG_MASK));
3940	////if (cMaxDepth >= 1)
3941	{
3942	/** @todo what about using the page pool for mapping PTs? */
3943	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3944	PX86PT pPT = NULL;
3945	PGMPAGEMAPLOCK LockPT;
3946
3947	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
3948
3949	int rc2 = VERR_INVALID_PARAMETER;
3950	if (pPT)
3951	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3952	else
3953	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3954
3955	if (rc == VINF_SUCCESS)
3956	PGMPhysReleasePageMappingLock(pVM, &LockPT);
3957
3958	if (rc2 < rc && RT_SUCCESS(rc))
3959	rc = rc2;
3960	}
3961	}
3962	}
3963	}
3964	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
3965	return rc;
3966	}
3967
3968
3969	/**
3970	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3971	*
3972	* @returns VBox status code (VINF_SUCCESS).
3973	* @param pVM The VM handle.
3974	* @param cr3 The root of the hierarchy.
3975	* @param cr4 The cr4, only PAE and PSE is currently used.
3976	* @param fLongMode Set if long mode, false if not long mode.
3977	* @param cMaxDepth Number of levels to dump.
3978	* @param pHlp Pointer to the output functions.
3979	*/
3980	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3981	{
3982	if (!pHlp)
3983	pHlp = DBGFR3InfoLogHlp();
3984	if (!cMaxDepth)
3985	return VINF_SUCCESS;
3986	const unsigned cch = fLongMode ? 16 : 8;
3987	pHlp->pfnPrintf(pHlp,
3988	"cr3=%08x cr4=%08x%s\n"
3989	"%-*s P - Present\n"
3990	"%-*s \| R/W - Read (0) / Write (1)\n"
3991	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3992	"%-*s \| \| \| A - Accessed\n"
3993	"%-*s \| \| \| \| D - Dirty\n"
3994	"%-*s \| \| \| \| \| G - Global\n"
3995	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3996	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3997	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3998	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3999	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4000	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4001	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4002	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4003	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4004	- W U - - - -- -- -- -- -- 010 */
4005	, cr3, cr4, fLongMode ? " Long Mode" : "",
4006	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4007	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4008	if (cr4 & X86_CR4_PAE)
4009	{
4010	if (fLongMode)
4011	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4012	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4013	}
4014	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4015	}
4016
4017	#ifdef VBOX_WITH_DEBUGGER
4018
4019	/**
4020	* The '.pgmram' command.
4021	*
4022	* @returns VBox status.
4023	* @param pCmd Pointer to the command descriptor (as registered).
4024	* @param pCmdHlp Pointer to command helper functions.
4025	* @param pVM Pointer to the current VM (if any).
4026	* @param paArgs Pointer to (readonly) array of arguments.
4027	* @param cArgs Number of arguments in the array.
4028	*/
4029	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4030	{
4031	/*
4032	* Validate input.
4033	*/
4034	if (!pVM)
4035	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4036	if (!pVM->pgm.s.pRamRangesRC)
4037	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4038
4039	/*
4040	* Dump the ranges.
4041	*/
4042	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4043	PPGMRAMRANGE pRam;
4044	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4045	{
4046	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4047	"%RGp - %RGp %p\n",
4048	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4049	if (RT_FAILURE(rc))
4050	return rc;
4051	}
4052
4053	return VINF_SUCCESS;
4054	}
4055
4056
4057	/**
4058	* The '.pgmerror' and '.pgmerroroff' commands.
4059	*
4060	* @returns VBox status.
4061	* @param pCmd Pointer to the command descriptor (as registered).
4062	* @param pCmdHlp Pointer to command helper functions.
4063	* @param pVM Pointer to the current VM (if any).
4064	* @param paArgs Pointer to (readonly) array of arguments.
4065	* @param cArgs Number of arguments in the array.
4066	*/
4067	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4068	{
4069	/*
4070	* Validate input.
4071	*/
4072	if (!pVM)
4073	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4074	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4075	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4076
4077	if (!cArgs)
4078	{
4079	/*
4080	* Print the list of error injection locations with status.
4081	*/
4082	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4083	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4084	}
4085	else
4086	{
4087
4088	/*
4089	* String switch on where to inject the error.
4090	*/
4091	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4092	const char *pszWhere = paArgs[0].u.pszString;
4093	if (!strcmp(pszWhere, "handy"))
4094	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4095	else
4096	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4097	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4098	}
4099	return VINF_SUCCESS;
4100	}
4101
4102
4103	/**
4104	* The '.pgmsync' command.
4105	*
4106	* @returns VBox status.
4107	* @param pCmd Pointer to the command descriptor (as registered).
4108	* @param pCmdHlp Pointer to command helper functions.
4109	* @param pVM Pointer to the current VM (if any).
4110	* @param paArgs Pointer to (readonly) array of arguments.
4111	* @param cArgs Number of arguments in the array.
4112	*/
4113	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4114	{
4115	/** @todo SMP support */
4116	PVMCPU pVCpu = &pVM->aCpus[0];
4117
4118	/*
4119	* Validate input.
4120	*/
4121	if (!pVM)
4122	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4123
4124	/*
4125	* Force page directory sync.
4126	*/
4127	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4128
4129	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4130	if (RT_FAILURE(rc))
4131	return rc;
4132
4133	return VINF_SUCCESS;
4134	}
4135
4136
4137	#ifdef VBOX_STRICT
4138	/**
4139	* The '.pgmassertcr3' command.
4140	*
4141	* @returns VBox status.
4142	* @param pCmd Pointer to the command descriptor (as registered).
4143	* @param pCmdHlp Pointer to command helper functions.
4144	* @param pVM Pointer to the current VM (if any).
4145	* @param paArgs Pointer to (readonly) array of arguments.
4146	* @param cArgs Number of arguments in the array.
4147	*/
4148	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4149	{
4150	/** @todo SMP support!! */
4151	PVMCPU pVCpu = &pVM->aCpus[0];
4152
4153	/*
4154	* Validate input.
4155	*/
4156	if (!pVM)
4157	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4158
4159	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4160	if (RT_FAILURE(rc))
4161	return rc;
4162
4163	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4164
4165	return VINF_SUCCESS;
4166	}
4167	#endif /* VBOX_STRICT */
4168
4169
4170	/**
4171	* The '.pgmsyncalways' command.
4172	*
4173	* @returns VBox status.
4174	* @param pCmd Pointer to the command descriptor (as registered).
4175	* @param pCmdHlp Pointer to command helper functions.
4176	* @param pVM Pointer to the current VM (if any).
4177	* @param paArgs Pointer to (readonly) array of arguments.
4178	* @param cArgs Number of arguments in the array.
4179	*/
4180	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4181	{
4182	/** @todo SMP support!! */
4183	PVMCPU pVCpu = &pVM->aCpus[0];
4184
4185	/*
4186	* Validate input.
4187	*/
4188	if (!pVM)
4189	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4190
4191	/*
4192	* Force page directory sync.
4193	*/
4194	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4195	{
4196	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4197	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4198	}
4199	else
4200	{
4201	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4202	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4203	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4204	}
4205	}
4206
4207
4208	/**
4209	* The '.pgmsyncalways' command.
4210	*
4211	* @returns VBox status.
4212	* @param pCmd Pointer to the command descriptor (as registered).
4213	* @param pCmdHlp Pointer to command helper functions.
4214	* @param pVM Pointer to the current VM (if any).
4215	* @param paArgs Pointer to (readonly) array of arguments.
4216	* @param cArgs Number of arguments in the array.
4217	*/
4218	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4219	{
4220	/*
4221	* Validate input.
4222	*/
4223	if (!pVM)
4224	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4225	if ( cArgs < 1
4226	\|\| cArgs > 2
4227	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4228	\|\| ( cArgs > 1
4229	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4230	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4231	if ( cArgs >= 2
4232	&& strcmp(paArgs[1].u.pszString, "nozero"))
4233	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4234	bool fIncZeroPgs = cArgs < 2;
4235
4236	/*
4237	* Open the output file and get the ram parameters.
4238	*/
4239	RTFILE hFile;
4240	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4241	if (RT_FAILURE(rc))
4242	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4243
4244	uint32_t cbRamHole = 0;
4245	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4246	uint64_t cbRam = 0;
4247	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4248	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4249
4250	/*
4251	* Dump the physical memory, page by page.
4252	*/
4253	RTGCPHYS GCPhys = 0;
4254	char abZeroPg[PAGE_SIZE];
4255	RT_ZERO(abZeroPg);
4256
4257	pgmLock(pVM);
4258	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4259	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4260	pRam = pRam->pNextR3)
4261	{
4262	/* fill the gap */
4263	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4264	{
4265	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4266	{
4267	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4268	GCPhys += PAGE_SIZE;
4269	}
4270	}
4271
4272	PCPGMPAGE pPage = &pRam->aPages[0];
4273	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4274	{
4275	if ( PGM_PAGE_IS_ZERO(pPage)
4276	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4277	{
4278	if (fIncZeroPgs)
4279	{
4280	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4281	if (RT_FAILURE(rc))
4282	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4283	}
4284	}
4285	else
4286	{
4287	switch (PGM_PAGE_GET_TYPE(pPage))
4288	{
4289	case PGMPAGETYPE_RAM:
4290	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4291	case PGMPAGETYPE_ROM:
4292	case PGMPAGETYPE_MMIO2:
4293	{
4294	void const *pvPage;
4295	PGMPAGEMAPLOCK Lock;
4296	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4297	if (RT_SUCCESS(rc))
4298	{
4299	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4300	PGMPhysReleasePageMappingLock(pVM, &Lock);
4301	if (RT_FAILURE(rc))
4302	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4303	}
4304	else
4305	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4306	break;
4307	}
4308
4309	default:
4310	AssertFailed();
4311	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4312	case PGMPAGETYPE_MMIO:
4313	if (fIncZeroPgs)
4314	{
4315	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4316	if (RT_FAILURE(rc))
4317	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4318	}
4319	break;
4320	}
4321	}
4322
4323
4324	/* advance */
4325	GCPhys += PAGE_SIZE;
4326	pPage++;
4327	}
4328	}
4329	pgmUnlock(pVM);
4330
4331	RTFileClose(hFile);
4332	if (RT_SUCCESS(rc))
4333	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4334	return VINF_SUCCESS;
4335	}
4336
4337	#endif /* VBOX_WITH_DEBUGGER */
4338
4339	/**
4340	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4341	*/
4342	typedef struct PGMCHECKINTARGS
4343	{
4344	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4345	PPGMPHYSHANDLER pPrevPhys;
4346	PPGMVIRTHANDLER pPrevVirt;
4347	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4348	PVM pVM;
4349	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4350
4351	/**
4352	* Validate a node in the physical handler tree.
4353	*
4354	* @returns 0 on if ok, other wise 1.
4355	* @param pNode The handler node.
4356	* @param pvUser pVM.
4357	*/
4358	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4359	{
4360	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4361	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4362	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4363	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4364	AssertReleaseMsg( !pArgs->pPrevPhys
4365	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4366	("pPrevPhys=%p %RGp-%RGp %s\n"
4367	" pCur=%p %RGp-%RGp %s\n",
4368	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4369	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4370	pArgs->pPrevPhys = pCur;
4371	return 0;
4372	}
4373
4374
4375	/**
4376	* Validate a node in the virtual handler tree.
4377	*
4378	* @returns 0 on if ok, other wise 1.
4379	* @param pNode The handler node.
4380	* @param pvUser pVM.
4381	*/
4382	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4383	{
4384	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4385	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4386	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4387	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4388	AssertReleaseMsg( !pArgs->pPrevVirt
4389	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4390	("pPrevVirt=%p %RGv-%RGv %s\n"
4391	" pCur=%p %RGv-%RGv %s\n",
4392	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4393	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4394	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4395	{
4396	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4397	("pCur=%p %RGv-%RGv %s\n"
4398	"iPage=%d offVirtHandle=%#x expected %#x\n",
4399	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4400	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4401	}
4402	pArgs->pPrevVirt = pCur;
4403	return 0;
4404	}
4405
4406
4407	/**
4408	* Validate a node in the virtual handler tree.
4409	*
4410	* @returns 0 on if ok, other wise 1.
4411	* @param pNode The handler node.
4412	* @param pvUser pVM.
4413	*/
4414	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4415	{
4416	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4417	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4418	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4419	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4420	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4421	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4422	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4423	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4424	" pCur=%p %RGp-%RGp\n",
4425	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4426	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4427	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4428	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4429	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4430	" pCur=%p %RGp-%RGp\n",
4431	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4432	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4433	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4434	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4435	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4436	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4437	{
4438	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4439	for (;;)
4440	{
4441	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4442	AssertReleaseMsg(pCur2 != pCur,
4443	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4444	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4445	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4446	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4447	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4448	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4449	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4450	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4451	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4452	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4453	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4454	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4455	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4456	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4457	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4458	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4459	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4460	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4461	break;
4462	}
4463	}
4464
4465	pArgs->pPrevPhys2Virt = pCur;
4466	return 0;
4467	}
4468
4469
4470	/**
4471	* Perform an integrity check on the PGM component.
4472	*
4473	* @returns VINF_SUCCESS if everything is fine.
4474	* @returns VBox error status after asserting on integrity breach.
4475	* @param pVM The VM handle.
4476	*/
4477	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4478	{
4479	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4480
4481	/*
4482	* Check the trees.
4483	*/
4484	int cErrors = 0;
4485	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4486	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4487	PGMCHECKINTARGS Args = s_LeftToRight;
4488	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4489	Args = s_RightToLeft;
4490	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4491	Args = s_LeftToRight;
4492	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4493	Args = s_RightToLeft;
4494	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4495	Args = s_LeftToRight;
4496	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4497	Args = s_RightToLeft;
4498	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4499	Args = s_LeftToRight;
4500	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4501	Args = s_RightToLeft;
4502	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4503
4504	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4505	}
4506

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 30791

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