PGM.cpp@ 31296

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1	/* $Id: PGM.cpp 31206 2010-07-29 13:05:31Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570	/*******************************************************************************
571	* Header Files *
572	*******************************************************************************/
573	#define LOG_GROUP LOG_GROUP_PGM
574	#include <VBox/dbgf.h>
575	#include <VBox/pgm.h>
576	#include <VBox/cpum.h>
577	#include <VBox/iom.h>
578	#include <VBox/sup.h>
579	#include <VBox/mm.h>
580	#include <VBox/em.h>
581	#include <VBox/stam.h>
582	#include <VBox/rem.h>
583	#include <VBox/selm.h>
584	#include <VBox/ssm.h>
585	#include <VBox/hwaccm.h>
586	#include "PGMInternal.h"
587	#include <VBox/vm.h>
588	#include "PGMInline.h"
589
590	#include <VBox/dbg.h>
591	#include <VBox/param.h>
592	#include <VBox/err.h>
593
594	#include <iprt/asm.h>
595	#include <iprt/asm-amd64-x86.h>
596	#include <iprt/assert.h>
597	#include <iprt/env.h>
598	#include <iprt/mem.h>
599	#include <iprt/file.h>
600	#include <iprt/string.h>
601	#include <iprt/thread.h>
602
603
604	/*******************************************************************************
605	* Internal Functions *
606	*******************************************************************************/
607	static int pgmR3InitPaging(PVM pVM);
608	static int pgmR3InitStats(PVM pVM);
609	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
610	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
613	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	#ifdef VBOX_STRICT
616	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
617	#endif
618	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
619	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
620	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
621
622	#ifdef VBOX_WITH_DEBUGGER
623	/** @todo Convert the first two commands to 'info' items. */
624	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
625	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
626	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
627	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
628	# ifdef VBOX_STRICT
629	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
630	# endif
631	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	#endif
633
634
635	/*******************************************************************************
636	* Global Variables *
637	*******************************************************************************/
638	#ifdef VBOX_WITH_DEBUGGER
639	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
640	static const DBGCVARDESC g_aPgmErrorArgs[] =
641	{
642	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
643	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
644	};
645
646	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
647	{
648	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
649	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
650	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
651	};
652
653	/** Command descriptors. */
654	static const DBGCCMD g_aCmds[] =
655	{
656	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
657	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
660	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
661	#ifdef VBOX_STRICT
662	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
663	#endif
664	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
665	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
666	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
667	#endif
668	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
669	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
670	};
671	#endif
672
673
674
675
676	/*
677	* Shadow - 32-bit mode
678	*/
679	#define PGM_SHW_TYPE PGM_TYPE_32BIT
680	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
681	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
682	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
683	#include "PGMShw.h"
684
685	/* Guest - real mode */
686	#define PGM_GST_TYPE PGM_TYPE_REAL
687	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
688	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
689	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
690	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
691	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
692	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
693	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
694	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
695	#include "PGMBth.h"
696	#include "PGMGstDefs.h"
697	#include "PGMGst.h"
698	#undef BTH_PGMPOOLKIND_PT_FOR_PT
699	#undef BTH_PGMPOOLKIND_ROOT
700	#undef PGM_BTH_NAME
701	#undef PGM_BTH_NAME_RC_STR
702	#undef PGM_BTH_NAME_R0_STR
703	#undef PGM_GST_TYPE
704	#undef PGM_GST_NAME
705	#undef PGM_GST_NAME_RC_STR
706	#undef PGM_GST_NAME_R0_STR
707
708	/* Guest - protected mode */
709	#define PGM_GST_TYPE PGM_TYPE_PROT
710	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
711	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
712	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
713	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
714	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
715	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
716	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
717	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
718	#include "PGMBth.h"
719	#include "PGMGstDefs.h"
720	#include "PGMGst.h"
721	#undef BTH_PGMPOOLKIND_PT_FOR_PT
722	#undef BTH_PGMPOOLKIND_ROOT
723	#undef PGM_BTH_NAME
724	#undef PGM_BTH_NAME_RC_STR
725	#undef PGM_BTH_NAME_R0_STR
726	#undef PGM_GST_TYPE
727	#undef PGM_GST_NAME
728	#undef PGM_GST_NAME_RC_STR
729	#undef PGM_GST_NAME_R0_STR
730
731	/* Guest - 32-bit mode */
732	#define PGM_GST_TYPE PGM_TYPE_32BIT
733	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
734	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
735	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
736	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
737	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
738	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
739	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
740	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
741	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
742	#include "PGMBth.h"
743	#include "PGMGstDefs.h"
744	#include "PGMGst.h"
745	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
746	#undef BTH_PGMPOOLKIND_PT_FOR_PT
747	#undef BTH_PGMPOOLKIND_ROOT
748	#undef PGM_BTH_NAME
749	#undef PGM_BTH_NAME_RC_STR
750	#undef PGM_BTH_NAME_R0_STR
751	#undef PGM_GST_TYPE
752	#undef PGM_GST_NAME
753	#undef PGM_GST_NAME_RC_STR
754	#undef PGM_GST_NAME_R0_STR
755
756	#undef PGM_SHW_TYPE
757	#undef PGM_SHW_NAME
758	#undef PGM_SHW_NAME_RC_STR
759	#undef PGM_SHW_NAME_R0_STR
760
761
762	/*
763	* Shadow - PAE mode
764	*/
765	#define PGM_SHW_TYPE PGM_TYPE_PAE
766	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
767	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
768	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
769	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
770	#include "PGMShw.h"
771
772	/* Guest - real mode */
773	#define PGM_GST_TYPE PGM_TYPE_REAL
774	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
775	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
776	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
777	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
778	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
779	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
780	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
781	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
782	#include "PGMGstDefs.h"
783	#include "PGMBth.h"
784	#undef BTH_PGMPOOLKIND_PT_FOR_PT
785	#undef BTH_PGMPOOLKIND_ROOT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - protected mode */
795	#define PGM_GST_TYPE PGM_TYPE_PROT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
803	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
804	#include "PGMGstDefs.h"
805	#include "PGMBth.h"
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef BTH_PGMPOOLKIND_ROOT
808	#undef PGM_BTH_NAME
809	#undef PGM_BTH_NAME_RC_STR
810	#undef PGM_BTH_NAME_R0_STR
811	#undef PGM_GST_TYPE
812	#undef PGM_GST_NAME
813	#undef PGM_GST_NAME_RC_STR
814	#undef PGM_GST_NAME_R0_STR
815
816	/* Guest - 32-bit mode */
817	#define PGM_GST_TYPE PGM_TYPE_32BIT
818	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
819	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
820	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
821	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
822	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
823	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
824	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
825	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
826	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
827	#include "PGMGstDefs.h"
828	#include "PGMBth.h"
829	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
830	#undef BTH_PGMPOOLKIND_PT_FOR_PT
831	#undef BTH_PGMPOOLKIND_ROOT
832	#undef PGM_BTH_NAME
833	#undef PGM_BTH_NAME_RC_STR
834	#undef PGM_BTH_NAME_R0_STR
835	#undef PGM_GST_TYPE
836	#undef PGM_GST_NAME
837	#undef PGM_GST_NAME_RC_STR
838	#undef PGM_GST_NAME_R0_STR
839
840	/* Guest - PAE mode */
841	#define PGM_GST_TYPE PGM_TYPE_PAE
842	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
843	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
844	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
845	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
846	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
847	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
848	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
849	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
850	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
851	#include "PGMBth.h"
852	#include "PGMGstDefs.h"
853	#include "PGMGst.h"
854	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
855	#undef BTH_PGMPOOLKIND_PT_FOR_PT
856	#undef BTH_PGMPOOLKIND_ROOT
857	#undef PGM_BTH_NAME
858	#undef PGM_BTH_NAME_RC_STR
859	#undef PGM_BTH_NAME_R0_STR
860	#undef PGM_GST_TYPE
861	#undef PGM_GST_NAME
862	#undef PGM_GST_NAME_RC_STR
863	#undef PGM_GST_NAME_R0_STR
864
865	#undef PGM_SHW_TYPE
866	#undef PGM_SHW_NAME
867	#undef PGM_SHW_NAME_RC_STR
868	#undef PGM_SHW_NAME_R0_STR
869
870
871	/*
872	* Shadow - AMD64 mode
873	*/
874	#define PGM_SHW_TYPE PGM_TYPE_AMD64
875	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
876	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
877	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
878	#include "PGMShw.h"
879
880	#ifdef VBOX_WITH_64_BITS_GUESTS
881	/* Guest - AMD64 mode */
882	# define PGM_GST_TYPE PGM_TYPE_AMD64
883	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
884	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
885	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
886	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
887	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
888	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
889	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
890	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
891	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
892	# include "PGMBth.h"
893	# include "PGMGstDefs.h"
894	# include "PGMGst.h"
895	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
896	# undef BTH_PGMPOOLKIND_PT_FOR_PT
897	# undef BTH_PGMPOOLKIND_ROOT
898	# undef PGM_BTH_NAME
899	# undef PGM_BTH_NAME_RC_STR
900	# undef PGM_BTH_NAME_R0_STR
901	# undef PGM_GST_TYPE
902	# undef PGM_GST_NAME
903	# undef PGM_GST_NAME_RC_STR
904	# undef PGM_GST_NAME_R0_STR
905	#endif /* VBOX_WITH_64_BITS_GUESTS */
906
907	#undef PGM_SHW_TYPE
908	#undef PGM_SHW_NAME
909	#undef PGM_SHW_NAME_RC_STR
910	#undef PGM_SHW_NAME_R0_STR
911
912
913	/*
914	* Shadow - Nested paging mode
915	*/
916	#define PGM_SHW_TYPE PGM_TYPE_NESTED
917	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
918	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
919	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
920	#include "PGMShw.h"
921
922	/* Guest - real mode */
923	#define PGM_GST_TYPE PGM_TYPE_REAL
924	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
925	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
926	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
927	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
928	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
929	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
930	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
931	#include "PGMGstDefs.h"
932	#include "PGMBth.h"
933	#undef BTH_PGMPOOLKIND_PT_FOR_PT
934	#undef PGM_BTH_NAME
935	#undef PGM_BTH_NAME_RC_STR
936	#undef PGM_BTH_NAME_R0_STR
937	#undef PGM_GST_TYPE
938	#undef PGM_GST_NAME
939	#undef PGM_GST_NAME_RC_STR
940	#undef PGM_GST_NAME_R0_STR
941
942	/* Guest - protected mode */
943	#define PGM_GST_TYPE PGM_TYPE_PROT
944	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
945	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
946	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
947	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
948	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
949	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
950	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
951	#include "PGMGstDefs.h"
952	#include "PGMBth.h"
953	#undef BTH_PGMPOOLKIND_PT_FOR_PT
954	#undef PGM_BTH_NAME
955	#undef PGM_BTH_NAME_RC_STR
956	#undef PGM_BTH_NAME_R0_STR
957	#undef PGM_GST_TYPE
958	#undef PGM_GST_NAME
959	#undef PGM_GST_NAME_RC_STR
960	#undef PGM_GST_NAME_R0_STR
961
962	/* Guest - 32-bit mode */
963	#define PGM_GST_TYPE PGM_TYPE_32BIT
964	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
965	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
966	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
967	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
968	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
969	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
970	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
971	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
972	#include "PGMGstDefs.h"
973	#include "PGMBth.h"
974	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
975	#undef BTH_PGMPOOLKIND_PT_FOR_PT
976	#undef PGM_BTH_NAME
977	#undef PGM_BTH_NAME_RC_STR
978	#undef PGM_BTH_NAME_R0_STR
979	#undef PGM_GST_TYPE
980	#undef PGM_GST_NAME
981	#undef PGM_GST_NAME_RC_STR
982	#undef PGM_GST_NAME_R0_STR
983
984	/* Guest - PAE mode */
985	#define PGM_GST_TYPE PGM_TYPE_PAE
986	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
987	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
988	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
989	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
990	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
991	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
992	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
993	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
994	#include "PGMGstDefs.h"
995	#include "PGMBth.h"
996	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
997	#undef BTH_PGMPOOLKIND_PT_FOR_PT
998	#undef PGM_BTH_NAME
999	#undef PGM_BTH_NAME_RC_STR
1000	#undef PGM_BTH_NAME_R0_STR
1001	#undef PGM_GST_TYPE
1002	#undef PGM_GST_NAME
1003	#undef PGM_GST_NAME_RC_STR
1004	#undef PGM_GST_NAME_R0_STR
1005
1006	#ifdef VBOX_WITH_64_BITS_GUESTS
1007	/* Guest - AMD64 mode */
1008	# define PGM_GST_TYPE PGM_TYPE_AMD64
1009	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1010	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1011	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1012	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1013	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1014	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1015	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1016	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1017	# include "PGMGstDefs.h"
1018	# include "PGMBth.h"
1019	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1020	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1021	# undef PGM_BTH_NAME
1022	# undef PGM_BTH_NAME_RC_STR
1023	# undef PGM_BTH_NAME_R0_STR
1024	# undef PGM_GST_TYPE
1025	# undef PGM_GST_NAME
1026	# undef PGM_GST_NAME_RC_STR
1027	# undef PGM_GST_NAME_R0_STR
1028	#endif /* VBOX_WITH_64_BITS_GUESTS */
1029
1030	#undef PGM_SHW_TYPE
1031	#undef PGM_SHW_NAME
1032	#undef PGM_SHW_NAME_RC_STR
1033	#undef PGM_SHW_NAME_R0_STR
1034
1035
1036	/*
1037	* Shadow - EPT
1038	*/
1039	#define PGM_SHW_TYPE PGM_TYPE_EPT
1040	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1041	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1042	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1043	#include "PGMShw.h"
1044
1045	/* Guest - real mode */
1046	#define PGM_GST_TYPE PGM_TYPE_REAL
1047	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1048	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1049	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1050	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1051	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1052	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1053	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1054	#include "PGMGstDefs.h"
1055	#include "PGMBth.h"
1056	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1057	#undef PGM_BTH_NAME
1058	#undef PGM_BTH_NAME_RC_STR
1059	#undef PGM_BTH_NAME_R0_STR
1060	#undef PGM_GST_TYPE
1061	#undef PGM_GST_NAME
1062	#undef PGM_GST_NAME_RC_STR
1063	#undef PGM_GST_NAME_R0_STR
1064
1065	/* Guest - protected mode */
1066	#define PGM_GST_TYPE PGM_TYPE_PROT
1067	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1068	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1069	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1070	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1071	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1072	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1073	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1074	#include "PGMGstDefs.h"
1075	#include "PGMBth.h"
1076	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1077	#undef PGM_BTH_NAME
1078	#undef PGM_BTH_NAME_RC_STR
1079	#undef PGM_BTH_NAME_R0_STR
1080	#undef PGM_GST_TYPE
1081	#undef PGM_GST_NAME
1082	#undef PGM_GST_NAME_RC_STR
1083	#undef PGM_GST_NAME_R0_STR
1084
1085	/* Guest - 32-bit mode */
1086	#define PGM_GST_TYPE PGM_TYPE_32BIT
1087	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1088	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1089	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1090	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1091	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1092	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1093	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1094	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1095	#include "PGMGstDefs.h"
1096	#include "PGMBth.h"
1097	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1098	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1099	#undef PGM_BTH_NAME
1100	#undef PGM_BTH_NAME_RC_STR
1101	#undef PGM_BTH_NAME_R0_STR
1102	#undef PGM_GST_TYPE
1103	#undef PGM_GST_NAME
1104	#undef PGM_GST_NAME_RC_STR
1105	#undef PGM_GST_NAME_R0_STR
1106
1107	/* Guest - PAE mode */
1108	#define PGM_GST_TYPE PGM_TYPE_PAE
1109	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1110	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1111	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1112	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1113	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1114	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1115	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1116	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1117	#include "PGMGstDefs.h"
1118	#include "PGMBth.h"
1119	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1120	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1121	#undef PGM_BTH_NAME
1122	#undef PGM_BTH_NAME_RC_STR
1123	#undef PGM_BTH_NAME_R0_STR
1124	#undef PGM_GST_TYPE
1125	#undef PGM_GST_NAME
1126	#undef PGM_GST_NAME_RC_STR
1127	#undef PGM_GST_NAME_R0_STR
1128
1129	#ifdef VBOX_WITH_64_BITS_GUESTS
1130	/* Guest - AMD64 mode */
1131	# define PGM_GST_TYPE PGM_TYPE_AMD64
1132	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1133	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1134	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1135	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1136	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1137	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1138	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1139	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1140	# include "PGMGstDefs.h"
1141	# include "PGMBth.h"
1142	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1143	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1144	# undef PGM_BTH_NAME
1145	# undef PGM_BTH_NAME_RC_STR
1146	# undef PGM_BTH_NAME_R0_STR
1147	# undef PGM_GST_TYPE
1148	# undef PGM_GST_NAME
1149	# undef PGM_GST_NAME_RC_STR
1150	# undef PGM_GST_NAME_R0_STR
1151	#endif /* VBOX_WITH_64_BITS_GUESTS */
1152
1153	#undef PGM_SHW_TYPE
1154	#undef PGM_SHW_NAME
1155	#undef PGM_SHW_NAME_RC_STR
1156	#undef PGM_SHW_NAME_R0_STR
1157
1158
1159
1160	/**
1161	* Initiates the paging of VM.
1162	*
1163	* @returns VBox status code.
1164	* @param pVM Pointer to VM structure.
1165	*/
1166	VMMR3DECL(int) PGMR3Init(PVM pVM)
1167	{
1168	LogFlow(("PGMR3Init:\n"));
1169	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1170	int rc;
1171
1172	/*
1173	* Assert alignment and sizes.
1174	*/
1175	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1176	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1177	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1178
1179	/*
1180	* Init the structure.
1181	*/
1182	#ifdef PGM_WITHOUT_MAPPINGS
1183	pVM->pgm.s.fMappingsDisabled = true;
1184	#endif
1185	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1186	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1187
1188	/* Init the per-CPU part. */
1189	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1190	{
1191	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1192	PPGMCPU pPGM = &pVCpu->pgm.s;
1193
1194	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1195	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1196	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1197
1198	pPGM->enmShadowMode = PGMMODE_INVALID;
1199	pPGM->enmGuestMode = PGMMODE_INVALID;
1200
1201	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1202
1203	pPGM->pGst32BitPdR3 = NULL;
1204	pPGM->pGstPaePdptR3 = NULL;
1205	pPGM->pGstAmd64Pml4R3 = NULL;
1206	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1207	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1208	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1209	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1210	#endif
1211	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1212	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1213	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1214	{
1215	pPGM->apGstPaePDsR3[i] = NULL;
1216	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1217	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1218	#endif
1219	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1220	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1221	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1222	}
1223
1224	pPGM->fA20Enabled = true;
1225	}
1226
1227	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1228	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1229	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1230
1231	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1232	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1233	true
1234	#else
1235	false
1236	#endif
1237	);
1238	AssertLogRelRCReturn(rc, rc);
1239
1240	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
1241	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1242	#else
1243	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1244	#endif
1245	AssertLogRelRCReturn(rc, rc);
1246	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1247	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1248
1249	/*
1250	* Get the configured RAM size - to estimate saved state size.
1251	*/
1252	uint64_t cbRam;
1253	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1254	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1255	cbRam = 0;
1256	else if (RT_SUCCESS(rc))
1257	{
1258	if (cbRam < PAGE_SIZE)
1259	cbRam = 0;
1260	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1261	}
1262	else
1263	{
1264	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1265	return rc;
1266	}
1267
1268	#ifdef VBOX_WITH_STATISTICS
1269	/*
1270	* Allocate memory for the statistics before someone tries to use them.
1271	*/
1272	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1273	void *pv;
1274	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1275	AssertRCReturn(rc, rc);
1276
1277	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1278	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1279	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1280	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1281
1282	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1283	{
1284	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1285	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1286	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1287
1288	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1289	}
1290	#endif /* VBOX_WITH_STATISTICS */
1291
1292	/*
1293	* Register callbacks, string formatters and the saved state data unit.
1294	*/
1295	#ifdef VBOX_STRICT
1296	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1297	#endif
1298	PGMRegisterStringFormatTypes();
1299
1300	rc = pgmR3InitSavedState(pVM, cbRam);
1301	if (RT_FAILURE(rc))
1302	return rc;
1303
1304	/*
1305	* Initialize the PGM critical section and flush the phys TLBs
1306	*/
1307	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1308	AssertRCReturn(rc, rc);
1309
1310	PGMR3PhysChunkInvalidateTLB(pVM);
1311	PGMPhysInvalidatePageMapTLB(pVM);
1312
1313	/*
1314	* For the time being we sport a full set of handy pages in addition to the base
1315	* memory to simplify things.
1316	*/
1317	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1318	AssertRCReturn(rc, rc);
1319
1320	/*
1321	* Trees
1322	*/
1323	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1324	if (RT_SUCCESS(rc))
1325	{
1326	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1327	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1328
1329	/*
1330	* Allocate the zero page.
1331	*/
1332	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1333	}
1334	if (RT_SUCCESS(rc))
1335	{
1336	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1337	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1338	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1339	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1340
1341	/*
1342	* Allocate the invalid MMIO page.
1343	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1344	*/
1345	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1346	}
1347	if (RT_SUCCESS(rc))
1348	{
1349	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1350	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1351	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1352	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1353
1354	/*
1355	* Init the paging.
1356	*/
1357	rc = pgmR3InitPaging(pVM);
1358	}
1359	if (RT_SUCCESS(rc))
1360	{
1361	/*
1362	* Init the page pool.
1363	*/
1364	rc = pgmR3PoolInit(pVM);
1365	}
1366	if (RT_SUCCESS(rc))
1367	{
1368	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1369	{
1370	PVMCPU pVCpu = &pVM->aCpus[i];
1371	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1372	if (RT_FAILURE(rc))
1373	break;
1374	}
1375	}
1376
1377	if (RT_SUCCESS(rc))
1378	{
1379	/*
1380	* Info & statistics
1381	*/
1382	DBGFR3InfoRegisterInternal(pVM, "mode",
1383	"Shows the current paging mode. "
1384	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1385	pgmR3InfoMode);
1386	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1387	"Dumps all the entries in the top level paging table. No arguments.",
1388	pgmR3InfoCr3);
1389	DBGFR3InfoRegisterInternal(pVM, "phys",
1390	"Dumps all the physical address ranges. No arguments.",
1391	pgmR3PhysInfo);
1392	DBGFR3InfoRegisterInternal(pVM, "handlers",
1393	"Dumps physical, virtual and hyper virtual handlers. "
1394	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1395	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1396	pgmR3InfoHandlers);
1397	DBGFR3InfoRegisterInternal(pVM, "mappings",
1398	"Dumps guest mappings.",
1399	pgmR3MapInfo);
1400
1401	pgmR3InitStats(pVM);
1402
1403	#ifdef VBOX_WITH_DEBUGGER
1404	/*
1405	* Debugger commands.
1406	*/
1407	static bool s_fRegisteredCmds = false;
1408	if (!s_fRegisteredCmds)
1409	{
1410	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1411	if (RT_SUCCESS(rc2))
1412	s_fRegisteredCmds = true;
1413	}
1414	#endif
1415	return VINF_SUCCESS;
1416	}
1417
1418	/* Almost no cleanup necessary, MM frees all memory. */
1419	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1420
1421	return rc;
1422	}
1423
1424
1425	/**
1426	* Initializes the per-VCPU PGM.
1427	*
1428	* @returns VBox status code.
1429	* @param pVM The VM to operate on.
1430	*/
1431	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1432	{
1433	LogFlow(("PGMR3InitCPU\n"));
1434	return VINF_SUCCESS;
1435	}
1436
1437
1438	/**
1439	* Init paging.
1440	*
1441	* Since we need to check what mode the host is operating in before we can choose
1442	* the right paging functions for the host we have to delay this until R0 has
1443	* been initialized.
1444	*
1445	* @returns VBox status code.
1446	* @param pVM VM handle.
1447	*/
1448	static int pgmR3InitPaging(PVM pVM)
1449	{
1450	/*
1451	* Force a recalculation of modes and switcher so everyone gets notified.
1452	*/
1453	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1454	{
1455	PVMCPU pVCpu = &pVM->aCpus[i];
1456
1457	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1458	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1459	}
1460
1461	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1462
1463	/*
1464	* Allocate static mapping space for whatever the cr3 register
1465	* points to and in the case of PAE mode to the 4 PDs.
1466	*/
1467	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1468	if (RT_FAILURE(rc))
1469	{
1470	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1471	return rc;
1472	}
1473	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1474
1475	/*
1476	* Allocate pages for the three possible intermediate contexts
1477	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1478	* for the sake of simplicity. The AMD64 uses the PAE for the
1479	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1480	*
1481	* We assume that two page tables will be enought for the core code
1482	* mappings (HC virtual and identity).
1483	*/
1484	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1485	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1486	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1487	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1488	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1489	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1490	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1491	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1492	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1493	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1494	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1495	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1496
1497	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1498	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1499	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1500	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1501	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1502	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1503
1504	/*
1505	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1506	*/
1507	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1508	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1509	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1510
1511	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1512	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1513
1514	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1515	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1516	{
1517	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1518	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1519	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1520	}
1521
1522	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1523	{
1524	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1525	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1526	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1527	}
1528
1529	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1530	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1531	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1532	\| HCPhysInterPaePDPT64;
1533
1534	/*
1535	* Initialize paging workers and mode from current host mode
1536	* and the guest running in real mode.
1537	*/
1538	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1539	switch (pVM->pgm.s.enmHostMode)
1540	{
1541	case SUPPAGINGMODE_32_BIT:
1542	case SUPPAGINGMODE_32_BIT_GLOBAL:
1543	case SUPPAGINGMODE_PAE:
1544	case SUPPAGINGMODE_PAE_GLOBAL:
1545	case SUPPAGINGMODE_PAE_NX:
1546	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1547	break;
1548
1549	case SUPPAGINGMODE_AMD64:
1550	case SUPPAGINGMODE_AMD64_GLOBAL:
1551	case SUPPAGINGMODE_AMD64_NX:
1552	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1553	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1554	if (ARCH_BITS != 64)
1555	{
1556	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1557	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1558	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1559	}
1560	#endif
1561	break;
1562	default:
1563	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1564	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1565	}
1566	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1567	if (RT_SUCCESS(rc))
1568	{
1569	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1570	#if HC_ARCH_BITS == 64
1571	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1572	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1573	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1574	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1575	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1576	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1577	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1578	#endif
1579	return VINF_SUCCESS;
1580	}
1581
1582	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1583	return rc;
1584	}
1585
1586
1587	/**
1588	* Init statistics
1589	* @returns VBox status code.
1590	*/
1591	static int pgmR3InitStats(PVM pVM)
1592	{
1593	PPGM pPGM = &pVM->pgm.s;
1594	int rc;
1595
1596	/*
1597	* Release statistics.
1598	*/
1599	/* Common - misc variables */
1600	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1601	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1602	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1603	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1604	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1605	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1606	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1607	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1608	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1609	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1610	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1611	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1612	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1613	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1614	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1615	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1616	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1617
1618	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1619	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1620	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1621	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1622
1623	/* Live save */
1624	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1625	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1626	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1627	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1628	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1629	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1630	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1631	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1632	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1633	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1634	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1635	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1636	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1637	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1638	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1639	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1640	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1641	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1642
1643	#ifdef VBOX_WITH_STATISTICS
1644
1645	# define PGM_REG_COUNTER(a, b, c) \
1646	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1647	AssertRC(rc);
1648
1649	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1650	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1651	AssertRC(rc);
1652
1653	# define PGM_REG_PROFILE(a, b, c) \
1654	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1655	AssertRC(rc);
1656
1657	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1658
1659	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1660	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1661	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1662	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1663
1664	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1665	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1666	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1667	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1668	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1669	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1670	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1671	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1672	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1673	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1674
1675	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1676	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1677	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1678	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1679	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1680	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1681
1682	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1683	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1684	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1685	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1686	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1687	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1688	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1689	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1690
1691	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1692	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1693	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1694	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1695
1696	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1697	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1698	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1699	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1700	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1701	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1702	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1703	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1704
1705	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1706	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1707	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1708	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1709	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1710	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1711
1712	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1713	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1714	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1715	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1716	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1717	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1718	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1719	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1720
1721	/* GC only: */
1722	PGM_REG_COUNTER(&pStats->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1723	PGM_REG_COUNTER(&pStats->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1724	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1725	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1726
1727	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1728	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1729	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1730	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1731	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1732	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1733	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1734	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1735
1736	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1737	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1738	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1739	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1740	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1741	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1742	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1743
1744	# undef PGM_REG_COUNTER
1745	# undef PGM_REG_PROFILE
1746	#endif
1747
1748	/*
1749	* Note! The layout below matches the member layout exactly!
1750	*/
1751
1752	/*
1753	* Common - stats
1754	*/
1755	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1756	{
1757	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1758
1759	#define PGM_REG_COUNTER(a, b, c) \
1760	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1761	AssertRC(rc);
1762	#define PGM_REG_PROFILE(a, b, c) \
1763	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1764	AssertRC(rc);
1765
1766	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1767
1768	#ifdef VBOX_WITH_STATISTICS
1769	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1770
1771	# if 0 /* rarely useful; leave for debugging. */
1772	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1773	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1774	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1775	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1776	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1777	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1778	# endif
1779	/* R0 only: */
1780	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1781	PGM_REG_PROFILE(&pCpuStats->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1782	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1783	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1784	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1785	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1786	PGM_REG_PROFILE(&pCpuStats->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1787	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1788	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1789	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1790	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1791	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1792	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1793	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1794	PGM_REG_PROFILE(&pCpuStats->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1795	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1796	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1797	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1798	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1799	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1800	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1801	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1802	//PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1803	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1804	PGM_REG_COUNTER(&pCpuStats->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1805	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1806	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1807	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1808	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1809	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1810	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1811	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1812	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1813	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1814	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1815	PGM_REG_COUNTER(&pCpuStats->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1816
1817	/* RZ only: */
1818	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1819	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1820	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1821	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1822	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1823	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1824	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1825	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1826	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1827	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1828	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is releated to the guest mappings.");
1829	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1830	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1831	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1832	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1833	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1834	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1835	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1836	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1837	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1838	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1839	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1840	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1841	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1842	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1843	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1844	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1845	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1846	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1847	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1848	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1849	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1850	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1851	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1852	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1853	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1854	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1855	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1856	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1857	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1858	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1859	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1860	#if 0 /* rarely useful; leave for debugging. */
1861	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1862	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1863	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1864	#endif
1865	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1866	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1867	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1868	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1869	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1870
1871	/* HC only: */
1872
1873	/* RZ & R3: */
1874	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1875	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1876	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1877	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1878	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1879	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1880	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1881	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1882	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1883	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1884	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1885	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1886	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1887	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1888	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1889	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1891	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1894	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1900	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1914	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1915	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1919	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1920	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1921
1922	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1923	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1924	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1925	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1926	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1927	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1928	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1929	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1930	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1931	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1932	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1933	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1934	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1935	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1936	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1937	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1938	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1939	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1940	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1941	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1942	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1943	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1944	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1945	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1946	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1947	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1948	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1949	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1950	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1951	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1952	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1953	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1954	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1955	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1956	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1957	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1958	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1959	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1960	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1961	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1962	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1963	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1964	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1965	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1966	#endif /* VBOX_WITH_STATISTICS */
1967
1968	#undef PGM_REG_PROFILE
1969	#undef PGM_REG_COUNTER
1970
1971	}
1972
1973	return VINF_SUCCESS;
1974	}
1975
1976
1977	/**
1978	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1979	*
1980	* The dynamic mapping area will also be allocated and initialized at this
1981	* time. We could allocate it during PGMR3Init of course, but the mapping
1982	* wouldn't be allocated at that time preventing us from setting up the
1983	* page table entries with the dummy page.
1984	*
1985	* @returns VBox status code.
1986	* @param pVM VM handle.
1987	*/
1988	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1989	{
1990	RTGCPTR GCPtr;
1991	int rc;
1992
1993	/*
1994	* Reserve space for the dynamic mappings.
1995	*/
1996	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1997	if (RT_SUCCESS(rc))
1998	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1999
2000	if ( RT_SUCCESS(rc)
2001	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2002	{
2003	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2004	if (RT_SUCCESS(rc))
2005	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2006	}
2007	if (RT_SUCCESS(rc))
2008	{
2009	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2010	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2011	}
2012	return rc;
2013	}
2014
2015
2016	/**
2017	* Ring-3 init finalizing.
2018	*
2019	* @returns VBox status code.
2020	* @param pVM The VM handle.
2021	*/
2022	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2023	{
2024	int rc;
2025
2026	/*
2027	* Reserve space for the dynamic mappings.
2028	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2029	*/
2030	/* get the pointer to the page table entries. */
2031	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2032	AssertRelease(pMapping);
2033	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2034	const unsigned iPT = off >> X86_PD_SHIFT;
2035	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2036	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2037	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2038
2039	/* init cache */
2040	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2041	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
2042	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
2043
2044	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
2045	{
2046	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
2047	AssertRCReturn(rc, rc);
2048	}
2049
2050	/*
2051	* Determin the max physical address width (MAXPHYADDR) and apply it to
2052	* all the mask members and stuff.
2053	*/
2054	uint32_t cMaxPhysAddrWidth;
2055	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2056	if ( uMaxExtLeaf >= 0x80000008
2057	&& uMaxExtLeaf <= 0x80000fff)
2058	{
2059	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2060	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2061	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2062	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2063	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2064	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2065	}
2066	else
2067	{
2068	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2069	cMaxPhysAddrWidth = 48;
2070	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2071	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2072	}
2073
2074	pVM->pgm.s.GCPhysInvAddrMask = 0;
2075	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2076	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2077
2078	/*
2079	* Initialize the invalid paging entry masks, assuming NX is disabled.
2080	*/
2081	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2082	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2083	{
2084	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2085
2086	/** @todo The manuals are not entirely clear whether the physical
2087	* address width is relevant. See table 5-9 in the intel
2088	* manual vs the PDE4M descriptions. Write testcase (NP). */
2089	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2090	\| X86_PDE4M_MBZ_MASK;
2091
2092	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2093	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2094	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2095	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2096
2097	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2098	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2099	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2100	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2101	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2102	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2103	}
2104
2105	/*
2106	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2107	* Intel only goes up to 36 bits, so we stick to 36 as well.
2108	* Update: More recent intel manuals specifies 40 bits just like AMD.
2109	*/
2110	uint32_t u32Dummy, u32Features;
2111	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2112	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2113	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2114	else
2115	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2116
2117	/*
2118	* Allocate memory if we're supposed to do that.
2119	*/
2120	if (pVM->pgm.s.fRamPreAlloc)
2121	rc = pgmR3PhysRamPreAllocate(pVM);
2122
2123	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2124	return rc;
2125	}
2126
2127
2128	/**
2129	* Applies relocations to data and code managed by this component.
2130	*
2131	* This function will be called at init and whenever the VMM need to relocate it
2132	* self inside the GC.
2133	*
2134	* @param pVM The VM.
2135	* @param offDelta Relocation delta relative to old location.
2136	*/
2137	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2138	{
2139	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2140
2141	/*
2142	* Paging stuff.
2143	*/
2144	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2145
2146	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2147
2148	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2149	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2150	{
2151	PVMCPU pVCpu = &pVM->aCpus[i];
2152
2153	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2154
2155	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2156	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2157	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2158	}
2159
2160	/*
2161	* Trees.
2162	*/
2163	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2164
2165	/*
2166	* Ram ranges.
2167	*/
2168	if (pVM->pgm.s.pRamRangesR3)
2169	{
2170	/* Update the pSelfRC pointers and relink them. */
2171	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2172	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2173	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2174	pgmR3PhysRelinkRamRanges(pVM);
2175	}
2176
2177	/*
2178	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2179	* be mapped and thus not included in the above exercise.
2180	*/
2181	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2182	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2183	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2184
2185	/*
2186	* Update the two page directories with all page table mappings.
2187	* (One or more of them have changed, that's why we're here.)
2188	*/
2189	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2190	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2191	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2192
2193	/* Relocate GC addresses of Page Tables. */
2194	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2195	{
2196	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2197	{
2198	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2199	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2200	}
2201	}
2202
2203	/*
2204	* Dynamic page mapping area.
2205	*/
2206	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2207	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2208	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2209
2210	/*
2211	* The Zero page.
2212	*/
2213	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2214	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2215	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2216	#else
2217	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2218	#endif
2219
2220	/*
2221	* Physical and virtual handlers.
2222	*/
2223	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2224	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2225	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2226	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2227
2228	/*
2229	* The page pool.
2230	*/
2231	pgmR3PoolRelocate(pVM);
2232
2233	#ifdef VBOX_WITH_STATISTICS
2234	/*
2235	* Statistics.
2236	*/
2237	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2238	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2239	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2240	#endif
2241	}
2242
2243
2244	/**
2245	* Callback function for relocating a physical access handler.
2246	*
2247	* @returns 0 (continue enum)
2248	* @param pNode Pointer to a PGMPHYSHANDLER node.
2249	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2250	* not certain the delta will fit in a void pointer for all possible configs.
2251	*/
2252	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2253	{
2254	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2255	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2256	if (pHandler->pfnHandlerRC)
2257	pHandler->pfnHandlerRC += offDelta;
2258	if (pHandler->pvUserRC >= 0x10000)
2259	pHandler->pvUserRC += offDelta;
2260	return 0;
2261	}
2262
2263
2264	/**
2265	* Callback function for relocating a virtual access handler.
2266	*
2267	* @returns 0 (continue enum)
2268	* @param pNode Pointer to a PGMVIRTHANDLER node.
2269	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2270	* not certain the delta will fit in a void pointer for all possible configs.
2271	*/
2272	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2273	{
2274	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2275	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2276	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2277	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2278	Assert(pHandler->pfnHandlerRC);
2279	pHandler->pfnHandlerRC += offDelta;
2280	return 0;
2281	}
2282
2283
2284	/**
2285	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2286	*
2287	* @returns 0 (continue enum)
2288	* @param pNode Pointer to a PGMVIRTHANDLER node.
2289	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2290	* not certain the delta will fit in a void pointer for all possible configs.
2291	*/
2292	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2293	{
2294	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2295	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2296	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2297	Assert(pHandler->pfnHandlerRC);
2298	pHandler->pfnHandlerRC += offDelta;
2299	return 0;
2300	}
2301
2302
2303	/**
2304	* Resets a virtual CPU when unplugged.
2305	*
2306	* @param pVM The VM handle.
2307	* @param pVCpu The virtual CPU handle.
2308	*/
2309	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2310	{
2311	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2312	AssertRC(rc);
2313
2314	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2315	AssertRC(rc);
2316
2317	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2318
2319	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2320
2321	/*
2322	* Re-init other members.
2323	*/
2324	pVCpu->pgm.s.fA20Enabled = true;
2325
2326	/*
2327	* Clear the FFs PGM owns.
2328	*/
2329	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2330	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2331	}
2332
2333
2334	/**
2335	* The VM is being reset.
2336	*
2337	* For the PGM component this means that any PD write monitors
2338	* needs to be removed.
2339	*
2340	* @param pVM VM handle.
2341	*/
2342	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2343	{
2344	int rc;
2345
2346	LogFlow(("PGMR3Reset:\n"));
2347	VM_ASSERT_EMT(pVM);
2348
2349	pgmLock(pVM);
2350
2351	/*
2352	* Unfix any fixed mappings and disable CR3 monitoring.
2353	*/
2354	pVM->pgm.s.fMappingsFixed = false;
2355	pVM->pgm.s.fMappingsFixedRestored = false;
2356	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2357	pVM->pgm.s.cbMappingFixed = 0;
2358
2359	/*
2360	* Exit the guest paging mode before the pgm pool gets reset.
2361	* Important to clean up the amd64 case.
2362	*/
2363	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2364	{
2365	PVMCPU pVCpu = &pVM->aCpus[i];
2366	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2367	AssertRC(rc);
2368	}
2369
2370	#ifdef DEBUG
2371	DBGFR3InfoLog(pVM, "mappings", NULL);
2372	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2373	#endif
2374
2375	/*
2376	* Switch mode back to real mode. (before resetting the pgm pool!)
2377	*/
2378	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2379	{
2380	PVMCPU pVCpu = &pVM->aCpus[i];
2381
2382	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2383	AssertRC(rc);
2384
2385	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2386	}
2387
2388	/*
2389	* Reset the shadow page pool.
2390	*/
2391	pgmR3PoolReset(pVM);
2392
2393	/*
2394	* Re-init various other members and clear the FFs that PGM owns.
2395	*/
2396	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2397	{
2398	PVMCPU pVCpu = &pVM->aCpus[i];
2399
2400	pVCpu->pgm.s.fA20Enabled = true;
2401	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2402	PGMNotifyNxeChanged(pVCpu, false);
2403
2404	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2405	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2406	}
2407
2408	/*
2409	* Reset (zero) RAM and shadow ROM pages.
2410	*/
2411	rc = pgmR3PhysRamReset(pVM);
2412	if (RT_SUCCESS(rc))
2413	rc = pgmR3PhysRomReset(pVM);
2414
2415
2416	pgmUnlock(pVM);
2417	AssertReleaseRC(rc);
2418	}
2419
2420
2421	#ifdef VBOX_STRICT
2422	/**
2423	* VM state change callback for clearing fNoMorePhysWrites after
2424	* a snapshot has been created.
2425	*/
2426	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2427	{
2428	if ( enmState == VMSTATE_RUNNING
2429	\|\| enmState == VMSTATE_RESUMING)
2430	pVM->pgm.s.fNoMorePhysWrites = false;
2431	}
2432	#endif
2433
2434
2435	/**
2436	* Terminates the PGM.
2437	*
2438	* @returns VBox status code.
2439	* @param pVM Pointer to VM structure.
2440	*/
2441	VMMR3DECL(int) PGMR3Term(PVM pVM)
2442	{
2443	/* Must free shared pages here. */
2444	pgmLock(pVM);
2445	pgmR3PhysRamTerm(pVM);
2446	pgmR3PhysRomTerm(pVM);
2447	pgmUnlock(pVM);
2448
2449	PGMDeregisterStringFormatTypes();
2450	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2451	}
2452
2453
2454	/**
2455	* Terminates the per-VCPU PGM.
2456	*
2457	* Termination means cleaning up and freeing all resources,
2458	* the VM it self is at this point powered off or suspended.
2459	*
2460	* @returns VBox status code.
2461	* @param pVM The VM to operate on.
2462	*/
2463	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2464	{
2465	return 0;
2466	}
2467
2468
2469	/**
2470	* Show paging mode.
2471	*
2472	* @param pVM VM Handle.
2473	* @param pHlp The info helpers.
2474	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2475	*/
2476	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2477	{
2478	/* digest argument. */
2479	bool fGuest, fShadow, fHost;
2480	if (pszArgs)
2481	pszArgs = RTStrStripL(pszArgs);
2482	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2483	fShadow = fHost = fGuest = true;
2484	else
2485	{
2486	fShadow = fHost = fGuest = false;
2487	if (strstr(pszArgs, "guest"))
2488	fGuest = true;
2489	if (strstr(pszArgs, "shadow"))
2490	fShadow = true;
2491	if (strstr(pszArgs, "host"))
2492	fHost = true;
2493	}
2494
2495	/** @todo SMP support! */
2496	/* print info. */
2497	if (fGuest)
2498	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2499	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2500	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2501	if (fShadow)
2502	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2503	if (fHost)
2504	{
2505	const char *psz;
2506	switch (pVM->pgm.s.enmHostMode)
2507	{
2508	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2509	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2510	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2511	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2512	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2513	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2514	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2515	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2516	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2517	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2518	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2519	default: psz = "unknown"; break;
2520	}
2521	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2522	}
2523	}
2524
2525
2526	/**
2527	* Dump registered MMIO ranges to the log.
2528	*
2529	* @param pVM VM Handle.
2530	* @param pHlp The info helpers.
2531	* @param pszArgs Arguments, ignored.
2532	*/
2533	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2534	{
2535	NOREF(pszArgs);
2536	pHlp->pfnPrintf(pHlp,
2537	"RAM ranges (pVM=%p)\n"
2538	"%.s %.s\n",
2539	pVM,
2540	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2541	sizeof(RTHCPTR) * 2, "pvHC ");
2542
2543	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2544	pHlp->pfnPrintf(pHlp,
2545	"%RGp-%RGp %RHv %s\n",
2546	pCur->GCPhys,
2547	pCur->GCPhysLast,
2548	pCur->pvR3,
2549	pCur->pszDesc);
2550	}
2551
2552	/**
2553	* Dump the page directory to the log.
2554	*
2555	* @param pVM VM Handle.
2556	* @param pHlp The info helpers.
2557	* @param pszArgs Arguments, ignored.
2558	*/
2559	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2560	{
2561	/** @todo SMP support!! */
2562	PVMCPU pVCpu = &pVM->aCpus[0];
2563
2564	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2565	/* Big pages supported? */
2566	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2567
2568	/* Global pages supported? */
2569	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2570
2571	NOREF(pszArgs);
2572
2573	/*
2574	* Get page directory addresses.
2575	*/
2576	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2577	Assert(pPDSrc);
2578	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2579
2580	/*
2581	* Iterate the page directory.
2582	*/
2583	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2584	{
2585	X86PDE PdeSrc = pPDSrc->a[iPD];
2586	if (PdeSrc.n.u1Present)
2587	{
2588	if (PdeSrc.b.u1Size && fPSE)
2589	pHlp->pfnPrintf(pHlp,
2590	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2591	iPD,
2592	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2593	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2594	else
2595	pHlp->pfnPrintf(pHlp,
2596	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2597	iPD,
2598	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2599	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2600	}
2601	}
2602	}
2603
2604
2605	/**
2606	* Service a VMMCALLRING3_PGM_LOCK call.
2607	*
2608	* @returns VBox status code.
2609	* @param pVM The VM handle.
2610	*/
2611	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2612	{
2613	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2614	AssertRC(rc);
2615	return rc;
2616	}
2617
2618
2619	/**
2620	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2621	*
2622	* @returns PGM_TYPE_*.
2623	* @param pgmMode The mode value to convert.
2624	*/
2625	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2626	{
2627	switch (pgmMode)
2628	{
2629	case PGMMODE_REAL: return PGM_TYPE_REAL;
2630	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2631	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2632	case PGMMODE_PAE:
2633	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2634	case PGMMODE_AMD64:
2635	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2636	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2637	case PGMMODE_EPT: return PGM_TYPE_EPT;
2638	default:
2639	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2640	}
2641	}
2642
2643
2644	/**
2645	* Gets the index into the paging mode data array of a SHW+GST mode.
2646	*
2647	* @returns PGM::paPagingData index.
2648	* @param uShwType The shadow paging mode type.
2649	* @param uGstType The guest paging mode type.
2650	*/
2651	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2652	{
2653	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2654	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2655	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2656	+ (uGstType - PGM_TYPE_REAL);
2657	}
2658
2659
2660	/**
2661	* Gets the index into the paging mode data array of a SHW+GST mode.
2662	*
2663	* @returns PGM::paPagingData index.
2664	* @param enmShw The shadow paging mode.
2665	* @param enmGst The guest paging mode.
2666	*/
2667	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2668	{
2669	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2670	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2671	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2672	}
2673
2674
2675	/**
2676	* Calculates the max data index.
2677	* @returns The number of entries in the paging data array.
2678	*/
2679	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2680	{
2681	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2682	}
2683
2684
2685	/**
2686	* Initializes the paging mode data kept in PGM::paModeData.
2687	*
2688	* @param pVM The VM handle.
2689	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2690	* This is used early in the init process to avoid trouble with PDM
2691	* not being initialized yet.
2692	*/
2693	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2694	{
2695	PPGMMODEDATA pModeData;
2696	int rc;
2697
2698	/*
2699	* Allocate the array on the first call.
2700	*/
2701	if (!pVM->pgm.s.paModeData)
2702	{
2703	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2704	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2705	}
2706
2707	/*
2708	* Initialize the array entries.
2709	*/
2710	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2711	pModeData->uShwType = PGM_TYPE_32BIT;
2712	pModeData->uGstType = PGM_TYPE_REAL;
2713	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2716
2717	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2718	pModeData->uShwType = PGM_TYPE_32BIT;
2719	pModeData->uGstType = PGM_TYPE_PROT;
2720	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2723
2724	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2725	pModeData->uShwType = PGM_TYPE_32BIT;
2726	pModeData->uGstType = PGM_TYPE_32BIT;
2727	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2728	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2729	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2730
2731	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2732	pModeData->uShwType = PGM_TYPE_PAE;
2733	pModeData->uGstType = PGM_TYPE_REAL;
2734	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2736	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2737
2738	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2739	pModeData->uShwType = PGM_TYPE_PAE;
2740	pModeData->uGstType = PGM_TYPE_PROT;
2741	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2743	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744
2745	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2746	pModeData->uShwType = PGM_TYPE_PAE;
2747	pModeData->uGstType = PGM_TYPE_32BIT;
2748	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751
2752	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2753	pModeData->uShwType = PGM_TYPE_PAE;
2754	pModeData->uGstType = PGM_TYPE_PAE;
2755	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758
2759	#ifdef VBOX_WITH_64_BITS_GUESTS
2760	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2761	pModeData->uShwType = PGM_TYPE_AMD64;
2762	pModeData->uGstType = PGM_TYPE_AMD64;
2763	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766	#endif
2767
2768	/* The nested paging mode. */
2769	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2770	pModeData->uShwType = PGM_TYPE_NESTED;
2771	pModeData->uGstType = PGM_TYPE_REAL;
2772	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2773	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2776	pModeData->uShwType = PGM_TYPE_NESTED;
2777	pModeData->uGstType = PGM_TYPE_PROT;
2778	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780
2781	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2782	pModeData->uShwType = PGM_TYPE_NESTED;
2783	pModeData->uGstType = PGM_TYPE_32BIT;
2784	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2785	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2786
2787	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2788	pModeData->uShwType = PGM_TYPE_NESTED;
2789	pModeData->uGstType = PGM_TYPE_PAE;
2790	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2792
2793	#ifdef VBOX_WITH_64_BITS_GUESTS
2794	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2795	pModeData->uShwType = PGM_TYPE_NESTED;
2796	pModeData->uGstType = PGM_TYPE_AMD64;
2797	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2799	#endif
2800
2801	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2802	switch (pVM->pgm.s.enmHostMode)
2803	{
2804	#if HC_ARCH_BITS == 32
2805	case SUPPAGINGMODE_32_BIT:
2806	case SUPPAGINGMODE_32_BIT_GLOBAL:
2807	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2808	{
2809	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2810	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	}
2812	# ifdef VBOX_WITH_64_BITS_GUESTS
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2814	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2815	# endif
2816	break;
2817
2818	case SUPPAGINGMODE_PAE:
2819	case SUPPAGINGMODE_PAE_NX:
2820	case SUPPAGINGMODE_PAE_GLOBAL:
2821	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2822	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2823	{
2824	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2825	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826	}
2827	# ifdef VBOX_WITH_64_BITS_GUESTS
2828	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2829	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	# endif
2831	break;
2832	#endif /* HC_ARCH_BITS == 32 */
2833
2834	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2835	case SUPPAGINGMODE_AMD64:
2836	case SUPPAGINGMODE_AMD64_GLOBAL:
2837	case SUPPAGINGMODE_AMD64_NX:
2838	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2839	# ifdef VBOX_WITH_64_BITS_GUESTS
2840	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2841	# else
2842	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2843	# endif
2844	{
2845	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2846	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2847	}
2848	break;
2849	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2850
2851	default:
2852	AssertFailed();
2853	break;
2854	}
2855
2856	/* Extended paging (EPT) / Intel VT-x */
2857	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2858	pModeData->uShwType = PGM_TYPE_EPT;
2859	pModeData->uGstType = PGM_TYPE_REAL;
2860	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2861	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863
2864	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2865	pModeData->uShwType = PGM_TYPE_EPT;
2866	pModeData->uGstType = PGM_TYPE_PROT;
2867	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2868	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870
2871	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2872	pModeData->uShwType = PGM_TYPE_EPT;
2873	pModeData->uGstType = PGM_TYPE_32BIT;
2874	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877
2878	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2879	pModeData->uShwType = PGM_TYPE_EPT;
2880	pModeData->uGstType = PGM_TYPE_PAE;
2881	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2882	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2883	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884
2885	#ifdef VBOX_WITH_64_BITS_GUESTS
2886	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2887	pModeData->uShwType = PGM_TYPE_EPT;
2888	pModeData->uGstType = PGM_TYPE_AMD64;
2889	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2891	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2892	#endif
2893	return VINF_SUCCESS;
2894	}
2895
2896
2897	/**
2898	* Switch to different (or relocated in the relocate case) mode data.
2899	*
2900	* @param pVM The VM handle.
2901	* @param pVCpu The VMCPU to operate on.
2902	* @param enmShw The the shadow paging mode.
2903	* @param enmGst The the guest paging mode.
2904	*/
2905	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2906	{
2907	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2908
2909	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2910	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2911
2912	/* shadow */
2913	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2914	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2915	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2916	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2917	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2918
2919	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2920	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2921
2922	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2923	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2924
2925
2926	/* guest */
2927	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2928	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2929	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2930	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2931	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2932	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2933	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2934	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2935	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2936	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2937	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2938	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2939
2940	/* both */
2941	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2942	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2943	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2944	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2945	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2946	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2947	#ifdef VBOX_STRICT
2948	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2949	#endif
2950	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2951	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2952
2953	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2954	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2955	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2956	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2957	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2958	#ifdef VBOX_STRICT
2959	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2960	#endif
2961	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2962	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2963
2964	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2965	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2966	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2967	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2968	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2969	#ifdef VBOX_STRICT
2970	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2971	#endif
2972	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2973	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2974	}
2975
2976
2977	/**
2978	* Calculates the shadow paging mode.
2979	*
2980	* @returns The shadow paging mode.
2981	* @param pVM VM handle.
2982	* @param enmGuestMode The guest mode.
2983	* @param enmHostMode The host mode.
2984	* @param enmShadowMode The current shadow mode.
2985	* @param penmSwitcher Where to store the switcher to use.
2986	* VMMSWITCHER_INVALID means no change.
2987	*/
2988	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2989	{
2990	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2991	switch (enmGuestMode)
2992	{
2993	/*
2994	* When switching to real or protected mode we don't change
2995	* anything since it's likely that we'll switch back pretty soon.
2996	*
2997	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2998	* and is supposed to determine which shadow paging and switcher to
2999	* use during init.
3000	*/
3001	case PGMMODE_REAL:
3002	case PGMMODE_PROTECTED:
3003	if ( enmShadowMode != PGMMODE_INVALID
3004	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3005	break; /* (no change) */
3006
3007	switch (enmHostMode)
3008	{
3009	case SUPPAGINGMODE_32_BIT:
3010	case SUPPAGINGMODE_32_BIT_GLOBAL:
3011	enmShadowMode = PGMMODE_32_BIT;
3012	enmSwitcher = VMMSWITCHER_32_TO_32;
3013	break;
3014
3015	case SUPPAGINGMODE_PAE:
3016	case SUPPAGINGMODE_PAE_NX:
3017	case SUPPAGINGMODE_PAE_GLOBAL:
3018	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3019	enmShadowMode = PGMMODE_PAE;
3020	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3021	#ifdef DEBUG_bird
3022	if (RTEnvExist("VBOX_32BIT"))
3023	{
3024	enmShadowMode = PGMMODE_32_BIT;
3025	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3026	}
3027	#endif
3028	break;
3029
3030	case SUPPAGINGMODE_AMD64:
3031	case SUPPAGINGMODE_AMD64_GLOBAL:
3032	case SUPPAGINGMODE_AMD64_NX:
3033	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3034	enmShadowMode = PGMMODE_PAE;
3035	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3036	#ifdef DEBUG_bird
3037	if (RTEnvExist("VBOX_32BIT"))
3038	{
3039	enmShadowMode = PGMMODE_32_BIT;
3040	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3041	}
3042	#endif
3043	break;
3044
3045	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3046	}
3047	break;
3048
3049	case PGMMODE_32_BIT:
3050	switch (enmHostMode)
3051	{
3052	case SUPPAGINGMODE_32_BIT:
3053	case SUPPAGINGMODE_32_BIT_GLOBAL:
3054	enmShadowMode = PGMMODE_32_BIT;
3055	enmSwitcher = VMMSWITCHER_32_TO_32;
3056	break;
3057
3058	case SUPPAGINGMODE_PAE:
3059	case SUPPAGINGMODE_PAE_NX:
3060	case SUPPAGINGMODE_PAE_GLOBAL:
3061	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3062	enmShadowMode = PGMMODE_PAE;
3063	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3064	#ifdef DEBUG_bird
3065	if (RTEnvExist("VBOX_32BIT"))
3066	{
3067	enmShadowMode = PGMMODE_32_BIT;
3068	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3069	}
3070	#endif
3071	break;
3072
3073	case SUPPAGINGMODE_AMD64:
3074	case SUPPAGINGMODE_AMD64_GLOBAL:
3075	case SUPPAGINGMODE_AMD64_NX:
3076	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3077	enmShadowMode = PGMMODE_PAE;
3078	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3079	#ifdef DEBUG_bird
3080	if (RTEnvExist("VBOX_32BIT"))
3081	{
3082	enmShadowMode = PGMMODE_32_BIT;
3083	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3084	}
3085	#endif
3086	break;
3087
3088	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3089	}
3090	break;
3091
3092	case PGMMODE_PAE:
3093	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3094	switch (enmHostMode)
3095	{
3096	case SUPPAGINGMODE_32_BIT:
3097	case SUPPAGINGMODE_32_BIT_GLOBAL:
3098	enmShadowMode = PGMMODE_PAE;
3099	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3100	break;
3101
3102	case SUPPAGINGMODE_PAE:
3103	case SUPPAGINGMODE_PAE_NX:
3104	case SUPPAGINGMODE_PAE_GLOBAL:
3105	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3106	enmShadowMode = PGMMODE_PAE;
3107	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3108	break;
3109
3110	case SUPPAGINGMODE_AMD64:
3111	case SUPPAGINGMODE_AMD64_GLOBAL:
3112	case SUPPAGINGMODE_AMD64_NX:
3113	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3114	enmShadowMode = PGMMODE_PAE;
3115	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3116	break;
3117
3118	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3119	}
3120	break;
3121
3122	case PGMMODE_AMD64:
3123	case PGMMODE_AMD64_NX:
3124	switch (enmHostMode)
3125	{
3126	case SUPPAGINGMODE_32_BIT:
3127	case SUPPAGINGMODE_32_BIT_GLOBAL:
3128	enmShadowMode = PGMMODE_AMD64;
3129	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3130	break;
3131
3132	case SUPPAGINGMODE_PAE:
3133	case SUPPAGINGMODE_PAE_NX:
3134	case SUPPAGINGMODE_PAE_GLOBAL:
3135	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3136	enmShadowMode = PGMMODE_AMD64;
3137	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3138	break;
3139
3140	case SUPPAGINGMODE_AMD64:
3141	case SUPPAGINGMODE_AMD64_GLOBAL:
3142	case SUPPAGINGMODE_AMD64_NX:
3143	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3144	enmShadowMode = PGMMODE_AMD64;
3145	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3146	break;
3147
3148	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3149	}
3150	break;
3151
3152
3153	default:
3154	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3155	*penmSwitcher = VMMSWITCHER_INVALID;
3156	return PGMMODE_INVALID;
3157	}
3158	/* Override the shadow mode is nested paging is active. */
3159	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3160	if (pVM->pgm.s.fNestedPaging)
3161	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3162
3163	*penmSwitcher = enmSwitcher;
3164	return enmShadowMode;
3165	}
3166
3167
3168	/**
3169	* Performs the actual mode change.
3170	* This is called by PGMChangeMode and pgmR3InitPaging().
3171	*
3172	* @returns VBox status code. May suspend or power off the VM on error, but this
3173	* will trigger using FFs and not status codes.
3174	*
3175	* @param pVM VM handle.
3176	* @param pVCpu The VMCPU to operate on.
3177	* @param enmGuestMode The new guest mode. This is assumed to be different from
3178	* the current mode.
3179	*/
3180	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3181	{
3182	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3183	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3184
3185	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3186	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3187
3188	/*
3189	* Calc the shadow mode and switcher.
3190	*/
3191	VMMSWITCHER enmSwitcher;
3192	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3193
3194	#ifdef VBOX_WITH_RAW_MODE
3195	if (enmSwitcher != VMMSWITCHER_INVALID)
3196	{
3197	/*
3198	* Select new switcher.
3199	*/
3200	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3201	if (RT_FAILURE(rc))
3202	{
3203	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3204	return rc;
3205	}
3206	}
3207	#endif
3208
3209	/*
3210	* Exit old mode(s).
3211	*/
3212	#if HC_ARCH_BITS == 32
3213	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3214	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3215	&& enmShadowMode == PGMMODE_NESTED);
3216	#else
3217	const bool fForceShwEnterExit = false;
3218	#endif
3219	/* shadow */
3220	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3221	\|\| fForceShwEnterExit)
3222	{
3223	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3224	if (PGM_SHW_PFN(Exit, pVCpu))
3225	{
3226	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3227	if (RT_FAILURE(rc))
3228	{
3229	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3230	return rc;
3231	}
3232	}
3233
3234	}
3235	else
3236	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3237
3238	/* guest */
3239	if (PGM_GST_PFN(Exit, pVCpu))
3240	{
3241	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3242	if (RT_FAILURE(rc))
3243	{
3244	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3245	return rc;
3246	}
3247	}
3248
3249	/*
3250	* Load new paging mode data.
3251	*/
3252	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3253
3254	/*
3255	* Enter new shadow mode (if changed).
3256	*/
3257	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3258	\|\| fForceShwEnterExit)
3259	{
3260	int rc;
3261	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3262	switch (enmShadowMode)
3263	{
3264	case PGMMODE_32_BIT:
3265	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3266	break;
3267	case PGMMODE_PAE:
3268	case PGMMODE_PAE_NX:
3269	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3270	break;
3271	case PGMMODE_AMD64:
3272	case PGMMODE_AMD64_NX:
3273	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3274	break;
3275	case PGMMODE_NESTED:
3276	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3277	break;
3278	case PGMMODE_EPT:
3279	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3280	break;
3281	case PGMMODE_REAL:
3282	case PGMMODE_PROTECTED:
3283	default:
3284	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3285	return VERR_INTERNAL_ERROR;
3286	}
3287	if (RT_FAILURE(rc))
3288	{
3289	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3290	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3291	return rc;
3292	}
3293	}
3294
3295	/*
3296	* Always flag the necessary updates
3297	*/
3298	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3299
3300	/*
3301	* Enter the new guest and shadow+guest modes.
3302	*/
3303	int rc = -1;
3304	int rc2 = -1;
3305	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3306	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3307	switch (enmGuestMode)
3308	{
3309	case PGMMODE_REAL:
3310	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3311	switch (pVCpu->pgm.s.enmShadowMode)
3312	{
3313	case PGMMODE_32_BIT:
3314	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3315	break;
3316	case PGMMODE_PAE:
3317	case PGMMODE_PAE_NX:
3318	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3319	break;
3320	case PGMMODE_NESTED:
3321	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3322	break;
3323	case PGMMODE_EPT:
3324	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3325	break;
3326	case PGMMODE_AMD64:
3327	case PGMMODE_AMD64_NX:
3328	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3329	default: AssertFailed(); break;
3330	}
3331	break;
3332
3333	case PGMMODE_PROTECTED:
3334	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3335	switch (pVCpu->pgm.s.enmShadowMode)
3336	{
3337	case PGMMODE_32_BIT:
3338	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3339	break;
3340	case PGMMODE_PAE:
3341	case PGMMODE_PAE_NX:
3342	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3343	break;
3344	case PGMMODE_NESTED:
3345	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3346	break;
3347	case PGMMODE_EPT:
3348	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3349	break;
3350	case PGMMODE_AMD64:
3351	case PGMMODE_AMD64_NX:
3352	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3353	default: AssertFailed(); break;
3354	}
3355	break;
3356
3357	case PGMMODE_32_BIT:
3358	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3359	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3360	switch (pVCpu->pgm.s.enmShadowMode)
3361	{
3362	case PGMMODE_32_BIT:
3363	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3364	break;
3365	case PGMMODE_PAE:
3366	case PGMMODE_PAE_NX:
3367	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3368	break;
3369	case PGMMODE_NESTED:
3370	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3371	break;
3372	case PGMMODE_EPT:
3373	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3374	break;
3375	case PGMMODE_AMD64:
3376	case PGMMODE_AMD64_NX:
3377	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3378	default: AssertFailed(); break;
3379	}
3380	break;
3381
3382	case PGMMODE_PAE_NX:
3383	case PGMMODE_PAE:
3384	{
3385	uint32_t u32Dummy, u32Features;
3386
3387	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3388	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3389	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3390	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3391
3392	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3393	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3394	switch (pVCpu->pgm.s.enmShadowMode)
3395	{
3396	case PGMMODE_PAE:
3397	case PGMMODE_PAE_NX:
3398	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3399	break;
3400	case PGMMODE_NESTED:
3401	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3402	break;
3403	case PGMMODE_EPT:
3404	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3405	break;
3406	case PGMMODE_32_BIT:
3407	case PGMMODE_AMD64:
3408	case PGMMODE_AMD64_NX:
3409	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3410	default: AssertFailed(); break;
3411	}
3412	break;
3413	}
3414
3415	#ifdef VBOX_WITH_64_BITS_GUESTS
3416	case PGMMODE_AMD64_NX:
3417	case PGMMODE_AMD64:
3418	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3419	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3420	switch (pVCpu->pgm.s.enmShadowMode)
3421	{
3422	case PGMMODE_AMD64:
3423	case PGMMODE_AMD64_NX:
3424	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3425	break;
3426	case PGMMODE_NESTED:
3427	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3428	break;
3429	case PGMMODE_EPT:
3430	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3431	break;
3432	case PGMMODE_32_BIT:
3433	case PGMMODE_PAE:
3434	case PGMMODE_PAE_NX:
3435	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3436	default: AssertFailed(); break;
3437	}
3438	break;
3439	#endif
3440
3441	default:
3442	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3443	rc = VERR_NOT_IMPLEMENTED;
3444	break;
3445	}
3446
3447	/* status codes. */
3448	AssertRC(rc);
3449	AssertRC(rc2);
3450	if (RT_SUCCESS(rc))
3451	{
3452	rc = rc2;
3453	if (RT_SUCCESS(rc)) /* no informational status codes. */
3454	rc = VINF_SUCCESS;
3455	}
3456
3457	/* Notify HWACCM as well. */
3458	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3459	return rc;
3460	}
3461
3462
3463	/**
3464	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3465	*
3466	* @returns VBox status code, fully asserted.
3467	* @param pVM The VM handle.
3468	* @param pVCpu The VMCPU to operate on.
3469	*/
3470	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3471	{
3472	/* Unmap the old CR3 value before flushing everything. */
3473	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3474	AssertRC(rc);
3475
3476	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3477	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3478	AssertRC(rc);
3479	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3480	return rc;
3481	}
3482
3483
3484	/**
3485	* Called by pgmPoolFlushAllInt after flushing the pool.
3486	*
3487	* @returns VBox status code, fully asserted.
3488	* @param pVM The VM handle.
3489	* @param pVCpu The VMCPU to operate on.
3490	*/
3491	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3492	{
3493	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3494	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3495	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3496	AssertRCReturn(rc, rc);
3497	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3498
3499	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3500	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3501	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3502	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3503	return rc;
3504	}
3505
3506
3507	/**
3508	* Dumps a PAE shadow page table.
3509	*
3510	* @returns VBox status code (VINF_SUCCESS).
3511	* @param pVM The VM handle.
3512	* @param pPT Pointer to the page table.
3513	* @param u64Address The virtual address of the page table starts.
3514	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3515	* @param cMaxDepth The maxium depth.
3516	* @param pHlp Pointer to the output functions.
3517	*/
3518	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3519	{
3520	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3521	{
3522	X86PTEPAE Pte = pPT->a[i];
3523	if (Pte.n.u1Present)
3524	{
3525	pHlp->pfnPrintf(pHlp,
3526	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3527	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3528	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3529	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3530	Pte.n.u1Write ? 'W' : 'R',
3531	Pte.n.u1User ? 'U' : 'S',
3532	Pte.n.u1Accessed ? 'A' : '-',
3533	Pte.n.u1Dirty ? 'D' : '-',
3534	Pte.n.u1Global ? 'G' : '-',
3535	Pte.n.u1WriteThru ? "WT" : "--",
3536	Pte.n.u1CacheDisable? "CD" : "--",
3537	Pte.n.u1PAT ? "AT" : "--",
3538	Pte.n.u1NoExecute ? "NX" : "--",
3539	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3540	Pte.u & RT_BIT(10) ? '1' : '0',
3541	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3542	Pte.u & X86_PTE_PAE_PG_MASK);
3543	}
3544	}
3545	return VINF_SUCCESS;
3546	}
3547
3548
3549	/**
3550	* Dumps a PAE shadow page directory table.
3551	*
3552	* @returns VBox status code (VINF_SUCCESS).
3553	* @param pVM The VM handle.
3554	* @param HCPhys The physical address of the page directory table.
3555	* @param u64Address The virtual address of the page table starts.
3556	* @param cr4 The CR4, PSE is currently used.
3557	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3558	* @param cMaxDepth The maxium depth.
3559	* @param pHlp Pointer to the output functions.
3560	*/
3561	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3562	{
3563	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3564	if (!pPD)
3565	{
3566	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3567	fLongMode ? 16 : 8, u64Address, HCPhys);
3568	return VERR_INVALID_PARAMETER;
3569	}
3570	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3571
3572	int rc = VINF_SUCCESS;
3573	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3574	{
3575	X86PDEPAE Pde = pPD->a[i];
3576	if (Pde.n.u1Present)
3577	{
3578	if (fBigPagesSupported && Pde.b.u1Size)
3579	pHlp->pfnPrintf(pHlp,
3580	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3581	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3582	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3583	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3584	Pde.b.u1Write ? 'W' : 'R',
3585	Pde.b.u1User ? 'U' : 'S',
3586	Pde.b.u1Accessed ? 'A' : '-',
3587	Pde.b.u1Dirty ? 'D' : '-',
3588	Pde.b.u1Global ? 'G' : '-',
3589	Pde.b.u1WriteThru ? "WT" : "--",
3590	Pde.b.u1CacheDisable? "CD" : "--",
3591	Pde.b.u1PAT ? "AT" : "--",
3592	Pde.b.u1NoExecute ? "NX" : "--",
3593	Pde.u & RT_BIT_64(9) ? '1' : '0',
3594	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3595	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3596	Pde.u & X86_PDE_PAE_PG_MASK);
3597	else
3598	{
3599	pHlp->pfnPrintf(pHlp,
3600	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3601	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3602	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3603	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3604	Pde.n.u1Write ? 'W' : 'R',
3605	Pde.n.u1User ? 'U' : 'S',
3606	Pde.n.u1Accessed ? 'A' : '-',
3607	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3608	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3609	Pde.n.u1WriteThru ? "WT" : "--",
3610	Pde.n.u1CacheDisable? "CD" : "--",
3611	Pde.n.u1NoExecute ? "NX" : "--",
3612	Pde.u & RT_BIT_64(9) ? '1' : '0',
3613	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3614	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3615	Pde.u & X86_PDE_PAE_PG_MASK);
3616	if (cMaxDepth >= 1)
3617	{
3618	/** @todo what about using the page pool for mapping PTs? */
3619	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3620	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3621	PX86PTPAE pPT = NULL;
3622	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3623	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3624	else
3625	{
3626	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3627	{
3628	uint64_t off = u64AddressPT - pMap->GCPtr;
3629	if (off < pMap->cb)
3630	{
3631	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3632	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3633	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3634	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3635	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3636	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3637	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3638	}
3639	}
3640	}
3641	int rc2 = VERR_INVALID_PARAMETER;
3642	if (pPT)
3643	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3644	else
3645	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3646	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3647	if (rc2 < rc && RT_SUCCESS(rc))
3648	rc = rc2;
3649	}
3650	}
3651	}
3652	}
3653	return rc;
3654	}
3655
3656
3657	/**
3658	* Dumps a PAE shadow page directory pointer table.
3659	*
3660	* @returns VBox status code (VINF_SUCCESS).
3661	* @param pVM The VM handle.
3662	* @param HCPhys The physical address of the page directory pointer table.
3663	* @param u64Address The virtual address of the page table starts.
3664	* @param cr4 The CR4, PSE is currently used.
3665	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3666	* @param cMaxDepth The maxium depth.
3667	* @param pHlp Pointer to the output functions.
3668	*/
3669	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3670	{
3671	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3672	if (!pPDPT)
3673	{
3674	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3675	fLongMode ? 16 : 8, u64Address, HCPhys);
3676	return VERR_INVALID_PARAMETER;
3677	}
3678
3679	int rc = VINF_SUCCESS;
3680	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3681	for (unsigned i = 0; i < c; i++)
3682	{
3683	X86PDPE Pdpe = pPDPT->a[i];
3684	if (Pdpe.n.u1Present)
3685	{
3686	if (fLongMode)
3687	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3688	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3689	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3690	Pdpe.lm.u1Write ? 'W' : 'R',
3691	Pdpe.lm.u1User ? 'U' : 'S',
3692	Pdpe.lm.u1Accessed ? 'A' : '-',
3693	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3694	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3695	Pdpe.lm.u1WriteThru ? "WT" : "--",
3696	Pdpe.lm.u1CacheDisable? "CD" : "--",
3697	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3698	Pdpe.lm.u1NoExecute ? "NX" : "--",
3699	Pdpe.u & RT_BIT(9) ? '1' : '0',
3700	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3701	Pdpe.u & RT_BIT(11) ? '1' : '0',
3702	Pdpe.u & X86_PDPE_PG_MASK);
3703	else
3704	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3705	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3706	i << X86_PDPT_SHIFT,
3707	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3708	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3709	Pdpe.n.u1WriteThru ? "WT" : "--",
3710	Pdpe.n.u1CacheDisable? "CD" : "--",
3711	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3712	Pdpe.u & RT_BIT(9) ? '1' : '0',
3713	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3714	Pdpe.u & RT_BIT(11) ? '1' : '0',
3715	Pdpe.u & X86_PDPE_PG_MASK);
3716	if (cMaxDepth >= 1)
3717	{
3718	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3719	cr4, fLongMode, cMaxDepth - 1, pHlp);
3720	if (rc2 < rc && RT_SUCCESS(rc))
3721	rc = rc2;
3722	}
3723	}
3724	}
3725	return rc;
3726	}
3727
3728
3729	/**
3730	* Dumps a 32-bit shadow page table.
3731	*
3732	* @returns VBox status code (VINF_SUCCESS).
3733	* @param pVM The VM handle.
3734	* @param HCPhys The physical address of the table.
3735	* @param cr4 The CR4, PSE is currently used.
3736	* @param cMaxDepth The maxium depth.
3737	* @param pHlp Pointer to the output functions.
3738	*/
3739	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3740	{
3741	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3742	if (!pPML4)
3743	{
3744	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3745	return VERR_INVALID_PARAMETER;
3746	}
3747
3748	int rc = VINF_SUCCESS;
3749	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3750	{
3751	X86PML4E Pml4e = pPML4->a[i];
3752	if (Pml4e.n.u1Present)
3753	{
3754	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3755	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3756	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3757	u64Address,
3758	Pml4e.n.u1Write ? 'W' : 'R',
3759	Pml4e.n.u1User ? 'U' : 'S',
3760	Pml4e.n.u1Accessed ? 'A' : '-',
3761	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3762	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3763	Pml4e.n.u1WriteThru ? "WT" : "--",
3764	Pml4e.n.u1CacheDisable? "CD" : "--",
3765	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3766	Pml4e.n.u1NoExecute ? "NX" : "--",
3767	Pml4e.u & RT_BIT(9) ? '1' : '0',
3768	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3769	Pml4e.u & RT_BIT(11) ? '1' : '0',
3770	Pml4e.u & X86_PML4E_PG_MASK);
3771
3772	if (cMaxDepth >= 1)
3773	{
3774	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3775	if (rc2 < rc && RT_SUCCESS(rc))
3776	rc = rc2;
3777	}
3778	}
3779	}
3780	return rc;
3781	}
3782
3783
3784	/**
3785	* Dumps a 32-bit shadow page table.
3786	*
3787	* @returns VBox status code (VINF_SUCCESS).
3788	* @param pVM The VM handle.
3789	* @param pPT Pointer to the page table.
3790	* @param u32Address The virtual address this table starts at.
3791	* @param pHlp Pointer to the output functions.
3792	*/
3793	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3794	{
3795	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3796	{
3797	X86PTE Pte = pPT->a[i];
3798	if (Pte.n.u1Present)
3799	{
3800	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3801	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3802	u32Address + (i << X86_PT_SHIFT),
3803	Pte.n.u1Write ? 'W' : 'R',
3804	Pte.n.u1User ? 'U' : 'S',
3805	Pte.n.u1Accessed ? 'A' : '-',
3806	Pte.n.u1Dirty ? 'D' : '-',
3807	Pte.n.u1Global ? 'G' : '-',
3808	Pte.n.u1WriteThru ? "WT" : "--",
3809	Pte.n.u1CacheDisable? "CD" : "--",
3810	Pte.n.u1PAT ? "AT" : "--",
3811	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3812	Pte.u & RT_BIT(10) ? '1' : '0',
3813	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3814	Pte.u & X86_PDE_PG_MASK);
3815	}
3816	}
3817	return VINF_SUCCESS;
3818	}
3819
3820
3821	/**
3822	* Dumps a 32-bit shadow page directory and page tables.
3823	*
3824	* @returns VBox status code (VINF_SUCCESS).
3825	* @param pVM The VM handle.
3826	* @param cr3 The root of the hierarchy.
3827	* @param cr4 The CR4, PSE is currently used.
3828	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3829	* @param pHlp Pointer to the output functions.
3830	*/
3831	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3832	{
3833	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3834	if (!pPD)
3835	{
3836	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3837	return VERR_INVALID_PARAMETER;
3838	}
3839
3840	int rc = VINF_SUCCESS;
3841	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3842	{
3843	X86PDE Pde = pPD->a[i];
3844	if (Pde.n.u1Present)
3845	{
3846	const uint32_t u32Address = i << X86_PD_SHIFT;
3847	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3848	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3849	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3850	u32Address,
3851	Pde.b.u1Write ? 'W' : 'R',
3852	Pde.b.u1User ? 'U' : 'S',
3853	Pde.b.u1Accessed ? 'A' : '-',
3854	Pde.b.u1Dirty ? 'D' : '-',
3855	Pde.b.u1Global ? 'G' : '-',
3856	Pde.b.u1WriteThru ? "WT" : "--",
3857	Pde.b.u1CacheDisable? "CD" : "--",
3858	Pde.b.u1PAT ? "AT" : "--",
3859	Pde.u & RT_BIT_64(9) ? '1' : '0',
3860	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3861	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3862	Pde.u & X86_PDE4M_PG_MASK);
3863	else
3864	{
3865	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3866	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3867	u32Address,
3868	Pde.n.u1Write ? 'W' : 'R',
3869	Pde.n.u1User ? 'U' : 'S',
3870	Pde.n.u1Accessed ? 'A' : '-',
3871	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3872	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3873	Pde.n.u1WriteThru ? "WT" : "--",
3874	Pde.n.u1CacheDisable? "CD" : "--",
3875	Pde.u & RT_BIT_64(9) ? '1' : '0',
3876	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3877	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3878	Pde.u & X86_PDE_PG_MASK);
3879	if (cMaxDepth >= 1)
3880	{
3881	/** @todo what about using the page pool for mapping PTs? */
3882	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3883	PX86PT pPT = NULL;
3884	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3885	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3886	else
3887	{
3888	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3889	if (u32Address - pMap->GCPtr < pMap->cb)
3890	{
3891	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3892	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3893	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3894	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3895	pPT = pMap->aPTs[iPDE].pPTR3;
3896	}
3897	}
3898	int rc2 = VERR_INVALID_PARAMETER;
3899	if (pPT)
3900	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3901	else
3902	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3903	if (rc2 < rc && RT_SUCCESS(rc))
3904	rc = rc2;
3905	}
3906	}
3907	}
3908	}
3909
3910	return rc;
3911	}
3912
3913
3914	/**
3915	* Dumps a 32-bit shadow page table.
3916	*
3917	* @returns VBox status code (VINF_SUCCESS).
3918	* @param pVM The VM handle.
3919	* @param pPT Pointer to the page table.
3920	* @param u32Address The virtual address this table starts at.
3921	* @param PhysSearch Address to search for.
3922	*/
3923	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3924	{
3925	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3926	{
3927	X86PTE Pte = pPT->a[i];
3928	if (Pte.n.u1Present)
3929	{
3930	Log(( /P R S A D G WT CD AT NX 4M a m d /
3931	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3932	u32Address + (i << X86_PT_SHIFT),
3933	Pte.n.u1Write ? 'W' : 'R',
3934	Pte.n.u1User ? 'U' : 'S',
3935	Pte.n.u1Accessed ? 'A' : '-',
3936	Pte.n.u1Dirty ? 'D' : '-',
3937	Pte.n.u1Global ? 'G' : '-',
3938	Pte.n.u1WriteThru ? "WT" : "--",
3939	Pte.n.u1CacheDisable? "CD" : "--",
3940	Pte.n.u1PAT ? "AT" : "--",
3941	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3942	Pte.u & RT_BIT(10) ? '1' : '0',
3943	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3944	Pte.u & X86_PDE_PG_MASK));
3945
3946	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3947	{
3948	uint64_t fPageShw = 0;
3949	RTHCPHYS pPhysHC = 0;
3950
3951	/** @todo SMP support!! */
3952	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3953	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3954	}
3955	}
3956	}
3957	return VINF_SUCCESS;
3958	}
3959
3960
3961	/**
3962	* Dumps a 32-bit guest page directory and page tables.
3963	*
3964	* @returns VBox status code (VINF_SUCCESS).
3965	* @param pVM The VM handle.
3966	* @param cr3 The root of the hierarchy.
3967	* @param cr4 The CR4, PSE is currently used.
3968	* @param PhysSearch Address to search for.
3969	*/
3970	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3971	{
3972	bool fLongMode = false;
3973	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3974	PX86PD pPD = 0;
3975	PGMPAGEMAPLOCK LockCr3;
3976
3977	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
3978	if ( RT_FAILURE(rc)
3979	\|\| !pPD)
3980	{
3981	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3982	return VERR_INVALID_PARAMETER;
3983	}
3984
3985	Log(("cr3=%08x cr4=%08x%s\n"
3986	"%-*s P - Present\n"
3987	"%-*s \| R/W - Read (0) / Write (1)\n"
3988	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3989	"%-*s \| \| \| A - Accessed\n"
3990	"%-*s \| \| \| \| D - Dirty\n"
3991	"%-*s \| \| \| \| \| G - Global\n"
3992	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3993	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3994	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3995	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3996	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3997	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3998	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3999	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4000	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4001	- W U - - - -- -- -- -- -- 010 */
4002	, cr3, cr4, fLongMode ? " Long Mode" : "",
4003	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4004	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4005
4006	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4007	{
4008	X86PDE Pde = pPD->a[i];
4009	if (Pde.n.u1Present)
4010	{
4011	const uint32_t u32Address = i << X86_PD_SHIFT;
4012
4013	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4014	Log(( /P R S A D G WT CD AT NX 4M a m d /
4015	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4016	u32Address,
4017	Pde.b.u1Write ? 'W' : 'R',
4018	Pde.b.u1User ? 'U' : 'S',
4019	Pde.b.u1Accessed ? 'A' : '-',
4020	Pde.b.u1Dirty ? 'D' : '-',
4021	Pde.b.u1Global ? 'G' : '-',
4022	Pde.b.u1WriteThru ? "WT" : "--",
4023	Pde.b.u1CacheDisable? "CD" : "--",
4024	Pde.b.u1PAT ? "AT" : "--",
4025	Pde.u & RT_BIT(9) ? '1' : '0',
4026	Pde.u & RT_BIT(10) ? '1' : '0',
4027	Pde.u & RT_BIT(11) ? '1' : '0',
4028	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4029	/** @todo PhysSearch */
4030	else
4031	{
4032	Log(( /P R S A D G WT CD AT NX 4M a m d /
4033	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4034	u32Address,
4035	Pde.n.u1Write ? 'W' : 'R',
4036	Pde.n.u1User ? 'U' : 'S',
4037	Pde.n.u1Accessed ? 'A' : '-',
4038	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4039	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4040	Pde.n.u1WriteThru ? "WT" : "--",
4041	Pde.n.u1CacheDisable? "CD" : "--",
4042	Pde.u & RT_BIT(9) ? '1' : '0',
4043	Pde.u & RT_BIT(10) ? '1' : '0',
4044	Pde.u & RT_BIT(11) ? '1' : '0',
4045	Pde.u & X86_PDE_PG_MASK));
4046	////if (cMaxDepth >= 1)
4047	{
4048	/** @todo what about using the page pool for mapping PTs? */
4049	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4050	PX86PT pPT = NULL;
4051	PGMPAGEMAPLOCK LockPT;
4052
4053	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
4054
4055	int rc2 = VERR_INVALID_PARAMETER;
4056	if (pPT)
4057	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4058	else
4059	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4060
4061	if (rc == VINF_SUCCESS)
4062	PGMPhysReleasePageMappingLock(pVM, &LockPT);
4063
4064	if (rc2 < rc && RT_SUCCESS(rc))
4065	rc = rc2;
4066	}
4067	}
4068	}
4069	}
4070	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
4071	return rc;
4072	}
4073
4074
4075	/**
4076	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4077	*
4078	* @returns VBox status code (VINF_SUCCESS).
4079	* @param pVM The VM handle.
4080	* @param cr3 The root of the hierarchy.
4081	* @param cr4 The cr4, only PAE and PSE is currently used.
4082	* @param fLongMode Set if long mode, false if not long mode.
4083	* @param cMaxDepth Number of levels to dump.
4084	* @param pHlp Pointer to the output functions.
4085	*/
4086	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4087	{
4088	if (!pHlp)
4089	pHlp = DBGFR3InfoLogHlp();
4090	if (!cMaxDepth)
4091	return VINF_SUCCESS;
4092	const unsigned cch = fLongMode ? 16 : 8;
4093	pHlp->pfnPrintf(pHlp,
4094	"cr3=%08x cr4=%08x%s\n"
4095	"%-*s P - Present\n"
4096	"%-*s \| R/W - Read (0) / Write (1)\n"
4097	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4098	"%-*s \| \| \| A - Accessed\n"
4099	"%-*s \| \| \| \| D - Dirty\n"
4100	"%-*s \| \| \| \| \| G - Global\n"
4101	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4102	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4103	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4104	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4105	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4106	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4107	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4108	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4109	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4110	- W U - - - -- -- -- -- -- 010 */
4111	, cr3, cr4, fLongMode ? " Long Mode" : "",
4112	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4113	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4114	if (cr4 & X86_CR4_PAE)
4115	{
4116	if (fLongMode)
4117	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4118	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4119	}
4120	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4121	}
4122
4123	#ifdef VBOX_WITH_DEBUGGER
4124
4125	/**
4126	* The '.pgmram' command.
4127	*
4128	* @returns VBox status.
4129	* @param pCmd Pointer to the command descriptor (as registered).
4130	* @param pCmdHlp Pointer to command helper functions.
4131	* @param pVM Pointer to the current VM (if any).
4132	* @param paArgs Pointer to (readonly) array of arguments.
4133	* @param cArgs Number of arguments in the array.
4134	*/
4135	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4136	{
4137	/*
4138	* Validate input.
4139	*/
4140	if (!pVM)
4141	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4142	if (!pVM->pgm.s.pRamRangesRC)
4143	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4144
4145	/*
4146	* Dump the ranges.
4147	*/
4148	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4149	PPGMRAMRANGE pRam;
4150	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4151	{
4152	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4153	"%RGp - %RGp %p\n",
4154	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4155	if (RT_FAILURE(rc))
4156	return rc;
4157	}
4158
4159	return VINF_SUCCESS;
4160	}
4161
4162
4163	/**
4164	* The '.pgmerror' and '.pgmerroroff' commands.
4165	*
4166	* @returns VBox status.
4167	* @param pCmd Pointer to the command descriptor (as registered).
4168	* @param pCmdHlp Pointer to command helper functions.
4169	* @param pVM Pointer to the current VM (if any).
4170	* @param paArgs Pointer to (readonly) array of arguments.
4171	* @param cArgs Number of arguments in the array.
4172	*/
4173	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4174	{
4175	/*
4176	* Validate input.
4177	*/
4178	if (!pVM)
4179	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4180	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4181	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4182
4183	if (!cArgs)
4184	{
4185	/*
4186	* Print the list of error injection locations with status.
4187	*/
4188	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4189	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4190	}
4191	else
4192	{
4193
4194	/*
4195	* String switch on where to inject the error.
4196	*/
4197	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4198	const char *pszWhere = paArgs[0].u.pszString;
4199	if (!strcmp(pszWhere, "handy"))
4200	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4201	else
4202	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4203	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4204	}
4205	return VINF_SUCCESS;
4206	}
4207
4208
4209	/**
4210	* The '.pgmsync' command.
4211	*
4212	* @returns VBox status.
4213	* @param pCmd Pointer to the command descriptor (as registered).
4214	* @param pCmdHlp Pointer to command helper functions.
4215	* @param pVM Pointer to the current VM (if any).
4216	* @param paArgs Pointer to (readonly) array of arguments.
4217	* @param cArgs Number of arguments in the array.
4218	*/
4219	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4220	{
4221	/** @todo SMP support */
4222	PVMCPU pVCpu = &pVM->aCpus[0];
4223
4224	/*
4225	* Validate input.
4226	*/
4227	if (!pVM)
4228	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4229
4230	/*
4231	* Force page directory sync.
4232	*/
4233	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4234
4235	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4236	if (RT_FAILURE(rc))
4237	return rc;
4238
4239	return VINF_SUCCESS;
4240	}
4241
4242
4243	#ifdef VBOX_STRICT
4244	/**
4245	* The '.pgmassertcr3' command.
4246	*
4247	* @returns VBox status.
4248	* @param pCmd Pointer to the command descriptor (as registered).
4249	* @param pCmdHlp Pointer to command helper functions.
4250	* @param pVM Pointer to the current VM (if any).
4251	* @param paArgs Pointer to (readonly) array of arguments.
4252	* @param cArgs Number of arguments in the array.
4253	*/
4254	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4255	{
4256	/** @todo SMP support!! */
4257	PVMCPU pVCpu = &pVM->aCpus[0];
4258
4259	/*
4260	* Validate input.
4261	*/
4262	if (!pVM)
4263	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4264
4265	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4266	if (RT_FAILURE(rc))
4267	return rc;
4268
4269	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4270
4271	return VINF_SUCCESS;
4272	}
4273	#endif /* VBOX_STRICT */
4274
4275
4276	/**
4277	* The '.pgmsyncalways' command.
4278	*
4279	* @returns VBox status.
4280	* @param pCmd Pointer to the command descriptor (as registered).
4281	* @param pCmdHlp Pointer to command helper functions.
4282	* @param pVM Pointer to the current VM (if any).
4283	* @param paArgs Pointer to (readonly) array of arguments.
4284	* @param cArgs Number of arguments in the array.
4285	*/
4286	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4287	{
4288	/** @todo SMP support!! */
4289	PVMCPU pVCpu = &pVM->aCpus[0];
4290
4291	/*
4292	* Validate input.
4293	*/
4294	if (!pVM)
4295	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4296
4297	/*
4298	* Force page directory sync.
4299	*/
4300	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4301	{
4302	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4303	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4304	}
4305	else
4306	{
4307	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4308	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4309	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4310	}
4311	}
4312
4313
4314	/**
4315	* The '.pgmsyncalways' command.
4316	*
4317	* @returns VBox status.
4318	* @param pCmd Pointer to the command descriptor (as registered).
4319	* @param pCmdHlp Pointer to command helper functions.
4320	* @param pVM Pointer to the current VM (if any).
4321	* @param paArgs Pointer to (readonly) array of arguments.
4322	* @param cArgs Number of arguments in the array.
4323	*/
4324	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4325	{
4326	/*
4327	* Validate input.
4328	*/
4329	if (!pVM)
4330	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4331	if ( cArgs < 1
4332	\|\| cArgs > 2
4333	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4334	\|\| ( cArgs > 1
4335	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4336	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4337	if ( cArgs >= 2
4338	&& strcmp(paArgs[1].u.pszString, "nozero"))
4339	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4340	bool fIncZeroPgs = cArgs < 2;
4341
4342	/*
4343	* Open the output file and get the ram parameters.
4344	*/
4345	RTFILE hFile;
4346	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4347	if (RT_FAILURE(rc))
4348	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4349
4350	uint32_t cbRamHole = 0;
4351	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4352	uint64_t cbRam = 0;
4353	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4354	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4355
4356	/*
4357	* Dump the physical memory, page by page.
4358	*/
4359	RTGCPHYS GCPhys = 0;
4360	char abZeroPg[PAGE_SIZE];
4361	RT_ZERO(abZeroPg);
4362
4363	pgmLock(pVM);
4364	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4365	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4366	pRam = pRam->pNextR3)
4367	{
4368	/* fill the gap */
4369	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4370	{
4371	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4372	{
4373	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4374	GCPhys += PAGE_SIZE;
4375	}
4376	}
4377
4378	PCPGMPAGE pPage = &pRam->aPages[0];
4379	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4380	{
4381	if ( PGM_PAGE_IS_ZERO(pPage)
4382	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4383	{
4384	if (fIncZeroPgs)
4385	{
4386	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4387	if (RT_FAILURE(rc))
4388	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4389	}
4390	}
4391	else
4392	{
4393	switch (PGM_PAGE_GET_TYPE(pPage))
4394	{
4395	case PGMPAGETYPE_RAM:
4396	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4397	case PGMPAGETYPE_ROM:
4398	case PGMPAGETYPE_MMIO2:
4399	{
4400	void const *pvPage;
4401	PGMPAGEMAPLOCK Lock;
4402	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4403	if (RT_SUCCESS(rc))
4404	{
4405	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4406	PGMPhysReleasePageMappingLock(pVM, &Lock);
4407	if (RT_FAILURE(rc))
4408	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4409	}
4410	else
4411	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4412	break;
4413	}
4414
4415	default:
4416	AssertFailed();
4417	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4418	case PGMPAGETYPE_MMIO:
4419	if (fIncZeroPgs)
4420	{
4421	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4422	if (RT_FAILURE(rc))
4423	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4424	}
4425	break;
4426	}
4427	}
4428
4429
4430	/* advance */
4431	GCPhys += PAGE_SIZE;
4432	pPage++;
4433	}
4434	}
4435	pgmUnlock(pVM);
4436
4437	RTFileClose(hFile);
4438	if (RT_SUCCESS(rc))
4439	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4440	return VINF_SUCCESS;
4441	}
4442
4443	#endif /* VBOX_WITH_DEBUGGER */
4444
4445	/**
4446	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4447	*/
4448	typedef struct PGMCHECKINTARGS
4449	{
4450	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4451	PPGMPHYSHANDLER pPrevPhys;
4452	PPGMVIRTHANDLER pPrevVirt;
4453	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4454	PVM pVM;
4455	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4456
4457	/**
4458	* Validate a node in the physical handler tree.
4459	*
4460	* @returns 0 on if ok, other wise 1.
4461	* @param pNode The handler node.
4462	* @param pvUser pVM.
4463	*/
4464	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4465	{
4466	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4467	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4468	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4469	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4470	AssertReleaseMsg( !pArgs->pPrevPhys
4471	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4472	("pPrevPhys=%p %RGp-%RGp %s\n"
4473	" pCur=%p %RGp-%RGp %s\n",
4474	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4475	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4476	pArgs->pPrevPhys = pCur;
4477	return 0;
4478	}
4479
4480
4481	/**
4482	* Validate a node in the virtual handler tree.
4483	*
4484	* @returns 0 on if ok, other wise 1.
4485	* @param pNode The handler node.
4486	* @param pvUser pVM.
4487	*/
4488	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4489	{
4490	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4491	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4492	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4493	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4494	AssertReleaseMsg( !pArgs->pPrevVirt
4495	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4496	("pPrevVirt=%p %RGv-%RGv %s\n"
4497	" pCur=%p %RGv-%RGv %s\n",
4498	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4499	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4500	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4501	{
4502	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4503	("pCur=%p %RGv-%RGv %s\n"
4504	"iPage=%d offVirtHandle=%#x expected %#x\n",
4505	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4506	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4507	}
4508	pArgs->pPrevVirt = pCur;
4509	return 0;
4510	}
4511
4512
4513	/**
4514	* Validate a node in the virtual handler tree.
4515	*
4516	* @returns 0 on if ok, other wise 1.
4517	* @param pNode The handler node.
4518	* @param pvUser pVM.
4519	*/
4520	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4521	{
4522	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4523	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4524	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4525	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4526	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4527	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4528	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4529	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4530	" pCur=%p %RGp-%RGp\n",
4531	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4532	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4533	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4534	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4535	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4536	" pCur=%p %RGp-%RGp\n",
4537	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4538	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4539	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4540	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4541	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4542	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4543	{
4544	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4545	for (;;)
4546	{
4547	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4548	AssertReleaseMsg(pCur2 != pCur,
4549	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4550	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4551	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4552	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4553	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4554	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4555	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4556	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4557	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4558	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4559	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4560	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4561	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4562	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4563	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4564	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4565	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4566	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4567	break;
4568	}
4569	}
4570
4571	pArgs->pPrevPhys2Virt = pCur;
4572	return 0;
4573	}
4574
4575
4576	/**
4577	* Perform an integrity check on the PGM component.
4578	*
4579	* @returns VINF_SUCCESS if everything is fine.
4580	* @returns VBox error status after asserting on integrity breach.
4581	* @param pVM The VM handle.
4582	*/
4583	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4584	{
4585	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4586
4587	/*
4588	* Check the trees.
4589	*/
4590	int cErrors = 0;
4591	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4592	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4593	PGMCHECKINTARGS Args = s_LeftToRight;
4594	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4595	Args = s_RightToLeft;
4596	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4597	Args = s_LeftToRight;
4598	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4599	Args = s_RightToLeft;
4600	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4601	Args = s_LeftToRight;
4602	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4603	Args = s_RightToLeft;
4604	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4605	Args = s_LeftToRight;
4606	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4607	Args = s_RightToLeft;
4608	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4609
4610	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4611	}
4612

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 31296

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