PGM.cpp@ 31589

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1	/* $Id: PGM.cpp 31565 2010-08-11 12:47:07Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
484	* however on 32-bit darwin the ring-0 code is running in a different memory
485	* context and therefore needs a separate cache. In raw-mode context we also
486	* need a separate cache. The 32-bit darwin mapping cache and the one for
487	* raw-mode context share a lot of code, see PGMRZDYNMAP.
488	*
489	*
490	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
491	*
492	* We've considered implementing the ring-3 mapping cache page based but found
493	* that this was bother some when one had to take into account TLBs+SMP and
494	* portability (missing the necessary APIs on several platforms). There were
495	* also some performance concerns with this approach which hadn't quite been
496	* worked out.
497	*
498	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
499	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
500	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
501	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
502	* costly than a single page, although how much more costly is uncertain. We'll
503	* try address this by using a very big cache, preferably bigger than the actual
504	* VM RAM size if possible. The current VM RAM sizes should give some idea for
505	* 32-bit boxes, while on 64-bit we can probably get away with employing an
506	* unlimited cache.
507	*
508	* The cache have to parts, as already indicated, the ring-3 side and the
509	* ring-0 side.
510	*
511	* The ring-0 will be tied to the page allocator since it will operate on the
512	* memory objects it contains. It will therefore require the first ring-0 mutex
513	* discussed in @ref subsec_pgmPhys_Serializing. We
514	* some double house keeping wrt to who has mapped what I think, since both
515	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
516	*
517	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
518	* require anyone that desires to do changes to the mapping cache to do that
519	* from within this critsect. Alternatively, we could employ a separate critsect
520	* for serializing changes to the mapping cache as this would reduce potential
521	* contention with other threads accessing mappings unrelated to the changes
522	* that are in process. We can see about this later, contention will show
523	* up in the statistics anyway, so it'll be simple to tell.
524	*
525	* The organization of the ring-3 part will be very much like how the allocation
526	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
527	* having to walk the tree all the time, we'll have a couple of lookaside entries
528	* like in we do for I/O ports and MMIO in IOM.
529	*
530	* The simplified flow of a PGMPhysRead/Write function:
531	* -# Enter the PGM critsect.
532	* -# Lookup GCPhys in the ram ranges and get the Page ID.
533	* -# Calc the Allocation Chunk ID from the Page ID.
534	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
535	* If not found in cache:
536	* -# Call ring-0 and request it to be mapped and supply
537	* a chunk to be unmapped if the cache is maxed out already.
538	* -# Insert the new mapping into the AVL tree (id + R3 address).
539	* -# Update the relevant lookaside entry and return the mapping address.
540	* -# Do the read/write according to monitoring flags and everything.
541	* -# Leave the critsect.
542	*
543	*
544	* @section sec_pgmPhys_Fallback Fallback
545	*
546	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
547	* API and thus require a fallback.
548	*
549	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
550	* will return to the ring-3 caller (and later ring-0) and asking it to seed
551	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
552	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
553	* "SeededAllocPages" call to ring-0.
554	*
555	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
556	* all page sharing (zero page detection will continue). It will also force
557	* all allocations to come from the VM which seeded the page. Both these
558	* measures are taken to make sure that there will never be any need for
559	* mapping anything into ring-3 - everything will be mapped already.
560	*
561	* Whether we'll continue to use the current MM locked memory management
562	* for this I don't quite know (I'd prefer not to and just ditch that all
563	* togther), we'll see what's simplest to do.
564	*
565	*
566	*
567	* @section sec_pgmPhys_Changes Changes
568	*
569	* Breakdown of the changes involved?
570	*/
571
572	/*******************************************************************************
573	* Header Files *
574	*******************************************************************************/
575	#define LOG_GROUP LOG_GROUP_PGM
576	#include <VBox/dbgf.h>
577	#include <VBox/pgm.h>
578	#include <VBox/cpum.h>
579	#include <VBox/iom.h>
580	#include <VBox/sup.h>
581	#include <VBox/mm.h>
582	#include <VBox/em.h>
583	#include <VBox/stam.h>
584	#include <VBox/rem.h>
585	#include <VBox/selm.h>
586	#include <VBox/ssm.h>
587	#include <VBox/hwaccm.h>
588	#include "PGMInternal.h"
589	#include <VBox/vm.h>
590	#include "PGMInline.h"
591
592	#include <VBox/dbg.h>
593	#include <VBox/param.h>
594	#include <VBox/err.h>
595
596	#include <iprt/asm.h>
597	#include <iprt/asm-amd64-x86.h>
598	#include <iprt/assert.h>
599	#include <iprt/env.h>
600	#include <iprt/mem.h>
601	#include <iprt/file.h>
602	#include <iprt/string.h>
603	#include <iprt/thread.h>
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static int pgmR3InitStats(PVM pVM);
611	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
617	#ifdef VBOX_STRICT
618	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
619	#endif
620	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
621	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
622	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
623
624	#ifdef VBOX_WITH_DEBUGGER
625	/** @todo Convert the first two commands to 'info' items. */
626	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
627	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
628	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
629	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
630	# ifdef VBOX_STRICT
631	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	# endif
633	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	#endif
635
636
637	/*******************************************************************************
638	* Global Variables *
639	*******************************************************************************/
640	#ifdef VBOX_WITH_DEBUGGER
641	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
642	static const DBGCVARDESC g_aPgmErrorArgs[] =
643	{
644	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
645	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
646	};
647
648	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
649	{
650	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
651	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
652	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
653	};
654
655	/** Command descriptors. */
656	static const DBGCCMD g_aCmds[] =
657	{
658	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
659	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
660	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
661	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
662	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
663	#ifdef VBOX_STRICT
664	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
665	#endif
666	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
667	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
668	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
669	#endif
670	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
671	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
672	};
673	#endif
674
675
676
677
678	/*
679	* Shadow - 32-bit mode
680	*/
681	#define PGM_SHW_TYPE PGM_TYPE_32BIT
682	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
683	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
684	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
685	#include "PGMShw.h"
686
687	/* Guest - real mode */
688	#define PGM_GST_TYPE PGM_TYPE_REAL
689	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
690	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
691	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
692	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
693	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
694	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
695	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
696	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
697	#include "PGMBth.h"
698	#include "PGMGstDefs.h"
699	#include "PGMGst.h"
700	#undef BTH_PGMPOOLKIND_PT_FOR_PT
701	#undef BTH_PGMPOOLKIND_ROOT
702	#undef PGM_BTH_NAME
703	#undef PGM_BTH_NAME_RC_STR
704	#undef PGM_BTH_NAME_R0_STR
705	#undef PGM_GST_TYPE
706	#undef PGM_GST_NAME
707	#undef PGM_GST_NAME_RC_STR
708	#undef PGM_GST_NAME_R0_STR
709
710	/* Guest - protected mode */
711	#define PGM_GST_TYPE PGM_TYPE_PROT
712	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
713	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
714	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
715	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
716	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
717	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
718	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
719	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
720	#include "PGMBth.h"
721	#include "PGMGstDefs.h"
722	#include "PGMGst.h"
723	#undef BTH_PGMPOOLKIND_PT_FOR_PT
724	#undef BTH_PGMPOOLKIND_ROOT
725	#undef PGM_BTH_NAME
726	#undef PGM_BTH_NAME_RC_STR
727	#undef PGM_BTH_NAME_R0_STR
728	#undef PGM_GST_TYPE
729	#undef PGM_GST_NAME
730	#undef PGM_GST_NAME_RC_STR
731	#undef PGM_GST_NAME_R0_STR
732
733	/* Guest - 32-bit mode */
734	#define PGM_GST_TYPE PGM_TYPE_32BIT
735	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
736	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
737	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
738	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
739	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
740	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
741	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
742	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
743	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
744	#include "PGMBth.h"
745	#include "PGMGstDefs.h"
746	#include "PGMGst.h"
747	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
748	#undef BTH_PGMPOOLKIND_PT_FOR_PT
749	#undef BTH_PGMPOOLKIND_ROOT
750	#undef PGM_BTH_NAME
751	#undef PGM_BTH_NAME_RC_STR
752	#undef PGM_BTH_NAME_R0_STR
753	#undef PGM_GST_TYPE
754	#undef PGM_GST_NAME
755	#undef PGM_GST_NAME_RC_STR
756	#undef PGM_GST_NAME_R0_STR
757
758	#undef PGM_SHW_TYPE
759	#undef PGM_SHW_NAME
760	#undef PGM_SHW_NAME_RC_STR
761	#undef PGM_SHW_NAME_R0_STR
762
763
764	/*
765	* Shadow - PAE mode
766	*/
767	#define PGM_SHW_TYPE PGM_TYPE_PAE
768	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
769	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
770	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
771	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
772	#include "PGMShw.h"
773
774	/* Guest - real mode */
775	#define PGM_GST_TYPE PGM_TYPE_REAL
776	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
777	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
778	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
779	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
780	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
781	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
782	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
783	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
784	#include "PGMGstDefs.h"
785	#include "PGMBth.h"
786	#undef BTH_PGMPOOLKIND_PT_FOR_PT
787	#undef BTH_PGMPOOLKIND_ROOT
788	#undef PGM_BTH_NAME
789	#undef PGM_BTH_NAME_RC_STR
790	#undef PGM_BTH_NAME_R0_STR
791	#undef PGM_GST_TYPE
792	#undef PGM_GST_NAME
793	#undef PGM_GST_NAME_RC_STR
794	#undef PGM_GST_NAME_R0_STR
795
796	/* Guest - protected mode */
797	#define PGM_GST_TYPE PGM_TYPE_PROT
798	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
799	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
800	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
801	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
802	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
803	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
804	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
805	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
806	#include "PGMGstDefs.h"
807	#include "PGMBth.h"
808	#undef BTH_PGMPOOLKIND_PT_FOR_PT
809	#undef BTH_PGMPOOLKIND_ROOT
810	#undef PGM_BTH_NAME
811	#undef PGM_BTH_NAME_RC_STR
812	#undef PGM_BTH_NAME_R0_STR
813	#undef PGM_GST_TYPE
814	#undef PGM_GST_NAME
815	#undef PGM_GST_NAME_RC_STR
816	#undef PGM_GST_NAME_R0_STR
817
818	/* Guest - 32-bit mode */
819	#define PGM_GST_TYPE PGM_TYPE_32BIT
820	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
821	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
822	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
823	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
824	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
825	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
826	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
827	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
828	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
829	#include "PGMGstDefs.h"
830	#include "PGMBth.h"
831	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
832	#undef BTH_PGMPOOLKIND_PT_FOR_PT
833	#undef BTH_PGMPOOLKIND_ROOT
834	#undef PGM_BTH_NAME
835	#undef PGM_BTH_NAME_RC_STR
836	#undef PGM_BTH_NAME_R0_STR
837	#undef PGM_GST_TYPE
838	#undef PGM_GST_NAME
839	#undef PGM_GST_NAME_RC_STR
840	#undef PGM_GST_NAME_R0_STR
841
842	/* Guest - PAE mode */
843	#define PGM_GST_TYPE PGM_TYPE_PAE
844	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
845	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
846	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
847	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
848	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
849	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
850	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
851	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
852	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
853	#include "PGMBth.h"
854	#include "PGMGstDefs.h"
855	#include "PGMGst.h"
856	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
857	#undef BTH_PGMPOOLKIND_PT_FOR_PT
858	#undef BTH_PGMPOOLKIND_ROOT
859	#undef PGM_BTH_NAME
860	#undef PGM_BTH_NAME_RC_STR
861	#undef PGM_BTH_NAME_R0_STR
862	#undef PGM_GST_TYPE
863	#undef PGM_GST_NAME
864	#undef PGM_GST_NAME_RC_STR
865	#undef PGM_GST_NAME_R0_STR
866
867	#undef PGM_SHW_TYPE
868	#undef PGM_SHW_NAME
869	#undef PGM_SHW_NAME_RC_STR
870	#undef PGM_SHW_NAME_R0_STR
871
872
873	/*
874	* Shadow - AMD64 mode
875	*/
876	#define PGM_SHW_TYPE PGM_TYPE_AMD64
877	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
878	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
879	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
880	#include "PGMShw.h"
881
882	#ifdef VBOX_WITH_64_BITS_GUESTS
883	/* Guest - AMD64 mode */
884	# define PGM_GST_TYPE PGM_TYPE_AMD64
885	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
886	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
887	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
888	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
889	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
890	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
891	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
892	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
893	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
894	# include "PGMBth.h"
895	# include "PGMGstDefs.h"
896	# include "PGMGst.h"
897	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
898	# undef BTH_PGMPOOLKIND_PT_FOR_PT
899	# undef BTH_PGMPOOLKIND_ROOT
900	# undef PGM_BTH_NAME
901	# undef PGM_BTH_NAME_RC_STR
902	# undef PGM_BTH_NAME_R0_STR
903	# undef PGM_GST_TYPE
904	# undef PGM_GST_NAME
905	# undef PGM_GST_NAME_RC_STR
906	# undef PGM_GST_NAME_R0_STR
907	#endif /* VBOX_WITH_64_BITS_GUESTS */
908
909	#undef PGM_SHW_TYPE
910	#undef PGM_SHW_NAME
911	#undef PGM_SHW_NAME_RC_STR
912	#undef PGM_SHW_NAME_R0_STR
913
914
915	/*
916	* Shadow - Nested paging mode
917	*/
918	#define PGM_SHW_TYPE PGM_TYPE_NESTED
919	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
920	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
921	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
922	#include "PGMShw.h"
923
924	/* Guest - real mode */
925	#define PGM_GST_TYPE PGM_TYPE_REAL
926	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
927	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
928	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
929	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
930	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
931	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
932	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
933	#include "PGMGstDefs.h"
934	#include "PGMBth.h"
935	#undef BTH_PGMPOOLKIND_PT_FOR_PT
936	#undef PGM_BTH_NAME
937	#undef PGM_BTH_NAME_RC_STR
938	#undef PGM_BTH_NAME_R0_STR
939	#undef PGM_GST_TYPE
940	#undef PGM_GST_NAME
941	#undef PGM_GST_NAME_RC_STR
942	#undef PGM_GST_NAME_R0_STR
943
944	/* Guest - protected mode */
945	#define PGM_GST_TYPE PGM_TYPE_PROT
946	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
947	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
948	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
949	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
950	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
951	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
952	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
953	#include "PGMGstDefs.h"
954	#include "PGMBth.h"
955	#undef BTH_PGMPOOLKIND_PT_FOR_PT
956	#undef PGM_BTH_NAME
957	#undef PGM_BTH_NAME_RC_STR
958	#undef PGM_BTH_NAME_R0_STR
959	#undef PGM_GST_TYPE
960	#undef PGM_GST_NAME
961	#undef PGM_GST_NAME_RC_STR
962	#undef PGM_GST_NAME_R0_STR
963
964	/* Guest - 32-bit mode */
965	#define PGM_GST_TYPE PGM_TYPE_32BIT
966	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
967	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
968	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
969	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
970	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
971	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
972	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
973	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
974	#include "PGMGstDefs.h"
975	#include "PGMBth.h"
976	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
977	#undef BTH_PGMPOOLKIND_PT_FOR_PT
978	#undef PGM_BTH_NAME
979	#undef PGM_BTH_NAME_RC_STR
980	#undef PGM_BTH_NAME_R0_STR
981	#undef PGM_GST_TYPE
982	#undef PGM_GST_NAME
983	#undef PGM_GST_NAME_RC_STR
984	#undef PGM_GST_NAME_R0_STR
985
986	/* Guest - PAE mode */
987	#define PGM_GST_TYPE PGM_TYPE_PAE
988	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
989	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
990	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
991	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
992	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
993	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
994	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
995	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
996	#include "PGMGstDefs.h"
997	#include "PGMBth.h"
998	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
999	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1000	#undef PGM_BTH_NAME
1001	#undef PGM_BTH_NAME_RC_STR
1002	#undef PGM_BTH_NAME_R0_STR
1003	#undef PGM_GST_TYPE
1004	#undef PGM_GST_NAME
1005	#undef PGM_GST_NAME_RC_STR
1006	#undef PGM_GST_NAME_R0_STR
1007
1008	#ifdef VBOX_WITH_64_BITS_GUESTS
1009	/* Guest - AMD64 mode */
1010	# define PGM_GST_TYPE PGM_TYPE_AMD64
1011	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1012	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1013	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1014	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1015	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1016	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1017	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1018	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1019	# include "PGMGstDefs.h"
1020	# include "PGMBth.h"
1021	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1022	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1023	# undef PGM_BTH_NAME
1024	# undef PGM_BTH_NAME_RC_STR
1025	# undef PGM_BTH_NAME_R0_STR
1026	# undef PGM_GST_TYPE
1027	# undef PGM_GST_NAME
1028	# undef PGM_GST_NAME_RC_STR
1029	# undef PGM_GST_NAME_R0_STR
1030	#endif /* VBOX_WITH_64_BITS_GUESTS */
1031
1032	#undef PGM_SHW_TYPE
1033	#undef PGM_SHW_NAME
1034	#undef PGM_SHW_NAME_RC_STR
1035	#undef PGM_SHW_NAME_R0_STR
1036
1037
1038	/*
1039	* Shadow - EPT
1040	*/
1041	#define PGM_SHW_TYPE PGM_TYPE_EPT
1042	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1043	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1044	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1045	#include "PGMShw.h"
1046
1047	/* Guest - real mode */
1048	#define PGM_GST_TYPE PGM_TYPE_REAL
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1056	#include "PGMGstDefs.h"
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1059	#undef PGM_BTH_NAME
1060	#undef PGM_BTH_NAME_RC_STR
1061	#undef PGM_BTH_NAME_R0_STR
1062	#undef PGM_GST_TYPE
1063	#undef PGM_GST_NAME
1064	#undef PGM_GST_NAME_RC_STR
1065	#undef PGM_GST_NAME_R0_STR
1066
1067	/* Guest - protected mode */
1068	#define PGM_GST_TYPE PGM_TYPE_PROT
1069	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1070	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1071	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1072	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1073	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1074	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1075	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1076	#include "PGMGstDefs.h"
1077	#include "PGMBth.h"
1078	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1079	#undef PGM_BTH_NAME
1080	#undef PGM_BTH_NAME_RC_STR
1081	#undef PGM_BTH_NAME_R0_STR
1082	#undef PGM_GST_TYPE
1083	#undef PGM_GST_NAME
1084	#undef PGM_GST_NAME_RC_STR
1085	#undef PGM_GST_NAME_R0_STR
1086
1087	/* Guest - 32-bit mode */
1088	#define PGM_GST_TYPE PGM_TYPE_32BIT
1089	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1090	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1091	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1092	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1093	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1094	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1095	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1096	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1097	#include "PGMGstDefs.h"
1098	#include "PGMBth.h"
1099	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1100	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1101	#undef PGM_BTH_NAME
1102	#undef PGM_BTH_NAME_RC_STR
1103	#undef PGM_BTH_NAME_R0_STR
1104	#undef PGM_GST_TYPE
1105	#undef PGM_GST_NAME
1106	#undef PGM_GST_NAME_RC_STR
1107	#undef PGM_GST_NAME_R0_STR
1108
1109	/* Guest - PAE mode */
1110	#define PGM_GST_TYPE PGM_TYPE_PAE
1111	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1112	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1113	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1114	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1115	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1116	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1119	#include "PGMGstDefs.h"
1120	#include "PGMBth.h"
1121	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1122	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1123	#undef PGM_BTH_NAME
1124	#undef PGM_BTH_NAME_RC_STR
1125	#undef PGM_BTH_NAME_R0_STR
1126	#undef PGM_GST_TYPE
1127	#undef PGM_GST_NAME
1128	#undef PGM_GST_NAME_RC_STR
1129	#undef PGM_GST_NAME_R0_STR
1130
1131	#ifdef VBOX_WITH_64_BITS_GUESTS
1132	/* Guest - AMD64 mode */
1133	# define PGM_GST_TYPE PGM_TYPE_AMD64
1134	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1135	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1136	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1137	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1138	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1139	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1140	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1141	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1142	# include "PGMGstDefs.h"
1143	# include "PGMBth.h"
1144	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1145	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1146	# undef PGM_BTH_NAME
1147	# undef PGM_BTH_NAME_RC_STR
1148	# undef PGM_BTH_NAME_R0_STR
1149	# undef PGM_GST_TYPE
1150	# undef PGM_GST_NAME
1151	# undef PGM_GST_NAME_RC_STR
1152	# undef PGM_GST_NAME_R0_STR
1153	#endif /* VBOX_WITH_64_BITS_GUESTS */
1154
1155	#undef PGM_SHW_TYPE
1156	#undef PGM_SHW_NAME
1157	#undef PGM_SHW_NAME_RC_STR
1158	#undef PGM_SHW_NAME_R0_STR
1159
1160
1161
1162	/**
1163	* Initiates the paging of VM.
1164	*
1165	* @returns VBox status code.
1166	* @param pVM Pointer to VM structure.
1167	*/
1168	VMMR3DECL(int) PGMR3Init(PVM pVM)
1169	{
1170	LogFlow(("PGMR3Init:\n"));
1171	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1172	int rc;
1173
1174	/*
1175	* Assert alignment and sizes.
1176	*/
1177	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1178	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1179	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1180
1181	/*
1182	* Init the structure.
1183	*/
1184	#ifdef PGM_WITHOUT_MAPPINGS
1185	pVM->pgm.s.fMappingsDisabled = true;
1186	#endif
1187	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1188	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1189
1190	/* Init the per-CPU part. */
1191	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1192	{
1193	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1194	PPGMCPU pPGM = &pVCpu->pgm.s;
1195
1196	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1197	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1198	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1199
1200	pPGM->enmShadowMode = PGMMODE_INVALID;
1201	pPGM->enmGuestMode = PGMMODE_INVALID;
1202
1203	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1204
1205	pPGM->pGst32BitPdR3 = NULL;
1206	pPGM->pGstPaePdptR3 = NULL;
1207	pPGM->pGstAmd64Pml4R3 = NULL;
1208	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1209	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1210	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1211	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1212	#endif
1213	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1214	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1215	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1216	{
1217	pPGM->apGstPaePDsR3[i] = NULL;
1218	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1220	#endif
1221	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1222	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1223	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1224	}
1225
1226	pPGM->fA20Enabled = true;
1227	}
1228
1229	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1230	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1231	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1232
1233	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1234	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1235	true
1236	#else
1237	false
1238	#endif
1239	);
1240	AssertLogRelRCReturn(rc, rc);
1241
1242	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
1243	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1244	#else
1245	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1246	#endif
1247	AssertLogRelRCReturn(rc, rc);
1248	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1249	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1250
1251	/*
1252	* Get the configured RAM size - to estimate saved state size.
1253	*/
1254	uint64_t cbRam;
1255	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1256	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1257	cbRam = 0;
1258	else if (RT_SUCCESS(rc))
1259	{
1260	if (cbRam < PAGE_SIZE)
1261	cbRam = 0;
1262	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1263	}
1264	else
1265	{
1266	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1267	return rc;
1268	}
1269
1270	#ifdef VBOX_WITH_STATISTICS
1271	/*
1272	* Allocate memory for the statistics before someone tries to use them.
1273	*/
1274	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1275	void *pv;
1276	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1277	AssertRCReturn(rc, rc);
1278
1279	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1280	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1281	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1282	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1283
1284	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1285	{
1286	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1287	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1288	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1289
1290	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1291	}
1292	#endif /* VBOX_WITH_STATISTICS */
1293
1294	/*
1295	* Register callbacks, string formatters and the saved state data unit.
1296	*/
1297	#ifdef VBOX_STRICT
1298	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1299	#endif
1300	PGMRegisterStringFormatTypes();
1301
1302	rc = pgmR3InitSavedState(pVM, cbRam);
1303	if (RT_FAILURE(rc))
1304	return rc;
1305
1306	/*
1307	* Initialize the PGM critical section and flush the phys TLBs
1308	*/
1309	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1310	AssertRCReturn(rc, rc);
1311
1312	PGMR3PhysChunkInvalidateTLB(pVM);
1313	PGMPhysInvalidatePageMapTLB(pVM);
1314
1315	/*
1316	* For the time being we sport a full set of handy pages in addition to the base
1317	* memory to simplify things.
1318	*/
1319	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1320	AssertRCReturn(rc, rc);
1321
1322	/*
1323	* Trees
1324	*/
1325	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1326	if (RT_SUCCESS(rc))
1327	{
1328	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1329	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1330
1331	/*
1332	* Allocate the zero page.
1333	*/
1334	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1335	}
1336	if (RT_SUCCESS(rc))
1337	{
1338	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1339	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1340	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1341	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1342
1343	/*
1344	* Allocate the invalid MMIO page.
1345	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1346	*/
1347	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1348	}
1349	if (RT_SUCCESS(rc))
1350	{
1351	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1352	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1353	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1354	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1355
1356	/*
1357	* Init the paging.
1358	*/
1359	rc = pgmR3InitPaging(pVM);
1360	}
1361	if (RT_SUCCESS(rc))
1362	{
1363	/*
1364	* Init the page pool.
1365	*/
1366	rc = pgmR3PoolInit(pVM);
1367	}
1368	if (RT_SUCCESS(rc))
1369	{
1370	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1371	{
1372	PVMCPU pVCpu = &pVM->aCpus[i];
1373	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1374	if (RT_FAILURE(rc))
1375	break;
1376	}
1377	}
1378
1379	if (RT_SUCCESS(rc))
1380	{
1381	/*
1382	* Info & statistics
1383	*/
1384	DBGFR3InfoRegisterInternal(pVM, "mode",
1385	"Shows the current paging mode. "
1386	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1387	pgmR3InfoMode);
1388	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1389	"Dumps all the entries in the top level paging table. No arguments.",
1390	pgmR3InfoCr3);
1391	DBGFR3InfoRegisterInternal(pVM, "phys",
1392	"Dumps all the physical address ranges. No arguments.",
1393	pgmR3PhysInfo);
1394	DBGFR3InfoRegisterInternal(pVM, "handlers",
1395	"Dumps physical, virtual and hyper virtual handlers. "
1396	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1397	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1398	pgmR3InfoHandlers);
1399	DBGFR3InfoRegisterInternal(pVM, "mappings",
1400	"Dumps guest mappings.",
1401	pgmR3MapInfo);
1402
1403	pgmR3InitStats(pVM);
1404
1405	#ifdef VBOX_WITH_DEBUGGER
1406	/*
1407	* Debugger commands.
1408	*/
1409	static bool s_fRegisteredCmds = false;
1410	if (!s_fRegisteredCmds)
1411	{
1412	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1413	if (RT_SUCCESS(rc2))
1414	s_fRegisteredCmds = true;
1415	}
1416	#endif
1417	return VINF_SUCCESS;
1418	}
1419
1420	/* Almost no cleanup necessary, MM frees all memory. */
1421	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1422
1423	return rc;
1424	}
1425
1426
1427	/**
1428	* Initializes the per-VCPU PGM.
1429	*
1430	* @returns VBox status code.
1431	* @param pVM The VM to operate on.
1432	*/
1433	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1434	{
1435	LogFlow(("PGMR3InitCPU\n"));
1436	return VINF_SUCCESS;
1437	}
1438
1439
1440	/**
1441	* Init paging.
1442	*
1443	* Since we need to check what mode the host is operating in before we can choose
1444	* the right paging functions for the host we have to delay this until R0 has
1445	* been initialized.
1446	*
1447	* @returns VBox status code.
1448	* @param pVM VM handle.
1449	*/
1450	static int pgmR3InitPaging(PVM pVM)
1451	{
1452	/*
1453	* Force a recalculation of modes and switcher so everyone gets notified.
1454	*/
1455	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1456	{
1457	PVMCPU pVCpu = &pVM->aCpus[i];
1458
1459	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1460	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1461	}
1462
1463	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1464
1465	/*
1466	* Allocate static mapping space for whatever the cr3 register
1467	* points to and in the case of PAE mode to the 4 PDs.
1468	*/
1469	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1470	if (RT_FAILURE(rc))
1471	{
1472	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1473	return rc;
1474	}
1475	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1476
1477	/*
1478	* Allocate pages for the three possible intermediate contexts
1479	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1480	* for the sake of simplicity. The AMD64 uses the PAE for the
1481	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1482	*
1483	* We assume that two page tables will be enought for the core code
1484	* mappings (HC virtual and identity).
1485	*/
1486	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1487	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1488	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1489	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1490	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1491	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1492	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1493	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1494	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1495	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1496	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1497	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1498
1499	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1500	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1501	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1502	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1503	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1504	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1505
1506	/*
1507	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1508	*/
1509	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1510	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1511	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1512
1513	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1514	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1515
1516	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1517	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1518	{
1519	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1520	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1521	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1522	}
1523
1524	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1525	{
1526	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1527	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1528	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1529	}
1530
1531	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1532	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1533	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1534	\| HCPhysInterPaePDPT64;
1535
1536	/*
1537	* Initialize paging workers and mode from current host mode
1538	* and the guest running in real mode.
1539	*/
1540	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1541	switch (pVM->pgm.s.enmHostMode)
1542	{
1543	case SUPPAGINGMODE_32_BIT:
1544	case SUPPAGINGMODE_32_BIT_GLOBAL:
1545	case SUPPAGINGMODE_PAE:
1546	case SUPPAGINGMODE_PAE_GLOBAL:
1547	case SUPPAGINGMODE_PAE_NX:
1548	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1549	break;
1550
1551	case SUPPAGINGMODE_AMD64:
1552	case SUPPAGINGMODE_AMD64_GLOBAL:
1553	case SUPPAGINGMODE_AMD64_NX:
1554	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1555	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1556	if (ARCH_BITS != 64)
1557	{
1558	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1559	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1560	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1561	}
1562	#endif
1563	break;
1564	default:
1565	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1566	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1567	}
1568	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1569	if (RT_SUCCESS(rc))
1570	{
1571	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1572	#if HC_ARCH_BITS == 64
1573	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1574	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1575	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1576	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1577	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1578	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1579	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1580	#endif
1581	return VINF_SUCCESS;
1582	}
1583
1584	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1585	return rc;
1586	}
1587
1588
1589	/**
1590	* Init statistics
1591	* @returns VBox status code.
1592	*/
1593	static int pgmR3InitStats(PVM pVM)
1594	{
1595	PPGM pPGM = &pVM->pgm.s;
1596	int rc;
1597
1598	/*
1599	* Release statistics.
1600	*/
1601	/* Common - misc variables */
1602	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1603	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1604	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1605	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1606	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1607	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1608	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1609	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1610	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1611	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1612	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1613	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1614	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1615	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1616	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1617	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1618	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1619
1620	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1621	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1622	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1623	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1624
1625	/* Live save */
1626	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1627	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1628	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1629	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1630	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1631	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1632	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1633	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1634	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1635	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1636	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1637	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1638	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1639	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1640	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1641	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1642	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1643	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1644
1645	#ifdef VBOX_WITH_STATISTICS
1646
1647	# define PGM_REG_COUNTER(a, b, c) \
1648	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1649	AssertRC(rc);
1650
1651	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1652	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1653	AssertRC(rc);
1654
1655	# define PGM_REG_PROFILE(a, b, c) \
1656	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1657	AssertRC(rc);
1658
1659	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1660
1661	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1662	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1663	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1664	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1665
1666	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1667	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1668	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1669	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1670	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1671	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1672	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1673	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1674	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1675	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1676
1677	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1678	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1679	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1680	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1681	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1682	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1683
1684	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1685	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1686	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1687	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1688	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1689	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1690	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1691	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1692
1693	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1694	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1695	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1696	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1697
1698	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1699	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1700	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1701	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1702	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1703	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1704	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1705	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1706
1707	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1708	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1709	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1710	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1711	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1712	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1713
1714	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1715	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1716	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1717	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1718	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1719	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1720	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1721	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1722
1723	/* GC only: */
1724	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1725	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1726
1727	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1728	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1729	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1730	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1731	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1732	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1733	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1734	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1735
1736	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1737	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1738	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1739	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1740	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1741	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1742	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1743
1744	# undef PGM_REG_COUNTER
1745	# undef PGM_REG_PROFILE
1746	#endif
1747
1748	/*
1749	* Note! The layout below matches the member layout exactly!
1750	*/
1751
1752	/*
1753	* Common - stats
1754	*/
1755	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1756	{
1757	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1758
1759	#define PGM_REG_COUNTER(a, b, c) \
1760	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1761	AssertRC(rc);
1762	#define PGM_REG_PROFILE(a, b, c) \
1763	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1764	AssertRC(rc);
1765
1766	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1767
1768	#ifdef VBOX_WITH_STATISTICS
1769	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1770
1771	# if 0 /* rarely useful; leave for debugging. */
1772	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1773	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1774	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1775	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1776	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1777	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1778	# endif
1779	/* R0 only: */
1780	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1781	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1782
1783	/* RZ only: */
1784	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1785	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1786	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1787	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1788	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1789	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1790	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1791	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1792	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1793	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1794	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is releated to the guest mappings.");
1795	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1796	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1797	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1798	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1799	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1800	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1801	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1802	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1803	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1804	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1805	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1806	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1807	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1808	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1809	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1810	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1811	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1812	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1813	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1814	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1815	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1816	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1817	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1818	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1819	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1820	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1821	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1822	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1823	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1824	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1825	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1826	#if 0 /* rarely useful; leave for debugging. */
1827	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1828	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1829	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1830	#endif
1831	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1832	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1833	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1834	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1835	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1836
1837	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1838	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1839	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1840	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1841	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1842	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1843	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1844	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1845	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1846	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1847	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1848	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restorting to subset flushes.");
1849	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1850	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1851	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1852	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1853	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1854	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1855	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1856	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1857	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1858	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1859	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1860	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1861	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1862	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1863	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1864	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1865	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1866	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1867	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1868	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1869	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1870	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1871	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1872	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1873
1874	/* HC only: */
1875
1876	/* RZ & R3: */
1877	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1878	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1879	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1880	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1881	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1882	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1883	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1884	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1885	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1886	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1887	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1888	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1889	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1891	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1894	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1900	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1903	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1917	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1918	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1919	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1923	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1924
1925	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1926	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1927	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1928	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1929	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1930	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1931	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1932	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1933	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1934	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1935	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1936	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1937	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1938	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1939	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1940	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1941	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1942	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1943	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1944	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1945	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1946	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1947	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1948	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1949	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1950	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1951	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1952	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1953	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1954	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1955	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1956	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1957	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1958	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1959	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1960	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1961	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1962	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1963	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1964	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1965	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1966	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1967	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1968	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1969	#endif /* VBOX_WITH_STATISTICS */
1970
1971	#undef PGM_REG_PROFILE
1972	#undef PGM_REG_COUNTER
1973
1974	}
1975
1976	return VINF_SUCCESS;
1977	}
1978
1979
1980	/**
1981	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1982	*
1983	* The dynamic mapping area will also be allocated and initialized at this
1984	* time. We could allocate it during PGMR3Init of course, but the mapping
1985	* wouldn't be allocated at that time preventing us from setting up the
1986	* page table entries with the dummy page.
1987	*
1988	* @returns VBox status code.
1989	* @param pVM VM handle.
1990	*/
1991	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1992	{
1993	RTGCPTR GCPtr;
1994	int rc;
1995
1996	/*
1997	* Reserve space for the dynamic mappings.
1998	*/
1999	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2000	if (RT_SUCCESS(rc))
2001	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2002
2003	if ( RT_SUCCESS(rc)
2004	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2005	{
2006	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2007	if (RT_SUCCESS(rc))
2008	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2009	}
2010	if (RT_SUCCESS(rc))
2011	{
2012	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2013	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2014	}
2015	return rc;
2016	}
2017
2018
2019	/**
2020	* Ring-3 init finalizing.
2021	*
2022	* @returns VBox status code.
2023	* @param pVM The VM handle.
2024	*/
2025	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2026	{
2027	int rc;
2028
2029	/*
2030	* Reserve space for the dynamic mappings.
2031	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2032	*/
2033	/* get the pointer to the page table entries. */
2034	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2035	AssertRelease(pMapping);
2036	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2037	const unsigned iPT = off >> X86_PD_SHIFT;
2038	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2039	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2040	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2041
2042	/* init cache area */
2043	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2044	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2045	{
2046	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2047	AssertRCReturn(rc, rc);
2048	}
2049
2050	/*
2051	* Determin the max physical address width (MAXPHYADDR) and apply it to
2052	* all the mask members and stuff.
2053	*/
2054	uint32_t cMaxPhysAddrWidth;
2055	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2056	if ( uMaxExtLeaf >= 0x80000008
2057	&& uMaxExtLeaf <= 0x80000fff)
2058	{
2059	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2060	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2061	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2062	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2063	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2064	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2065	}
2066	else
2067	{
2068	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2069	cMaxPhysAddrWidth = 48;
2070	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2071	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2072	}
2073
2074	pVM->pgm.s.GCPhysInvAddrMask = 0;
2075	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2076	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2077
2078	/*
2079	* Initialize the invalid paging entry masks, assuming NX is disabled.
2080	*/
2081	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2082	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2083	{
2084	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2085
2086	/** @todo The manuals are not entirely clear whether the physical
2087	* address width is relevant. See table 5-9 in the intel
2088	* manual vs the PDE4M descriptions. Write testcase (NP). */
2089	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2090	\| X86_PDE4M_MBZ_MASK;
2091
2092	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2093	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2094	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2095	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2096
2097	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2098	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2099	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2100	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2101	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2102	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2103	}
2104
2105	/*
2106	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2107	* Intel only goes up to 36 bits, so we stick to 36 as well.
2108	* Update: More recent intel manuals specifies 40 bits just like AMD.
2109	*/
2110	uint32_t u32Dummy, u32Features;
2111	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2112	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2113	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2114	else
2115	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2116
2117	/*
2118	* Allocate memory if we're supposed to do that.
2119	*/
2120	if (pVM->pgm.s.fRamPreAlloc)
2121	rc = pgmR3PhysRamPreAllocate(pVM);
2122
2123	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2124	return rc;
2125	}
2126
2127
2128	/**
2129	* Applies relocations to data and code managed by this component.
2130	*
2131	* This function will be called at init and whenever the VMM need to relocate it
2132	* self inside the GC.
2133	*
2134	* @param pVM The VM.
2135	* @param offDelta Relocation delta relative to old location.
2136	*/
2137	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2138	{
2139	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2140
2141	/*
2142	* Paging stuff.
2143	*/
2144	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2145
2146	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2147
2148	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2149	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2150	{
2151	PVMCPU pVCpu = &pVM->aCpus[i];
2152
2153	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2154
2155	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2156	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2157	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2158	}
2159
2160	/*
2161	* Trees.
2162	*/
2163	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2164
2165	/*
2166	* Ram ranges.
2167	*/
2168	if (pVM->pgm.s.pRamRangesR3)
2169	{
2170	/* Update the pSelfRC pointers and relink them. */
2171	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2172	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2173	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2174	pgmR3PhysRelinkRamRanges(pVM);
2175	}
2176
2177	/*
2178	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2179	* be mapped and thus not included in the above exercise.
2180	*/
2181	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2182	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2183	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2184
2185	/*
2186	* Update the two page directories with all page table mappings.
2187	* (One or more of them have changed, that's why we're here.)
2188	*/
2189	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2190	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2191	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2192
2193	/* Relocate GC addresses of Page Tables. */
2194	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2195	{
2196	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2197	{
2198	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2199	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2200	}
2201	}
2202
2203	/*
2204	* Dynamic page mapping area.
2205	*/
2206	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2207	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2208	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2209
2210	if (pVM->pgm.s.pRCDynMap)
2211	{
2212	pVM->pgm.s.pRCDynMap += offDelta;
2213	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2214
2215	pDynMap->paPages += offDelta;
2216	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2217
2218	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2219	{
2220	paPages[iPage].pvPage += offDelta;
2221	paPages[iPage].uPte.pv += offDelta;
2222	}
2223	}
2224
2225	/*
2226	* The Zero page.
2227	*/
2228	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2229	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2230	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2231	#else
2232	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2233	#endif
2234
2235	/*
2236	* Physical and virtual handlers.
2237	*/
2238	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2239	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2240	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2241	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2242
2243	/*
2244	* The page pool.
2245	*/
2246	pgmR3PoolRelocate(pVM);
2247
2248	#ifdef VBOX_WITH_STATISTICS
2249	/*
2250	* Statistics.
2251	*/
2252	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2253	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2254	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2255	#endif
2256	}
2257
2258
2259	/**
2260	* Callback function for relocating a physical access handler.
2261	*
2262	* @returns 0 (continue enum)
2263	* @param pNode Pointer to a PGMPHYSHANDLER node.
2264	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2265	* not certain the delta will fit in a void pointer for all possible configs.
2266	*/
2267	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2268	{
2269	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2270	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2271	if (pHandler->pfnHandlerRC)
2272	pHandler->pfnHandlerRC += offDelta;
2273	if (pHandler->pvUserRC >= 0x10000)
2274	pHandler->pvUserRC += offDelta;
2275	return 0;
2276	}
2277
2278
2279	/**
2280	* Callback function for relocating a virtual access handler.
2281	*
2282	* @returns 0 (continue enum)
2283	* @param pNode Pointer to a PGMVIRTHANDLER node.
2284	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2285	* not certain the delta will fit in a void pointer for all possible configs.
2286	*/
2287	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2288	{
2289	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2290	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2291	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2292	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2293	Assert(pHandler->pfnHandlerRC);
2294	pHandler->pfnHandlerRC += offDelta;
2295	return 0;
2296	}
2297
2298
2299	/**
2300	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2301	*
2302	* @returns 0 (continue enum)
2303	* @param pNode Pointer to a PGMVIRTHANDLER node.
2304	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2305	* not certain the delta will fit in a void pointer for all possible configs.
2306	*/
2307	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2308	{
2309	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2310	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2311	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2312	Assert(pHandler->pfnHandlerRC);
2313	pHandler->pfnHandlerRC += offDelta;
2314	return 0;
2315	}
2316
2317
2318	/**
2319	* Resets a virtual CPU when unplugged.
2320	*
2321	* @param pVM The VM handle.
2322	* @param pVCpu The virtual CPU handle.
2323	*/
2324	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2325	{
2326	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2327	AssertRC(rc);
2328
2329	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2330	AssertRC(rc);
2331
2332	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2333
2334	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2335
2336	/*
2337	* Re-init other members.
2338	*/
2339	pVCpu->pgm.s.fA20Enabled = true;
2340
2341	/*
2342	* Clear the FFs PGM owns.
2343	*/
2344	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2345	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2346	}
2347
2348
2349	/**
2350	* The VM is being reset.
2351	*
2352	* For the PGM component this means that any PD write monitors
2353	* needs to be removed.
2354	*
2355	* @param pVM VM handle.
2356	*/
2357	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2358	{
2359	int rc;
2360
2361	LogFlow(("PGMR3Reset:\n"));
2362	VM_ASSERT_EMT(pVM);
2363
2364	pgmLock(pVM);
2365
2366	/*
2367	* Unfix any fixed mappings and disable CR3 monitoring.
2368	*/
2369	pVM->pgm.s.fMappingsFixed = false;
2370	pVM->pgm.s.fMappingsFixedRestored = false;
2371	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2372	pVM->pgm.s.cbMappingFixed = 0;
2373
2374	/*
2375	* Exit the guest paging mode before the pgm pool gets reset.
2376	* Important to clean up the amd64 case.
2377	*/
2378	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2379	{
2380	PVMCPU pVCpu = &pVM->aCpus[i];
2381	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2382	AssertRC(rc);
2383	}
2384
2385	#ifdef DEBUG
2386	DBGFR3InfoLog(pVM, "mappings", NULL);
2387	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2388	#endif
2389
2390	/*
2391	* Switch mode back to real mode. (before resetting the pgm pool!)
2392	*/
2393	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2394	{
2395	PVMCPU pVCpu = &pVM->aCpus[i];
2396
2397	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2398	AssertRC(rc);
2399
2400	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2401	}
2402
2403	/*
2404	* Reset the shadow page pool.
2405	*/
2406	pgmR3PoolReset(pVM);
2407
2408	/*
2409	* Re-init various other members and clear the FFs that PGM owns.
2410	*/
2411	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2412	{
2413	PVMCPU pVCpu = &pVM->aCpus[i];
2414
2415	pVCpu->pgm.s.fA20Enabled = true;
2416	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2417	PGMNotifyNxeChanged(pVCpu, false);
2418
2419	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2420	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2421	}
2422
2423	/*
2424	* Reset (zero) RAM and shadow ROM pages.
2425	*/
2426	rc = pgmR3PhysRamReset(pVM);
2427	if (RT_SUCCESS(rc))
2428	rc = pgmR3PhysRomReset(pVM);
2429
2430
2431	pgmUnlock(pVM);
2432	AssertReleaseRC(rc);
2433	}
2434
2435
2436	#ifdef VBOX_STRICT
2437	/**
2438	* VM state change callback for clearing fNoMorePhysWrites after
2439	* a snapshot has been created.
2440	*/
2441	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2442	{
2443	if ( enmState == VMSTATE_RUNNING
2444	\|\| enmState == VMSTATE_RESUMING)
2445	pVM->pgm.s.fNoMorePhysWrites = false;
2446	}
2447	#endif
2448
2449
2450	/**
2451	* Terminates the PGM.
2452	*
2453	* @returns VBox status code.
2454	* @param pVM Pointer to VM structure.
2455	*/
2456	VMMR3DECL(int) PGMR3Term(PVM pVM)
2457	{
2458	/* Must free shared pages here. */
2459	pgmLock(pVM);
2460	pgmR3PhysRamTerm(pVM);
2461	pgmR3PhysRomTerm(pVM);
2462	pgmUnlock(pVM);
2463
2464	PGMDeregisterStringFormatTypes();
2465	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2466	}
2467
2468
2469	/**
2470	* Terminates the per-VCPU PGM.
2471	*
2472	* Termination means cleaning up and freeing all resources,
2473	* the VM it self is at this point powered off or suspended.
2474	*
2475	* @returns VBox status code.
2476	* @param pVM The VM to operate on.
2477	*/
2478	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2479	{
2480	return 0;
2481	}
2482
2483
2484	/**
2485	* Show paging mode.
2486	*
2487	* @param pVM VM Handle.
2488	* @param pHlp The info helpers.
2489	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2490	*/
2491	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2492	{
2493	/* digest argument. */
2494	bool fGuest, fShadow, fHost;
2495	if (pszArgs)
2496	pszArgs = RTStrStripL(pszArgs);
2497	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2498	fShadow = fHost = fGuest = true;
2499	else
2500	{
2501	fShadow = fHost = fGuest = false;
2502	if (strstr(pszArgs, "guest"))
2503	fGuest = true;
2504	if (strstr(pszArgs, "shadow"))
2505	fShadow = true;
2506	if (strstr(pszArgs, "host"))
2507	fHost = true;
2508	}
2509
2510	/** @todo SMP support! */
2511	/* print info. */
2512	if (fGuest)
2513	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2514	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2515	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2516	if (fShadow)
2517	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2518	if (fHost)
2519	{
2520	const char *psz;
2521	switch (pVM->pgm.s.enmHostMode)
2522	{
2523	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2524	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2525	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2526	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2527	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2528	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2529	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2530	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2531	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2532	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2533	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2534	default: psz = "unknown"; break;
2535	}
2536	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2537	}
2538	}
2539
2540
2541	/**
2542	* Dump registered MMIO ranges to the log.
2543	*
2544	* @param pVM VM Handle.
2545	* @param pHlp The info helpers.
2546	* @param pszArgs Arguments, ignored.
2547	*/
2548	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2549	{
2550	NOREF(pszArgs);
2551	pHlp->pfnPrintf(pHlp,
2552	"RAM ranges (pVM=%p)\n"
2553	"%.s %.s\n",
2554	pVM,
2555	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2556	sizeof(RTHCPTR) * 2, "pvHC ");
2557
2558	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2559	pHlp->pfnPrintf(pHlp,
2560	"%RGp-%RGp %RHv %s\n",
2561	pCur->GCPhys,
2562	pCur->GCPhysLast,
2563	pCur->pvR3,
2564	pCur->pszDesc);
2565	}
2566
2567	/**
2568	* Dump the page directory to the log.
2569	*
2570	* @param pVM VM Handle.
2571	* @param pHlp The info helpers.
2572	* @param pszArgs Arguments, ignored.
2573	*/
2574	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2575	{
2576	/** @todo SMP support!! */
2577	PVMCPU pVCpu = &pVM->aCpus[0];
2578
2579	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2580	/* Big pages supported? */
2581	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2582
2583	/* Global pages supported? */
2584	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2585
2586	NOREF(pszArgs);
2587
2588	/*
2589	* Get page directory addresses.
2590	*/
2591	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2592	Assert(pPDSrc);
2593	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2594
2595	/*
2596	* Iterate the page directory.
2597	*/
2598	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2599	{
2600	X86PDE PdeSrc = pPDSrc->a[iPD];
2601	if (PdeSrc.n.u1Present)
2602	{
2603	if (PdeSrc.b.u1Size && fPSE)
2604	pHlp->pfnPrintf(pHlp,
2605	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2606	iPD,
2607	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2608	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2609	else
2610	pHlp->pfnPrintf(pHlp,
2611	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2612	iPD,
2613	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2614	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2615	}
2616	}
2617	}
2618
2619
2620	/**
2621	* Service a VMMCALLRING3_PGM_LOCK call.
2622	*
2623	* @returns VBox status code.
2624	* @param pVM The VM handle.
2625	*/
2626	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2627	{
2628	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2629	AssertRC(rc);
2630	return rc;
2631	}
2632
2633
2634	/**
2635	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2636	*
2637	* @returns PGM_TYPE_*.
2638	* @param pgmMode The mode value to convert.
2639	*/
2640	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2641	{
2642	switch (pgmMode)
2643	{
2644	case PGMMODE_REAL: return PGM_TYPE_REAL;
2645	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2646	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2647	case PGMMODE_PAE:
2648	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2649	case PGMMODE_AMD64:
2650	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2651	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2652	case PGMMODE_EPT: return PGM_TYPE_EPT;
2653	default:
2654	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2655	}
2656	}
2657
2658
2659	/**
2660	* Gets the index into the paging mode data array of a SHW+GST mode.
2661	*
2662	* @returns PGM::paPagingData index.
2663	* @param uShwType The shadow paging mode type.
2664	* @param uGstType The guest paging mode type.
2665	*/
2666	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2667	{
2668	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2669	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2670	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2671	+ (uGstType - PGM_TYPE_REAL);
2672	}
2673
2674
2675	/**
2676	* Gets the index into the paging mode data array of a SHW+GST mode.
2677	*
2678	* @returns PGM::paPagingData index.
2679	* @param enmShw The shadow paging mode.
2680	* @param enmGst The guest paging mode.
2681	*/
2682	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2683	{
2684	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2685	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2686	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2687	}
2688
2689
2690	/**
2691	* Calculates the max data index.
2692	* @returns The number of entries in the paging data array.
2693	*/
2694	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2695	{
2696	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2697	}
2698
2699
2700	/**
2701	* Initializes the paging mode data kept in PGM::paModeData.
2702	*
2703	* @param pVM The VM handle.
2704	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2705	* This is used early in the init process to avoid trouble with PDM
2706	* not being initialized yet.
2707	*/
2708	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2709	{
2710	PPGMMODEDATA pModeData;
2711	int rc;
2712
2713	/*
2714	* Allocate the array on the first call.
2715	*/
2716	if (!pVM->pgm.s.paModeData)
2717	{
2718	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2719	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2720	}
2721
2722	/*
2723	* Initialize the array entries.
2724	*/
2725	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2726	pModeData->uShwType = PGM_TYPE_32BIT;
2727	pModeData->uGstType = PGM_TYPE_REAL;
2728	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2729	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2730	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2731
2732	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2733	pModeData->uShwType = PGM_TYPE_32BIT;
2734	pModeData->uGstType = PGM_TYPE_PROT;
2735	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2736	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2737	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2738
2739	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2740	pModeData->uShwType = PGM_TYPE_32BIT;
2741	pModeData->uGstType = PGM_TYPE_32BIT;
2742	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2743	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745
2746	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2747	pModeData->uShwType = PGM_TYPE_PAE;
2748	pModeData->uGstType = PGM_TYPE_REAL;
2749	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2752
2753	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2754	pModeData->uShwType = PGM_TYPE_PAE;
2755	pModeData->uGstType = PGM_TYPE_PROT;
2756	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2759
2760	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2761	pModeData->uShwType = PGM_TYPE_PAE;
2762	pModeData->uGstType = PGM_TYPE_32BIT;
2763	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766
2767	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2768	pModeData->uShwType = PGM_TYPE_PAE;
2769	pModeData->uGstType = PGM_TYPE_PAE;
2770	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2773
2774	#ifdef VBOX_WITH_64_BITS_GUESTS
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2776	pModeData->uShwType = PGM_TYPE_AMD64;
2777	pModeData->uGstType = PGM_TYPE_AMD64;
2778	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781	#endif
2782
2783	/* The nested paging mode. */
2784	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2785	pModeData->uShwType = PGM_TYPE_NESTED;
2786	pModeData->uGstType = PGM_TYPE_REAL;
2787	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789
2790	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2791	pModeData->uShwType = PGM_TYPE_NESTED;
2792	pModeData->uGstType = PGM_TYPE_PROT;
2793	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2794	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795
2796	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2797	pModeData->uShwType = PGM_TYPE_NESTED;
2798	pModeData->uGstType = PGM_TYPE_32BIT;
2799	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2800	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2801
2802	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2803	pModeData->uShwType = PGM_TYPE_NESTED;
2804	pModeData->uGstType = PGM_TYPE_PAE;
2805	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2807
2808	#ifdef VBOX_WITH_64_BITS_GUESTS
2809	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2810	pModeData->uShwType = PGM_TYPE_NESTED;
2811	pModeData->uGstType = PGM_TYPE_AMD64;
2812	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2814	#endif
2815
2816	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2817	switch (pVM->pgm.s.enmHostMode)
2818	{
2819	#if HC_ARCH_BITS == 32
2820	case SUPPAGINGMODE_32_BIT:
2821	case SUPPAGINGMODE_32_BIT_GLOBAL:
2822	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2823	{
2824	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2825	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826	}
2827	# ifdef VBOX_WITH_64_BITS_GUESTS
2828	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2829	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	# endif
2831	break;
2832
2833	case SUPPAGINGMODE_PAE:
2834	case SUPPAGINGMODE_PAE_NX:
2835	case SUPPAGINGMODE_PAE_GLOBAL:
2836	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2837	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2838	{
2839	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2840	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2841	}
2842	# ifdef VBOX_WITH_64_BITS_GUESTS
2843	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2844	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845	# endif
2846	break;
2847	#endif /* HC_ARCH_BITS == 32 */
2848
2849	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2850	case SUPPAGINGMODE_AMD64:
2851	case SUPPAGINGMODE_AMD64_GLOBAL:
2852	case SUPPAGINGMODE_AMD64_NX:
2853	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2854	# ifdef VBOX_WITH_64_BITS_GUESTS
2855	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2856	# else
2857	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2858	# endif
2859	{
2860	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2861	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	}
2863	break;
2864	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2865
2866	default:
2867	AssertFailed();
2868	break;
2869	}
2870
2871	/* Extended paging (EPT) / Intel VT-x */
2872	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2873	pModeData->uShwType = PGM_TYPE_EPT;
2874	pModeData->uGstType = PGM_TYPE_REAL;
2875	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878
2879	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2880	pModeData->uShwType = PGM_TYPE_EPT;
2881	pModeData->uGstType = PGM_TYPE_PROT;
2882	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2883	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2885
2886	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2887	pModeData->uShwType = PGM_TYPE_EPT;
2888	pModeData->uGstType = PGM_TYPE_32BIT;
2889	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2891	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2892
2893	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2894	pModeData->uShwType = PGM_TYPE_EPT;
2895	pModeData->uGstType = PGM_TYPE_PAE;
2896	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2898	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2899
2900	#ifdef VBOX_WITH_64_BITS_GUESTS
2901	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2902	pModeData->uShwType = PGM_TYPE_EPT;
2903	pModeData->uGstType = PGM_TYPE_AMD64;
2904	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2906	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	#endif
2908	return VINF_SUCCESS;
2909	}
2910
2911
2912	/**
2913	* Switch to different (or relocated in the relocate case) mode data.
2914	*
2915	* @param pVM The VM handle.
2916	* @param pVCpu The VMCPU to operate on.
2917	* @param enmShw The the shadow paging mode.
2918	* @param enmGst The the guest paging mode.
2919	*/
2920	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2921	{
2922	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2923
2924	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2925	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2926
2927	/* shadow */
2928	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2929	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2930	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2931	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2932	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2933
2934	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2935	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2936
2937	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2938	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2939
2940
2941	/* guest */
2942	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2943	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2944	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2945	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2946	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2947	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2948	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2949	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2950	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2951	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2952	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2953	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2954
2955	/* both */
2956	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2957	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2958	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2959	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2960	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2961	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2962	#ifdef VBOX_STRICT
2963	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2964	#endif
2965	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2966	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2967
2968	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2969	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2970	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2971	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2972	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2973	#ifdef VBOX_STRICT
2974	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2975	#endif
2976	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2977	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2978
2979	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2980	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2981	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2982	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2983	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2984	#ifdef VBOX_STRICT
2985	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2986	#endif
2987	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2988	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2989	}
2990
2991
2992	/**
2993	* Calculates the shadow paging mode.
2994	*
2995	* @returns The shadow paging mode.
2996	* @param pVM VM handle.
2997	* @param enmGuestMode The guest mode.
2998	* @param enmHostMode The host mode.
2999	* @param enmShadowMode The current shadow mode.
3000	* @param penmSwitcher Where to store the switcher to use.
3001	* VMMSWITCHER_INVALID means no change.
3002	*/
3003	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3004	{
3005	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3006	switch (enmGuestMode)
3007	{
3008	/*
3009	* When switching to real or protected mode we don't change
3010	* anything since it's likely that we'll switch back pretty soon.
3011	*
3012	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3013	* and is supposed to determine which shadow paging and switcher to
3014	* use during init.
3015	*/
3016	case PGMMODE_REAL:
3017	case PGMMODE_PROTECTED:
3018	if ( enmShadowMode != PGMMODE_INVALID
3019	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3020	break; /* (no change) */
3021
3022	switch (enmHostMode)
3023	{
3024	case SUPPAGINGMODE_32_BIT:
3025	case SUPPAGINGMODE_32_BIT_GLOBAL:
3026	enmShadowMode = PGMMODE_32_BIT;
3027	enmSwitcher = VMMSWITCHER_32_TO_32;
3028	break;
3029
3030	case SUPPAGINGMODE_PAE:
3031	case SUPPAGINGMODE_PAE_NX:
3032	case SUPPAGINGMODE_PAE_GLOBAL:
3033	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3034	enmShadowMode = PGMMODE_PAE;
3035	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3036	#ifdef DEBUG_bird
3037	if (RTEnvExist("VBOX_32BIT"))
3038	{
3039	enmShadowMode = PGMMODE_32_BIT;
3040	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3041	}
3042	#endif
3043	break;
3044
3045	case SUPPAGINGMODE_AMD64:
3046	case SUPPAGINGMODE_AMD64_GLOBAL:
3047	case SUPPAGINGMODE_AMD64_NX:
3048	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3049	enmShadowMode = PGMMODE_PAE;
3050	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3051	#ifdef DEBUG_bird
3052	if (RTEnvExist("VBOX_32BIT"))
3053	{
3054	enmShadowMode = PGMMODE_32_BIT;
3055	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3056	}
3057	#endif
3058	break;
3059
3060	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3061	}
3062	break;
3063
3064	case PGMMODE_32_BIT:
3065	switch (enmHostMode)
3066	{
3067	case SUPPAGINGMODE_32_BIT:
3068	case SUPPAGINGMODE_32_BIT_GLOBAL:
3069	enmShadowMode = PGMMODE_32_BIT;
3070	enmSwitcher = VMMSWITCHER_32_TO_32;
3071	break;
3072
3073	case SUPPAGINGMODE_PAE:
3074	case SUPPAGINGMODE_PAE_NX:
3075	case SUPPAGINGMODE_PAE_GLOBAL:
3076	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3077	enmShadowMode = PGMMODE_PAE;
3078	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3079	#ifdef DEBUG_bird
3080	if (RTEnvExist("VBOX_32BIT"))
3081	{
3082	enmShadowMode = PGMMODE_32_BIT;
3083	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3084	}
3085	#endif
3086	break;
3087
3088	case SUPPAGINGMODE_AMD64:
3089	case SUPPAGINGMODE_AMD64_GLOBAL:
3090	case SUPPAGINGMODE_AMD64_NX:
3091	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3092	enmShadowMode = PGMMODE_PAE;
3093	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3094	#ifdef DEBUG_bird
3095	if (RTEnvExist("VBOX_32BIT"))
3096	{
3097	enmShadowMode = PGMMODE_32_BIT;
3098	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3099	}
3100	#endif
3101	break;
3102
3103	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3104	}
3105	break;
3106
3107	case PGMMODE_PAE:
3108	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3109	switch (enmHostMode)
3110	{
3111	case SUPPAGINGMODE_32_BIT:
3112	case SUPPAGINGMODE_32_BIT_GLOBAL:
3113	enmShadowMode = PGMMODE_PAE;
3114	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3115	break;
3116
3117	case SUPPAGINGMODE_PAE:
3118	case SUPPAGINGMODE_PAE_NX:
3119	case SUPPAGINGMODE_PAE_GLOBAL:
3120	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3121	enmShadowMode = PGMMODE_PAE;
3122	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3123	break;
3124
3125	case SUPPAGINGMODE_AMD64:
3126	case SUPPAGINGMODE_AMD64_GLOBAL:
3127	case SUPPAGINGMODE_AMD64_NX:
3128	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3129	enmShadowMode = PGMMODE_PAE;
3130	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3131	break;
3132
3133	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3134	}
3135	break;
3136
3137	case PGMMODE_AMD64:
3138	case PGMMODE_AMD64_NX:
3139	switch (enmHostMode)
3140	{
3141	case SUPPAGINGMODE_32_BIT:
3142	case SUPPAGINGMODE_32_BIT_GLOBAL:
3143	enmShadowMode = PGMMODE_AMD64;
3144	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3145	break;
3146
3147	case SUPPAGINGMODE_PAE:
3148	case SUPPAGINGMODE_PAE_NX:
3149	case SUPPAGINGMODE_PAE_GLOBAL:
3150	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3151	enmShadowMode = PGMMODE_AMD64;
3152	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3153	break;
3154
3155	case SUPPAGINGMODE_AMD64:
3156	case SUPPAGINGMODE_AMD64_GLOBAL:
3157	case SUPPAGINGMODE_AMD64_NX:
3158	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3159	enmShadowMode = PGMMODE_AMD64;
3160	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3161	break;
3162
3163	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3164	}
3165	break;
3166
3167
3168	default:
3169	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3170	*penmSwitcher = VMMSWITCHER_INVALID;
3171	return PGMMODE_INVALID;
3172	}
3173	/* Override the shadow mode is nested paging is active. */
3174	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3175	if (pVM->pgm.s.fNestedPaging)
3176	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3177
3178	*penmSwitcher = enmSwitcher;
3179	return enmShadowMode;
3180	}
3181
3182
3183	/**
3184	* Performs the actual mode change.
3185	* This is called by PGMChangeMode and pgmR3InitPaging().
3186	*
3187	* @returns VBox status code. May suspend or power off the VM on error, but this
3188	* will trigger using FFs and not status codes.
3189	*
3190	* @param pVM VM handle.
3191	* @param pVCpu The VMCPU to operate on.
3192	* @param enmGuestMode The new guest mode. This is assumed to be different from
3193	* the current mode.
3194	*/
3195	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3196	{
3197	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3198	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3199
3200	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3201	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3202
3203	/*
3204	* Calc the shadow mode and switcher.
3205	*/
3206	VMMSWITCHER enmSwitcher;
3207	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3208
3209	#ifdef VBOX_WITH_RAW_MODE
3210	if (enmSwitcher != VMMSWITCHER_INVALID)
3211	{
3212	/*
3213	* Select new switcher.
3214	*/
3215	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3216	if (RT_FAILURE(rc))
3217	{
3218	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3219	return rc;
3220	}
3221	}
3222	#endif
3223
3224	/*
3225	* Exit old mode(s).
3226	*/
3227	#if HC_ARCH_BITS == 32
3228	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3229	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3230	&& enmShadowMode == PGMMODE_NESTED);
3231	#else
3232	const bool fForceShwEnterExit = false;
3233	#endif
3234	/* shadow */
3235	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3236	\|\| fForceShwEnterExit)
3237	{
3238	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3239	if (PGM_SHW_PFN(Exit, pVCpu))
3240	{
3241	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3242	if (RT_FAILURE(rc))
3243	{
3244	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3245	return rc;
3246	}
3247	}
3248
3249	}
3250	else
3251	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3252
3253	/* guest */
3254	if (PGM_GST_PFN(Exit, pVCpu))
3255	{
3256	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3257	if (RT_FAILURE(rc))
3258	{
3259	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3260	return rc;
3261	}
3262	}
3263
3264	/*
3265	* Load new paging mode data.
3266	*/
3267	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3268
3269	/*
3270	* Enter new shadow mode (if changed).
3271	*/
3272	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3273	\|\| fForceShwEnterExit)
3274	{
3275	int rc;
3276	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3277	switch (enmShadowMode)
3278	{
3279	case PGMMODE_32_BIT:
3280	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3281	break;
3282	case PGMMODE_PAE:
3283	case PGMMODE_PAE_NX:
3284	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3285	break;
3286	case PGMMODE_AMD64:
3287	case PGMMODE_AMD64_NX:
3288	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3289	break;
3290	case PGMMODE_NESTED:
3291	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3292	break;
3293	case PGMMODE_EPT:
3294	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3295	break;
3296	case PGMMODE_REAL:
3297	case PGMMODE_PROTECTED:
3298	default:
3299	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3300	return VERR_INTERNAL_ERROR;
3301	}
3302	if (RT_FAILURE(rc))
3303	{
3304	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3305	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3306	return rc;
3307	}
3308	}
3309
3310	/*
3311	* Always flag the necessary updates
3312	*/
3313	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3314
3315	/*
3316	* Enter the new guest and shadow+guest modes.
3317	*/
3318	int rc = -1;
3319	int rc2 = -1;
3320	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3321	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3322	switch (enmGuestMode)
3323	{
3324	case PGMMODE_REAL:
3325	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3326	switch (pVCpu->pgm.s.enmShadowMode)
3327	{
3328	case PGMMODE_32_BIT:
3329	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3330	break;
3331	case PGMMODE_PAE:
3332	case PGMMODE_PAE_NX:
3333	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3334	break;
3335	case PGMMODE_NESTED:
3336	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3337	break;
3338	case PGMMODE_EPT:
3339	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3340	break;
3341	case PGMMODE_AMD64:
3342	case PGMMODE_AMD64_NX:
3343	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3344	default: AssertFailed(); break;
3345	}
3346	break;
3347
3348	case PGMMODE_PROTECTED:
3349	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3350	switch (pVCpu->pgm.s.enmShadowMode)
3351	{
3352	case PGMMODE_32_BIT:
3353	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3354	break;
3355	case PGMMODE_PAE:
3356	case PGMMODE_PAE_NX:
3357	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3358	break;
3359	case PGMMODE_NESTED:
3360	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3361	break;
3362	case PGMMODE_EPT:
3363	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3364	break;
3365	case PGMMODE_AMD64:
3366	case PGMMODE_AMD64_NX:
3367	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3368	default: AssertFailed(); break;
3369	}
3370	break;
3371
3372	case PGMMODE_32_BIT:
3373	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3374	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3375	switch (pVCpu->pgm.s.enmShadowMode)
3376	{
3377	case PGMMODE_32_BIT:
3378	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3379	break;
3380	case PGMMODE_PAE:
3381	case PGMMODE_PAE_NX:
3382	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3383	break;
3384	case PGMMODE_NESTED:
3385	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3386	break;
3387	case PGMMODE_EPT:
3388	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3389	break;
3390	case PGMMODE_AMD64:
3391	case PGMMODE_AMD64_NX:
3392	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3393	default: AssertFailed(); break;
3394	}
3395	break;
3396
3397	case PGMMODE_PAE_NX:
3398	case PGMMODE_PAE:
3399	{
3400	uint32_t u32Dummy, u32Features;
3401
3402	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3403	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3404	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3405	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3406
3407	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3408	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3409	switch (pVCpu->pgm.s.enmShadowMode)
3410	{
3411	case PGMMODE_PAE:
3412	case PGMMODE_PAE_NX:
3413	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3414	break;
3415	case PGMMODE_NESTED:
3416	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3417	break;
3418	case PGMMODE_EPT:
3419	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3420	break;
3421	case PGMMODE_32_BIT:
3422	case PGMMODE_AMD64:
3423	case PGMMODE_AMD64_NX:
3424	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3425	default: AssertFailed(); break;
3426	}
3427	break;
3428	}
3429
3430	#ifdef VBOX_WITH_64_BITS_GUESTS
3431	case PGMMODE_AMD64_NX:
3432	case PGMMODE_AMD64:
3433	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3434	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3435	switch (pVCpu->pgm.s.enmShadowMode)
3436	{
3437	case PGMMODE_AMD64:
3438	case PGMMODE_AMD64_NX:
3439	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3440	break;
3441	case PGMMODE_NESTED:
3442	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3443	break;
3444	case PGMMODE_EPT:
3445	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3446	break;
3447	case PGMMODE_32_BIT:
3448	case PGMMODE_PAE:
3449	case PGMMODE_PAE_NX:
3450	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3451	default: AssertFailed(); break;
3452	}
3453	break;
3454	#endif
3455
3456	default:
3457	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3458	rc = VERR_NOT_IMPLEMENTED;
3459	break;
3460	}
3461
3462	/* status codes. */
3463	AssertRC(rc);
3464	AssertRC(rc2);
3465	if (RT_SUCCESS(rc))
3466	{
3467	rc = rc2;
3468	if (RT_SUCCESS(rc)) /* no informational status codes. */
3469	rc = VINF_SUCCESS;
3470	}
3471
3472	/* Notify HWACCM as well. */
3473	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3474	return rc;
3475	}
3476
3477
3478	/**
3479	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3480	*
3481	* @returns VBox status code, fully asserted.
3482	* @param pVM The VM handle.
3483	* @param pVCpu The VMCPU to operate on.
3484	*/
3485	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3486	{
3487	/* Unmap the old CR3 value before flushing everything. */
3488	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3489	AssertRC(rc);
3490
3491	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3492	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3493	AssertRC(rc);
3494	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3495	return rc;
3496	}
3497
3498
3499	/**
3500	* Called by pgmPoolFlushAllInt after flushing the pool.
3501	*
3502	* @returns VBox status code, fully asserted.
3503	* @param pVM The VM handle.
3504	* @param pVCpu The VMCPU to operate on.
3505	*/
3506	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3507	{
3508	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3509	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3510	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3511	AssertRCReturn(rc, rc);
3512	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3513
3514	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3515	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3516	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3517	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3518	return rc;
3519	}
3520
3521
3522	/**
3523	* Dumps a PAE shadow page table.
3524	*
3525	* @returns VBox status code (VINF_SUCCESS).
3526	* @param pVM The VM handle.
3527	* @param pPT Pointer to the page table.
3528	* @param u64Address The virtual address of the page table starts.
3529	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3530	* @param cMaxDepth The maxium depth.
3531	* @param pHlp Pointer to the output functions.
3532	*/
3533	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3534	{
3535	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3536	{
3537	X86PTEPAE Pte = pPT->a[i];
3538	if (Pte.n.u1Present)
3539	{
3540	pHlp->pfnPrintf(pHlp,
3541	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3542	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3543	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3544	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3545	Pte.n.u1Write ? 'W' : 'R',
3546	Pte.n.u1User ? 'U' : 'S',
3547	Pte.n.u1Accessed ? 'A' : '-',
3548	Pte.n.u1Dirty ? 'D' : '-',
3549	Pte.n.u1Global ? 'G' : '-',
3550	Pte.n.u1WriteThru ? "WT" : "--",
3551	Pte.n.u1CacheDisable? "CD" : "--",
3552	Pte.n.u1PAT ? "AT" : "--",
3553	Pte.n.u1NoExecute ? "NX" : "--",
3554	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3555	Pte.u & RT_BIT(10) ? '1' : '0',
3556	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3557	Pte.u & X86_PTE_PAE_PG_MASK);
3558	}
3559	}
3560	return VINF_SUCCESS;
3561	}
3562
3563
3564	/**
3565	* Dumps a PAE shadow page directory table.
3566	*
3567	* @returns VBox status code (VINF_SUCCESS).
3568	* @param pVM The VM handle.
3569	* @param HCPhys The physical address of the page directory table.
3570	* @param u64Address The virtual address of the page table starts.
3571	* @param cr4 The CR4, PSE is currently used.
3572	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3573	* @param cMaxDepth The maxium depth.
3574	* @param pHlp Pointer to the output functions.
3575	*/
3576	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3577	{
3578	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3579	if (!pPD)
3580	{
3581	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3582	fLongMode ? 16 : 8, u64Address, HCPhys);
3583	return VERR_INVALID_PARAMETER;
3584	}
3585	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3586
3587	int rc = VINF_SUCCESS;
3588	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3589	{
3590	X86PDEPAE Pde = pPD->a[i];
3591	if (Pde.n.u1Present)
3592	{
3593	if (fBigPagesSupported && Pde.b.u1Size)
3594	pHlp->pfnPrintf(pHlp,
3595	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3596	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3597	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3598	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3599	Pde.b.u1Write ? 'W' : 'R',
3600	Pde.b.u1User ? 'U' : 'S',
3601	Pde.b.u1Accessed ? 'A' : '-',
3602	Pde.b.u1Dirty ? 'D' : '-',
3603	Pde.b.u1Global ? 'G' : '-',
3604	Pde.b.u1WriteThru ? "WT" : "--",
3605	Pde.b.u1CacheDisable? "CD" : "--",
3606	Pde.b.u1PAT ? "AT" : "--",
3607	Pde.b.u1NoExecute ? "NX" : "--",
3608	Pde.u & RT_BIT_64(9) ? '1' : '0',
3609	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3610	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3611	Pde.u & X86_PDE_PAE_PG_MASK);
3612	else
3613	{
3614	pHlp->pfnPrintf(pHlp,
3615	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3616	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3617	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3618	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3619	Pde.n.u1Write ? 'W' : 'R',
3620	Pde.n.u1User ? 'U' : 'S',
3621	Pde.n.u1Accessed ? 'A' : '-',
3622	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3623	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3624	Pde.n.u1WriteThru ? "WT" : "--",
3625	Pde.n.u1CacheDisable? "CD" : "--",
3626	Pde.n.u1NoExecute ? "NX" : "--",
3627	Pde.u & RT_BIT_64(9) ? '1' : '0',
3628	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3629	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3630	Pde.u & X86_PDE_PAE_PG_MASK);
3631	if (cMaxDepth >= 1)
3632	{
3633	/** @todo what about using the page pool for mapping PTs? */
3634	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3635	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3636	PX86PTPAE pPT = NULL;
3637	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3638	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3639	else
3640	{
3641	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3642	{
3643	uint64_t off = u64AddressPT - pMap->GCPtr;
3644	if (off < pMap->cb)
3645	{
3646	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3647	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3648	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3649	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3650	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3651	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3652	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3653	}
3654	}
3655	}
3656	int rc2 = VERR_INVALID_PARAMETER;
3657	if (pPT)
3658	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3659	else
3660	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3661	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3662	if (rc2 < rc && RT_SUCCESS(rc))
3663	rc = rc2;
3664	}
3665	}
3666	}
3667	}
3668	return rc;
3669	}
3670
3671
3672	/**
3673	* Dumps a PAE shadow page directory pointer table.
3674	*
3675	* @returns VBox status code (VINF_SUCCESS).
3676	* @param pVM The VM handle.
3677	* @param HCPhys The physical address of the page directory pointer table.
3678	* @param u64Address The virtual address of the page table starts.
3679	* @param cr4 The CR4, PSE is currently used.
3680	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3681	* @param cMaxDepth The maxium depth.
3682	* @param pHlp Pointer to the output functions.
3683	*/
3684	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3685	{
3686	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3687	if (!pPDPT)
3688	{
3689	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3690	fLongMode ? 16 : 8, u64Address, HCPhys);
3691	return VERR_INVALID_PARAMETER;
3692	}
3693
3694	int rc = VINF_SUCCESS;
3695	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3696	for (unsigned i = 0; i < c; i++)
3697	{
3698	X86PDPE Pdpe = pPDPT->a[i];
3699	if (Pdpe.n.u1Present)
3700	{
3701	if (fLongMode)
3702	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3703	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3704	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3705	Pdpe.lm.u1Write ? 'W' : 'R',
3706	Pdpe.lm.u1User ? 'U' : 'S',
3707	Pdpe.lm.u1Accessed ? 'A' : '-',
3708	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3709	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3710	Pdpe.lm.u1WriteThru ? "WT" : "--",
3711	Pdpe.lm.u1CacheDisable? "CD" : "--",
3712	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3713	Pdpe.lm.u1NoExecute ? "NX" : "--",
3714	Pdpe.u & RT_BIT(9) ? '1' : '0',
3715	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3716	Pdpe.u & RT_BIT(11) ? '1' : '0',
3717	Pdpe.u & X86_PDPE_PG_MASK);
3718	else
3719	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3720	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3721	i << X86_PDPT_SHIFT,
3722	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3723	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3724	Pdpe.n.u1WriteThru ? "WT" : "--",
3725	Pdpe.n.u1CacheDisable? "CD" : "--",
3726	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3727	Pdpe.u & RT_BIT(9) ? '1' : '0',
3728	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3729	Pdpe.u & RT_BIT(11) ? '1' : '0',
3730	Pdpe.u & X86_PDPE_PG_MASK);
3731	if (cMaxDepth >= 1)
3732	{
3733	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3734	cr4, fLongMode, cMaxDepth - 1, pHlp);
3735	if (rc2 < rc && RT_SUCCESS(rc))
3736	rc = rc2;
3737	}
3738	}
3739	}
3740	return rc;
3741	}
3742
3743
3744	/**
3745	* Dumps a 32-bit shadow page table.
3746	*
3747	* @returns VBox status code (VINF_SUCCESS).
3748	* @param pVM The VM handle.
3749	* @param HCPhys The physical address of the table.
3750	* @param cr4 The CR4, PSE is currently used.
3751	* @param cMaxDepth The maxium depth.
3752	* @param pHlp Pointer to the output functions.
3753	*/
3754	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3755	{
3756	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3757	if (!pPML4)
3758	{
3759	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3760	return VERR_INVALID_PARAMETER;
3761	}
3762
3763	int rc = VINF_SUCCESS;
3764	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3765	{
3766	X86PML4E Pml4e = pPML4->a[i];
3767	if (Pml4e.n.u1Present)
3768	{
3769	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3770	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3771	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3772	u64Address,
3773	Pml4e.n.u1Write ? 'W' : 'R',
3774	Pml4e.n.u1User ? 'U' : 'S',
3775	Pml4e.n.u1Accessed ? 'A' : '-',
3776	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3777	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3778	Pml4e.n.u1WriteThru ? "WT" : "--",
3779	Pml4e.n.u1CacheDisable? "CD" : "--",
3780	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3781	Pml4e.n.u1NoExecute ? "NX" : "--",
3782	Pml4e.u & RT_BIT(9) ? '1' : '0',
3783	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3784	Pml4e.u & RT_BIT(11) ? '1' : '0',
3785	Pml4e.u & X86_PML4E_PG_MASK);
3786
3787	if (cMaxDepth >= 1)
3788	{
3789	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3790	if (rc2 < rc && RT_SUCCESS(rc))
3791	rc = rc2;
3792	}
3793	}
3794	}
3795	return rc;
3796	}
3797
3798
3799	/**
3800	* Dumps a 32-bit shadow page table.
3801	*
3802	* @returns VBox status code (VINF_SUCCESS).
3803	* @param pVM The VM handle.
3804	* @param pPT Pointer to the page table.
3805	* @param u32Address The virtual address this table starts at.
3806	* @param pHlp Pointer to the output functions.
3807	*/
3808	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3809	{
3810	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3811	{
3812	X86PTE Pte = pPT->a[i];
3813	if (Pte.n.u1Present)
3814	{
3815	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3816	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3817	u32Address + (i << X86_PT_SHIFT),
3818	Pte.n.u1Write ? 'W' : 'R',
3819	Pte.n.u1User ? 'U' : 'S',
3820	Pte.n.u1Accessed ? 'A' : '-',
3821	Pte.n.u1Dirty ? 'D' : '-',
3822	Pte.n.u1Global ? 'G' : '-',
3823	Pte.n.u1WriteThru ? "WT" : "--",
3824	Pte.n.u1CacheDisable? "CD" : "--",
3825	Pte.n.u1PAT ? "AT" : "--",
3826	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3827	Pte.u & RT_BIT(10) ? '1' : '0',
3828	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3829	Pte.u & X86_PDE_PG_MASK);
3830	}
3831	}
3832	return VINF_SUCCESS;
3833	}
3834
3835
3836	/**
3837	* Dumps a 32-bit shadow page directory and page tables.
3838	*
3839	* @returns VBox status code (VINF_SUCCESS).
3840	* @param pVM The VM handle.
3841	* @param cr3 The root of the hierarchy.
3842	* @param cr4 The CR4, PSE is currently used.
3843	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3844	* @param pHlp Pointer to the output functions.
3845	*/
3846	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3847	{
3848	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3849	if (!pPD)
3850	{
3851	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3852	return VERR_INVALID_PARAMETER;
3853	}
3854
3855	int rc = VINF_SUCCESS;
3856	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3857	{
3858	X86PDE Pde = pPD->a[i];
3859	if (Pde.n.u1Present)
3860	{
3861	const uint32_t u32Address = i << X86_PD_SHIFT;
3862	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3863	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3864	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3865	u32Address,
3866	Pde.b.u1Write ? 'W' : 'R',
3867	Pde.b.u1User ? 'U' : 'S',
3868	Pde.b.u1Accessed ? 'A' : '-',
3869	Pde.b.u1Dirty ? 'D' : '-',
3870	Pde.b.u1Global ? 'G' : '-',
3871	Pde.b.u1WriteThru ? "WT" : "--",
3872	Pde.b.u1CacheDisable? "CD" : "--",
3873	Pde.b.u1PAT ? "AT" : "--",
3874	Pde.u & RT_BIT_64(9) ? '1' : '0',
3875	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3876	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3877	Pde.u & X86_PDE4M_PG_MASK);
3878	else
3879	{
3880	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3881	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3882	u32Address,
3883	Pde.n.u1Write ? 'W' : 'R',
3884	Pde.n.u1User ? 'U' : 'S',
3885	Pde.n.u1Accessed ? 'A' : '-',
3886	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3887	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3888	Pde.n.u1WriteThru ? "WT" : "--",
3889	Pde.n.u1CacheDisable? "CD" : "--",
3890	Pde.u & RT_BIT_64(9) ? '1' : '0',
3891	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3892	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3893	Pde.u & X86_PDE_PG_MASK);
3894	if (cMaxDepth >= 1)
3895	{
3896	/** @todo what about using the page pool for mapping PTs? */
3897	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3898	PX86PT pPT = NULL;
3899	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3900	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3901	else
3902	{
3903	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3904	if (u32Address - pMap->GCPtr < pMap->cb)
3905	{
3906	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3907	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3908	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3909	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3910	pPT = pMap->aPTs[iPDE].pPTR3;
3911	}
3912	}
3913	int rc2 = VERR_INVALID_PARAMETER;
3914	if (pPT)
3915	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3916	else
3917	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3918	if (rc2 < rc && RT_SUCCESS(rc))
3919	rc = rc2;
3920	}
3921	}
3922	}
3923	}
3924
3925	return rc;
3926	}
3927
3928
3929	/**
3930	* Dumps a 32-bit shadow page table.
3931	*
3932	* @returns VBox status code (VINF_SUCCESS).
3933	* @param pVM The VM handle.
3934	* @param pPT Pointer to the page table.
3935	* @param u32Address The virtual address this table starts at.
3936	* @param PhysSearch Address to search for.
3937	*/
3938	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3939	{
3940	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3941	{
3942	X86PTE Pte = pPT->a[i];
3943	if (Pte.n.u1Present)
3944	{
3945	Log(( /P R S A D G WT CD AT NX 4M a m d /
3946	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3947	u32Address + (i << X86_PT_SHIFT),
3948	Pte.n.u1Write ? 'W' : 'R',
3949	Pte.n.u1User ? 'U' : 'S',
3950	Pte.n.u1Accessed ? 'A' : '-',
3951	Pte.n.u1Dirty ? 'D' : '-',
3952	Pte.n.u1Global ? 'G' : '-',
3953	Pte.n.u1WriteThru ? "WT" : "--",
3954	Pte.n.u1CacheDisable? "CD" : "--",
3955	Pte.n.u1PAT ? "AT" : "--",
3956	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3957	Pte.u & RT_BIT(10) ? '1' : '0',
3958	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3959	Pte.u & X86_PDE_PG_MASK));
3960
3961	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3962	{
3963	uint64_t fPageShw = 0;
3964	RTHCPHYS pPhysHC = 0;
3965
3966	/** @todo SMP support!! */
3967	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3968	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3969	}
3970	}
3971	}
3972	return VINF_SUCCESS;
3973	}
3974
3975
3976	/**
3977	* Dumps a 32-bit guest page directory and page tables.
3978	*
3979	* @returns VBox status code (VINF_SUCCESS).
3980	* @param pVM The VM handle.
3981	* @param cr3 The root of the hierarchy.
3982	* @param cr4 The CR4, PSE is currently used.
3983	* @param PhysSearch Address to search for.
3984	*/
3985	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3986	{
3987	bool fLongMode = false;
3988	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3989	PX86PD pPD = 0;
3990	PGMPAGEMAPLOCK LockCr3;
3991
3992	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
3993	if ( RT_FAILURE(rc)
3994	\|\| !pPD)
3995	{
3996	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3997	return VERR_INVALID_PARAMETER;
3998	}
3999
4000	Log(("cr3=%08x cr4=%08x%s\n"
4001	"%-*s P - Present\n"
4002	"%-*s \| R/W - Read (0) / Write (1)\n"
4003	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4004	"%-*s \| \| \| A - Accessed\n"
4005	"%-*s \| \| \| \| D - Dirty\n"
4006	"%-*s \| \| \| \| \| G - Global\n"
4007	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4008	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4009	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4010	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4011	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4012	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4013	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4014	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4015	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4016	- W U - - - -- -- -- -- -- 010 */
4017	, cr3, cr4, fLongMode ? " Long Mode" : "",
4018	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4019	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4020
4021	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4022	{
4023	X86PDE Pde = pPD->a[i];
4024	if (Pde.n.u1Present)
4025	{
4026	const uint32_t u32Address = i << X86_PD_SHIFT;
4027
4028	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4029	Log(( /P R S A D G WT CD AT NX 4M a m d /
4030	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4031	u32Address,
4032	Pde.b.u1Write ? 'W' : 'R',
4033	Pde.b.u1User ? 'U' : 'S',
4034	Pde.b.u1Accessed ? 'A' : '-',
4035	Pde.b.u1Dirty ? 'D' : '-',
4036	Pde.b.u1Global ? 'G' : '-',
4037	Pde.b.u1WriteThru ? "WT" : "--",
4038	Pde.b.u1CacheDisable? "CD" : "--",
4039	Pde.b.u1PAT ? "AT" : "--",
4040	Pde.u & RT_BIT(9) ? '1' : '0',
4041	Pde.u & RT_BIT(10) ? '1' : '0',
4042	Pde.u & RT_BIT(11) ? '1' : '0',
4043	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4044	/** @todo PhysSearch */
4045	else
4046	{
4047	Log(( /P R S A D G WT CD AT NX 4M a m d /
4048	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4049	u32Address,
4050	Pde.n.u1Write ? 'W' : 'R',
4051	Pde.n.u1User ? 'U' : 'S',
4052	Pde.n.u1Accessed ? 'A' : '-',
4053	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4054	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4055	Pde.n.u1WriteThru ? "WT" : "--",
4056	Pde.n.u1CacheDisable? "CD" : "--",
4057	Pde.u & RT_BIT(9) ? '1' : '0',
4058	Pde.u & RT_BIT(10) ? '1' : '0',
4059	Pde.u & RT_BIT(11) ? '1' : '0',
4060	Pde.u & X86_PDE_PG_MASK));
4061	////if (cMaxDepth >= 1)
4062	{
4063	/** @todo what about using the page pool for mapping PTs? */
4064	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4065	PX86PT pPT = NULL;
4066	PGMPAGEMAPLOCK LockPT;
4067
4068	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
4069
4070	int rc2 = VERR_INVALID_PARAMETER;
4071	if (pPT)
4072	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4073	else
4074	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4075
4076	if (rc == VINF_SUCCESS)
4077	PGMPhysReleasePageMappingLock(pVM, &LockPT);
4078
4079	if (rc2 < rc && RT_SUCCESS(rc))
4080	rc = rc2;
4081	}
4082	}
4083	}
4084	}
4085	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
4086	return rc;
4087	}
4088
4089
4090	/**
4091	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4092	*
4093	* @returns VBox status code (VINF_SUCCESS).
4094	* @param pVM The VM handle.
4095	* @param cr3 The root of the hierarchy.
4096	* @param cr4 The cr4, only PAE and PSE is currently used.
4097	* @param fLongMode Set if long mode, false if not long mode.
4098	* @param cMaxDepth Number of levels to dump.
4099	* @param pHlp Pointer to the output functions.
4100	*/
4101	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4102	{
4103	if (!pHlp)
4104	pHlp = DBGFR3InfoLogHlp();
4105	if (!cMaxDepth)
4106	return VINF_SUCCESS;
4107	const unsigned cch = fLongMode ? 16 : 8;
4108	pHlp->pfnPrintf(pHlp,
4109	"cr3=%08x cr4=%08x%s\n"
4110	"%-*s P - Present\n"
4111	"%-*s \| R/W - Read (0) / Write (1)\n"
4112	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4113	"%-*s \| \| \| A - Accessed\n"
4114	"%-*s \| \| \| \| D - Dirty\n"
4115	"%-*s \| \| \| \| \| G - Global\n"
4116	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4117	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4118	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4119	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4120	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4121	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4122	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4123	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4124	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4125	- W U - - - -- -- -- -- -- 010 */
4126	, cr3, cr4, fLongMode ? " Long Mode" : "",
4127	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4128	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4129	if (cr4 & X86_CR4_PAE)
4130	{
4131	if (fLongMode)
4132	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4133	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4134	}
4135	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4136	}
4137
4138	#ifdef VBOX_WITH_DEBUGGER
4139
4140	/**
4141	* The '.pgmram' command.
4142	*
4143	* @returns VBox status.
4144	* @param pCmd Pointer to the command descriptor (as registered).
4145	* @param pCmdHlp Pointer to command helper functions.
4146	* @param pVM Pointer to the current VM (if any).
4147	* @param paArgs Pointer to (readonly) array of arguments.
4148	* @param cArgs Number of arguments in the array.
4149	*/
4150	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4151	{
4152	/*
4153	* Validate input.
4154	*/
4155	if (!pVM)
4156	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4157	if (!pVM->pgm.s.pRamRangesRC)
4158	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4159
4160	/*
4161	* Dump the ranges.
4162	*/
4163	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4164	PPGMRAMRANGE pRam;
4165	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4166	{
4167	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4168	"%RGp - %RGp %p\n",
4169	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4170	if (RT_FAILURE(rc))
4171	return rc;
4172	}
4173
4174	return VINF_SUCCESS;
4175	}
4176
4177
4178	/**
4179	* The '.pgmerror' and '.pgmerroroff' commands.
4180	*
4181	* @returns VBox status.
4182	* @param pCmd Pointer to the command descriptor (as registered).
4183	* @param pCmdHlp Pointer to command helper functions.
4184	* @param pVM Pointer to the current VM (if any).
4185	* @param paArgs Pointer to (readonly) array of arguments.
4186	* @param cArgs Number of arguments in the array.
4187	*/
4188	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4189	{
4190	/*
4191	* Validate input.
4192	*/
4193	if (!pVM)
4194	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4195	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4196	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4197
4198	if (!cArgs)
4199	{
4200	/*
4201	* Print the list of error injection locations with status.
4202	*/
4203	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4204	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4205	}
4206	else
4207	{
4208
4209	/*
4210	* String switch on where to inject the error.
4211	*/
4212	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4213	const char *pszWhere = paArgs[0].u.pszString;
4214	if (!strcmp(pszWhere, "handy"))
4215	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4216	else
4217	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4218	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4219	}
4220	return VINF_SUCCESS;
4221	}
4222
4223
4224	/**
4225	* The '.pgmsync' command.
4226	*
4227	* @returns VBox status.
4228	* @param pCmd Pointer to the command descriptor (as registered).
4229	* @param pCmdHlp Pointer to command helper functions.
4230	* @param pVM Pointer to the current VM (if any).
4231	* @param paArgs Pointer to (readonly) array of arguments.
4232	* @param cArgs Number of arguments in the array.
4233	*/
4234	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4235	{
4236	/** @todo SMP support */
4237	PVMCPU pVCpu = &pVM->aCpus[0];
4238
4239	/*
4240	* Validate input.
4241	*/
4242	if (!pVM)
4243	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4244
4245	/*
4246	* Force page directory sync.
4247	*/
4248	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4249
4250	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4251	if (RT_FAILURE(rc))
4252	return rc;
4253
4254	return VINF_SUCCESS;
4255	}
4256
4257
4258	#ifdef VBOX_STRICT
4259	/**
4260	* The '.pgmassertcr3' command.
4261	*
4262	* @returns VBox status.
4263	* @param pCmd Pointer to the command descriptor (as registered).
4264	* @param pCmdHlp Pointer to command helper functions.
4265	* @param pVM Pointer to the current VM (if any).
4266	* @param paArgs Pointer to (readonly) array of arguments.
4267	* @param cArgs Number of arguments in the array.
4268	*/
4269	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4270	{
4271	/** @todo SMP support!! */
4272	PVMCPU pVCpu = &pVM->aCpus[0];
4273
4274	/*
4275	* Validate input.
4276	*/
4277	if (!pVM)
4278	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4279
4280	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4281	if (RT_FAILURE(rc))
4282	return rc;
4283
4284	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4285
4286	return VINF_SUCCESS;
4287	}
4288	#endif /* VBOX_STRICT */
4289
4290
4291	/**
4292	* The '.pgmsyncalways' command.
4293	*
4294	* @returns VBox status.
4295	* @param pCmd Pointer to the command descriptor (as registered).
4296	* @param pCmdHlp Pointer to command helper functions.
4297	* @param pVM Pointer to the current VM (if any).
4298	* @param paArgs Pointer to (readonly) array of arguments.
4299	* @param cArgs Number of arguments in the array.
4300	*/
4301	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4302	{
4303	/** @todo SMP support!! */
4304	PVMCPU pVCpu = &pVM->aCpus[0];
4305
4306	/*
4307	* Validate input.
4308	*/
4309	if (!pVM)
4310	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4311
4312	/*
4313	* Force page directory sync.
4314	*/
4315	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4316	{
4317	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4318	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4319	}
4320	else
4321	{
4322	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4323	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4324	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4325	}
4326	}
4327
4328
4329	/**
4330	* The '.pgmsyncalways' command.
4331	*
4332	* @returns VBox status.
4333	* @param pCmd Pointer to the command descriptor (as registered).
4334	* @param pCmdHlp Pointer to command helper functions.
4335	* @param pVM Pointer to the current VM (if any).
4336	* @param paArgs Pointer to (readonly) array of arguments.
4337	* @param cArgs Number of arguments in the array.
4338	*/
4339	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4340	{
4341	/*
4342	* Validate input.
4343	*/
4344	if (!pVM)
4345	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4346	if ( cArgs < 1
4347	\|\| cArgs > 2
4348	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4349	\|\| ( cArgs > 1
4350	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4351	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4352	if ( cArgs >= 2
4353	&& strcmp(paArgs[1].u.pszString, "nozero"))
4354	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4355	bool fIncZeroPgs = cArgs < 2;
4356
4357	/*
4358	* Open the output file and get the ram parameters.
4359	*/
4360	RTFILE hFile;
4361	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4362	if (RT_FAILURE(rc))
4363	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4364
4365	uint32_t cbRamHole = 0;
4366	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4367	uint64_t cbRam = 0;
4368	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4369	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4370
4371	/*
4372	* Dump the physical memory, page by page.
4373	*/
4374	RTGCPHYS GCPhys = 0;
4375	char abZeroPg[PAGE_SIZE];
4376	RT_ZERO(abZeroPg);
4377
4378	pgmLock(pVM);
4379	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4380	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4381	pRam = pRam->pNextR3)
4382	{
4383	/* fill the gap */
4384	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4385	{
4386	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4387	{
4388	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4389	GCPhys += PAGE_SIZE;
4390	}
4391	}
4392
4393	PCPGMPAGE pPage = &pRam->aPages[0];
4394	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4395	{
4396	if ( PGM_PAGE_IS_ZERO(pPage)
4397	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4398	{
4399	if (fIncZeroPgs)
4400	{
4401	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4402	if (RT_FAILURE(rc))
4403	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4404	}
4405	}
4406	else
4407	{
4408	switch (PGM_PAGE_GET_TYPE(pPage))
4409	{
4410	case PGMPAGETYPE_RAM:
4411	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4412	case PGMPAGETYPE_ROM:
4413	case PGMPAGETYPE_MMIO2:
4414	{
4415	void const *pvPage;
4416	PGMPAGEMAPLOCK Lock;
4417	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4418	if (RT_SUCCESS(rc))
4419	{
4420	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4421	PGMPhysReleasePageMappingLock(pVM, &Lock);
4422	if (RT_FAILURE(rc))
4423	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4424	}
4425	else
4426	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4427	break;
4428	}
4429
4430	default:
4431	AssertFailed();
4432	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4433	case PGMPAGETYPE_MMIO:
4434	if (fIncZeroPgs)
4435	{
4436	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4437	if (RT_FAILURE(rc))
4438	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4439	}
4440	break;
4441	}
4442	}
4443
4444
4445	/* advance */
4446	GCPhys += PAGE_SIZE;
4447	pPage++;
4448	}
4449	}
4450	pgmUnlock(pVM);
4451
4452	RTFileClose(hFile);
4453	if (RT_SUCCESS(rc))
4454	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4455	return VINF_SUCCESS;
4456	}
4457
4458	#endif /* VBOX_WITH_DEBUGGER */
4459
4460	/**
4461	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4462	*/
4463	typedef struct PGMCHECKINTARGS
4464	{
4465	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4466	PPGMPHYSHANDLER pPrevPhys;
4467	PPGMVIRTHANDLER pPrevVirt;
4468	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4469	PVM pVM;
4470	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4471
4472	/**
4473	* Validate a node in the physical handler tree.
4474	*
4475	* @returns 0 on if ok, other wise 1.
4476	* @param pNode The handler node.
4477	* @param pvUser pVM.
4478	*/
4479	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4480	{
4481	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4482	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4483	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4484	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4485	AssertReleaseMsg( !pArgs->pPrevPhys
4486	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4487	("pPrevPhys=%p %RGp-%RGp %s\n"
4488	" pCur=%p %RGp-%RGp %s\n",
4489	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4490	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4491	pArgs->pPrevPhys = pCur;
4492	return 0;
4493	}
4494
4495
4496	/**
4497	* Validate a node in the virtual handler tree.
4498	*
4499	* @returns 0 on if ok, other wise 1.
4500	* @param pNode The handler node.
4501	* @param pvUser pVM.
4502	*/
4503	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4504	{
4505	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4506	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4507	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4508	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4509	AssertReleaseMsg( !pArgs->pPrevVirt
4510	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4511	("pPrevVirt=%p %RGv-%RGv %s\n"
4512	" pCur=%p %RGv-%RGv %s\n",
4513	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4514	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4515	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4516	{
4517	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4518	("pCur=%p %RGv-%RGv %s\n"
4519	"iPage=%d offVirtHandle=%#x expected %#x\n",
4520	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4521	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4522	}
4523	pArgs->pPrevVirt = pCur;
4524	return 0;
4525	}
4526
4527
4528	/**
4529	* Validate a node in the virtual handler tree.
4530	*
4531	* @returns 0 on if ok, other wise 1.
4532	* @param pNode The handler node.
4533	* @param pvUser pVM.
4534	*/
4535	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4536	{
4537	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4538	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4539	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4540	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4541	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4542	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4543	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4544	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4545	" pCur=%p %RGp-%RGp\n",
4546	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4547	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4548	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4549	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4550	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4551	" pCur=%p %RGp-%RGp\n",
4552	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4553	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4554	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4555	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4556	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4557	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4558	{
4559	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4560	for (;;)
4561	{
4562	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4563	AssertReleaseMsg(pCur2 != pCur,
4564	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4565	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4566	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4567	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4568	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4569	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4570	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4571	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4572	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4573	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4574	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4575	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4576	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4577	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4578	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4579	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4580	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4581	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4582	break;
4583	}
4584	}
4585
4586	pArgs->pPrevPhys2Virt = pCur;
4587	return 0;
4588	}
4589
4590
4591	/**
4592	* Perform an integrity check on the PGM component.
4593	*
4594	* @returns VINF_SUCCESS if everything is fine.
4595	* @returns VBox error status after asserting on integrity breach.
4596	* @param pVM The VM handle.
4597	*/
4598	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4599	{
4600	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4601
4602	/*
4603	* Check the trees.
4604	*/
4605	int cErrors = 0;
4606	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4607	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4608	PGMCHECKINTARGS Args = s_LeftToRight;
4609	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4610	Args = s_RightToLeft;
4611	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4612	Args = s_LeftToRight;
4613	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4614	Args = s_RightToLeft;
4615	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4616	Args = s_LeftToRight;
4617	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4618	Args = s_RightToLeft;
4619	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4620	Args = s_LeftToRight;
4621	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4622	Args = s_RightToLeft;
4623	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4624
4625	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4626	}
4627

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 31589

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