PGM.cpp@ 850

Last change on this file since 850 was 838, checked in by vboxsync, 18 years ago
GC Phys to HC virt conversion changes for dynamic RAM allocation.
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1	/* $Id: PGM.cpp 838 2007-02-12 12:05:52Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pg_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pg_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPTR and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pg_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pg_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pg_misc Misc
97	*
98	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*/
111
112
113
114	/** Saved state data unit version. */
115	#define PGM_SAVED_STATE_VERSION 5
116
117	/*******************************************************************************
118	* Header Files *
119	*******************************************************************************/
120	#define LOG_GROUP LOG_GROUP_PGM
121	#include <VBox/dbgf.h>
122	#include <VBox/pgm.h>
123	#include <VBox/cpum.h>
124	#include <VBox/iom.h>
125	#include <VBox/sup.h>
126	#include <VBox/mm.h>
127	#include <VBox/pdm.h>
128	#include <VBox/em.h>
129	#include <VBox/stam.h>
130	#include <VBox/rem.h>
131	#include <VBox/dbgf.h>
132	#include <VBox/rem.h>
133	#include <VBox/selm.h>
134	#include <VBox/ssm.h>
135	#include "PGMInternal.h"
136	#include <VBox/vm.h>
137	#include <VBox/dbg.h>
138	#include <VBox/hwaccm.h>
139
140	#include <VBox/log.h>
141	#include <iprt/assert.h>
142	#include <iprt/alloc.h>
143	#include <iprt/asm.h>
144	#include <iprt/thread.h>
145	#include <iprt/string.h>
146	#include <VBox/param.h>
147	#include <VBox/err.h>
148
149
150
151	/*******************************************************************************
152	* Internal Functions *
153	*******************************************************************************/
154	static int pgmR3InitPaging(PVM pVM);
155	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
157	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
158	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
159	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
160	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
161	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
162	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
163	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
164	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
165
166	#ifdef VBOX_WITH_STATISTICS
167	static void pgmR3InitStats(PVM pVM);
168	#endif
169
170	#ifdef VBOX_WITH_DEBUGGER
171	/** @todo all but the two last commands must be converted to 'info'. */
172	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
173	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
174	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
175	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
176	#endif
177
178
179	/*******************************************************************************
180	* Global Variables *
181	*******************************************************************************/
182	#ifdef VBOX_WITH_DEBUGGER
183	/** Command descriptors. */
184	static const DBGCCMD g_aCmds[] =
185	{
186	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
187	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
188	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
189	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
190	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
191	};
192	#endif
193
194
195
196
197	#if 1/// @todo ndef __AMD64__
198	/*
199	* Shadow - 32-bit mode
200	*/
201	#define PGM_SHW_TYPE PGM_TYPE_32BIT
202	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
203	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
204	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
205	#include "PGMShw.h"
206
207	/* Guest - real mode */
208	#define PGM_GST_TYPE PGM_TYPE_REAL
209	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
210	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
211	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
212	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
213	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
214	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
215	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
216	#include "PGMGst.h"
217	#include "PGMBth.h"
218	#undef BTH_PGMPOOLKIND_PT_FOR_PT
219	#undef PGM_BTH_NAME
220	#undef PGM_BTH_NAME_GC_STR
221	#undef PGM_BTH_NAME_R0_STR
222	#undef PGM_GST_TYPE
223	#undef PGM_GST_NAME
224	#undef PGM_GST_NAME_GC_STR
225	#undef PGM_GST_NAME_R0_STR
226
227	/* Guest - protected mode */
228	#define PGM_GST_TYPE PGM_TYPE_PROT
229	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
230	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
231	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
232	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
233	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
234	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
235	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
236	#include "PGMGst.h"
237	#include "PGMBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef PGM_BTH_NAME
240	#undef PGM_BTH_NAME_GC_STR
241	#undef PGM_BTH_NAME_R0_STR
242	#undef PGM_GST_TYPE
243	#undef PGM_GST_NAME
244	#undef PGM_GST_NAME_GC_STR
245	#undef PGM_GST_NAME_R0_STR
246
247	/* Guest - 32-bit mode */
248	#define PGM_GST_TYPE PGM_TYPE_32BIT
249	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
251	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
252	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
253	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
254	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
255	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
256	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
257	#include "PGMGst.h"
258	#include "PGMBth.h"
259	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
260	#undef BTH_PGMPOOLKIND_PT_FOR_PT
261	#undef PGM_BTH_NAME
262	#undef PGM_BTH_NAME_GC_STR
263	#undef PGM_BTH_NAME_R0_STR
264	#undef PGM_GST_TYPE
265	#undef PGM_GST_NAME
266	#undef PGM_GST_NAME_GC_STR
267	#undef PGM_GST_NAME_R0_STR
268
269	#undef PGM_SHW_TYPE
270	#undef PGM_SHW_NAME
271	#undef PGM_SHW_NAME_GC_STR
272	#undef PGM_SHW_NAME_R0_STR
273	#endif /* !__AMD64__ */
274
275
276	/*
277	* Shadow - PAE mode
278	*/
279	#define PGM_SHW_TYPE PGM_TYPE_PAE
280	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
281	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
282	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
283	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
284	#include "PGMShw.h"
285
286	/* Guest - real mode */
287	#define PGM_GST_TYPE PGM_TYPE_REAL
288	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
289	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
290	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
291	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
292	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
293	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
294	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
295	#include "PGMBth.h"
296	#undef BTH_PGMPOOLKIND_PT_FOR_PT
297	#undef PGM_BTH_NAME
298	#undef PGM_BTH_NAME_GC_STR
299	#undef PGM_BTH_NAME_R0_STR
300	#undef PGM_GST_TYPE
301	#undef PGM_GST_NAME
302	#undef PGM_GST_NAME_GC_STR
303	#undef PGM_GST_NAME_R0_STR
304
305	/* Guest - protected mode */
306	#define PGM_GST_TYPE PGM_TYPE_PROT
307	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
308	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
309	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
310	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
311	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
312	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
313	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
314	#include "PGMBth.h"
315	#undef BTH_PGMPOOLKIND_PT_FOR_PT
316	#undef PGM_BTH_NAME
317	#undef PGM_BTH_NAME_GC_STR
318	#undef PGM_BTH_NAME_R0_STR
319	#undef PGM_GST_TYPE
320	#undef PGM_GST_NAME
321	#undef PGM_GST_NAME_GC_STR
322	#undef PGM_GST_NAME_R0_STR
323
324	/* Guest - 32-bit mode */
325	#define PGM_GST_TYPE PGM_TYPE_32BIT
326	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
327	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
328	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
329	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
330	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
331	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
332	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
333	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
334	#include "PGMBth.h"
335	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
336	#undef BTH_PGMPOOLKIND_PT_FOR_PT
337	#undef PGM_BTH_NAME
338	#undef PGM_BTH_NAME_GC_STR
339	#undef PGM_BTH_NAME_R0_STR
340	#undef PGM_GST_TYPE
341	#undef PGM_GST_NAME
342	#undef PGM_GST_NAME_GC_STR
343	#undef PGM_GST_NAME_R0_STR
344
345	/* Guest - PAE mode */
346	#define PGM_GST_TYPE PGM_TYPE_PAE
347	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
348	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
349	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
351	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
352	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
353	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
354	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
355	#include "PGMGst.h"
356	#include "PGMBth.h"
357	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
358	#undef BTH_PGMPOOLKIND_PT_FOR_PT
359	#undef PGM_BTH_NAME
360	#undef PGM_BTH_NAME_GC_STR
361	#undef PGM_BTH_NAME_R0_STR
362	#undef PGM_GST_TYPE
363	#undef PGM_GST_NAME
364	#undef PGM_GST_NAME_GC_STR
365	#undef PGM_GST_NAME_R0_STR
366
367	#undef PGM_SHW_TYPE
368	#undef PGM_SHW_NAME
369	#undef PGM_SHW_NAME_GC_STR
370	#undef PGM_SHW_NAME_R0_STR
371
372
373	/*
374	* Shadow - AMD64 mode
375	*/
376	#define PGM_SHW_TYPE PGM_TYPE_AMD64
377	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
378	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
379	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
380	#include "PGMShw.h"
381
382	/* Guest - real mode */
383	#define PGM_GST_TYPE PGM_TYPE_REAL
384	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
385	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
386	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
387	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
388	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
389	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
390	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
391	#include "PGMBth.h"
392	#undef BTH_PGMPOOLKIND_PT_FOR_PT
393	#undef PGM_BTH_NAME
394	#undef PGM_BTH_NAME_GC_STR
395	#undef PGM_BTH_NAME_R0_STR
396	#undef PGM_GST_TYPE
397	#undef PGM_GST_NAME
398	#undef PGM_GST_NAME_GC_STR
399	#undef PGM_GST_NAME_R0_STR
400
401	/* Guest - protected mode */
402	#define PGM_GST_TYPE PGM_TYPE_PROT
403	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
404	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
405	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
406	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
407	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
408	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
409	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
410	#include "PGMBth.h"
411	#undef BTH_PGMPOOLKIND_PT_FOR_PT
412	#undef PGM_BTH_NAME
413	#undef PGM_BTH_NAME_GC_STR
414	#undef PGM_BTH_NAME_R0_STR
415	#undef PGM_GST_TYPE
416	#undef PGM_GST_NAME
417	#undef PGM_GST_NAME_GC_STR
418	#undef PGM_GST_NAME_R0_STR
419
420	/* Guest - AMD64 mode */
421	#define PGM_GST_TYPE PGM_TYPE_AMD64
422	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
423	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
424	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
425	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
426	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
427	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
428	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
429	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
430	#include "PGMGst.h"
431	#include "PGMBth.h"
432	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
433	#undef BTH_PGMPOOLKIND_PT_FOR_PT
434	#undef PGM_BTH_NAME
435	#undef PGM_BTH_NAME_GC_STR
436	#undef PGM_BTH_NAME_R0_STR
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439	#undef PGM_GST_NAME_GC_STR
440	#undef PGM_GST_NAME_R0_STR
441
442	#undef PGM_SHW_TYPE
443	#undef PGM_SHW_NAME
444	#undef PGM_SHW_NAME_GC_STR
445	#undef PGM_SHW_NAME_R0_STR
446
447
448
449
450	/**
451	* Initiates the paging of VM.
452	*
453	* @returns VBox status code.
454	* @param pVM Pointer to VM structure.
455	*/
456	PGMR3DECL(int) PGMR3Init(PVM pVM)
457	{
458	LogFlow(("PGMR3Init:\n"));
459
460	/*
461	* Assert alignment and sizes.
462	*/
463	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
464
465	/*
466	* Init the structure.
467	*/
468	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
469	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
470	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
471	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
472	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
473	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
474	pVM->pgm.s.fA20Enabled = true;
475	pVM->pgm.s.pGstPaePDPTRHC = NULL;
476	pVM->pgm.s.pGstPaePDPTRGC = 0;
477	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
478	{
479	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
480	pVM->pgm.s.apGstPaePDsGC[i] = 0;
481	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
482	}
483
484	/*
485	* Get the configured RAM size - to estimate saved state size.
486	*/
487	uint64_t cbRam;
488	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
489	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
490	cbRam = pVM->pgm.s.cbRamSize = 0;
491	else if (VBOX_SUCCESS(rc))
492	{
493	if (cbRam < PAGE_SIZE)
494	cbRam = 0;
495	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
496	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
497	}
498	else
499	{
500	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
501	return rc;
502	}
503
504	/*
505	* Register saved state data unit.
506	*/
507	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
508	NULL, pgmR3Save, NULL,
509	NULL, pgmR3Load, NULL);
510	if (VBOX_FAILURE(rc))
511	return rc;
512
513	/* Initialise PGM critical section. */
514	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
515	AssertRCReturn(rc, rc);
516
517	/*
518	* Trees
519	*/
520	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
521	if (VBOX_SUCCESS(rc))
522	{
523	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
524
525	/*
526	* Init the paging.
527	*/
528	rc = pgmR3InitPaging(pVM);
529	}
530	if (VBOX_SUCCESS(rc))
531	{
532	/*
533	* Init the page pool.
534	*/
535	rc = pgmR3PoolInit(pVM);
536	}
537	if (VBOX_SUCCESS(rc))
538	{
539	/*
540	* Info & statistics
541	*/
542	DBGFR3InfoRegisterInternal(pVM, "mode",
543	"Shows the current paging mode. "
544	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
545	pgmR3InfoMode);
546	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
547	"Dumps all the entries in the top level paging table. No arguments.",
548	pgmR3InfoCr3);
549	DBGFR3InfoRegisterInternal(pVM, "phys",
550	"Dumps all the physical address ranges. No arguments.",
551	pgmR3PhysInfo);
552	DBGFR3InfoRegisterInternal(pVM, "handlers",
553	"Dumps physical and virtual handlers. "
554	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
555	pgmR3InfoHandlers);
556
557	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
558	#ifdef VBOX_WITH_STATISTICS
559	pgmR3InitStats(pVM);
560	#endif
561	#ifdef VBOX_WITH_DEBUGGER
562	/*
563	* Debugger commands.
564	*/
565	static bool fRegisteredCmds = false;
566	if (!fRegisteredCmds)
567	{
568	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
569	if (VBOX_SUCCESS(rc))
570	fRegisteredCmds = true;
571	}
572	#endif
573	return VINF_SUCCESS;
574	}
575	/* No cleanup necessary, MM frees all memory. */
576
577	return rc;
578	}
579
580
581	/**
582	* Init paging.
583	*
584	* Since we need to check what mode the host is operating in before we can choose
585	* the right paging functions for the host we have to delay this until R0 has
586	* been initialized.
587	*
588	* @returns VBox status code.
589	* @param pVM VM handle.
590	*/
591	static int pgmR3InitPaging(PVM pVM)
592	{
593	/*
594	* Force a recalculation of modes and switcher so everyone gets notified.
595	*/
596	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
597	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
598	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
599
600	/*
601	* Allocate static mapping space for whatever the cr3 register
602	* points to and in the case of PAE mode to the 4 PDs.
603	*/
604	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
605	if (VBOX_FAILURE(rc))
606	{
607	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
608	return rc;
609	}
610	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
611
612	/*
613	* Allocate pages for the three possible intermediate contexts
614	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
615	* for the sake of simplicity. The AMD64 uses the PAE for the
616	* lower levels, making the total number of pages 11 (3 + 7 + 1).
617	*
618	* We assume that two page tables will be enought for the core code
619	* mappings (HC virtual and identity).
620	*/
621	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
622	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
623	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
624	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
625	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
626	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
627	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
628	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
629	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
630	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
631	#if 1
632	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
633	#endif
634	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
635	if ( !pVM->pgm.s.pInterPD
636	\|\| !pVM->pgm.s.apInterPTs[0]
637	\|\| !pVM->pgm.s.apInterPTs[1]
638	\|\| !pVM->pgm.s.apInterPaePTs[0]
639	\|\| !pVM->pgm.s.apInterPaePTs[1]
640	\|\| !pVM->pgm.s.apInterPaePDs[0]
641	\|\| !pVM->pgm.s.apInterPaePDs[1]
642	\|\| !pVM->pgm.s.apInterPaePDs[2]
643	\|\| !pVM->pgm.s.apInterPaePDs[3]
644	\|\| !pVM->pgm.s.pInterPaePDPTR
645	#if 1
646	\|\| !pVM->pgm.s.pInterPaePDPTR64
647	#endif
648	\|\| !pVM->pgm.s.pInterPaePML4)
649	{
650	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
651	return VERR_NO_PAGE_MEMORY;
652	}
653
654	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
655	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
656	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
657	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
658	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
659	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
660
661	#if 1 /* let's see if this is the cause of the problems... */
662	/*
663	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
664	*/
665	ASMMemZeroPage(pVM->pgm.s.pInterPD);
666	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
667	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
668
669	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
670	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
671
672	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
673	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
674	{
675	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
676	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
677	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
678	}
679
680	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
681	{
682	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
683	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
684	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
685	}
686
687	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
688	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
689	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
690	\| HCPhysInterPaePDPTR64;
691	#else
692	/*
693	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
694	*/
695	ASMMemZero32(pVM->pgm.s.pInterPD, PAGE_SIZE);
696	ASMMemZero32(pVM->pgm.s.apInterPTs[0], PAGE_SIZE);
697	ASMMemZero32(pVM->pgm.s.apInterPTs[1], PAGE_SIZE);
698
699	ASMMemZero32(pVM->pgm.s.apInterPaePTs[0], PAGE_SIZE);
700	ASMMemZero32(pVM->pgm.s.apInterPaePTs[1], PAGE_SIZE);
701
702	ASMMemZero32(pVM->pgm.s.pInterPaePDPTR, PAGE_SIZE);
703	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
704	{
705	ASMMemZero32(pVM->pgm.s.apInterPaePDs[i], PAGE_SIZE);
706	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
707	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
708	}
709
710	ASMMemZero32(pVM->pgm.s.pInterPaePML4, PAGE_SIZE);
711	pVM->pgm.s.pInterPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A
712	\| pVM->pgm.s.HCPhysInterPaePDPTR;
713	#endif
714
715
716	/*
717	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
718	* We allocate pages for all three posibilities to in order to simplify mappings and
719	* avoid resource failure during mode switches. So, we need to cover all levels of the
720	* of the first 4GB down to PD level.
721	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
722	*/
723	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
724	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
725	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
726	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
727	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
728	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
729	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
730	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
731	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
732	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
733	if ( !pVM->pgm.s.pHC32BitPD
734	\|\| !pVM->pgm.s.apHCPaePDs[0]
735	\|\| !pVM->pgm.s.apHCPaePDs[1]
736	\|\| !pVM->pgm.s.apHCPaePDs[2]
737	\|\| !pVM->pgm.s.apHCPaePDs[3]
738	\|\| !pVM->pgm.s.pHCPaePDPTR
739	\|\| !pVM->pgm.s.pHCPaePML4)
740	{
741	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
742	return VERR_NO_PAGE_MEMORY;
743	}
744
745	/* get physical addresses. */
746	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
747	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
748	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
749	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
750	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
751	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
752	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
753	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
754
755	/*
756	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
757	*/
758	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
759
760	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
761	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
762	{
763	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
764	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
765	/* The flags will be corrected when entering and leaving long mode. */
766	}
767
768	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
769	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
770	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
771
772	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
773
774	/*
775	* Initialize paging workers and mode from current host mode
776	* and the guest running in real mode.
777	*/
778	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
779	switch (pVM->pgm.s.enmHostMode)
780	{
781	case SUPPAGINGMODE_32_BIT:
782	case SUPPAGINGMODE_32_BIT_GLOBAL:
783	case SUPPAGINGMODE_PAE:
784	case SUPPAGINGMODE_PAE_GLOBAL:
785	case SUPPAGINGMODE_PAE_NX:
786	case SUPPAGINGMODE_PAE_GLOBAL_NX:
787	break;
788
789	case SUPPAGINGMODE_AMD64:
790	case SUPPAGINGMODE_AMD64_GLOBAL:
791	case SUPPAGINGMODE_AMD64_NX:
792	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
793	if (ARCH_BITS != 64)
794	{
795	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
796	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
797	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
798	}
799	break;
800	default:
801	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
802	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
803	}
804	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
805	if (VBOX_SUCCESS(rc))
806	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
807	if (VBOX_SUCCESS(rc))
808	{
809	LogFlow(("pgmR3InitPaging: returns successfully\n"));
810	return VINF_SUCCESS;
811	}
812
813	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
814	return rc;
815	}
816
817
818	#ifdef VBOX_WITH_STATISTICS
819	/**
820	* Init statistics
821	*/
822	static void pgmR3InitStats(PVM pVM)
823	{
824	PPGM pPGM = &pVM->pgm.s;
825	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
826	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
827	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
828	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
829	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
830	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
831	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
832	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
833	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
834	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
835	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
836	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
837	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
838	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
839	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
840	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
841	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
842	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
843	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
844	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
845	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
846	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
847
848	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
849	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
850	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
851	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
852	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
853	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
854	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
855	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
856	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
857	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
858	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
859	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
860	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
861	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
862	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
863	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
864	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
865	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
866	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
867
868	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
869	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
870	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
871	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
872	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
873	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
874	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
875
876	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
877	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
878	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
879	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
880	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
881	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
882
883	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
884	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
885	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
886	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
887	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
888	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
889
890
891	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
892	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
893	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
894
895	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
896	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
897
898	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
899	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
900
901	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
902	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
903
904	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
905	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
906	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
907
908	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
909	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
910	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
911	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
912	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
913	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
914	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
915	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
916	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
917	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
918	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
919
920	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
921	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
922	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
923	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
924	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
925	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
926	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
927
928	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
929	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
930	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
931	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
932
933	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
934	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
935	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
936	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
937	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
938
939	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
940	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
941	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
942	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
943	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
944	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
945	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
946	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
947	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
948	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
949	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
950	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
951
952	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
953	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
954	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
955	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
956	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
957	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
958	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
959	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
960	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
961	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
962	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
963	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
964
965	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
966	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
967	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
968
969	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
970	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
971
972	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
973	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
974	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
975	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
976
977	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
978	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
979
980	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
981	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
982	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
983	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
984	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
985	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
986	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
987	#endif
988
989	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
990	{
991	/** @todo r=bird: We need a STAMR3RegisterF()! */
992	char szName[32];
993
994	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
995	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
996	AssertRC(rc);
997
998	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
999	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1000	AssertRC(rc);
1001
1002	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1003	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1004	AssertRC(rc);
1005	}
1006	}
1007	#endif /* VBOX_WITH_STATISTICS */
1008
1009	/**
1010	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1011	*
1012	* The dynamic mapping area will also be allocated and initialized at this
1013	* time. We could allocate it during PGMR3Init of course, but the mapping
1014	* wouldn't be allocated at that time preventing us from setting up the
1015	* page table entries with the dummy page.
1016	*
1017	* @returns VBox status code.
1018	* @param pVM VM handle.
1019	*/
1020	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1021	{
1022	/*
1023	* Reserve space for mapping the paging pages into guest context.
1024	*/
1025	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1026	AssertRCReturn(rc, rc);
1027	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1028
1029	/*
1030	* Reserve space for the dynamic mappings.
1031	*/
1032	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1033	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1034	if ( VBOX_SUCCESS(rc)
1035	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1036	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1037	if (VBOX_SUCCESS(rc))
1038	{
1039	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1040	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1041	}
1042	return rc;
1043	}
1044
1045
1046	/**
1047	* Ring-3 init finalizing.
1048	*
1049	* @returns VBox status code.
1050	* @param pVM The VM handle.
1051	*/
1052	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1053	{
1054	/*
1055	* Map the paging pages into the guest context.
1056	*/
1057	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1058	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1059
1060	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1061	AssertRCReturn(rc, rc);
1062	pVM->pgm.s.pGC32BitPD = GCPtr;
1063	GCPtr += PAGE_SIZE;
1064	GCPtr += PAGE_SIZE; /* reserved page */
1065
1066	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1067	{
1068	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1069	AssertRCReturn(rc, rc);
1070	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1071	GCPtr += PAGE_SIZE;
1072	}
1073	/* A bit of paranoia is justified. */
1074	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1075	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1076	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1077	GCPtr += PAGE_SIZE; /* reserved page */
1078
1079	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1080	AssertRCReturn(rc, rc);
1081	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1082	GCPtr += PAGE_SIZE;
1083	GCPtr += PAGE_SIZE; /* reserved page */
1084
1085	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1086	AssertRCReturn(rc, rc);
1087	pVM->pgm.s.pGCPaePML4 = GCPtr;
1088	GCPtr += PAGE_SIZE;
1089	GCPtr += PAGE_SIZE; /* reserved page */
1090
1091
1092	/*
1093	* Reserve space for the dynamic mappings.
1094	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1095	*/
1096	/* get the pointer to the page table entries. */
1097	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1098	AssertRelease(pMapping);
1099	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1100	const unsigned iPT = off >> X86_PD_SHIFT;
1101	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1102	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTHC->a[0]);
1103	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsHC->a[0]);
1104
1105	/* init cache */
1106	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1107	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1108	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1109
1110	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1111	{
1112	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1113	AssertRCReturn(rc, rc);
1114	}
1115
1116	return rc;
1117	}
1118
1119
1120	/**
1121	* Applies relocations to data and code managed by this
1122	* component. This function will be called at init and
1123	* whenever the VMM need to relocate it self inside the GC.
1124	*
1125	* @param pVM The VM.
1126	* @param offDelta Relocation delta relative to old location.
1127	*/
1128	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1129	{
1130	LogFlow(("PGMR3Relocate\n"));
1131
1132	/*
1133	* Paging stuff.
1134	*/
1135	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1136	/** @todo move this into shadow and guest specific relocation functions. */
1137	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1138	pVM->pgm.s.pGC32BitPD += offDelta;
1139	pVM->pgm.s.pGuestPDGC += offDelta;
1140	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1141	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1142	pVM->pgm.s.pGCPaePDPTR += offDelta;
1143	pVM->pgm.s.pGCPaePML4 += offDelta;
1144
1145	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1146	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1147
1148	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1149	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1150	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1151
1152	/*
1153	* Trees.
1154	*/
1155	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1156
1157	/*
1158	* Ram ranges.
1159	*/
1160	if (pVM->pgm.s.pRamRangesHC)
1161	{
1162	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1163	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1164	{
1165	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1166	if (pCur->pavHCChunkGC)
1167	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1168	}
1169	}
1170
1171	/*
1172	* Update the two page directories with all page table mappings.
1173	* (One or more of them have changed, that's why we're here.)
1174	*/
1175	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsHC);
1176	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur->pNextHC; pCur = pCur->pNextHC)
1177	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1178
1179	/* Relocate GC addresses of Page Tables. */
1180	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
1181	{
1182	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1183	{
1184	pCur->aPTs[i].pPTGC = MMHyperHC2GC(pVM, pCur->aPTs[i].pPTHC);
1185	pCur->aPTs[i].paPaePTsGC = MMHyperHC2GC(pVM, pCur->aPTs[i].paPaePTsHC);
1186	}
1187	}
1188
1189	/*
1190	* Dynamic page mapping area.
1191	*/
1192	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1193	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1194	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1195
1196	/*
1197	* Physical and virtual handlers.
1198	*/
1199	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1200	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1201
1202	/*
1203	* The page pool.
1204	*/
1205	pgmR3PoolRelocate(pVM);
1206	}
1207
1208
1209	/**
1210	* Callback function for relocating a physical access handler.
1211	*
1212	* @returns 0 (continue enum)
1213	* @param pNode Pointer to a PGMPHYSHANDLER node.
1214	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1215	* not certain the delta will fit in a void pointer for all possible configs.
1216	*/
1217	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1218	{
1219	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1220	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1221	Assert(pHandler->pfnHandlerGC);
1222	pHandler->pfnHandlerGC += offDelta;
1223	if (pHandler->pvUserGC)
1224	pHandler->pvUserGC += offDelta;
1225	return 0;
1226	}
1227
1228	/**
1229	* Callback function for relocating a virtual access handler.
1230	*
1231	* @returns 0 (continue enum)
1232	* @param pNode Pointer to a PGMVIRTHANDLER node.
1233	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1234	* not certain the delta will fit in a void pointer for all possible configs.
1235	*/
1236	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1237	{
1238	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1239	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1240	Assert(pHandler->pfnHandlerGC);
1241	pHandler->pfnHandlerGC += offDelta;
1242	return 0;
1243	}
1244
1245
1246	/**
1247	* The VM is being reset.
1248	*
1249	* For the PGM component this means that any PD write monitors
1250	* needs to be removed.
1251	*
1252	* @param pVM VM handle.
1253	*/
1254	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1255	{
1256	LogFlow(("PGMR3Reset:\n"));
1257	VM_ASSERT_EMT(pVM);
1258
1259	/*
1260	* Unfix any fixed mappings and disable CR3 monitoring.
1261	*/
1262	pVM->pgm.s.fMappingsFixed = false;
1263	pVM->pgm.s.GCPtrMappingFixed = 0;
1264	pVM->pgm.s.cbMappingFixed = 0;
1265
1266	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1267	AssertRC(rc);
1268	#ifdef DEBUG
1269	PGMR3DumpMappings(pVM);
1270	#endif
1271
1272	/*
1273	* Reset the shadow page pool.
1274	*/
1275	pgmR3PoolReset(pVM);
1276
1277	/*
1278	* Re-init other members.
1279	*/
1280	pVM->pgm.s.fA20Enabled = true;
1281
1282	/*
1283	* Clear the FFs PGM owns.
1284	*/
1285	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1286	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1287
1288	/*
1289	* Zero memory.
1290	*/
1291	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1292	{
1293	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1294	while (iPage-- > 0)
1295	{
1296	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1297	{
1298	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1299	continue;
1300	}
1301	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1302	{
1303	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1304	if (pRam->pavHCChunkHC[iChunk])
1305	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1306	}
1307	else
1308	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1309	}
1310	}
1311
1312	/*
1313	* Switch mode back to real mode.
1314	*/
1315	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1316	AssertReleaseRC(rc);
1317	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1318	}
1319
1320
1321	/**
1322	* Terminates the PGM.
1323	*
1324	* @returns VBox status code.
1325	* @param pVM Pointer to VM structure.
1326	*/
1327	PGMR3DECL(int) PGMR3Term(PVM pVM)
1328	{
1329	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1330	}
1331
1332
1333	/**
1334	* Execute state save operation.
1335	*
1336	* @returns VBox status code.
1337	* @param pVM VM Handle.
1338	* @param pSSM SSM operation handle.
1339	*/
1340	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1341	{
1342	PPGM pPGM = &pVM->pgm.s;
1343
1344	/*
1345	* Save basic data (required / unaffected by relocation).
1346	*/
1347	#if 1
1348	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1349	#else
1350	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1351	#endif
1352	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1353	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1354	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1355	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1356	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1357	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1358	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1359	SSMR3PutU32(pSSM, ~0); /* Separator. */
1360
1361	/*
1362	* The guest mappings.
1363	*/
1364	uint32_t i = 0;
1365	for (PPGMMAPPING pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC, i++)
1366	{
1367	SSMR3PutU32(pSSM, i);
1368	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1369	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1370	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1371	/* flags are done by the mapping owners! */
1372	}
1373	SSMR3PutU32(pSSM, ~0); /* terminator. */
1374
1375	/*
1376	* Ram range flags and bits.
1377	*/
1378	i = 0;
1379	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1380	{
1381	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1382
1383	SSMR3PutU32(pSSM, i);
1384	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1385	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1386	SSMR3PutGCPhys(pSSM, pRam->cb);
1387	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1388
1389	/* Flags. */
1390	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1391	for (unsigned iPage = 0; iPage < cPages; iPage++)
1392	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1393
1394	/* any memory associated with the range. */
1395	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1396	{
1397	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1398	{
1399	if (pRam->pavHCChunkHC[iChunk])
1400	{
1401	SSMR3PutU8(pSSM, 1); /* chunk present */
1402	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1403	}
1404	else
1405	SSMR3PutU8(pSSM, 0); /* no chunk present */
1406	}
1407	}
1408	else if (pRam->pvHC)
1409	{
1410	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1411	if (VBOX_FAILURE(rc))
1412	{
1413	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1414	return rc;
1415	}
1416	}
1417	}
1418	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1419	}
1420
1421
1422	/**
1423	* Execute state load operation.
1424	*
1425	* @returns VBox status code.
1426	* @param pVM VM Handle.
1427	* @param pSSM SSM operation handle.
1428	* @param u32Version Data layout version.
1429	*/
1430	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1431	{
1432	/*
1433	* Validate version.
1434	*/
1435	if (u32Version != PGM_SAVED_STATE_VERSION)
1436	{
1437	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1438	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1439	}
1440
1441	/*
1442	* Call the reset function to make sure all the memory is cleared.
1443	*/
1444	PGMR3Reset(pVM);
1445
1446	/*
1447	* Load basic data (required / unaffected by relocation).
1448	*/
1449	PPGM pPGM = &pVM->pgm.s;
1450	#if 1
1451	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1452	#else
1453	uint32_t u;
1454	SSMR3GetU32(pSSM, &u);
1455	pPGM->fMappingsFixed = u;
1456	#endif
1457	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1458	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1459
1460	RTUINT cbRamSize;
1461	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1462	if (VBOX_FAILURE(rc))
1463	return rc;
1464	if (cbRamSize != pPGM->cbRamSize)
1465	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1466	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1467	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1468	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1469	RTUINT uGuestMode;
1470	SSMR3GetUInt(pSSM, &uGuestMode);
1471	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1472
1473	/* check separator. */
1474	uint32_t u32Sep;
1475	SSMR3GetU32(pSSM, &u32Sep);
1476	if (VBOX_FAILURE(rc))
1477	return rc;
1478	if (u32Sep != (uint32_t)~0)
1479	{
1480	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1481	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1482	}
1483
1484	/*
1485	* The guest mappings.
1486	*/
1487	uint32_t i = 0;
1488	for (;; i++)
1489	{
1490	/* Check the seqence number / separator. */
1491	rc = SSMR3GetU32(pSSM, &u32Sep);
1492	if (VBOX_FAILURE(rc))
1493	return rc;
1494	if (u32Sep == ~0U)
1495	break;
1496	if (u32Sep != i)
1497	{
1498	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1499	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1500	}
1501
1502	/* get the mapping details. */
1503	char szDesc[256];
1504	szDesc[0] = '\0';
1505	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1506	if (VBOX_FAILURE(rc))
1507	return rc;
1508	RTGCPTR GCPtr;
1509	SSMR3GetGCPtr(pSSM, &GCPtr);
1510	RTGCUINTPTR cPTs;
1511	rc = SSMR3GetU32(pSSM, &cPTs);
1512	if (VBOX_FAILURE(rc))
1513	return rc;
1514
1515	/* find matching range. */
1516	PPGMMAPPING pMapping;
1517	for (pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC)
1518	if ( pMapping->cPTs == cPTs
1519	&& !strcmp(pMapping->pszDesc, szDesc))
1520	break;
1521	if (!pMapping)
1522	{
1523	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1524	cPTs, szDesc, GCPtr));
1525	AssertFailed();
1526	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1527	}
1528
1529	/* relocate it. */
1530	if (pMapping->GCPtr != GCPtr)
1531	{
1532	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1533	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1534	}
1535	else
1536	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1537	}
1538
1539	/*
1540	* Ram range flags and bits.
1541	*/
1542	i = 0;
1543	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1544	{
1545	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1546	/* Check the seqence number / separator. */
1547	rc = SSMR3GetU32(pSSM, &u32Sep);
1548	if (VBOX_FAILURE(rc))
1549	return rc;
1550	if (u32Sep == ~0U)
1551	break;
1552	if (u32Sep != i)
1553	{
1554	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1555	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1556	}
1557
1558	/* Get the range details. */
1559	RTGCPHYS GCPhys;
1560	SSMR3GetGCPhys(pSSM, &GCPhys);
1561	RTGCPHYS GCPhysLast;
1562	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1563	RTGCPHYS cb;
1564	SSMR3GetGCPhys(pSSM, &cb);
1565	uint8_t fHaveBits;
1566	rc = SSMR3GetU8(pSSM, &fHaveBits);
1567	if (VBOX_FAILURE(rc))
1568	return rc;
1569	if (fHaveBits & ~1)
1570	{
1571	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1572	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1573	}
1574
1575	/* Match it up with the current range. */
1576	if ( GCPhys != pRam->GCPhys
1577	\|\| GCPhysLast != pRam->GCPhysLast
1578	\|\| cb != pRam->cb
1579	\|\| fHaveBits != !!pRam->pvHC)
1580	{
1581	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1582	"State : %VGp-%VGp %VGp bytes %s\n",
1583	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1584	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1585	AssertFailed();
1586	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1587	}
1588
1589	/* Flags. */
1590	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1591	for (unsigned iPage = 0; iPage < cPages; iPage++)
1592	{
1593	uint16_t u16 = 0;
1594	SSMR3GetU16(pSSM, &u16);
1595	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1596	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1597	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1598	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1599	}
1600
1601	/* any memory associated with the range. */
1602	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1603	{
1604	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1605	{
1606	uint8_t fValidChunk;
1607
1608	rc = SSMR3GetU8(pSSM, &fValidChunk);
1609	if (VBOX_FAILURE(rc))
1610	return rc;
1611	if (fValidChunk > 1)
1612	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1613
1614	if (fValidChunk)
1615	{
1616	if (!pRam->pavHCChunkHC[iChunk])
1617	{
1618	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1619	if (VBOX_FAILURE(rc))
1620	return rc;
1621	}
1622	Assert(pRam->pavHCChunkHC[iChunk]);
1623
1624	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1625	}
1626	/* else nothing to do */
1627	}
1628	}
1629	else if (pRam->pvHC)
1630	{
1631	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1632	if (VBOX_FAILURE(rc))
1633	{
1634	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1635	return rc;
1636	}
1637	}
1638	}
1639
1640	/*
1641	* We require a full resync now.
1642	*/
1643	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1644	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1645	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1646	pPGM->fPhysCacheFlushPending = true;
1647	pgmR3HandlerPhysicalUpdateAll(pVM);
1648
1649	/*
1650	* Change the paging mode.
1651	*/
1652	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1653	}
1654
1655
1656	/**
1657	* Show paging mode.
1658	*
1659	* @param pVM VM Handle.
1660	* @param pHlp The info helpers.
1661	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1662	*/
1663	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1664	{
1665	/* digest argument. */
1666	bool fGuest, fShadow, fHost;
1667	if (pszArgs)
1668	pszArgs = RTStrStripL(pszArgs);
1669	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1670	fShadow = fHost = fGuest = true;
1671	else
1672	{
1673	fShadow = fHost = fGuest = false;
1674	if (strstr(pszArgs, "guest"))
1675	fGuest = true;
1676	if (strstr(pszArgs, "shadow"))
1677	fShadow = true;
1678	if (strstr(pszArgs, "host"))
1679	fHost = true;
1680	}
1681
1682	/* print info. */
1683	if (fGuest)
1684	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1685	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1686	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1687	if (fShadow)
1688	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1689	if (fHost)
1690	{
1691	const char *psz;
1692	switch (pVM->pgm.s.enmHostMode)
1693	{
1694	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1695	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1696	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1697	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1698	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1699	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1700	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1701	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1702	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1703	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1704	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1705	default: psz = "unknown"; break;
1706	}
1707	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1708	}
1709	}
1710
1711
1712	/**
1713	* Dump registered MMIO ranges to the log.
1714	*
1715	* @param pVM VM Handle.
1716	* @param pHlp The info helpers.
1717	* @param pszArgs Arguments, ignored.
1718	*/
1719	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1720	{
1721	NOREF(pszArgs);
1722	pHlp->pfnPrintf(pHlp,
1723	"RAM ranges (pVM=%p)\n"
1724	"%.s %.s\n",
1725	pVM,
1726	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1727	sizeof(RTHCPTR) * 2, "pvHC ");
1728
1729	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1730	pHlp->pfnPrintf(pHlp,
1731	"%VGp-%VGp %VHv\n",
1732	pCur->GCPhys,
1733	pCur->GCPhysLast,
1734	pCur->pvHC);
1735	}
1736
1737	/**
1738	* Dump the page directory to the log.
1739	*
1740	* @param pVM VM Handle.
1741	* @param pHlp The info helpers.
1742	* @param pszArgs Arguments, ignored.
1743	*/
1744	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1745	{
1746	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1747	/* Big pages supported? */
1748	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1749	/* Global pages supported? */
1750	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1751
1752	NOREF(pszArgs);
1753
1754	/*
1755	* Get page directory addresses.
1756	*/
1757	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1758	Assert(pPDSrc);
1759	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
1760
1761	/*
1762	* Iterate the page directory.
1763	*/
1764	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1765	{
1766	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1767	if (PdeSrc.n.u1Present)
1768	{
1769	if (PdeSrc.b.u1Size && fPSE)
1770	{
1771	pHlp->pfnPrintf(pHlp,
1772	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1773	iPD,
1774	PdeSrc.u & X86_PDE_PG_MASK,
1775	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1776	}
1777	else
1778	{
1779	pHlp->pfnPrintf(pHlp,
1780	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1781	iPD,
1782	PdeSrc.u & X86_PDE4M_PG_MASK,
1783	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1784	}
1785	}
1786	}
1787	}
1788
1789
1790	/**
1791	* Serivce a VMMCALLHOST_PGM_LOCK call.
1792	*
1793	* @returns VBox status code.
1794	* @param pVM The VM handle.
1795	*/
1796	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1797	{
1798	return pgmLock(pVM);
1799	}
1800
1801
1802	/**
1803	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1804	*
1805	* @returns PGM_TYPE_*.
1806	* @param pgmMode The mode value to convert.
1807	*/
1808	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1809	{
1810	switch (pgmMode)
1811	{
1812	case PGMMODE_REAL: return PGM_TYPE_REAL;
1813	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1814	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1815	case PGMMODE_PAE:
1816	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1817	case PGMMODE_AMD64:
1818	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1819	default:
1820	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1821	}
1822	}
1823
1824
1825	/**
1826	* Gets the index into the paging mode data array of a SHW+GST mode.
1827	*
1828	* @returns PGM::paPagingData index.
1829	* @param uShwType The shadow paging mode type.
1830	* @param uGstType The guest paging mode type.
1831	*/
1832	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1833	{
1834	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1835	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1836	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1837	+ (uGstType - PGM_TYPE_REAL);
1838	}
1839
1840
1841	/**
1842	* Gets the index into the paging mode data array of a SHW+GST mode.
1843	*
1844	* @returns PGM::paPagingData index.
1845	* @param enmShw The shadow paging mode.
1846	* @param enmGst The guest paging mode.
1847	*/
1848	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1849	{
1850	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1851	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1852	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1853	}
1854
1855
1856	/**
1857	* Calculates the max data index.
1858	* @returns The number of entries in the pagaing data array.
1859	*/
1860	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1861	{
1862	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1863	}
1864
1865
1866	/**
1867	* Initializes the paging mode data kept in PGM::paModeData.
1868	*
1869	* @param pVM The VM handle.
1870	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1871	* This is used early in the init process to avoid trouble with PDM
1872	* not being initialized yet.
1873	*/
1874	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1875	{
1876	PPGMMODEDATA pModeData;
1877	int rc;
1878
1879	/*
1880	* Allocate the array on the first call.
1881	*/
1882	if (!pVM->pgm.s.paModeData)
1883	{
1884	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1885	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1886	}
1887
1888	/*
1889	* Initialize the array entries.
1890	*/
1891	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1892	pModeData->uShwType = PGM_TYPE_32BIT;
1893	pModeData->uGstType = PGM_TYPE_REAL;
1894	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1895	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1896	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1897
1898	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1899	pModeData->uShwType = PGM_TYPE_32BIT;
1900	pModeData->uGstType = PGM_TYPE_PROT;
1901	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1902	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1903	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1904
1905	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1906	pModeData->uShwType = PGM_TYPE_32BIT;
1907	pModeData->uGstType = PGM_TYPE_32BIT;
1908	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1909	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1910	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1911
1912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1913	pModeData->uShwType = PGM_TYPE_PAE;
1914	pModeData->uGstType = PGM_TYPE_REAL;
1915	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1916	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1917	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1918
1919	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1920	pModeData->uShwType = PGM_TYPE_PAE;
1921	pModeData->uGstType = PGM_TYPE_PROT;
1922	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1923	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1924	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1925
1926	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1927	pModeData->uShwType = PGM_TYPE_PAE;
1928	pModeData->uGstType = PGM_TYPE_32BIT;
1929	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1930	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1931	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1932
1933	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1934	pModeData->uShwType = PGM_TYPE_PAE;
1935	pModeData->uGstType = PGM_TYPE_PAE;
1936	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1937	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1938	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1939
1940	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1941	pModeData->uShwType = PGM_TYPE_AMD64;
1942	pModeData->uGstType = PGM_TYPE_REAL;
1943	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1944	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1945	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1946
1947	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1948	pModeData->uShwType = PGM_TYPE_AMD64;
1949	pModeData->uGstType = PGM_TYPE_PROT;
1950	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1951	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1952	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1953
1954	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1955	pModeData->uShwType = PGM_TYPE_AMD64;
1956	pModeData->uGstType = PGM_TYPE_AMD64;
1957	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1958	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1959	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1960
1961	return VINF_SUCCESS;
1962	}
1963
1964
1965	/**
1966	* Swtich to different (or relocated in the relocate case) mode data.
1967	*
1968	* @param pVM The VM handle.
1969	* @param enmShw The the shadow paging mode.
1970	* @param enmGst The the guest paging mode.
1971	*/
1972	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1973	{
1974	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1975
1976	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1977	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1978
1979	/* shadow */
1980	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
1981	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
1982	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
1983	Assert(pVM->pgm.s.pfnR3ShwGetPage);
1984	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
1985	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
1986	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
1987	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
1988
1989	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
1990	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
1991	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
1992	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
1993	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
1994
1995	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
1996	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
1997	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
1998	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
1999	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2000
2001
2002	/* guest */
2003	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2004	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2005	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2006	Assert(pVM->pgm.s.pfnR3GstGetPage);
2007	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2008	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2009	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2010	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2011	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2012	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2013	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2014	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2015
2016	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2017	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2018	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2019	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2020	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2021	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2022	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2023	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2024
2025	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2026	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2027	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2028	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2029	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2030	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2031	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2032	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2033
2034
2035	/* both */
2036	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2037	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2038	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2039	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2040	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2041	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2042	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2043	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2044	#ifdef VBOX_STRICT
2045	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2046	#endif
2047
2048	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2049	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2050	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2051	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2052	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2053	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2054	#ifdef VBOX_STRICT
2055	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2056	#endif
2057
2058	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2059	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2060	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2061	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2062	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2063	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2064	#ifdef VBOX_STRICT
2065	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2066	#endif
2067	}
2068
2069
2070	#ifdef DEBUG_bird
2071	#include <stdlib.h> /* getenv() remove me! */
2072	#endif
2073
2074	/**
2075	* Calculates the shadow paging mode.
2076	*
2077	* @returns The shadow paging mode.
2078	* @param enmGuestMode The guest mode.
2079	* @param enmHostMode The host mode.
2080	* @param enmShadowMode The current shadow mode.
2081	* @param penmSwitcher Where to store the switcher to use.
2082	* VMMSWITCHER_INVALID means no change.
2083	*/
2084	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2085	{
2086	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2087	switch (enmGuestMode)
2088	{
2089	/*
2090	* When switching to real or protected mode we don't change
2091	* anything since it's likely that we'll switch back pretty soon.
2092	*
2093	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2094	* and is supposed to determin which shadow paging and switcher to
2095	* use during init.
2096	*/
2097	case PGMMODE_REAL:
2098	case PGMMODE_PROTECTED:
2099	if (enmShadowMode != PGMMODE_INVALID)
2100	break; /* (no change) */
2101	switch (enmHostMode)
2102	{
2103	case SUPPAGINGMODE_32_BIT:
2104	case SUPPAGINGMODE_32_BIT_GLOBAL:
2105	enmShadowMode = PGMMODE_32_BIT;
2106	enmSwitcher = VMMSWITCHER_32_TO_32;
2107	break;
2108
2109	case SUPPAGINGMODE_PAE:
2110	case SUPPAGINGMODE_PAE_NX:
2111	case SUPPAGINGMODE_PAE_GLOBAL:
2112	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2113	enmShadowMode = PGMMODE_PAE;
2114	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2115	#ifdef DEBUG_bird
2116	if (getenv("VBOX_32BIT"))
2117	{
2118	enmShadowMode = PGMMODE_32_BIT;
2119	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2120	}
2121	#endif
2122	break;
2123
2124	case SUPPAGINGMODE_AMD64:
2125	case SUPPAGINGMODE_AMD64_GLOBAL:
2126	case SUPPAGINGMODE_AMD64_NX:
2127	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2128	enmShadowMode = PGMMODE_PAE;
2129	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2130	break;
2131
2132	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2133	}
2134	break;
2135
2136	case PGMMODE_32_BIT:
2137	switch (enmHostMode)
2138	{
2139	case SUPPAGINGMODE_32_BIT:
2140	case SUPPAGINGMODE_32_BIT_GLOBAL:
2141	enmShadowMode = PGMMODE_32_BIT;
2142	enmSwitcher = VMMSWITCHER_32_TO_32;
2143	break;
2144
2145	case SUPPAGINGMODE_PAE:
2146	case SUPPAGINGMODE_PAE_NX:
2147	case SUPPAGINGMODE_PAE_GLOBAL:
2148	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2149	enmShadowMode = PGMMODE_PAE;
2150	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2151	#ifdef DEBUG_bird
2152	if (getenv("VBOX_32BIT"))
2153	{
2154	enmShadowMode = PGMMODE_32_BIT;
2155	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2156	}
2157	#endif
2158	break;
2159
2160	case SUPPAGINGMODE_AMD64:
2161	case SUPPAGINGMODE_AMD64_GLOBAL:
2162	case SUPPAGINGMODE_AMD64_NX:
2163	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2164	enmShadowMode = PGMMODE_PAE;
2165	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2166	break;
2167
2168	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2169	}
2170	break;
2171
2172	case PGMMODE_PAE:
2173	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2174	switch (enmHostMode)
2175	{
2176	case SUPPAGINGMODE_32_BIT:
2177	case SUPPAGINGMODE_32_BIT_GLOBAL:
2178	enmShadowMode = PGMMODE_PAE;
2179	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2180	break;
2181
2182	case SUPPAGINGMODE_PAE:
2183	case SUPPAGINGMODE_PAE_NX:
2184	case SUPPAGINGMODE_PAE_GLOBAL:
2185	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2186	enmShadowMode = PGMMODE_PAE;
2187	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2188	break;
2189
2190	case SUPPAGINGMODE_AMD64:
2191	case SUPPAGINGMODE_AMD64_GLOBAL:
2192	case SUPPAGINGMODE_AMD64_NX:
2193	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2194	enmShadowMode = PGMMODE_PAE;
2195	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2196	break;
2197
2198	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2199	}
2200	break;
2201
2202	case PGMMODE_AMD64:
2203	case PGMMODE_AMD64_NX:
2204	switch (enmHostMode)
2205	{
2206	case SUPPAGINGMODE_32_BIT:
2207	case SUPPAGINGMODE_32_BIT_GLOBAL:
2208	enmShadowMode = PGMMODE_PAE;
2209	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2210	break;
2211
2212	case SUPPAGINGMODE_PAE:
2213	case SUPPAGINGMODE_PAE_NX:
2214	case SUPPAGINGMODE_PAE_GLOBAL:
2215	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2216	enmShadowMode = PGMMODE_PAE;
2217	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2218	break;
2219
2220	case SUPPAGINGMODE_AMD64:
2221	case SUPPAGINGMODE_AMD64_GLOBAL:
2222	case SUPPAGINGMODE_AMD64_NX:
2223	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2224	enmShadowMode = PGMMODE_PAE;
2225	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2226	break;
2227
2228	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2229	}
2230	break;
2231
2232
2233	default:
2234	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2235	return PGMMODE_INVALID;
2236	}
2237
2238	*penmSwitcher = enmSwitcher;
2239	return enmShadowMode;
2240	}
2241
2242
2243	/**
2244	* Performs the actual mode change.
2245	* This is called by PGMChangeMode and pgmR3InitPaging().
2246	*
2247	* @returns VBox status code.
2248	* @param pVM VM handle.
2249	* @param enmGuestMode The new guest mode. This is assumed to be different from
2250	* the current mode.
2251	*/
2252	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2253	{
2254	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2255	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2256
2257	/*
2258	* Calc the shadow mode and switcher.
2259	*/
2260	VMMSWITCHER enmSwitcher;
2261	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2262	if (enmSwitcher != VMMSWITCHER_INVALID)
2263	{
2264	/*
2265	* Select new switcher.
2266	*/
2267	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2268	if (VBOX_FAILURE(rc))
2269	{
2270	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2271	return rc;
2272	}
2273	}
2274
2275	/*
2276	* Exit old mode(s).
2277	*/
2278	/* shadow */
2279	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2280	{
2281	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2282	if (PGM_SHW_PFN(Exit, pVM))
2283	{
2284	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2285	if (VBOX_FAILURE(rc))
2286	{
2287	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2288	return rc;
2289	}
2290	}
2291
2292	}
2293
2294	/* guest */
2295	if (PGM_GST_PFN(Exit, pVM))
2296	{
2297	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2298	if (VBOX_FAILURE(rc))
2299	{
2300	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2301	return rc;
2302	}
2303	}
2304
2305	/*
2306	* Load new paging mode data.
2307	*/
2308	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2309
2310	/*
2311	* Enter new shadow mode (if changed).
2312	*/
2313	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2314	{
2315	int rc;
2316	pVM->pgm.s.enmShadowMode = enmShadowMode;
2317	switch (enmShadowMode)
2318	{
2319	case PGMMODE_32_BIT:
2320	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2321	break;
2322	case PGMMODE_PAE:
2323	case PGMMODE_PAE_NX:
2324	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2325	break;
2326	case PGMMODE_AMD64:
2327	case PGMMODE_AMD64_NX:
2328	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2329	break;
2330	case PGMMODE_REAL:
2331	case PGMMODE_PROTECTED:
2332	default:
2333	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2334	return VERR_INTERNAL_ERROR;
2335	}
2336	if (VBOX_FAILURE(rc))
2337	{
2338	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2339	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2340	return rc;
2341	}
2342	}
2343
2344	/*
2345	* Enter the new guest and shadow+guest modes.
2346	*/
2347	int rc = -1;
2348	int rc2 = -1;
2349	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2350	pVM->pgm.s.enmGuestMode = enmGuestMode;
2351	switch (enmGuestMode)
2352	{
2353	case PGMMODE_REAL:
2354	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2355	switch (pVM->pgm.s.enmShadowMode)
2356	{
2357	case PGMMODE_32_BIT:
2358	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2359	break;
2360	case PGMMODE_PAE:
2361	case PGMMODE_PAE_NX:
2362	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2363	break;
2364	case PGMMODE_AMD64:
2365	case PGMMODE_AMD64_NX:
2366	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2367	break;
2368	default: AssertFailed(); break;
2369	}
2370	break;
2371
2372	case PGMMODE_PROTECTED:
2373	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2374	switch (pVM->pgm.s.enmShadowMode)
2375	{
2376	case PGMMODE_32_BIT:
2377	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2378	break;
2379	case PGMMODE_PAE:
2380	case PGMMODE_PAE_NX:
2381	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2382	break;
2383	case PGMMODE_AMD64:
2384	case PGMMODE_AMD64_NX:
2385	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2386	break;
2387	default: AssertFailed(); break;
2388	}
2389	break;
2390
2391	case PGMMODE_32_BIT:
2392	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2393	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2394	switch (pVM->pgm.s.enmShadowMode)
2395	{
2396	case PGMMODE_32_BIT:
2397	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2398	break;
2399	case PGMMODE_PAE:
2400	case PGMMODE_PAE_NX:
2401	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2402	break;
2403	case PGMMODE_AMD64:
2404	case PGMMODE_AMD64_NX:
2405	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2406	default: AssertFailed(); break;
2407	}
2408	break;
2409
2410	//case PGMMODE_PAE_NX:
2411	case PGMMODE_PAE:
2412	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2413	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2414	switch (pVM->pgm.s.enmShadowMode)
2415	{
2416	case PGMMODE_PAE:
2417	case PGMMODE_PAE_NX:
2418	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2419	break;
2420	case PGMMODE_32_BIT:
2421	case PGMMODE_AMD64:
2422	case PGMMODE_AMD64_NX:
2423	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2424	default: AssertFailed(); break;
2425	}
2426	break;
2427
2428	//case PGMMODE_AMD64_NX:
2429	case PGMMODE_AMD64:
2430	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2431	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2432	switch (pVM->pgm.s.enmShadowMode)
2433	{
2434	case PGMMODE_AMD64:
2435	case PGMMODE_AMD64_NX:
2436	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2437	break;
2438	case PGMMODE_32_BIT:
2439	case PGMMODE_PAE:
2440	case PGMMODE_PAE_NX:
2441	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2442	default: AssertFailed(); break;
2443	}
2444	break;
2445
2446	default:
2447	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2448	rc = VERR_NOT_IMPLEMENTED;
2449	break;
2450	}
2451
2452	/* status codes. */
2453	AssertRC(rc);
2454	AssertRC(rc2);
2455	if (VBOX_SUCCESS(rc))
2456	{
2457	rc = rc2;
2458	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2459	rc = VINF_SUCCESS;
2460	}
2461
2462	/*
2463	* Notify SELM so it can update the TSSes with correct CR3s.
2464	*/
2465	SELMR3PagingModeChanged(pVM);
2466
2467	/* Notify HWACCM as well. */
2468	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2469	return rc;
2470	}
2471
2472
2473	/**
2474	* Dumps a PAE shadow page table.
2475	*
2476	* @returns VBox status code (VINF_SUCCESS).
2477	* @param pVM The VM handle.
2478	* @param pPT Pointer to the page table.
2479	* @param u64Address The virtual address of the page table starts.
2480	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2481	* @param cMaxDepth The maxium depth.
2482	* @param pHlp Pointer to the output functions.
2483	*/
2484	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2485	{
2486	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2487	{
2488	X86PTEPAE Pte = pPT->a[i];
2489	if (Pte.n.u1Present)
2490	{
2491	pHlp->pfnPrintf(pHlp,
2492	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2493	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2494	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2495	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2496	Pte.n.u1Write ? 'W' : 'R',
2497	Pte.n.u1User ? 'U' : 'S',
2498	Pte.n.u1Accessed ? 'A' : '-',
2499	Pte.n.u1Dirty ? 'D' : '-',
2500	Pte.n.u1Global ? 'G' : '-',
2501	Pte.n.u1WriteThru ? "WT" : "--",
2502	Pte.n.u1CacheDisable? "CD" : "--",
2503	Pte.n.u1PAT ? "AT" : "--",
2504	Pte.n.u1NoExecute ? "NX" : "--",
2505	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2506	Pte.u & BIT(10) ? '1' : '0',
2507	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2508	Pte.u & X86_PTE_PAE_PG_MASK);
2509	}
2510	}
2511	return VINF_SUCCESS;
2512	}
2513
2514
2515	/**
2516	* Dumps a PAE shadow page directory table.
2517	*
2518	* @returns VBox status code (VINF_SUCCESS).
2519	* @param pVM The VM handle.
2520	* @param HCPhys The physical address of the page directory table.
2521	* @param u64Address The virtual address of the page table starts.
2522	* @param cr4 The CR4, PSE is currently used.
2523	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2524	* @param cMaxDepth The maxium depth.
2525	* @param pHlp Pointer to the output functions.
2526	*/
2527	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2528	{
2529	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2530	if (!pPD)
2531	{
2532	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2533	fLongMode ? 16 : 8, u64Address, HCPhys);
2534	return VERR_INVALID_PARAMETER;
2535	}
2536	int rc = VINF_SUCCESS;
2537	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2538	{
2539	X86PDEPAE Pde = pPD->a[i];
2540	if (Pde.n.u1Present)
2541	{
2542	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2543	pHlp->pfnPrintf(pHlp,
2544	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2545	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2546	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2547	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2548	Pde.b.u1Write ? 'W' : 'R',
2549	Pde.b.u1User ? 'U' : 'S',
2550	Pde.b.u1Accessed ? 'A' : '-',
2551	Pde.b.u1Dirty ? 'D' : '-',
2552	Pde.b.u1Global ? 'G' : '-',
2553	Pde.b.u1WriteThru ? "WT" : "--",
2554	Pde.b.u1CacheDisable? "CD" : "--",
2555	Pde.b.u1PAT ? "AT" : "--",
2556	Pde.b.u1NoExecute ? "NX" : "--",
2557	Pde.u & BIT64(9) ? '1' : '0',
2558	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2559	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2560	Pde.u & X86_PDE_PAE_PG_MASK);
2561	else
2562	{
2563	pHlp->pfnPrintf(pHlp,
2564	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2565	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2566	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2567	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2568	Pde.n.u1Write ? 'W' : 'R',
2569	Pde.n.u1User ? 'U' : 'S',
2570	Pde.n.u1Accessed ? 'A' : '-',
2571	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2572	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2573	Pde.n.u1WriteThru ? "WT" : "--",
2574	Pde.n.u1CacheDisable? "CD" : "--",
2575	Pde.n.u1NoExecute ? "NX" : "--",
2576	Pde.u & BIT64(9) ? '1' : '0',
2577	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2578	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2579	Pde.u & X86_PDE_PAE_PG_MASK);
2580	if (cMaxDepth >= 1)
2581	{
2582	/** @todo what about using the page pool for mapping PTs? */
2583	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2584	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2585	PX86PTPAE pPT = NULL;
2586	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2587	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2588	else
2589	{
2590	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2591	{
2592	uint64_t off = u64AddressPT - pMap->GCPtr;
2593	if (off < pMap->cb)
2594	{
2595	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2596	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2597	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2598	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2599	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2600	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2601	pPT = &pMap->aPTs[iPDE].paPaePTsHC[iSub];
2602	}
2603	}
2604	}
2605	int rc2 = VERR_INVALID_PARAMETER;
2606	if (pPT)
2607	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2608	else
2609	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2610	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2611	if (rc2 < rc && VBOX_SUCCESS(rc))
2612	rc = rc2;
2613	}
2614	}
2615	}
2616	}
2617	return rc;
2618	}
2619
2620
2621	/**
2622	* Dumps a PAE shadow page directory pointer table.
2623	*
2624	* @returns VBox status code (VINF_SUCCESS).
2625	* @param pVM The VM handle.
2626	* @param HCPhys The physical address of the page directory pointer table.
2627	* @param u64Address The virtual address of the page table starts.
2628	* @param cr4 The CR4, PSE is currently used.
2629	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2630	* @param cMaxDepth The maxium depth.
2631	* @param pHlp Pointer to the output functions.
2632	*/
2633	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2634	{
2635	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2636	if (!pPDPTR)
2637	{
2638	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2639	fLongMode ? 16 : 8, u64Address, HCPhys);
2640	return VERR_INVALID_PARAMETER;
2641	}
2642
2643	int rc = VINF_SUCCESS;
2644	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2645	for (unsigned i = 0; i < c; i++)
2646	{
2647	X86PDPE Pdpe = pPDPTR->a[i];
2648	if (Pdpe.n.u1Present)
2649	{
2650	if (fLongMode)
2651	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2652	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2653	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2654	Pdpe.n.u1Write ? 'W' : 'R',
2655	Pdpe.n.u1User ? 'U' : 'S',
2656	Pdpe.n.u1Accessed ? 'A' : '-',
2657	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2658	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2659	Pdpe.n.u1WriteThru ? "WT" : "--",
2660	Pdpe.n.u1CacheDisable? "CD" : "--",
2661	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2662	Pdpe.n.u1NoExecute ? "NX" : "--",
2663	Pdpe.u & BIT(9) ? '1' : '0',
2664	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2665	Pdpe.u & BIT(11) ? '1' : '0',
2666	Pdpe.u & X86_PDPE_PG_MASK);
2667	else
2668	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2669	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2670	i << X86_PDPTR_SHIFT,
2671	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2672	Pdpe.n.u1User ? '!' : '.', /* mbz */
2673	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2674	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2675	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2676	Pdpe.n.u1WriteThru ? "WT" : "--",
2677	Pdpe.n.u1CacheDisable? "CD" : "--",
2678	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2679	Pdpe.n.u1NoExecute ? "NX" : "--",
2680	Pdpe.u & BIT(9) ? '1' : '0',
2681	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2682	Pdpe.u & BIT(11) ? '1' : '0',
2683	Pdpe.u & X86_PDPE_PG_MASK);
2684	if (cMaxDepth >= 1)
2685	{
2686	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2687	cr4, fLongMode, cMaxDepth - 1, pHlp);
2688	if (rc2 < rc && VBOX_SUCCESS(rc))
2689	rc = rc2;
2690	}
2691	}
2692	}
2693	return rc;
2694	}
2695
2696
2697	/**
2698	* Dumps a 32-bit shadow page table.
2699	*
2700	* @returns VBox status code (VINF_SUCCESS).
2701	* @param pVM The VM handle.
2702	* @param HCPhys The physical address of the table.
2703	* @param cr4 The CR4, PSE is currently used.
2704	* @param cMaxDepth The maxium depth.
2705	* @param pHlp Pointer to the output functions.
2706	*/
2707	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2708	{
2709	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2710	if (!pPML4)
2711	{
2712	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2713	return VERR_INVALID_PARAMETER;
2714	}
2715
2716	int rc = VINF_SUCCESS;
2717	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2718	{
2719	X86PML4E Pml4e = pPML4->a[i];
2720	if (Pml4e.n.u1Present)
2721	{
2722	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2723	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2724	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2725	u64Address,
2726	Pml4e.n.u1Write ? 'W' : 'R',
2727	Pml4e.n.u1User ? 'U' : 'S',
2728	Pml4e.n.u1Accessed ? 'A' : '-',
2729	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2730	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2731	Pml4e.n.u1WriteThru ? "WT" : "--",
2732	Pml4e.n.u1CacheDisable? "CD" : "--",
2733	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2734	Pml4e.n.u1NoExecute ? "NX" : "--",
2735	Pml4e.u & BIT(9) ? '1' : '0',
2736	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2737	Pml4e.u & BIT(11) ? '1' : '0',
2738	Pml4e.u & X86_PML4E_PG_MASK);
2739
2740	if (cMaxDepth >= 1)
2741	{
2742	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2743	if (rc2 < rc && VBOX_SUCCESS(rc))
2744	rc = rc2;
2745	}
2746	}
2747	}
2748	return rc;
2749	}
2750
2751
2752	/**
2753	* Dumps a 32-bit shadow page table.
2754	*
2755	* @returns VBox status code (VINF_SUCCESS).
2756	* @param pVM The VM handle.
2757	* @param pPT Pointer to the page table.
2758	* @param u32Address The virtual address this table starts at.
2759	* @param pHlp Pointer to the output functions.
2760	*/
2761	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2762	{
2763	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2764	{
2765	X86PTE Pte = pPT->a[i];
2766	if (Pte.n.u1Present)
2767	{
2768	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2769	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2770	u32Address + (i << X86_PT_SHIFT),
2771	Pte.n.u1Write ? 'W' : 'R',
2772	Pte.n.u1User ? 'U' : 'S',
2773	Pte.n.u1Accessed ? 'A' : '-',
2774	Pte.n.u1Dirty ? 'D' : '-',
2775	Pte.n.u1Global ? 'G' : '-',
2776	Pte.n.u1WriteThru ? "WT" : "--",
2777	Pte.n.u1CacheDisable? "CD" : "--",
2778	Pte.n.u1PAT ? "AT" : "--",
2779	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2780	Pte.u & BIT(10) ? '1' : '0',
2781	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2782	Pte.u & X86_PDE_PG_MASK);
2783	}
2784	}
2785	return VINF_SUCCESS;
2786	}
2787
2788
2789	/**
2790	* Dumps a 32-bit shadow page directory and page tables.
2791	*
2792	* @returns VBox status code (VINF_SUCCESS).
2793	* @param pVM The VM handle.
2794	* @param cr3 The root of the hierarchy.
2795	* @param cr4 The CR4, PSE is currently used.
2796	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2797	* @param pHlp Pointer to the output functions.
2798	*/
2799	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2800	{
2801	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2802	if (!pPD)
2803	{
2804	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2805	return VERR_INVALID_PARAMETER;
2806	}
2807
2808	int rc = VINF_SUCCESS;
2809	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2810	{
2811	X86PDE Pde = pPD->a[i];
2812	if (Pde.n.u1Present)
2813	{
2814	const uint32_t u32Address = i << X86_PD_SHIFT;
2815	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2816	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2817	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2818	u32Address,
2819	Pde.b.u1Write ? 'W' : 'R',
2820	Pde.b.u1User ? 'U' : 'S',
2821	Pde.b.u1Accessed ? 'A' : '-',
2822	Pde.b.u1Dirty ? 'D' : '-',
2823	Pde.b.u1Global ? 'G' : '-',
2824	Pde.b.u1WriteThru ? "WT" : "--",
2825	Pde.b.u1CacheDisable? "CD" : "--",
2826	Pde.b.u1PAT ? "AT" : "--",
2827	Pde.u & BIT64(9) ? '1' : '0',
2828	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2829	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2830	Pde.u & X86_PDE4M_PG_MASK);
2831	else
2832	{
2833	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2834	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2835	u32Address,
2836	Pde.n.u1Write ? 'W' : 'R',
2837	Pde.n.u1User ? 'U' : 'S',
2838	Pde.n.u1Accessed ? 'A' : '-',
2839	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2840	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2841	Pde.n.u1WriteThru ? "WT" : "--",
2842	Pde.n.u1CacheDisable? "CD" : "--",
2843	Pde.u & BIT64(9) ? '1' : '0',
2844	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2845	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2846	Pde.u & X86_PDE_PG_MASK);
2847	if (cMaxDepth >= 1)
2848	{
2849	/** @todo what about using the page pool for mapping PTs? */
2850	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2851	PX86PT pPT = NULL;
2852	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2853	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2854	else
2855	{
2856	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2857	if (u32Address - pMap->GCPtr < pMap->cb)
2858	{
2859	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2860	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2861	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2862	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2863	pPT = pMap->aPTs[iPDE].pPTHC;
2864	}
2865	}
2866	int rc2 = VERR_INVALID_PARAMETER;
2867	if (pPT)
2868	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2869	else
2870	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2871	if (rc2 < rc && VBOX_SUCCESS(rc))
2872	rc = rc2;
2873	}
2874	}
2875	}
2876	}
2877
2878	return rc;
2879	}
2880
2881
2882	/**
2883	* Dumps a 32-bit shadow page table.
2884	*
2885	* @returns VBox status code (VINF_SUCCESS).
2886	* @param pVM The VM handle.
2887	* @param pPT Pointer to the page table.
2888	* @param u32Address The virtual address this table starts at.
2889	* @param PhysSearch Address to search for.
2890	*/
2891	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2892	{
2893	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2894	{
2895	X86PTE Pte = pPT->a[i];
2896	if (Pte.n.u1Present)
2897	{
2898	Log(( /P R S A D G WT CD AT NX 4M a m d /
2899	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2900	u32Address + (i << X86_PT_SHIFT),
2901	Pte.n.u1Write ? 'W' : 'R',
2902	Pte.n.u1User ? 'U' : 'S',
2903	Pte.n.u1Accessed ? 'A' : '-',
2904	Pte.n.u1Dirty ? 'D' : '-',
2905	Pte.n.u1Global ? 'G' : '-',
2906	Pte.n.u1WriteThru ? "WT" : "--",
2907	Pte.n.u1CacheDisable? "CD" : "--",
2908	Pte.n.u1PAT ? "AT" : "--",
2909	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2910	Pte.u & BIT(10) ? '1' : '0',
2911	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2912	Pte.u & X86_PDE_PG_MASK));
2913
2914	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2915	{
2916	uint64_t fPageShw = 0;
2917	RTHCPHYS pPhysHC = 0;
2918
2919	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2920	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2921	}
2922	}
2923	}
2924	return VINF_SUCCESS;
2925	}
2926
2927
2928	/**
2929	* Dumps a 32-bit guest page directory and page tables.
2930	*
2931	* @returns VBox status code (VINF_SUCCESS).
2932	* @param pVM The VM handle.
2933	* @param cr3 The root of the hierarchy.
2934	* @param cr4 The CR4, PSE is currently used.
2935	* @param PhysSearch Address to search for.
2936	*/
2937	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2938	{
2939	bool fLongMode = false;
2940	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2941	PX86PD pPD = 0;
2942
2943	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2944	if (VBOX_FAILURE(rc) \|\| !pPD)
2945	{
2946	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2947	return VERR_INVALID_PARAMETER;
2948	}
2949
2950	Log(("cr3=%08x cr4=%08x%s\n"
2951	"%-*s P - Present\n"
2952	"%-*s \| R/W - Read (0) / Write (1)\n"
2953	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2954	"%-*s \| \| \| A - Accessed\n"
2955	"%-*s \| \| \| \| D - Dirty\n"
2956	"%-*s \| \| \| \| \| G - Global\n"
2957	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2958	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2959	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2960	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2961	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2962	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2963	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2964	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2965	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2966	- W U - - - -- -- -- -- -- 010 */
2967	, cr3, cr4, fLongMode ? " Long Mode" : "",
2968	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2969	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2970
2971	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2972	{
2973	X86PDE Pde = pPD->a[i];
2974	if (Pde.n.u1Present)
2975	{
2976	const uint32_t u32Address = i << X86_PD_SHIFT;
2977
2978	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2979	Log(( /P R S A D G WT CD AT NX 4M a m d /
2980	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2981	u32Address,
2982	Pde.b.u1Write ? 'W' : 'R',
2983	Pde.b.u1User ? 'U' : 'S',
2984	Pde.b.u1Accessed ? 'A' : '-',
2985	Pde.b.u1Dirty ? 'D' : '-',
2986	Pde.b.u1Global ? 'G' : '-',
2987	Pde.b.u1WriteThru ? "WT" : "--",
2988	Pde.b.u1CacheDisable? "CD" : "--",
2989	Pde.b.u1PAT ? "AT" : "--",
2990	Pde.u & BIT(9) ? '1' : '0',
2991	Pde.u & BIT(10) ? '1' : '0',
2992	Pde.u & BIT(11) ? '1' : '0',
2993	Pde.u & X86_PDE4M_PG_MASK));
2994	/** @todo PhysSearch */
2995	else
2996	{
2997	Log(( /P R S A D G WT CD AT NX 4M a m d /
2998	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2999	u32Address,
3000	Pde.n.u1Write ? 'W' : 'R',
3001	Pde.n.u1User ? 'U' : 'S',
3002	Pde.n.u1Accessed ? 'A' : '-',
3003	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3004	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3005	Pde.n.u1WriteThru ? "WT" : "--",
3006	Pde.n.u1CacheDisable? "CD" : "--",
3007	Pde.u & BIT(9) ? '1' : '0',
3008	Pde.u & BIT(10) ? '1' : '0',
3009	Pde.u & BIT(11) ? '1' : '0',
3010	Pde.u & X86_PDE_PG_MASK));
3011	////if (cMaxDepth >= 1)
3012	{
3013	/** @todo what about using the page pool for mapping PTs? */
3014	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3015	PX86PT pPT = NULL;
3016
3017	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3018
3019	int rc2 = VERR_INVALID_PARAMETER;
3020	if (pPT)
3021	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3022	else
3023	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3024	if (rc2 < rc && VBOX_SUCCESS(rc))
3025	rc = rc2;
3026	}
3027	}
3028	}
3029	}
3030
3031	return rc;
3032	}
3033
3034
3035	/**
3036	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3037	*
3038	* @returns VBox status code (VINF_SUCCESS).
3039	* @param pVM The VM handle.
3040	* @param cr3 The root of the hierarchy.
3041	* @param cr4 The cr4, only PAE and PSE is currently used.
3042	* @param fLongMode Set if long mode, false if not long mode.
3043	* @param cMaxDepth Number of levels to dump.
3044	* @param pHlp Pointer to the output functions.
3045	*/
3046	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3047	{
3048	if (!pHlp)
3049	pHlp = DBGFR3InfoLogHlp();
3050	if (!cMaxDepth)
3051	return VINF_SUCCESS;
3052	const unsigned cch = fLongMode ? 16 : 8;
3053	pHlp->pfnPrintf(pHlp,
3054	"cr3=%08x cr4=%08x%s\n"
3055	"%-*s P - Present\n"
3056	"%-*s \| R/W - Read (0) / Write (1)\n"
3057	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3058	"%-*s \| \| \| A - Accessed\n"
3059	"%-*s \| \| \| \| D - Dirty\n"
3060	"%-*s \| \| \| \| \| G - Global\n"
3061	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3062	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3063	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3064	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3065	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3066	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3067	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3068	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3069	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3070	- W U - - - -- -- -- -- -- 010 */
3071	, cr3, cr4, fLongMode ? " Long Mode" : "",
3072	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3073	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3074	if (cr4 & X86_CR4_PAE)
3075	{
3076	if (fLongMode)
3077	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3078	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3079	}
3080	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3081	}
3082
3083
3084
3085	#ifdef VBOX_WITH_DEBUGGER
3086	/**
3087	* The '.pgmram' command.
3088	*
3089	* @returns VBox status.
3090	* @param pCmd Pointer to the command descriptor (as registered).
3091	* @param pCmdHlp Pointer to command helper functions.
3092	* @param pVM Pointer to the current VM (if any).
3093	* @param paArgs Pointer to (readonly) array of arguments.
3094	* @param cArgs Number of arguments in the array.
3095	*/
3096	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3097	{
3098	/*
3099	* Validate input.
3100	*/
3101	if (!pVM)
3102	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3103	if (!pVM->pgm.s.pRamRangesGC)
3104	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3105
3106	/*
3107	* Dump the ranges.
3108	*/
3109	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3110	PPGMRAMRANGE pRam;
3111	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3112	{
3113	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3114	"%VGp - %VGp %p\n",
3115	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3116	if (VBOX_FAILURE(rc))
3117	return rc;
3118	}
3119
3120	return VINF_SUCCESS;
3121	}
3122
3123
3124	/**
3125	* The '.pgmmap' command.
3126	*
3127	* @returns VBox status.
3128	* @param pCmd Pointer to the command descriptor (as registered).
3129	* @param pCmdHlp Pointer to command helper functions.
3130	* @param pVM Pointer to the current VM (if any).
3131	* @param paArgs Pointer to (readonly) array of arguments.
3132	* @param cArgs Number of arguments in the array.
3133	*/
3134	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3135	{
3136	/*
3137	* Validate input.
3138	*/
3139	if (!pVM)
3140	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3141	if (!pVM->pgm.s.pMappingsHC)
3142	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3143
3144	/*
3145	* Print message about the fixedness of the mappings.
3146	*/
3147	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3148	if (VBOX_FAILURE(rc))
3149	return rc;
3150
3151	/*
3152	* Dump the ranges.
3153	*/
3154	PPGMMAPPING pCur;
3155	for (pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
3156	{
3157	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3158	"%08x - %08x %s\n",
3159	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3160	if (VBOX_FAILURE(rc))
3161	return rc;
3162	}
3163
3164	return VINF_SUCCESS;
3165	}
3166
3167
3168	/**
3169	* The '.pgmsync' command.
3170	*
3171	* @returns VBox status.
3172	* @param pCmd Pointer to the command descriptor (as registered).
3173	* @param pCmdHlp Pointer to command helper functions.
3174	* @param pVM Pointer to the current VM (if any).
3175	* @param paArgs Pointer to (readonly) array of arguments.
3176	* @param cArgs Number of arguments in the array.
3177	*/
3178	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3179	{
3180	/*
3181	* Validate input.
3182	*/
3183	if (!pVM)
3184	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3185
3186	/*
3187	* Force page directory sync.
3188	*/
3189	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3190
3191	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3192	if (VBOX_FAILURE(rc))
3193	return rc;
3194
3195	return VINF_SUCCESS;
3196	}
3197
3198
3199	/**
3200	* The '.pgmsyncalways' command.
3201	*
3202	* @returns VBox status.
3203	* @param pCmd Pointer to the command descriptor (as registered).
3204	* @param pCmdHlp Pointer to command helper functions.
3205	* @param pVM Pointer to the current VM (if any).
3206	* @param paArgs Pointer to (readonly) array of arguments.
3207	* @param cArgs Number of arguments in the array.
3208	*/
3209	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3210	{
3211	/*
3212	* Validate input.
3213	*/
3214	if (!pVM)
3215	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3216
3217	/*
3218	* Force page directory sync.
3219	*/
3220	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3221	{
3222	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3223	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3224	}
3225	else
3226	{
3227	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3228	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3229	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3230	}
3231	}
3232
3233	#endif
3234
3235	/**
3236	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3237	*/
3238	typedef struct PGMCHECKINTARGS
3239	{
3240	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3241	PPGMPHYSHANDLER pPrevPhys;
3242	PPGMVIRTHANDLER pPrevVirt;
3243	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3244	PVM pVM;
3245	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3246
3247	/**
3248	* Validate a node in the physical handler tree.
3249	*
3250	* @returns 0 on if ok, other wise 1.
3251	* @param pNode The handler node.
3252	* @param pvUser pVM.
3253	*/
3254	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3255	{
3256	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3257	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3258	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3259	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3260	AssertReleaseMsg( !pArgs->pPrevPhys
3261	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3262	("pPrevPhys=%p %VGp-%VGp %s\n"
3263	" pCur=%p %VGp-%VGp %s\n",
3264	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3265	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3266	pArgs->pPrevPhys = pCur;
3267	return 0;
3268	}
3269
3270
3271	/**
3272	* Validate a node in the virtual handler tree.
3273	*
3274	* @returns 0 on if ok, other wise 1.
3275	* @param pNode The handler node.
3276	* @param pvUser pVM.
3277	*/
3278	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3279	{
3280	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3281	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3282	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3283	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3284	AssertReleaseMsg( !pArgs->pPrevVirt
3285	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3286	("pPrevVirt=%p %VGv-%VGv %s\n"
3287	" pCur=%p %VGv-%VGv %s\n",
3288	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3289	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3290	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3291	{
3292	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3293	("pCur=%p %VGv-%VGv %s\n"
3294	"iPage=%d offVirtHandle=%#x expected %#x\n",
3295	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3296	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3297	}
3298	pArgs->pPrevVirt = pCur;
3299	return 0;
3300	}
3301
3302
3303	/**
3304	* Validate a node in the virtual handler tree.
3305	*
3306	* @returns 0 on if ok, other wise 1.
3307	* @param pNode The handler node.
3308	* @param pvUser pVM.
3309	*/
3310	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3311	{
3312	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3313	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3314	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3315	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3316	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3317	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3318	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3319	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3320	" pCur=%p %VGp-%VGp\n",
3321	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3322	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3323	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3324	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3325	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3326	" pCur=%p %VGp-%VGp\n",
3327	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3328	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3329	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3330	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3331	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3332	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3333	{
3334	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3335	for (;;)
3336	{
3337	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3338	AssertReleaseMsg(pCur2 != pCur,
3339	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3340	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3341	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3342	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3343	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3344	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3345	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3346	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3347	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3348	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3349	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3350	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3351	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3352	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3353	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3354	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3355	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3356	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3357	break;
3358	}
3359	}
3360
3361	pArgs->pPrevPhys2Virt = pCur;
3362	return 0;
3363	}
3364
3365
3366	/**
3367	* Perform an integrity check on the PGM component.
3368	*
3369	* @returns VINF_SUCCESS if everything is fine.
3370	* @returns VBox error status after asserting on integrity breach.
3371	* @param pVM The VM handle.
3372	*/
3373	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3374	{
3375	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3376
3377	/*
3378	* Check the trees.
3379	*/
3380	int cErrors = 0;
3381	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3382	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3383	Args.fLeftToRight = false;
3384	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3385	Args.fLeftToRight = true;
3386	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3387	Args.fLeftToRight = false;
3388	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3389	Args.fLeftToRight = true;
3390	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3391	Args.fLeftToRight = false;
3392	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3393
3394	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3395	}
3396
3397
3398	/**
3399	* Inform PGM we don't wish any mapping to be put into the shadow page table. (necessary for e.g. VMX)
3400	*
3401	* @returns VBox status code.
3402	* @param pVM VM handle.
3403	*/
3404	PGMR3DECL(int) PGMR3RemoveMappingsFromShwPD(PVM pVM)
3405	{
3406
3407	pVM->pgm.s.fDisableMappings = true;
3408
3409	size_t cb;
3410	int rc = PGMR3MappingsSize(pVM, &cb);
3411	AssertRCReturn(rc, rc);
3412
3413	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3414	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3415	AssertRCReturn(rc, rc);
3416
3417	VMMR3DisableSwitcher(pVM);
3418	return VINF_SUCCESS;
3419	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 850

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