PGM.cpp@ 9981

Last change on this file since 9981 was 9981, checked in by vboxsync, 16 years ago
Always switch the PGM mode when we're using VT-x/AMD-v
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1	/* $Id: PGM.cpp 9981 2008-06-27 08:39:23Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	#endif
636
637
638	/*******************************************************************************
639	* Global Variables *
640	*******************************************************************************/
641	#ifdef VBOX_WITH_DEBUGGER
642	/** Command descriptors. */
643	static const DBGCCMD g_aCmds[] =
644	{
645	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
646	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
647	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
648	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
649	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
650	};
651	#endif
652
653
654
655
656	/*
657	* Shadow - 32-bit mode
658	*/
659	#define PGM_SHW_TYPE PGM_TYPE_32BIT
660	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
661	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
662	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
663	#include "PGMShw.h"
664
665	/* Guest - real mode */
666	#define PGM_GST_TYPE PGM_TYPE_REAL
667	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
668	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
669	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
670	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
671	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
672	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
673	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
674	#include "PGMGst.h"
675	#include "PGMBth.h"
676	#undef BTH_PGMPOOLKIND_PT_FOR_PT
677	#undef PGM_BTH_NAME
678	#undef PGM_BTH_NAME_GC_STR
679	#undef PGM_BTH_NAME_R0_STR
680	#undef PGM_GST_TYPE
681	#undef PGM_GST_NAME
682	#undef PGM_GST_NAME_GC_STR
683	#undef PGM_GST_NAME_R0_STR
684
685	/* Guest - protected mode */
686	#define PGM_GST_TYPE PGM_TYPE_PROT
687	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
688	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
689	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
690	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
691	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
692	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
693	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
694	#include "PGMGst.h"
695	#include "PGMBth.h"
696	#undef BTH_PGMPOOLKIND_PT_FOR_PT
697	#undef PGM_BTH_NAME
698	#undef PGM_BTH_NAME_GC_STR
699	#undef PGM_BTH_NAME_R0_STR
700	#undef PGM_GST_TYPE
701	#undef PGM_GST_NAME
702	#undef PGM_GST_NAME_GC_STR
703	#undef PGM_GST_NAME_R0_STR
704
705	/* Guest - 32-bit mode */
706	#define PGM_GST_TYPE PGM_TYPE_32BIT
707	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
708	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
709	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
710	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
711	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
712	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
713	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
714	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
715	#include "PGMGst.h"
716	#include "PGMBth.h"
717	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
718	#undef BTH_PGMPOOLKIND_PT_FOR_PT
719	#undef PGM_BTH_NAME
720	#undef PGM_BTH_NAME_GC_STR
721	#undef PGM_BTH_NAME_R0_STR
722	#undef PGM_GST_TYPE
723	#undef PGM_GST_NAME
724	#undef PGM_GST_NAME_GC_STR
725	#undef PGM_GST_NAME_R0_STR
726
727	#undef PGM_SHW_TYPE
728	#undef PGM_SHW_NAME
729	#undef PGM_SHW_NAME_GC_STR
730	#undef PGM_SHW_NAME_R0_STR
731
732
733	/*
734	* Shadow - PAE mode
735	*/
736	#define PGM_SHW_TYPE PGM_TYPE_PAE
737	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
738	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
739	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
740	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
741	#include "PGMShw.h"
742
743	/* Guest - real mode */
744	#define PGM_GST_TYPE PGM_TYPE_REAL
745	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
746	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
747	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
748	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
749	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
750	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
751	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
752	#include "PGMBth.h"
753	#undef BTH_PGMPOOLKIND_PT_FOR_PT
754	#undef PGM_BTH_NAME
755	#undef PGM_BTH_NAME_GC_STR
756	#undef PGM_BTH_NAME_R0_STR
757	#undef PGM_GST_TYPE
758	#undef PGM_GST_NAME
759	#undef PGM_GST_NAME_GC_STR
760	#undef PGM_GST_NAME_R0_STR
761
762	/* Guest - protected mode */
763	#define PGM_GST_TYPE PGM_TYPE_PROT
764	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
765	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
766	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
767	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
768	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
769	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
770	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
771	#include "PGMBth.h"
772	#undef BTH_PGMPOOLKIND_PT_FOR_PT
773	#undef PGM_BTH_NAME
774	#undef PGM_BTH_NAME_GC_STR
775	#undef PGM_BTH_NAME_R0_STR
776	#undef PGM_GST_TYPE
777	#undef PGM_GST_NAME
778	#undef PGM_GST_NAME_GC_STR
779	#undef PGM_GST_NAME_R0_STR
780
781	/* Guest - 32-bit mode */
782	#define PGM_GST_TYPE PGM_TYPE_32BIT
783	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
784	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
785	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
786	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
787	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
788	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
789	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
790	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
791	#include "PGMBth.h"
792	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
793	#undef BTH_PGMPOOLKIND_PT_FOR_PT
794	#undef PGM_BTH_NAME
795	#undef PGM_BTH_NAME_GC_STR
796	#undef PGM_BTH_NAME_R0_STR
797	#undef PGM_GST_TYPE
798	#undef PGM_GST_NAME
799	#undef PGM_GST_NAME_GC_STR
800	#undef PGM_GST_NAME_R0_STR
801
802	/* Guest - PAE mode */
803	#define PGM_GST_TYPE PGM_TYPE_PAE
804	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
805	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
806	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
807	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
808	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
809	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
810	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
811	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
812	#include "PGMGst.h"
813	#include "PGMBth.h"
814	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
815	#undef BTH_PGMPOOLKIND_PT_FOR_PT
816	#undef PGM_BTH_NAME
817	#undef PGM_BTH_NAME_GC_STR
818	#undef PGM_BTH_NAME_R0_STR
819	#undef PGM_GST_TYPE
820	#undef PGM_GST_NAME
821	#undef PGM_GST_NAME_GC_STR
822	#undef PGM_GST_NAME_R0_STR
823
824	#undef PGM_SHW_TYPE
825	#undef PGM_SHW_NAME
826	#undef PGM_SHW_NAME_GC_STR
827	#undef PGM_SHW_NAME_R0_STR
828
829
830	/*
831	* Shadow - AMD64 mode
832	*/
833	#define PGM_SHW_TYPE PGM_TYPE_AMD64
834	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
835	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
836	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
837	#include "PGMShw.h"
838
839	/* Guest - AMD64 mode */
840	#define PGM_GST_TYPE PGM_TYPE_AMD64
841	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
842	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
843	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
844	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
845	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
846	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
847	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
848	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
849	#include "PGMGst.h"
850	#include "PGMBth.h"
851	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
852	#undef BTH_PGMPOOLKIND_PT_FOR_PT
853	#undef PGM_BTH_NAME
854	#undef PGM_BTH_NAME_GC_STR
855	#undef PGM_BTH_NAME_R0_STR
856	#undef PGM_GST_TYPE
857	#undef PGM_GST_NAME
858	#undef PGM_GST_NAME_GC_STR
859	#undef PGM_GST_NAME_R0_STR
860
861	#undef PGM_SHW_TYPE
862	#undef PGM_SHW_NAME
863	#undef PGM_SHW_NAME_GC_STR
864	#undef PGM_SHW_NAME_R0_STR
865
866	/*
867	* Shadow - Nested paging mode
868	*/
869	#define PGM_SHW_TYPE PGM_TYPE_NESTED
870	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
871	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
872	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
873	#include "PGMShw.h"
874
875	/* Guest - real mode */
876	#define PGM_GST_TYPE PGM_TYPE_REAL
877	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
878	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
879	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
880	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
881	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
882	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
883	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
884	#include "PGMBth.h"
885	#undef BTH_PGMPOOLKIND_PT_FOR_PT
886	#undef PGM_BTH_NAME
887	#undef PGM_BTH_NAME_GC_STR
888	#undef PGM_BTH_NAME_R0_STR
889	#undef PGM_GST_TYPE
890	#undef PGM_GST_NAME
891	#undef PGM_GST_NAME_GC_STR
892	#undef PGM_GST_NAME_R0_STR
893
894	/* Guest - protected mode */
895	#define PGM_GST_TYPE PGM_TYPE_PROT
896	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
897	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
898	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
899	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
900	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
901	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
902	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
903	#include "PGMBth.h"
904	#undef BTH_PGMPOOLKIND_PT_FOR_PT
905	#undef PGM_BTH_NAME
906	#undef PGM_BTH_NAME_GC_STR
907	#undef PGM_BTH_NAME_R0_STR
908	#undef PGM_GST_TYPE
909	#undef PGM_GST_NAME
910	#undef PGM_GST_NAME_GC_STR
911	#undef PGM_GST_NAME_R0_STR
912
913	/* Guest - 32-bit mode */
914	#define PGM_GST_TYPE PGM_TYPE_32BIT
915	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
916	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
917	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
918	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
919	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
920	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
921	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
922	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
923	#include "PGMBth.h"
924	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
925	#undef BTH_PGMPOOLKIND_PT_FOR_PT
926	#undef PGM_BTH_NAME
927	#undef PGM_BTH_NAME_GC_STR
928	#undef PGM_BTH_NAME_R0_STR
929	#undef PGM_GST_TYPE
930	#undef PGM_GST_NAME
931	#undef PGM_GST_NAME_GC_STR
932	#undef PGM_GST_NAME_R0_STR
933
934	/* Guest - PAE mode */
935	#define PGM_GST_TYPE PGM_TYPE_PAE
936	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
937	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
938	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
939	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
940	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
941	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
942	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
943	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
944	#include "PGMBth.h"
945	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
946	#undef BTH_PGMPOOLKIND_PT_FOR_PT
947	#undef PGM_BTH_NAME
948	#undef PGM_BTH_NAME_GC_STR
949	#undef PGM_BTH_NAME_R0_STR
950	#undef PGM_GST_TYPE
951	#undef PGM_GST_NAME
952	#undef PGM_GST_NAME_GC_STR
953	#undef PGM_GST_NAME_R0_STR
954
955	/* Guest - AMD64 mode */
956	#define PGM_GST_TYPE PGM_TYPE_AMD64
957	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
958	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
959	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
960	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
961	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
962	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
963	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
964	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
965	#include "PGMBth.h"
966	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
967	#undef BTH_PGMPOOLKIND_PT_FOR_PT
968	#undef PGM_BTH_NAME
969	#undef PGM_BTH_NAME_GC_STR
970	#undef PGM_BTH_NAME_R0_STR
971	#undef PGM_GST_TYPE
972	#undef PGM_GST_NAME
973	#undef PGM_GST_NAME_GC_STR
974	#undef PGM_GST_NAME_R0_STR
975
976	#undef PGM_SHW_TYPE
977	#undef PGM_SHW_NAME
978	#undef PGM_SHW_NAME_GC_STR
979	#undef PGM_SHW_NAME_R0_STR
980
981
982	/**
983	* Initiates the paging of VM.
984	*
985	* @returns VBox status code.
986	* @param pVM Pointer to VM structure.
987	*/
988	PGMR3DECL(int) PGMR3Init(PVM pVM)
989	{
990	LogFlow(("PGMR3Init:\n"));
991
992	/*
993	* Assert alignment and sizes.
994	*/
995	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
996
997	/*
998	* Init the structure.
999	*/
1000	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1001	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1002	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1003	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1004	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1005	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1006	pVM->pgm.s.fA20Enabled = true;
1007	pVM->pgm.s.pGstPaePDPTHC = NULL;
1008	pVM->pgm.s.pGstPaePDPTGC = 0;
1009	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1010	{
1011	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1012	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1013	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1014	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1015	}
1016
1017	#ifdef VBOX_STRICT
1018	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1019	#endif
1020
1021	/*
1022	* Get the configured RAM size - to estimate saved state size.
1023	*/
1024	uint64_t cbRam;
1025	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1026	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1027	cbRam = pVM->pgm.s.cbRamSize = 0;
1028	else if (VBOX_SUCCESS(rc))
1029	{
1030	if (cbRam < PAGE_SIZE)
1031	cbRam = 0;
1032	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1033	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1034	}
1035	else
1036	{
1037	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1038	return rc;
1039	}
1040
1041	/*
1042	* Register saved state data unit.
1043	*/
1044	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1045	NULL, pgmR3Save, NULL,
1046	NULL, pgmR3Load, NULL);
1047	if (VBOX_FAILURE(rc))
1048	return rc;
1049
1050	/*
1051	* Initialize the PGM critical section and flush the phys TLBs
1052	*/
1053	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1054	AssertRCReturn(rc, rc);
1055
1056	PGMR3PhysChunkInvalidateTLB(pVM);
1057	PGMPhysInvalidatePageR3MapTLB(pVM);
1058	PGMPhysInvalidatePageR0MapTLB(pVM);
1059	PGMPhysInvalidatePageGCMapTLB(pVM);
1060
1061	/*
1062	* Trees
1063	*/
1064	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1065	if (VBOX_SUCCESS(rc))
1066	{
1067	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1068
1069	/*
1070	* Alocate the zero page.
1071	*/
1072	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1073	}
1074	if (VBOX_SUCCESS(rc))
1075	{
1076	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
1077	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1078	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1079	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1080	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1081
1082	/*
1083	* Init the paging.
1084	*/
1085	rc = pgmR3InitPaging(pVM);
1086	}
1087	if (VBOX_SUCCESS(rc))
1088	{
1089	/*
1090	* Init the page pool.
1091	*/
1092	rc = pgmR3PoolInit(pVM);
1093	}
1094	if (VBOX_SUCCESS(rc))
1095	{
1096	/*
1097	* Info & statistics
1098	*/
1099	DBGFR3InfoRegisterInternal(pVM, "mode",
1100	"Shows the current paging mode. "
1101	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1102	pgmR3InfoMode);
1103	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1104	"Dumps all the entries in the top level paging table. No arguments.",
1105	pgmR3InfoCr3);
1106	DBGFR3InfoRegisterInternal(pVM, "phys",
1107	"Dumps all the physical address ranges. No arguments.",
1108	pgmR3PhysInfo);
1109	DBGFR3InfoRegisterInternal(pVM, "handlers",
1110	"Dumps physical, virtual and hyper virtual handlers. "
1111	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1112	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1113	pgmR3InfoHandlers);
1114	DBGFR3InfoRegisterInternal(pVM, "mappings",
1115	"Dumps guest mappings.",
1116	pgmR3MapInfo);
1117
1118	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1119	#ifdef VBOX_WITH_STATISTICS
1120	pgmR3InitStats(pVM);
1121	#endif
1122	#ifdef VBOX_WITH_DEBUGGER
1123	/*
1124	* Debugger commands.
1125	*/
1126	static bool fRegisteredCmds = false;
1127	if (!fRegisteredCmds)
1128	{
1129	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1130	if (VBOX_SUCCESS(rc))
1131	fRegisteredCmds = true;
1132	}
1133	#endif
1134	return VINF_SUCCESS;
1135	}
1136
1137	/* Almost no cleanup necessary, MM frees all memory. */
1138	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1139
1140	return rc;
1141	}
1142
1143
1144	/**
1145	* Init paging.
1146	*
1147	* Since we need to check what mode the host is operating in before we can choose
1148	* the right paging functions for the host we have to delay this until R0 has
1149	* been initialized.
1150	*
1151	* @returns VBox status code.
1152	* @param pVM VM handle.
1153	*/
1154	static int pgmR3InitPaging(PVM pVM)
1155	{
1156	/*
1157	* Force a recalculation of modes and switcher so everyone gets notified.
1158	*/
1159	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1160	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1161	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1162
1163	/*
1164	* Allocate static mapping space for whatever the cr3 register
1165	* points to and in the case of PAE mode to the 4 PDs.
1166	*/
1167	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1168	if (VBOX_FAILURE(rc))
1169	{
1170	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1171	return rc;
1172	}
1173	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1174
1175	/*
1176	* Allocate pages for the three possible intermediate contexts
1177	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1178	* for the sake of simplicity. The AMD64 uses the PAE for the
1179	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1180	*
1181	* We assume that two page tables will be enought for the core code
1182	* mappings (HC virtual and identity).
1183	*/
1184	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1185	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1186	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1187	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1188	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1189	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1190	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1191	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1192	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1193	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1194	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1195	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1196	if ( !pVM->pgm.s.pInterPD
1197	\|\| !pVM->pgm.s.apInterPTs[0]
1198	\|\| !pVM->pgm.s.apInterPTs[1]
1199	\|\| !pVM->pgm.s.apInterPaePTs[0]
1200	\|\| !pVM->pgm.s.apInterPaePTs[1]
1201	\|\| !pVM->pgm.s.apInterPaePDs[0]
1202	\|\| !pVM->pgm.s.apInterPaePDs[1]
1203	\|\| !pVM->pgm.s.apInterPaePDs[2]
1204	\|\| !pVM->pgm.s.apInterPaePDs[3]
1205	\|\| !pVM->pgm.s.pInterPaePDPT
1206	\|\| !pVM->pgm.s.pInterPaePDPT64
1207	\|\| !pVM->pgm.s.pInterPaePML4)
1208	{
1209	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1210	return VERR_NO_PAGE_MEMORY;
1211	}
1212
1213	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1214	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1215	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1216	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1217	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1218	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1219
1220	/*
1221	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1222	*/
1223	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1224	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1225	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1226
1227	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1228	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1229
1230	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1231	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1232	{
1233	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1234	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1235	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1236	}
1237
1238	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1239	{
1240	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1241	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1242	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1243	}
1244
1245	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1246	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1247	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1248	\| HCPhysInterPaePDPT64;
1249
1250	/*
1251	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1252	* We allocate pages for all three posibilities to in order to simplify mappings and
1253	* avoid resource failure during mode switches. So, we need to cover all levels of the
1254	* of the first 4GB down to PD level.
1255	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1256	*/
1257	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1258	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1259	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1260	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1261	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1262	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1263	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1264	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1265	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1266	if ( !pVM->pgm.s.pHC32BitPD
1267	\|\| !pVM->pgm.s.apHCPaePDs[0]
1268	\|\| !pVM->pgm.s.apHCPaePDs[1]
1269	\|\| !pVM->pgm.s.apHCPaePDs[2]
1270	\|\| !pVM->pgm.s.apHCPaePDs[3]
1271	\|\| !pVM->pgm.s.pHCPaePDPT)
1272	{
1273	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1274	return VERR_NO_PAGE_MEMORY;
1275	}
1276
1277	/* get physical addresses. */
1278	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1279	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1280	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1281	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1282	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1283	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1284	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1285
1286	/*
1287	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1288	*/
1289	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1290
1291	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1292	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1293	{
1294	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1295	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1296	/* The flags will be corrected when entering and leaving long mode. */
1297	}
1298
1299	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1300
1301	/*
1302	* Initialize paging workers and mode from current host mode
1303	* and the guest running in real mode.
1304	*/
1305	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1306	switch (pVM->pgm.s.enmHostMode)
1307	{
1308	case SUPPAGINGMODE_32_BIT:
1309	case SUPPAGINGMODE_32_BIT_GLOBAL:
1310	case SUPPAGINGMODE_PAE:
1311	case SUPPAGINGMODE_PAE_GLOBAL:
1312	case SUPPAGINGMODE_PAE_NX:
1313	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1314	break;
1315
1316	case SUPPAGINGMODE_AMD64:
1317	case SUPPAGINGMODE_AMD64_GLOBAL:
1318	case SUPPAGINGMODE_AMD64_NX:
1319	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1320	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1321	if (ARCH_BITS != 64)
1322	{
1323	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1324	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1325	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1326	}
1327	#endif
1328	break;
1329	default:
1330	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1331	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1332	}
1333	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1334	if (VBOX_SUCCESS(rc))
1335	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1336	if (VBOX_SUCCESS(rc))
1337	{
1338	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1339	#if HC_ARCH_BITS == 64
1340	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1341	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1342	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1343	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1344	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1345	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1346	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1347	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1348	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1349	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1350	#endif
1351
1352	return VINF_SUCCESS;
1353	}
1354
1355	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1356	return rc;
1357	}
1358
1359
1360	#ifdef VBOX_WITH_STATISTICS
1361	/**
1362	* Init statistics
1363	*/
1364	static void pgmR3InitStats(PVM pVM)
1365	{
1366	PPGM pPGM = &pVM->pgm.s;
1367	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1368	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1369	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1370	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1371	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1372	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1373	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1374	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1375	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1376	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1377	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1378	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1379	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1380	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1381	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1382	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1383	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1384	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1385	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1386	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1387	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1388	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1389
1390	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1391	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1392	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1393	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1394	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1395	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1396	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1397	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1398	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1399	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1400	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1401	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1402	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1403	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1404	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1405	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1406	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1407	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1408	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1409
1410	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1411	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1412	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1413	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1414	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1415	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1416	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1417	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1418
1419	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1420	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1421	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1422	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1423	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1424	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1425	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1426
1427	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1428	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1429	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1430	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1431	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1432	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1433	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1434
1435	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1436	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1437
1438	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1439	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1440	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1441
1442	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1443	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1444
1445	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1446	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1447
1448	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1449	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1450
1451	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1452	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1453	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1454
1455	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1456	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1457	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1458	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1459	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1460	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1461	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1462	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1463	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1464	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1465	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1466
1467	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1468	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1469	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1470	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1471	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1472	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1473	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1474
1475	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1476	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1477	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1478	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1479
1480	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1481	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1482	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1483	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1484	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1485
1486	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1487	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1488	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1489	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1490	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1491	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1492	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1493	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1494	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1495	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1496	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1497	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1498
1499	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1500	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1501	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1502	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1503	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1504	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1505	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1506	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1507	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1508	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1509	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1510	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1511
1512	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1513	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1514	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1515
1516	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1517	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1518
1519	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1520	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1521	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1522	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1523
1524	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1525	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1526
1527	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1528	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1529	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1530	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1531	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1532	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1533	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1534	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1535	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1536	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1537	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1538	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1539	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1540
1541	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1542	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1543	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1544	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1545	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1546	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1547	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1548	#endif
1549
1550	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1551	{
1552	/** @todo r=bird: We need a STAMR3RegisterF()! */
1553	char szName[32];
1554
1555	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1556	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1557	AssertRC(rc);
1558
1559	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1560	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1561	AssertRC(rc);
1562
1563	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1564	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1565	AssertRC(rc);
1566	}
1567	}
1568	#endif /* VBOX_WITH_STATISTICS */
1569
1570	/**
1571	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1572	*
1573	* The dynamic mapping area will also be allocated and initialized at this
1574	* time. We could allocate it during PGMR3Init of course, but the mapping
1575	* wouldn't be allocated at that time preventing us from setting up the
1576	* page table entries with the dummy page.
1577	*
1578	* @returns VBox status code.
1579	* @param pVM VM handle.
1580	*/
1581	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1582	{
1583	RTGCPTR GCPtr;
1584	/*
1585	* Reserve space for mapping the paging pages into guest context.
1586	*/
1587	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1588	AssertRCReturn(rc, rc);
1589	pVM->pgm.s.pGC32BitPD = GCPtr;
1590	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1591
1592	/*
1593	* Reserve space for the dynamic mappings.
1594	*/
1595	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1596	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1597	if (VBOX_SUCCESS(rc))
1598	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1599
1600	if ( VBOX_SUCCESS(rc)
1601	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1602	{
1603	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1604	if (VBOX_SUCCESS(rc))
1605	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1606	}
1607	if (VBOX_SUCCESS(rc))
1608	{
1609	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1610	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1611	}
1612	return rc;
1613	}
1614
1615
1616	/**
1617	* Ring-3 init finalizing.
1618	*
1619	* @returns VBox status code.
1620	* @param pVM The VM handle.
1621	*/
1622	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1623	{
1624	/*
1625	* Map the paging pages into the guest context.
1626	*/
1627	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1628	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1629
1630	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1631	AssertRCReturn(rc, rc);
1632	pVM->pgm.s.pGC32BitPD = GCPtr;
1633	GCPtr += PAGE_SIZE;
1634	GCPtr += PAGE_SIZE; /* reserved page */
1635
1636	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1637	{
1638	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1639	AssertRCReturn(rc, rc);
1640	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1641	GCPtr += PAGE_SIZE;
1642	}
1643	/* A bit of paranoia is justified. */
1644	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1645	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1646	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1647	GCPtr += PAGE_SIZE; /* reserved page */
1648
1649	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1650	AssertRCReturn(rc, rc);
1651	pVM->pgm.s.pGCPaePDPT = GCPtr;
1652	GCPtr += PAGE_SIZE;
1653	GCPtr += PAGE_SIZE; /* reserved page */
1654
1655
1656	/*
1657	* Reserve space for the dynamic mappings.
1658	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1659	*/
1660	/* get the pointer to the page table entries. */
1661	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1662	AssertRelease(pMapping);
1663	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1664	const unsigned iPT = off >> X86_PD_SHIFT;
1665	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1666	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1667	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1668
1669	/* init cache */
1670	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1671	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1672	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1673
1674	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1675	{
1676	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1677	AssertRCReturn(rc, rc);
1678	}
1679
1680	return rc;
1681	}
1682
1683
1684	/**
1685	* Applies relocations to data and code managed by this
1686	* component. This function will be called at init and
1687	* whenever the VMM need to relocate it self inside the GC.
1688	*
1689	* @param pVM The VM.
1690	* @param offDelta Relocation delta relative to old location.
1691	*/
1692	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1693	{
1694	LogFlow(("PGMR3Relocate\n"));
1695
1696	/*
1697	* Paging stuff.
1698	*/
1699	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1700	/** @todo move this into shadow and guest specific relocation functions. */
1701	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1702	pVM->pgm.s.pGC32BitPD += offDelta;
1703	pVM->pgm.s.pGuestPDGC += offDelta;
1704	AssertCompile(ELEMENTS(pVM->pgm.s.apGCPaePDs) == ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1705	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1706	{
1707	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1708	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1709	}
1710	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1711	pVM->pgm.s.pGCPaePDPT += offDelta;
1712
1713	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1714	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1715
1716	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1717	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1718	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1719
1720	/*
1721	* Trees.
1722	*/
1723	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1724
1725	/*
1726	* Ram ranges.
1727	*/
1728	if (pVM->pgm.s.pRamRangesR3)
1729	{
1730	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1731	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1732	#ifdef VBOX_WITH_NEW_PHYS_CODE
1733	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1734	#else
1735	{
1736	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1737	if (pCur->pavHCChunkGC)
1738	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1739	}
1740	#endif
1741	}
1742
1743	/*
1744	* Update the two page directories with all page table mappings.
1745	* (One or more of them have changed, that's why we're here.)
1746	*/
1747	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1748	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1749	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1750
1751	/* Relocate GC addresses of Page Tables. */
1752	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1753	{
1754	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1755	{
1756	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1757	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1758	}
1759	}
1760
1761	/*
1762	* Dynamic page mapping area.
1763	*/
1764	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1765	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1766	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1767
1768	/*
1769	* The Zero page.
1770	*/
1771	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1772	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1773
1774	/*
1775	* Physical and virtual handlers.
1776	*/
1777	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1778	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1779	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1780
1781	/*
1782	* The page pool.
1783	*/
1784	pgmR3PoolRelocate(pVM);
1785	}
1786
1787
1788	/**
1789	* Callback function for relocating a physical access handler.
1790	*
1791	* @returns 0 (continue enum)
1792	* @param pNode Pointer to a PGMPHYSHANDLER node.
1793	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1794	* not certain the delta will fit in a void pointer for all possible configs.
1795	*/
1796	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1797	{
1798	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1799	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1800	if (pHandler->pfnHandlerGC)
1801	pHandler->pfnHandlerGC += offDelta;
1802	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1803	pHandler->pvUserGC += offDelta;
1804	return 0;
1805	}
1806
1807
1808	/**
1809	* Callback function for relocating a virtual access handler.
1810	*
1811	* @returns 0 (continue enum)
1812	* @param pNode Pointer to a PGMVIRTHANDLER node.
1813	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1814	* not certain the delta will fit in a void pointer for all possible configs.
1815	*/
1816	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1817	{
1818	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1819	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1820	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1821	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1822	Assert(pHandler->pfnHandlerGC);
1823	pHandler->pfnHandlerGC += offDelta;
1824	return 0;
1825	}
1826
1827
1828	/**
1829	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1830	*
1831	* @returns 0 (continue enum)
1832	* @param pNode Pointer to a PGMVIRTHANDLER node.
1833	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1834	* not certain the delta will fit in a void pointer for all possible configs.
1835	*/
1836	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1837	{
1838	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1839	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1840	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1841	Assert(pHandler->pfnHandlerGC);
1842	pHandler->pfnHandlerGC += offDelta;
1843	return 0;
1844	}
1845
1846
1847	/**
1848	* The VM is being reset.
1849	*
1850	* For the PGM component this means that any PD write monitors
1851	* needs to be removed.
1852	*
1853	* @param pVM VM handle.
1854	*/
1855	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1856	{
1857	LogFlow(("PGMR3Reset:\n"));
1858	VM_ASSERT_EMT(pVM);
1859
1860	pgmLock(pVM);
1861
1862	/*
1863	* Unfix any fixed mappings and disable CR3 monitoring.
1864	*/
1865	pVM->pgm.s.fMappingsFixed = false;
1866	pVM->pgm.s.GCPtrMappingFixed = 0;
1867	pVM->pgm.s.cbMappingFixed = 0;
1868
1869	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1870	AssertRC(rc);
1871	#ifdef DEBUG
1872	DBGFR3InfoLog(pVM, "mappings", NULL);
1873	DBGFR3InfoLog(pVM, "handlers", "all nostat");
1874	#endif
1875
1876	/*
1877	* Reset the shadow page pool.
1878	*/
1879	pgmR3PoolReset(pVM);
1880
1881	/*
1882	* Re-init other members.
1883	*/
1884	pVM->pgm.s.fA20Enabled = true;
1885
1886	/*
1887	* Clear the FFs PGM owns.
1888	*/
1889	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1890	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1891
1892	/*
1893	* Reset (zero) RAM pages.
1894	*/
1895	rc = pgmR3PhysRamReset(pVM);
1896	if (RT_SUCCESS(rc))
1897	{
1898	#ifdef VBOX_WITH_NEW_PHYS_CODE
1899	/*
1900	* Reset (zero) shadow ROM pages.
1901	*/
1902	rc = pgmR3PhysRomReset(pVM);
1903	#endif
1904	if (RT_SUCCESS(rc))
1905	{
1906	/*
1907	* Switch mode back to real mode.
1908	*/
1909	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1910	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1911	}
1912	}
1913
1914	pgmUnlock(pVM);
1915	//return rc;
1916	AssertReleaseRC(rc);
1917	}
1918
1919
1920	#ifdef VBOX_STRICT
1921	/**
1922	* VM state change callback for clearing fNoMorePhysWrites after
1923	* a snapshot has been created.
1924	*/
1925	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1926	{
1927	if (enmState == VMSTATE_RUNNING)
1928	pVM->pgm.s.fNoMorePhysWrites = false;
1929	}
1930	#endif
1931
1932
1933	/**
1934	* Terminates the PGM.
1935	*
1936	* @returns VBox status code.
1937	* @param pVM Pointer to VM structure.
1938	*/
1939	PGMR3DECL(int) PGMR3Term(PVM pVM)
1940	{
1941	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1942	}
1943
1944
1945	/**
1946	* Execute state save operation.
1947	*
1948	* @returns VBox status code.
1949	* @param pVM VM Handle.
1950	* @param pSSM SSM operation handle.
1951	*/
1952	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1953	{
1954	PPGM pPGM = &pVM->pgm.s;
1955
1956	/* No more writes to physical memory after this point! */
1957	pVM->pgm.s.fNoMorePhysWrites = true;
1958
1959	/*
1960	* Save basic data (required / unaffected by relocation).
1961	*/
1962	#if 1
1963	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1964	#else
1965	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1966	#endif
1967	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1968	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1969	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1970	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1971	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1972	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1973	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1974	SSMR3PutU32(pSSM, ~0); /* Separator. */
1975
1976	/*
1977	* The guest mappings.
1978	*/
1979	uint32_t i = 0;
1980	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1981	{
1982	SSMR3PutU32(pSSM, i);
1983	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1984	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1985	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1986	/* flags are done by the mapping owners! */
1987	}
1988	SSMR3PutU32(pSSM, ~0); /* terminator. */
1989
1990	/*
1991	* Ram range flags and bits.
1992	*/
1993	i = 0;
1994	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
1995	{
1996	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1997
1998	SSMR3PutU32(pSSM, i);
1999	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2000	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2001	SSMR3PutGCPhys(pSSM, pRam->cb);
2002	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
2003
2004	/* Flags. */
2005	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2006	for (unsigned iPage = 0; iPage < cPages; iPage++)
2007	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2008
2009	/* any memory associated with the range. */
2010	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2011	{
2012	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2013	{
2014	if (pRam->pavHCChunkHC[iChunk])
2015	{
2016	SSMR3PutU8(pSSM, 1); /* chunk present */
2017	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2018	}
2019	else
2020	SSMR3PutU8(pSSM, 0); /* no chunk present */
2021	}
2022	}
2023	else if (pRam->pvHC)
2024	{
2025	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
2026	if (VBOX_FAILURE(rc))
2027	{
2028	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2029	return rc;
2030	}
2031	}
2032	}
2033	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2034	}
2035
2036
2037	/**
2038	* Execute state load operation.
2039	*
2040	* @returns VBox status code.
2041	* @param pVM VM Handle.
2042	* @param pSSM SSM operation handle.
2043	* @param u32Version Data layout version.
2044	*/
2045	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2046	{
2047	/*
2048	* Validate version.
2049	*/
2050	if (u32Version != PGM_SAVED_STATE_VERSION)
2051	{
2052	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2053	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2054	}
2055
2056	/*
2057	* Call the reset function to make sure all the memory is cleared.
2058	*/
2059	PGMR3Reset(pVM);
2060
2061	/*
2062	* Load basic data (required / unaffected by relocation).
2063	*/
2064	PPGM pPGM = &pVM->pgm.s;
2065	#if 1
2066	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2067	#else
2068	uint32_t u;
2069	SSMR3GetU32(pSSM, &u);
2070	pPGM->fMappingsFixed = u;
2071	#endif
2072	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2073	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2074
2075	RTUINT cbRamSize;
2076	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2077	if (VBOX_FAILURE(rc))
2078	return rc;
2079	if (cbRamSize != pPGM->cbRamSize)
2080	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2081	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2082	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2083	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2084	RTUINT uGuestMode;
2085	SSMR3GetUInt(pSSM, &uGuestMode);
2086	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2087
2088	/* check separator. */
2089	uint32_t u32Sep;
2090	SSMR3GetU32(pSSM, &u32Sep);
2091	if (VBOX_FAILURE(rc))
2092	return rc;
2093	if (u32Sep != (uint32_t)~0)
2094	{
2095	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2096	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2097	}
2098
2099	/*
2100	* The guest mappings.
2101	*/
2102	uint32_t i = 0;
2103	for (;; i++)
2104	{
2105	/* Check the seqence number / separator. */
2106	rc = SSMR3GetU32(pSSM, &u32Sep);
2107	if (VBOX_FAILURE(rc))
2108	return rc;
2109	if (u32Sep == ~0U)
2110	break;
2111	if (u32Sep != i)
2112	{
2113	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2114	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2115	}
2116
2117	/* get the mapping details. */
2118	char szDesc[256];
2119	szDesc[0] = '\0';
2120	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2121	if (VBOX_FAILURE(rc))
2122	return rc;
2123	RTGCPTR GCPtr;
2124	SSMR3GetGCPtr(pSSM, &GCPtr);
2125	RTGCUINTPTR cPTs;
2126	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2127	if (VBOX_FAILURE(rc))
2128	return rc;
2129
2130	/* find matching range. */
2131	PPGMMAPPING pMapping;
2132	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2133	if ( pMapping->cPTs == cPTs
2134	&& !strcmp(pMapping->pszDesc, szDesc))
2135	break;
2136	if (!pMapping)
2137	{
2138	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2139	cPTs, szDesc, GCPtr));
2140	AssertFailed();
2141	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2142	}
2143
2144	/* relocate it. */
2145	if (pMapping->GCPtr != GCPtr)
2146	{
2147	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2148	#if HC_ARCH_BITS == 64
2149	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2150	#endif
2151	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2152	}
2153	else
2154	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2155	}
2156
2157	/*
2158	* Ram range flags and bits.
2159	*/
2160	i = 0;
2161	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2162	{
2163	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2164	/* Check the seqence number / separator. */
2165	rc = SSMR3GetU32(pSSM, &u32Sep);
2166	if (VBOX_FAILURE(rc))
2167	return rc;
2168	if (u32Sep == ~0U)
2169	break;
2170	if (u32Sep != i)
2171	{
2172	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2173	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2174	}
2175
2176	/* Get the range details. */
2177	RTGCPHYS GCPhys;
2178	SSMR3GetGCPhys(pSSM, &GCPhys);
2179	RTGCPHYS GCPhysLast;
2180	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2181	RTGCPHYS cb;
2182	SSMR3GetGCPhys(pSSM, &cb);
2183	uint8_t fHaveBits;
2184	rc = SSMR3GetU8(pSSM, &fHaveBits);
2185	if (VBOX_FAILURE(rc))
2186	return rc;
2187	if (fHaveBits & ~1)
2188	{
2189	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2190	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2191	}
2192
2193	/* Match it up with the current range. */
2194	if ( GCPhys != pRam->GCPhys
2195	\|\| GCPhysLast != pRam->GCPhysLast
2196	\|\| cb != pRam->cb
2197	\|\| fHaveBits != !!pRam->pvHC)
2198	{
2199	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2200	"State : %VGp-%VGp %VGp bytes %s\n",
2201	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2202	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2203	/*
2204	* If we're loading a state for debugging purpose, don't make a fuss if
2205	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2206	*/
2207	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2208	\|\| GCPhys < 8 * _1M)
2209	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2210
2211	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2212	while (cPages-- > 0)
2213	{
2214	uint16_t u16Ignore;
2215	SSMR3GetU16(pSSM, &u16Ignore);
2216	}
2217	continue;
2218	}
2219
2220	/* Flags. */
2221	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2222	for (unsigned iPage = 0; iPage < cPages; iPage++)
2223	{
2224	uint16_t u16 = 0;
2225	SSMR3GetU16(pSSM, &u16);
2226	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2227	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2228	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2229	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2230	}
2231
2232	/* any memory associated with the range. */
2233	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2234	{
2235	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2236	{
2237	uint8_t fValidChunk;
2238
2239	rc = SSMR3GetU8(pSSM, &fValidChunk);
2240	if (VBOX_FAILURE(rc))
2241	return rc;
2242	if (fValidChunk > 1)
2243	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2244
2245	if (fValidChunk)
2246	{
2247	if (!pRam->pavHCChunkHC[iChunk])
2248	{
2249	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2250	if (VBOX_FAILURE(rc))
2251	return rc;
2252	}
2253	Assert(pRam->pavHCChunkHC[iChunk]);
2254
2255	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2256	}
2257	/* else nothing to do */
2258	}
2259	}
2260	else if (pRam->pvHC)
2261	{
2262	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2263	if (VBOX_FAILURE(rc))
2264	{
2265	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2266	return rc;
2267	}
2268	}
2269	}
2270
2271	/*
2272	* We require a full resync now.
2273	*/
2274	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2275	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2276	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2277	pPGM->fPhysCacheFlushPending = true;
2278	pgmR3HandlerPhysicalUpdateAll(pVM);
2279
2280	/*
2281	* Change the paging mode.
2282	*/
2283	return PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2284	}
2285
2286
2287	/**
2288	* Show paging mode.
2289	*
2290	* @param pVM VM Handle.
2291	* @param pHlp The info helpers.
2292	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2293	*/
2294	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2295	{
2296	/* digest argument. */
2297	bool fGuest, fShadow, fHost;
2298	if (pszArgs)
2299	pszArgs = RTStrStripL(pszArgs);
2300	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2301	fShadow = fHost = fGuest = true;
2302	else
2303	{
2304	fShadow = fHost = fGuest = false;
2305	if (strstr(pszArgs, "guest"))
2306	fGuest = true;
2307	if (strstr(pszArgs, "shadow"))
2308	fShadow = true;
2309	if (strstr(pszArgs, "host"))
2310	fHost = true;
2311	}
2312
2313	/* print info. */
2314	if (fGuest)
2315	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2316	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2317	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2318	if (fShadow)
2319	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2320	if (fHost)
2321	{
2322	const char *psz;
2323	switch (pVM->pgm.s.enmHostMode)
2324	{
2325	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2326	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2327	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2328	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2329	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2330	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2331	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2332	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2333	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2334	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2335	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2336	default: psz = "unknown"; break;
2337	}
2338	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2339	}
2340	}
2341
2342
2343	/**
2344	* Dump registered MMIO ranges to the log.
2345	*
2346	* @param pVM VM Handle.
2347	* @param pHlp The info helpers.
2348	* @param pszArgs Arguments, ignored.
2349	*/
2350	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2351	{
2352	NOREF(pszArgs);
2353	pHlp->pfnPrintf(pHlp,
2354	"RAM ranges (pVM=%p)\n"
2355	"%.s %.s\n",
2356	pVM,
2357	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2358	sizeof(RTHCPTR) * 2, "pvHC ");
2359
2360	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2361	pHlp->pfnPrintf(pHlp,
2362	"%RGp-%RGp %RHv %s\n",
2363	pCur->GCPhys,
2364	pCur->GCPhysLast,
2365	pCur->pvHC,
2366	pCur->pszDesc);
2367	}
2368
2369	/**
2370	* Dump the page directory to the log.
2371	*
2372	* @param pVM VM Handle.
2373	* @param pHlp The info helpers.
2374	* @param pszArgs Arguments, ignored.
2375	*/
2376	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2377	{
2378	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2379	/* Big pages supported? */
2380	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2381
2382	/* Global pages supported? */
2383	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2384
2385	NOREF(pszArgs);
2386
2387	/*
2388	* Get page directory addresses.
2389	*/
2390	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2391	Assert(pPDSrc);
2392	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2393
2394	/*
2395	* Iterate the page directory.
2396	*/
2397	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2398	{
2399	X86PDE PdeSrc = pPDSrc->a[iPD];
2400	if (PdeSrc.n.u1Present)
2401	{
2402	if (PdeSrc.b.u1Size && fPSE)
2403	{
2404	pHlp->pfnPrintf(pHlp,
2405	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2406	iPD,
2407	PdeSrc.u & X86_PDE_PG_MASK,
2408	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2409	}
2410	else
2411	{
2412	pHlp->pfnPrintf(pHlp,
2413	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2414	iPD,
2415	PdeSrc.u & X86_PDE4M_PG_MASK,
2416	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2417	}
2418	}
2419	}
2420	}
2421
2422
2423	/**
2424	* Serivce a VMMCALLHOST_PGM_LOCK call.
2425	*
2426	* @returns VBox status code.
2427	* @param pVM The VM handle.
2428	*/
2429	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2430	{
2431	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2432	AssertRC(rc);
2433	return rc;
2434	}
2435
2436
2437	/**
2438	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2439	*
2440	* @returns PGM_TYPE_*.
2441	* @param pgmMode The mode value to convert.
2442	*/
2443	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2444	{
2445	switch (pgmMode)
2446	{
2447	case PGMMODE_REAL: return PGM_TYPE_REAL;
2448	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2449	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2450	case PGMMODE_PAE:
2451	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2452	case PGMMODE_AMD64:
2453	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2454	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2455	default:
2456	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2457	}
2458	}
2459
2460
2461	/**
2462	* Gets the index into the paging mode data array of a SHW+GST mode.
2463	*
2464	* @returns PGM::paPagingData index.
2465	* @param uShwType The shadow paging mode type.
2466	* @param uGstType The guest paging mode type.
2467	*/
2468	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2469	{
2470	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_NESTED);
2471	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2472	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2473	+ (uGstType - PGM_TYPE_REAL);
2474	}
2475
2476
2477	/**
2478	* Gets the index into the paging mode data array of a SHW+GST mode.
2479	*
2480	* @returns PGM::paPagingData index.
2481	* @param enmShw The shadow paging mode.
2482	* @param enmGst The guest paging mode.
2483	*/
2484	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2485	{
2486	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2487	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2488	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2489	}
2490
2491
2492	/**
2493	* Calculates the max data index.
2494	* @returns The number of entries in the paging data array.
2495	*/
2496	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2497	{
2498	return pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64) + 1;
2499	}
2500
2501
2502	/**
2503	* Initializes the paging mode data kept in PGM::paModeData.
2504	*
2505	* @param pVM The VM handle.
2506	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2507	* This is used early in the init process to avoid trouble with PDM
2508	* not being initialized yet.
2509	*/
2510	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2511	{
2512	PPGMMODEDATA pModeData;
2513	int rc;
2514
2515	/*
2516	* Allocate the array on the first call.
2517	*/
2518	if (!pVM->pgm.s.paModeData)
2519	{
2520	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2521	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2522	}
2523
2524	/*
2525	* Initialize the array entries.
2526	*/
2527	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2528	pModeData->uShwType = PGM_TYPE_32BIT;
2529	pModeData->uGstType = PGM_TYPE_REAL;
2530	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2531	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2532	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2533
2534	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2535	pModeData->uShwType = PGM_TYPE_32BIT;
2536	pModeData->uGstType = PGM_TYPE_PROT;
2537	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2538	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2539	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2540
2541	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2542	pModeData->uShwType = PGM_TYPE_32BIT;
2543	pModeData->uGstType = PGM_TYPE_32BIT;
2544	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2545	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2546	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2547
2548	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2549	pModeData->uShwType = PGM_TYPE_PAE;
2550	pModeData->uGstType = PGM_TYPE_REAL;
2551	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2552	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2553	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2554
2555	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2556	pModeData->uShwType = PGM_TYPE_PAE;
2557	pModeData->uGstType = PGM_TYPE_PROT;
2558	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2559	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2560	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2561
2562	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2563	pModeData->uShwType = PGM_TYPE_PAE;
2564	pModeData->uGstType = PGM_TYPE_32BIT;
2565	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2566	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2567	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2568
2569	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2570	pModeData->uShwType = PGM_TYPE_PAE;
2571	pModeData->uGstType = PGM_TYPE_PAE;
2572	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2573	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2574	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2575
2576	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2577	pModeData->uShwType = PGM_TYPE_AMD64;
2578	pModeData->uGstType = PGM_TYPE_AMD64;
2579	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2580	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2581	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2582
2583	/* The nested paging mode. */
2584	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2585	pModeData->uShwType = PGM_TYPE_NESTED;
2586	pModeData->uGstType = PGM_TYPE_REAL;
2587	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2588	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2589
2590	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2591	pModeData->uShwType = PGM_TYPE_NESTED;
2592	pModeData->uGstType = PGM_TYPE_PROT;
2593	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2594	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2595
2596	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2597	pModeData->uShwType = PGM_TYPE_NESTED;
2598	pModeData->uGstType = PGM_TYPE_32BIT;
2599	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2600	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2601
2602	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2603	pModeData->uShwType = PGM_TYPE_NESTED;
2604	pModeData->uGstType = PGM_TYPE_PAE;
2605	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2606	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2607
2608	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2609	pModeData->uShwType = PGM_TYPE_NESTED;
2610	pModeData->uGstType = PGM_TYPE_AMD64;
2611	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2612	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2613
2614	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2615	switch(pVM->pgm.s.enmHostMode)
2616	{
2617	case SUPPAGINGMODE_32_BIT:
2618	case SUPPAGINGMODE_32_BIT_GLOBAL:
2619	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2620	{
2621	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2622	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2623	}
2624	break;
2625
2626	case SUPPAGINGMODE_PAE:
2627	case SUPPAGINGMODE_PAE_NX:
2628	case SUPPAGINGMODE_PAE_GLOBAL:
2629	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2630	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2631	{
2632	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2633	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2634	}
2635	break;
2636
2637	case SUPPAGINGMODE_AMD64:
2638	case SUPPAGINGMODE_AMD64_GLOBAL:
2639	case SUPPAGINGMODE_AMD64_NX:
2640	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2641	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2642	{
2643	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2644	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2645	}
2646	break;
2647	default:
2648	AssertFailed();
2649	break;
2650	}
2651	return VINF_SUCCESS;
2652	}
2653
2654
2655	/**
2656	* Switch to different (or relocated in the relocate case) mode data.
2657	*
2658	* @param pVM The VM handle.
2659	* @param enmShw The the shadow paging mode.
2660	* @param enmGst The the guest paging mode.
2661	*/
2662	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2663	{
2664	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2665
2666	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2667	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2668
2669	/* shadow */
2670	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2671	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2672	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2673	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2674	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2675
2676	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2677	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2678
2679	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2680	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2681
2682
2683	/* guest */
2684	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2685	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2686	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2687	Assert(pVM->pgm.s.pfnR3GstGetPage);
2688	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2689	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2690	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2691	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2692	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2693	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2694	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2695	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2696	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2697	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2698
2699	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2700	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2701	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2702	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2703	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2704	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2705	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2706	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2707	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2708
2709	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2710	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2711	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2712	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2713	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2714	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2715	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2716	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2717	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2718
2719
2720	/* both */
2721	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2722	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2723	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2724	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2725	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2726	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2727	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2728	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2729	#ifdef VBOX_STRICT
2730	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2731	#endif
2732
2733	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2734	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2735	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2736	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2737	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2738	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2739	#ifdef VBOX_STRICT
2740	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2741	#endif
2742
2743	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2744	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2745	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2746	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2747	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2748	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2749	#ifdef VBOX_STRICT
2750	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2751	#endif
2752	}
2753
2754
2755	#ifdef DEBUG_bird
2756	#include <stdlib.h> /* getenv() remove me! */
2757	#endif
2758
2759	/**
2760	* Calculates the shadow paging mode.
2761	*
2762	* @returns The shadow paging mode.
2763	* @param pVM VM handle.
2764	* @param enmGuestMode The guest mode.
2765	* @param enmHostMode The host mode.
2766	* @param enmShadowMode The current shadow mode.
2767	* @param penmSwitcher Where to store the switcher to use.
2768	* VMMSWITCHER_INVALID means no change.
2769	*/
2770	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2771	{
2772	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2773	switch (enmGuestMode)
2774	{
2775	/*
2776	* When switching to real or protected mode we don't change
2777	* anything since it's likely that we'll switch back pretty soon.
2778	*
2779	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2780	* and is supposed to determine which shadow paging and switcher to
2781	* use during init.
2782	*/
2783	case PGMMODE_REAL:
2784	case PGMMODE_PROTECTED:
2785	if ( enmShadowMode != PGMMODE_INVALID
2786	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2787	break; /* (no change) */
2788
2789	switch (enmHostMode)
2790	{
2791	case SUPPAGINGMODE_32_BIT:
2792	case SUPPAGINGMODE_32_BIT_GLOBAL:
2793	enmShadowMode = PGMMODE_32_BIT;
2794	enmSwitcher = VMMSWITCHER_32_TO_32;
2795	break;
2796
2797	case SUPPAGINGMODE_PAE:
2798	case SUPPAGINGMODE_PAE_NX:
2799	case SUPPAGINGMODE_PAE_GLOBAL:
2800	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2801	enmShadowMode = PGMMODE_PAE;
2802	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2803	#ifdef DEBUG_bird
2804	if (getenv("VBOX_32BIT"))
2805	{
2806	enmShadowMode = PGMMODE_32_BIT;
2807	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2808	}
2809	#endif
2810	break;
2811
2812	case SUPPAGINGMODE_AMD64:
2813	case SUPPAGINGMODE_AMD64_GLOBAL:
2814	case SUPPAGINGMODE_AMD64_NX:
2815	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2816	enmShadowMode = PGMMODE_PAE;
2817	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2818	break;
2819
2820	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2821	}
2822	break;
2823
2824	case PGMMODE_32_BIT:
2825	switch (enmHostMode)
2826	{
2827	case SUPPAGINGMODE_32_BIT:
2828	case SUPPAGINGMODE_32_BIT_GLOBAL:
2829	enmShadowMode = PGMMODE_32_BIT;
2830	enmSwitcher = VMMSWITCHER_32_TO_32;
2831	break;
2832
2833	case SUPPAGINGMODE_PAE:
2834	case SUPPAGINGMODE_PAE_NX:
2835	case SUPPAGINGMODE_PAE_GLOBAL:
2836	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2837	enmShadowMode = PGMMODE_PAE;
2838	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2839	#ifdef DEBUG_bird
2840	if (getenv("VBOX_32BIT"))
2841	{
2842	enmShadowMode = PGMMODE_32_BIT;
2843	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2844	}
2845	#endif
2846	break;
2847
2848	case SUPPAGINGMODE_AMD64:
2849	case SUPPAGINGMODE_AMD64_GLOBAL:
2850	case SUPPAGINGMODE_AMD64_NX:
2851	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2852	enmShadowMode = PGMMODE_PAE;
2853	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2854	break;
2855
2856	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2857	}
2858	break;
2859
2860	case PGMMODE_PAE:
2861	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2862	switch (enmHostMode)
2863	{
2864	case SUPPAGINGMODE_32_BIT:
2865	case SUPPAGINGMODE_32_BIT_GLOBAL:
2866	enmShadowMode = PGMMODE_PAE;
2867	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2868	break;
2869
2870	case SUPPAGINGMODE_PAE:
2871	case SUPPAGINGMODE_PAE_NX:
2872	case SUPPAGINGMODE_PAE_GLOBAL:
2873	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2874	enmShadowMode = PGMMODE_PAE;
2875	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2876	break;
2877
2878	case SUPPAGINGMODE_AMD64:
2879	case SUPPAGINGMODE_AMD64_GLOBAL:
2880	case SUPPAGINGMODE_AMD64_NX:
2881	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2882	enmShadowMode = PGMMODE_PAE;
2883	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2884	break;
2885
2886	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2887	}
2888	break;
2889
2890	case PGMMODE_AMD64:
2891	case PGMMODE_AMD64_NX:
2892	switch (enmHostMode)
2893	{
2894	case SUPPAGINGMODE_32_BIT:
2895	case SUPPAGINGMODE_32_BIT_GLOBAL:
2896	enmShadowMode = PGMMODE_PAE;
2897	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2898	break;
2899
2900	case SUPPAGINGMODE_PAE:
2901	case SUPPAGINGMODE_PAE_NX:
2902	case SUPPAGINGMODE_PAE_GLOBAL:
2903	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2904	enmShadowMode = PGMMODE_PAE;
2905	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2906	break;
2907
2908	case SUPPAGINGMODE_AMD64:
2909	case SUPPAGINGMODE_AMD64_GLOBAL:
2910	case SUPPAGINGMODE_AMD64_NX:
2911	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2912	enmShadowMode = PGMMODE_AMD64;
2913	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2914	break;
2915
2916	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2917	}
2918	break;
2919
2920
2921	default:
2922	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2923	return PGMMODE_INVALID;
2924	}
2925	/* Override the shadow mode is nested paging is active. */
2926	if (HWACCMIsNestedPagingActive(pVM))
2927	enmShadowMode = PGMMODE_NESTED;
2928
2929	*penmSwitcher = enmSwitcher;
2930	return enmShadowMode;
2931	}
2932
2933	#ifdef LOG_ENABLED
2934	/**
2935	* Return the string corresponding to the guest mode
2936	*
2937	* @returns string
2938	* @param enmGuestMode The guest mode.
2939	*/
2940	const char *pgmr3GuestModeString(PGMMODE enmGuestMode)
2941	{
2942	switch(enmGuestMode)
2943	{
2944	case PGMMODE_REAL:
2945	return "Real mode";
2946
2947	case PGMMODE_PROTECTED:
2948	return "Protected mode without paging";
2949
2950	case PGMMODE_32_BIT:
2951	return "32 bits protected mode";
2952
2953	case PGMMODE_PAE:
2954	return "PAE";
2955
2956	case PGMMODE_PAE_NX:
2957	return "PAE + NX";
2958
2959	case PGMMODE_AMD64:
2960	return "AMD64";
2961
2962	case PGMMODE_AMD64_NX:
2963	return "AMD64 + NX";
2964
2965	default:
2966	return "Unknown";
2967	}
2968	}
2969	#endif
2970
2971	/**
2972	* Performs the actual mode change.
2973	* This is called by PGMChangeMode and pgmR3InitPaging().
2974	*
2975	* @returns VBox status code.
2976	* @param pVM VM handle.
2977	* @param enmGuestMode The new guest mode. This is assumed to be different from
2978	* the current mode.
2979	*/
2980	PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2981	{
2982	LogFlow(("PGMR3ChangeMode: Guest mode: %s -> %s\n", pgmr3GuestModeString(pVM->pgm.s.enmGuestMode), pgmr3GuestModeString(enmGuestMode)));
2983	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2984
2985	/*
2986	* Calc the shadow mode and switcher.
2987	*/
2988	VMMSWITCHER enmSwitcher;
2989	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2990	if (enmSwitcher != VMMSWITCHER_INVALID)
2991	{
2992	/*
2993	* Select new switcher.
2994	*/
2995	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2996	if (VBOX_FAILURE(rc))
2997	{
2998	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2999	return rc;
3000	}
3001	}
3002
3003	/*
3004	* Exit old mode(s).
3005	*/
3006	/* shadow */
3007	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3008	{
3009	LogFlow(("PGMR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
3010	if (PGM_SHW_PFN(Exit, pVM))
3011	{
3012	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3013	if (VBOX_FAILURE(rc))
3014	{
3015	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3016	return rc;
3017	}
3018	}
3019
3020	}
3021
3022	/* guest */
3023	if (PGM_GST_PFN(Exit, pVM))
3024	{
3025	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3026	if (VBOX_FAILURE(rc))
3027	{
3028	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3029	return rc;
3030	}
3031	}
3032
3033	/*
3034	* Load new paging mode data.
3035	*/
3036	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3037
3038	/*
3039	* Enter new shadow mode (if changed).
3040	*/
3041	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3042	{
3043	int rc;
3044	pVM->pgm.s.enmShadowMode = enmShadowMode;
3045	switch (enmShadowMode)
3046	{
3047	case PGMMODE_32_BIT:
3048	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3049	break;
3050	case PGMMODE_PAE:
3051	case PGMMODE_PAE_NX:
3052	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3053	break;
3054	case PGMMODE_AMD64:
3055	case PGMMODE_AMD64_NX:
3056	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3057	break;
3058	case PGMMODE_NESTED:
3059	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3060	break;
3061	case PGMMODE_REAL:
3062	case PGMMODE_PROTECTED:
3063	default:
3064	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3065	return VERR_INTERNAL_ERROR;
3066	}
3067	if (VBOX_FAILURE(rc))
3068	{
3069	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3070	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3071	return rc;
3072	}
3073	}
3074
3075	/*
3076	* Enter the new guest and shadow+guest modes.
3077	*/
3078	int rc = -1;
3079	int rc2 = -1;
3080	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3081	pVM->pgm.s.enmGuestMode = enmGuestMode;
3082	switch (enmGuestMode)
3083	{
3084	case PGMMODE_REAL:
3085	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3086	switch (pVM->pgm.s.enmShadowMode)
3087	{
3088	case PGMMODE_32_BIT:
3089	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3090	break;
3091	case PGMMODE_PAE:
3092	case PGMMODE_PAE_NX:
3093	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3094	break;
3095	case PGMMODE_NESTED:
3096	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3097	break;
3098	case PGMMODE_AMD64:
3099	case PGMMODE_AMD64_NX:
3100	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3101	default: AssertFailed(); break;
3102	}
3103	break;
3104
3105	case PGMMODE_PROTECTED:
3106	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3107	switch (pVM->pgm.s.enmShadowMode)
3108	{
3109	case PGMMODE_32_BIT:
3110	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3111	break;
3112	case PGMMODE_PAE:
3113	case PGMMODE_PAE_NX:
3114	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3115	break;
3116	case PGMMODE_NESTED:
3117	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3118	break;
3119	case PGMMODE_AMD64:
3120	case PGMMODE_AMD64_NX:
3121	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3122	default: AssertFailed(); break;
3123	}
3124	break;
3125
3126	case PGMMODE_32_BIT:
3127	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3128	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3129	switch (pVM->pgm.s.enmShadowMode)
3130	{
3131	case PGMMODE_32_BIT:
3132	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3133	break;
3134	case PGMMODE_PAE:
3135	case PGMMODE_PAE_NX:
3136	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3137	break;
3138	case PGMMODE_NESTED:
3139	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3140	break;
3141	case PGMMODE_AMD64:
3142	case PGMMODE_AMD64_NX:
3143	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3144	default: AssertFailed(); break;
3145	}
3146	break;
3147
3148	//case PGMMODE_PAE_NX:
3149	case PGMMODE_PAE:
3150	{
3151	uint32_t u32Dummy, u32Features;
3152
3153	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3154	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3155	{
3156	/* Pause first, then inform Main. */
3157	rc = VMR3SuspendNoSave(pVM);
3158	AssertRC(rc);
3159
3160	VMSetRuntimeError(pVM, true, "PAEmode",
3161	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage."));
3162	/* we must return TRUE here otherwise the recompiler will assert */
3163	return VINF_SUCCESS;
3164	}
3165	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3166	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3167	switch (pVM->pgm.s.enmShadowMode)
3168	{
3169	case PGMMODE_PAE:
3170	case PGMMODE_PAE_NX:
3171	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3172	break;
3173	case PGMMODE_NESTED:
3174	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3175	break;
3176	case PGMMODE_32_BIT:
3177	case PGMMODE_AMD64:
3178	case PGMMODE_AMD64_NX:
3179	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3180	default: AssertFailed(); break;
3181	}
3182	break;
3183	}
3184
3185	case PGMMODE_AMD64_NX:
3186	case PGMMODE_AMD64:
3187	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3188	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3189	switch (pVM->pgm.s.enmShadowMode)
3190	{
3191	case PGMMODE_AMD64:
3192	case PGMMODE_AMD64_NX:
3193	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3194	break;
3195	case PGMMODE_NESTED:
3196	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3197	break;
3198	case PGMMODE_32_BIT:
3199	case PGMMODE_PAE:
3200	case PGMMODE_PAE_NX:
3201	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3202	default: AssertFailed(); break;
3203	}
3204	break;
3205
3206	default:
3207	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3208	rc = VERR_NOT_IMPLEMENTED;
3209	break;
3210	}
3211
3212	/* status codes. */
3213	AssertRC(rc);
3214	AssertRC(rc2);
3215	if (VBOX_SUCCESS(rc))
3216	{
3217	rc = rc2;
3218	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3219	rc = VINF_SUCCESS;
3220	}
3221
3222	/*
3223	* Notify SELM so it can update the TSSes with correct CR3s.
3224	*/
3225	SELMR3PagingModeChanged(pVM);
3226
3227	/* Notify HWACCM as well. */
3228	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3229	return rc;
3230	}
3231
3232
3233	/**
3234	* Dumps a PAE shadow page table.
3235	*
3236	* @returns VBox status code (VINF_SUCCESS).
3237	* @param pVM The VM handle.
3238	* @param pPT Pointer to the page table.
3239	* @param u64Address The virtual address of the page table starts.
3240	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3241	* @param cMaxDepth The maxium depth.
3242	* @param pHlp Pointer to the output functions.
3243	*/
3244	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3245	{
3246	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3247	{
3248	X86PTEPAE Pte = pPT->a[i];
3249	if (Pte.n.u1Present)
3250	{
3251	pHlp->pfnPrintf(pHlp,
3252	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3253	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3254	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3255	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3256	Pte.n.u1Write ? 'W' : 'R',
3257	Pte.n.u1User ? 'U' : 'S',
3258	Pte.n.u1Accessed ? 'A' : '-',
3259	Pte.n.u1Dirty ? 'D' : '-',
3260	Pte.n.u1Global ? 'G' : '-',
3261	Pte.n.u1WriteThru ? "WT" : "--",
3262	Pte.n.u1CacheDisable? "CD" : "--",
3263	Pte.n.u1PAT ? "AT" : "--",
3264	Pte.n.u1NoExecute ? "NX" : "--",
3265	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3266	Pte.u & RT_BIT(10) ? '1' : '0',
3267	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3268	Pte.u & X86_PTE_PAE_PG_MASK);
3269	}
3270	}
3271	return VINF_SUCCESS;
3272	}
3273
3274
3275	/**
3276	* Dumps a PAE shadow page directory table.
3277	*
3278	* @returns VBox status code (VINF_SUCCESS).
3279	* @param pVM The VM handle.
3280	* @param HCPhys The physical address of the page directory table.
3281	* @param u64Address The virtual address of the page table starts.
3282	* @param cr4 The CR4, PSE is currently used.
3283	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3284	* @param cMaxDepth The maxium depth.
3285	* @param pHlp Pointer to the output functions.
3286	*/
3287	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3288	{
3289	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3290	if (!pPD)
3291	{
3292	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3293	fLongMode ? 16 : 8, u64Address, HCPhys);
3294	return VERR_INVALID_PARAMETER;
3295	}
3296	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3297
3298	int rc = VINF_SUCCESS;
3299	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3300	{
3301	X86PDEPAE Pde = pPD->a[i];
3302	if (Pde.n.u1Present)
3303	{
3304	if (fBigPagesSupported && Pde.b.u1Size)
3305	pHlp->pfnPrintf(pHlp,
3306	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3307	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3308	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3309	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3310	Pde.b.u1Write ? 'W' : 'R',
3311	Pde.b.u1User ? 'U' : 'S',
3312	Pde.b.u1Accessed ? 'A' : '-',
3313	Pde.b.u1Dirty ? 'D' : '-',
3314	Pde.b.u1Global ? 'G' : '-',
3315	Pde.b.u1WriteThru ? "WT" : "--",
3316	Pde.b.u1CacheDisable? "CD" : "--",
3317	Pde.b.u1PAT ? "AT" : "--",
3318	Pde.b.u1NoExecute ? "NX" : "--",
3319	Pde.u & RT_BIT_64(9) ? '1' : '0',
3320	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3321	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3322	Pde.u & X86_PDE_PAE_PG_MASK);
3323	else
3324	{
3325	pHlp->pfnPrintf(pHlp,
3326	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3327	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3328	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3329	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3330	Pde.n.u1Write ? 'W' : 'R',
3331	Pde.n.u1User ? 'U' : 'S',
3332	Pde.n.u1Accessed ? 'A' : '-',
3333	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3334	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3335	Pde.n.u1WriteThru ? "WT" : "--",
3336	Pde.n.u1CacheDisable? "CD" : "--",
3337	Pde.n.u1NoExecute ? "NX" : "--",
3338	Pde.u & RT_BIT_64(9) ? '1' : '0',
3339	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3340	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3341	Pde.u & X86_PDE_PAE_PG_MASK);
3342	if (cMaxDepth >= 1)
3343	{
3344	/** @todo what about using the page pool for mapping PTs? */
3345	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3346	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3347	PX86PTPAE pPT = NULL;
3348	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3349	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3350	else
3351	{
3352	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3353	{
3354	uint64_t off = u64AddressPT - pMap->GCPtr;
3355	if (off < pMap->cb)
3356	{
3357	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3358	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3359	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3360	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3361	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3362	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3363	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3364	}
3365	}
3366	}
3367	int rc2 = VERR_INVALID_PARAMETER;
3368	if (pPT)
3369	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3370	else
3371	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3372	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3373	if (rc2 < rc && VBOX_SUCCESS(rc))
3374	rc = rc2;
3375	}
3376	}
3377	}
3378	}
3379	return rc;
3380	}
3381
3382
3383	/**
3384	* Dumps a PAE shadow page directory pointer table.
3385	*
3386	* @returns VBox status code (VINF_SUCCESS).
3387	* @param pVM The VM handle.
3388	* @param HCPhys The physical address of the page directory pointer table.
3389	* @param u64Address The virtual address of the page table starts.
3390	* @param cr4 The CR4, PSE is currently used.
3391	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3392	* @param cMaxDepth The maxium depth.
3393	* @param pHlp Pointer to the output functions.
3394	*/
3395	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3396	{
3397	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3398	if (!pPDPT)
3399	{
3400	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3401	fLongMode ? 16 : 8, u64Address, HCPhys);
3402	return VERR_INVALID_PARAMETER;
3403	}
3404
3405	int rc = VINF_SUCCESS;
3406	const unsigned c = fLongMode ? ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3407	for (unsigned i = 0; i < c; i++)
3408	{
3409	X86PDPE Pdpe = pPDPT->a[i];
3410	if (Pdpe.n.u1Present)
3411	{
3412	if (fLongMode)
3413	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3414	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3415	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3416	Pdpe.lm.u1Write ? 'W' : 'R',
3417	Pdpe.lm.u1User ? 'U' : 'S',
3418	Pdpe.lm.u1Accessed ? 'A' : '-',
3419	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3420	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3421	Pdpe.lm.u1WriteThru ? "WT" : "--",
3422	Pdpe.lm.u1CacheDisable? "CD" : "--",
3423	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3424	Pdpe.lm.u1NoExecute ? "NX" : "--",
3425	Pdpe.u & RT_BIT(9) ? '1' : '0',
3426	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3427	Pdpe.u & RT_BIT(11) ? '1' : '0',
3428	Pdpe.u & X86_PDPE_PG_MASK);
3429	else
3430	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3431	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3432	i << X86_PDPT_SHIFT,
3433	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3434	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3435	Pdpe.n.u1WriteThru ? "WT" : "--",
3436	Pdpe.n.u1CacheDisable? "CD" : "--",
3437	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3438	Pdpe.u & RT_BIT(9) ? '1' : '0',
3439	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3440	Pdpe.u & RT_BIT(11) ? '1' : '0',
3441	Pdpe.u & X86_PDPE_PG_MASK);
3442	if (cMaxDepth >= 1)
3443	{
3444	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3445	cr4, fLongMode, cMaxDepth - 1, pHlp);
3446	if (rc2 < rc && VBOX_SUCCESS(rc))
3447	rc = rc2;
3448	}
3449	}
3450	}
3451	return rc;
3452	}
3453
3454
3455	/**
3456	* Dumps a 32-bit shadow page table.
3457	*
3458	* @returns VBox status code (VINF_SUCCESS).
3459	* @param pVM The VM handle.
3460	* @param HCPhys The physical address of the table.
3461	* @param cr4 The CR4, PSE is currently used.
3462	* @param cMaxDepth The maxium depth.
3463	* @param pHlp Pointer to the output functions.
3464	*/
3465	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3466	{
3467	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3468	if (!pPML4)
3469	{
3470	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3471	return VERR_INVALID_PARAMETER;
3472	}
3473
3474	int rc = VINF_SUCCESS;
3475	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3476	{
3477	X86PML4E Pml4e = pPML4->a[i];
3478	if (Pml4e.n.u1Present)
3479	{
3480	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3481	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3482	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3483	u64Address,
3484	Pml4e.n.u1Write ? 'W' : 'R',
3485	Pml4e.n.u1User ? 'U' : 'S',
3486	Pml4e.n.u1Accessed ? 'A' : '-',
3487	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3488	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3489	Pml4e.n.u1WriteThru ? "WT" : "--",
3490	Pml4e.n.u1CacheDisable? "CD" : "--",
3491	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3492	Pml4e.n.u1NoExecute ? "NX" : "--",
3493	Pml4e.u & RT_BIT(9) ? '1' : '0',
3494	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3495	Pml4e.u & RT_BIT(11) ? '1' : '0',
3496	Pml4e.u & X86_PML4E_PG_MASK);
3497
3498	if (cMaxDepth >= 1)
3499	{
3500	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3501	if (rc2 < rc && VBOX_SUCCESS(rc))
3502	rc = rc2;
3503	}
3504	}
3505	}
3506	return rc;
3507	}
3508
3509
3510	/**
3511	* Dumps a 32-bit shadow page table.
3512	*
3513	* @returns VBox status code (VINF_SUCCESS).
3514	* @param pVM The VM handle.
3515	* @param pPT Pointer to the page table.
3516	* @param u32Address The virtual address this table starts at.
3517	* @param pHlp Pointer to the output functions.
3518	*/
3519	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3520	{
3521	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3522	{
3523	X86PTE Pte = pPT->a[i];
3524	if (Pte.n.u1Present)
3525	{
3526	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3527	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3528	u32Address + (i << X86_PT_SHIFT),
3529	Pte.n.u1Write ? 'W' : 'R',
3530	Pte.n.u1User ? 'U' : 'S',
3531	Pte.n.u1Accessed ? 'A' : '-',
3532	Pte.n.u1Dirty ? 'D' : '-',
3533	Pte.n.u1Global ? 'G' : '-',
3534	Pte.n.u1WriteThru ? "WT" : "--",
3535	Pte.n.u1CacheDisable? "CD" : "--",
3536	Pte.n.u1PAT ? "AT" : "--",
3537	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3538	Pte.u & RT_BIT(10) ? '1' : '0',
3539	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3540	Pte.u & X86_PDE_PG_MASK);
3541	}
3542	}
3543	return VINF_SUCCESS;
3544	}
3545
3546
3547	/**
3548	* Dumps a 32-bit shadow page directory and page tables.
3549	*
3550	* @returns VBox status code (VINF_SUCCESS).
3551	* @param pVM The VM handle.
3552	* @param cr3 The root of the hierarchy.
3553	* @param cr4 The CR4, PSE is currently used.
3554	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3555	* @param pHlp Pointer to the output functions.
3556	*/
3557	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3558	{
3559	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3560	if (!pPD)
3561	{
3562	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3563	return VERR_INVALID_PARAMETER;
3564	}
3565
3566	int rc = VINF_SUCCESS;
3567	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3568	{
3569	X86PDE Pde = pPD->a[i];
3570	if (Pde.n.u1Present)
3571	{
3572	const uint32_t u32Address = i << X86_PD_SHIFT;
3573	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3574	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3575	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3576	u32Address,
3577	Pde.b.u1Write ? 'W' : 'R',
3578	Pde.b.u1User ? 'U' : 'S',
3579	Pde.b.u1Accessed ? 'A' : '-',
3580	Pde.b.u1Dirty ? 'D' : '-',
3581	Pde.b.u1Global ? 'G' : '-',
3582	Pde.b.u1WriteThru ? "WT" : "--",
3583	Pde.b.u1CacheDisable? "CD" : "--",
3584	Pde.b.u1PAT ? "AT" : "--",
3585	Pde.u & RT_BIT_64(9) ? '1' : '0',
3586	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3587	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3588	Pde.u & X86_PDE4M_PG_MASK);
3589	else
3590	{
3591	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3592	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3593	u32Address,
3594	Pde.n.u1Write ? 'W' : 'R',
3595	Pde.n.u1User ? 'U' : 'S',
3596	Pde.n.u1Accessed ? 'A' : '-',
3597	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3598	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3599	Pde.n.u1WriteThru ? "WT" : "--",
3600	Pde.n.u1CacheDisable? "CD" : "--",
3601	Pde.u & RT_BIT_64(9) ? '1' : '0',
3602	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3603	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3604	Pde.u & X86_PDE_PG_MASK);
3605	if (cMaxDepth >= 1)
3606	{
3607	/** @todo what about using the page pool for mapping PTs? */
3608	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3609	PX86PT pPT = NULL;
3610	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3611	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3612	else
3613	{
3614	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3615	if (u32Address - pMap->GCPtr < pMap->cb)
3616	{
3617	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3618	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3619	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3620	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3621	pPT = pMap->aPTs[iPDE].pPTR3;
3622	}
3623	}
3624	int rc2 = VERR_INVALID_PARAMETER;
3625	if (pPT)
3626	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3627	else
3628	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3629	if (rc2 < rc && VBOX_SUCCESS(rc))
3630	rc = rc2;
3631	}
3632	}
3633	}
3634	}
3635
3636	return rc;
3637	}
3638
3639
3640	/**
3641	* Dumps a 32-bit shadow page table.
3642	*
3643	* @returns VBox status code (VINF_SUCCESS).
3644	* @param pVM The VM handle.
3645	* @param pPT Pointer to the page table.
3646	* @param u32Address The virtual address this table starts at.
3647	* @param PhysSearch Address to search for.
3648	*/
3649	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3650	{
3651	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3652	{
3653	X86PTE Pte = pPT->a[i];
3654	if (Pte.n.u1Present)
3655	{
3656	Log(( /P R S A D G WT CD AT NX 4M a m d /
3657	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3658	u32Address + (i << X86_PT_SHIFT),
3659	Pte.n.u1Write ? 'W' : 'R',
3660	Pte.n.u1User ? 'U' : 'S',
3661	Pte.n.u1Accessed ? 'A' : '-',
3662	Pte.n.u1Dirty ? 'D' : '-',
3663	Pte.n.u1Global ? 'G' : '-',
3664	Pte.n.u1WriteThru ? "WT" : "--",
3665	Pte.n.u1CacheDisable? "CD" : "--",
3666	Pte.n.u1PAT ? "AT" : "--",
3667	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3668	Pte.u & RT_BIT(10) ? '1' : '0',
3669	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3670	Pte.u & X86_PDE_PG_MASK));
3671
3672	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3673	{
3674	uint64_t fPageShw = 0;
3675	RTHCPHYS pPhysHC = 0;
3676
3677	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3678	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3679	}
3680	}
3681	}
3682	return VINF_SUCCESS;
3683	}
3684
3685
3686	/**
3687	* Dumps a 32-bit guest page directory and page tables.
3688	*
3689	* @returns VBox status code (VINF_SUCCESS).
3690	* @param pVM The VM handle.
3691	* @param cr3 The root of the hierarchy.
3692	* @param cr4 The CR4, PSE is currently used.
3693	* @param PhysSearch Address to search for.
3694	*/
3695	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3696	{
3697	bool fLongMode = false;
3698	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3699	PX86PD pPD = 0;
3700
3701	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3702	if (VBOX_FAILURE(rc) \|\| !pPD)
3703	{
3704	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3705	return VERR_INVALID_PARAMETER;
3706	}
3707
3708	Log(("cr3=%08x cr4=%08x%s\n"
3709	"%-*s P - Present\n"
3710	"%-*s \| R/W - Read (0) / Write (1)\n"
3711	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3712	"%-*s \| \| \| A - Accessed\n"
3713	"%-*s \| \| \| \| D - Dirty\n"
3714	"%-*s \| \| \| \| \| G - Global\n"
3715	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3716	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3717	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3718	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3719	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3720	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3721	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3722	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3723	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3724	- W U - - - -- -- -- -- -- 010 */
3725	, cr3, cr4, fLongMode ? " Long Mode" : "",
3726	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3727	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3728
3729	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3730	{
3731	X86PDE Pde = pPD->a[i];
3732	if (Pde.n.u1Present)
3733	{
3734	const uint32_t u32Address = i << X86_PD_SHIFT;
3735
3736	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3737	Log(( /P R S A D G WT CD AT NX 4M a m d /
3738	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3739	u32Address,
3740	Pde.b.u1Write ? 'W' : 'R',
3741	Pde.b.u1User ? 'U' : 'S',
3742	Pde.b.u1Accessed ? 'A' : '-',
3743	Pde.b.u1Dirty ? 'D' : '-',
3744	Pde.b.u1Global ? 'G' : '-',
3745	Pde.b.u1WriteThru ? "WT" : "--",
3746	Pde.b.u1CacheDisable? "CD" : "--",
3747	Pde.b.u1PAT ? "AT" : "--",
3748	Pde.u & RT_BIT(9) ? '1' : '0',
3749	Pde.u & RT_BIT(10) ? '1' : '0',
3750	Pde.u & RT_BIT(11) ? '1' : '0',
3751	Pde.u & X86_PDE4M_PG_MASK));
3752	/** @todo PhysSearch */
3753	else
3754	{
3755	Log(( /P R S A D G WT CD AT NX 4M a m d /
3756	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3757	u32Address,
3758	Pde.n.u1Write ? 'W' : 'R',
3759	Pde.n.u1User ? 'U' : 'S',
3760	Pde.n.u1Accessed ? 'A' : '-',
3761	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3762	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3763	Pde.n.u1WriteThru ? "WT" : "--",
3764	Pde.n.u1CacheDisable? "CD" : "--",
3765	Pde.u & RT_BIT(9) ? '1' : '0',
3766	Pde.u & RT_BIT(10) ? '1' : '0',
3767	Pde.u & RT_BIT(11) ? '1' : '0',
3768	Pde.u & X86_PDE_PG_MASK));
3769	////if (cMaxDepth >= 1)
3770	{
3771	/** @todo what about using the page pool for mapping PTs? */
3772	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3773	PX86PT pPT = NULL;
3774
3775	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3776
3777	int rc2 = VERR_INVALID_PARAMETER;
3778	if (pPT)
3779	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3780	else
3781	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3782	if (rc2 < rc && VBOX_SUCCESS(rc))
3783	rc = rc2;
3784	}
3785	}
3786	}
3787	}
3788
3789	return rc;
3790	}
3791
3792
3793	/**
3794	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3795	*
3796	* @returns VBox status code (VINF_SUCCESS).
3797	* @param pVM The VM handle.
3798	* @param cr3 The root of the hierarchy.
3799	* @param cr4 The cr4, only PAE and PSE is currently used.
3800	* @param fLongMode Set if long mode, false if not long mode.
3801	* @param cMaxDepth Number of levels to dump.
3802	* @param pHlp Pointer to the output functions.
3803	*/
3804	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3805	{
3806	if (!pHlp)
3807	pHlp = DBGFR3InfoLogHlp();
3808	if (!cMaxDepth)
3809	return VINF_SUCCESS;
3810	const unsigned cch = fLongMode ? 16 : 8;
3811	pHlp->pfnPrintf(pHlp,
3812	"cr3=%08x cr4=%08x%s\n"
3813	"%-*s P - Present\n"
3814	"%-*s \| R/W - Read (0) / Write (1)\n"
3815	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3816	"%-*s \| \| \| A - Accessed\n"
3817	"%-*s \| \| \| \| D - Dirty\n"
3818	"%-*s \| \| \| \| \| G - Global\n"
3819	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3820	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3821	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3822	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3823	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3824	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3825	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3826	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3827	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3828	- W U - - - -- -- -- -- -- 010 */
3829	, cr3, cr4, fLongMode ? " Long Mode" : "",
3830	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3831	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3832	if (cr4 & X86_CR4_PAE)
3833	{
3834	if (fLongMode)
3835	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3836	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3837	}
3838	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3839	}
3840
3841
3842
3843	#ifdef VBOX_WITH_DEBUGGER
3844	/**
3845	* The '.pgmram' command.
3846	*
3847	* @returns VBox status.
3848	* @param pCmd Pointer to the command descriptor (as registered).
3849	* @param pCmdHlp Pointer to command helper functions.
3850	* @param pVM Pointer to the current VM (if any).
3851	* @param paArgs Pointer to (readonly) array of arguments.
3852	* @param cArgs Number of arguments in the array.
3853	*/
3854	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3855	{
3856	/*
3857	* Validate input.
3858	*/
3859	if (!pVM)
3860	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3861	if (!pVM->pgm.s.pRamRangesGC)
3862	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3863
3864	/*
3865	* Dump the ranges.
3866	*/
3867	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3868	PPGMRAMRANGE pRam;
3869	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
3870	{
3871	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3872	"%VGp - %VGp %p\n",
3873	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3874	if (VBOX_FAILURE(rc))
3875	return rc;
3876	}
3877
3878	return VINF_SUCCESS;
3879	}
3880
3881
3882	/**
3883	* The '.pgmmap' command.
3884	*
3885	* @returns VBox status.
3886	* @param pCmd Pointer to the command descriptor (as registered).
3887	* @param pCmdHlp Pointer to command helper functions.
3888	* @param pVM Pointer to the current VM (if any).
3889	* @param paArgs Pointer to (readonly) array of arguments.
3890	* @param cArgs Number of arguments in the array.
3891	*/
3892	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3893	{
3894	/*
3895	* Validate input.
3896	*/
3897	if (!pVM)
3898	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3899	if (!pVM->pgm.s.pMappingsR3)
3900	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3901
3902	/*
3903	* Print message about the fixedness of the mappings.
3904	*/
3905	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3906	if (VBOX_FAILURE(rc))
3907	return rc;
3908
3909	/*
3910	* Dump the ranges.
3911	*/
3912	PPGMMAPPING pCur;
3913	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3914	{
3915	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3916	"%08x - %08x %s\n",
3917	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3918	if (VBOX_FAILURE(rc))
3919	return rc;
3920	}
3921
3922	return VINF_SUCCESS;
3923	}
3924
3925
3926	/**
3927	* The '.pgmsync' command.
3928	*
3929	* @returns VBox status.
3930	* @param pCmd Pointer to the command descriptor (as registered).
3931	* @param pCmdHlp Pointer to command helper functions.
3932	* @param pVM Pointer to the current VM (if any).
3933	* @param paArgs Pointer to (readonly) array of arguments.
3934	* @param cArgs Number of arguments in the array.
3935	*/
3936	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3937	{
3938	/*
3939	* Validate input.
3940	*/
3941	if (!pVM)
3942	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3943
3944	/*
3945	* Force page directory sync.
3946	*/
3947	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3948
3949	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3950	if (VBOX_FAILURE(rc))
3951	return rc;
3952
3953	return VINF_SUCCESS;
3954	}
3955
3956
3957	/**
3958	* The '.pgmsyncalways' command.
3959	*
3960	* @returns VBox status.
3961	* @param pCmd Pointer to the command descriptor (as registered).
3962	* @param pCmdHlp Pointer to command helper functions.
3963	* @param pVM Pointer to the current VM (if any).
3964	* @param paArgs Pointer to (readonly) array of arguments.
3965	* @param cArgs Number of arguments in the array.
3966	*/
3967	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3968	{
3969	/*
3970	* Validate input.
3971	*/
3972	if (!pVM)
3973	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3974
3975	/*
3976	* Force page directory sync.
3977	*/
3978	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3979	{
3980	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3981	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3982	}
3983	else
3984	{
3985	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3986	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3987	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3988	}
3989	}
3990
3991	#endif
3992
3993	/**
3994	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3995	*/
3996	typedef struct PGMCHECKINTARGS
3997	{
3998	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3999	PPGMPHYSHANDLER pPrevPhys;
4000	PPGMVIRTHANDLER pPrevVirt;
4001	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4002	PVM pVM;
4003	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4004
4005	/**
4006	* Validate a node in the physical handler tree.
4007	*
4008	* @returns 0 on if ok, other wise 1.
4009	* @param pNode The handler node.
4010	* @param pvUser pVM.
4011	*/
4012	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4013	{
4014	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4015	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4016	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4017	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4018	AssertReleaseMsg( !pArgs->pPrevPhys
4019	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4020	("pPrevPhys=%p %VGp-%VGp %s\n"
4021	" pCur=%p %VGp-%VGp %s\n",
4022	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4023	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4024	pArgs->pPrevPhys = pCur;
4025	return 0;
4026	}
4027
4028
4029	/**
4030	* Validate a node in the virtual handler tree.
4031	*
4032	* @returns 0 on if ok, other wise 1.
4033	* @param pNode The handler node.
4034	* @param pvUser pVM.
4035	*/
4036	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4037	{
4038	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4039	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4040	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4041	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4042	AssertReleaseMsg( !pArgs->pPrevVirt
4043	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4044	("pPrevVirt=%p %VGv-%VGv %s\n"
4045	" pCur=%p %VGv-%VGv %s\n",
4046	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4047	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4048	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4049	{
4050	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4051	("pCur=%p %VGv-%VGv %s\n"
4052	"iPage=%d offVirtHandle=%#x expected %#x\n",
4053	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4054	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4055	}
4056	pArgs->pPrevVirt = pCur;
4057	return 0;
4058	}
4059
4060
4061	/**
4062	* Validate a node in the virtual handler tree.
4063	*
4064	* @returns 0 on if ok, other wise 1.
4065	* @param pNode The handler node.
4066	* @param pvUser pVM.
4067	*/
4068	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4069	{
4070	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4071	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4072	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4073	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4074	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4075	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4076	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4077	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4078	" pCur=%p %VGp-%VGp\n",
4079	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4080	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4081	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4082	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4083	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4084	" pCur=%p %VGp-%VGp\n",
4085	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4086	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4087	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4088	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4089	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4090	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4091	{
4092	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4093	for (;;)
4094	{
4095	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4096	AssertReleaseMsg(pCur2 != pCur,
4097	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4098	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4099	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4100	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4101	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4102	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4103	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4104	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4105	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4106	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4107	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4108	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4109	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4110	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4111	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4112	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4113	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4114	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4115	break;
4116	}
4117	}
4118
4119	pArgs->pPrevPhys2Virt = pCur;
4120	return 0;
4121	}
4122
4123
4124	/**
4125	* Perform an integrity check on the PGM component.
4126	*
4127	* @returns VINF_SUCCESS if everything is fine.
4128	* @returns VBox error status after asserting on integrity breach.
4129	* @param pVM The VM handle.
4130	*/
4131	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4132	{
4133	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4134
4135	/*
4136	* Check the trees.
4137	*/
4138	int cErrors = 0;
4139	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4140	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4141	PGMCHECKINTARGS Args = s_LeftToRight;
4142	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4143	Args = s_RightToLeft;
4144	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4145	Args = s_LeftToRight;
4146	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4147	Args = s_RightToLeft;
4148	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4149	Args = s_LeftToRight;
4150	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4151	Args = s_RightToLeft;
4152	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4153	Args = s_LeftToRight;
4154	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4155	Args = s_RightToLeft;
4156	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4157
4158	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4159	}
4160
4161
4162	/**
4163	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4164	*
4165	* @returns VBox status code.
4166	* @param pVM VM handle.
4167	* @param fEnable Enable or disable shadow mappings
4168	*/
4169	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4170	{
4171	pVM->pgm.s.fDisableMappings = !fEnable;
4172
4173	uint32_t cb;
4174	int rc = PGMR3MappingsSize(pVM, &cb);
4175	AssertRCReturn(rc, rc);
4176
4177	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4178	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4179	AssertRCReturn(rc, rc);
4180
4181	return VINF_SUCCESS;
4182	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 9981

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