PGMGst.h@ 14082

Last change on this file since 14082 was 14075, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMGst.h 14075 2008-11-11 00:14:05Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager / Monitor, Guest Paging Template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef GSTPT
26	#undef PGSTPT
27	#undef GSTPTE
28	#undef PGSTPTE
29	#undef GSTPD
30	#undef PGSTPD
31	#undef GSTPDE
32	#undef PGSTPDE
33	#undef GST_BIG_PAGE_SIZE
34	#undef GST_BIG_PAGE_OFFSET_MASK
35	#undef GST_PDE_PG_MASK
36	#undef GST_PDE_BIG_PG_MASK
37	#undef GST_PD_SHIFT
38	#undef GST_PD_MASK
39	#undef GST_PTE_PG_MASK
40	#undef GST_PT_SHIFT
41	#undef GST_PT_MASK
42	#undef GST_TOTAL_PD_ENTRIES
43	#undef GST_CR3_PAGE_MASK
44	#undef GST_PDPE_ENTRIES
45	#undef GST_GET_PDE_BIG_PG_GCPHYS
46
47	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
48	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
49	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
50	# define GSTPT X86PT
51	# define PGSTPT PX86PT
52	# define GSTPTE X86PTE
53	# define PGSTPTE PX86PTE
54	# define GSTPD X86PD
55	# define PGSTPD PX86PD
56	# define GSTPDE X86PDE
57	# define PGSTPDE PX86PDE
58	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
59	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
60	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
61	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
62	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
63	# define GST_PD_SHIFT X86_PD_SHIFT
64	# define GST_PD_MASK X86_PD_MASK
65	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
66	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
67	# define GST_PT_SHIFT X86_PT_SHIFT
68	# define GST_PT_MASK X86_PT_MASK
69	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
70
71	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
73	# define GSTPT X86PTPAE
74	# define PGSTPT PX86PTPAE
75	# define GSTPTE X86PTEPAE
76	# define PGSTPTE PX86PTEPAE
77	# define GSTPD X86PDPAE
78	# define PGSTPD PX86PDPAE
79	# define GSTPDE X86PDEPAE
80	# define PGSTPDE PX86PDEPAE
81	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
86	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
87	# define GST_PD_MASK X86_PD_PAE_MASK
88	# if PGM_GST_TYPE == PGM_TYPE_PAE
89	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
90	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
91	# else
92	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
93	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
94	# endif
95	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
96	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
97	# define GST_PT_MASK X86_PT_PAE_MASK
98	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
99	#endif
100
101
102	/*******************************************************************************
103	* Internal Functions *
104	*******************************************************************************/
105	__BEGIN_DECLS
106	/* r3 */
107	PGM_GST_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
108	PGM_GST_DECL(int, Enter)(PVM pVM, RTGCPHYS GCPhysCR3);
109	PGM_GST_DECL(int, Relocate)(PVM pVM, RTGCPTR offDelta);
110	PGM_GST_DECL(int, Exit)(PVM pVM);
111
112	static DECLCALLBACK(int) pgmR3Gst32BitWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
113	static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
114	#if 0
115	static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerPD(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
116	#endif
117
118	/* all */
119	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
120	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
121	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
122	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
123	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
124	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
125	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
126	__END_DECLS
127
128
129	/**
130	* Initializes the guest bit of the paging mode data.
131	*
132	* @returns VBox status code.
133	* @param pVM The VM handle.
134	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
135	* This is used early in the init process to avoid trouble with PDM
136	* not being initialized yet.
137	*/
138	PGM_GST_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
139	{
140	Assert(pModeData->uGstType == PGM_GST_TYPE);
141
142	/* Ring-3 */
143	pModeData->pfnR3GstRelocate = PGM_GST_NAME(Relocate);
144	pModeData->pfnR3GstExit = PGM_GST_NAME(Exit);
145	pModeData->pfnR3GstGetPDE = PGM_GST_NAME(GetPDE);
146	pModeData->pfnR3GstGetPage = PGM_GST_NAME(GetPage);
147	pModeData->pfnR3GstModifyPage = PGM_GST_NAME(ModifyPage);
148	pModeData->pfnR3GstMapCR3 = PGM_GST_NAME(MapCR3);
149	pModeData->pfnR3GstUnmapCR3 = PGM_GST_NAME(UnmapCR3);
150	pModeData->pfnR3GstMonitorCR3 = PGM_GST_NAME(MonitorCR3);
151	pModeData->pfnR3GstUnmonitorCR3 = PGM_GST_NAME(UnmonitorCR3);
152
153	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
154	pModeData->pfnR3GstWriteHandlerCR3 = PGM_GST_NAME(WriteHandlerCR3);
155	pModeData->pszR3GstWriteHandlerCR3 = "Guest CR3 Write access handler";
156	pModeData->pfnR3GstPAEWriteHandlerCR3 = PGM_GST_NAME(WriteHandlerCR3);
157	pModeData->pszR3GstPAEWriteHandlerCR3 = "Guest CR3 Write access handler (PAE)";
158	#else
159	pModeData->pfnR3GstWriteHandlerCR3 = NULL;
160	pModeData->pszR3GstWriteHandlerCR3 = NULL;
161	pModeData->pfnR3GstPAEWriteHandlerCR3 = NULL;
162	pModeData->pszR3GstPAEWriteHandlerCR3 = NULL;
163	#endif
164
165	if (fResolveGCAndR0)
166	{
167	int rc;
168
169	#if PGM_SHW_TYPE != PGM_TYPE_AMD64 /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
170	/* GC */
171	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(GetPage), &pModeData->pfnRCGstGetPage);
172	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(GetPage), rc), rc);
173	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(ModifyPage), &pModeData->pfnRCGstModifyPage);
174	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(ModifyPage), rc), rc);
175	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(GetPDE), &pModeData->pfnRCGstGetPDE);
176	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(GetPDE), rc), rc);
177	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(MonitorCR3), &pModeData->pfnRCGstMonitorCR3);
178	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(MonitorCR3), rc), rc);
179	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(UnmonitorCR3), &pModeData->pfnRCGstUnmonitorCR3);
180	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(UnmonitorCR3), rc), rc);
181	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(MapCR3), &pModeData->pfnRCGstMapCR3);
182	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(MapCR3), rc), rc);
183	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(UnmapCR3), &pModeData->pfnRCGstUnmapCR3);
184	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(UnmapCR3), rc), rc);
185	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
186	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(WriteHandlerCR3), &pModeData->pfnRCGstWriteHandlerCR3);
187	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
188	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_GST_NAME_RC_STR(WriteHandlerCR3), &pModeData->pfnRCGstPAEWriteHandlerCR3);
189	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
190	# endif
191	#endif /* Not AMD64 shadow paging. */
192
193	/* Ring-0 */
194	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(GetPage), &pModeData->pfnR0GstGetPage);
195	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(GetPage), rc), rc);
196	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(ModifyPage), &pModeData->pfnR0GstModifyPage);
197	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(ModifyPage), rc), rc);
198	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(GetPDE), &pModeData->pfnR0GstGetPDE);
199	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(GetPDE), rc), rc);
200	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(MonitorCR3), &pModeData->pfnR0GstMonitorCR3);
201	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(MonitorCR3), rc), rc);
202	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(UnmonitorCR3), &pModeData->pfnR0GstUnmonitorCR3);
203	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(UnmonitorCR3), rc), rc);
204	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(MapCR3), &pModeData->pfnR0GstMapCR3);
205	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(MapCR3), rc), rc);
206	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(UnmapCR3), &pModeData->pfnR0GstUnmapCR3);
207	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(UnmapCR3), rc), rc);
208	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
209	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(WriteHandlerCR3), &pModeData->pfnR0GstWriteHandlerCR3);
210	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
211	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_GST_NAME_R0_STR(WriteHandlerCR3), &pModeData->pfnR0GstPAEWriteHandlerCR3);
212	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
213	#endif
214	}
215
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* Enters the guest mode.
222	*
223	* @returns VBox status code.
224	* @param pVM VM handle.
225	* @param GCPhysCR3 The physical address from the CR3 register.
226	*/
227	PGM_GST_DECL(int, Enter)(PVM pVM, RTGCPHYS GCPhysCR3)
228	{
229	/*
230	* Map and monitor CR3
231	*/
232	int rc = PGM_GST_NAME(MapCR3)(pVM, GCPhysCR3);
233	if (RT_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
234	rc = PGM_GST_NAME(MonitorCR3)(pVM, GCPhysCR3);
235	return rc;
236	}
237
238
239	/**
240	* Relocate any GC pointers related to guest mode paging.
241	*
242	* @returns VBox status code.
243	* @param pVM The VM handle.
244	* @param offDelta The reloation offset.
245	*/
246	PGM_GST_DECL(int, Relocate)(PVM pVM, RTGCPTR offDelta)
247	{
248	/* nothing special to do here - InitData does the job. */
249	return VINF_SUCCESS;
250	}
251
252
253	/**
254	* Exits the guest mode.
255	*
256	* @returns VBox status code.
257	* @param pVM VM handle.
258	*/
259	PGM_GST_DECL(int, Exit)(PVM pVM)
260	{
261	int rc = PGM_GST_NAME(UnmonitorCR3)(pVM);
262	if (RT_SUCCESS(rc))
263	rc = PGM_GST_NAME(UnmapCR3)(pVM);
264	return rc;
265	}
266
267
268	#if PGM_GST_TYPE == PGM_TYPE_32BIT
269	/**
270	* Physical write access for the Guest CR3 in 32-bit mode.
271	*
272	* @returns VINF_SUCCESS if the handler have carried out the operation.
273	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
274	* @param pVM VM Handle.
275	* @param GCPhys The physical address the guest is writing to.
276	* @param pvPhys The HC mapping of that address.
277	* @param pvBuf What the guest is reading/writing.
278	* @param cbBuf How much it's reading/writing.
279	* @param enmAccessType The access type.
280	* @param pvUser User argument.
281	*/
282	static DECLCALLBACK(int) pgmR3Gst32BitWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
283	{
284	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
285	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
286	Log2(("pgmR3Gst32BitWriteHandlerCR3: ff=%#x GCPhys=%RGp pvPhys=%p cbBuf=%d pvBuf={%.*Rhxs}\n", pVM->fForcedActions, GCPhys, pvPhys, cbBuf, cbBuf, pvBuf));
287
288	/*
289	* Do the write operation.
290	*/
291	memcpy(pvPhys, pvBuf, cbBuf);
292	if ( !pVM->pgm.s.fMappingsFixed
293	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
294	{
295	/*
296	* Check for conflicts.
297	*/
298	const RTGCPTR offPD = GCPhys & PAGE_OFFSET_MASK;
299	const unsigned iPD1 = offPD / sizeof(X86PDE);
300	const unsigned iPD2 = (unsigned)(offPD + cbBuf - 1) / sizeof(X86PDE);
301	Assert(iPD1 - iPD2 <= 1);
302	if ( ( pVM->pgm.s.pGuestPDR3->a[iPD1].n.u1Present
303	&& pgmGetMapping(pVM, iPD1 << X86_PD_SHIFT) )
304	\|\| ( iPD1 != iPD2
305	&& pVM->pgm.s.pGuestPDR3->a[iPD2].n.u1Present
306	&& pgmGetMapping(pVM, iPD2 << X86_PD_SHIFT) )
307	)
308	{
309	Log(("pgmR3Gst32BitWriteHandlerCR3: detected conflict. iPD1=%#x iPD2=%#x GCPhys=%RGp\n", iPD1, iPD2, GCPhys));
310	STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWriteConflict);
311	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
312	}
313	}
314
315	STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWrite);
316	return VINF_SUCCESS;
317	}
318	#endif /* 32BIT */
319
320	#if PGM_GST_TYPE == PGM_TYPE_PAE
321
322	/**
323	* Physical write access handler for the Guest CR3 in PAE mode.
324	*
325	* @returns VINF_SUCCESS if the handler have carried out the operation.
326	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
327	* @param pVM VM Handle.
328	* @param GCPhys The physical address the guest is writing to.
329	* @param pvPhys The HC mapping of that address.
330	* @param pvBuf What the guest is reading/writing.
331	* @param cbBuf How much it's reading/writing.
332	* @param enmAccessType The access type.
333	* @param pvUser User argument.
334	*/
335	static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
336	{
337	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
338	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
339	Log2(("pgmR3GstPAEWriteHandlerCR3: ff=%#x GCPhys=%RGp pvPhys=%p cbBuf=%d pvBuf={%.*Rhxs}\n", pVM->fForcedActions, GCPhys, pvPhys, cbBuf, cbBuf, pvBuf));
340
341	/*
342	* Do the write operation.
343	*/
344	memcpy(pvPhys, pvBuf, cbBuf);
345	if ( !pVM->pgm.s.fMappingsFixed
346	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
347	{
348	/*
349	* Check if any of the PDs have changed.
350	* We'll simply check all of them instead of figuring out which one/two to check.
351	*/
352	for (unsigned i = 0; i < 4; i++)
353	{
354	if ( pVM->pgm.s.pGstPaePDPTR3->a[i].n.u1Present
355	&& (pVM->pgm.s.pGstPaePDPTR3->a[i].u & X86_PDPE_PG_MASK) != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
356	{
357	Log(("pgmR3GstPAEWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
358	i, pVM->pgm.s.pGstPaePDPTR3->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
359	/*
360	* The PD has changed.
361	* We will schedule a monitoring update for the next TLB Flush,
362	* InvalidatePage or SyncCR3.
363	*
364	* This isn't perfect, because a lazy page sync might be dealing with an half
365	* updated PDPE. However, we assume that the guest OS is disabling interrupts
366	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
367	* executing.
368	*/
369	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
370	}
371	}
372	}
373	/*
374	* Flag a updating of the monitor at the next crossroad so we don't monitor the
375	* wrong pages for soo long that they can be reused as code pages and freak out
376	* the recompiler or something.
377	*/
378	else
379	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
380
381
382	STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWrite);
383	return VINF_SUCCESS;
384	}
385
386	# if 0
387	/**
388	* Physical write access for Guest CR3.
389	*
390	* @returns VINF_SUCCESS if the handler have carried out the operation.
391	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
392	* @param pVM VM Handle.
393	* @param GCPhys The physical address the guest is writing to.
394	* @param pvPhys The HC mapping of that address.
395	* @param pvBuf What the guest is reading/writing.
396	* @param cbBuf How much it's reading/writing.
397	* @param enmAccessType The access type.
398	* @param pvUser User argument.
399	*/
400	static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerPD(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
401	{
402	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
403	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
404	Log2(("pgmR3GstPAEWriteHandlerPD: ff=%#x GCPhys=%RGp pvPhys=%p cbBuf=%d pvBuf={%.*Rhxs}\n", pVM->fForcedActions, GCPhys, pvPhys, cbBuf, cbBuf, pvBuf));
405
406	/*
407	* Do the write operation.
408	*/
409	memcpy(pvPhys, pvBuf, cbBuf);
410	if ( !pVM->pgm.s.fMappingsFixed
411	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
412	{
413	/*
414	* Figure out which of the 4 PDs this is.
415	*/
416	unsigned i;
417	for (i = 0; i < 4; i++)
418	if (pVM->pgm.s.pGstPaePDPTHC->a[i].u == (GCPhys & X86_PTE_PAE_PG_MASK))
419	{
420	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
421	const RTGCPTR offPD = GCPhys & PAGE_OFFSET_MASK;
422	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
423	const unsigned iPD2 = (offPD + cbBuf - 1) / sizeof(X86PDEPAE);
424	Assert(iPD1 - iPD2 <= 1);
425	if ( ( pPDSrc->a[iPD1].n.u1Present
426	&& pgmGetMapping(pVM, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)) )
427	\|\| ( iPD1 != iPD2
428	&& pPDSrc->a[iPD2].n.u1Present
429	&& pgmGetMapping(pVM, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)) )
430	)
431	{
432	Log(("pgmR3GstPaePD3WriteHandler: detected conflict. i=%d iPD1=%#x iPD2=%#x GCPhys=%RGp\n",
433	i, iPD1, iPD2, GCPhys));
434	STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWriteConflict);
435	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
436	}
437	break; /* ASSUMES no duplicate entries... */
438	}
439	Assert(i < 4);
440	}
441
442	STAM_COUNTER_INC(&pVM->pgm.s.StatR3GuestPDWrite);
443	return VINF_SUCCESS;
444	}
445	# endif
446
447	#endif /* PAE */
448

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source: vbox/trunk/src/VBox/VMM/PGMGst.h@ 14082

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