VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 12998

Last change on this file since 12998 was 12989, checked in by vboxsync, 16 years ago

VMM + VBox/cdefs.h: consolidated all the XYZ*DECLS of the VMM into VMM*DECL. Removed dead DECL and IN_XYZ* macros.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 156.4 KB
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1/* $Id: PGMInternal.h 12989 2008-10-06 02:15:39Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) ((uGstType) >= PGM_TYPE_32BIT && (uShwType) != PGM_TYPE_NESTED && (uShwType) != PGM_TYPE_EPT)
201
202/** Macro for checking if the guest supports the NX bit.
203 * @param uGstType PGM_TYPE_*
204 * @param uShwType PGM_TYPE_*
205 * @remark ASSUMES certain order of the PGM_TYPE_* values.
206 */
207#define PGM_WITH_NX(uGstType, uShwType) ((uGstType) >= PGM_TYPE_PAE && (uShwType) != PGM_TYPE_NESTED && (uShwType) != PGM_TYPE_EPT)
208
209
210/** @def PGM_HCPHYS_2_PTR
211 * Maps a HC physical page pool address to a virtual address.
212 *
213 * @returns VBox status code.
214 * @param pVM The VM handle.
215 * @param HCPhys The HC physical address to map to a virtual one.
216 * @param ppv Where to store the virtual address. No need to cast this.
217 *
218 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
219 * small page window employeed by that function. Be careful.
220 * @remark There is no need to assert on the result.
221 */
222#ifdef IN_GC
223# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
224#else
225# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
226#endif
227
228/** @def PGM_GCPHYS_2_PTR
229 * Maps a GC physical page address to a virtual address.
230 *
231 * @returns VBox status code.
232 * @param pVM The VM handle.
233 * @param GCPhys The GC physical address to map to a virtual one.
234 * @param ppv Where to store the virtual address. No need to cast this.
235 *
236 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
237 * small page window employeed by that function. Be careful.
238 * @remark There is no need to assert on the result.
239 */
240#ifdef IN_GC
241# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
242#else
243# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
244#endif
245
246/** @def PGM_GCPHYS_2_PTR_EX
247 * Maps a unaligned GC physical page address to a virtual address.
248 *
249 * @returns VBox status code.
250 * @param pVM The VM handle.
251 * @param GCPhys The GC physical address to map to a virtual one.
252 * @param ppv Where to store the virtual address. No need to cast this.
253 *
254 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
255 * small page window employeed by that function. Be careful.
256 * @remark There is no need to assert on the result.
257 */
258#ifdef IN_GC
259# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
260#else
261# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
262#endif
263
264/** @def PGM_INVL_PG
265 * Invalidates a page when in GC does nothing in HC.
266 *
267 * @param GCVirt The virtual address of the page to invalidate.
268 */
269#ifdef IN_GC
270# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
271#elif defined(IN_RING0)
272# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
273#else
274# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
275#endif
276
277/** @def PGM_INVL_BIG_PG
278 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
279 *
280 * @param GCVirt The virtual address within the page directory to invalidate.
281 */
282#ifdef IN_GC
283# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
284#elif defined(IN_RING0)
285# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
286#else
287# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
288#endif
289
290/** @def PGM_INVL_GUEST_TLBS()
291 * Invalidates all guest TLBs.
292 */
293#ifdef IN_GC
294# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
295#elif defined(IN_RING0)
296# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
297#else
298# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
299#endif
300
301
302/**
303 * Structure for tracking GC Mappings.
304 *
305 * This structure is used by linked list in both GC and HC.
306 */
307typedef struct PGMMAPPING
308{
309 /** Pointer to next entry. */
310 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
311 /** Pointer to next entry. */
312 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
313 /** Pointer to next entry. */
314 RCPTRTYPE(struct PGMMAPPING *) pNextGC;
315#if GC_ARCH_BITS == 64
316 RTRCPTR padding0;
317#endif
318 /** Start Virtual address. */
319 RTGCUINTPTR GCPtr;
320 /** Last Virtual address (inclusive). */
321 RTGCUINTPTR GCPtrLast;
322 /** Range size (bytes). */
323 RTGCUINTPTR cb;
324 /** Pointer to relocation callback function. */
325 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
326 /** User argument to the callback. */
327 R3PTRTYPE(void *) pvUser;
328 /** Mapping description / name. For easing debugging. */
329 R3PTRTYPE(const char *) pszDesc;
330 /** Number of page tables. */
331 RTUINT cPTs;
332#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
333 RTUINT uPadding1; /**< Alignment padding. */
334#endif
335 /** Array of page table mapping data. Each entry
336 * describes one page table. The array can be longer
337 * than the declared length.
338 */
339 struct
340 {
341 /** The HC physical address of the page table. */
342 RTHCPHYS HCPhysPT;
343 /** The HC physical address of the first PAE page table. */
344 RTHCPHYS HCPhysPaePT0;
345 /** The HC physical address of the second PAE page table. */
346 RTHCPHYS HCPhysPaePT1;
347 /** The HC virtual address of the 32-bit page table. */
348 R3PTRTYPE(PX86PT) pPTR3;
349 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
350 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
351 /** The GC virtual address of the 32-bit page table. */
352 RCPTRTYPE(PX86PT) pPTGC;
353 /** The GC virtual address of the two PAE page table. */
354 RCPTRTYPE(PX86PTPAE) paPaePTsGC;
355 /** The GC virtual address of the 32-bit page table. */
356 R0PTRTYPE(PX86PT) pPTR0;
357 /** The GC virtual address of the two PAE page table. */
358 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
359 } aPTs[1];
360} PGMMAPPING;
361/** Pointer to structure for tracking GC Mappings. */
362typedef struct PGMMAPPING *PPGMMAPPING;
363
364
365/**
366 * Physical page access handler structure.
367 *
368 * This is used to keep track of physical address ranges
369 * which are being monitored in some kind of way.
370 */
371typedef struct PGMPHYSHANDLER
372{
373 AVLROGCPHYSNODECORE Core;
374 /** Access type. */
375 PGMPHYSHANDLERTYPE enmType;
376 /** Number of pages to update. */
377 uint32_t cPages;
378 /** Pointer to R3 callback function. */
379 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
380 /** User argument for R3 handlers. */
381 R3PTRTYPE(void *) pvUserR3;
382 /** Pointer to R0 callback function. */
383 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
384 /** User argument for R0 handlers. */
385 R0PTRTYPE(void *) pvUserR0;
386 /** Pointer to GC callback function. */
387 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
388 /** User argument for GC handlers. */
389 RCPTRTYPE(void *) pvUserGC;
390 /** Description / Name. For easing debugging. */
391 R3PTRTYPE(const char *) pszDesc;
392#ifdef VBOX_WITH_STATISTICS
393 /** Profiling of this handler. */
394 STAMPROFILE Stat;
395#endif
396} PGMPHYSHANDLER;
397/** Pointer to a physical page access handler structure. */
398typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
399
400
401/**
402 * Cache node for the physical addresses covered by a virtual handler.
403 */
404typedef struct PGMPHYS2VIRTHANDLER
405{
406 /** Core node for the tree based on physical ranges. */
407 AVLROGCPHYSNODECORE Core;
408 /** Offset from this struct to the PGMVIRTHANDLER structure. */
409 int32_t offVirtHandler;
410 /** Offset of the next alias relative to this one.
411 * Bit 0 is used for indicating whether we're in the tree.
412 * Bit 1 is used for indicating that we're the head node.
413 */
414 int32_t offNextAlias;
415} PGMPHYS2VIRTHANDLER;
416/** Pointer to a phys to virtual handler structure. */
417typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
418
419/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
420 * node is in the tree. */
421#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
422/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
423 * node is in the head of an alias chain.
424 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
425#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
426/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
427#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
428
429
430/**
431 * Virtual page access handler structure.
432 *
433 * This is used to keep track of virtual address ranges
434 * which are being monitored in some kind of way.
435 */
436typedef struct PGMVIRTHANDLER
437{
438 /** Core node for the tree based on virtual ranges. */
439 AVLROGCPTRNODECORE Core;
440 /** Number of cache pages. */
441 uint32_t u32Padding;
442 /** Access type. */
443 PGMVIRTHANDLERTYPE enmType;
444 /** Number of cache pages. */
445 uint32_t cPages;
446#if GC_ARCH_BITS == 64
447 uint32_t padding0;
448#endif
449/** @todo The next two members are redundant. It adds some readability though. */
450 /** Start of the range. */
451 RTGCPTR GCPtr;
452 /** End of the range (exclusive). */
453 RTGCPTR GCPtrLast;
454 /** Size of the range (in bytes). */
455 RTGCUINTPTR cb;
456 /** Pointer to the GC callback function. */
457 RCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
458#if GC_ARCH_BITS == 64
459 RTRCPTR padding1;
460#endif
461 /** Pointer to the HC callback function for invalidation. */
462 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
463 /** Pointer to the HC callback function. */
464 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
465 /** Description / Name. For easing debugging. */
466 R3PTRTYPE(const char *) pszDesc;
467#ifdef VBOX_WITH_STATISTICS
468 /** Profiling of this handler. */
469 STAMPROFILE Stat;
470#endif
471 /** Array of cached physical addresses for the monitored ranged. */
472 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
473} PGMVIRTHANDLER;
474/** Pointer to a virtual page access handler structure. */
475typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
476
477
478/**
479 * Page type.
480 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
481 * @todo convert to \#defines.
482 */
483typedef enum PGMPAGETYPE
484{
485 /** The usual invalid zero entry. */
486 PGMPAGETYPE_INVALID = 0,
487 /** RAM page. (RWX) */
488 PGMPAGETYPE_RAM,
489 /** MMIO2 page. (RWX) */
490 PGMPAGETYPE_MMIO2,
491 /** Shadowed ROM. (RWX) */
492 PGMPAGETYPE_ROM_SHADOW,
493 /** ROM page. (R-X) */
494 PGMPAGETYPE_ROM,
495 /** MMIO page. (---) */
496 PGMPAGETYPE_MMIO,
497 /** End of valid entries. */
498 PGMPAGETYPE_END
499} PGMPAGETYPE;
500AssertCompile(PGMPAGETYPE_END < 7);
501
502/** @name Page type predicates.
503 * @{ */
504#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
505#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
506#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
507#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
508#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
509/** @} */
510
511
512/**
513 * A Physical Guest Page tracking structure.
514 *
515 * The format of this structure is complicated because we have to fit a lot
516 * of information into as few bits as possible. The format is also subject
517 * to change (there is one comming up soon). Which means that for we'll be
518 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
519 * accessess to the structure.
520 */
521typedef struct PGMPAGE
522{
523 /** The physical address and a whole lot of other stuff. All bits are used! */
524 RTHCPHYS HCPhys;
525 /** The page state. */
526 uint32_t u2StateX : 2;
527 /** Flag indicating that a write monitored page was written to when set. */
528 uint32_t fWrittenToX : 1;
529 /** For later. */
530 uint32_t fSomethingElse : 1;
531 /** The Page ID.
532 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
533 * The HCPhys will be 100% static. */
534 uint32_t idPageX : 28;
535 /** The page type (PGMPAGETYPE). */
536 uint32_t u3Type : 3;
537 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
538 uint32_t u2HandlerPhysStateX : 2;
539 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
540 uint32_t u2HandlerVirtStateX : 2;
541 uint32_t u29B : 25;
542} PGMPAGE;
543AssertCompileSize(PGMPAGE, 16);
544/** Pointer to a physical guest page. */
545typedef PGMPAGE *PPGMPAGE;
546/** Pointer to a const physical guest page. */
547typedef const PGMPAGE *PCPGMPAGE;
548/** Pointer to a physical guest page pointer. */
549typedef PPGMPAGE *PPPGMPAGE;
550
551
552/**
553 * Clears the page structure.
554 * @param pPage Pointer to the physical guest page tracking structure.
555 */
556#define PGM_PAGE_CLEAR(pPage) \
557 do { \
558 (pPage)->HCPhys = 0; \
559 (pPage)->u2StateX = 0; \
560 (pPage)->fWrittenToX = 0; \
561 (pPage)->fSomethingElse = 0; \
562 (pPage)->idPageX = 0; \
563 (pPage)->u3Type = 0; \
564 (pPage)->u29B = 0; \
565 } while (0)
566
567/**
568 * Initializes the page structure.
569 * @param pPage Pointer to the physical guest page tracking structure.
570 */
571#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
572 do { \
573 (pPage)->HCPhys = (_HCPhys); \
574 (pPage)->u2StateX = (_uState); \
575 (pPage)->fWrittenToX = 0; \
576 (pPage)->fSomethingElse = 0; \
577 (pPage)->idPageX = (_idPage); \
578 /*(pPage)->u3Type = (_uType); - later */ \
579 PGM_PAGE_SET_TYPE(pPage, _uType); \
580 (pPage)->u29B = 0; \
581 } while (0)
582
583/**
584 * Initializes the page structure of a ZERO page.
585 * @param pPage Pointer to the physical guest page tracking structure.
586 */
587#ifdef VBOX_WITH_NEW_PHYS_CODE
588# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
589 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
590#else
591# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
592 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
593#endif
594/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
595# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
596 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
597
598
599/** @name The Page state, PGMPAGE::u2StateX.
600 * @{ */
601/** The zero page.
602 * This is a per-VM page that's never ever mapped writable. */
603#define PGM_PAGE_STATE_ZERO 0
604/** A allocated page.
605 * This is a per-VM page allocated from the page pool (or wherever
606 * we get MMIO2 pages from if the type is MMIO2).
607 */
608#define PGM_PAGE_STATE_ALLOCATED 1
609/** A allocated page that's being monitored for writes.
610 * The shadow page table mappings are read-only. When a write occurs, the
611 * fWrittenTo member is set, the page remapped as read-write and the state
612 * moved back to allocated. */
613#define PGM_PAGE_STATE_WRITE_MONITORED 2
614/** The page is shared, aka. copy-on-write.
615 * This is a page that's shared with other VMs. */
616#define PGM_PAGE_STATE_SHARED 3
617/** @} */
618
619
620/**
621 * Gets the page state.
622 * @returns page state (PGM_PAGE_STATE_*).
623 * @param pPage Pointer to the physical guest page tracking structure.
624 */
625#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
626
627/**
628 * Sets the page state.
629 * @param pPage Pointer to the physical guest page tracking structure.
630 * @param _uState The new page state.
631 */
632#define PGM_PAGE_SET_STATE(pPage, _uState) \
633 do { (pPage)->u2StateX = (_uState); } while (0)
634
635
636/**
637 * Gets the host physical address of the guest page.
638 * @returns host physical address (RTHCPHYS).
639 * @param pPage Pointer to the physical guest page tracking structure.
640 */
641#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
642
643/**
644 * Sets the host physical address of the guest page.
645 * @param pPage Pointer to the physical guest page tracking structure.
646 * @param _HCPhys The new host physical address.
647 */
648#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
649 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
650 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
651
652/**
653 * Get the Page ID.
654 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
655 * @param pPage Pointer to the physical guest page tracking structure.
656 */
657#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
658/* later:
659#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
660 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
661*/
662/**
663 * Sets the Page ID.
664 * @param pPage Pointer to the physical guest page tracking structure.
665 */
666#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
667/* later:
668#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
669 | ((_idPage) & 0xfff) \
670 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
671*/
672
673/**
674 * Get the Chunk ID.
675 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
676 * @param pPage Pointer to the physical guest page tracking structure.
677 */
678#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
679/* later:
680#if GMM_CHUNKID_SHIFT == 12
681# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
682#elif GMM_CHUNKID_SHIFT > 12
683# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
684#elif GMM_CHUNKID_SHIFT < 12
685# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
686 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
687#else
688# error "GMM_CHUNKID_SHIFT isn't defined or something."
689#endif
690*/
691
692/**
693 * Get the index of the page within the allocaiton chunk.
694 * @returns The page index.
695 * @param pPage Pointer to the physical guest page tracking structure.
696 */
697#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
698/* later:
699#if GMM_CHUNKID_SHIFT <= 12
700# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
701#else
702# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
703 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
704#endif
705*/
706
707
708/**
709 * Gets the page type.
710 * @returns The page type.
711 * @param pPage Pointer to the physical guest page tracking structure.
712 */
713#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
714
715/**
716 * Sets the page type.
717 * @param pPage Pointer to the physical guest page tracking structure.
718 * @param _enmType The new page type (PGMPAGETYPE).
719 */
720#ifdef VBOX_WITH_NEW_PHYS_CODE
721#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
722 do { (pPage)->u3Type = (_enmType); } while (0)
723#else
724#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
725 do { \
726 (pPage)->u3Type = (_enmType); \
727 if ((_enmType) == PGMPAGETYPE_ROM) \
728 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
729 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
730 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
731 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
732 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
733 } while (0)
734#endif
735
736
737/**
738 * Checks if the page is 'reserved'.
739 * @returns true/false.
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
743
744/**
745 * Checks if the page is marked for MMIO.
746 * @returns true/false.
747 * @param pPage Pointer to the physical guest page tracking structure.
748 */
749#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
750
751/**
752 * Checks if the page is backed by the ZERO page.
753 * @returns true/false.
754 * @param pPage Pointer to the physical guest page tracking structure.
755 */
756#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
757
758/**
759 * Checks if the page is backed by a SHARED page.
760 * @returns true/false.
761 * @param pPage Pointer to the physical guest page tracking structure.
762 */
763#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
764
765
766/**
767 * Marks the paget as written to (for GMM change monitoring).
768 * @param pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
771
772/**
773 * Clears the written-to indicator.
774 * @param pPage Pointer to the physical guest page tracking structure.
775 */
776#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
777
778/**
779 * Checks if the page was marked as written-to.
780 * @returns true/false.
781 * @param pPage Pointer to the physical guest page tracking structure.
782 */
783#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
784
785
786/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
787 *
788 * @remarks The values are assigned in order of priority, so we can calculate
789 * the correct state for a page with different handlers installed.
790 * @{ */
791/** No handler installed. */
792#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
793/** Monitoring is temporarily disabled. */
794#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
795/** Write access is monitored. */
796#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
797/** All access is monitored. */
798#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
799/** @} */
800
801/**
802 * Gets the physical access handler state of a page.
803 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
807
808/**
809 * Sets the physical access handler state of a page.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 * @param _uState The new state value.
812 */
813#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
814 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
815
816/**
817 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
818 * @returns true/false
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
822
823/**
824 * Checks if the page has any active physical access handlers.
825 * @returns true/false
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
829
830
831/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
832 *
833 * @remarks The values are assigned in order of priority, so we can calculate
834 * the correct state for a page with different handlers installed.
835 * @{ */
836/** No handler installed. */
837#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
838/* 1 is reserved so the lineup is identical with the physical ones. */
839/** Write access is monitored. */
840#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
841/** All access is monitored. */
842#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
843/** @} */
844
845/**
846 * Gets the virtual access handler state of a page.
847 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
848 * @param pPage Pointer to the physical guest page tracking structure.
849 */
850#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
851
852/**
853 * Sets the virtual access handler state of a page.
854 * @param pPage Pointer to the physical guest page tracking structure.
855 * @param _uState The new state value.
856 */
857#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
858 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
859
860/**
861 * Checks if the page has any virtual access handlers.
862 * @returns true/false
863 * @param pPage Pointer to the physical guest page tracking structure.
864 */
865#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
866
867/**
868 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
869 * virtual handlers.
870 * @returns true/false
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
874
875
876
877/**
878 * Checks if the page has any access handlers, including temporarily disabled ones.
879 * @returns true/false
880 * @param pPage Pointer to the physical guest page tracking structure.
881 */
882#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
883 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
884 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
885
886/**
887 * Checks if the page has any active access handlers.
888 * @returns true/false
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
892 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
893 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
894
895/**
896 * Checks if the page has any active access handlers catching all accesses.
897 * @returns true/false
898 * @param pPage Pointer to the physical guest page tracking structure.
899 */
900#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
901 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
902 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
903
904
905/**
906 * Ram range for GC Phys to HC Phys conversion.
907 *
908 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
909 * conversions too, but we'll let MM handle that for now.
910 *
911 * This structure is used by linked lists in both GC and HC.
912 */
913typedef struct PGMRAMRANGE
914{
915 /** Pointer to the next RAM range - for R3. */
916 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
917 /** Pointer to the next RAM range - for R0. */
918 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
919 /** Pointer to the next RAM range - for GC. */
920 RCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
921 /** Pointer alignment. */
922 RTRCPTR GCPtrAlignment;
923 /** Start of the range. Page aligned. */
924 RTGCPHYS GCPhys;
925 /** Last address in the range (inclusive). Page aligned (-1). */
926 RTGCPHYS GCPhysLast;
927 /** Size of the range. (Page aligned of course). */
928 RTGCPHYS cb;
929 /** MM_RAM_* flags */
930 uint32_t fFlags;
931#ifdef VBOX_WITH_NEW_PHYS_CODE
932 uint32_t u32Alignment; /**< alignment. */
933#else
934 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
935 RCPTRTYPE(PRTHCPTR) pavHCChunkGC;
936 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
937 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
938#endif
939 /** Start of the HC mapping of the range. This is only used for MMIO2. */
940 R3PTRTYPE(void *) pvHC;
941 /** The range description. */
942 R3PTRTYPE(const char *) pszDesc;
943
944 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
945#ifdef VBOX_WITH_NEW_PHYS_CODE
946 uint32_t au32Reserved[2];
947#elif HC_ARCH_BITS == 32
948 uint32_t au32Reserved[1];
949#endif
950
951 /** Array of physical guest page tracking structures. */
952 PGMPAGE aPages[1];
953} PGMRAMRANGE;
954/** Pointer to Ram range for GC Phys to HC Phys conversion. */
955typedef PGMRAMRANGE *PPGMRAMRANGE;
956
957/** Return hc ptr corresponding to the ram range and physical offset */
958#define PGMRAMRANGE_GETHCPTR(pRam, off) \
959 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
960 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
961
962/**
963 * Per page tracking structure for ROM image.
964 *
965 * A ROM image may have a shadow page, in which case we may have
966 * two pages backing it. This structure contains the PGMPAGE for
967 * both while PGMRAMRANGE have a copy of the active one. It is
968 * important that these aren't out of sync in any regard other
969 * than page pool tracking data.
970 */
971typedef struct PGMROMPAGE
972{
973 /** The page structure for the virgin ROM page. */
974 PGMPAGE Virgin;
975 /** The page structure for the shadow RAM page. */
976 PGMPAGE Shadow;
977 /** The current protection setting. */
978 PGMROMPROT enmProt;
979 /** Pad the structure size to a multiple of 8. */
980 uint32_t u32Padding;
981} PGMROMPAGE;
982/** Pointer to a ROM page tracking structure. */
983typedef PGMROMPAGE *PPGMROMPAGE;
984
985
986/**
987 * A registered ROM image.
988 *
989 * This is needed to keep track of ROM image since they generally
990 * intrude into a PGMRAMRANGE. It also keeps track of additional
991 * info like the two page sets (read-only virgin and read-write shadow),
992 * the current state of each page.
993 *
994 * Because access handlers cannot easily be executed in a different
995 * context, the ROM ranges needs to be accessible and in all contexts.
996 */
997typedef struct PGMROMRANGE
998{
999 /** Pointer to the next range - R3. */
1000 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1001 /** Pointer to the next range - R0. */
1002 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1003 /** Pointer to the next range - GC. */
1004 RCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1005 /** Pointer alignment */
1006 RTRCPTR GCPtrAlignment;
1007 /** Address of the range. */
1008 RTGCPHYS GCPhys;
1009 /** Address of the last byte in the range. */
1010 RTGCPHYS GCPhysLast;
1011 /** Size of the range. */
1012 RTGCPHYS cb;
1013 /** The flags (PGMPHYS_ROM_FLAG_*). */
1014 uint32_t fFlags;
1015 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1016 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1017 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1018 * This is used for strictness checks. */
1019 R3PTRTYPE(const void *) pvOriginal;
1020 /** The ROM description. */
1021 R3PTRTYPE(const char *) pszDesc;
1022 /** The per page tracking structures. */
1023 PGMROMPAGE aPages[1];
1024} PGMROMRANGE;
1025/** Pointer to a ROM range. */
1026typedef PGMROMRANGE *PPGMROMRANGE;
1027
1028
1029/**
1030 * A registered MMIO2 (= Device RAM) range.
1031 *
1032 * There are a few reason why we need to keep track of these
1033 * registrations. One of them is the deregistration & cleanup
1034 * stuff, while another is that the PGMRAMRANGE associated with
1035 * such a region may have to be removed from the ram range list.
1036 *
1037 * Overlapping with a RAM range has to be 100% or none at all. The
1038 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1039 * meditation will be raised if a partial overlap or an overlap of
1040 * ROM pages is encountered. On an overlap we will free all the
1041 * existing RAM pages and put in the ram range pages instead.
1042 */
1043typedef struct PGMMMIO2RANGE
1044{
1045 /** The owner of the range. (a device) */
1046 PPDMDEVINSR3 pDevInsR3;
1047 /** Pointer to the ring-3 mapping of the allocation. */
1048 RTR3PTR pvR3;
1049 /** Pointer to the next range - R3. */
1050 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1051 /** Whether it's mapped or not. */
1052 bool fMapped;
1053 /** Whether it's overlapping or not. */
1054 bool fOverlapping;
1055 /** The PCI region number.
1056 * @remarks This ASSUMES that nobody will ever really need to have multiple
1057 * PCI devices with matching MMIO region numbers on a single device. */
1058 uint8_t iRegion;
1059 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1060 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1061 /** The associated RAM range. */
1062 PGMRAMRANGE RamRange;
1063} PGMMMIO2RANGE;
1064/** Pointer to a MMIO2 range. */
1065typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1066
1067
1068
1069
1070/** @todo r=bird: fix typename. */
1071/**
1072 * PGMPhysRead/Write cache entry
1073 */
1074typedef struct PGMPHYSCACHE_ENTRY
1075{
1076 /** HC pointer to physical page */
1077 R3PTRTYPE(uint8_t *) pbHC;
1078 /** GC Physical address for cache entry */
1079 RTGCPHYS GCPhys;
1080#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1081 RTGCPHYS u32Padding0; /**< alignment padding. */
1082#endif
1083} PGMPHYSCACHE_ENTRY;
1084
1085/**
1086 * PGMPhysRead/Write cache to reduce REM memory access overhead
1087 */
1088typedef struct PGMPHYSCACHE
1089{
1090 /** Bitmap of valid cache entries */
1091 uint64_t aEntries;
1092 /** Cache entries */
1093 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1094} PGMPHYSCACHE;
1095
1096
1097/** Pointer to an allocation chunk ring-3 mapping. */
1098typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1099/** Pointer to an allocation chunk ring-3 mapping pointer. */
1100typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1101
1102/**
1103 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1104 *
1105 * The primary tree (Core) uses the chunk id as key.
1106 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1107 */
1108typedef struct PGMCHUNKR3MAP
1109{
1110 /** The key is the chunk id. */
1111 AVLU32NODECORE Core;
1112 /** The key is the ageing sequence number. */
1113 AVLLU32NODECORE AgeCore;
1114 /** The current age thingy. */
1115 uint32_t iAge;
1116 /** The current reference count. */
1117 uint32_t volatile cRefs;
1118 /** The current permanent reference count. */
1119 uint32_t volatile cPermRefs;
1120 /** The mapping address. */
1121 void *pv;
1122} PGMCHUNKR3MAP;
1123
1124/**
1125 * Allocation chunk ring-3 mapping TLB entry.
1126 */
1127typedef struct PGMCHUNKR3MAPTLBE
1128{
1129 /** The chunk id. */
1130 uint32_t volatile idChunk;
1131#if HC_ARCH_BITS == 64
1132 uint32_t u32Padding; /**< alignment padding. */
1133#endif
1134 /** The chunk map. */
1135 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1136} PGMCHUNKR3MAPTLBE;
1137/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1138typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1139
1140/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1141 * @remark Must be a power of two value. */
1142#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1143
1144/**
1145 * Allocation chunk ring-3 mapping TLB.
1146 *
1147 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1148 * At first glance this might look kinda odd since AVL trees are
1149 * supposed to give the most optimial lookup times of all trees
1150 * due to their balancing. However, take a tree with 1023 nodes
1151 * in it, that's 10 levels, meaning that most searches has to go
1152 * down 9 levels before they find what they want. This isn't fast
1153 * compared to a TLB hit. There is the factor of cache misses,
1154 * and of course the problem with trees and branch prediction.
1155 * This is why we use TLBs in front of most of the trees.
1156 *
1157 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1158 * difficult when we switch to inlined AVL trees (from kStuff).
1159 */
1160typedef struct PGMCHUNKR3MAPTLB
1161{
1162 /** The TLB entries. */
1163 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1164} PGMCHUNKR3MAPTLB;
1165
1166/**
1167 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1168 * @returns Chunk TLB index.
1169 * @param idChunk The Chunk ID.
1170 */
1171#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1172
1173
1174/**
1175 * Ring-3 guest page mapping TLB entry.
1176 * @remarks used in ring-0 as well at the moment.
1177 */
1178typedef struct PGMPAGER3MAPTLBE
1179{
1180 /** Address of the page. */
1181 RTGCPHYS volatile GCPhys;
1182 /** The guest page. */
1183 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1184 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1185 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1186 /** The address */
1187 R3R0PTRTYPE(void *) volatile pv;
1188#if HC_ARCH_BITS == 32
1189 uint32_t u32Padding; /**< alignment padding. */
1190#endif
1191} PGMPAGER3MAPTLBE;
1192/** Pointer to an entry in the HC physical TLB. */
1193typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1194
1195
1196/** The number of entries in the ring-3 guest page mapping TLB.
1197 * @remarks The value must be a power of two. */
1198#define PGM_PAGER3MAPTLB_ENTRIES 64
1199
1200/**
1201 * Ring-3 guest page mapping TLB.
1202 * @remarks used in ring-0 as well at the moment.
1203 */
1204typedef struct PGMPAGER3MAPTLB
1205{
1206 /** The TLB entries. */
1207 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1208} PGMPAGER3MAPTLB;
1209/** Pointer to the ring-3 guest page mapping TLB. */
1210typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1211
1212/**
1213 * Calculates the index of the TLB entry for the specified guest page.
1214 * @returns Physical TLB index.
1215 * @param GCPhys The guest physical address.
1216 */
1217#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1218
1219
1220/** @name Context neutrual page mapper TLB.
1221 *
1222 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1223 * code is writting in a kind of context neutrual way. Time will show whether
1224 * this actually makes sense or not...
1225 *
1226 * @{ */
1227/** @typedef PPGMPAGEMAPTLB
1228 * The page mapper TLB pointer type for the current context. */
1229/** @typedef PPGMPAGEMAPTLB
1230 * The page mapper TLB entry pointer type for the current context. */
1231/** @typedef PPGMPAGEMAPTLB
1232 * The page mapper TLB entry pointer pointer type for the current context. */
1233/** @def PGM_PAGEMAPTLB_ENTRIES
1234 * The number of TLB entries in the page mapper TLB for the current context. */
1235/** @def PGM_PAGEMAPTLB_IDX
1236 * Calculate the TLB index for a guest physical address.
1237 * @returns The TLB index.
1238 * @param GCPhys The guest physical address. */
1239/** @typedef PPGMPAGEMAP
1240 * Pointer to a page mapper unit for current context. */
1241/** @typedef PPPGMPAGEMAP
1242 * Pointer to a page mapper unit pointer for current context. */
1243#ifdef IN_GC
1244// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1245// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1246// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1247# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1248# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1249 typedef void * PPGMPAGEMAP;
1250 typedef void ** PPPGMPAGEMAP;
1251//#elif IN_RING0
1252// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1253// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1254// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1255//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1256//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1257// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1258// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1259#else
1260 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1261 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1262 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1263# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1264# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1265 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1266 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1267#endif
1268/** @} */
1269
1270
1271/** @name PGM Pool Indexes.
1272 * Aka. the unique shadow page identifier.
1273 * @{ */
1274/** NIL page pool IDX. */
1275#define NIL_PGMPOOL_IDX 0
1276/** The first normal index. */
1277#define PGMPOOL_IDX_FIRST_SPECIAL 1
1278/** Page directory (32-bit root). */
1279#define PGMPOOL_IDX_PD 1
1280/** The extended PAE page directory (2048 entries, works as root currently). */
1281#define PGMPOOL_IDX_PAE_PD 2
1282/** PAE Page Directory Table 0. */
1283#define PGMPOOL_IDX_PAE_PD_0 3
1284/** PAE Page Directory Table 1. */
1285#define PGMPOOL_IDX_PAE_PD_1 4
1286/** PAE Page Directory Table 2. */
1287#define PGMPOOL_IDX_PAE_PD_2 5
1288/** PAE Page Directory Table 3. */
1289#define PGMPOOL_IDX_PAE_PD_3 6
1290/** Page Directory Pointer Table (PAE root, not currently used). */
1291#define PGMPOOL_IDX_PDPT 7
1292/** AMD64 CR3 level index.*/
1293#define PGMPOOL_IDX_AMD64_CR3 8
1294/** Nested paging root.*/
1295#define PGMPOOL_IDX_NESTED_ROOT 9
1296/** The first normal index. */
1297#define PGMPOOL_IDX_FIRST 10
1298/** The last valid index. (inclusive, 14 bits) */
1299#define PGMPOOL_IDX_LAST 0x3fff
1300/** @} */
1301
1302/** The NIL index for the parent chain. */
1303#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1304
1305/**
1306 * Node in the chain linking a shadowed page to it's parent (user).
1307 */
1308#pragma pack(1)
1309typedef struct PGMPOOLUSER
1310{
1311 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1312 uint16_t iNext;
1313 /** The user page index. */
1314 uint16_t iUser;
1315 /** Index into the user table. */
1316 uint32_t iUserTable;
1317} PGMPOOLUSER, *PPGMPOOLUSER;
1318typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1319#pragma pack()
1320
1321
1322/** The NIL index for the phys ext chain. */
1323#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1324
1325/**
1326 * Node in the chain of physical cross reference extents.
1327 */
1328#pragma pack(1)
1329typedef struct PGMPOOLPHYSEXT
1330{
1331 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1332 uint16_t iNext;
1333 /** The user page index. */
1334 uint16_t aidx[3];
1335} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1336typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1337#pragma pack()
1338
1339
1340/**
1341 * The kind of page that's being shadowed.
1342 */
1343typedef enum PGMPOOLKIND
1344{
1345 /** The virtual invalid 0 entry. */
1346 PGMPOOLKIND_INVALID = 0,
1347 /** The entry is free (=unused). */
1348 PGMPOOLKIND_FREE,
1349
1350 /** Shw: 32-bit page table; Gst: no paging */
1351 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1352 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1353 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1354 /** Shw: 32-bit page table; Gst: 4MB page. */
1355 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1356 /** Shw: PAE page table; Gst: no paging */
1357 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1358 /** Shw: PAE page table; Gst: 32-bit page table. */
1359 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1360 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1361 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1362 /** Shw: PAE page table; Gst: PAE page table. */
1363 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1364 /** Shw: PAE page table; Gst: 2MB page. */
1365 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1366
1367 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1368 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1369 /** Shw: PAE page directory; Gst: PAE page directory. */
1370 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1371
1372 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1373 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1374 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1375 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1376 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1377 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1378 /** Shw: 64-bit page directory table; Gst: no paging */
1379 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1380
1381 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1382 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1383
1384 /** Shw: EPT page directory pointer table; Gst: no paging */
1385 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1386 /** Shw: EPT page directory table; Gst: no paging */
1387 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1388 /** Shw: EPT page table; Gst: no paging */
1389 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1390
1391 /** Shw: Root 32-bit page directory. */
1392 PGMPOOLKIND_ROOT_32BIT_PD,
1393 /** Shw: Root PAE page directory */
1394 PGMPOOLKIND_ROOT_PAE_PD,
1395 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1396 PGMPOOLKIND_ROOT_PDPT,
1397 /** Shw: Root Nested paging table. */
1398 PGMPOOLKIND_ROOT_NESTED,
1399
1400 /** The last valid entry. */
1401 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1402} PGMPOOLKIND;
1403
1404
1405/**
1406 * The tracking data for a page in the pool.
1407 */
1408typedef struct PGMPOOLPAGE
1409{
1410 /** AVL node code with the (HC) physical address of this page. */
1411 AVLOHCPHYSNODECORE Core;
1412 /** Pointer to the HC mapping of the page. */
1413 R3R0PTRTYPE(void *) pvPageHC;
1414 /** The guest physical address. */
1415#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1416 uint32_t Alignment0;
1417#endif
1418 RTGCPHYS GCPhys;
1419 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1420 uint8_t enmKind;
1421 uint8_t bPadding;
1422 /** The index of this page. */
1423 uint16_t idx;
1424 /** The next entry in the list this page currently resides in.
1425 * It's either in the free list or in the GCPhys hash. */
1426 uint16_t iNext;
1427#ifdef PGMPOOL_WITH_USER_TRACKING
1428 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1429 uint16_t iUserHead;
1430 /** The number of present entries. */
1431 uint16_t cPresent;
1432 /** The first entry in the table which is present. */
1433 uint16_t iFirstPresent;
1434#endif
1435#ifdef PGMPOOL_WITH_MONITORING
1436 /** The number of modifications to the monitored page. */
1437 uint16_t cModifications;
1438 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1439 uint16_t iModifiedNext;
1440 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1441 uint16_t iModifiedPrev;
1442 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1443 uint16_t iMonitoredNext;
1444 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1445 uint16_t iMonitoredPrev;
1446#endif
1447#ifdef PGMPOOL_WITH_CACHE
1448 /** The next page in the age list. */
1449 uint16_t iAgeNext;
1450 /** The previous page in the age list. */
1451 uint16_t iAgePrev;
1452#endif /* PGMPOOL_WITH_CACHE */
1453 /** Used to indicate that the page is zeroed. */
1454 bool fZeroed;
1455 /** Used to indicate that a PT has non-global entries. */
1456 bool fSeenNonGlobal;
1457 /** Used to indicate that we're monitoring writes to the guest page. */
1458 bool fMonitored;
1459 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1460 * (All pages are in the age list.) */
1461 bool fCached;
1462 /** This is used by the R3 access handlers when invoked by an async thread.
1463 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1464 bool volatile fReusedFlushPending;
1465 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1466 * In these cases the access handler acts differently and will check
1467 * for mapping conflicts like the normal CR3 handler.
1468 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1469 * replaced by a list of pages which share access handler.
1470 */
1471 bool fCR3Mix;
1472} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1473
1474
1475#ifdef PGMPOOL_WITH_CACHE
1476/** The hash table size. */
1477# define PGMPOOL_HASH_SIZE 0x40
1478/** The hash function. */
1479# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1480#endif
1481
1482
1483/**
1484 * The shadow page pool instance data.
1485 *
1486 * It's all one big allocation made at init time, except for the
1487 * pages that is. The user nodes follows immediatly after the
1488 * page structures.
1489 */
1490typedef struct PGMPOOL
1491{
1492 /** The VM handle - HC Ptr. */
1493 R3R0PTRTYPE(PVM) pVMHC;
1494 /** The VM handle - GC Ptr. */
1495 RCPTRTYPE(PVM) pVMGC;
1496 /** The max pool size. This includes the special IDs. */
1497 uint16_t cMaxPages;
1498 /** The current pool size. */
1499 uint16_t cCurPages;
1500 /** The head of the free page list. */
1501 uint16_t iFreeHead;
1502 /* Padding. */
1503 uint16_t u16Padding;
1504#ifdef PGMPOOL_WITH_USER_TRACKING
1505 /** Head of the chain of free user nodes. */
1506 uint16_t iUserFreeHead;
1507 /** The number of user nodes we've allocated. */
1508 uint16_t cMaxUsers;
1509 /** The number of present page table entries in the entire pool. */
1510 uint32_t cPresent;
1511 /** Pointer to the array of user nodes - GC pointer. */
1512 RCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1513 /** Pointer to the array of user nodes - HC pointer. */
1514 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1515#endif /* PGMPOOL_WITH_USER_TRACKING */
1516#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1517 /** Head of the chain of free phys ext nodes. */
1518 uint16_t iPhysExtFreeHead;
1519 /** The number of user nodes we've allocated. */
1520 uint16_t cMaxPhysExts;
1521 /** Pointer to the array of physical xref extent - GC pointer. */
1522 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1523 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1524 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1525#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1526#ifdef PGMPOOL_WITH_CACHE
1527 /** Hash table for GCPhys addresses. */
1528 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1529 /** The head of the age list. */
1530 uint16_t iAgeHead;
1531 /** The tail of the age list. */
1532 uint16_t iAgeTail;
1533 /** Set if the cache is enabled. */
1534 bool fCacheEnabled;
1535#endif /* PGMPOOL_WITH_CACHE */
1536#ifdef PGMPOOL_WITH_MONITORING
1537 /** Head of the list of modified pages. */
1538 uint16_t iModifiedHead;
1539 /** The current number of modified pages. */
1540 uint16_t cModifiedPages;
1541 /** Access handler, GC. */
1542 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1543 /** Access handler, R0. */
1544 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1545 /** Access handler, R3. */
1546 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1547 /** The access handler description (HC ptr). */
1548 R3PTRTYPE(const char *) pszAccessHandler;
1549#endif /* PGMPOOL_WITH_MONITORING */
1550 /** The number of pages currently in use. */
1551 uint16_t cUsedPages;
1552#ifdef VBOX_WITH_STATISTICS
1553 /** The high wather mark for cUsedPages. */
1554 uint16_t cUsedPagesHigh;
1555 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1556 /** Profiling pgmPoolAlloc(). */
1557 STAMPROFILEADV StatAlloc;
1558 /** Profiling pgmPoolClearAll(). */
1559 STAMPROFILE StatClearAll;
1560 /** Profiling pgmPoolFlushAllInt(). */
1561 STAMPROFILE StatFlushAllInt;
1562 /** Profiling pgmPoolFlushPage(). */
1563 STAMPROFILE StatFlushPage;
1564 /** Profiling pgmPoolFree(). */
1565 STAMPROFILE StatFree;
1566 /** Profiling time spent zeroing pages. */
1567 STAMPROFILE StatZeroPage;
1568# ifdef PGMPOOL_WITH_USER_TRACKING
1569 /** Profiling of pgmPoolTrackDeref. */
1570 STAMPROFILE StatTrackDeref;
1571 /** Profiling pgmTrackFlushGCPhysPT. */
1572 STAMPROFILE StatTrackFlushGCPhysPT;
1573 /** Profiling pgmTrackFlushGCPhysPTs. */
1574 STAMPROFILE StatTrackFlushGCPhysPTs;
1575 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1576 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1577 /** Number of times we've been out of user records. */
1578 STAMCOUNTER StatTrackFreeUpOneUser;
1579# endif
1580# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1581 /** Profiling deref activity related tracking GC physical pages. */
1582 STAMPROFILE StatTrackDerefGCPhys;
1583 /** Number of linear searches for a HCPhys in the ram ranges. */
1584 STAMCOUNTER StatTrackLinearRamSearches;
1585 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1586 STAMCOUNTER StamTrackPhysExtAllocFailures;
1587# endif
1588# ifdef PGMPOOL_WITH_MONITORING
1589 /** Profiling the GC PT access handler. */
1590 STAMPROFILE StatMonitorGC;
1591 /** Times we've failed interpreting the instruction. */
1592 STAMCOUNTER StatMonitorGCEmulateInstr;
1593 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1594 STAMPROFILE StatMonitorGCFlushPage;
1595 /** Times we've detected fork(). */
1596 STAMCOUNTER StatMonitorGCFork;
1597 /** Profiling the GC access we've handled (except REP STOSD). */
1598 STAMPROFILE StatMonitorGCHandled;
1599 /** Times we've failed interpreting a patch code instruction. */
1600 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1601 /** Times we've failed interpreting a patch code instruction during flushing. */
1602 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1603 /** The number of times we've seen rep prefixes we can't handle. */
1604 STAMCOUNTER StatMonitorGCRepPrefix;
1605 /** Profiling the REP STOSD cases we've handled. */
1606 STAMPROFILE StatMonitorGCRepStosd;
1607
1608 /** Profiling the HC PT access handler. */
1609 STAMPROFILE StatMonitorHC;
1610 /** Times we've failed interpreting the instruction. */
1611 STAMCOUNTER StatMonitorHCEmulateInstr;
1612 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1613 STAMPROFILE StatMonitorHCFlushPage;
1614 /** Times we've detected fork(). */
1615 STAMCOUNTER StatMonitorHCFork;
1616 /** Profiling the HC access we've handled (except REP STOSD). */
1617 STAMPROFILE StatMonitorHCHandled;
1618 /** The number of times we've seen rep prefixes we can't handle. */
1619 STAMCOUNTER StatMonitorHCRepPrefix;
1620 /** Profiling the REP STOSD cases we've handled. */
1621 STAMPROFILE StatMonitorHCRepStosd;
1622 /** The number of times we're called in an async thread an need to flush. */
1623 STAMCOUNTER StatMonitorHCAsync;
1624 /** The high wather mark for cModifiedPages. */
1625 uint16_t cModifiedPagesHigh;
1626 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1627# endif
1628# ifdef PGMPOOL_WITH_CACHE
1629 /** The number of cache hits. */
1630 STAMCOUNTER StatCacheHits;
1631 /** The number of cache misses. */
1632 STAMCOUNTER StatCacheMisses;
1633 /** The number of times we've got a conflict of 'kind' in the cache. */
1634 STAMCOUNTER StatCacheKindMismatches;
1635 /** Number of times we've been out of pages. */
1636 STAMCOUNTER StatCacheFreeUpOne;
1637 /** The number of cacheable allocations. */
1638 STAMCOUNTER StatCacheCacheable;
1639 /** The number of uncacheable allocations. */
1640 STAMCOUNTER StatCacheUncacheable;
1641# endif
1642#elif HC_ARCH_BITS == 64
1643 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1644#endif
1645 /** The AVL tree for looking up a page by its HC physical address. */
1646 AVLOHCPHYSTREE HCPhysTree;
1647 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1648 /** Array of pages. (cMaxPages in length)
1649 * The Id is the index into thist array.
1650 */
1651 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1652} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1653
1654
1655/** @def PGMPOOL_PAGE_2_PTR
1656 * Maps a pool page pool into the current context.
1657 *
1658 * @returns VBox status code.
1659 * @param pVM The VM handle.
1660 * @param pPage The pool page.
1661 *
1662 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1663 * small page window employeed by that function. Be careful.
1664 * @remark There is no need to assert on the result.
1665 */
1666#ifdef IN_GC
1667# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1668#else
1669# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1670#endif
1671
1672
1673/**
1674 * Trees are using self relative offsets as pointers.
1675 * So, all its data, including the root pointer, must be in the heap for HC and GC
1676 * to have the same layout.
1677 */
1678typedef struct PGMTREES
1679{
1680 /** Physical access handlers (AVL range+offsetptr tree). */
1681 AVLROGCPHYSTREE PhysHandlers;
1682 /** Virtual access handlers (AVL range + GC ptr tree). */
1683 AVLROGCPTRTREE VirtHandlers;
1684 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1685 AVLROGCPHYSTREE PhysToVirtHandlers;
1686 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1687 AVLROGCPTRTREE HyperVirtHandlers;
1688} PGMTREES;
1689/** Pointer to PGM trees. */
1690typedef PGMTREES *PPGMTREES;
1691
1692
1693/** @name Paging mode macros
1694 * @{ */
1695#ifdef IN_GC
1696# define PGM_CTX(a,b) a##GC##b
1697# define PGM_CTX_STR(a,b) a "GC" b
1698# define PGM_CTX_DECL(type) VMMRCDECL(type)
1699#else
1700# ifdef IN_RING3
1701# define PGM_CTX(a,b) a##R3##b
1702# define PGM_CTX_STR(a,b) a "R3" b
1703# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1704# else
1705# define PGM_CTX(a,b) a##R0##b
1706# define PGM_CTX_STR(a,b) a "R0" b
1707# define PGM_CTX_DECL(type) VMMDECL(type)
1708# endif
1709#endif
1710
1711#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1712#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1713#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1714#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1715#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1716#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1717#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1718#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1719#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1720#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1721#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1722#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1723#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1724#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1725#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1726#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1727#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1728
1729#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1730#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1731#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1732#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1733#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1734#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1735#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1736#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1737#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1738#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1739#define PGM_SHW_NAME_GC_NESTED_STR(name) "pgmGCShwNested" #name
1740#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1741#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1742#define PGM_SHW_NAME_GC_EPT_STR(name) "pgmGCShwEPT" #name
1743#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1744#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1745#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1746
1747/* Shw_Gst */
1748#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1749#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1750#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1751#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1752#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1753#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1754#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1755#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1756#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1757#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1758#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1759#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1760#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1761#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1762#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1763#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1764#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1765#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1766#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1767
1768#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1769#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1770#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1771#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1772#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1773#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1774#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1775#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1776#define PGM_BTH_NAME_GC_NESTED_REAL_STR(name) "pgmGCBthNestedReal" #name
1777#define PGM_BTH_NAME_GC_NESTED_PROT_STR(name) "pgmGCBthNestedProt" #name
1778#define PGM_BTH_NAME_GC_NESTED_32BIT_STR(name) "pgmGCBthNested32Bit" #name
1779#define PGM_BTH_NAME_GC_NESTED_PAE_STR(name) "pgmGCBthNestedPAE" #name
1780#define PGM_BTH_NAME_GC_NESTED_AMD64_STR(name) "pgmGCBthNestedAMD64" #name
1781#define PGM_BTH_NAME_GC_EPT_REAL_STR(name) "pgmGCBthEPTReal" #name
1782#define PGM_BTH_NAME_GC_EPT_PROT_STR(name) "pgmGCBthEPTProt" #name
1783#define PGM_BTH_NAME_GC_EPT_32BIT_STR(name) "pgmGCBthEPT32Bit" #name
1784#define PGM_BTH_NAME_GC_EPT_PAE_STR(name) "pgmGCBthEPTPAE" #name
1785#define PGM_BTH_NAME_GC_EPT_AMD64_STR(name) "pgmGCBthEPTAMD64" #name
1786#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1787#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1788#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1789#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1790#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1791#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1792#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1793#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1794#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1795#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1796#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1797#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1798#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1799#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1800#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1801#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1802#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1803#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1804#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1805
1806#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1807#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1808/** @} */
1809
1810/**
1811 * Data for each paging mode.
1812 */
1813typedef struct PGMMODEDATA
1814{
1815 /** The guest mode type. */
1816 uint32_t uGstType;
1817 /** The shadow mode type. */
1818 uint32_t uShwType;
1819
1820 /** @name Function pointers for Shadow paging.
1821 * @{
1822 */
1823 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1824 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1825 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1826 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1827
1828 DECLRCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1829 DECLRCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1830
1831 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1832 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1833 /** @} */
1834
1835 /** @name Function pointers for Guest paging.
1836 * @{
1837 */
1838 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1839 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1840 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1841 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1842 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1843 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1844 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1845 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1846 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1847 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1848 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1849 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1850 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1851
1852 DECLRCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1853 DECLRCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1854 DECLRCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1855 DECLRCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1856 DECLRCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1857 DECLRCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1858 DECLRCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1859 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1860 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1861
1862 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1863 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1864 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1865 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1866 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1867 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1868 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1869 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1870 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1871 /** @} */
1872
1873 /** @name Function pointers for Both Shadow and Guest paging.
1874 * @{
1875 */
1876 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1877 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1878 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1879 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1880 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1881 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1882 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1883#ifdef VBOX_STRICT
1884 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1885#endif
1886
1887 DECLRCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1888 DECLRCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1889 DECLRCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1890 DECLRCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1891 DECLRCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1892 DECLRCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1893#ifdef VBOX_STRICT
1894 DECLRCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1895#endif
1896
1897 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1898 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1899 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1900 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1901 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1902 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1903#ifdef VBOX_STRICT
1904 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1905#endif
1906 /** @} */
1907} PGMMODEDATA, *PPGMMODEDATA;
1908
1909
1910
1911/**
1912 * Converts a PGM pointer into a VM pointer.
1913 * @returns Pointer to the VM structure the PGM is part of.
1914 * @param pPGM Pointer to PGM instance data.
1915 */
1916#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1917
1918/**
1919 * PGM Data (part of VM)
1920 */
1921typedef struct PGM
1922{
1923 /** Offset to the VM structure. */
1924 RTINT offVM;
1925
1926 /*
1927 * This will be redefined at least two more times before we're done, I'm sure.
1928 * The current code is only to get on with the coding.
1929 * - 2004-06-10: initial version, bird.
1930 * - 2004-07-02: 1st time, bird.
1931 * - 2004-10-18: 2nd time, bird.
1932 * - 2005-07-xx: 3rd time, bird.
1933 */
1934
1935 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1936 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1937 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1938 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1939
1940 /** The host paging mode. (This is what SUPLib reports.) */
1941 SUPPAGINGMODE enmHostMode;
1942 /** The shadow paging mode. */
1943 PGMMODE enmShadowMode;
1944 /** The guest paging mode. */
1945 PGMMODE enmGuestMode;
1946
1947 /** The current physical address representing in the guest CR3 register. */
1948 RTGCPHYS GCPhysCR3;
1949 /** Pointer to the 5 page CR3 content mapping.
1950 * The first page is always the CR3 (in some form) while the 4 other pages
1951 * are used of the PDs in PAE mode. */
1952 RTGCPTR GCPtrCR3Mapping;
1953#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1954 uint32_t u32Alignment;
1955#endif
1956 /** The physical address of the currently monitored guest CR3 page.
1957 * When this value is NIL_RTGCPHYS no page is being monitored. */
1958 RTGCPHYS GCPhysGstCR3Monitored;
1959
1960 /** @name 32-bit Guest Paging.
1961 * @{ */
1962 /** The guest's page directory, HC pointer. */
1963 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1964 /** The guest's page directory, static GC mapping. */
1965 RCPTRTYPE(PX86PD) pGuestPDGC;
1966 /** @} */
1967
1968 /** @name PAE Guest Paging.
1969 * @{ */
1970 /** The guest's page directory pointer table, static GC mapping. */
1971 RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1972 /** The guest's page directory pointer table, HC pointer. */
1973 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1974 /** The guest's page directories, HC pointers.
1975 * These are individual pointers and don't have to be adjecent.
1976 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1977 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1978 /** The guest's page directories, static GC mapping.
1979 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1980 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1981 RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1982 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1983 RTGCPHYS aGCPhysGstPaePDs[4];
1984 /** The physical addresses of the monitored guest page directories (PAE). */
1985 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1986 /** @} */
1987
1988 /** @name AMD64 Guest Paging.
1989 * @{ */
1990 /** The guest's page directory pointer table, HC pointer. */
1991 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1992 /** @} */
1993
1994 /** @name 32-bit Shadow Paging
1995 * @{ */
1996 /** The 32-Bit PD - HC Ptr. */
1997 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1998 /** The 32-Bit PD - GC Ptr. */
1999 RCPTRTYPE(PX86PD) pGC32BitPD;
2000#if HC_ARCH_BITS == 64
2001 uint32_t u32Padding1; /**< alignment padding. */
2002#endif
2003 /** The Physical Address (HC) of the 32-Bit PD. */
2004 RTHCPHYS HCPhys32BitPD;
2005 /** @} */
2006
2007 /** @name PAE Shadow Paging
2008 * @{ */
2009 /** The four PDs for the low 4GB - HC Ptr.
2010 * Even though these are 4 pointers, what they point at is a single table.
2011 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2012 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2013 /** The four PDs for the low 4GB - GC Ptr.
2014 * Same kind of mapping as apHCPaePDs. */
2015 RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
2016 /** The Physical Address (HC) of the four PDs for the low 4GB.
2017 * These are *NOT* 4 contiguous pages. */
2018 RTHCPHYS aHCPhysPaePDs[4];
2019 /** The PAE PDP - HC Ptr. */
2020 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
2021 /** The Physical Address (HC) of the PAE PDPT. */
2022 RTHCPHYS HCPhysPaePDPT;
2023 /** The PAE PDPT - GC Ptr. */
2024 RCPTRTYPE(PX86PDPT) pGCPaePDPT;
2025 /** @} */
2026
2027 /** @name AMD64 Shadow Paging
2028 * Extends PAE Paging.
2029 * @{ */
2030#if HC_ARCH_BITS == 64
2031 RTRCPTR alignment5; /**< structure size alignment. */
2032#endif
2033 /** The Page Map Level 4 table - HC Ptr. */
2034 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2035 /** The Physical Address (HC) of the Page Map Level 4 table. */
2036 RTHCPHYS HCPhysPaePML4;
2037 /** The pgm pool page descriptor for the current active CR3. */
2038 R3R0PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2039
2040 /** @}*/
2041
2042 /** @name Nested Shadow Paging
2043 * @{ */
2044 /** Root table; format depends on the host paging mode (AMD-V) or EPT */
2045 R3R0PTRTYPE(void *) pHCNestedRoot;
2046 /** The Physical Address (HC) of the nested paging root. */
2047 RTHCPHYS HCPhysNestedRoot;
2048
2049 /** @name Function pointers for Shadow paging.
2050 * @{
2051 */
2052 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2053 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2054 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2055 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2056
2057 DECLRCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2058 DECLRCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2059
2060 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2061 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2062
2063 /** @} */
2064
2065 /** @name Function pointers for Guest paging.
2066 * @{
2067 */
2068 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2069 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2070 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2071 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2072 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2073 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2074 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2075 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2076 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2077 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2078 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2079 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2080 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2081
2082 DECLRCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2083 DECLRCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2084 DECLRCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2085 DECLRCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2086 DECLRCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2087 DECLRCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2088 DECLRCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2089 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2090 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2091#if HC_ARCH_BITS == 64
2092 RTRCPTR alignment3; /**< structure size alignment. */
2093#endif
2094
2095 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2096 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2097 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2098 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2099 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2100 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2101 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2102 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2103 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2104 /** @} */
2105
2106 /** @name Function pointers for Both Shadow and Guest paging.
2107 * @{
2108 */
2109 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2110 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2111 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2112 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2113 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2114 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2115 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2116 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2117
2118 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2119 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2120 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2121 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2122 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2123 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2124 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2125
2126 DECLRCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2127 DECLRCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2128 DECLRCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2129 DECLRCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2130 DECLRCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2131 DECLRCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2132 DECLRCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2133#if HC_ARCH_BITS == 64
2134 RTRCPTR alignment2; /**< structure size alignment. */
2135#endif
2136 /** @} */
2137
2138 /** Pointer to SHW+GST mode data (function pointers).
2139 * The index into this table is made up from */
2140 R3PTRTYPE(PPGMMODEDATA) paModeData;
2141
2142 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2143 * This is sorted by physical address and contains no overlapping ranges. */
2144 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2145 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2146 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2147 /** GC pointer corresponding to PGM::pRamRangesR3. */
2148 RCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2149 /** The configured RAM size. */
2150 RTUINT cbRamSize;
2151
2152 /** Pointer to the list of ROM ranges - for R3.
2153 * This is sorted by physical address and contains no overlapping ranges. */
2154 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2155 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2156 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2157 /** GC pointer corresponding to PGM::pRomRangesR3. */
2158 RCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2159 /** Alignment padding. */
2160 RTRCPTR GCPtrPadding2;
2161
2162 /** Pointer to the list of MMIO2 ranges - for R3.
2163 * Registration order. */
2164 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2165
2166 /** PGM offset based trees - HC Ptr. */
2167 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2168 /** PGM offset based trees - GC Ptr. */
2169 RCPTRTYPE(PPGMTREES) pTreesGC;
2170
2171 /** Linked list of GC mappings - for GC.
2172 * The list is sorted ascending on address.
2173 */
2174 RCPTRTYPE(PPGMMAPPING) pMappingsGC;
2175 /** Linked list of GC mappings - for HC.
2176 * The list is sorted ascending on address.
2177 */
2178 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2179 /** Linked list of GC mappings - for R0.
2180 * The list is sorted ascending on address.
2181 */
2182 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2183
2184 /** If set no conflict checks are required. (boolean) */
2185 bool fMappingsFixed;
2186 /** If set, then no mappings are put into the shadow page table. (boolean) */
2187 bool fDisableMappings;
2188 /** Size of fixed mapping */
2189 uint32_t cbMappingFixed;
2190 /** Base address (GC) of fixed mapping */
2191 RTGCPTR GCPtrMappingFixed;
2192#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2193 uint32_t u32Padding0; /**< alignment padding. */
2194#endif
2195
2196
2197 /** @name Intermediate Context
2198 * @{ */
2199 /** Pointer to the intermediate page directory - Normal. */
2200 R3PTRTYPE(PX86PD) pInterPD;
2201 /** Pointer to the intermedate page tables - Normal.
2202 * There are two page tables, one for the identity mapping and one for
2203 * the host context mapping (of the core code). */
2204 R3PTRTYPE(PX86PT) apInterPTs[2];
2205 /** Pointer to the intermedate page tables - PAE. */
2206 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2207 /** Pointer to the intermedate page directory - PAE. */
2208 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2209 /** Pointer to the intermedate page directory - PAE. */
2210 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2211 /** Pointer to the intermedate page-map level 4 - AMD64. */
2212 R3PTRTYPE(PX86PML4) pInterPaePML4;
2213 /** Pointer to the intermedate page directory - AMD64. */
2214 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2215 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2216 RTHCPHYS HCPhysInterPD;
2217 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2218 RTHCPHYS HCPhysInterPaePDPT;
2219 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2220 RTHCPHYS HCPhysInterPaePML4;
2221 /** @} */
2222
2223 /** Base address of the dynamic page mapping area.
2224 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2225 */
2226 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2227 /** The index of the last entry used in the dynamic page mapping area. */
2228 RTUINT iDynPageMapLast;
2229 /** Cache containing the last entries in the dynamic page mapping area.
2230 * The cache size is covering half of the mapping area. */
2231 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2232
2233 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2234 RTGCPHYS GCPhys4MBPSEMask;
2235
2236 /** A20 gate mask.
2237 * Our current approach to A20 emulation is to let REM do it and don't bother
2238 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2239 * But whould need arrise, we'll subject physical addresses to this mask. */
2240 RTGCPHYS GCPhysA20Mask;
2241 /** A20 gate state - boolean! */
2242 RTUINT fA20Enabled;
2243
2244 /** What needs syncing (PGM_SYNC_*).
2245 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2246 * PGMFlushTLB, and PGMR3Load. */
2247 RTUINT fSyncFlags;
2248
2249 /** PGM critical section.
2250 * This protects the physical & virtual access handlers, ram ranges,
2251 * and the page flag updating (some of it anyway).
2252 */
2253 PDMCRITSECT CritSect;
2254
2255 /** Shadow Page Pool - HC Ptr. */
2256 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2257 /** Shadow Page Pool - GC Ptr. */
2258 RCPTRTYPE(PPGMPOOL) pPoolGC;
2259
2260 /** We're not in a state which permits writes to guest memory.
2261 * (Only used in strict builds.) */
2262 bool fNoMorePhysWrites;
2263
2264 /** Flush the cache on the next access. */
2265 bool fPhysCacheFlushPending;
2266/** @todo r=bird: Fix member names!*/
2267 /** PGMPhysRead cache */
2268 PGMPHYSCACHE pgmphysreadcache;
2269 /** PGMPhysWrite cache */
2270 PGMPHYSCACHE pgmphyswritecache;
2271
2272 /**
2273 * Data associated with managing the ring-3 mappings of the allocation chunks.
2274 */
2275 struct
2276 {
2277 /** The chunk tree, ordered by chunk id. */
2278 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2279 /** The chunk mapping TLB. */
2280 PGMCHUNKR3MAPTLB Tlb;
2281 /** The number of mapped chunks. */
2282 uint32_t c;
2283 /** The maximum number of mapped chunks.
2284 * @cfgm PGM/MaxRing3Chunks */
2285 uint32_t cMax;
2286 /** The chunk age tree, ordered by ageing sequence number. */
2287 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2288 /** The current time. */
2289 uint32_t iNow;
2290 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2291 uint32_t AgeingCountdown;
2292 } ChunkR3Map;
2293
2294 /**
2295 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2296 */
2297 PGMPAGER3MAPTLB PhysTlbHC;
2298
2299 /** @name The zero page.
2300 * @{ */
2301 /** The host physical address of the zero page. */
2302 RTHCPHYS HCPhysZeroPg;
2303 /** The ring-3 mapping of the zero page. */
2304 RTR3PTR pvZeroPgR3;
2305 /** The ring-0 mapping of the zero page. */
2306 RTR0PTR pvZeroPgR0;
2307 /** The GC mapping of the zero page. */
2308 RTGCPTR pvZeroPgGC;
2309#if GC_ARCH_BITS != 32
2310 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2311#endif
2312 /** @}*/
2313
2314 /** The number of handy pages. */
2315 uint32_t cHandyPages;
2316 /**
2317 * Array of handy pages.
2318 *
2319 * This array is used in a two way communication between pgmPhysAllocPage
2320 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2321 * an intermediary.
2322 *
2323 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2324 * (The current size of 32 pages, means 128 KB of handy memory.)
2325 */
2326 GMMPAGEDESC aHandyPages[32];
2327
2328 /** @name Release Statistics
2329 * @{ */
2330 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2331 uint32_t cPrivatePages; /**< The number of private pages. */
2332 uint32_t cSharedPages; /**< The number of shared pages. */
2333 uint32_t cZeroPages; /**< The number of zero backed pages. */
2334 /** The number of times the guest has switched mode since last reset or statistics reset. */
2335 STAMCOUNTER cGuestModeChanges;
2336 /** @} */
2337
2338#ifdef VBOX_WITH_STATISTICS
2339 /** GC: Which statistic this \#PF should be attributed to. */
2340 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2341 RTRCPTR padding0;
2342 /** HC: Which statistic this \#PF should be attributed to. */
2343 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2344 RTHCPTR padding1;
2345 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2346 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2347 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2348 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2349 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2350 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2351 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2352 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2353 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2354 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2355 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2356 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2357 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2358
2359 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2360 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2361
2362 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2363 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2364 STAMCOUNTER StatGCTrap0eUSWrite;
2365 STAMCOUNTER StatGCTrap0eUSReserved;
2366 STAMCOUNTER StatGCTrap0eUSNXE;
2367 STAMCOUNTER StatGCTrap0eUSRead;
2368
2369 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2370 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2371 STAMCOUNTER StatGCTrap0eSVWrite;
2372 STAMCOUNTER StatGCTrap0eSVReserved;
2373 STAMCOUNTER StatGCTrap0eSNXE;
2374
2375 STAMCOUNTER StatTrap0eWPEmulGC;
2376 STAMCOUNTER StatTrap0eWPEmulR3;
2377
2378 STAMCOUNTER StatGCTrap0eUnhandled;
2379 STAMCOUNTER StatGCTrap0eMap;
2380
2381 /** GC: PGMSyncPT() profiling. */
2382 STAMPROFILE StatGCSyncPT;
2383 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2384 STAMCOUNTER StatGCSyncPTAlloc;
2385 /** GC: The number of times PGMSyncPT() detected conflicts. */
2386 STAMCOUNTER StatGCSyncPTConflict;
2387 /** GC: The number of times PGMSyncPT() failed. */
2388 STAMCOUNTER StatGCSyncPTFailed;
2389 /** GC: PGMGCInvalidatePage() profiling. */
2390 STAMPROFILE StatGCInvalidatePage;
2391 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2392 STAMCOUNTER StatGCInvalidatePage4KBPages;
2393 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2394 STAMCOUNTER StatGCInvalidatePage4MBPages;
2395 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2396 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2397 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2398 STAMCOUNTER StatGCInvalidatePagePDNAs;
2399 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2400 STAMCOUNTER StatGCInvalidatePagePDNPs;
2401 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2402 STAMCOUNTER StatGCInvalidatePagePDMappings;
2403 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2404 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2405 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2406 STAMCOUNTER StatGCInvalidatePageSkipped;
2407 /** GC: The number of times user page is out of sync was detected in GC. */
2408 STAMCOUNTER StatGCPageOutOfSyncUser;
2409 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2410 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2411 /** GC: The number of dynamic page mapping cache hits */
2412 STAMCOUNTER StatDynMapCacheMisses;
2413 /** GC: The number of dynamic page mapping cache misses */
2414 STAMCOUNTER StatDynMapCacheHits;
2415 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2416 STAMCOUNTER StatGCGuestCR3WriteHandled;
2417 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2418 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2419 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2420 STAMCOUNTER StatGCGuestCR3WriteConflict;
2421 /** GC: Number of out-of-sync handled pages. */
2422 STAMCOUNTER StatHandlersOutOfSync;
2423 /** GC: Number of traps due to physical access handlers. */
2424 STAMCOUNTER StatHandlersPhysical;
2425 /** GC: Number of traps due to virtual access handlers. */
2426 STAMCOUNTER StatHandlersVirtual;
2427 /** GC: Number of traps due to virtual access handlers found by physical address. */
2428 STAMCOUNTER StatHandlersVirtualByPhys;
2429 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2430 STAMCOUNTER StatHandlersVirtualUnmarked;
2431 /** GC: Number of traps due to access outside range of monitored page(s). */
2432 STAMCOUNTER StatHandlersUnhandled;
2433 /** GC: Number of traps due to access to invalid physical memory. */
2434 STAMCOUNTER StatHandlersInvalid;
2435
2436 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2437 STAMCOUNTER StatGCGuestROMWriteHandled;
2438 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2439 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2440
2441 /** HC: PGMR3InvalidatePage() profiling. */
2442 STAMPROFILE StatHCInvalidatePage;
2443 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2444 STAMCOUNTER StatHCInvalidatePage4KBPages;
2445 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2446 STAMCOUNTER StatHCInvalidatePage4MBPages;
2447 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2448 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2449 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2450 STAMCOUNTER StatHCInvalidatePagePDNAs;
2451 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2452 STAMCOUNTER StatHCInvalidatePagePDNPs;
2453 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2454 STAMCOUNTER StatHCInvalidatePagePDMappings;
2455 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2456 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2457 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2458 STAMCOUNTER StatHCInvalidatePageSkipped;
2459 /** HC: PGMR3SyncPT() profiling. */
2460 STAMPROFILE StatHCSyncPT;
2461 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2462 STAMPROFILE StatHCResolveConflict;
2463 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2464 STAMCOUNTER StatHCDetectedConflicts;
2465 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2466 STAMCOUNTER StatHCGuestPDWrite;
2467 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2468 STAMCOUNTER StatHCGuestPDWriteConflict;
2469
2470 /** HC: The number of pages marked not present for accessed bit emulation. */
2471 STAMCOUNTER StatHCAccessedPage;
2472 /** HC: The number of pages marked read-only for dirty bit tracking. */
2473 STAMCOUNTER StatHCDirtyPage;
2474 /** HC: The number of pages marked read-only for dirty bit tracking. */
2475 STAMCOUNTER StatHCDirtyPageBig;
2476 /** HC: The number of traps generated for dirty bit tracking. */
2477 STAMCOUNTER StatHCDirtyPageTrap;
2478 /** HC: The number of pages already dirty or readonly. */
2479 STAMCOUNTER StatHCDirtyPageSkipped;
2480
2481 /** GC: The number of pages marked not present for accessed bit emulation. */
2482 STAMCOUNTER StatGCAccessedPage;
2483 /** GC: The number of pages marked read-only for dirty bit tracking. */
2484 STAMCOUNTER StatGCDirtyPage;
2485 /** GC: The number of pages marked read-only for dirty bit tracking. */
2486 STAMCOUNTER StatGCDirtyPageBig;
2487 /** GC: The number of traps generated for dirty bit tracking. */
2488 STAMCOUNTER StatGCDirtyPageTrap;
2489 /** GC: The number of pages already dirty or readonly. */
2490 STAMCOUNTER StatGCDirtyPageSkipped;
2491 /** GC: The number of pages marked dirty because of write accesses. */
2492 STAMCOUNTER StatGCDirtiedPage;
2493 /** GC: The number of pages already marked dirty because of write accesses. */
2494 STAMCOUNTER StatGCPageAlreadyDirty;
2495 /** GC: The number of real pages faults during dirty bit tracking. */
2496 STAMCOUNTER StatGCDirtyTrackRealPF;
2497
2498 /** GC: Profiling of the PGMTrackDirtyBit() body */
2499 STAMPROFILE StatGCDirtyBitTracking;
2500 /** HC: Profiling of the PGMTrackDirtyBit() body */
2501 STAMPROFILE StatHCDirtyBitTracking;
2502
2503 /** GC: Profiling of the PGMGstModifyPage() body */
2504 STAMPROFILE StatGCGstModifyPage;
2505 /** HC: Profiling of the PGMGstModifyPage() body */
2506 STAMPROFILE StatHCGstModifyPage;
2507
2508 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2509 STAMCOUNTER StatGCSyncPagePDNAs;
2510 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2511 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2512 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2513 STAMCOUNTER StatHCSyncPagePDNAs;
2514 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2515 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2516
2517 STAMCOUNTER StatSynPT4kGC;
2518 STAMCOUNTER StatSynPT4kHC;
2519 STAMCOUNTER StatSynPT4MGC;
2520 STAMCOUNTER StatSynPT4MHC;
2521
2522 /** Profiling of the PGMFlushTLB() body. */
2523 STAMPROFILE StatFlushTLB;
2524 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2525 STAMCOUNTER StatFlushTLBNewCR3;
2526 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2527 STAMCOUNTER StatFlushTLBNewCR3Global;
2528 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2529 STAMCOUNTER StatFlushTLBSameCR3;
2530 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2531 STAMCOUNTER StatFlushTLBSameCR3Global;
2532
2533 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2534 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2535 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2536 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2537 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2538 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2539 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2540 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2541 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2542 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2543 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2544 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2545
2546 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2547 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2548 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2549 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2550 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2551 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2552 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2553 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2554 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2555 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2556 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2557 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2558
2559 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2560 STAMPROFILE StatVirtHandleSearchByPhysGC;
2561 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2562 STAMPROFILE StatVirtHandleSearchByPhysHC;
2563 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2564 STAMCOUNTER StatHandlePhysicalReset;
2565
2566 STAMPROFILE StatCheckPageFault;
2567 STAMPROFILE StatLazySyncPT;
2568 STAMPROFILE StatMapping;
2569 STAMPROFILE StatOutOfSync;
2570 STAMPROFILE StatHandlers;
2571 STAMPROFILE StatEIPHandlers;
2572 STAMPROFILE StatHCPrefetch;
2573
2574# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2575 /** The number of first time shadowings. */
2576 STAMCOUNTER StatTrackVirgin;
2577 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2578 STAMCOUNTER StatTrackAliased;
2579 /** The number of times we're tracking using cRef2. */
2580 STAMCOUNTER StatTrackAliasedMany;
2581 /** The number of times we're hitting pages which has overflowed cRef2. */
2582 STAMCOUNTER StatTrackAliasedLots;
2583 /** The number of times the extent list grows to long. */
2584 STAMCOUNTER StatTrackOverflows;
2585 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2586 STAMPROFILE StatTrackDeref;
2587# endif
2588
2589 /** Ring-3/0 page mapper TLB hits. */
2590 STAMCOUNTER StatPageHCMapTlbHits;
2591 /** Ring-3/0 page mapper TLB misses. */
2592 STAMCOUNTER StatPageHCMapTlbMisses;
2593 /** Ring-3/0 chunk mapper TLB hits. */
2594 STAMCOUNTER StatChunkR3MapTlbHits;
2595 /** Ring-3/0 chunk mapper TLB misses. */
2596 STAMCOUNTER StatChunkR3MapTlbMisses;
2597 /** Times a shared page has been replaced by a private one. */
2598 STAMCOUNTER StatPageReplaceShared;
2599 /** Times the zero page has been replaced by a private one. */
2600 STAMCOUNTER StatPageReplaceZero;
2601 /** The number of times we've executed GMMR3AllocateHandyPages. */
2602 STAMCOUNTER StatPageHandyAllocs;
2603
2604 /** Allocated mbs of guest ram */
2605 STAMCOUNTER StatDynRamTotal;
2606 /** Nr of pgmr3PhysGrowRange calls. */
2607 STAMCOUNTER StatDynRamGrow;
2608
2609 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2610 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2611 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2612#endif
2613} PGM, *PPGM;
2614
2615
2616/** @name PGM::fSyncFlags Flags
2617 * @{
2618 */
2619/** Updates the virtual access handler state bit in PGMPAGE. */
2620#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2621/** Always sync CR3. */
2622#define PGM_SYNC_ALWAYS RT_BIT(1)
2623/** Check monitoring on next CR3 (re)load and invalidate page. */
2624#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2625/** Clear the page pool (a light weight flush). */
2626#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2627/** @} */
2628
2629
2630__BEGIN_DECLS
2631
2632int pgmLock(PVM pVM);
2633void pgmUnlock(PVM pVM);
2634
2635VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2636VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2637
2638int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2639int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2640PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2641void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2642DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2643
2644void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2645int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2646DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2647#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2648void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2649#else
2650# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2651#endif
2652DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2653
2654
2655void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2656int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2657int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2658int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2659#ifdef IN_RING3
2660int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2661int pgmR3PhysRamReset(PVM pVM);
2662int pgmR3PhysRomReset(PVM pVM);
2663#ifndef VBOX_WITH_NEW_PHYS_CODE
2664int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2665#endif
2666
2667int pgmR3PoolInit(PVM pVM);
2668void pgmR3PoolRelocate(PVM pVM);
2669void pgmR3PoolReset(PVM pVM);
2670
2671#endif /* IN_RING3 */
2672#ifdef IN_GC
2673void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2674#endif
2675int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2676PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2677void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2678void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2679int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2680void pgmPoolFlushAll(PVM pVM);
2681void pgmPoolClearAll(PVM pVM);
2682int pgmPoolSyncCR3(PVM pVM);
2683void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2684void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2685int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2686PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2687void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2688void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2689uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2690void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2691#ifdef PGMPOOL_WITH_MONITORING
2692# ifdef IN_RING3
2693void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2694# else
2695void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2696# endif
2697int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2698void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2699void pgmPoolMonitorModifiedClearAll(PVM pVM);
2700int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2701int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2702#endif
2703
2704__END_DECLS
2705
2706
2707/**
2708 * Gets the PGMRAMRANGE structure for a guest page.
2709 *
2710 * @returns Pointer to the RAM range on success.
2711 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2712 *
2713 * @param pPGM PGM handle.
2714 * @param GCPhys The GC physical address.
2715 */
2716DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2717{
2718 /*
2719 * Optimize for the first range.
2720 */
2721 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2722 RTGCPHYS off = GCPhys - pRam->GCPhys;
2723 if (RT_UNLIKELY(off >= pRam->cb))
2724 {
2725 do
2726 {
2727 pRam = CTXALLSUFF(pRam->pNext);
2728 if (RT_UNLIKELY(!pRam))
2729 break;
2730 off = GCPhys - pRam->GCPhys;
2731 } while (off >= pRam->cb);
2732 }
2733 return pRam;
2734}
2735
2736
2737/**
2738 * Gets the PGMPAGE structure for a guest page.
2739 *
2740 * @returns Pointer to the page on success.
2741 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2742 *
2743 * @param pPGM PGM handle.
2744 * @param GCPhys The GC physical address.
2745 */
2746DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2747{
2748 /*
2749 * Optimize for the first range.
2750 */
2751 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2752 RTGCPHYS off = GCPhys - pRam->GCPhys;
2753 if (RT_UNLIKELY(off >= pRam->cb))
2754 {
2755 do
2756 {
2757 pRam = CTXALLSUFF(pRam->pNext);
2758 if (RT_UNLIKELY(!pRam))
2759 return NULL;
2760 off = GCPhys - pRam->GCPhys;
2761 } while (off >= pRam->cb);
2762 }
2763 return &pRam->aPages[off >> PAGE_SHIFT];
2764}
2765
2766
2767/**
2768 * Gets the PGMPAGE structure for a guest page.
2769 *
2770 * Old Phys code: Will make sure the page is present.
2771 *
2772 * @returns VBox status code.
2773 * @retval VINF_SUCCESS and a valid *ppPage on success.
2774 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2775 *
2776 * @param pPGM PGM handle.
2777 * @param GCPhys The GC physical address.
2778 * @param ppPage Where to store the page poitner on success.
2779 */
2780DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2781{
2782 /*
2783 * Optimize for the first range.
2784 */
2785 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2786 RTGCPHYS off = GCPhys - pRam->GCPhys;
2787 if (RT_UNLIKELY(off >= pRam->cb))
2788 {
2789 do
2790 {
2791 pRam = CTXALLSUFF(pRam->pNext);
2792 if (RT_UNLIKELY(!pRam))
2793 {
2794 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2795 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2796 }
2797 off = GCPhys - pRam->GCPhys;
2798 } while (off >= pRam->cb);
2799 }
2800 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2801#ifndef VBOX_WITH_NEW_PHYS_CODE
2802
2803 /*
2804 * Make sure it's present.
2805 */
2806 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2807 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2808 {
2809#ifdef IN_RING3
2810 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2811#else
2812 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2813#endif
2814 if (VBOX_FAILURE(rc))
2815 {
2816 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2817 return rc;
2818 }
2819 Assert(rc == VINF_SUCCESS);
2820 }
2821#endif
2822 return VINF_SUCCESS;
2823}
2824
2825
2826
2827
2828/**
2829 * Gets the PGMPAGE structure for a guest page.
2830 *
2831 * Old Phys code: Will make sure the page is present.
2832 *
2833 * @returns VBox status code.
2834 * @retval VINF_SUCCESS and a valid *ppPage on success.
2835 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2836 *
2837 * @param pPGM PGM handle.
2838 * @param GCPhys The GC physical address.
2839 * @param ppPage Where to store the page poitner on success.
2840 * @param ppRamHint Where to read and store the ram list hint.
2841 * The caller initializes this to NULL before the call.
2842 */
2843DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2844{
2845 RTGCPHYS off;
2846 PPGMRAMRANGE pRam = *ppRamHint;
2847 if ( !pRam
2848 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2849 {
2850 pRam = CTXALLSUFF(pPGM->pRamRanges);
2851 off = GCPhys - pRam->GCPhys;
2852 if (RT_UNLIKELY(off >= pRam->cb))
2853 {
2854 do
2855 {
2856 pRam = CTXALLSUFF(pRam->pNext);
2857 if (RT_UNLIKELY(!pRam))
2858 {
2859 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2860 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2861 }
2862 off = GCPhys - pRam->GCPhys;
2863 } while (off >= pRam->cb);
2864 }
2865 *ppRamHint = pRam;
2866 }
2867 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2868#ifndef VBOX_WITH_NEW_PHYS_CODE
2869
2870 /*
2871 * Make sure it's present.
2872 */
2873 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2874 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2875 {
2876#ifdef IN_RING3
2877 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2878#else
2879 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2880#endif
2881 if (VBOX_FAILURE(rc))
2882 {
2883 *ppPage = NULL; /* Shut up annoying smart ass. */
2884 return rc;
2885 }
2886 Assert(rc == VINF_SUCCESS);
2887 }
2888#endif
2889 return VINF_SUCCESS;
2890}
2891
2892
2893/**
2894 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2895 *
2896 * @returns Pointer to the page on success.
2897 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2898 *
2899 * @param pPGM PGM handle.
2900 * @param GCPhys The GC physical address.
2901 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2902 */
2903DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2904{
2905 /*
2906 * Optimize for the first range.
2907 */
2908 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2909 RTGCPHYS off = GCPhys - pRam->GCPhys;
2910 if (RT_UNLIKELY(off >= pRam->cb))
2911 {
2912 do
2913 {
2914 pRam = CTXALLSUFF(pRam->pNext);
2915 if (RT_UNLIKELY(!pRam))
2916 return NULL;
2917 off = GCPhys - pRam->GCPhys;
2918 } while (off >= pRam->cb);
2919 }
2920 *ppRam = pRam;
2921 return &pRam->aPages[off >> PAGE_SHIFT];
2922}
2923
2924
2925
2926
2927/**
2928 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2929 *
2930 * @returns Pointer to the page on success.
2931 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2932 *
2933 * @param pPGM PGM handle.
2934 * @param GCPhys The GC physical address.
2935 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2936 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2937 */
2938DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2939{
2940 /*
2941 * Optimize for the first range.
2942 */
2943 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2944 RTGCPHYS off = GCPhys - pRam->GCPhys;
2945 if (RT_UNLIKELY(off >= pRam->cb))
2946 {
2947 do
2948 {
2949 pRam = CTXALLSUFF(pRam->pNext);
2950 if (RT_UNLIKELY(!pRam))
2951 {
2952 *ppRam = NULL; /* Shut up silly GCC warnings. */
2953 *ppPage = NULL; /* ditto */
2954 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2955 }
2956 off = GCPhys - pRam->GCPhys;
2957 } while (off >= pRam->cb);
2958 }
2959 *ppRam = pRam;
2960 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2961#ifndef VBOX_WITH_NEW_PHYS_CODE
2962
2963 /*
2964 * Make sure it's present.
2965 */
2966 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2967 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2968 {
2969#ifdef IN_RING3
2970 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2971#else
2972 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2973#endif
2974 if (VBOX_FAILURE(rc))
2975 {
2976 *ppPage = NULL; /* Shut up silly GCC warnings. */
2977 *ppPage = NULL; /* ditto */
2978 return rc;
2979 }
2980 Assert(rc == VINF_SUCCESS);
2981
2982 }
2983#endif
2984 return VINF_SUCCESS;
2985}
2986
2987
2988/**
2989 * Convert GC Phys to HC Phys.
2990 *
2991 * @returns VBox status.
2992 * @param pPGM PGM handle.
2993 * @param GCPhys The GC physical address.
2994 * @param pHCPhys Where to store the corresponding HC physical address.
2995 *
2996 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2997 * Avoid when writing new code!
2998 */
2999DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3000{
3001 PPGMPAGE pPage;
3002 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3003 if (VBOX_FAILURE(rc))
3004 return rc;
3005 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3006 return VINF_SUCCESS;
3007}
3008
3009
3010#ifndef IN_GC
3011/**
3012 * Queries the Physical TLB entry for a physical guest page,
3013 * attemting to load the TLB entry if necessary.
3014 *
3015 * @returns VBox status code.
3016 * @retval VINF_SUCCESS on success
3017 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3018 * @param pPGM The PGM instance handle.
3019 * @param GCPhys The address of the guest page.
3020 * @param ppTlbe Where to store the pointer to the TLB entry.
3021 */
3022
3023DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3024{
3025 int rc;
3026 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3027 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3028 {
3029 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
3030 rc = VINF_SUCCESS;
3031 }
3032 else
3033 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3034 *ppTlbe = pTlbe;
3035 return rc;
3036}
3037#endif /* !IN_GC */
3038
3039
3040#ifndef VBOX_WITH_NEW_PHYS_CODE
3041/**
3042 * Convert GC Phys to HC Virt.
3043 *
3044 * @returns VBox status.
3045 * @param pPGM PGM handle.
3046 * @param GCPhys The GC physical address.
3047 * @param pHCPtr Where to store the corresponding HC virtual address.
3048 *
3049 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3050 */
3051DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3052{
3053 PPGMRAMRANGE pRam;
3054 PPGMPAGE pPage;
3055 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3056 if (VBOX_FAILURE(rc))
3057 {
3058 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3059 return rc;
3060 }
3061 RTGCPHYS off = GCPhys - pRam->GCPhys;
3062
3063 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3064 {
3065 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3066 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3067 return VINF_SUCCESS;
3068 }
3069 if (pRam->pvHC)
3070 {
3071 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3072 return VINF_SUCCESS;
3073 }
3074 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3075 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3076}
3077#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3078
3079
3080/**
3081 * Convert GC Phys to HC Virt.
3082 *
3083 * @returns VBox status.
3084 * @param PVM VM handle.
3085 * @param pRam Ram range
3086 * @param GCPhys The GC physical address.
3087 * @param pHCPtr Where to store the corresponding HC virtual address.
3088 *
3089 * @deprecated This will be eliminated. Don't use it.
3090 */
3091DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3092{
3093 RTGCPHYS off = GCPhys - pRam->GCPhys;
3094 Assert(off < pRam->cb);
3095
3096 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3097 {
3098 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3099 /* Physical chunk in dynamically allocated range not present? */
3100 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3101 {
3102#ifdef IN_RING3
3103 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3104#else
3105 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3106#endif
3107 if (rc != VINF_SUCCESS)
3108 {
3109 *pHCPtr = 0; /* GCC crap */
3110 return rc;
3111 }
3112 }
3113 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3114 return VINF_SUCCESS;
3115 }
3116 if (pRam->pvHC)
3117 {
3118 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3119 return VINF_SUCCESS;
3120 }
3121 *pHCPtr = 0; /* GCC crap */
3122 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3123}
3124
3125
3126/**
3127 * Convert GC Phys to HC Virt and HC Phys.
3128 *
3129 * @returns VBox status.
3130 * @param pPGM PGM handle.
3131 * @param GCPhys The GC physical address.
3132 * @param pHCPtr Where to store the corresponding HC virtual address.
3133 * @param pHCPhys Where to store the HC Physical address and its flags.
3134 *
3135 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3136 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3137 */
3138DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3139{
3140 PPGMRAMRANGE pRam;
3141 PPGMPAGE pPage;
3142 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3143 if (VBOX_FAILURE(rc))
3144 {
3145 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3146 *pHCPhys = 0; /* ditto */
3147 return rc;
3148 }
3149 RTGCPHYS off = GCPhys - pRam->GCPhys;
3150
3151 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3152 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3153 {
3154 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3155 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3156 return VINF_SUCCESS;
3157 }
3158 if (pRam->pvHC)
3159 {
3160 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3161 return VINF_SUCCESS;
3162 }
3163 *pHCPtr = 0;
3164 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3165}
3166
3167
3168/**
3169 * Clears flags associated with a RAM address.
3170 *
3171 * @returns VBox status code.
3172 * @param pPGM PGM handle.
3173 * @param GCPhys Guest context physical address.
3174 * @param fFlags fFlags to clear. (Bits 0-11.)
3175 */
3176DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3177{
3178 PPGMPAGE pPage;
3179 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3180 if (VBOX_FAILURE(rc))
3181 return rc;
3182
3183 fFlags &= ~X86_PTE_PAE_PG_MASK;
3184 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3185 return VINF_SUCCESS;
3186}
3187
3188
3189/**
3190 * Clears flags associated with a RAM address.
3191 *
3192 * @returns VBox status code.
3193 * @param pPGM PGM handle.
3194 * @param GCPhys Guest context physical address.
3195 * @param fFlags fFlags to clear. (Bits 0-11.)
3196 * @param ppRamHint Where to read and store the ram list hint.
3197 * The caller initializes this to NULL before the call.
3198 */
3199DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3200{
3201 PPGMPAGE pPage;
3202 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3203 if (VBOX_FAILURE(rc))
3204 return rc;
3205
3206 fFlags &= ~X86_PTE_PAE_PG_MASK;
3207 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3208 return VINF_SUCCESS;
3209}
3210
3211/**
3212 * Sets (bitwise OR) flags associated with a RAM address.
3213 *
3214 * @returns VBox status code.
3215 * @param pPGM PGM handle.
3216 * @param GCPhys Guest context physical address.
3217 * @param fFlags fFlags to set clear. (Bits 0-11.)
3218 */
3219DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3220{
3221 PPGMPAGE pPage;
3222 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3223 if (VBOX_FAILURE(rc))
3224 return rc;
3225
3226 fFlags &= ~X86_PTE_PAE_PG_MASK;
3227 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3228 return VINF_SUCCESS;
3229}
3230
3231
3232/**
3233 * Sets (bitwise OR) flags associated with a RAM address.
3234 *
3235 * @returns VBox status code.
3236 * @param pPGM PGM handle.
3237 * @param GCPhys Guest context physical address.
3238 * @param fFlags fFlags to set clear. (Bits 0-11.)
3239 * @param ppRamHint Where to read and store the ram list hint.
3240 * The caller initializes this to NULL before the call.
3241 */
3242DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3243{
3244 PPGMPAGE pPage;
3245 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3246 if (VBOX_FAILURE(rc))
3247 return rc;
3248
3249 fFlags &= ~X86_PTE_PAE_PG_MASK;
3250 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3251 return VINF_SUCCESS;
3252}
3253
3254/**
3255 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3256 * Takes PSE-36 into account.
3257 *
3258 * @returns guest physical address
3259 * @param pPGM Pointer to the PGM instance data.
3260 * @param Pde Guest Pde
3261 */
3262DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3263{
3264 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3265 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3266
3267 return GCPhys & pPGM->GCPhys4MBPSEMask;
3268}
3269
3270/**
3271 * Gets the page directory for the specified address.
3272 *
3273 * @returns Pointer to the page directory in question.
3274 * @returns NULL if the page directory is not present or on an invalid page.
3275 * @param pPGM Pointer to the PGM instance data.
3276 * @param GCPtr The address.
3277 */
3278DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3279{
3280 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3281 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3282 {
3283 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3284 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3285
3286 /* cache is out-of-sync. */
3287 PX86PDPAE pPD;
3288 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3289 if (VBOX_SUCCESS(rc))
3290 return pPD;
3291 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3292 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3293 }
3294 return NULL;
3295}
3296
3297
3298/**
3299 * Gets the page directory entry for the specified address.
3300 *
3301 * @returns Pointer to the page directory entry in question.
3302 * @returns NULL if the page directory is not present or on an invalid page.
3303 * @param pPGM Pointer to the PGM instance data.
3304 * @param GCPtr The address.
3305 */
3306DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3307{
3308 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3309 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3310 {
3311 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3312 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3313 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3314
3315 /* The cache is out-of-sync. */
3316 PX86PDPAE pPD;
3317 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3318 if (VBOX_SUCCESS(rc))
3319 return &pPD->a[iPD];
3320 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3321 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3322 }
3323 return NULL;
3324}
3325
3326
3327/**
3328 * Gets the page directory entry for the specified address.
3329 *
3330 * @returns The page directory entry in question.
3331 * @returns A non-present entry if the page directory is not present or on an invalid page.
3332 * @param pPGM Pointer to the PGM instance data.
3333 * @param GCPtr The address.
3334 */
3335DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3336{
3337 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3338 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3339 {
3340 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3341 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3342 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3343
3344 /* cache is out-of-sync. */
3345 PX86PDPAE pPD;
3346 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3347 if (VBOX_SUCCESS(rc))
3348 return pPD->a[iPD].u;
3349 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3350 }
3351 return 0ULL;
3352}
3353
3354
3355/**
3356 * Gets the page directory pointer table entry for the specified address
3357 * and returns the index into the page directory
3358 *
3359 * @returns Pointer to the page directory in question.
3360 * @returns NULL if the page directory is not present or on an invalid page.
3361 * @param pPGM Pointer to the PGM instance data.
3362 * @param GCPtr The address.
3363 * @param piPD Receives the index into the returned page directory
3364 */
3365DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3366{
3367 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3368 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3369 {
3370 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3371 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3372 {
3373 *piPD = iPD;
3374 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3375 }
3376
3377 /* cache is out-of-sync. */
3378 PX86PDPAE pPD;
3379 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3380 if (VBOX_SUCCESS(rc))
3381 {
3382 *piPD = iPD;
3383 return pPD;
3384 }
3385 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3386 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3387 }
3388 return NULL;
3389}
3390
3391#ifndef IN_GC
3392/**
3393 * Gets the page directory pointer entry for the specified address.
3394 *
3395 * @returns Pointer to the page directory pointer entry in question.
3396 * @returns NULL if the page directory is not present or on an invalid page.
3397 * @param pPGM Pointer to the PGM instance data.
3398 * @param GCPtr The address.
3399 * @param ppPml4e Page Map Level-4 Entry (out)
3400 */
3401DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3402{
3403 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3404
3405 Assert(pPGM->pGstPaePML4HC);
3406 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3407 if ((*ppPml4e)->n.u1Present)
3408 {
3409 PX86PDPT pPdpt;
3410 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3411 if (VBOX_FAILURE(rc))
3412 {
3413 AssertFailed();
3414 return NULL;
3415 }
3416 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3417 return &pPdpt->a[iPdPt];
3418 }
3419 return NULL;
3420}
3421
3422/**
3423 * Gets the page directory entry for the specified address.
3424 *
3425 * @returns The page directory entry in question.
3426 * @returns A non-present entry if the page directory is not present or on an invalid page.
3427 * @param pPGM Pointer to the PGM instance data.
3428 * @param GCPtr The address.
3429 * @param ppPml4e Page Map Level-4 Entry (out)
3430 * @param pPdpe Page directory pointer table entry (out)
3431 */
3432DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3433{
3434 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3435
3436 Assert(pPGM->pGstPaePML4HC);
3437 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3438 if ((*ppPml4e)->n.u1Present)
3439 {
3440 PX86PDPT pPdptTemp;
3441 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3442 if (VBOX_FAILURE(rc))
3443 {
3444 AssertFailed();
3445 return 0ULL;
3446 }
3447
3448 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3449 *pPdpe = pPdptTemp->a[iPdPt];
3450 if (pPdpe->n.u1Present)
3451 {
3452 PX86PDPAE pPD;
3453
3454 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3455 if (VBOX_FAILURE(rc))
3456 {
3457 AssertFailed();
3458 return 0ULL;
3459 }
3460 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3461 return pPD->a[iPD].u;
3462 }
3463 }
3464 return 0ULL;
3465}
3466
3467/**
3468 * Gets the page directory entry for the specified address.
3469 *
3470 * @returns The page directory entry in question.
3471 * @returns A non-present entry if the page directory is not present or on an invalid page.
3472 * @param pPGM Pointer to the PGM instance data.
3473 * @param GCPtr The address.
3474 */
3475DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3476{
3477 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3478
3479 Assert(pPGM->pGstPaePML4HC);
3480 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3481 {
3482 PX86PDPT pPdptTemp;
3483 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3484 if (VBOX_FAILURE(rc))
3485 {
3486 AssertFailed();
3487 return 0ULL;
3488 }
3489
3490 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3491 if (pPdptTemp->a[iPdPt].n.u1Present)
3492 {
3493 PX86PDPAE pPD;
3494
3495 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3496 if (VBOX_FAILURE(rc))
3497 {
3498 AssertFailed();
3499 return 0ULL;
3500 }
3501 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3502 return pPD->a[iPD].u;
3503 }
3504 }
3505 return 0ULL;
3506}
3507
3508/**
3509 * Gets the page directory entry for the specified address.
3510 *
3511 * @returns Pointer to the page directory entry in question.
3512 * @returns NULL if the page directory is not present or on an invalid page.
3513 * @param pPGM Pointer to the PGM instance data.
3514 * @param GCPtr The address.
3515 */
3516DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3517{
3518 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3519
3520 Assert(pPGM->pGstPaePML4HC);
3521 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3522 {
3523 PX86PDPT pPdptTemp;
3524 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3525 if (VBOX_FAILURE(rc))
3526 {
3527 AssertFailed();
3528 return NULL;
3529 }
3530
3531 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3532 if (pPdptTemp->a[iPdPt].n.u1Present)
3533 {
3534 PX86PDPAE pPD;
3535
3536 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3537 if (VBOX_FAILURE(rc))
3538 {
3539 AssertFailed();
3540 return NULL;
3541 }
3542 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3543 return &pPD->a[iPD];
3544 }
3545 }
3546 return NULL;
3547}
3548
3549
3550/**
3551 * Gets the GUEST page directory pointer for the specified address.
3552 *
3553 * @returns The page directory in question.
3554 * @returns NULL if the page directory is not present or on an invalid page.
3555 * @param pPGM Pointer to the PGM instance data.
3556 * @param GCPtr The address.
3557 * @param ppPml4e Page Map Level-4 Entry (out)
3558 * @param pPdpe Page directory pointer table entry (out)
3559 * @param piPD Receives the index into the returned page directory
3560 */
3561DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3562{
3563 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3564
3565 Assert(pPGM->pGstPaePML4HC);
3566 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3567 if ((*ppPml4e)->n.u1Present)
3568 {
3569 PX86PDPT pPdptTemp;
3570 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3571 if (VBOX_FAILURE(rc))
3572 {
3573 AssertFailed();
3574 return 0ULL;
3575 }
3576
3577 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3578 *pPdpe = pPdptTemp->a[iPdPt];
3579 if (pPdpe->n.u1Present)
3580 {
3581 PX86PDPAE pPD;
3582
3583 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3584 if (VBOX_FAILURE(rc))
3585 {
3586 AssertFailed();
3587 return 0ULL;
3588 }
3589 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3590 return pPD;
3591 }
3592 }
3593 return 0ULL;
3594}
3595
3596/**
3597 * Gets the GUEST page directory pointer for the specified address.
3598 *
3599 * @returns The page directory in question.
3600 * @returns NULL if the page directory is not present or on an invalid page.
3601 * @param pPGM Pointer to the PGM instance data.
3602 * @param GCPtr The address.
3603 * @param piPD Receives the index into the returned page directory
3604 */
3605DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3606{
3607 PX86PML4E pPml4e;
3608 PX86PDPE pPdpe;
3609 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3610
3611 Assert(pPGM->pGstPaePML4HC);
3612 pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3613 if (pPml4e->n.u1Present)
3614 {
3615 PX86PDPT pPdptTemp;
3616 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3617 if (VBOX_FAILURE(rc))
3618 {
3619 AssertFailed();
3620 return 0ULL;
3621 }
3622
3623 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3624 pPdpe = &pPdptTemp->a[iPdPt];
3625 if (pPdpe->n.u1Present)
3626 {
3627 PX86PDPAE pPD;
3628
3629 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3630 if (VBOX_FAILURE(rc))
3631 {
3632 AssertFailed();
3633 return 0ULL;
3634 }
3635 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3636 return pPD;
3637 }
3638 }
3639 return 0ULL;
3640}
3641
3642#endif /* !IN_GC */
3643
3644/**
3645 * Checks if any of the specified page flags are set for the given page.
3646 *
3647 * @returns true if any of the flags are set.
3648 * @returns false if all the flags are clear.
3649 * @param pPGM PGM handle.
3650 * @param GCPhys The GC physical address.
3651 * @param fFlags The flags to check for.
3652 */
3653DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3654{
3655 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3656 return pPage
3657 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3658}
3659
3660
3661/**
3662 * Gets the page state for a physical handler.
3663 *
3664 * @returns The physical handler page state.
3665 * @param pCur The physical handler in question.
3666 */
3667DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3668{
3669 switch (pCur->enmType)
3670 {
3671 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3672 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3673
3674 case PGMPHYSHANDLERTYPE_MMIO:
3675 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3676 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3677
3678 default:
3679 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3680 }
3681}
3682
3683
3684/**
3685 * Gets the page state for a virtual handler.
3686 *
3687 * @returns The virtual handler page state.
3688 * @param pCur The virtual handler in question.
3689 * @remarks This should never be used on a hypervisor access handler.
3690 */
3691DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3692{
3693 switch (pCur->enmType)
3694 {
3695 case PGMVIRTHANDLERTYPE_WRITE:
3696 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3697 case PGMVIRTHANDLERTYPE_ALL:
3698 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3699 default:
3700 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3701 }
3702}
3703
3704
3705/**
3706 * Clears one physical page of a virtual handler
3707 *
3708 * @param pPGM Pointer to the PGM instance.
3709 * @param pCur Virtual handler structure
3710 * @param iPage Physical page index
3711 *
3712 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3713 * need to care about other handlers in the same page.
3714 */
3715DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3716{
3717 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3718
3719 /*
3720 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3721 */
3722#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3723 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3724 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3725 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3726#endif
3727 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3728 {
3729 /* We're the head of the alias chain. */
3730 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3731#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3732 AssertReleaseMsg(pRemove != NULL,
3733 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3734 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3735 AssertReleaseMsg(pRemove == pPhys2Virt,
3736 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3737 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3738 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3739 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3740#endif
3741 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3742 {
3743 /* Insert the next list in the alias chain into the tree. */
3744 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3745#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3746 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3747 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3748 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3749#endif
3750 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3751 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3752 AssertRelease(fRc);
3753 }
3754 }
3755 else
3756 {
3757 /* Locate the previous node in the alias chain. */
3758 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3759#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3760 AssertReleaseMsg(pPrev != pPhys2Virt,
3761 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3762 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3763#endif
3764 for (;;)
3765 {
3766 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3767 if (pNext == pPhys2Virt)
3768 {
3769 /* unlink. */
3770 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3771 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3772 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3773 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3774 else
3775 {
3776 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3777 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3778 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3779 }
3780 break;
3781 }
3782
3783 /* next */
3784 if (pNext == pPrev)
3785 {
3786#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3787 AssertReleaseMsg(pNext != pPrev,
3788 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3789 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3790#endif
3791 break;
3792 }
3793 pPrev = pNext;
3794 }
3795 }
3796 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3797 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
3798 pPhys2Virt->offNextAlias = 0;
3799 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3800
3801 /*
3802 * Clear the ram flags for this page.
3803 */
3804 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3805 AssertReturnVoid(pPage);
3806 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3807}
3808
3809
3810/**
3811 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3812 *
3813 * @returns Pointer to the shadow page structure.
3814 * @param pPool The pool.
3815 * @param HCPhys The HC physical address of the shadow page.
3816 */
3817DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3818{
3819 /*
3820 * Look up the page.
3821 */
3822 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3823 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3824 return pPage;
3825}
3826
3827
3828/**
3829 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3830 *
3831 * @returns Pointer to the shadow page structure.
3832 * @param pPool The pool.
3833 * @param idx The pool page index.
3834 */
3835DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3836{
3837 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3838 return &pPool->aPages[idx];
3839}
3840
3841
3842#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3843/**
3844 * Clear references to guest physical memory.
3845 *
3846 * @param pPool The pool.
3847 * @param pPoolPage The pool page.
3848 * @param pPhysPage The physical guest page tracking structure.
3849 */
3850DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3851{
3852 /*
3853 * Just deal with the simple case here.
3854 */
3855#ifdef LOG_ENABLED
3856 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3857#endif
3858 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3859 if (cRefs == 1)
3860 {
3861 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3862 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3863 }
3864 else
3865 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3866 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3867}
3868#endif
3869
3870
3871#ifdef PGMPOOL_WITH_CACHE
3872/**
3873 * Moves the page to the head of the age list.
3874 *
3875 * This is done when the cached page is used in one way or another.
3876 *
3877 * @param pPool The pool.
3878 * @param pPage The cached page.
3879 * @todo inline in PGMInternal.h!
3880 */
3881DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3882{
3883 /*
3884 * Move to the head of the age list.
3885 */
3886 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3887 {
3888 /* unlink */
3889 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3890 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3891 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3892 else
3893 pPool->iAgeTail = pPage->iAgePrev;
3894
3895 /* insert at head */
3896 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3897 pPage->iAgeNext = pPool->iAgeHead;
3898 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3899 pPool->iAgeHead = pPage->idx;
3900 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3901 }
3902}
3903#endif /* PGMPOOL_WITH_CACHE */
3904
3905/**
3906 * Tells if mappings are to be put into the shadow page table or not
3907 *
3908 * @returns boolean result
3909 * @param pVM VM handle.
3910 */
3911
3912DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3913{
3914#ifdef IN_RING0
3915 /* There are no mappings in VT-x and AMD-V mode. */
3916 Assert(pPGM->fDisableMappings);
3917 return false;
3918#else
3919 return !pPGM->fDisableMappings;
3920#endif
3921}
3922
3923/** @} */
3924
3925#endif
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