VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 14398

Last change on this file since 14398 was 14374, checked in by vboxsync, 16 years ago

#1865: ring-0 mapping cache, code in progress.
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1/* $Id: PGMInternal.h 14374 2008-11-19 19:13:00Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) \
201 ( (uGstType) >= PGM_TYPE_32BIT \
202 && (uShwType) != PGM_TYPE_NESTED \
203 && (uShwType) != PGM_TYPE_EPT)
204
205/** Macro for checking if the guest supports the NX bit.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_NX(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_PAE \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215
216/** @def PGM_HCPHYS_2_PTR
217 * Maps a HC physical page pool address to a virtual address.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM handle.
221 * @param HCPhys The HC physical address to map to a virtual one.
222 * @param ppv Where to store the virtual address. No need to cast this.
223 *
224 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225 * small page window employeed by that function. Be careful.
226 * @remark There is no need to assert on the result.
227 */
228#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
229# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231#else
232# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
234#endif
235
236/** @def PGM_GCPHYS_2_PTR
237 * Maps a GC physical page address to a virtual address.
238 *
239 * @returns VBox status code.
240 * @param pVM The VM handle.
241 * @param GCPhys The GC physical address to map to a virtual one.
242 * @param ppv Where to store the virtual address. No need to cast this.
243 *
244 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
245 * small page window employeed by that function. Be careful.
246 * @remark There is no need to assert on the result.
247 */
248#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
249# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
250 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
251#else
252# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
253 PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
254#endif
255
256/** @def PGM_GCPHYS_2_PTR_EX
257 * Maps a unaligned GC physical page address to a virtual address.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM handle.
261 * @param GCPhys The GC physical address to map to a virtual one.
262 * @param ppv Where to store the virtual address. No need to cast this.
263 *
264 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
265 * small page window employeed by that function. Be careful.
266 * @remark There is no need to assert on the result.
267 */
268#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
269# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
270 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
271#else
272# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
273 PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
274#endif
275
276/** @def PGM_INVL_PG
277 * Invalidates a page when in GC does nothing in HC.
278 *
279 * @param GCVirt The virtual address of the page to invalidate.
280 */
281#ifdef IN_RC
282# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
283#elif defined(IN_RING0)
284# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
285#else
286# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
287#endif
288
289/** @def PGM_INVL_BIG_PG
290 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
291 *
292 * @param GCVirt The virtual address within the page directory to invalidate.
293 */
294#ifdef IN_RC
295# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
296#elif defined(IN_RING0)
297# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
298#else
299# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
300#endif
301
302/** @def PGM_INVL_GUEST_TLBS()
303 * Invalidates all guest TLBs.
304 */
305#ifdef IN_RC
306# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
307#elif defined(IN_RING0)
308# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
309#else
310# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
311#endif
312
313
314/**
315 * Structure for tracking GC Mappings.
316 *
317 * This structure is used by linked list in both GC and HC.
318 */
319typedef struct PGMMAPPING
320{
321 /** Pointer to next entry. */
322 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
323 /** Pointer to next entry. */
324 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
325 /** Pointer to next entry. */
326 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
327#if GC_ARCH_BITS == 64
328 RTRCPTR padding0;
329#endif
330 /** Start Virtual address. */
331 RTGCPTR GCPtr;
332 /** Last Virtual address (inclusive). */
333 RTGCPTR GCPtrLast;
334 /** Range size (bytes). */
335 RTGCPTR cb;
336 /** Pointer to relocation callback function. */
337 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
338 /** User argument to the callback. */
339 R3PTRTYPE(void *) pvUser;
340 /** Mapping description / name. For easing debugging. */
341 R3PTRTYPE(const char *) pszDesc;
342 /** Number of page tables. */
343 RTUINT cPTs;
344#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
345 RTUINT uPadding1; /**< Alignment padding. */
346#endif
347 /** Array of page table mapping data. Each entry
348 * describes one page table. The array can be longer
349 * than the declared length.
350 */
351 struct
352 {
353 /** The HC physical address of the page table. */
354 RTHCPHYS HCPhysPT;
355 /** The HC physical address of the first PAE page table. */
356 RTHCPHYS HCPhysPaePT0;
357 /** The HC physical address of the second PAE page table. */
358 RTHCPHYS HCPhysPaePT1;
359 /** The HC virtual address of the 32-bit page table. */
360 R3PTRTYPE(PX86PT) pPTR3;
361 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
362 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
363 /** The GC virtual address of the 32-bit page table. */
364 RCPTRTYPE(PX86PT) pPTRC;
365 /** The GC virtual address of the two PAE page table. */
366 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
367 /** The GC virtual address of the 32-bit page table. */
368 R0PTRTYPE(PX86PT) pPTR0;
369 /** The GC virtual address of the two PAE page table. */
370 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
371 } aPTs[1];
372} PGMMAPPING;
373/** Pointer to structure for tracking GC Mappings. */
374typedef struct PGMMAPPING *PPGMMAPPING;
375
376
377/**
378 * Physical page access handler structure.
379 *
380 * This is used to keep track of physical address ranges
381 * which are being monitored in some kind of way.
382 */
383typedef struct PGMPHYSHANDLER
384{
385 AVLROGCPHYSNODECORE Core;
386 /** Access type. */
387 PGMPHYSHANDLERTYPE enmType;
388 /** Number of pages to update. */
389 uint32_t cPages;
390 /** Pointer to R3 callback function. */
391 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
392 /** User argument for R3 handlers. */
393 R3PTRTYPE(void *) pvUserR3;
394 /** Pointer to R0 callback function. */
395 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
396 /** User argument for R0 handlers. */
397 R0PTRTYPE(void *) pvUserR0;
398 /** Pointer to GC callback function. */
399 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
400 /** User argument for RC handlers. */
401 RCPTRTYPE(void *) pvUserRC;
402 /** Description / Name. For easing debugging. */
403 R3PTRTYPE(const char *) pszDesc;
404#ifdef VBOX_WITH_STATISTICS
405 /** Profiling of this handler. */
406 STAMPROFILE Stat;
407#endif
408} PGMPHYSHANDLER;
409/** Pointer to a physical page access handler structure. */
410typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
411
412
413/**
414 * Cache node for the physical addresses covered by a virtual handler.
415 */
416typedef struct PGMPHYS2VIRTHANDLER
417{
418 /** Core node for the tree based on physical ranges. */
419 AVLROGCPHYSNODECORE Core;
420 /** Offset from this struct to the PGMVIRTHANDLER structure. */
421 int32_t offVirtHandler;
422 /** Offset of the next alias relative to this one.
423 * Bit 0 is used for indicating whether we're in the tree.
424 * Bit 1 is used for indicating that we're the head node.
425 */
426 int32_t offNextAlias;
427} PGMPHYS2VIRTHANDLER;
428/** Pointer to a phys to virtual handler structure. */
429typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
430
431/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
432 * node is in the tree. */
433#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
434/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
435 * node is in the head of an alias chain.
436 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
437#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
438/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
439#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
440
441
442/**
443 * Virtual page access handler structure.
444 *
445 * This is used to keep track of virtual address ranges
446 * which are being monitored in some kind of way.
447 */
448typedef struct PGMVIRTHANDLER
449{
450 /** Core node for the tree based on virtual ranges. */
451 AVLROGCPTRNODECORE Core;
452 /** Size of the range (in bytes). */
453 RTGCPTR cb;
454 /** Number of cache pages. */
455 uint32_t cPages;
456 /** Access type. */
457 PGMVIRTHANDLERTYPE enmType;
458 /** Pointer to the RC callback function. */
459 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
460#if HC_ARCH_BITS == 64
461 RTRCPTR padding;
462#endif
463 /** Pointer to the R3 callback function for invalidation. */
464 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
465 /** Pointer to the R3 callback function. */
466 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
467 /** Description / Name. For easing debugging. */
468 R3PTRTYPE(const char *) pszDesc;
469#ifdef VBOX_WITH_STATISTICS
470 /** Profiling of this handler. */
471 STAMPROFILE Stat;
472#endif
473 /** Array of cached physical addresses for the monitored ranged. */
474 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
475} PGMVIRTHANDLER;
476/** Pointer to a virtual page access handler structure. */
477typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
478
479
480/**
481 * Page type.
482 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
483 * @todo convert to \#defines.
484 */
485typedef enum PGMPAGETYPE
486{
487 /** The usual invalid zero entry. */
488 PGMPAGETYPE_INVALID = 0,
489 /** RAM page. (RWX) */
490 PGMPAGETYPE_RAM,
491 /** MMIO2 page. (RWX) */
492 PGMPAGETYPE_MMIO2,
493 /** Shadowed ROM. (RWX) */
494 PGMPAGETYPE_ROM_SHADOW,
495 /** ROM page. (R-X) */
496 PGMPAGETYPE_ROM,
497 /** MMIO page. (---) */
498 PGMPAGETYPE_MMIO,
499 /** End of valid entries. */
500 PGMPAGETYPE_END
501} PGMPAGETYPE;
502AssertCompile(PGMPAGETYPE_END < 7);
503
504/** @name Page type predicates.
505 * @{ */
506#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
507#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
508#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
509#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
510#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
511/** @} */
512
513
514/**
515 * A Physical Guest Page tracking structure.
516 *
517 * The format of this structure is complicated because we have to fit a lot
518 * of information into as few bits as possible. The format is also subject
519 * to change (there is one comming up soon). Which means that for we'll be
520 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
521 * accessess to the structure.
522 */
523typedef struct PGMPAGE
524{
525 /** The physical address and a whole lot of other stuff. All bits are used! */
526 RTHCPHYS HCPhys;
527 /** The page state. */
528 uint32_t u2StateX : 2;
529 /** Flag indicating that a write monitored page was written to when set. */
530 uint32_t fWrittenToX : 1;
531 /** For later. */
532 uint32_t fSomethingElse : 1;
533 /** The Page ID.
534 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
535 * The HCPhys will be 100% static. */
536 uint32_t idPageX : 28;
537 /** The page type (PGMPAGETYPE). */
538 uint32_t u3Type : 3;
539 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
540 uint32_t u2HandlerPhysStateX : 2;
541 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
542 uint32_t u2HandlerVirtStateX : 2;
543 uint32_t u29B : 25;
544} PGMPAGE;
545AssertCompileSize(PGMPAGE, 16);
546/** Pointer to a physical guest page. */
547typedef PGMPAGE *PPGMPAGE;
548/** Pointer to a const physical guest page. */
549typedef const PGMPAGE *PCPGMPAGE;
550/** Pointer to a physical guest page pointer. */
551typedef PPGMPAGE *PPPGMPAGE;
552
553
554/**
555 * Clears the page structure.
556 * @param pPage Pointer to the physical guest page tracking structure.
557 */
558#define PGM_PAGE_CLEAR(pPage) \
559 do { \
560 (pPage)->HCPhys = 0; \
561 (pPage)->u2StateX = 0; \
562 (pPage)->fWrittenToX = 0; \
563 (pPage)->fSomethingElse = 0; \
564 (pPage)->idPageX = 0; \
565 (pPage)->u3Type = 0; \
566 (pPage)->u29B = 0; \
567 } while (0)
568
569/**
570 * Initializes the page structure.
571 * @param pPage Pointer to the physical guest page tracking structure.
572 */
573#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
574 do { \
575 (pPage)->HCPhys = (_HCPhys); \
576 (pPage)->u2StateX = (_uState); \
577 (pPage)->fWrittenToX = 0; \
578 (pPage)->fSomethingElse = 0; \
579 (pPage)->idPageX = (_idPage); \
580 /*(pPage)->u3Type = (_uType); - later */ \
581 PGM_PAGE_SET_TYPE(pPage, _uType); \
582 (pPage)->u29B = 0; \
583 } while (0)
584
585/**
586 * Initializes the page structure of a ZERO page.
587 * @param pPage Pointer to the physical guest page tracking structure.
588 */
589#ifdef VBOX_WITH_NEW_PHYS_CODE
590# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
591 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
592#else
593# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
594 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
595#endif
596/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
597# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
598 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
599
600
601/** @name The Page state, PGMPAGE::u2StateX.
602 * @{ */
603/** The zero page.
604 * This is a per-VM page that's never ever mapped writable. */
605#define PGM_PAGE_STATE_ZERO 0
606/** A allocated page.
607 * This is a per-VM page allocated from the page pool (or wherever
608 * we get MMIO2 pages from if the type is MMIO2).
609 */
610#define PGM_PAGE_STATE_ALLOCATED 1
611/** A allocated page that's being monitored for writes.
612 * The shadow page table mappings are read-only. When a write occurs, the
613 * fWrittenTo member is set, the page remapped as read-write and the state
614 * moved back to allocated. */
615#define PGM_PAGE_STATE_WRITE_MONITORED 2
616/** The page is shared, aka. copy-on-write.
617 * This is a page that's shared with other VMs. */
618#define PGM_PAGE_STATE_SHARED 3
619/** @} */
620
621
622/**
623 * Gets the page state.
624 * @returns page state (PGM_PAGE_STATE_*).
625 * @param pPage Pointer to the physical guest page tracking structure.
626 */
627#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
628
629/**
630 * Sets the page state.
631 * @param pPage Pointer to the physical guest page tracking structure.
632 * @param _uState The new page state.
633 */
634#define PGM_PAGE_SET_STATE(pPage, _uState) \
635 do { (pPage)->u2StateX = (_uState); } while (0)
636
637
638/**
639 * Gets the host physical address of the guest page.
640 * @returns host physical address (RTHCPHYS).
641 * @param pPage Pointer to the physical guest page tracking structure.
642 */
643#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
644
645/**
646 * Sets the host physical address of the guest page.
647 * @param pPage Pointer to the physical guest page tracking structure.
648 * @param _HCPhys The new host physical address.
649 */
650#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
651 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
652 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
653
654/**
655 * Get the Page ID.
656 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
657 * @param pPage Pointer to the physical guest page tracking structure.
658 */
659#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
660/* later:
661#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
662 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
663*/
664/**
665 * Sets the Page ID.
666 * @param pPage Pointer to the physical guest page tracking structure.
667 */
668#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
669/* later:
670#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
671 | ((_idPage) & 0xfff) \
672 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
673*/
674
675/**
676 * Get the Chunk ID.
677 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
678 * @param pPage Pointer to the physical guest page tracking structure.
679 */
680#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
681/* later:
682#if GMM_CHUNKID_SHIFT == 12
683# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
684#elif GMM_CHUNKID_SHIFT > 12
685# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
686#elif GMM_CHUNKID_SHIFT < 12
687# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
688 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
689#else
690# error "GMM_CHUNKID_SHIFT isn't defined or something."
691#endif
692*/
693
694/**
695 * Get the index of the page within the allocaiton chunk.
696 * @returns The page index.
697 * @param pPage Pointer to the physical guest page tracking structure.
698 */
699#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
700/* later:
701#if GMM_CHUNKID_SHIFT <= 12
702# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
703#else
704# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
705 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
706#endif
707*/
708
709
710/**
711 * Gets the page type.
712 * @returns The page type.
713 * @param pPage Pointer to the physical guest page tracking structure.
714 */
715#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
716
717/**
718 * Sets the page type.
719 * @param pPage Pointer to the physical guest page tracking structure.
720 * @param _enmType The new page type (PGMPAGETYPE).
721 */
722#ifdef VBOX_WITH_NEW_PHYS_CODE
723#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
724 do { (pPage)->u3Type = (_enmType); } while (0)
725#else
726#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
727 do { \
728 (pPage)->u3Type = (_enmType); \
729 if ((_enmType) == PGMPAGETYPE_ROM) \
730 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
731 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
732 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
733 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
734 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
735 } while (0)
736#endif
737
738
739/**
740 * Checks if the page is 'reserved'.
741 * @returns true/false.
742 * @param pPage Pointer to the physical guest page tracking structure.
743 */
744#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
745
746/**
747 * Checks if the page is marked for MMIO.
748 * @returns true/false.
749 * @param pPage Pointer to the physical guest page tracking structure.
750 */
751#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
752
753/**
754 * Checks if the page is backed by the ZERO page.
755 * @returns true/false.
756 * @param pPage Pointer to the physical guest page tracking structure.
757 */
758#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
759
760/**
761 * Checks if the page is backed by a SHARED page.
762 * @returns true/false.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 */
765#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
766
767
768/**
769 * Marks the paget as written to (for GMM change monitoring).
770 * @param pPage Pointer to the physical guest page tracking structure.
771 */
772#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
773
774/**
775 * Clears the written-to indicator.
776 * @param pPage Pointer to the physical guest page tracking structure.
777 */
778#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
779
780/**
781 * Checks if the page was marked as written-to.
782 * @returns true/false.
783 * @param pPage Pointer to the physical guest page tracking structure.
784 */
785#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
786
787
788/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
789 *
790 * @remarks The values are assigned in order of priority, so we can calculate
791 * the correct state for a page with different handlers installed.
792 * @{ */
793/** No handler installed. */
794#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
795/** Monitoring is temporarily disabled. */
796#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
797/** Write access is monitored. */
798#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
799/** All access is monitored. */
800#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
801/** @} */
802
803/**
804 * Gets the physical access handler state of a page.
805 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
806 * @param pPage Pointer to the physical guest page tracking structure.
807 */
808#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
809
810/**
811 * Sets the physical access handler state of a page.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 * @param _uState The new state value.
814 */
815#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
816 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
817
818/**
819 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
820 * @returns true/false
821 * @param pPage Pointer to the physical guest page tracking structure.
822 */
823#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
824
825/**
826 * Checks if the page has any active physical access handlers.
827 * @returns true/false
828 * @param pPage Pointer to the physical guest page tracking structure.
829 */
830#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
831
832
833/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
834 *
835 * @remarks The values are assigned in order of priority, so we can calculate
836 * the correct state for a page with different handlers installed.
837 * @{ */
838/** No handler installed. */
839#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
840/* 1 is reserved so the lineup is identical with the physical ones. */
841/** Write access is monitored. */
842#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
843/** All access is monitored. */
844#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
845/** @} */
846
847/**
848 * Gets the virtual access handler state of a page.
849 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
853
854/**
855 * Sets the virtual access handler state of a page.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 * @param _uState The new state value.
858 */
859#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
860 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
861
862/**
863 * Checks if the page has any virtual access handlers.
864 * @returns true/false
865 * @param pPage Pointer to the physical guest page tracking structure.
866 */
867#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
868
869/**
870 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
871 * virtual handlers.
872 * @returns true/false
873 * @param pPage Pointer to the physical guest page tracking structure.
874 */
875#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
876
877
878
879/**
880 * Checks if the page has any access handlers, including temporarily disabled ones.
881 * @returns true/false
882 * @param pPage Pointer to the physical guest page tracking structure.
883 */
884#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
885 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
886 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
887
888/**
889 * Checks if the page has any active access handlers.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
894 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
895 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
896
897/**
898 * Checks if the page has any active access handlers catching all accesses.
899 * @returns true/false
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
903 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
904 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
905
906
907/**
908 * Ram range for GC Phys to HC Phys conversion.
909 *
910 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
911 * conversions too, but we'll let MM handle that for now.
912 *
913 * This structure is used by linked lists in both GC and HC.
914 */
915typedef struct PGMRAMRANGE
916{
917 /** Pointer to the next RAM range - for R3. */
918 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
919 /** Pointer to the next RAM range - for R0. */
920 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
921 /** Pointer to the next RAM range - for RC. */
922 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
923 /** Pointer alignment. */
924 RTRCPTR RCPtrAlignment;
925 /** Start of the range. Page aligned. */
926 RTGCPHYS GCPhys;
927 /** Last address in the range (inclusive). Page aligned (-1). */
928 RTGCPHYS GCPhysLast;
929 /** Size of the range. (Page aligned of course). */
930 RTGCPHYS cb;
931 /** MM_RAM_* flags */
932 uint32_t fFlags;
933 uint32_t u32Alignment; /**< alignment. */
934#ifndef VBOX_WITH_NEW_PHYS_CODE
935 /** R3 virtual lookup ranges for chunks.
936 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
937 * @remarks This is occationally accessed from ring-0!! (not darwin) */
938# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
939 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
940# else
941 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
942# endif
943#endif
944 /** Start of the HC mapping of the range. This is only used for MMIO2. */
945 R3PTRTYPE(void *) pvR3;
946 /** The range description. */
947 R3PTRTYPE(const char *) pszDesc;
948
949 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
950#ifdef VBOX_WITH_NEW_PHYS_CODE
951 uint32_t au32Reserved[2];
952#elif HC_ARCH_BITS == 32
953 uint32_t au32Reserved[1];
954#endif
955
956 /** Array of physical guest page tracking structures. */
957 PGMPAGE aPages[1];
958} PGMRAMRANGE;
959/** Pointer to Ram range for GC Phys to HC Phys conversion. */
960typedef PGMRAMRANGE *PPGMRAMRANGE;
961
962/** Return hc ptr corresponding to the ram range and physical offset */
963#define PGMRAMRANGE_GETHCPTR(pRam, off) \
964 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
965 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
966
967/**
968 * Per page tracking structure for ROM image.
969 *
970 * A ROM image may have a shadow page, in which case we may have
971 * two pages backing it. This structure contains the PGMPAGE for
972 * both while PGMRAMRANGE have a copy of the active one. It is
973 * important that these aren't out of sync in any regard other
974 * than page pool tracking data.
975 */
976typedef struct PGMROMPAGE
977{
978 /** The page structure for the virgin ROM page. */
979 PGMPAGE Virgin;
980 /** The page structure for the shadow RAM page. */
981 PGMPAGE Shadow;
982 /** The current protection setting. */
983 PGMROMPROT enmProt;
984 /** Pad the structure size to a multiple of 8. */
985 uint32_t u32Padding;
986} PGMROMPAGE;
987/** Pointer to a ROM page tracking structure. */
988typedef PGMROMPAGE *PPGMROMPAGE;
989
990
991/**
992 * A registered ROM image.
993 *
994 * This is needed to keep track of ROM image since they generally
995 * intrude into a PGMRAMRANGE. It also keeps track of additional
996 * info like the two page sets (read-only virgin and read-write shadow),
997 * the current state of each page.
998 *
999 * Because access handlers cannot easily be executed in a different
1000 * context, the ROM ranges needs to be accessible and in all contexts.
1001 */
1002typedef struct PGMROMRANGE
1003{
1004 /** Pointer to the next range - R3. */
1005 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1006 /** Pointer to the next range - R0. */
1007 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1008 /** Pointer to the next range - RC. */
1009 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1010 /** Pointer alignment */
1011 RTRCPTR GCPtrAlignment;
1012 /** Address of the range. */
1013 RTGCPHYS GCPhys;
1014 /** Address of the last byte in the range. */
1015 RTGCPHYS GCPhysLast;
1016 /** Size of the range. */
1017 RTGCPHYS cb;
1018 /** The flags (PGMPHYS_ROM_FLAG_*). */
1019 uint32_t fFlags;
1020 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1021 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1022 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1023 * This is used for strictness checks. */
1024 R3PTRTYPE(const void *) pvOriginal;
1025 /** The ROM description. */
1026 R3PTRTYPE(const char *) pszDesc;
1027 /** The per page tracking structures. */
1028 PGMROMPAGE aPages[1];
1029} PGMROMRANGE;
1030/** Pointer to a ROM range. */
1031typedef PGMROMRANGE *PPGMROMRANGE;
1032
1033
1034/**
1035 * A registered MMIO2 (= Device RAM) range.
1036 *
1037 * There are a few reason why we need to keep track of these
1038 * registrations. One of them is the deregistration & cleanup
1039 * stuff, while another is that the PGMRAMRANGE associated with
1040 * such a region may have to be removed from the ram range list.
1041 *
1042 * Overlapping with a RAM range has to be 100% or none at all. The
1043 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1044 * meditation will be raised if a partial overlap or an overlap of
1045 * ROM pages is encountered. On an overlap we will free all the
1046 * existing RAM pages and put in the ram range pages instead.
1047 */
1048typedef struct PGMMMIO2RANGE
1049{
1050 /** The owner of the range. (a device) */
1051 PPDMDEVINSR3 pDevInsR3;
1052 /** Pointer to the ring-3 mapping of the allocation. */
1053 RTR3PTR pvR3;
1054 /** Pointer to the next range - R3. */
1055 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1056 /** Whether it's mapped or not. */
1057 bool fMapped;
1058 /** Whether it's overlapping or not. */
1059 bool fOverlapping;
1060 /** The PCI region number.
1061 * @remarks This ASSUMES that nobody will ever really need to have multiple
1062 * PCI devices with matching MMIO region numbers on a single device. */
1063 uint8_t iRegion;
1064 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1065 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1066 /** The associated RAM range. */
1067 PGMRAMRANGE RamRange;
1068} PGMMMIO2RANGE;
1069/** Pointer to a MMIO2 range. */
1070typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1071
1072
1073
1074
1075/**
1076 * PGMPhysRead/Write cache entry
1077 */
1078typedef struct PGMPHYSCACHEENTRY
1079{
1080 /** R3 pointer to physical page. */
1081 R3PTRTYPE(uint8_t *) pbR3;
1082 /** GC Physical address for cache entry */
1083 RTGCPHYS GCPhys;
1084#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1085 RTGCPHYS u32Padding0; /**< alignment padding. */
1086#endif
1087} PGMPHYSCACHEENTRY;
1088
1089/**
1090 * PGMPhysRead/Write cache to reduce REM memory access overhead
1091 */
1092typedef struct PGMPHYSCACHE
1093{
1094 /** Bitmap of valid cache entries */
1095 uint64_t aEntries;
1096 /** Cache entries */
1097 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1098} PGMPHYSCACHE;
1099
1100
1101/** Pointer to an allocation chunk ring-3 mapping. */
1102typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1103/** Pointer to an allocation chunk ring-3 mapping pointer. */
1104typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1105
1106/**
1107 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1108 *
1109 * The primary tree (Core) uses the chunk id as key.
1110 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1111 */
1112typedef struct PGMCHUNKR3MAP
1113{
1114 /** The key is the chunk id. */
1115 AVLU32NODECORE Core;
1116 /** The key is the ageing sequence number. */
1117 AVLLU32NODECORE AgeCore;
1118 /** The current age thingy. */
1119 uint32_t iAge;
1120 /** The current reference count. */
1121 uint32_t volatile cRefs;
1122 /** The current permanent reference count. */
1123 uint32_t volatile cPermRefs;
1124 /** The mapping address. */
1125 void *pv;
1126} PGMCHUNKR3MAP;
1127
1128/**
1129 * Allocation chunk ring-3 mapping TLB entry.
1130 */
1131typedef struct PGMCHUNKR3MAPTLBE
1132{
1133 /** The chunk id. */
1134 uint32_t volatile idChunk;
1135#if HC_ARCH_BITS == 64
1136 uint32_t u32Padding; /**< alignment padding. */
1137#endif
1138 /** The chunk map. */
1139#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1140 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1141#else
1142 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1143#endif
1144} PGMCHUNKR3MAPTLBE;
1145/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1146typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1147
1148/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1149 * @remark Must be a power of two value. */
1150#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1151
1152/**
1153 * Allocation chunk ring-3 mapping TLB.
1154 *
1155 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1156 * At first glance this might look kinda odd since AVL trees are
1157 * supposed to give the most optimial lookup times of all trees
1158 * due to their balancing. However, take a tree with 1023 nodes
1159 * in it, that's 10 levels, meaning that most searches has to go
1160 * down 9 levels before they find what they want. This isn't fast
1161 * compared to a TLB hit. There is the factor of cache misses,
1162 * and of course the problem with trees and branch prediction.
1163 * This is why we use TLBs in front of most of the trees.
1164 *
1165 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1166 * difficult when we switch to the new inlined AVL trees (from kStuff).
1167 */
1168typedef struct PGMCHUNKR3MAPTLB
1169{
1170 /** The TLB entries. */
1171 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1172} PGMCHUNKR3MAPTLB;
1173
1174/**
1175 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1176 * @returns Chunk TLB index.
1177 * @param idChunk The Chunk ID.
1178 */
1179#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1180
1181
1182/**
1183 * Ring-3 guest page mapping TLB entry.
1184 * @remarks used in ring-0 as well at the moment.
1185 */
1186typedef struct PGMPAGER3MAPTLBE
1187{
1188 /** Address of the page. */
1189 RTGCPHYS volatile GCPhys;
1190 /** The guest page. */
1191#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1192 R3PTRTYPE(PPGMPAGE) volatile pPage;
1193#else
1194 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1195#endif
1196 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1197#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1198 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1199#else
1200 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1201#endif
1202 /** The address */
1203#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1204 R3PTRTYPE(void *) volatile pv;
1205#else
1206 R3R0PTRTYPE(void *) volatile pv;
1207#endif
1208#if HC_ARCH_BITS == 32
1209 uint32_t u32Padding; /**< alignment padding. */
1210#endif
1211} PGMPAGER3MAPTLBE;
1212/** Pointer to an entry in the HC physical TLB. */
1213typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1214
1215
1216/** The number of entries in the ring-3 guest page mapping TLB.
1217 * @remarks The value must be a power of two. */
1218#define PGM_PAGER3MAPTLB_ENTRIES 64
1219
1220/**
1221 * Ring-3 guest page mapping TLB.
1222 * @remarks used in ring-0 as well at the moment.
1223 */
1224typedef struct PGMPAGER3MAPTLB
1225{
1226 /** The TLB entries. */
1227 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1228} PGMPAGER3MAPTLB;
1229/** Pointer to the ring-3 guest page mapping TLB. */
1230typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1231
1232/**
1233 * Calculates the index of the TLB entry for the specified guest page.
1234 * @returns Physical TLB index.
1235 * @param GCPhys The guest physical address.
1236 */
1237#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1238
1239
1240/**
1241 * Mapping cache usage set entry.
1242 *
1243 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1244 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1245 * cache. If it's extended to include ring-3, well, then something will
1246 * have be changed here...
1247 */
1248typedef struct PGMMAPSETENTRY
1249{
1250 /** The mapping cache index. */
1251 uint16_t iPage;
1252 /** The number of references. */
1253 uint16_t cRefs;
1254} PGMMAPSETENTRY;
1255/** Pointer to a mapping cache usage set entry. */
1256typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1257
1258/**
1259 * Mapping cache usage set.
1260 *
1261 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1262 * done during exits / traps. The set is
1263 */
1264typedef struct PGMMAPSET
1265{
1266 /** The number of occupied.
1267 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1268 * dynamic mappings. */
1269 uint32_t cEntries;
1270 /** The entries. */
1271 PGMMAPSETENTRY aEntries[32];
1272} PGMMAPSET;
1273/** Pointer to the mapping cache set. */
1274typedef PGMMAPSET *PPGMMAPSET;
1275
1276/** PGMMAPSET::cEntries value for a closed set. */
1277#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1278
1279
1280/** @name Context neutrual page mapper TLB.
1281 *
1282 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1283 * code is writting in a kind of context neutrual way. Time will show whether
1284 * this actually makes sense or not...
1285 *
1286 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1287 * context ends up using a global mapping cache on some platforms
1288 * (darwin).
1289 *
1290 * @{ */
1291/** @typedef PPGMPAGEMAPTLB
1292 * The page mapper TLB pointer type for the current context. */
1293/** @typedef PPGMPAGEMAPTLB
1294 * The page mapper TLB entry pointer type for the current context. */
1295/** @typedef PPGMPAGEMAPTLB
1296 * The page mapper TLB entry pointer pointer type for the current context. */
1297/** @def PGM_PAGEMAPTLB_ENTRIES
1298 * The number of TLB entries in the page mapper TLB for the current context. */
1299/** @def PGM_PAGEMAPTLB_IDX
1300 * Calculate the TLB index for a guest physical address.
1301 * @returns The TLB index.
1302 * @param GCPhys The guest physical address. */
1303/** @typedef PPGMPAGEMAP
1304 * Pointer to a page mapper unit for current context. */
1305/** @typedef PPPGMPAGEMAP
1306 * Pointer to a page mapper unit pointer for current context. */
1307#ifdef IN_RC
1308// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1309// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1310// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1311# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1312# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1313 typedef void * PPGMPAGEMAP;
1314 typedef void ** PPPGMPAGEMAP;
1315//#elif IN_RING0
1316// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1317// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1318// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1319//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1320//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1321// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1322// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1323#else
1324 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1325 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1326 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1327# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1328# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1329 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1330 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1331#endif
1332/** @} */
1333
1334
1335/** @name PGM Pool Indexes.
1336 * Aka. the unique shadow page identifier.
1337 * @{ */
1338/** NIL page pool IDX. */
1339#define NIL_PGMPOOL_IDX 0
1340/** The first normal index. */
1341#define PGMPOOL_IDX_FIRST_SPECIAL 1
1342/** Page directory (32-bit root). */
1343#define PGMPOOL_IDX_PD 1
1344#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1345/** Page directory (32-bit root). */
1346#define PGMPOOL_IDX_PD 1
1347/** Page Directory Pointer Table (PAE root). */
1348#define PGMPOOL_IDX_PDPT 2
1349/** AMD64 CR3 level index.*/
1350#define PGMPOOL_IDX_AMD64_CR3 3
1351/** Nested paging root.*/
1352#define PGMPOOL_IDX_NESTED_ROOT 4
1353/** The first normal index. */
1354#define PGMPOOL_IDX_FIRST 5
1355#else
1356/** The extended PAE page directory (2048 entries, works as root currently). */
1357#define PGMPOOL_IDX_PAE_PD 2
1358/** PAE Page Directory Table 0. */
1359#define PGMPOOL_IDX_PAE_PD_0 3
1360/** PAE Page Directory Table 1. */
1361#define PGMPOOL_IDX_PAE_PD_1 4
1362/** PAE Page Directory Table 2. */
1363#define PGMPOOL_IDX_PAE_PD_2 5
1364/** PAE Page Directory Table 3. */
1365#define PGMPOOL_IDX_PAE_PD_3 6
1366/** Page Directory Pointer Table (PAE root, not currently used). */
1367#define PGMPOOL_IDX_PDPT 7
1368/** AMD64 CR3 level index.*/
1369#define PGMPOOL_IDX_AMD64_CR3 8
1370/** Nested paging root.*/
1371#define PGMPOOL_IDX_NESTED_ROOT 9
1372/** The first normal index. */
1373#define PGMPOOL_IDX_FIRST 10
1374#endif
1375/** The last valid index. (inclusive, 14 bits) */
1376#define PGMPOOL_IDX_LAST 0x3fff
1377/** @} */
1378
1379/** The NIL index for the parent chain. */
1380#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1381
1382/**
1383 * Node in the chain linking a shadowed page to it's parent (user).
1384 */
1385#pragma pack(1)
1386typedef struct PGMPOOLUSER
1387{
1388 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1389 uint16_t iNext;
1390 /** The user page index. */
1391 uint16_t iUser;
1392 /** Index into the user table. */
1393 uint32_t iUserTable;
1394} PGMPOOLUSER, *PPGMPOOLUSER;
1395typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1396#pragma pack()
1397
1398
1399/** The NIL index for the phys ext chain. */
1400#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1401
1402/**
1403 * Node in the chain of physical cross reference extents.
1404 */
1405#pragma pack(1)
1406typedef struct PGMPOOLPHYSEXT
1407{
1408 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1409 uint16_t iNext;
1410 /** The user page index. */
1411 uint16_t aidx[3];
1412} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1413typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1414#pragma pack()
1415
1416
1417/**
1418 * The kind of page that's being shadowed.
1419 */
1420typedef enum PGMPOOLKIND
1421{
1422 /** The virtual invalid 0 entry. */
1423 PGMPOOLKIND_INVALID = 0,
1424 /** The entry is free (=unused). */
1425 PGMPOOLKIND_FREE,
1426
1427 /** Shw: 32-bit page table; Gst: no paging */
1428 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1429 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1430 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1431 /** Shw: 32-bit page table; Gst: 4MB page. */
1432 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1433 /** Shw: PAE page table; Gst: no paging */
1434 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1435 /** Shw: PAE page table; Gst: 32-bit page table. */
1436 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1437 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1438 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1439 /** Shw: PAE page table; Gst: PAE page table. */
1440 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1441 /** Shw: PAE page table; Gst: 2MB page. */
1442 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1443
1444 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1445 PGMPOOLKIND_32BIT_PD,
1446 /** Shw: 32-bit page directory. Gst: real mode. */
1447 PGMPOOLKIND_32BIT_PD_PHYS_REAL,
1448 /** Shw: 32-bit page directory. Gst: protected mode without paging. */
1449 PGMPOOLKIND_32BIT_PD_PHYS_PROT,
1450 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1451 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1452 /** Shw: PAE page directory; Gst: PAE page directory. */
1453 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1454 /** Shw: PAE page directory; Gst: real mode. */
1455 PGMPOOLKIND_PAE_PD_PHYS_REAL,
1456 /** Shw: PAE page directory; Gst: protected mode without paging. */
1457 PGMPOOLKIND_PAE_PD_PHYS_PROT,
1458
1459 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1460 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1461 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1462 PGMPOOLKIND_PAE_PDPT,
1463
1464 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1465 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1466 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1467 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1468 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1469 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1470 /** Shw: 64-bit page directory table; Gst: no paging */
1471 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1472
1473 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1474 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1475
1476 /** Shw: EPT page directory pointer table; Gst: no paging */
1477 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1478 /** Shw: EPT page directory table; Gst: no paging */
1479 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1480 /** Shw: EPT page table; Gst: no paging */
1481 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1482
1483#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1484 /** Shw: Root 32-bit page directory. */
1485 PGMPOOLKIND_ROOT_32BIT_PD,
1486 /** Shw: Root PAE page directory */
1487 PGMPOOLKIND_ROOT_PAE_PD,
1488 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1489 PGMPOOLKIND_ROOT_PDPT,
1490#endif
1491 /** Shw: Root Nested paging table. */
1492 PGMPOOLKIND_ROOT_NESTED,
1493
1494 /** The last valid entry. */
1495 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1496} PGMPOOLKIND;
1497
1498
1499/**
1500 * The tracking data for a page in the pool.
1501 */
1502typedef struct PGMPOOLPAGE
1503{
1504 /** AVL node code with the (R3) physical address of this page. */
1505 AVLOHCPHYSNODECORE Core;
1506 /** Pointer to the R3 mapping of the page. */
1507#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1508 R3PTRTYPE(void *) pvPageR3;
1509#else
1510 R3R0PTRTYPE(void *) pvPageR3;
1511#endif
1512 /** The guest physical address. */
1513#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1514 uint32_t Alignment0;
1515#endif
1516 RTGCPHYS GCPhys;
1517 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1518 uint8_t enmKind;
1519 uint8_t bPadding;
1520 /** The index of this page. */
1521 uint16_t idx;
1522 /** The next entry in the list this page currently resides in.
1523 * It's either in the free list or in the GCPhys hash. */
1524 uint16_t iNext;
1525#ifdef PGMPOOL_WITH_USER_TRACKING
1526 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1527 uint16_t iUserHead;
1528 /** The number of present entries. */
1529 uint16_t cPresent;
1530 /** The first entry in the table which is present. */
1531 uint16_t iFirstPresent;
1532#endif
1533#ifdef PGMPOOL_WITH_MONITORING
1534 /** The number of modifications to the monitored page. */
1535 uint16_t cModifications;
1536 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1537 uint16_t iModifiedNext;
1538 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1539 uint16_t iModifiedPrev;
1540 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1541 uint16_t iMonitoredNext;
1542 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1543 uint16_t iMonitoredPrev;
1544#endif
1545#ifdef PGMPOOL_WITH_CACHE
1546 /** The next page in the age list. */
1547 uint16_t iAgeNext;
1548 /** The previous page in the age list. */
1549 uint16_t iAgePrev;
1550#endif /* PGMPOOL_WITH_CACHE */
1551 /** Used to indicate that the page is zeroed. */
1552 bool fZeroed;
1553 /** Used to indicate that a PT has non-global entries. */
1554 bool fSeenNonGlobal;
1555 /** Used to indicate that we're monitoring writes to the guest page. */
1556 bool fMonitored;
1557 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1558 * (All pages are in the age list.) */
1559 bool fCached;
1560 /** This is used by the R3 access handlers when invoked by an async thread.
1561 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1562 bool volatile fReusedFlushPending;
1563 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1564 * In these cases the access handler acts differently and will check
1565 * for mapping conflicts like the normal CR3 handler.
1566 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1567 * replaced by a list of pages which share access handler.
1568 */
1569 bool fCR3Mix;
1570} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1571
1572
1573#ifdef PGMPOOL_WITH_CACHE
1574/** The hash table size. */
1575# define PGMPOOL_HASH_SIZE 0x40
1576/** The hash function. */
1577# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1578#endif
1579
1580
1581/**
1582 * The shadow page pool instance data.
1583 *
1584 * It's all one big allocation made at init time, except for the
1585 * pages that is. The user nodes follows immediatly after the
1586 * page structures.
1587 */
1588typedef struct PGMPOOL
1589{
1590 /** The VM handle - R3 Ptr. */
1591 PVMR3 pVMR3;
1592 /** The VM handle - R0 Ptr. */
1593 PVMR0 pVMR0;
1594 /** The VM handle - RC Ptr. */
1595 PVMRC pVMRC;
1596 /** The max pool size. This includes the special IDs. */
1597 uint16_t cMaxPages;
1598 /** The current pool size. */
1599 uint16_t cCurPages;
1600 /** The head of the free page list. */
1601 uint16_t iFreeHead;
1602 /* Padding. */
1603 uint16_t u16Padding;
1604#ifdef PGMPOOL_WITH_USER_TRACKING
1605 /** Head of the chain of free user nodes. */
1606 uint16_t iUserFreeHead;
1607 /** The number of user nodes we've allocated. */
1608 uint16_t cMaxUsers;
1609 /** The number of present page table entries in the entire pool. */
1610 uint32_t cPresent;
1611 /** Pointer to the array of user nodes - RC pointer. */
1612 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1613 /** Pointer to the array of user nodes - R3 pointer. */
1614 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1615 /** Pointer to the array of user nodes - R0 pointer. */
1616 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1617#endif /* PGMPOOL_WITH_USER_TRACKING */
1618#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1619 /** Head of the chain of free phys ext nodes. */
1620 uint16_t iPhysExtFreeHead;
1621 /** The number of user nodes we've allocated. */
1622 uint16_t cMaxPhysExts;
1623 /** Pointer to the array of physical xref extent - RC pointer. */
1624 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1625 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1626 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1627 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1628 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1629#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1630#ifdef PGMPOOL_WITH_CACHE
1631 /** Hash table for GCPhys addresses. */
1632 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1633 /** The head of the age list. */
1634 uint16_t iAgeHead;
1635 /** The tail of the age list. */
1636 uint16_t iAgeTail;
1637 /** Set if the cache is enabled. */
1638 bool fCacheEnabled;
1639#endif /* PGMPOOL_WITH_CACHE */
1640#ifdef PGMPOOL_WITH_MONITORING
1641 /** Head of the list of modified pages. */
1642 uint16_t iModifiedHead;
1643 /** The current number of modified pages. */
1644 uint16_t cModifiedPages;
1645 /** Access handler, RC. */
1646 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1647 /** Access handler, R0. */
1648 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1649 /** Access handler, R3. */
1650 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1651 /** The access handler description (HC ptr). */
1652 R3PTRTYPE(const char *) pszAccessHandler;
1653#endif /* PGMPOOL_WITH_MONITORING */
1654 /** The number of pages currently in use. */
1655 uint16_t cUsedPages;
1656#ifdef VBOX_WITH_STATISTICS
1657 /** The high wather mark for cUsedPages. */
1658 uint16_t cUsedPagesHigh;
1659 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1660 /** Profiling pgmPoolAlloc(). */
1661 STAMPROFILEADV StatAlloc;
1662 /** Profiling pgmPoolClearAll(). */
1663 STAMPROFILE StatClearAll;
1664 /** Profiling pgmPoolFlushAllInt(). */
1665 STAMPROFILE StatFlushAllInt;
1666 /** Profiling pgmPoolFlushPage(). */
1667 STAMPROFILE StatFlushPage;
1668 /** Profiling pgmPoolFree(). */
1669 STAMPROFILE StatFree;
1670 /** Profiling time spent zeroing pages. */
1671 STAMPROFILE StatZeroPage;
1672# ifdef PGMPOOL_WITH_USER_TRACKING
1673 /** Profiling of pgmPoolTrackDeref. */
1674 STAMPROFILE StatTrackDeref;
1675 /** Profiling pgmTrackFlushGCPhysPT. */
1676 STAMPROFILE StatTrackFlushGCPhysPT;
1677 /** Profiling pgmTrackFlushGCPhysPTs. */
1678 STAMPROFILE StatTrackFlushGCPhysPTs;
1679 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1680 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1681 /** Number of times we've been out of user records. */
1682 STAMCOUNTER StatTrackFreeUpOneUser;
1683# endif
1684# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1685 /** Profiling deref activity related tracking GC physical pages. */
1686 STAMPROFILE StatTrackDerefGCPhys;
1687 /** Number of linear searches for a HCPhys in the ram ranges. */
1688 STAMCOUNTER StatTrackLinearRamSearches;
1689 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1690 STAMCOUNTER StamTrackPhysExtAllocFailures;
1691# endif
1692# ifdef PGMPOOL_WITH_MONITORING
1693 /** Profiling the RC/R0 access handler. */
1694 STAMPROFILE StatMonitorRZ;
1695 /** Times we've failed interpreting the instruction. */
1696 STAMCOUNTER StatMonitorRZEmulateInstr;
1697 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1698 STAMPROFILE StatMonitorRZFlushPage;
1699 /** Times we've detected fork(). */
1700 STAMCOUNTER StatMonitorRZFork;
1701 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1702 STAMPROFILE StatMonitorRZHandled;
1703 /** Times we've failed interpreting a patch code instruction. */
1704 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1705 /** Times we've failed interpreting a patch code instruction during flushing. */
1706 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1707 /** The number of times we've seen rep prefixes we can't handle. */
1708 STAMCOUNTER StatMonitorRZRepPrefix;
1709 /** Profiling the REP STOSD cases we've handled. */
1710 STAMPROFILE StatMonitorRZRepStosd;
1711
1712 /** Profiling the R3 access handler. */
1713 STAMPROFILE StatMonitorR3;
1714 /** Times we've failed interpreting the instruction. */
1715 STAMCOUNTER StatMonitorR3EmulateInstr;
1716 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1717 STAMPROFILE StatMonitorR3FlushPage;
1718 /** Times we've detected fork(). */
1719 STAMCOUNTER StatMonitorR3Fork;
1720 /** Profiling the R3 access we've handled (except REP STOSD). */
1721 STAMPROFILE StatMonitorR3Handled;
1722 /** The number of times we've seen rep prefixes we can't handle. */
1723 STAMCOUNTER StatMonitorR3RepPrefix;
1724 /** Profiling the REP STOSD cases we've handled. */
1725 STAMPROFILE StatMonitorR3RepStosd;
1726 /** The number of times we're called in an async thread an need to flush. */
1727 STAMCOUNTER StatMonitorR3Async;
1728 /** The high wather mark for cModifiedPages. */
1729 uint16_t cModifiedPagesHigh;
1730 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1731# endif
1732# ifdef PGMPOOL_WITH_CACHE
1733 /** The number of cache hits. */
1734 STAMCOUNTER StatCacheHits;
1735 /** The number of cache misses. */
1736 STAMCOUNTER StatCacheMisses;
1737 /** The number of times we've got a conflict of 'kind' in the cache. */
1738 STAMCOUNTER StatCacheKindMismatches;
1739 /** Number of times we've been out of pages. */
1740 STAMCOUNTER StatCacheFreeUpOne;
1741 /** The number of cacheable allocations. */
1742 STAMCOUNTER StatCacheCacheable;
1743 /** The number of uncacheable allocations. */
1744 STAMCOUNTER StatCacheUncacheable;
1745# endif
1746#elif HC_ARCH_BITS == 64
1747 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1748#endif
1749 /** The AVL tree for looking up a page by its HC physical address. */
1750 AVLOHCPHYSTREE HCPhysTree;
1751 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1752 /** Array of pages. (cMaxPages in length)
1753 * The Id is the index into thist array.
1754 */
1755 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1756} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1757
1758
1759/** @def PGMPOOL_PAGE_2_PTR
1760 * Maps a pool page pool into the current context.
1761 *
1762 * @returns VBox status code.
1763 * @param pVM The VM handle.
1764 * @param pPage The pool page.
1765 *
1766 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1767 * small page window employeed by that function. Be careful.
1768 * @remark There is no need to assert on the result.
1769 */
1770#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1771# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1772#else
1773 inline R3R0PTRTYPE(void *) PGMPOOL_PAGE_2_PTR(PVM pVM, PPGMPOOLPAGE pPage)
1774 {
1775 Assert(pPage->pvPageR3);
1776 return pPage->pvPageR3;
1777 }
1778#endif
1779
1780
1781/**
1782 * Trees are using self relative offsets as pointers.
1783 * So, all its data, including the root pointer, must be in the heap for HC and GC
1784 * to have the same layout.
1785 */
1786typedef struct PGMTREES
1787{
1788 /** Physical access handlers (AVL range+offsetptr tree). */
1789 AVLROGCPHYSTREE PhysHandlers;
1790 /** Virtual access handlers (AVL range + GC ptr tree). */
1791 AVLROGCPTRTREE VirtHandlers;
1792 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1793 AVLROGCPHYSTREE PhysToVirtHandlers;
1794 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1795 AVLROGCPTRTREE HyperVirtHandlers;
1796} PGMTREES;
1797/** Pointer to PGM trees. */
1798typedef PGMTREES *PPGMTREES;
1799
1800
1801/** @name Paging mode macros
1802 * @{ */
1803#ifdef IN_RC
1804# define PGM_CTX(a,b) a##RC##b
1805# define PGM_CTX_STR(a,b) a "GC" b
1806# define PGM_CTX_DECL(type) VMMRCDECL(type)
1807#else
1808# ifdef IN_RING3
1809# define PGM_CTX(a,b) a##R3##b
1810# define PGM_CTX_STR(a,b) a "R3" b
1811# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1812# else
1813# define PGM_CTX(a,b) a##R0##b
1814# define PGM_CTX_STR(a,b) a "R0" b
1815# define PGM_CTX_DECL(type) VMMDECL(type)
1816# endif
1817#endif
1818
1819#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1820#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1821#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1822#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1823#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1824#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1825#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1826#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1827#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1828#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1829#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1830#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1831#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1832#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1833#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1834#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1835#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1836
1837#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1838#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1839#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1840#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1841#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1842#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1843#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1844#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1845#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1846#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1847#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1848#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1849#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1850#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1851#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1852#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1853#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1854
1855/* Shw_Gst */
1856#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1857#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1858#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1859#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1860#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1861#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1862#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1863#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1864#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1865#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1866#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1867#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1868#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1869#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1870#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1871#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1872#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1873#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1874#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1875
1876#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1877#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1878#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1879#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1880#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1881#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1882#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1883#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1884#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1885#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1886#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1887#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1888#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1889#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1890#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1891#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1892#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1893#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1894#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1895#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1896#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1897#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1898#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1899#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1900#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1901#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1902#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1903#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1904#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1905#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1906#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1907#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1908#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1909#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1910#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1911#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1912#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1913
1914#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1915#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1916/** @} */
1917
1918/**
1919 * Data for each paging mode.
1920 */
1921typedef struct PGMMODEDATA
1922{
1923 /** The guest mode type. */
1924 uint32_t uGstType;
1925 /** The shadow mode type. */
1926 uint32_t uShwType;
1927
1928 /** @name Function pointers for Shadow paging.
1929 * @{
1930 */
1931 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
1932 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1933 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1934 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1935
1936 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1937 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1938
1939 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1940 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1941 /** @} */
1942
1943 /** @name Function pointers for Guest paging.
1944 * @{
1945 */
1946 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
1947 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1948 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1949 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1950 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1951#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1952 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1953 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1954#endif
1955 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1956 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1957#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1958 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1959 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1960 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1961 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1962#endif
1963 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1964 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1965 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1966#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1967 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1968 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
1969#endif
1970 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1971 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
1972#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1973 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
1974 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
1975#endif
1976 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1977 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1978 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1979#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1980 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1981 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1982#endif
1983 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1984 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1985#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1986 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1987 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1988#endif
1989 /** @} */
1990
1991 /** @name Function pointers for Both Shadow and Guest paging.
1992 * @{
1993 */
1994 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
1995 /* no pfnR3BthTrap0eHandler */
1996 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1997 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1998 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
1999 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2000 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2001#ifdef VBOX_STRICT
2002 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2003#endif
2004
2005 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2006 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2007 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2008 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2009 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2010 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2011#ifdef VBOX_STRICT
2012 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2013#endif
2014
2015 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2016 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2017 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2018 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2019 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2020 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2021#ifdef VBOX_STRICT
2022 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2023#endif
2024 /** @} */
2025} PGMMODEDATA, *PPGMMODEDATA;
2026
2027
2028
2029/**
2030 * Converts a PGM pointer into a VM pointer.
2031 * @returns Pointer to the VM structure the PGM is part of.
2032 * @param pPGM Pointer to PGM instance data.
2033 */
2034#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2035
2036/**
2037 * PGM Data (part of VM)
2038 */
2039typedef struct PGM
2040{
2041 /** Offset to the VM structure. */
2042 RTINT offVM;
2043
2044 /*
2045 * This will be redefined at least two more times before we're done, I'm sure.
2046 * The current code is only to get on with the coding.
2047 * - 2004-06-10: initial version, bird.
2048 * - 2004-07-02: 1st time, bird.
2049 * - 2004-10-18: 2nd time, bird.
2050 * - 2005-07-xx: 3rd time, bird.
2051 */
2052
2053 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2054 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2055 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2056 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2057
2058 /** The host paging mode. (This is what SUPLib reports.) */
2059 SUPPAGINGMODE enmHostMode;
2060 /** The shadow paging mode. */
2061 PGMMODE enmShadowMode;
2062 /** The guest paging mode. */
2063 PGMMODE enmGuestMode;
2064
2065 /** The current physical address representing in the guest CR3 register. */
2066 RTGCPHYS GCPhysCR3;
2067 /** Pointer to the 5 page CR3 content mapping.
2068 * The first page is always the CR3 (in some form) while the 4 other pages
2069 * are used of the PDs in PAE mode. */
2070 RTGCPTR GCPtrCR3Mapping;
2071#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2072 uint32_t u32Alignment;
2073#endif
2074 /** The physical address of the currently monitored guest CR3 page.
2075 * When this value is NIL_RTGCPHYS no page is being monitored. */
2076 RTGCPHYS GCPhysGstCR3Monitored;
2077
2078 /** @name 32-bit Guest Paging.
2079 * @{ */
2080 /** The guest's page directory, R3 pointer. */
2081 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2082#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2083 /** The guest's page directory, R0 pointer. */
2084 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2085#endif
2086 /** The guest's page directory, static RC mapping. */
2087 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2088 /** @} */
2089
2090 /** @name PAE Guest Paging.
2091 * @{ */
2092 /** The guest's page directory pointer table, static RC mapping. */
2093 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2094 /** The guest's page directory pointer table, R3 pointer. */
2095 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2096#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2097 /** The guest's page directory pointer table, R0 pointer. */
2098 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2099#endif
2100
2101 /** The guest's page directories, R3 pointers.
2102 * These are individual pointers and don't have to be adjecent.
2103 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2104 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2105 /** The guest's page directories, R0 pointers.
2106 * Same restrictions as apGstPaePDsR3. */
2107#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2108 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2109#endif
2110 /** The guest's page directories, static GC mapping.
2111 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2112 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2113 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2114 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2115 RTGCPHYS aGCPhysGstPaePDs[4];
2116 /** The physical addresses of the monitored guest page directories (PAE). */
2117 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2118 /** @} */
2119
2120 /** @name AMD64 Guest Paging.
2121 * @{ */
2122 /** The guest's page directory pointer table, R3 pointer. */
2123 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2124#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2125 /** The guest's page directory pointer table, R0 pointer. */
2126 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2127#endif
2128 /** @} */
2129
2130 /** @name 32-bit Shadow Paging
2131 * @{ */
2132#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2133 /** The Physical Address (HC) of the current active shadow CR3. */
2134 RTHCPHYS HCPhysShwCR3;
2135 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2136 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2137 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2138 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2139 /** Pointer to the page of the current active CR3 - RC Ptr. */
2140 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2141# if HC_ARCH_BITS == 64
2142 RTRCPTR alignment6; /**< structure size alignment. */
2143# endif
2144#else
2145 /** The 32-Bit PD - R3 Ptr. */
2146 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2147 /** The 32-Bit PD - R0 Ptr. */
2148 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2149 /** The 32-Bit PD - RC Ptr. */
2150 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2151# if HC_ARCH_BITS == 64
2152 uint32_t u32Padding1; /**< alignment padding. */
2153# endif
2154 /** The Physical Address (HC) of the 32-Bit PD. */
2155 RTHCPHYS HCPhysShw32BitPD;
2156 /** @} */
2157
2158 /** @name PAE Shadow Paging
2159 * @{ */
2160 /** The four PDs for the low 4GB - R3 Ptr.
2161 * Even though these are 4 pointers, what they point at is a single table.
2162 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2163 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2164# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2165 /** The four PDs for the low 4GB - R0 Ptr.
2166 * Same kind of mapping as apHCPaePDs. */
2167 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2168# endif
2169 /** The four PDs for the low 4GB - RC Ptr.
2170 * Same kind of mapping as apHCPaePDs. */
2171 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2172 /** The Physical Address (HC) of the four PDs for the low 4GB.
2173 * These are *NOT* 4 contiguous pages. */
2174 RTHCPHYS aHCPhysPaePDs[4];
2175 /** The Physical Address (HC) of the PAE PDPT. */
2176 RTHCPHYS HCPhysShwPaePdpt;
2177 /** The PAE PDPT - R3 Ptr. */
2178 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2179 /** The PAE PDPT - R0 Ptr. */
2180 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2181 /** The PAE PDPT - RC Ptr. */
2182 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2183 /** @} */
2184# if HC_ARCH_BITS == 64
2185 RTRCPTR alignment5; /**< structure size alignment. */
2186# endif
2187
2188 /** @name AMD64 Shadow Paging
2189 * Extends PAE Paging.
2190 * @{ */
2191 /** The Page Map Level 4 table - R3 Ptr. */
2192 R3PTRTYPE(PX86PML4) pShwPaePml4R3;
2193# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2194 /** The Page Map Level 4 table - R0 Ptr. */
2195 R0PTRTYPE(PX86PML4) pShwPaePml4R0;
2196# endif
2197 /** The Physical Address (HC) of the Page Map Level 4 table. */
2198 RTHCPHYS HCPhysShwPaePml4;
2199 /** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
2200 R3PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R3;
2201 /** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
2202 R0PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R0;
2203 /** @}*/
2204
2205 /** @name Nested Shadow Paging
2206 * @{ */
2207 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2208 RTR3PTR pShwNestedRootR3;
2209# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2210 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2211 RTR0PTR pShwNestedRootR0;
2212# endif
2213 /** The Physical Address (HC) of the nested paging root. */
2214 RTHCPHYS HCPhysShwNestedRoot;
2215#endif
2216 /** @} */
2217
2218 /** @name Function pointers for Shadow paging.
2219 * @{
2220 */
2221 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2222 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2223 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2224 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2225
2226 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2227 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2228
2229 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2230 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2231
2232 /** @} */
2233
2234 /** @name Function pointers for Guest paging.
2235 * @{
2236 */
2237 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2238 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2239 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2240 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2241 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2242#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2243 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2244 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2245#endif
2246 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2247 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2248#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2249 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2250 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2251 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2252 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2253#endif
2254 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2255 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2256 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2257#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2258 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2259 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2260#endif
2261 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2262 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2263#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2264 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2265 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2266#endif
2267#if HC_ARCH_BITS == 64
2268 RTRCPTR alignment3; /**< structure size alignment. */
2269#endif
2270
2271 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2272 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2273 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2274#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2275 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2276 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2277#endif
2278 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2279 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2280#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2281 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2282 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2283#endif
2284 /** @} */
2285
2286 /** @name Function pointers for Both Shadow and Guest paging.
2287 * @{
2288 */
2289 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2290 /* no pfnR3BthTrap0eHandler */
2291 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2292 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2293 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2294 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2295 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2296 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2297
2298 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2299 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2300 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2301 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2302 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2303 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2304 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2305
2306 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2307 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2308 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2309 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2310 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2311 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2312 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2313#if HC_ARCH_BITS == 64
2314 RTRCPTR alignment2; /**< structure size alignment. */
2315#endif
2316 /** @} */
2317
2318 /** Pointer to SHW+GST mode data (function pointers).
2319 * The index into this table is made up from */
2320 R3PTRTYPE(PPGMMODEDATA) paModeData;
2321
2322 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2323 * This is sorted by physical address and contains no overlapping ranges. */
2324 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2325 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2326 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2327 /** RC pointer corresponding to PGM::pRamRangesR3. */
2328 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2329 /** The configured RAM size. */
2330 RTUINT cbRamSize;
2331
2332 /** Pointer to the list of ROM ranges - for R3.
2333 * This is sorted by physical address and contains no overlapping ranges. */
2334 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2335 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2336 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2337 /** RC pointer corresponding to PGM::pRomRangesR3. */
2338 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2339 /** Alignment padding. */
2340 RTRCPTR GCPtrPadding2;
2341
2342 /** Pointer to the list of MMIO2 ranges - for R3.
2343 * Registration order. */
2344 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2345
2346 /** PGM offset based trees - R3 Ptr. */
2347 R3PTRTYPE(PPGMTREES) pTreesR3;
2348 /** PGM offset based trees - R0 Ptr. */
2349 R0PTRTYPE(PPGMTREES) pTreesR0;
2350 /** PGM offset based trees - RC Ptr. */
2351 RCPTRTYPE(PPGMTREES) pTreesRC;
2352
2353 /** Linked list of GC mappings - for RC.
2354 * The list is sorted ascending on address.
2355 */
2356 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2357 /** Linked list of GC mappings - for HC.
2358 * The list is sorted ascending on address.
2359 */
2360 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2361 /** Linked list of GC mappings - for R0.
2362 * The list is sorted ascending on address.
2363 */
2364 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2365
2366 /** If set no conflict checks are required. (boolean) */
2367 bool fMappingsFixed;
2368 /** If set, then no mappings are put into the shadow page table. (boolean) */
2369 bool fDisableMappings;
2370 /** Size of fixed mapping */
2371 uint32_t cbMappingFixed;
2372 /** Base address (GC) of fixed mapping */
2373 RTGCPTR GCPtrMappingFixed;
2374#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2375 uint32_t u32Padding0; /**< alignment padding. */
2376#endif
2377
2378
2379 /** @name Intermediate Context
2380 * @{ */
2381 /** Pointer to the intermediate page directory - Normal. */
2382 R3PTRTYPE(PX86PD) pInterPD;
2383 /** Pointer to the intermedate page tables - Normal.
2384 * There are two page tables, one for the identity mapping and one for
2385 * the host context mapping (of the core code). */
2386 R3PTRTYPE(PX86PT) apInterPTs[2];
2387 /** Pointer to the intermedate page tables - PAE. */
2388 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2389 /** Pointer to the intermedate page directory - PAE. */
2390 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2391 /** Pointer to the intermedate page directory - PAE. */
2392 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2393 /** Pointer to the intermedate page-map level 4 - AMD64. */
2394 R3PTRTYPE(PX86PML4) pInterPaePML4;
2395 /** Pointer to the intermedate page directory - AMD64. */
2396 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2397 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2398 RTHCPHYS HCPhysInterPD;
2399 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2400 RTHCPHYS HCPhysInterPaePDPT;
2401 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2402 RTHCPHYS HCPhysInterPaePML4;
2403 /** @} */
2404
2405 /** Base address of the dynamic page mapping area.
2406 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2407 */
2408 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2409 /** The index of the last entry used in the dynamic page mapping area. */
2410 RTUINT iDynPageMapLast;
2411 /** Cache containing the last entries in the dynamic page mapping area.
2412 * The cache size is covering half of the mapping area. */
2413 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2414
2415 /** The address of the ring-0 mapping cache if we're making use of it. */
2416 RTR0PTR pvR0DynMapUsed;
2417#if HC_ARCH_BITS == 32
2418 RTR0PTR R0PtrPadding0; /**< Alignment. */
2419#endif
2420
2421
2422 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2423 RTGCPHYS GCPhys4MBPSEMask;
2424
2425 /** A20 gate mask.
2426 * Our current approach to A20 emulation is to let REM do it and don't bother
2427 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2428 * But whould need arrise, we'll subject physical addresses to this mask. */
2429 RTGCPHYS GCPhysA20Mask;
2430 /** A20 gate state - boolean! */
2431 RTUINT fA20Enabled;
2432
2433 /** What needs syncing (PGM_SYNC_*).
2434 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2435 * PGMFlushTLB, and PGMR3Load. */
2436 RTUINT fSyncFlags;
2437
2438 /** PGM critical section.
2439 * This protects the physical & virtual access handlers, ram ranges,
2440 * and the page flag updating (some of it anyway).
2441 */
2442 PDMCRITSECT CritSect;
2443
2444 /** Shadow Page Pool - R3 Ptr. */
2445 R3PTRTYPE(PPGMPOOL) pPoolR3;
2446 /** Shadow Page Pool - R0 Ptr. */
2447 R0PTRTYPE(PPGMPOOL) pPoolR0;
2448 /** Shadow Page Pool - RC Ptr. */
2449 RCPTRTYPE(PPGMPOOL) pPoolRC;
2450
2451 /** We're not in a state which permits writes to guest memory.
2452 * (Only used in strict builds.) */
2453 bool fNoMorePhysWrites;
2454
2455 /** Flush the cache on the next access. */
2456 bool fPhysCacheFlushPending;
2457/** @todo r=bird: Fix member names!*/
2458 /** PGMPhysRead cache */
2459 PGMPHYSCACHE pgmphysreadcache;
2460 /** PGMPhysWrite cache */
2461 PGMPHYSCACHE pgmphyswritecache;
2462
2463 /**
2464 * Data associated with managing the ring-3 mappings of the allocation chunks.
2465 */
2466 struct
2467 {
2468 /** The chunk tree, ordered by chunk id. */
2469#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2470 R3PTRTYPE(PAVLU32NODECORE) pTree;
2471#else
2472 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2473#endif
2474 /** The chunk mapping TLB. */
2475 PGMCHUNKR3MAPTLB Tlb;
2476 /** The number of mapped chunks. */
2477 uint32_t c;
2478 /** The maximum number of mapped chunks.
2479 * @cfgm PGM/MaxRing3Chunks */
2480 uint32_t cMax;
2481 /** The chunk age tree, ordered by ageing sequence number. */
2482 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2483 /** The current time. */
2484 uint32_t iNow;
2485 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2486 uint32_t AgeingCountdown;
2487 } ChunkR3Map;
2488
2489 /**
2490 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2491 */
2492 PGMPAGER3MAPTLB PhysTlbHC;
2493
2494 /** @name The zero page.
2495 * @{ */
2496 /** The host physical address of the zero page. */
2497 RTHCPHYS HCPhysZeroPg;
2498 /** The ring-3 mapping of the zero page. */
2499 RTR3PTR pvZeroPgR3;
2500 /** The ring-0 mapping of the zero page. */
2501 RTR0PTR pvZeroPgR0;
2502 /** The GC mapping of the zero page. */
2503 RTGCPTR pvZeroPgGC;
2504#if GC_ARCH_BITS != 32
2505 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2506#endif
2507 /** @}*/
2508
2509 /** The number of handy pages. */
2510 uint32_t cHandyPages;
2511 /**
2512 * Array of handy pages.
2513 *
2514 * This array is used in a two way communication between pgmPhysAllocPage
2515 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2516 * an intermediary.
2517 *
2518 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2519 * (The current size of 32 pages, means 128 KB of handy memory.)
2520 */
2521 GMMPAGEDESC aHandyPages[32];
2522
2523 /** @name Release Statistics
2524 * @{ */
2525 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2526 uint32_t cPrivatePages; /**< The number of private pages. */
2527 uint32_t cSharedPages; /**< The number of shared pages. */
2528 uint32_t cZeroPages; /**< The number of zero backed pages. */
2529 /** The number of times the guest has switched mode since last reset or statistics reset. */
2530 STAMCOUNTER cGuestModeChanges;
2531 /** @} */
2532
2533#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2534 /** RC: Which statistic this \#PF should be attributed to. */
2535 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2536 RTRCPTR padding0;
2537 /** R0: Which statistic this \#PF should be attributed to. */
2538 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2539 RTR0PTR padding1;
2540
2541 /* Common */
2542# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2543 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2544 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2545 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2546 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2547 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2548 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2549# endif
2550 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2551 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2552
2553 /* R3 only: */
2554 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2555 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2556 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2557 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2558 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2559 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2560
2561 /* RC only: */
2562 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2563 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2564 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2565 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2566
2567 /* RZ only: */
2568 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2569 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2570 STAMPROFILE StatRZTrap0eTimeSyncPT;
2571 STAMPROFILE StatRZTrap0eTimeMapping;
2572 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2573 STAMPROFILE StatRZTrap0eTimeHandlers;
2574 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2575 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2576 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2577 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2578 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2579 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2580 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2581 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2582 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2583 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2584 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2585 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2586 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2587 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2588 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2589 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2590 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2591 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2592 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2593 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2594 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2595 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2596 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2597 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2598 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2599 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2600 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2601 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2602 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2603 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2604 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2605 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2606 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2607 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2608 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2609 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2610 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2611 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2612 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2613 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2614 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2615 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2616 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2617
2618 /* HC - R3 and (maybe) R0: */
2619
2620 /* RZ & R3: */
2621 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2622 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2623 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2624 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2625 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2626 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2627 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2628 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2629 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2630 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2631 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2632 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2633 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2634 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2635 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2636 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2637 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2638 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2639 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2640 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2641 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2642 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2643 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2644 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2645 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2646 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2647 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2648 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2649 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2650 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2651 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2652 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2653 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2654 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2655 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2656 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2657 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2658 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2659 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2660 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2661 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2662 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2663 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2664 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2665 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2666 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2667 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2668/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2669 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2670 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2671 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2672 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2673 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2674 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2675
2676 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2677 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2678 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2679 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2680 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2681 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2682 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2683 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2684 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2685 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2686 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2687 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2688 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2689 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2690 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2691 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2692 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2693 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2694 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2695 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2696 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2697 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2698 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2699 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2700 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2701 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2702 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2703 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2704 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2705 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2706 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2707 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2708 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2709 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2710 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2711 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2712 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2713 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2714 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2715 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2716 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2717 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2718 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2719 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2720 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2721 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2722 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2723/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2724 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2725 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2726 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2727 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2728 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2729 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2730#endif /* VBOX_WITH_STATISTICS */
2731} PGM;
2732/** Pointer to the PGM instance data. */
2733typedef PGM *PPGM;
2734
2735
2736/**
2737 * PGMCPU Data (part of VMCPU).
2738 */
2739typedef struct PGMCPU
2740{
2741 /** Offset to the VMCPU structure. */
2742 RTINT offVMCPU;
2743 /** Automatically tracked physical memory mapping set.
2744 * Ring-0 and strict raw-mode builds. */
2745 PGMMAPSET AutoSet;
2746} PGMCPU;
2747/** Pointer to the per-cpu PGM data. */
2748typedef PGMCPU *PPGMCPU;
2749
2750
2751/** @name PGM::fSyncFlags Flags
2752 * @{
2753 */
2754/** Updates the virtual access handler state bit in PGMPAGE. */
2755#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2756/** Always sync CR3. */
2757#define PGM_SYNC_ALWAYS RT_BIT(1)
2758/** Check monitoring on next CR3 (re)load and invalidate page. */
2759#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2760/** Clear the page pool (a light weight flush). */
2761#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2762/** @} */
2763
2764
2765__BEGIN_DECLS
2766
2767int pgmLock(PVM pVM);
2768void pgmUnlock(PVM pVM);
2769
2770VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2771VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2772
2773int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2774int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2775PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2776void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2777DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2778
2779void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2780int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2781DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2782#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2783void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2784#else
2785# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2786#endif
2787DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2788
2789
2790void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2791int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2792int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2793int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2794#ifdef IN_RING3
2795int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2796int pgmR3PhysRamReset(PVM pVM);
2797int pgmR3PhysRomReset(PVM pVM);
2798#ifndef VBOX_WITH_NEW_PHYS_CODE
2799int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2800#endif
2801
2802int pgmR3PoolInit(PVM pVM);
2803void pgmR3PoolRelocate(PVM pVM);
2804void pgmR3PoolReset(PVM pVM);
2805
2806#endif /* IN_RING3 */
2807#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2808void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2809#endif
2810int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2811PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2812void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2813void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2814int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2815void pgmPoolFlushAll(PVM pVM);
2816void pgmPoolClearAll(PVM pVM);
2817int pgmPoolSyncCR3(PVM pVM);
2818void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2819void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2820int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2821PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2822void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2823void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2824uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2825void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2826#ifdef PGMPOOL_WITH_MONITORING
2827# ifdef IN_RING3
2828void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2829# else
2830void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2831# endif
2832int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2833void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2834void pgmPoolMonitorModifiedClearAll(PVM pVM);
2835int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2836int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2837#endif
2838
2839__END_DECLS
2840
2841
2842/**
2843 * Gets the PGMRAMRANGE structure for a guest page.
2844 *
2845 * @returns Pointer to the RAM range on success.
2846 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2847 *
2848 * @param pPGM PGM handle.
2849 * @param GCPhys The GC physical address.
2850 */
2851DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2852{
2853 /*
2854 * Optimize for the first range.
2855 */
2856 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2857 RTGCPHYS off = GCPhys - pRam->GCPhys;
2858 if (RT_UNLIKELY(off >= pRam->cb))
2859 {
2860 do
2861 {
2862 pRam = pRam->CTX_SUFF(pNext);
2863 if (RT_UNLIKELY(!pRam))
2864 break;
2865 off = GCPhys - pRam->GCPhys;
2866 } while (off >= pRam->cb);
2867 }
2868 return pRam;
2869}
2870
2871
2872/**
2873 * Gets the PGMPAGE structure for a guest page.
2874 *
2875 * @returns Pointer to the page on success.
2876 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2877 *
2878 * @param pPGM PGM handle.
2879 * @param GCPhys The GC physical address.
2880 */
2881DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2882{
2883 /*
2884 * Optimize for the first range.
2885 */
2886 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2887 RTGCPHYS off = GCPhys - pRam->GCPhys;
2888 if (RT_UNLIKELY(off >= pRam->cb))
2889 {
2890 do
2891 {
2892 pRam = pRam->CTX_SUFF(pNext);
2893 if (RT_UNLIKELY(!pRam))
2894 return NULL;
2895 off = GCPhys - pRam->GCPhys;
2896 } while (off >= pRam->cb);
2897 }
2898 return &pRam->aPages[off >> PAGE_SHIFT];
2899}
2900
2901
2902/**
2903 * Gets the PGMPAGE structure for a guest page.
2904 *
2905 * Old Phys code: Will make sure the page is present.
2906 *
2907 * @returns VBox status code.
2908 * @retval VINF_SUCCESS and a valid *ppPage on success.
2909 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2910 *
2911 * @param pPGM PGM handle.
2912 * @param GCPhys The GC physical address.
2913 * @param ppPage Where to store the page poitner on success.
2914 */
2915DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2916{
2917 /*
2918 * Optimize for the first range.
2919 */
2920 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2921 RTGCPHYS off = GCPhys - pRam->GCPhys;
2922 if (RT_UNLIKELY(off >= pRam->cb))
2923 {
2924 do
2925 {
2926 pRam = pRam->CTX_SUFF(pNext);
2927 if (RT_UNLIKELY(!pRam))
2928 {
2929 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2930 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2931 }
2932 off = GCPhys - pRam->GCPhys;
2933 } while (off >= pRam->cb);
2934 }
2935 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2936#ifndef VBOX_WITH_NEW_PHYS_CODE
2937
2938 /*
2939 * Make sure it's present.
2940 */
2941 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2942 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2943 {
2944#ifdef IN_RING3
2945 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2946#else
2947 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2948#endif
2949 if (RT_FAILURE(rc))
2950 {
2951 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2952 return rc;
2953 }
2954 Assert(rc == VINF_SUCCESS);
2955 }
2956#endif
2957 return VINF_SUCCESS;
2958}
2959
2960
2961
2962
2963/**
2964 * Gets the PGMPAGE structure for a guest page.
2965 *
2966 * Old Phys code: Will make sure the page is present.
2967 *
2968 * @returns VBox status code.
2969 * @retval VINF_SUCCESS and a valid *ppPage on success.
2970 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2971 *
2972 * @param pPGM PGM handle.
2973 * @param GCPhys The GC physical address.
2974 * @param ppPage Where to store the page poitner on success.
2975 * @param ppRamHint Where to read and store the ram list hint.
2976 * The caller initializes this to NULL before the call.
2977 */
2978DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2979{
2980 RTGCPHYS off;
2981 PPGMRAMRANGE pRam = *ppRamHint;
2982 if ( !pRam
2983 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2984 {
2985 pRam = pPGM->CTX_SUFF(pRamRanges);
2986 off = GCPhys - pRam->GCPhys;
2987 if (RT_UNLIKELY(off >= pRam->cb))
2988 {
2989 do
2990 {
2991 pRam = pRam->CTX_SUFF(pNext);
2992 if (RT_UNLIKELY(!pRam))
2993 {
2994 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2995 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2996 }
2997 off = GCPhys - pRam->GCPhys;
2998 } while (off >= pRam->cb);
2999 }
3000 *ppRamHint = pRam;
3001 }
3002 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3003#ifndef VBOX_WITH_NEW_PHYS_CODE
3004
3005 /*
3006 * Make sure it's present.
3007 */
3008 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3009 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3010 {
3011#ifdef IN_RING3
3012 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3013#else
3014 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3015#endif
3016 if (RT_FAILURE(rc))
3017 {
3018 *ppPage = NULL; /* Shut up annoying smart ass. */
3019 return rc;
3020 }
3021 Assert(rc == VINF_SUCCESS);
3022 }
3023#endif
3024 return VINF_SUCCESS;
3025}
3026
3027
3028/**
3029 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3030 *
3031 * @returns Pointer to the page on success.
3032 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3033 *
3034 * @param pPGM PGM handle.
3035 * @param GCPhys The GC physical address.
3036 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3037 */
3038DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3039{
3040 /*
3041 * Optimize for the first range.
3042 */
3043 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3044 RTGCPHYS off = GCPhys - pRam->GCPhys;
3045 if (RT_UNLIKELY(off >= pRam->cb))
3046 {
3047 do
3048 {
3049 pRam = pRam->CTX_SUFF(pNext);
3050 if (RT_UNLIKELY(!pRam))
3051 return NULL;
3052 off = GCPhys - pRam->GCPhys;
3053 } while (off >= pRam->cb);
3054 }
3055 *ppRam = pRam;
3056 return &pRam->aPages[off >> PAGE_SHIFT];
3057}
3058
3059
3060/**
3061 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3062 *
3063 * @returns Pointer to the page on success.
3064 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3065 *
3066 * @param pPGM PGM handle.
3067 * @param GCPhys The GC physical address.
3068 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3069 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3070 */
3071DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3072{
3073 /*
3074 * Optimize for the first range.
3075 */
3076 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3077 RTGCPHYS off = GCPhys - pRam->GCPhys;
3078 if (RT_UNLIKELY(off >= pRam->cb))
3079 {
3080 do
3081 {
3082 pRam = pRam->CTX_SUFF(pNext);
3083 if (RT_UNLIKELY(!pRam))
3084 {
3085 *ppRam = NULL; /* Shut up silly GCC warnings. */
3086 *ppPage = NULL; /* ditto */
3087 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3088 }
3089 off = GCPhys - pRam->GCPhys;
3090 } while (off >= pRam->cb);
3091 }
3092 *ppRam = pRam;
3093 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3094#ifndef VBOX_WITH_NEW_PHYS_CODE
3095
3096 /*
3097 * Make sure it's present.
3098 */
3099 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3100 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3101 {
3102#ifdef IN_RING3
3103 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3104#else
3105 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3106#endif
3107 if (RT_FAILURE(rc))
3108 {
3109 *ppPage = NULL; /* Shut up silly GCC warnings. */
3110 *ppPage = NULL; /* ditto */
3111 return rc;
3112 }
3113 Assert(rc == VINF_SUCCESS);
3114
3115 }
3116#endif
3117 return VINF_SUCCESS;
3118}
3119
3120
3121/**
3122 * Convert GC Phys to HC Phys.
3123 *
3124 * @returns VBox status.
3125 * @param pPGM PGM handle.
3126 * @param GCPhys The GC physical address.
3127 * @param pHCPhys Where to store the corresponding HC physical address.
3128 *
3129 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3130 * Avoid when writing new code!
3131 */
3132DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3133{
3134 PPGMPAGE pPage;
3135 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3136 if (RT_FAILURE(rc))
3137 return rc;
3138 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3139 return VINF_SUCCESS;
3140}
3141
3142
3143#ifndef IN_RC
3144/**
3145 * Queries the Physical TLB entry for a physical guest page,
3146 * attemting to load the TLB entry if necessary.
3147 *
3148 * @returns VBox status code.
3149 * @retval VINF_SUCCESS on success
3150 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3151 * @param pPGM The PGM instance handle.
3152 * @param GCPhys The address of the guest page.
3153 * @param ppTlbe Where to store the pointer to the TLB entry.
3154 */
3155
3156DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3157{
3158 int rc;
3159 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3160 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3161 {
3162 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3163 rc = VINF_SUCCESS;
3164 }
3165 else
3166 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3167 *ppTlbe = pTlbe;
3168 return rc;
3169}
3170#endif /* !IN_RC */
3171
3172#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3173
3174# ifndef VBOX_WITH_NEW_PHYS_CODE
3175/**
3176 * Convert GC Phys to HC Virt.
3177 *
3178 * @returns VBox status.
3179 * @param pPGM PGM handle.
3180 * @param GCPhys The GC physical address.
3181 * @param pHCPtr Where to store the corresponding HC virtual address.
3182 *
3183 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3184 */
3185DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3186{
3187 PPGMRAMRANGE pRam;
3188 PPGMPAGE pPage;
3189 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3190 if (RT_FAILURE(rc))
3191 {
3192 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3193 return rc;
3194 }
3195 RTGCPHYS off = GCPhys - pRam->GCPhys;
3196
3197 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3198 {
3199 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3200 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3201 return VINF_SUCCESS;
3202 }
3203 if (pRam->pvR3)
3204 {
3205 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3206 return VINF_SUCCESS;
3207 }
3208 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3209 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3210}
3211# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3212
3213
3214/**
3215 * Convert GC Phys to HC Virt.
3216 *
3217 * @returns VBox status.
3218 * @param PVM VM handle.
3219 * @param pRam Ram range
3220 * @param GCPhys The GC physical address.
3221 * @param pHCPtr Where to store the corresponding HC virtual address.
3222 *
3223 * @deprecated This will be eliminated. Don't use it.
3224 */
3225DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3226{
3227 RTGCPHYS off = GCPhys - pRam->GCPhys;
3228 Assert(off < pRam->cb);
3229
3230 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3231 {
3232 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3233 /* Physical chunk in dynamically allocated range not present? */
3234 if (RT_UNLIKELY(!pRam->paChunkR3Ptrs[idx]))
3235 {
3236#ifdef IN_RING3
3237 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3238#else
3239 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3240#endif
3241 if (rc != VINF_SUCCESS)
3242 {
3243 *pHCPtr = 0; /* GCC crap */
3244 return rc;
3245 }
3246 }
3247 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3248 return VINF_SUCCESS;
3249 }
3250 if (pRam->pvR3)
3251 {
3252 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3253 return VINF_SUCCESS;
3254 }
3255 *pHCPtr = 0; /* GCC crap */
3256 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3257}
3258
3259#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3260
3261/**
3262 * Convert GC Phys to HC Virt and HC Phys.
3263 *
3264 * @returns VBox status.
3265 * @param pPGM PGM handle.
3266 * @param GCPhys The GC physical address.
3267 * @param pHCPtr Where to store the corresponding HC virtual address.
3268 * @param pHCPhys Where to store the HC Physical address and its flags.
3269 *
3270 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3271 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3272 */
3273DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3274{
3275 PPGMRAMRANGE pRam;
3276 PPGMPAGE pPage;
3277 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3278 if (RT_FAILURE(rc))
3279 {
3280 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3281 *pHCPhys = 0; /* ditto */
3282 return rc;
3283 }
3284 RTGCPHYS off = GCPhys - pRam->GCPhys;
3285
3286 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3287 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3288 {
3289 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3290#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3291 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3292 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3293#else
3294 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3295#endif
3296 return VINF_SUCCESS;
3297 }
3298 if (pRam->pvR3)
3299 {
3300 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3301 return VINF_SUCCESS;
3302 }
3303 *pHCPtr = 0;
3304 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3305}
3306
3307
3308/**
3309 * Clears flags associated with a RAM address.
3310 *
3311 * @returns VBox status code.
3312 * @param pPGM PGM handle.
3313 * @param GCPhys Guest context physical address.
3314 * @param fFlags fFlags to clear. (Bits 0-11.)
3315 */
3316DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3317{
3318 PPGMPAGE pPage;
3319 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3320 if (RT_FAILURE(rc))
3321 return rc;
3322
3323 fFlags &= ~X86_PTE_PAE_PG_MASK;
3324 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3325 return VINF_SUCCESS;
3326}
3327
3328
3329/**
3330 * Clears flags associated with a RAM address.
3331 *
3332 * @returns VBox status code.
3333 * @param pPGM PGM handle.
3334 * @param GCPhys Guest context physical address.
3335 * @param fFlags fFlags to clear. (Bits 0-11.)
3336 * @param ppRamHint Where to read and store the ram list hint.
3337 * The caller initializes this to NULL before the call.
3338 */
3339DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3340{
3341 PPGMPAGE pPage;
3342 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3343 if (RT_FAILURE(rc))
3344 return rc;
3345
3346 fFlags &= ~X86_PTE_PAE_PG_MASK;
3347 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3348 return VINF_SUCCESS;
3349}
3350
3351
3352/**
3353 * Sets (bitwise OR) flags associated with a RAM address.
3354 *
3355 * @returns VBox status code.
3356 * @param pPGM PGM handle.
3357 * @param GCPhys Guest context physical address.
3358 * @param fFlags fFlags to set clear. (Bits 0-11.)
3359 */
3360DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3361{
3362 PPGMPAGE pPage;
3363 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3364 if (RT_FAILURE(rc))
3365 return rc;
3366
3367 fFlags &= ~X86_PTE_PAE_PG_MASK;
3368 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3369 return VINF_SUCCESS;
3370}
3371
3372
3373/**
3374 * Sets (bitwise OR) flags associated with a RAM address.
3375 *
3376 * @returns VBox status code.
3377 * @param pPGM PGM handle.
3378 * @param GCPhys Guest context physical address.
3379 * @param fFlags fFlags to set clear. (Bits 0-11.)
3380 * @param ppRamHint Where to read and store the ram list hint.
3381 * The caller initializes this to NULL before the call.
3382 */
3383DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3384{
3385 PPGMPAGE pPage;
3386 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3387 if (RT_FAILURE(rc))
3388 return rc;
3389
3390 fFlags &= ~X86_PTE_PAE_PG_MASK;
3391 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3392 return VINF_SUCCESS;
3393}
3394
3395
3396/**
3397 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3398 * Takes PSE-36 into account.
3399 *
3400 * @returns guest physical address
3401 * @param pPGM Pointer to the PGM instance data.
3402 * @param Pde Guest Pde
3403 */
3404DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3405{
3406 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3407 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3408
3409 return GCPhys & pPGM->GCPhys4MBPSEMask;
3410}
3411
3412
3413/**
3414 * Gets the page directory entry for the specified address (32-bit paging).
3415 *
3416 * @returns The page directory entry in question.
3417 * @param pPGM Pointer to the PGM instance data.
3418 * @param GCPtr The address.
3419 */
3420DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3421{
3422#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3423 PCX86PD pGuestPD = 0;
3424 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3425 if (RT_FAILURE(rc))
3426 {
3427 X86PDE ZeroPde = {0};
3428 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3429 }
3430 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3431#else
3432 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3433#endif
3434}
3435
3436
3437/**
3438 * Gets the address of a specific page directory entry (32-bit paging).
3439 *
3440 * @returns Pointer the page directory entry in question.
3441 * @param pPGM Pointer to the PGM instance data.
3442 * @param GCPtr The address.
3443 */
3444DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3445{
3446#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3447 PX86PD pGuestPD = 0;
3448 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3449 AssertRCReturn(rc, 0);
3450 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3451#else
3452 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3453#endif
3454}
3455
3456
3457/**
3458 * Gets the address the guest page directory (32-bit paging).
3459 *
3460 * @returns Pointer the page directory entry in question.
3461 * @param pPGM Pointer to the PGM instance data.
3462 */
3463DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3464{
3465#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3466 PX86PD pGuestPD = 0;
3467 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3468 AssertRCReturn(rc, 0);
3469 return pGuestPD;
3470#else
3471 return pPGM->CTX_SUFF(pGst32BitPd);
3472#endif
3473}
3474
3475
3476/**
3477 * Gets the guest page directory pointer table.
3478 *
3479 * @returns Pointer to the page directory in question.
3480 * @returns NULL if the page directory is not present or on an invalid page.
3481 * @param pPGM Pointer to the PGM instance data.
3482 */
3483DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3484{
3485#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3486 PX86PDPT pGuestPDPT = 0;
3487 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPDPT);
3488 AssertRCReturn(rc, 0);
3489 return pGuestPDPT;
3490#else
3491 return pPGM->CTX_SUFF(pGstPaePdpt);
3492#endif
3493}
3494
3495
3496/**
3497 * Gets the guest page directory pointer table entry for the specified address.
3498 *
3499 * @returns Pointer to the page directory in question.
3500 * @returns NULL if the page directory is not present or on an invalid page.
3501 * @param pPGM Pointer to the PGM instance data.
3502 * @param GCPtr The address.
3503 */
3504DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3505{
3506 AssertGCPtr32(GCPtr);
3507
3508#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3509 PX86PDPT pGuestPDPT = 0;
3510 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPDPT);
3511 AssertRCReturn(rc, 0);
3512 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3513#else
3514 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3515#endif
3516}
3517
3518
3519/**
3520 * Gets the page directory for the specified address.
3521 *
3522 * @returns Pointer to the page directory in question.
3523 * @returns NULL if the page directory is not present or on an invalid page.
3524 * @param pPGM Pointer to the PGM instance data.
3525 * @param GCPtr The address.
3526 */
3527DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3528{
3529 AssertGCPtr32(GCPtr);
3530
3531#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3532 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3533 AssertReturn(pGuestPDPT, 0);
3534#else
3535 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3536#endif
3537 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3538 if (pGuestPDPT->a[iPdPt].n.u1Present)
3539 {
3540#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3541 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3542 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3543#endif
3544
3545 /* cache is out-of-sync. */
3546 PX86PDPAE pPD;
3547 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3548 if (RT_SUCCESS(rc))
3549 return pPD;
3550 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3551 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3552 }
3553 return NULL;
3554}
3555
3556
3557/**
3558 * Gets the page directory entry for the specified address.
3559 *
3560 * @returns Pointer to the page directory entry in question.
3561 * @returns NULL if the page directory is not present or on an invalid page.
3562 * @param pPGM Pointer to the PGM instance data.
3563 * @param GCPtr The address.
3564 */
3565DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3566{
3567 AssertGCPtr32(GCPtr);
3568
3569#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3570 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3571 AssertReturn(pGuestPDPT, 0);
3572#else
3573 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3574#endif
3575 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3576 if (pGuestPDPT->a[iPdPt].n.u1Present)
3577 {
3578 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3579#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3580 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3581 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3582#endif
3583
3584 /* The cache is out-of-sync. */
3585 PX86PDPAE pPD;
3586 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3587 if (RT_SUCCESS(rc))
3588 return &pPD->a[iPD];
3589 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3590 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3591 }
3592 return NULL;
3593}
3594
3595
3596/**
3597 * Gets the page directory entry for the specified address.
3598 *
3599 * @returns The page directory entry in question.
3600 * @returns A non-present entry if the page directory is not present or on an invalid page.
3601 * @param pPGM Pointer to the PGM instance data.
3602 * @param GCPtr The address.
3603 */
3604DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3605{
3606 AssertGCPtr32(GCPtr);
3607
3608#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3609 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3610 if (RT_LIKELY(pGuestPDPT))
3611#else
3612 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3613#endif
3614 {
3615 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3616 if (pGuestPDPT->a[iPdPt].n.u1Present)
3617 {
3618 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3619#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3620 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3621 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3622#endif
3623
3624 /* cache is out-of-sync. */
3625 PX86PDPAE pPD;
3626 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3627 if (RT_SUCCESS(rc))
3628 return pPD->a[iPD];
3629 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3630 }
3631 }
3632 X86PDEPAE ZeroPde = {0};
3633 return ZeroPde;
3634}
3635
3636
3637/**
3638 * Gets the page directory pointer table entry for the specified address
3639 * and returns the index into the page directory
3640 *
3641 * @returns Pointer to the page directory in question.
3642 * @returns NULL if the page directory is not present or on an invalid page.
3643 * @param pPGM Pointer to the PGM instance data.
3644 * @param GCPtr The address.
3645 * @param piPD Receives the index into the returned page directory
3646 * @param pPdpe Receives the page directory pointer entry. Optional.
3647 */
3648DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3649{
3650 AssertGCPtr32(GCPtr);
3651
3652#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3653 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3654 AssertReturn(pGuestPDPT, 0);
3655#else
3656 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3657#endif
3658 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3659 if (pPdpe)
3660 *pPdpe = pGuestPDPT->a[iPdPt];
3661 if (pGuestPDPT->a[iPdPt].n.u1Present)
3662 {
3663 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3664#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3665 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3666 {
3667 *piPD = iPD;
3668 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3669 }
3670#endif
3671
3672 /* cache is out-of-sync. */
3673 PX86PDPAE pPD;
3674 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3675 if (RT_SUCCESS(rc))
3676 {
3677 *piPD = iPD;
3678 return pPD;
3679 }
3680 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3681 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3682 }
3683 return NULL;
3684}
3685
3686#ifndef IN_RC
3687
3688/**
3689 * Gets the page map level-4 pointer for the guest.
3690 *
3691 * @returns Pointer to the PML4 page.
3692 * @param pPGM Pointer to the PGM instance data.
3693 */
3694DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3695{
3696#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3697 PX86PML4 pGuestPml4;
3698 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3699 AssertRCReturn(rc, NULL);
3700 return pGuestPml4;
3701#else
3702 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3703 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3704#endif
3705}
3706
3707
3708/**
3709 * Gets the pointer to a page map level-4 entry.
3710 *
3711 * @returns Pointer to the PML4 entry.
3712 * @param pPGM Pointer to the PGM instance data.
3713 * @param iPml4 The index.
3714 */
3715DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3716{
3717#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3718 PX86PML4 pGuestPml4;
3719 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3720 AssertRCReturn(rc, NULL);
3721 return &pGuestPml4->a[iPml4];
3722#else
3723 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3724 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3725#endif
3726}
3727
3728
3729/**
3730 * Gets a page map level-4 entry.
3731 *
3732 * @returns The PML4 entry.
3733 * @param pPGM Pointer to the PGM instance data.
3734 * @param iPml4 The index.
3735 */
3736DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3737{
3738#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3739 PX86PML4 pGuestPml4;
3740 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3741 if (RT_FAILURE(rc))
3742 {
3743 X86PML4E ZeroPml4e = {0};
3744 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3745 }
3746 return pGuestPml4->a[iPml4];
3747#else
3748 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3749 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3750#endif
3751}
3752
3753
3754/**
3755 * Gets the page directory pointer entry for the specified address.
3756 *
3757 * @returns Pointer to the page directory pointer entry in question.
3758 * @returns NULL if the page directory is not present or on an invalid page.
3759 * @param pPGM Pointer to the PGM instance data.
3760 * @param GCPtr The address.
3761 * @param ppPml4e Page Map Level-4 Entry (out)
3762 */
3763DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3764{
3765 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3766 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3767 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3768 if (pPml4e->n.u1Present)
3769 {
3770 PX86PDPT pPdpt;
3771 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3772 AssertRCReturn(rc, NULL);
3773
3774 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3775 return &pPdpt->a[iPdPt];
3776 }
3777 return NULL;
3778}
3779
3780
3781/**
3782 * Gets the page directory entry for the specified address.
3783 *
3784 * @returns The page directory entry in question.
3785 * @returns A non-present entry if the page directory is not present or on an invalid page.
3786 * @param pPGM Pointer to the PGM instance data.
3787 * @param GCPtr The address.
3788 * @param ppPml4e Page Map Level-4 Entry (out)
3789 * @param pPdpe Page directory pointer table entry (out)
3790 */
3791DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3792{
3793 X86PDEPAE ZeroPde = {0};
3794 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3795 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3796 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3797 if (pPml4e->n.u1Present)
3798 {
3799 PCX86PDPT pPdptTemp;
3800 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3801 AssertRCReturn(rc, ZeroPde);
3802
3803 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3804 *pPdpe = pPdptTemp->a[iPdPt];
3805 if (pPdptTemp->a[iPdPt].n.u1Present)
3806 {
3807 PCX86PDPAE pPD;
3808 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3809 AssertRCReturn(rc, ZeroPde);
3810
3811 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3812 return pPD->a[iPD];
3813 }
3814 }
3815
3816 return ZeroPde;
3817}
3818
3819
3820/**
3821 * Gets the page directory entry for the specified address.
3822 *
3823 * @returns The page directory entry in question.
3824 * @returns A non-present entry if the page directory is not present or on an invalid page.
3825 * @param pPGM Pointer to the PGM instance data.
3826 * @param GCPtr The address.
3827 */
3828DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
3829{
3830 X86PDEPAE ZeroPde = {0};
3831 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3832 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3833 if (pGuestPml4->a[iPml4].n.u1Present)
3834 {
3835 PCX86PDPT pPdptTemp;
3836 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3837 AssertRCReturn(rc, ZeroPde);
3838
3839 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3840 if (pPdptTemp->a[iPdPt].n.u1Present)
3841 {
3842 PCX86PDPAE pPD;
3843 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3844 AssertRCReturn(rc, ZeroPde);
3845
3846 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3847 return pPD->a[iPD];
3848 }
3849 }
3850 return ZeroPde;
3851}
3852
3853
3854/**
3855 * Gets the page directory entry for the specified address.
3856 *
3857 * @returns Pointer to the page directory entry in question.
3858 * @returns NULL if the page directory is not present or on an invalid page.
3859 * @param pPGM Pointer to the PGM instance data.
3860 * @param GCPtr The address.
3861 */
3862DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
3863{
3864 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3865 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3866 if (pGuestPml4->a[iPml4].n.u1Present)
3867 {
3868 PCX86PDPT pPdptTemp;
3869 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3870 AssertRCReturn(rc, NULL);
3871
3872 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3873 if (pPdptTemp->a[iPdPt].n.u1Present)
3874 {
3875 PX86PDPAE pPD;
3876 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3877 AssertRCReturn(rc, NULL);
3878
3879 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3880 return &pPD->a[iPD];
3881 }
3882 }
3883 return NULL;
3884}
3885
3886
3887/**
3888 * Gets the GUEST page directory pointer for the specified address.
3889 *
3890 * @returns The page directory in question.
3891 * @returns NULL if the page directory is not present or on an invalid page.
3892 * @param pPGM Pointer to the PGM instance data.
3893 * @param GCPtr The address.
3894 * @param ppPml4e Page Map Level-4 Entry (out)
3895 * @param pPdpe Page directory pointer table entry (out)
3896 * @param piPD Receives the index into the returned page directory
3897 */
3898DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3899{
3900 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3901 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3902 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3903 if (pPml4e->n.u1Present)
3904 {
3905 PCX86PDPT pPdptTemp;
3906 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3907 AssertRCReturn(rc, NULL);
3908
3909 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3910 *pPdpe = pPdptTemp->a[iPdPt];
3911 if (pPdptTemp->a[iPdPt].n.u1Present)
3912 {
3913 PX86PDPAE pPD;
3914 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3915 AssertRCReturn(rc, NULL);
3916
3917 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3918 return pPD;
3919 }
3920 }
3921 return 0;
3922}
3923
3924#endif /* !IN_RC */
3925
3926
3927/**
3928 * Gets the shadow page directory, 32-bit.
3929 *
3930 * @returns Pointer to the shadow 32-bit PD.
3931 * @param pPGM Pointer to the PGM instance data.
3932 */
3933DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
3934{
3935#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3936 return (PX86PD)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
3937#else
3938# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3939 PX86PD pShwPd;
3940 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
3941 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShw32BitPD, &pShwPd);
3942 AssertRCReturn(rc, NULL);
3943 return pShwPd;
3944# else
3945 return pPGM->CTX_SUFF(pShw32BitPd);
3946# endif
3947#endif
3948}
3949
3950
3951/**
3952 * Gets the shadow page directory entry for the specified address, 32-bit.
3953 *
3954 * @returns Shadow 32-bit PDE.
3955 * @param pPGM Pointer to the PGM instance data.
3956 * @param GCPtr The address.
3957 */
3958DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
3959{
3960 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
3961
3962 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
3963 if (!pShwPde)
3964 {
3965 X86PDE ZeroPde = {0};
3966 return ZeroPde;
3967 }
3968 return pShwPde->a[iPd];
3969}
3970
3971
3972/**
3973 * Gets the pointer to the shadow page directory entry for the specified
3974 * address, 32-bit.
3975 *
3976 * @returns Pointer to the shadow 32-bit PDE.
3977 * @param pPGM Pointer to the PGM instance data.
3978 * @param GCPtr The address.
3979 */
3980DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3981{
3982 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
3983
3984 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
3985 AssertReturn(pPde, NULL);
3986 return &pPde->a[iPd];
3987}
3988
3989
3990/**
3991 * Gets the shadow page pointer table, PAE.
3992 *
3993 * @returns Pointer to the shadow PAE PDPT.
3994 * @param pPGM Pointer to the PGM instance data.
3995 */
3996DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
3997{
3998#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3999 return (PX86PDPT)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4000#else
4001# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4002 PX86PDPT pShwPdpt;
4003 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4004 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4005 AssertRCReturn(rc, 0);
4006 return pShwPdpt;
4007# else
4008 return pPGM->CTX_SUFF(pShwPaePdpt);
4009# endif
4010#endif
4011}
4012
4013
4014/**
4015 * Gets the shadow page directory for the specified address, PAE.
4016 *
4017 * @returns Pointer to the shadow PD.
4018 * @param pPGM Pointer to the PGM instance data.
4019 * @param GCPtr The address.
4020 */
4021DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4022{
4023#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4024 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4025 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4026
4027 /* Fetch the pgm pool shadow descriptor. */
4028 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4029 AssertReturn(pShwPde, NULL);
4030
4031 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pShwPde);
4032#else
4033 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4034# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4035 PX86PDPAE pPD;
4036 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4037 AssertRCReturn(rc, 0);
4038 return pPD;
4039# else
4040 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4041 Assert(pPD);
4042 return pPD;
4043# endif
4044#endif
4045}
4046
4047
4048/**
4049 * Gets the shadow page directory entry, PAE.
4050 *
4051 * @returns PDE.
4052 * @param pPGM Pointer to the PGM instance data.
4053 * @param GCPtr The address.
4054 */
4055DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4056{
4057 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4058
4059 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4060 if (!pShwPde)
4061 {
4062 X86PDEPAE ZeroPde = {0};
4063 return ZeroPde;
4064 }
4065 return pShwPde->a[iPd];
4066}
4067
4068
4069/**
4070 * Gets the pointer to the shadow page directory entry for an address, PAE.
4071 *
4072 * @returns Pointer to the PDE.
4073 * @param pPGM Pointer to the PGM instance data.
4074 * @param GCPtr The address.
4075 */
4076DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4077{
4078 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4079
4080 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4081 AssertReturn(pPde, NULL);
4082 return &pPde->a[iPd];
4083}
4084
4085#ifndef IN_RC
4086
4087/**
4088 * Gets the shadow page map level-4 pointer.
4089 *
4090 * @returns Pointer to the shadow PML4.
4091 * @param pPGM Pointer to the PGM instance data.
4092 */
4093DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4094{
4095#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4096 return (PX86PML4)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4097#else
4098# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4099 PX86PML4 pShwPml4;
4100 Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
4101 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShwPaePml4, &pShwPml4);
4102 AssertRCReturn(rc, 0);
4103 return pShwPml4;
4104# else
4105 Assert(pPGM->CTX_SUFF(pShwPaePml4));
4106 return pPGM->CTX_SUFF(pShwPaePml4);
4107# endif
4108#endif
4109}
4110
4111
4112/**
4113 * Gets the shadow page map level-4 entry for the specified address.
4114 *
4115 * @returns The entry.
4116 * @param pPGM Pointer to the PGM instance data.
4117 * @param GCPtr The address.
4118 */
4119DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4120{
4121 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4122 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4123
4124 if (!pShwPml4)
4125 {
4126 X86PML4E ZeroPml4e = {0};
4127 return ZeroPml4e;
4128 }
4129 return pShwPml4->a[iPml4];
4130}
4131
4132
4133/**
4134 * Gets the pointer to the specified shadow page map level-4 entry.
4135 *
4136 * @returns The entry.
4137 * @param pPGM Pointer to the PGM instance data.
4138 * @param iPml4 The PML4 index.
4139 */
4140DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4141{
4142 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4143
4144 if (!pShwPml4)
4145 return NULL;
4146
4147 return &pShwPml4->a[iPml4];
4148}
4149
4150
4151/**
4152 * Gets the GUEST page directory pointer for the specified address.
4153 *
4154 * @returns The page directory in question.
4155 * @returns NULL if the page directory is not present or on an invalid page.
4156 * @param pPGM Pointer to the PGM instance data.
4157 * @param GCPtr The address.
4158 * @param piPD Receives the index into the returned page directory
4159 */
4160DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4161{
4162 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4163 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4164 if (pGuestPml4->a[iPml4].n.u1Present)
4165 {
4166 PCX86PDPT pPdptTemp;
4167 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4168 AssertRCReturn(rc, NULL);
4169
4170 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4171 if (pPdptTemp->a[iPdPt].n.u1Present)
4172 {
4173 PX86PDPAE pPD;
4174 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4175 AssertRCReturn(rc, NULL);
4176
4177 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4178 return pPD;
4179 }
4180 }
4181 return NULL;
4182}
4183
4184#endif /* !IN_RC */
4185
4186/**
4187 * Checks if any of the specified page flags are set for the given page.
4188 *
4189 * @returns true if any of the flags are set.
4190 * @returns false if all the flags are clear.
4191 * @param pPGM PGM handle.
4192 * @param GCPhys The GC physical address.
4193 * @param fFlags The flags to check for.
4194 */
4195DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4196{
4197 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4198 return pPage
4199 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4200}
4201
4202
4203/**
4204 * Gets the page state for a physical handler.
4205 *
4206 * @returns The physical handler page state.
4207 * @param pCur The physical handler in question.
4208 */
4209DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4210{
4211 switch (pCur->enmType)
4212 {
4213 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4214 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4215
4216 case PGMPHYSHANDLERTYPE_MMIO:
4217 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4218 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4219
4220 default:
4221 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4222 }
4223}
4224
4225
4226/**
4227 * Gets the page state for a virtual handler.
4228 *
4229 * @returns The virtual handler page state.
4230 * @param pCur The virtual handler in question.
4231 * @remarks This should never be used on a hypervisor access handler.
4232 */
4233DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4234{
4235 switch (pCur->enmType)
4236 {
4237 case PGMVIRTHANDLERTYPE_WRITE:
4238 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4239 case PGMVIRTHANDLERTYPE_ALL:
4240 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4241 default:
4242 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4243 }
4244}
4245
4246
4247/**
4248 * Clears one physical page of a virtual handler
4249 *
4250 * @param pPGM Pointer to the PGM instance.
4251 * @param pCur Virtual handler structure
4252 * @param iPage Physical page index
4253 *
4254 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4255 * need to care about other handlers in the same page.
4256 */
4257DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4258{
4259 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4260
4261 /*
4262 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4263 */
4264#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4265 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4266 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4267 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4268#endif
4269 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4270 {
4271 /* We're the head of the alias chain. */
4272 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4273#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4274 AssertReleaseMsg(pRemove != NULL,
4275 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4276 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4277 AssertReleaseMsg(pRemove == pPhys2Virt,
4278 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4279 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4280 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4281 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4282#endif
4283 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4284 {
4285 /* Insert the next list in the alias chain into the tree. */
4286 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4287#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4288 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4289 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4290 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4291#endif
4292 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4293 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4294 AssertRelease(fRc);
4295 }
4296 }
4297 else
4298 {
4299 /* Locate the previous node in the alias chain. */
4300 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4301#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4302 AssertReleaseMsg(pPrev != pPhys2Virt,
4303 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4304 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4305#endif
4306 for (;;)
4307 {
4308 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4309 if (pNext == pPhys2Virt)
4310 {
4311 /* unlink. */
4312 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4313 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4314 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4315 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4316 else
4317 {
4318 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4319 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4320 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4321 }
4322 break;
4323 }
4324
4325 /* next */
4326 if (pNext == pPrev)
4327 {
4328#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4329 AssertReleaseMsg(pNext != pPrev,
4330 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4331 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4332#endif
4333 break;
4334 }
4335 pPrev = pNext;
4336 }
4337 }
4338 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4339 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4340 pPhys2Virt->offNextAlias = 0;
4341 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4342
4343 /*
4344 * Clear the ram flags for this page.
4345 */
4346 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4347 AssertReturnVoid(pPage);
4348 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4349}
4350
4351
4352/**
4353 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4354 *
4355 * @returns Pointer to the shadow page structure.
4356 * @param pPool The pool.
4357 * @param HCPhys The HC physical address of the shadow page.
4358 */
4359DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4360{
4361 /*
4362 * Look up the page.
4363 */
4364 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4365 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
4366 return pPage;
4367}
4368
4369
4370/**
4371 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4372 *
4373 * @returns Pointer to the shadow page structure.
4374 * @param pPool The pool.
4375 * @param idx The pool page index.
4376 */
4377DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4378{
4379 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4380 return &pPool->aPages[idx];
4381}
4382
4383
4384#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4385/**
4386 * Clear references to guest physical memory.
4387 *
4388 * @param pPool The pool.
4389 * @param pPoolPage The pool page.
4390 * @param pPhysPage The physical guest page tracking structure.
4391 */
4392DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4393{
4394 /*
4395 * Just deal with the simple case here.
4396 */
4397# ifdef LOG_ENABLED
4398 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4399# endif
4400 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4401 if (cRefs == 1)
4402 {
4403 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4404 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4405 }
4406 else
4407 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4408 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4409}
4410#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4411
4412
4413#ifdef PGMPOOL_WITH_CACHE
4414/**
4415 * Moves the page to the head of the age list.
4416 *
4417 * This is done when the cached page is used in one way or another.
4418 *
4419 * @param pPool The pool.
4420 * @param pPage The cached page.
4421 * @todo inline in PGMInternal.h!
4422 */
4423DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4424{
4425 /*
4426 * Move to the head of the age list.
4427 */
4428 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4429 {
4430 /* unlink */
4431 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4432 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4433 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4434 else
4435 pPool->iAgeTail = pPage->iAgePrev;
4436
4437 /* insert at head */
4438 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4439 pPage->iAgeNext = pPool->iAgeHead;
4440 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4441 pPool->iAgeHead = pPage->idx;
4442 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4443 }
4444}
4445#endif /* PGMPOOL_WITH_CACHE */
4446
4447/**
4448 * Tells if mappings are to be put into the shadow page table or not
4449 *
4450 * @returns boolean result
4451 * @param pVM VM handle.
4452 */
4453
4454DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4455{
4456#ifdef IN_RING0
4457 /* There are no mappings in VT-x and AMD-V mode. */
4458 Assert(pPGM->fDisableMappings);
4459 return false;
4460#else
4461 return !pPGM->fDisableMappings;
4462#endif
4463}
4464
4465/** @} */
4466
4467#endif
4468
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