PGMInternal.h@ 16840

Last change on this file since 16840 was 16840, checked in by vboxsync, 16 years ago
VBOX_WITH_PGMPOOL_PAGING_ONLY: updates for raw mode
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1	/* $Id: PGMInternal.h 16840 2009-02-17 13:26:14Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/*
57	* Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58	*/
59	//#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61	/**
62	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63	* Comment it if it will break something.
64	*/
65	#define PGM_OUT_OF_SYNC_IN_GC
66
67	/**
68	* Check and skip global PDEs for non-global flushes
69	*/
70	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72	/**
73	* Sync N pages instead of a whole page table
74	*/
75	#define PGM_SYNC_N_PAGES
76
77	/**
78	* Number of pages to sync during a page fault
79	*
80	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82	*/
83	#define PGM_SYNC_NR_PAGES 8
84
85	/**
86	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87	*/
88	#define PGM_MAX_PHYSCACHE_ENTRIES 64
89	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91	/**
92	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93	*/
94	#define PGM_PHYSMEMACCESS_CACHING
95
96	/** @def PGMPOOL_WITH_CACHE
97	* Enable agressive caching using the page pool.
98	*
99	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100	*/
101	#define PGMPOOL_WITH_CACHE
102
103	/** @def PGMPOOL_WITH_MIXED_PT_CR3
104	* When defined, we'll deal with 'uncachable' pages.
105	*/
106	#ifdef PGMPOOL_WITH_CACHE
107	# define PGMPOOL_WITH_MIXED_PT_CR3
108	#endif
109
110	/** @def PGMPOOL_WITH_MONITORING
111	* Monitor the guest pages which are shadowed.
112	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113	* be enabled as well.
114	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115	*/
116	#ifdef PGMPOOL_WITH_CACHE
117	# define PGMPOOL_WITH_MONITORING
118	#endif
119
120	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121	* Tracking the of shadow pages mapping guest physical pages.
122	*
123	* This is very expensive, the current cache prototype is trying to figure out
124	* whether it will be acceptable with an agressive caching policy.
125	*/
126	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
127	# define PGMPOOL_WITH_GCPHYS_TRACKING
128	#endif
129
130	/** @def PGMPOOL_WITH_USER_TRACKING
131	* Tracking users of shadow pages. This is required for the linking of shadow page
132	* tables and physical guest addresses.
133	*/
134	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
135	# define PGMPOOL_WITH_USER_TRACKING
136	#endif
137
138	/** @def PGMPOOL_CFG_MAX_GROW
139	* The maximum number of pages to add to the pool in one go.
140	*/
141	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
145	*/
146	#ifdef VBOX_STRICT
147	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148	#endif
149	/** @} */
150
151
152	/** @name PDPT and PML4 flags.
153	* These are placed in the three bits available for system programs in
154	* the PDPT and PML4 entries.
155	* @{ */
156	/** The entry is a permanent one and it's must always be present.
157	* Never free such an entry. */
158	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159	/** Mapping (hypervisor allocated pagetable). */
160	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161	/** @} */
162
163	/** @name Page directory flags.
164	* These are placed in the three bits available for system programs in
165	* the page directory entries.
166	* @{ */
167	/** Mapping (hypervisor allocated pagetable). */
168	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169	/** Made read-only to facilitate dirty bit tracking. */
170	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171	/** @} */
172
173	/** @name Page flags.
174	* These are placed in the three bits available for system programs in
175	* the page entries.
176	* @{ */
177	/** Made read-only to facilitate dirty bit tracking. */
178	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181	/** Scanned and approved by CSAM (tm).
182	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
183	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185	#endif
186	/** @} */
187
188	/** @name Defines used to indicate the shadow and guest paging in the templates.
189	* @{ */
190	#define PGM_TYPE_REAL 1
191	#define PGM_TYPE_PROT 2
192	#define PGM_TYPE_32BIT 3
193	#define PGM_TYPE_PAE 4
194	#define PGM_TYPE_AMD64 5
195	#define PGM_TYPE_NESTED 6
196	#define PGM_TYPE_EPT 7
197	#define PGM_TYPE_MAX PGM_TYPE_EPT
198	/** @} */
199
200	/** Macro for checking if the guest is using paging.
201	* @param uGstType PGM_TYPE_*
202	* @param uShwType PGM_TYPE_*
203	* @remark ASSUMES certain order of the PGM_TYPE_* values.
204	*/
205	#define PGM_WITH_PAGING(uGstType, uShwType) \
206	( (uGstType) >= PGM_TYPE_32BIT \
207	&& (uShwType) != PGM_TYPE_NESTED \
208	&& (uShwType) != PGM_TYPE_EPT)
209
210	/** Macro for checking if the guest supports the NX bit.
211	* @param uGstType PGM_TYPE_*
212	* @param uShwType PGM_TYPE_*
213	* @remark ASSUMES certain order of the PGM_TYPE_* values.
214	*/
215	#define PGM_WITH_NX(uGstType, uShwType) \
216	( (uGstType) >= PGM_TYPE_PAE \
217	&& (uShwType) != PGM_TYPE_NESTED \
218	&& (uShwType) != PGM_TYPE_EPT)
219
220
221	/** @def PGM_HCPHYS_2_PTR
222	* Maps a HC physical page pool address to a virtual address.
223	*
224	* @returns VBox status code.
225	* @param pVM The VM handle.
226	* @param HCPhys The HC physical address to map to a virtual one.
227	* @param ppv Where to store the virtual address. No need to cast this.
228	*
229	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
230	* small page window employeed by that function. Be careful.
231	* @remark There is no need to assert on the result.
232	*/
233	#ifdef IN_RC
234	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
236	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
237	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
239	#else
240	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
241	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
242	#endif
243
244	/** @def PGM_HCPHYS_2_PTR_BY_PGM
245	* Maps a HC physical page pool address to a virtual address.
246	*
247	* @returns VBox status code.
248	* @param pPGM The PGM instance data.
249	* @param HCPhys The HC physical address to map to a virtual one.
250	* @param ppv Where to store the virtual address. No need to cast this.
251	*
252	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
253	* small page window employeed by that function. Be careful.
254	* @remark There is no need to assert on the result.
255	*/
256	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
257	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
259	#else
260	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
261	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
262	#endif
263
264	/** @def PGM_GCPHYS_2_PTR
265	* Maps a GC physical page address to a virtual address.
266	*
267	* @returns VBox status code.
268	* @param pVM The VM handle.
269	* @param GCPhys The GC physical address to map to a virtual one.
270	* @param ppv Where to store the virtual address. No need to cast this.
271	*
272	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
273	* small page window employeed by that function. Be careful.
274	* @remark There is no need to assert on the result.
275	*/
276	#ifdef IN_RC
277	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
279	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
280	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
282	#else
283	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
284	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
285	#endif
286
287	/** @def PGM_GCPHYS_2_PTR_BY_PGM
288	* Maps a GC physical page address to a virtual address.
289	*
290	* @returns VBox status code.
291	* @param pPGM Pointer to the PGM instance data.
292	* @param GCPhys The GC physical address to map to a virtual one.
293	* @param ppv Where to store the virtual address. No need to cast this.
294	*
295	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
296	* small page window employeed by that function. Be careful.
297	* @remark There is no need to assert on the result.
298	*/
299	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
300	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
301	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
302	#else
303	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
304	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
305	#endif
306
307	/** @def PGM_GCPHYS_2_PTR_EX
308	* Maps a unaligned GC physical page address to a virtual address.
309	*
310	* @returns VBox status code.
311	* @param pVM The VM handle.
312	* @param GCPhys The GC physical address to map to a virtual one.
313	* @param ppv Where to store the virtual address. No need to cast this.
314	*
315	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
316	* small page window employeed by that function. Be careful.
317	* @remark There is no need to assert on the result.
318	*/
319	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
320	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
322	#else
323	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
324	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
325	#endif
326
327	/** @def PGM_INVL_PG
328	* Invalidates a page when in GC does nothing in HC.
329	*
330	* @param GCVirt The virtual address of the page to invalidate.
331	*/
332	#ifdef IN_RC
333	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
334	#elif defined(IN_RING0)
335	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
336	#else
337	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
338	#endif
339
340	/** @def PGM_INVL_BIG_PG
341	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
342	*
343	* @param GCVirt The virtual address within the page directory to invalidate.
344	*/
345	#ifdef IN_RC
346	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
347	#elif defined(IN_RING0)
348	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
349	#else
350	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
351	#endif
352
353	/** @def PGM_INVL_GUEST_TLBS()
354	* Invalidates all guest TLBs.
355	*/
356	#ifdef IN_RC
357	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
358	#elif defined(IN_RING0)
359	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
360	#else
361	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
362	#endif
363
364
365	/**
366	* Structure for tracking GC Mappings.
367	*
368	* This structure is used by linked list in both GC and HC.
369	*/
370	typedef struct PGMMAPPING
371	{
372	/** Pointer to next entry. */
373	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
374	/** Pointer to next entry. */
375	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
376	/** Pointer to next entry. */
377	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
378	/** Indicate whether this entry is finalized. */
379	bool fFinalized;
380	/** Start Virtual address. */
381	RTGCPTR GCPtr;
382	/** Last Virtual address (inclusive). */
383	RTGCPTR GCPtrLast;
384	/** Range size (bytes). */
385	RTGCPTR cb;
386	/** Pointer to relocation callback function. */
387	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
388	/** User argument to the callback. */
389	R3PTRTYPE(void *) pvUser;
390	/** Mapping description / name. For easing debugging. */
391	R3PTRTYPE(const char *) pszDesc;
392	/** Number of page tables. */
393	uint32_t cPTs;
394	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
395	uint32_t uPadding1; /*< Alignment padding. /
396	#endif
397	/** Array of page table mapping data. Each entry
398	* describes one page table. The array can be longer
399	* than the declared length.
400	*/
401	struct
402	{
403	/** The HC physical address of the page table. */
404	RTHCPHYS HCPhysPT;
405	/** The HC physical address of the first PAE page table. */
406	RTHCPHYS HCPhysPaePT0;
407	/** The HC physical address of the second PAE page table. */
408	RTHCPHYS HCPhysPaePT1;
409	/** The HC virtual address of the 32-bit page table. */
410	R3PTRTYPE(PX86PT) pPTR3;
411	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
412	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
413	/** The GC virtual address of the 32-bit page table. */
414	RCPTRTYPE(PX86PT) pPTRC;
415	/** The GC virtual address of the two PAE page table. */
416	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
417	/** The GC virtual address of the 32-bit page table. */
418	R0PTRTYPE(PX86PT) pPTR0;
419	/** The GC virtual address of the two PAE page table. */
420	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
421	} aPTs[1];
422	} PGMMAPPING;
423	/** Pointer to structure for tracking GC Mappings. */
424	typedef struct PGMMAPPING *PPGMMAPPING;
425
426
427	/**
428	* Physical page access handler structure.
429	*
430	* This is used to keep track of physical address ranges
431	* which are being monitored in some kind of way.
432	*/
433	typedef struct PGMPHYSHANDLER
434	{
435	AVLROGCPHYSNODECORE Core;
436	/** Access type. */
437	PGMPHYSHANDLERTYPE enmType;
438	/** Number of pages to update. */
439	uint32_t cPages;
440	/** Pointer to R3 callback function. */
441	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
442	/** User argument for R3 handlers. */
443	R3PTRTYPE(void *) pvUserR3;
444	/** Pointer to R0 callback function. */
445	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
446	/** User argument for R0 handlers. */
447	R0PTRTYPE(void *) pvUserR0;
448	/** Pointer to GC callback function. */
449	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
450	/** User argument for RC handlers. */
451	RCPTRTYPE(void *) pvUserRC;
452	/** Description / Name. For easing debugging. */
453	R3PTRTYPE(const char *) pszDesc;
454	#ifdef VBOX_WITH_STATISTICS
455	/** Profiling of this handler. */
456	STAMPROFILE Stat;
457	#endif
458	} PGMPHYSHANDLER;
459	/** Pointer to a physical page access handler structure. */
460	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
461
462
463	/**
464	* Cache node for the physical addresses covered by a virtual handler.
465	*/
466	typedef struct PGMPHYS2VIRTHANDLER
467	{
468	/** Core node for the tree based on physical ranges. */
469	AVLROGCPHYSNODECORE Core;
470	/** Offset from this struct to the PGMVIRTHANDLER structure. */
471	int32_t offVirtHandler;
472	/** Offset of the next alias relative to this one.
473	* Bit 0 is used for indicating whether we're in the tree.
474	* Bit 1 is used for indicating that we're the head node.
475	*/
476	int32_t offNextAlias;
477	} PGMPHYS2VIRTHANDLER;
478	/** Pointer to a phys to virtual handler structure. */
479	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
480
481	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
482	* node is in the tree. */
483	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
484	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
485	* node is in the head of an alias chain.
486	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
487	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
488	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
489	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
490
491
492	/**
493	* Virtual page access handler structure.
494	*
495	* This is used to keep track of virtual address ranges
496	* which are being monitored in some kind of way.
497	*/
498	typedef struct PGMVIRTHANDLER
499	{
500	/** Core node for the tree based on virtual ranges. */
501	AVLROGCPTRNODECORE Core;
502	/** Size of the range (in bytes). */
503	RTGCPTR cb;
504	/** Number of cache pages. */
505	uint32_t cPages;
506	/** Access type. */
507	PGMVIRTHANDLERTYPE enmType;
508	/** Pointer to the RC callback function. */
509	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
510	#if HC_ARCH_BITS == 64
511	RTRCPTR padding;
512	#endif
513	/** Pointer to the R3 callback function for invalidation. */
514	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
515	/** Pointer to the R3 callback function. */
516	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
517	/** Description / Name. For easing debugging. */
518	R3PTRTYPE(const char *) pszDesc;
519	#ifdef VBOX_WITH_STATISTICS
520	/** Profiling of this handler. */
521	STAMPROFILE Stat;
522	#endif
523	/** Array of cached physical addresses for the monitored ranged. */
524	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
525	} PGMVIRTHANDLER;
526	/** Pointer to a virtual page access handler structure. */
527	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
528
529
530	/**
531	* Page type.
532	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
533	* @todo convert to \#defines.
534	*/
535	typedef enum PGMPAGETYPE
536	{
537	/** The usual invalid zero entry. */
538	PGMPAGETYPE_INVALID = 0,
539	/** RAM page. (RWX) */
540	PGMPAGETYPE_RAM,
541	/** MMIO2 page. (RWX) */
542	PGMPAGETYPE_MMIO2,
543	/** Shadowed ROM. (RWX) */
544	PGMPAGETYPE_ROM_SHADOW,
545	/** ROM page. (R-X) */
546	PGMPAGETYPE_ROM,
547	/** MMIO page. (---) */
548	PGMPAGETYPE_MMIO,
549	/** End of valid entries. */
550	PGMPAGETYPE_END
551	} PGMPAGETYPE;
552	AssertCompile(PGMPAGETYPE_END < 7);
553
554	/** @name Page type predicates.
555	* @{ */
556	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
557	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
558	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
559	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
560	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
561	/** @} */
562
563
564	/**
565	* A Physical Guest Page tracking structure.
566	*
567	* The format of this structure is complicated because we have to fit a lot
568	* of information into as few bits as possible. The format is also subject
569	* to change (there is one comming up soon). Which means that for we'll be
570	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
571	* accessess to the structure.
572	*/
573	typedef struct PGMPAGE
574	{
575	/** The physical address and a whole lot of other stuff. All bits are used! */
576	RTHCPHYS HCPhys;
577	/** The page state. */
578	uint32_t u2StateX : 2;
579	/** Flag indicating that a write monitored page was written to when set. */
580	uint32_t fWrittenToX : 1;
581	/** For later. */
582	uint32_t fSomethingElse : 1;
583	/** The Page ID.
584	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
585	* The HCPhys will be 100% static. */
586	uint32_t idPageX : 28;
587	/** The page type (PGMPAGETYPE). */
588	uint32_t u3Type : 3;
589	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
590	uint32_t u2HandlerPhysStateX : 2;
591	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
592	uint32_t u2HandlerVirtStateX : 2;
593	uint32_t u29B : 25;
594	} PGMPAGE;
595	AssertCompileSize(PGMPAGE, 16);
596	/** Pointer to a physical guest page. */
597	typedef PGMPAGE *PPGMPAGE;
598	/** Pointer to a const physical guest page. */
599	typedef const PGMPAGE *PCPGMPAGE;
600	/** Pointer to a physical guest page pointer. */
601	typedef PPGMPAGE *PPPGMPAGE;
602
603
604	/**
605	* Clears the page structure.
606	* @param pPage Pointer to the physical guest page tracking structure.
607	*/
608	#define PGM_PAGE_CLEAR(pPage) \
609	do { \
610	(pPage)->HCPhys = 0; \
611	(pPage)->u2StateX = 0; \
612	(pPage)->fWrittenToX = 0; \
613	(pPage)->fSomethingElse = 0; \
614	(pPage)->idPageX = 0; \
615	(pPage)->u3Type = 0; \
616	(pPage)->u29B = 0; \
617	} while (0)
618
619	/**
620	* Initializes the page structure.
621	* @param pPage Pointer to the physical guest page tracking structure.
622	*/
623	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
624	do { \
625	(pPage)->HCPhys = (_HCPhys); \
626	(pPage)->u2StateX = (_uState); \
627	(pPage)->fWrittenToX = 0; \
628	(pPage)->fSomethingElse = 0; \
629	(pPage)->idPageX = (_idPage); \
630	/(pPage)->u3Type = (_uType); - later / \
631	PGM_PAGE_SET_TYPE(pPage, _uType); \
632	(pPage)->u29B = 0; \
633	} while (0)
634
635	/**
636	* Initializes the page structure of a ZERO page.
637	* @param pPage Pointer to the physical guest page tracking structure.
638	*/
639	#ifdef VBOX_WITH_NEW_PHYS_CODE
640	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
641	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
642	#else
643	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
644	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645	#endif
646	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
647	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
648	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649
650
651	/** @name The Page state, PGMPAGE::u2StateX.
652	* @{ */
653	/** The zero page.
654	* This is a per-VM page that's never ever mapped writable. */
655	#define PGM_PAGE_STATE_ZERO 0
656	/** A allocated page.
657	* This is a per-VM page allocated from the page pool (or wherever
658	* we get MMIO2 pages from if the type is MMIO2).
659	*/
660	#define PGM_PAGE_STATE_ALLOCATED 1
661	/** A allocated page that's being monitored for writes.
662	* The shadow page table mappings are read-only. When a write occurs, the
663	* fWrittenTo member is set, the page remapped as read-write and the state
664	* moved back to allocated. */
665	#define PGM_PAGE_STATE_WRITE_MONITORED 2
666	/** The page is shared, aka. copy-on-write.
667	* This is a page that's shared with other VMs. */
668	#define PGM_PAGE_STATE_SHARED 3
669	/** @} */
670
671
672	/**
673	* Gets the page state.
674	* @returns page state (PGM_PAGE_STATE_*).
675	* @param pPage Pointer to the physical guest page tracking structure.
676	*/
677	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
678
679	/**
680	* Sets the page state.
681	* @param pPage Pointer to the physical guest page tracking structure.
682	* @param _uState The new page state.
683	*/
684	#define PGM_PAGE_SET_STATE(pPage, _uState) \
685	do { (pPage)->u2StateX = (_uState); } while (0)
686
687
688	/**
689	* Gets the host physical address of the guest page.
690	* @returns host physical address (RTHCPHYS).
691	* @param pPage Pointer to the physical guest page tracking structure.
692	*/
693	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
694
695	/**
696	* Sets the host physical address of the guest page.
697	* @param pPage Pointer to the physical guest page tracking structure.
698	* @param _HCPhys The new host physical address.
699	*/
700	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
701	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
702	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
703
704	/**
705	* Get the Page ID.
706	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
707	* @param pPage Pointer to the physical guest page tracking structure.
708	*/
709	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
710	/* later:
711	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
712	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
713	*/
714	/**
715	* Sets the Page ID.
716	* @param pPage Pointer to the physical guest page tracking structure.
717	*/
718	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
719	/* later:
720	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
721	\| ((_idPage) & 0xfff) \
722	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
723	*/
724
725	/**
726	* Get the Chunk ID.
727	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
728	* @param pPage Pointer to the physical guest page tracking structure.
729	*/
730	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
731	/* later:
732	#if GMM_CHUNKID_SHIFT == 12
733	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
734	#elif GMM_CHUNKID_SHIFT > 12
735	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
736	#elif GMM_CHUNKID_SHIFT < 12
737	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
738	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
739	#else
740	# error "GMM_CHUNKID_SHIFT isn't defined or something."
741	#endif
742	*/
743
744	/**
745	* Get the index of the page within the allocaiton chunk.
746	* @returns The page index.
747	* @param pPage Pointer to the physical guest page tracking structure.
748	*/
749	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
750	/* later:
751	#if GMM_CHUNKID_SHIFT <= 12
752	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
753	#else
754	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
755	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
756	#endif
757	*/
758
759
760	/**
761	* Gets the page type.
762	* @returns The page type.
763	* @param pPage Pointer to the physical guest page tracking structure.
764	*/
765	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
766
767	/**
768	* Sets the page type.
769	* @param pPage Pointer to the physical guest page tracking structure.
770	* @param _enmType The new page type (PGMPAGETYPE).
771	*/
772	#ifdef VBOX_WITH_NEW_PHYS_CODE
773	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
774	do { (pPage)->u3Type = (_enmType); } while (0)
775	#else
776	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
777	do { \
778	(pPage)->u3Type = (_enmType); \
779	if ((_enmType) == PGMPAGETYPE_ROM) \
780	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
781	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
782	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
783	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
784	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
785	} while (0)
786	#endif
787
788
789	/**
790	* Checks if the page is 'reserved'.
791	* @returns true/false.
792	* @param pPage Pointer to the physical guest page tracking structure.
793	*/
794	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
795
796	/**
797	* Checks if the page is marked for MMIO.
798	* @returns true/false.
799	* @param pPage Pointer to the physical guest page tracking structure.
800	*/
801	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
802
803	/**
804	* Checks if the page is backed by the ZERO page.
805	* @returns true/false.
806	* @param pPage Pointer to the physical guest page tracking structure.
807	*/
808	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
809
810	/**
811	* Checks if the page is backed by a SHARED page.
812	* @returns true/false.
813	* @param pPage Pointer to the physical guest page tracking structure.
814	*/
815	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
816
817
818	/**
819	* Marks the paget as written to (for GMM change monitoring).
820	* @param pPage Pointer to the physical guest page tracking structure.
821	*/
822	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
823
824	/**
825	* Clears the written-to indicator.
826	* @param pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
829
830	/**
831	* Checks if the page was marked as written-to.
832	* @returns true/false.
833	* @param pPage Pointer to the physical guest page tracking structure.
834	*/
835	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
836
837
838	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
839	*
840	* @remarks The values are assigned in order of priority, so we can calculate
841	* the correct state for a page with different handlers installed.
842	* @{ */
843	/** No handler installed. */
844	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
845	/** Monitoring is temporarily disabled. */
846	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
847	/** Write access is monitored. */
848	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
849	/** All access is monitored. */
850	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
851	/** @} */
852
853	/**
854	* Gets the physical access handler state of a page.
855	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
856	* @param pPage Pointer to the physical guest page tracking structure.
857	*/
858	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
859
860	/**
861	* Sets the physical access handler state of a page.
862	* @param pPage Pointer to the physical guest page tracking structure.
863	* @param _uState The new state value.
864	*/
865	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
866	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
867
868	/**
869	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
870	* @returns true/false
871	* @param pPage Pointer to the physical guest page tracking structure.
872	*/
873	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
874
875	/**
876	* Checks if the page has any active physical access handlers.
877	* @returns true/false
878	* @param pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
881
882
883	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
884	*
885	* @remarks The values are assigned in order of priority, so we can calculate
886	* the correct state for a page with different handlers installed.
887	* @{ */
888	/** No handler installed. */
889	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
890	/* 1 is reserved so the lineup is identical with the physical ones. */
891	/** Write access is monitored. */
892	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
893	/** All access is monitored. */
894	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
895	/** @} */
896
897	/**
898	* Gets the virtual access handler state of a page.
899	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
900	* @param pPage Pointer to the physical guest page tracking structure.
901	*/
902	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
903
904	/**
905	* Sets the virtual access handler state of a page.
906	* @param pPage Pointer to the physical guest page tracking structure.
907	* @param _uState The new state value.
908	*/
909	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
910	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
911
912	/**
913	* Checks if the page has any virtual access handlers.
914	* @returns true/false
915	* @param pPage Pointer to the physical guest page tracking structure.
916	*/
917	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
918
919	/**
920	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
921	* virtual handlers.
922	* @returns true/false
923	* @param pPage Pointer to the physical guest page tracking structure.
924	*/
925	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
926
927
928
929	/**
930	* Checks if the page has any access handlers, including temporarily disabled ones.
931	* @returns true/false
932	* @param pPage Pointer to the physical guest page tracking structure.
933	*/
934	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
935	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
936	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
937
938	/**
939	* Checks if the page has any active access handlers.
940	* @returns true/false
941	* @param pPage Pointer to the physical guest page tracking structure.
942	*/
943	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
944	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
945	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
946
947	/**
948	* Checks if the page has any active access handlers catching all accesses.
949	* @returns true/false
950	* @param pPage Pointer to the physical guest page tracking structure.
951	*/
952	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
953	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
954	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
955
956
957	/**
958	* Ram range for GC Phys to HC Phys conversion.
959	*
960	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
961	* conversions too, but we'll let MM handle that for now.
962	*
963	* This structure is used by linked lists in both GC and HC.
964	*/
965	typedef struct PGMRAMRANGE
966	{
967	/** Pointer to the next RAM range - for R3. */
968	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
969	/** Pointer to the next RAM range - for R0. */
970	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
971	/** Pointer to the next RAM range - for RC. */
972	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
973	/** Pointer alignment. */
974	RTRCPTR RCPtrAlignment;
975	/** Start of the range. Page aligned. */
976	RTGCPHYS GCPhys;
977	/** Last address in the range (inclusive). Page aligned (-1). */
978	RTGCPHYS GCPhysLast;
979	/** Size of the range. (Page aligned of course). */
980	RTGCPHYS cb;
981	/** MM_RAM_* flags */
982	uint32_t fFlags;
983	uint32_t u32Alignment; /*< alignment. /
984	#ifndef VBOX_WITH_NEW_PHYS_CODE
985	/** R3 virtual lookup ranges for chunks.
986	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
987	* @remarks This is occationally accessed from ring-0!! (not darwin) */
988	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
989	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
990	# else
991	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
992	# endif
993	#endif
994	/** Start of the HC mapping of the range. This is only used for MMIO2. */
995	R3PTRTYPE(void *) pvR3;
996	/** The range description. */
997	R3PTRTYPE(const char *) pszDesc;
998
999	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1000	#ifdef VBOX_WITH_NEW_PHYS_CODE
1001	uint32_t au32Reserved[2];
1002	#elif HC_ARCH_BITS == 32
1003	uint32_t au32Reserved[1];
1004	#endif
1005
1006	/** Array of physical guest page tracking structures. */
1007	PGMPAGE aPages[1];
1008	} PGMRAMRANGE;
1009	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1010	typedef PGMRAMRANGE *PPGMRAMRANGE;
1011
1012	/** Return hc ptr corresponding to the ram range and physical offset */
1013	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1014	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1015	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1016
1017	/**
1018	* Per page tracking structure for ROM image.
1019	*
1020	* A ROM image may have a shadow page, in which case we may have
1021	* two pages backing it. This structure contains the PGMPAGE for
1022	* both while PGMRAMRANGE have a copy of the active one. It is
1023	* important that these aren't out of sync in any regard other
1024	* than page pool tracking data.
1025	*/
1026	typedef struct PGMROMPAGE
1027	{
1028	/** The page structure for the virgin ROM page. */
1029	PGMPAGE Virgin;
1030	/** The page structure for the shadow RAM page. */
1031	PGMPAGE Shadow;
1032	/** The current protection setting. */
1033	PGMROMPROT enmProt;
1034	/** Pad the structure size to a multiple of 8. */
1035	uint32_t u32Padding;
1036	} PGMROMPAGE;
1037	/** Pointer to a ROM page tracking structure. */
1038	typedef PGMROMPAGE *PPGMROMPAGE;
1039
1040
1041	/**
1042	* A registered ROM image.
1043	*
1044	* This is needed to keep track of ROM image since they generally
1045	* intrude into a PGMRAMRANGE. It also keeps track of additional
1046	* info like the two page sets (read-only virgin and read-write shadow),
1047	* the current state of each page.
1048	*
1049	* Because access handlers cannot easily be executed in a different
1050	* context, the ROM ranges needs to be accessible and in all contexts.
1051	*/
1052	typedef struct PGMROMRANGE
1053	{
1054	/** Pointer to the next range - R3. */
1055	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1056	/** Pointer to the next range - R0. */
1057	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1058	/** Pointer to the next range - RC. */
1059	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1060	/** Pointer alignment */
1061	RTRCPTR GCPtrAlignment;
1062	/** Address of the range. */
1063	RTGCPHYS GCPhys;
1064	/** Address of the last byte in the range. */
1065	RTGCPHYS GCPhysLast;
1066	/** Size of the range. */
1067	RTGCPHYS cb;
1068	/** The flags (PGMPHYS_ROM_FLAG_). /
1069	uint32_t fFlags;
1070	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1071	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1072	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1073	* This is used for strictness checks. */
1074	R3PTRTYPE(const void *) pvOriginal;
1075	/** The ROM description. */
1076	R3PTRTYPE(const char *) pszDesc;
1077	/** The per page tracking structures. */
1078	PGMROMPAGE aPages[1];
1079	} PGMROMRANGE;
1080	/** Pointer to a ROM range. */
1081	typedef PGMROMRANGE *PPGMROMRANGE;
1082
1083
1084	/**
1085	* A registered MMIO2 (= Device RAM) range.
1086	*
1087	* There are a few reason why we need to keep track of these
1088	* registrations. One of them is the deregistration & cleanup
1089	* stuff, while another is that the PGMRAMRANGE associated with
1090	* such a region may have to be removed from the ram range list.
1091	*
1092	* Overlapping with a RAM range has to be 100% or none at all. The
1093	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1094	* meditation will be raised if a partial overlap or an overlap of
1095	* ROM pages is encountered. On an overlap we will free all the
1096	* existing RAM pages and put in the ram range pages instead.
1097	*/
1098	typedef struct PGMMMIO2RANGE
1099	{
1100	/** The owner of the range. (a device) */
1101	PPDMDEVINSR3 pDevInsR3;
1102	/** Pointer to the ring-3 mapping of the allocation. */
1103	RTR3PTR pvR3;
1104	/** Pointer to the next range - R3. */
1105	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1106	/** Whether it's mapped or not. */
1107	bool fMapped;
1108	/** Whether it's overlapping or not. */
1109	bool fOverlapping;
1110	/** The PCI region number.
1111	* @remarks This ASSUMES that nobody will ever really need to have multiple
1112	* PCI devices with matching MMIO region numbers on a single device. */
1113	uint8_t iRegion;
1114	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1115	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1116	/** The associated RAM range. */
1117	PGMRAMRANGE RamRange;
1118	} PGMMMIO2RANGE;
1119	/** Pointer to a MMIO2 range. */
1120	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1121
1122
1123
1124
1125	/**
1126	* PGMPhysRead/Write cache entry
1127	*/
1128	typedef struct PGMPHYSCACHEENTRY
1129	{
1130	/** R3 pointer to physical page. */
1131	R3PTRTYPE(uint8_t *) pbR3;
1132	/** GC Physical address for cache entry */
1133	RTGCPHYS GCPhys;
1134	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1135	RTGCPHYS u32Padding0; /*< alignment padding. /
1136	#endif
1137	} PGMPHYSCACHEENTRY;
1138
1139	/**
1140	* PGMPhysRead/Write cache to reduce REM memory access overhead
1141	*/
1142	typedef struct PGMPHYSCACHE
1143	{
1144	/** Bitmap of valid cache entries */
1145	uint64_t aEntries;
1146	/** Cache entries */
1147	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1148	} PGMPHYSCACHE;
1149
1150
1151	/** Pointer to an allocation chunk ring-3 mapping. */
1152	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1153	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1154	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1155
1156	/**
1157	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1158	*
1159	* The primary tree (Core) uses the chunk id as key.
1160	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1161	*/
1162	typedef struct PGMCHUNKR3MAP
1163	{
1164	/** The key is the chunk id. */
1165	AVLU32NODECORE Core;
1166	/** The key is the ageing sequence number. */
1167	AVLLU32NODECORE AgeCore;
1168	/** The current age thingy. */
1169	uint32_t iAge;
1170	/** The current reference count. */
1171	uint32_t volatile cRefs;
1172	/** The current permanent reference count. */
1173	uint32_t volatile cPermRefs;
1174	/** The mapping address. */
1175	void *pv;
1176	} PGMCHUNKR3MAP;
1177
1178	/**
1179	* Allocation chunk ring-3 mapping TLB entry.
1180	*/
1181	typedef struct PGMCHUNKR3MAPTLBE
1182	{
1183	/** The chunk id. */
1184	uint32_t volatile idChunk;
1185	#if HC_ARCH_BITS == 64
1186	uint32_t u32Padding; /*< alignment padding. /
1187	#endif
1188	/** The chunk map. */
1189	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1190	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1191	#else
1192	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1193	#endif
1194	} PGMCHUNKR3MAPTLBE;
1195	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1196	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1197
1198	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1199	* @remark Must be a power of two value. */
1200	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1201
1202	/**
1203	* Allocation chunk ring-3 mapping TLB.
1204	*
1205	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1206	* At first glance this might look kinda odd since AVL trees are
1207	* supposed to give the most optimial lookup times of all trees
1208	* due to their balancing. However, take a tree with 1023 nodes
1209	* in it, that's 10 levels, meaning that most searches has to go
1210	* down 9 levels before they find what they want. This isn't fast
1211	* compared to a TLB hit. There is the factor of cache misses,
1212	* and of course the problem with trees and branch prediction.
1213	* This is why we use TLBs in front of most of the trees.
1214	*
1215	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1216	* difficult when we switch to the new inlined AVL trees (from kStuff).
1217	*/
1218	typedef struct PGMCHUNKR3MAPTLB
1219	{
1220	/** The TLB entries. */
1221	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1222	} PGMCHUNKR3MAPTLB;
1223
1224	/**
1225	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1226	* @returns Chunk TLB index.
1227	* @param idChunk The Chunk ID.
1228	*/
1229	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1230
1231
1232	/**
1233	* Ring-3 guest page mapping TLB entry.
1234	* @remarks used in ring-0 as well at the moment.
1235	*/
1236	typedef struct PGMPAGER3MAPTLBE
1237	{
1238	/** Address of the page. */
1239	RTGCPHYS volatile GCPhys;
1240	/** The guest page. */
1241	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1242	R3PTRTYPE(PPGMPAGE) volatile pPage;
1243	#else
1244	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1245	#endif
1246	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1247	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1248	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1249	#else
1250	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1251	#endif
1252	/** The address */
1253	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1254	R3PTRTYPE(void *) volatile pv;
1255	#else
1256	R3R0PTRTYPE(void *) volatile pv;
1257	#endif
1258	#if HC_ARCH_BITS == 32
1259	uint32_t u32Padding; /*< alignment padding. /
1260	#endif
1261	} PGMPAGER3MAPTLBE;
1262	/** Pointer to an entry in the HC physical TLB. */
1263	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1264
1265
1266	/** The number of entries in the ring-3 guest page mapping TLB.
1267	* @remarks The value must be a power of two. */
1268	#define PGM_PAGER3MAPTLB_ENTRIES 64
1269
1270	/**
1271	* Ring-3 guest page mapping TLB.
1272	* @remarks used in ring-0 as well at the moment.
1273	*/
1274	typedef struct PGMPAGER3MAPTLB
1275	{
1276	/** The TLB entries. */
1277	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1278	} PGMPAGER3MAPTLB;
1279	/** Pointer to the ring-3 guest page mapping TLB. */
1280	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1281
1282	/**
1283	* Calculates the index of the TLB entry for the specified guest page.
1284	* @returns Physical TLB index.
1285	* @param GCPhys The guest physical address.
1286	*/
1287	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1288
1289
1290	/**
1291	* Mapping cache usage set entry.
1292	*
1293	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1294	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1295	* cache. If it's extended to include ring-3, well, then something will
1296	* have be changed here...
1297	*/
1298	typedef struct PGMMAPSETENTRY
1299	{
1300	/** The mapping cache index. */
1301	uint16_t iPage;
1302	/** The number of references.
1303	* The max is UINT16_MAX - 1. */
1304	uint16_t cRefs;
1305	/** Pointer to the page. */
1306	RTR0PTR pvPage;
1307	/** The physical address for this entry. */
1308	RTHCPHYS HCPhys;
1309	} PGMMAPSETENTRY;
1310	/** Pointer to a mapping cache usage set entry. */
1311	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1312
1313	/**
1314	* Mapping cache usage set.
1315	*
1316	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1317	* done during exits / traps. The set is
1318	*/
1319	typedef struct PGMMAPSET
1320	{
1321	/** The number of occupied entries.
1322	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1323	* dynamic mappings. */
1324	uint32_t cEntries;
1325	/** The start of the current subset.
1326	* This is UINT32_MAX if no subset is currently open. */
1327	uint32_t iSubset;
1328	/** The index of the current CPU, only valid if the set is open. */
1329	int32_t iCpu;
1330	/** The entries. */
1331	PGMMAPSETENTRY aEntries[64];
1332	/** HCPhys -> iEntry fast lookup table.
1333	* Use PGMMAPSET_HASH for hashing.
1334	* The entries may or may not be valid, check against cEntries. */
1335	uint8_t aiHashTable[128];
1336	} PGMMAPSET;
1337	/** Pointer to the mapping cache set. */
1338	typedef PGMMAPSET *PPGMMAPSET;
1339
1340	/** PGMMAPSET::cEntries value for a closed set. */
1341	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1342
1343	/** Hash function for aiHashTable. */
1344	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1345
1346	/** The max fill size (strict builds). */
1347	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1348
1349
1350	/** @name Context neutrual page mapper TLB.
1351	*
1352	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1353	* code is writting in a kind of context neutrual way. Time will show whether
1354	* this actually makes sense or not...
1355	*
1356	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1357	* context ends up using a global mapping cache on some platforms
1358	* (darwin).
1359	*
1360	* @{ */
1361	/** @typedef PPGMPAGEMAPTLB
1362	* The page mapper TLB pointer type for the current context. */
1363	/** @typedef PPGMPAGEMAPTLB
1364	* The page mapper TLB entry pointer type for the current context. */
1365	/** @typedef PPGMPAGEMAPTLB
1366	* The page mapper TLB entry pointer pointer type for the current context. */
1367	/** @def PGM_PAGEMAPTLB_ENTRIES
1368	* The number of TLB entries in the page mapper TLB for the current context. */
1369	/** @def PGM_PAGEMAPTLB_IDX
1370	* Calculate the TLB index for a guest physical address.
1371	* @returns The TLB index.
1372	* @param GCPhys The guest physical address. */
1373	/** @typedef PPGMPAGEMAP
1374	* Pointer to a page mapper unit for current context. */
1375	/** @typedef PPPGMPAGEMAP
1376	* Pointer to a page mapper unit pointer for current context. */
1377	#ifdef IN_RC
1378	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1379	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1380	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1381	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1382	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1383	typedef void * PPGMPAGEMAP;
1384	typedef void ** PPPGMPAGEMAP;
1385	//#elif IN_RING0
1386	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1387	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1388	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1389	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1390	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1391	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1392	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1393	#else
1394	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1395	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1396	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1397	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1398	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1399	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1400	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1401	#endif
1402	/** @} */
1403
1404
1405	/** @name PGM Pool Indexes.
1406	* Aka. the unique shadow page identifier.
1407	* @{ */
1408	/** NIL page pool IDX. */
1409	#define NIL_PGMPOOL_IDX 0
1410	/** The first normal index. */
1411	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1412	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1413	/** Page directory (32-bit root). */
1414	#define PGMPOOL_IDX_PD 1
1415	/** Page Directory Pointer Table (PAE root). */
1416	#define PGMPOOL_IDX_PDPT 2
1417	/** AMD64 CR3 level index.*/
1418	#define PGMPOOL_IDX_AMD64_CR3 3
1419	/** Nested paging root.*/
1420	#define PGMPOOL_IDX_NESTED_ROOT 4
1421	/** The first normal index. */
1422	#define PGMPOOL_IDX_FIRST 5
1423	#else
1424	/** Page directory (32-bit root). */
1425	#define PGMPOOL_IDX_PD 1
1426	/** The extended PAE page directory (2048 entries, works as root currently). */
1427	#define PGMPOOL_IDX_PAE_PD 2
1428	/** PAE Page Directory Table 0. */
1429	#define PGMPOOL_IDX_PAE_PD_0 3
1430	/** PAE Page Directory Table 1. */
1431	#define PGMPOOL_IDX_PAE_PD_1 4
1432	/** PAE Page Directory Table 2. */
1433	#define PGMPOOL_IDX_PAE_PD_2 5
1434	/** PAE Page Directory Table 3. */
1435	#define PGMPOOL_IDX_PAE_PD_3 6
1436	/** Page Directory Pointer Table (PAE root, not currently used). */
1437	#define PGMPOOL_IDX_PDPT 7
1438	/** AMD64 CR3 level index.*/
1439	#define PGMPOOL_IDX_AMD64_CR3 8
1440	/** Nested paging root.*/
1441	#define PGMPOOL_IDX_NESTED_ROOT 9
1442	/** The first normal index. */
1443	#define PGMPOOL_IDX_FIRST 10
1444	#endif
1445	/** The last valid index. (inclusive, 14 bits) */
1446	#define PGMPOOL_IDX_LAST 0x3fff
1447	/** @} */
1448
1449	/** The NIL index for the parent chain. */
1450	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1451
1452	/**
1453	* Node in the chain linking a shadowed page to it's parent (user).
1454	*/
1455	#pragma pack(1)
1456	typedef struct PGMPOOLUSER
1457	{
1458	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1459	uint16_t iNext;
1460	/** The user page index. */
1461	uint16_t iUser;
1462	/** Index into the user table. */
1463	uint32_t iUserTable;
1464	} PGMPOOLUSER, *PPGMPOOLUSER;
1465	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1466	#pragma pack()
1467
1468
1469	/** The NIL index for the phys ext chain. */
1470	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1471
1472	/**
1473	* Node in the chain of physical cross reference extents.
1474	*/
1475	#pragma pack(1)
1476	typedef struct PGMPOOLPHYSEXT
1477	{
1478	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1479	uint16_t iNext;
1480	/** The user page index. */
1481	uint16_t aidx[3];
1482	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1483	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1484	#pragma pack()
1485
1486
1487	/**
1488	* The kind of page that's being shadowed.
1489	*/
1490	typedef enum PGMPOOLKIND
1491	{
1492	/** The virtual invalid 0 entry. */
1493	PGMPOOLKIND_INVALID = 0,
1494	/** The entry is free (=unused). */
1495	PGMPOOLKIND_FREE,
1496
1497	/** Shw: 32-bit page table; Gst: no paging */
1498	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1499	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1500	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1501	/** Shw: 32-bit page table; Gst: 4MB page. */
1502	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1503	/** Shw: PAE page table; Gst: no paging */
1504	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1505	/** Shw: PAE page table; Gst: 32-bit page table. */
1506	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1507	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1508	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1509	/** Shw: PAE page table; Gst: PAE page table. */
1510	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1511	/** Shw: PAE page table; Gst: 2MB page. */
1512	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1513
1514	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1515	PGMPOOLKIND_32BIT_PD,
1516	/** Shw: 32-bit page directory. Gst: no paging. */
1517	PGMPOOLKIND_32BIT_PD_PHYS,
1518	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1519	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1520	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1521	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1522	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1523	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1524	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1525	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1526	/** Shw: PAE page directory; Gst: PAE page directory. */
1527	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1528	/** Shw: PAE page directory; Gst: no paging. */
1529	PGMPOOLKIND_PAE_PD_PHYS,
1530
1531	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1532	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1533	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1534	PGMPOOLKIND_PAE_PDPT,
1535	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1536	PGMPOOLKIND_PAE_PDPT_PHYS,
1537
1538	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1539	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1540	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1541	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1542	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1543	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1544	/** Shw: 64-bit page directory table; Gst: no paging */
1545	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1546
1547	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1548	PGMPOOLKIND_64BIT_PML4,
1549
1550	/** Shw: EPT page directory pointer table; Gst: no paging */
1551	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1552	/** Shw: EPT page directory table; Gst: no paging */
1553	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1554	/** Shw: EPT page table; Gst: no paging */
1555	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1556
1557	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1558	/** Shw: Root 32-bit page directory. */
1559	PGMPOOLKIND_ROOT_32BIT_PD,
1560	/** Shw: Root PAE page directory */
1561	PGMPOOLKIND_ROOT_PAE_PD,
1562	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1563	PGMPOOLKIND_ROOT_PDPT,
1564	#endif
1565	/** Shw: Root Nested paging table. */
1566	PGMPOOLKIND_ROOT_NESTED,
1567
1568	/** The last valid entry. */
1569	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1570	} PGMPOOLKIND;
1571
1572
1573	/**
1574	* The tracking data for a page in the pool.
1575	*/
1576	typedef struct PGMPOOLPAGE
1577	{
1578	/** AVL node code with the (R3) physical address of this page. */
1579	AVLOHCPHYSNODECORE Core;
1580	/** Pointer to the R3 mapping of the page. */
1581	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1582	R3PTRTYPE(void *) pvPageR3;
1583	#else
1584	R3R0PTRTYPE(void *) pvPageR3;
1585	#endif
1586	/** The guest physical address. */
1587	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1588	uint32_t Alignment0;
1589	#endif
1590	RTGCPHYS GCPhys;
1591	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1592	uint8_t enmKind;
1593	uint8_t bPadding;
1594	/** The index of this page. */
1595	uint16_t idx;
1596	/** The next entry in the list this page currently resides in.
1597	* It's either in the free list or in the GCPhys hash. */
1598	uint16_t iNext;
1599	#ifdef PGMPOOL_WITH_USER_TRACKING
1600	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1601	uint16_t iUserHead;
1602	/** The number of present entries. */
1603	uint16_t cPresent;
1604	/** The first entry in the table which is present. */
1605	uint16_t iFirstPresent;
1606	#endif
1607	#ifdef PGMPOOL_WITH_MONITORING
1608	/** The number of modifications to the monitored page. */
1609	uint16_t cModifications;
1610	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1611	uint16_t iModifiedNext;
1612	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1613	uint16_t iModifiedPrev;
1614	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1615	uint16_t iMonitoredNext;
1616	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1617	uint16_t iMonitoredPrev;
1618	#endif
1619	#ifdef PGMPOOL_WITH_CACHE
1620	/** The next page in the age list. */
1621	uint16_t iAgeNext;
1622	/** The previous page in the age list. */
1623	uint16_t iAgePrev;
1624	#endif /* PGMPOOL_WITH_CACHE */
1625	/** Used to indicate that the page is zeroed. */
1626	bool fZeroed;
1627	/** Used to indicate that a PT has non-global entries. */
1628	bool fSeenNonGlobal;
1629	/** Used to indicate that we're monitoring writes to the guest page. */
1630	bool fMonitored;
1631	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1632	* (All pages are in the age list.) */
1633	bool fCached;
1634	/** This is used by the R3 access handlers when invoked by an async thread.
1635	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1636	bool volatile fReusedFlushPending;
1637	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1638	* In these cases the access handler acts differently and will check
1639	* for mapping conflicts like the normal CR3 handler.
1640	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1641	* replaced by a list of pages which share access handler.
1642	*/
1643	bool fCR3Mix;
1644	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1645
1646
1647	#ifdef PGMPOOL_WITH_CACHE
1648	/** The hash table size. */
1649	# define PGMPOOL_HASH_SIZE 0x40
1650	/** The hash function. */
1651	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1652	#endif
1653
1654
1655	/**
1656	* The shadow page pool instance data.
1657	*
1658	* It's all one big allocation made at init time, except for the
1659	* pages that is. The user nodes follows immediatly after the
1660	* page structures.
1661	*/
1662	typedef struct PGMPOOL
1663	{
1664	/** The VM handle - R3 Ptr. */
1665	PVMR3 pVMR3;
1666	/** The VM handle - R0 Ptr. */
1667	PVMR0 pVMR0;
1668	/** The VM handle - RC Ptr. */
1669	PVMRC pVMRC;
1670	/** The max pool size. This includes the special IDs. */
1671	uint16_t cMaxPages;
1672	/** The current pool size. */
1673	uint16_t cCurPages;
1674	/** The head of the free page list. */
1675	uint16_t iFreeHead;
1676	/* Padding. */
1677	uint16_t u16Padding;
1678	#ifdef PGMPOOL_WITH_USER_TRACKING
1679	/** Head of the chain of free user nodes. */
1680	uint16_t iUserFreeHead;
1681	/** The number of user nodes we've allocated. */
1682	uint16_t cMaxUsers;
1683	/** The number of present page table entries in the entire pool. */
1684	uint32_t cPresent;
1685	/** Pointer to the array of user nodes - RC pointer. */
1686	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1687	/** Pointer to the array of user nodes - R3 pointer. */
1688	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1689	/** Pointer to the array of user nodes - R0 pointer. */
1690	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1691	#endif /* PGMPOOL_WITH_USER_TRACKING */
1692	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1693	/** Head of the chain of free phys ext nodes. */
1694	uint16_t iPhysExtFreeHead;
1695	/** The number of user nodes we've allocated. */
1696	uint16_t cMaxPhysExts;
1697	/** Pointer to the array of physical xref extent - RC pointer. */
1698	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1699	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1700	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1701	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1702	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1703	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1704	#ifdef PGMPOOL_WITH_CACHE
1705	/** Hash table for GCPhys addresses. */
1706	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1707	/** The head of the age list. */
1708	uint16_t iAgeHead;
1709	/** The tail of the age list. */
1710	uint16_t iAgeTail;
1711	/** Set if the cache is enabled. */
1712	bool fCacheEnabled;
1713	#endif /* PGMPOOL_WITH_CACHE */
1714	#ifdef PGMPOOL_WITH_MONITORING
1715	/** Head of the list of modified pages. */
1716	uint16_t iModifiedHead;
1717	/** The current number of modified pages. */
1718	uint16_t cModifiedPages;
1719	/** Access handler, RC. */
1720	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1721	/** Access handler, R0. */
1722	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1723	/** Access handler, R3. */
1724	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1725	/** The access handler description (HC ptr). */
1726	R3PTRTYPE(const char *) pszAccessHandler;
1727	#endif /* PGMPOOL_WITH_MONITORING */
1728	/** The number of pages currently in use. */
1729	uint16_t cUsedPages;
1730	#ifdef VBOX_WITH_STATISTICS
1731	/** The high wather mark for cUsedPages. */
1732	uint16_t cUsedPagesHigh;
1733	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1734	/** Profiling pgmPoolAlloc(). */
1735	STAMPROFILEADV StatAlloc;
1736	/** Profiling pgmPoolClearAll(). */
1737	STAMPROFILE StatClearAll;
1738	/** Profiling pgmPoolFlushAllInt(). */
1739	STAMPROFILE StatFlushAllInt;
1740	/** Profiling pgmPoolFlushPage(). */
1741	STAMPROFILE StatFlushPage;
1742	/** Profiling pgmPoolFree(). */
1743	STAMPROFILE StatFree;
1744	/** Profiling time spent zeroing pages. */
1745	STAMPROFILE StatZeroPage;
1746	# ifdef PGMPOOL_WITH_USER_TRACKING
1747	/** Profiling of pgmPoolTrackDeref. */
1748	STAMPROFILE StatTrackDeref;
1749	/** Profiling pgmTrackFlushGCPhysPT. */
1750	STAMPROFILE StatTrackFlushGCPhysPT;
1751	/** Profiling pgmTrackFlushGCPhysPTs. */
1752	STAMPROFILE StatTrackFlushGCPhysPTs;
1753	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1754	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1755	/** Number of times we've been out of user records. */
1756	STAMCOUNTER StatTrackFreeUpOneUser;
1757	# endif
1758	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1759	/** Profiling deref activity related tracking GC physical pages. */
1760	STAMPROFILE StatTrackDerefGCPhys;
1761	/** Number of linear searches for a HCPhys in the ram ranges. */
1762	STAMCOUNTER StatTrackLinearRamSearches;
1763	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1764	STAMCOUNTER StamTrackPhysExtAllocFailures;
1765	# endif
1766	# ifdef PGMPOOL_WITH_MONITORING
1767	/** Profiling the RC/R0 access handler. */
1768	STAMPROFILE StatMonitorRZ;
1769	/** Times we've failed interpreting the instruction. */
1770	STAMCOUNTER StatMonitorRZEmulateInstr;
1771	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1772	STAMPROFILE StatMonitorRZFlushPage;
1773	/** Times we've detected fork(). */
1774	STAMCOUNTER StatMonitorRZFork;
1775	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1776	STAMPROFILE StatMonitorRZHandled;
1777	/** Times we've failed interpreting a patch code instruction. */
1778	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1779	/** Times we've failed interpreting a patch code instruction during flushing. */
1780	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1781	/** The number of times we've seen rep prefixes we can't handle. */
1782	STAMCOUNTER StatMonitorRZRepPrefix;
1783	/** Profiling the REP STOSD cases we've handled. */
1784	STAMPROFILE StatMonitorRZRepStosd;
1785
1786	/** Profiling the R3 access handler. */
1787	STAMPROFILE StatMonitorR3;
1788	/** Times we've failed interpreting the instruction. */
1789	STAMCOUNTER StatMonitorR3EmulateInstr;
1790	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1791	STAMPROFILE StatMonitorR3FlushPage;
1792	/** Times we've detected fork(). */
1793	STAMCOUNTER StatMonitorR3Fork;
1794	/** Profiling the R3 access we've handled (except REP STOSD). */
1795	STAMPROFILE StatMonitorR3Handled;
1796	/** The number of times we've seen rep prefixes we can't handle. */
1797	STAMCOUNTER StatMonitorR3RepPrefix;
1798	/** Profiling the REP STOSD cases we've handled. */
1799	STAMPROFILE StatMonitorR3RepStosd;
1800	/** The number of times we're called in an async thread an need to flush. */
1801	STAMCOUNTER StatMonitorR3Async;
1802	/** The high wather mark for cModifiedPages. */
1803	uint16_t cModifiedPagesHigh;
1804	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1805	# endif
1806	# ifdef PGMPOOL_WITH_CACHE
1807	/** The number of cache hits. */
1808	STAMCOUNTER StatCacheHits;
1809	/** The number of cache misses. */
1810	STAMCOUNTER StatCacheMisses;
1811	/** The number of times we've got a conflict of 'kind' in the cache. */
1812	STAMCOUNTER StatCacheKindMismatches;
1813	/** Number of times we've been out of pages. */
1814	STAMCOUNTER StatCacheFreeUpOne;
1815	/** The number of cacheable allocations. */
1816	STAMCOUNTER StatCacheCacheable;
1817	/** The number of uncacheable allocations. */
1818	STAMCOUNTER StatCacheUncacheable;
1819	# endif
1820	#elif HC_ARCH_BITS == 64
1821	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1822	#endif
1823	/** The AVL tree for looking up a page by its HC physical address. */
1824	AVLOHCPHYSTREE HCPhysTree;
1825	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1826	/** Array of pages. (cMaxPages in length)
1827	* The Id is the index into thist array.
1828	*/
1829	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1830	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1831
1832
1833	/** @def PGMPOOL_PAGE_2_PTR
1834	* Maps a pool page pool into the current context.
1835	*
1836	* @returns VBox status code.
1837	* @param pVM The VM handle.
1838	* @param pPage The pool page.
1839	*
1840	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1841	* small page window employeed by that function. Be careful.
1842	* @remark There is no need to assert on the result.
1843	*/
1844	#if defined(IN_RC)
1845	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1846	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1847	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1848	#elif defined(VBOX_STRICT)
1849	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1850	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1851	{
1852	Assert(pPage->pvPageR3);
1853	return pPage->pvPageR3;
1854	}
1855	#else
1856	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1857	#endif
1858
1859	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1860	* Maps a pool page pool into the current context.
1861	*
1862	* @returns VBox status code.
1863	* @param pPGM Pointer to the PGM instance data.
1864	* @param pPage The pool page.
1865	*
1866	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1867	* small page window employeed by that function. Be careful.
1868	* @remark There is no need to assert on the result.
1869	*/
1870	#if defined(IN_RC)
1871	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1872	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1873	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1874	#else
1875	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1876	#endif
1877
1878
1879
1880	/**
1881	* Trees are using self relative offsets as pointers.
1882	* So, all its data, including the root pointer, must be in the heap for HC and GC
1883	* to have the same layout.
1884	*/
1885	typedef struct PGMTREES
1886	{
1887	/** Physical access handlers (AVL range+offsetptr tree). */
1888	AVLROGCPHYSTREE PhysHandlers;
1889	/** Virtual access handlers (AVL range + GC ptr tree). */
1890	AVLROGCPTRTREE VirtHandlers;
1891	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1892	AVLROGCPHYSTREE PhysToVirtHandlers;
1893	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1894	AVLROGCPTRTREE HyperVirtHandlers;
1895	} PGMTREES;
1896	/** Pointer to PGM trees. */
1897	typedef PGMTREES *PPGMTREES;
1898
1899
1900	/** @name Paging mode macros
1901	* @{ */
1902	#ifdef IN_RC
1903	# define PGM_CTX(a,b) a##RC##b
1904	# define PGM_CTX_STR(a,b) a "GC" b
1905	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1906	#else
1907	# ifdef IN_RING3
1908	# define PGM_CTX(a,b) a##R3##b
1909	# define PGM_CTX_STR(a,b) a "R3" b
1910	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1911	# else
1912	# define PGM_CTX(a,b) a##R0##b
1913	# define PGM_CTX_STR(a,b) a "R0" b
1914	# define PGM_CTX_DECL(type) VMMDECL(type)
1915	# endif
1916	#endif
1917
1918	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1919	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1920	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1921	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1922	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1923	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1924	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1925	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1926	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1927	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1928	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1929	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1930	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1931	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1932	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1933	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1934	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1935
1936	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1937	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1938	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1939	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1940	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1941	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1942	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1943	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1944	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1945	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1946	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1947	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1948	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1949	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1950	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1951	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1952	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1953
1954	/* Shw_Gst */
1955	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1956	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1957	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1958	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1959	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1960	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1961	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1962	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1963	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1964	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1965	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1966	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1967	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1968	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1969	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1970	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1971	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1972	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1973	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1974
1975	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1976	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1977	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1978	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1979	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1980	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1981	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1982	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1983	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1984	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1985	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1986	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1987	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1988	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1989	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1990	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1991	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1992	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1993	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1994	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1995	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1996	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1997	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1998	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1999	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2000	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2001	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2002	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2003	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2004	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2005	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2006	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2007	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2008	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2009	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2010	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2011	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2012
2013	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2014	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2015	/** @} */
2016
2017	/**
2018	* Data for each paging mode.
2019	*/
2020	typedef struct PGMMODEDATA
2021	{
2022	/** The guest mode type. */
2023	uint32_t uGstType;
2024	/** The shadow mode type. */
2025	uint32_t uShwType;
2026
2027	/** @name Function pointers for Shadow paging.
2028	* @{
2029	*/
2030	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2031	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2032	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2033	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2034
2035	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2036	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2037
2038	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2039	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2040	/** @} */
2041
2042	/** @name Function pointers for Guest paging.
2043	* @{
2044	*/
2045	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2046	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2047	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2048	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2049	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2050	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2051	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2052	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2053	#endif
2054	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2055	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2056	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2057	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2058	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2059	#endif
2060	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2061	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2062	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2063	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2064	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2065	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2066	#endif
2067	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2068	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2069	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2070	#endif
2071	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2072	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2073	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2074	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2075	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2076	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2077	#endif
2078	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2079	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2080	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2081	#endif
2082	/** @} */
2083
2084	/** @name Function pointers for Both Shadow and Guest paging.
2085	* @{
2086	*/
2087	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2088	/* no pfnR3BthTrap0eHandler */
2089	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2090	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2091	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2092	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2093	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2094	#ifdef VBOX_STRICT
2095	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2096	#endif
2097	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2098	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2099
2100	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2101	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2102	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2103	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2104	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2105	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2106	#ifdef VBOX_STRICT
2107	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2108	#endif
2109	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2110	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2111
2112	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2113	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2114	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2115	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2116	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2117	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2118	#ifdef VBOX_STRICT
2119	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2120	#endif
2121	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2122	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2123	/** @} */
2124	} PGMMODEDATA, *PPGMMODEDATA;
2125
2126
2127
2128	/**
2129	* Converts a PGM pointer into a VM pointer.
2130	* @returns Pointer to the VM structure the PGM is part of.
2131	* @param pPGM Pointer to PGM instance data.
2132	*/
2133	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2134
2135	/**
2136	* PGM Data (part of VM)
2137	*/
2138	typedef struct PGM
2139	{
2140	/** Offset to the VM structure. */
2141	RTINT offVM;
2142	/** Offset of the PGMCPU structure relative to VMCPU. */
2143	int32_t offVCpu;
2144	/** Alignment padding. */
2145	int32_t i32Alignment;
2146
2147	/*
2148	* This will be redefined at least two more times before we're done, I'm sure.
2149	* The current code is only to get on with the coding.
2150	* - 2004-06-10: initial version, bird.
2151	* - 2004-07-02: 1st time, bird.
2152	* - 2004-10-18: 2nd time, bird.
2153	* - 2005-07-xx: 3rd time, bird.
2154	*/
2155
2156	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2157	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2158	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2159	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2160
2161	/** The host paging mode. (This is what SUPLib reports.) */
2162	SUPPAGINGMODE enmHostMode;
2163	/** The shadow paging mode. */
2164	PGMMODE enmShadowMode;
2165	/** The guest paging mode. */
2166	PGMMODE enmGuestMode;
2167
2168	/** The current physical address representing in the guest CR3 register. */
2169	RTGCPHYS GCPhysCR3;
2170	/** Pointer to the 5 page CR3 content mapping.
2171	* The first page is always the CR3 (in some form) while the 4 other pages
2172	* are used of the PDs in PAE mode. */
2173	RTGCPTR GCPtrCR3Mapping;
2174	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2175	uint32_t u32Alignment;
2176	#endif
2177	/** The physical address of the currently monitored guest CR3 page.
2178	* When this value is NIL_RTGCPHYS no page is being monitored. */
2179	RTGCPHYS GCPhysGstCR3Monitored;
2180
2181	/** @name 32-bit Guest Paging.
2182	* @{ */
2183	/** The guest's page directory, R3 pointer. */
2184	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2185	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2186	/** The guest's page directory, R0 pointer. */
2187	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2188	#endif
2189	/** The guest's page directory, static RC mapping. */
2190	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2191	/** @} */
2192
2193	/** @name PAE Guest Paging.
2194	* @{ */
2195	/** The guest's page directory pointer table, static RC mapping. */
2196	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2197	/** The guest's page directory pointer table, R3 pointer. */
2198	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2199	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2200	/** The guest's page directory pointer table, R0 pointer. */
2201	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2202	#endif
2203
2204	/** The guest's page directories, R3 pointers.
2205	* These are individual pointers and don't have to be adjecent.
2206	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2207	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2208	/** The guest's page directories, R0 pointers.
2209	* Same restrictions as apGstPaePDsR3. */
2210	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2211	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2212	#endif
2213	/** The guest's page directories, static GC mapping.
2214	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2215	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2216	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2217	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2218	RTGCPHYS aGCPhysGstPaePDs[4];
2219	/** The physical addresses of the monitored guest page directories (PAE). */
2220	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2221	/** @} */
2222
2223	/** @name AMD64 Guest Paging.
2224	* @{ */
2225	/** The guest's page directory pointer table, R3 pointer. */
2226	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2227	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2228	/** The guest's page directory pointer table, R0 pointer. */
2229	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2230	#endif
2231	/** @} */
2232
2233	/** @name Shadow paging
2234	* @{ */
2235	/** The root page table - R3 Ptr. */
2236	R3PTRTYPE(void *) pShwRootR3;
2237	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2238	/** The root page table - R0 Ptr. */
2239	R0PTRTYPE(void *) pShwRootR0;
2240	# endif
2241	/** The root page table - RC Ptr. */
2242	RCPTRTYPE(void *) pShwRootRC;
2243	# if HC_ARCH_BITS == 64
2244	uint32_t u32Padding1; /*< alignment padding. /
2245	# endif
2246	/** The Physical Address (HC) of the current active shadow CR3. */
2247	RTHCPHYS HCPhysShwCR3;
2248	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2249	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2250	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2251	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2252	/** Pointer to the page of the current active CR3 - RC Ptr. */
2253	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2254	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2255	uint32_t iShwUser;
2256	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2257	uint32_t iShwUserTable;
2258	# if HC_ARCH_BITS == 64
2259	RTRCPTR alignment6; /*< structure size alignment. /
2260	# endif
2261	/** @} */
2262	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2263	/** @name 32-bit Shadow Paging
2264	* @{ */
2265	/** The 32-Bit PD - R3 Ptr. */
2266	R3PTRTYPE(PX86PD) pShw32BitPdR3;
2267	/** The 32-Bit PD - R0 Ptr. */
2268	R0PTRTYPE(PX86PD) pShw32BitPdR0;
2269	/** The 32-Bit PD - RC Ptr. */
2270	RCPTRTYPE(PX86PD) pShw32BitPdRC;
2271	# if HC_ARCH_BITS == 64
2272	uint32_t u32Padding10; /*< alignment padding. /
2273	# endif
2274	/** The Physical Address (HC) of the 32-Bit PD. */
2275	RTHCPHYS HCPhysShw32BitPD;
2276	/** @} */
2277
2278	/** @name PAE Shadow Paging
2279	* @{ */
2280	/** The four PDs for the low 4GB - R3 Ptr.
2281	* Even though these are 4 pointers, what they point at is a single table.
2282	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2283	R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2284	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2285	/** The four PDs for the low 4GB - R0 Ptr.
2286	* Same kind of mapping as apHCPaePDs. */
2287	R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2288	# endif
2289	/** The four PDs for the low 4GB - RC Ptr.
2290	* Same kind of mapping as apHCPaePDs. */
2291	RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2292	/** The Physical Address (HC) of the four PDs for the low 4GB.
2293	* These are NOT 4 contiguous pages. */
2294	RTHCPHYS aHCPhysPaePDs[4];
2295	/** The Physical Address (HC) of the PAE PDPT. */
2296	RTHCPHYS HCPhysShwPaePdpt;
2297	/** The PAE PDPT - R3 Ptr. */
2298	R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2299	/** The PAE PDPT - R0 Ptr. */
2300	R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2301	/** The PAE PDPT - RC Ptr. */
2302	RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2303	/** @} */
2304	# if HC_ARCH_BITS == 64
2305	RTRCPTR alignment5; /*< structure size alignment. /
2306	# endif
2307	#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2308	/** @name Nested Shadow Paging
2309	* @{ */
2310	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2311	RTR3PTR pShwNestedRootR3;
2312	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2313	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2314	RTR0PTR pShwNestedRootR0;
2315	# endif
2316	/** The Physical Address (HC) of the nested paging root. */
2317	RTHCPHYS HCPhysShwNestedRoot;
2318	/** @} */
2319
2320	/** @name Function pointers for Shadow paging.
2321	* @{
2322	*/
2323	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2324	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2325	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2326	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2327
2328	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2329	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2330
2331	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2332	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2333
2334	/** @} */
2335
2336	/** @name Function pointers for Guest paging.
2337	* @{
2338	*/
2339	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2340	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2341	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2342	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2343	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2344	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2345	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2346	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2347	#endif
2348	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2349	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2350	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2351	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2352	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2353	#endif
2354	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2355	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2356	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2357	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2358	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2359	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2360	#endif
2361	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2362	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2363	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2364	#endif
2365	#if HC_ARCH_BITS == 64
2366	RTRCPTR alignment3; /*< structure size alignment. /
2367	#endif
2368
2369	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2370	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2371	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2372	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2373	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2374	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2375	#endif
2376	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2377	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2378	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2379	#endif
2380	/** @} */
2381
2382	/** @name Function pointers for Both Shadow and Guest paging.
2383	* @{
2384	*/
2385	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2386	/* no pfnR3BthTrap0eHandler */
2387	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2388	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2389	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2390	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2391	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2392	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2393	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2394	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2395
2396	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2397	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2398	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2399	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2400	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2401	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2402	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2403	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2404	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2405
2406	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2407	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2408	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2409	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2410	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2411	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2412	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2413	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2414	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2415	#if HC_ARCH_BITS == 64
2416	RTRCPTR alignment2; /*< structure size alignment. /
2417	#endif
2418	/** @} */
2419
2420	/** Pointer to SHW+GST mode data (function pointers).
2421	* The index into this table is made up from */
2422	R3PTRTYPE(PPGMMODEDATA) paModeData;
2423
2424	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2425	* This is sorted by physical address and contains no overlapping ranges. */
2426	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2427	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2428	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2429	/** RC pointer corresponding to PGM::pRamRangesR3. */
2430	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2431	/** The configured RAM size. */
2432	RTUINT cbRamSize;
2433
2434	/** Pointer to the list of ROM ranges - for R3.
2435	* This is sorted by physical address and contains no overlapping ranges. */
2436	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2437	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2438	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2439	/** RC pointer corresponding to PGM::pRomRangesR3. */
2440	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2441	/** Alignment padding. */
2442	RTRCPTR GCPtrPadding2;
2443
2444	/** Pointer to the list of MMIO2 ranges - for R3.
2445	* Registration order. */
2446	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2447
2448	/** PGM offset based trees - R3 Ptr. */
2449	R3PTRTYPE(PPGMTREES) pTreesR3;
2450	/** PGM offset based trees - R0 Ptr. */
2451	R0PTRTYPE(PPGMTREES) pTreesR0;
2452	/** PGM offset based trees - RC Ptr. */
2453	RCPTRTYPE(PPGMTREES) pTreesRC;
2454
2455	/** Linked list of GC mappings - for RC.
2456	* The list is sorted ascending on address.
2457	*/
2458	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2459	/** Linked list of GC mappings - for HC.
2460	* The list is sorted ascending on address.
2461	*/
2462	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2463	/** Linked list of GC mappings - for R0.
2464	* The list is sorted ascending on address.
2465	*/
2466	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2467
2468	/** Indicates that PGMR3FinalizeMappings has been called and that further
2469	* PGMR3MapIntermediate calls will be rejected. */
2470	bool fFinalizedMappings;
2471	/** If set no conflict checks are required. (boolean) */
2472	bool fMappingsFixed;
2473	/** If set, then no mappings are put into the shadow page table. (boolean) */
2474	bool fDisableMappings;
2475	/** Size of fixed mapping */
2476	uint32_t cbMappingFixed;
2477	/** Base address (GC) of fixed mapping */
2478	RTGCPTR GCPtrMappingFixed;
2479	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2480	uint32_t u32Padding0; /*< alignment padding. /
2481	#endif
2482
2483
2484	/** @name Intermediate Context
2485	* @{ */
2486	/** Pointer to the intermediate page directory - Normal. */
2487	R3PTRTYPE(PX86PD) pInterPD;
2488	/** Pointer to the intermedate page tables - Normal.
2489	* There are two page tables, one for the identity mapping and one for
2490	* the host context mapping (of the core code). */
2491	R3PTRTYPE(PX86PT) apInterPTs[2];
2492	/** Pointer to the intermedate page tables - PAE. */
2493	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2494	/** Pointer to the intermedate page directory - PAE. */
2495	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2496	/** Pointer to the intermedate page directory - PAE. */
2497	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2498	/** Pointer to the intermedate page-map level 4 - AMD64. */
2499	R3PTRTYPE(PX86PML4) pInterPaePML4;
2500	/** Pointer to the intermedate page directory - AMD64. */
2501	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2502	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2503	RTHCPHYS HCPhysInterPD;
2504	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2505	RTHCPHYS HCPhysInterPaePDPT;
2506	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2507	RTHCPHYS HCPhysInterPaePML4;
2508	/** @} */
2509
2510	/** Base address of the dynamic page mapping area.
2511	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2512	*/
2513	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2514	/** The index of the last entry used in the dynamic page mapping area. */
2515	RTUINT iDynPageMapLast;
2516	/** Cache containing the last entries in the dynamic page mapping area.
2517	* The cache size is covering half of the mapping area. */
2518	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2519
2520	/** The address of the ring-0 mapping cache if we're making use of it. */
2521	RTR0PTR pvR0DynMapUsed;
2522	#if HC_ARCH_BITS == 32
2523	RTR0PTR R0PtrPadding0; /*< Alignment. /
2524	#endif
2525
2526
2527	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2528	RTGCPHYS GCPhys4MBPSEMask;
2529
2530	/** A20 gate mask.
2531	* Our current approach to A20 emulation is to let REM do it and don't bother
2532	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2533	* But whould need arrise, we'll subject physical addresses to this mask. */
2534	RTGCPHYS GCPhysA20Mask;
2535	/** A20 gate state - boolean! */
2536	RTUINT fA20Enabled;
2537
2538	/** What needs syncing (PGM_SYNC_*).
2539	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2540	* PGMFlushTLB, and PGMR3Load. */
2541	RTUINT fSyncFlags;
2542
2543	/** PGM critical section.
2544	* This protects the physical & virtual access handlers, ram ranges,
2545	* and the page flag updating (some of it anyway).
2546	*/
2547	PDMCRITSECT CritSect;
2548
2549	/** Shadow Page Pool - R3 Ptr. */
2550	R3PTRTYPE(PPGMPOOL) pPoolR3;
2551	/** Shadow Page Pool - R0 Ptr. */
2552	R0PTRTYPE(PPGMPOOL) pPoolR0;
2553	/** Shadow Page Pool - RC Ptr. */
2554	RCPTRTYPE(PPGMPOOL) pPoolRC;
2555
2556	/** We're not in a state which permits writes to guest memory.
2557	* (Only used in strict builds.) */
2558	bool fNoMorePhysWrites;
2559
2560	/** Flush the cache on the next access. */
2561	bool fPhysCacheFlushPending;
2562	/** @todo r=bird: Fix member names!*/
2563	/** PGMPhysRead cache */
2564	PGMPHYSCACHE pgmphysreadcache;
2565	/** PGMPhysWrite cache */
2566	PGMPHYSCACHE pgmphyswritecache;
2567
2568	/**
2569	* Data associated with managing the ring-3 mappings of the allocation chunks.
2570	*/
2571	struct
2572	{
2573	/** The chunk tree, ordered by chunk id. */
2574	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2575	R3PTRTYPE(PAVLU32NODECORE) pTree;
2576	#else
2577	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2578	#endif
2579	/** The chunk mapping TLB. */
2580	PGMCHUNKR3MAPTLB Tlb;
2581	/** The number of mapped chunks. */
2582	uint32_t c;
2583	/** The maximum number of mapped chunks.
2584	* @cfgm PGM/MaxRing3Chunks */
2585	uint32_t cMax;
2586	/** The chunk age tree, ordered by ageing sequence number. */
2587	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2588	/** The current time. */
2589	uint32_t iNow;
2590	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2591	uint32_t AgeingCountdown;
2592	} ChunkR3Map;
2593
2594	/**
2595	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2596	*/
2597	PGMPAGER3MAPTLB PhysTlbHC;
2598
2599	/** @name The zero page.
2600	* @{ */
2601	/** The host physical address of the zero page. */
2602	RTHCPHYS HCPhysZeroPg;
2603	/** The ring-3 mapping of the zero page. */
2604	RTR3PTR pvZeroPgR3;
2605	/** The ring-0 mapping of the zero page. */
2606	RTR0PTR pvZeroPgR0;
2607	/** The GC mapping of the zero page. */
2608	RTGCPTR pvZeroPgGC;
2609	#if GC_ARCH_BITS != 32
2610	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2611	#endif
2612	/** @}*/
2613
2614	/** The number of handy pages. */
2615	uint32_t cHandyPages;
2616	/**
2617	* Array of handy pages.
2618	*
2619	* This array is used in a two way communication between pgmPhysAllocPage
2620	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2621	* an intermediary.
2622	*
2623	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2624	* (The current size of 32 pages, means 128 KB of handy memory.)
2625	*/
2626	GMMPAGEDESC aHandyPages[32];
2627
2628	/** @name Release Statistics
2629	* @{ */
2630	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2631	uint32_t cPrivatePages; /*< The number of private pages. /
2632	uint32_t cSharedPages; /*< The number of shared pages. /
2633	uint32_t cZeroPages; /*< The number of zero backed pages. /
2634	/** The number of times the guest has switched mode since last reset or statistics reset. */
2635	STAMCOUNTER cGuestModeChanges;
2636	/** The number of times we were forced to change the hypervisor region location. */
2637	STAMCOUNTER cRelocations;
2638	/** @} */
2639
2640	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2641	/** RC: Which statistic this \#PF should be attributed to. */
2642	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2643	RTRCPTR padding0;
2644	/** R0: Which statistic this \#PF should be attributed to. */
2645	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2646	RTR0PTR padding1;
2647
2648	/* Common */
2649	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2650	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2651	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2652	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2653	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2654	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2655	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2656	# endif
2657	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2658	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2659
2660	/* R3 only: */
2661	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2662	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2663	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2664	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2665	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2666	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2667
2668	/* R0 only: */
2669	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2670	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2671	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2672	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2673	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2674	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2675	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2676	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2677	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2678	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2679	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2680	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2681	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2682	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2683	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2684	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2685	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2686	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2687	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2688	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2689	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2690	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2691	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2692	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2693	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2694	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2695
2696	/* RC only: */
2697	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2698	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2699	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2700	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2701
2702	/* RZ only: */
2703	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2704	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2705	STAMPROFILE StatRZTrap0eTimeSyncPT;
2706	STAMPROFILE StatRZTrap0eTimeMapping;
2707	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2708	STAMPROFILE StatRZTrap0eTimeHandlers;
2709	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2710	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2711	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2712	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2713	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2714	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2715	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2716	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2717	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2718	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2719	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2720	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2721	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2722	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2723	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2724	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2725	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2726	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2727	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2728	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2729	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2730	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2731	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2732	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2733	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2734	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2735	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2736	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2737	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2738	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2739	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2740	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2741	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2742	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2743	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2744	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2745	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2746	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2747	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2748	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2749	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2750	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2751	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2752
2753	/* HC - R3 and (maybe) R0: */
2754
2755	/* RZ & R3: */
2756	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2757	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2758	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2759	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2760	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2761	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2762	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2763	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2764	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2765	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2766	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2767	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2768	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2769	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2770	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2771	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2772	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2773	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2774	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2775	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2776	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2777	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2778	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2779	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2780	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2781	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2782	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2783	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2784	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2785	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2786	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2787	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2788	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2789	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2790	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2791	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2792	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2793	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2794	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2795	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2796	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2797	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2798	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2799	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2800	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2801	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2802	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2803	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2804	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2805	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2806	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2807	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2808	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2809	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2810
2811	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2812	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2813	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2814	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2815	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2816	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2817	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2818	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2819	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2820	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2821	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2822	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2823	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2824	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2825	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2826	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2827	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2828	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2829	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2830	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2831	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2832	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2833	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2834	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2835	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2836	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2837	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2838	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2839	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2840	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2841	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2842	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2843	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2844	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2845	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2846	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2847	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2848	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2849	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2850	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2851	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2852	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2853	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2854	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2855	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2856	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2857	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2858	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2859	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2860	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2861	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2862	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2863	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2864	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2865	#endif /* VBOX_WITH_STATISTICS */
2866	} PGM;
2867	/** Pointer to the PGM instance data. */
2868	typedef PGM *PPGM;
2869
2870
2871	/**
2872	* PGMCPU Data (part of VMCPU).
2873	*/
2874	typedef struct PGMCPU
2875	{
2876	/** Offset to the VMCPU structure. */
2877	RTINT offVMCPU;
2878	/** Automatically tracked physical memory mapping set.
2879	* Ring-0 and strict raw-mode builds. */
2880	PGMMAPSET AutoSet;
2881	} PGMCPU;
2882	/** Pointer to the per-cpu PGM data. */
2883	typedef PGMCPU *PPGMCPU;
2884
2885
2886	/** @name PGM::fSyncFlags Flags
2887	* @{
2888	*/
2889	/** Updates the virtual access handler state bit in PGMPAGE. */
2890	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2891	/** Always sync CR3. */
2892	#define PGM_SYNC_ALWAYS RT_BIT(1)
2893	/** Check monitoring on next CR3 (re)load and invalidate page. */
2894	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2895	/** Check guest mapping in SyncCR3. */
2896	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2897	/** Clear the page pool (a light weight flush). */
2898	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2899	/** @} */
2900
2901
2902	__BEGIN_DECLS
2903
2904	int pgmLock(PVM pVM);
2905	void pgmUnlock(PVM pVM);
2906
2907	VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2908	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2909
2910	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2911	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2912	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2913	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2914	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2915
2916	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2917	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2918	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2919	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2920	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2921	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2922	#else
2923	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2924	#endif
2925	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2926
2927
2928	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2929	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2930	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2931	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2932	#ifdef IN_RING3
2933	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2934	int pgmR3PhysRamReset(PVM pVM);
2935	int pgmR3PhysRomReset(PVM pVM);
2936	# ifndef VBOX_WITH_NEW_PHYS_CODE
2937	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2938	# endif
2939
2940	int pgmR3PoolInit(PVM pVM);
2941	void pgmR3PoolRelocate(PVM pVM);
2942	void pgmR3PoolReset(PVM pVM);
2943
2944	#endif /* IN_RING3 */
2945	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2946	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2947	#endif
2948	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2949	void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2950	#endif
2951	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2952	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2953	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2954	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2955	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2956	void pgmPoolFlushAll(PVM pVM);
2957	void pgmPoolClearAll(PVM pVM);
2958	int pgmPoolSyncCR3(PVM pVM);
2959	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2960	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2961	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2962	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2963	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2964	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2965	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2966	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2967	#ifdef PGMPOOL_WITH_MONITORING
2968	# ifdef IN_RING3
2969	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2970	# else
2971	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2972	# endif
2973	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2974	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2975	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2976	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2977	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2978	#endif
2979
2980	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2981	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
2982	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2983	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2984	#endif
2985
2986	__END_DECLS
2987
2988
2989	/**
2990	* Gets the PGMRAMRANGE structure for a guest page.
2991	*
2992	* @returns Pointer to the RAM range on success.
2993	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2994	*
2995	* @param pPGM PGM handle.
2996	* @param GCPhys The GC physical address.
2997	*/
2998	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2999	{
3000	/*
3001	* Optimize for the first range.
3002	*/
3003	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3004	RTGCPHYS off = GCPhys - pRam->GCPhys;
3005	if (RT_UNLIKELY(off >= pRam->cb))
3006	{
3007	do
3008	{
3009	pRam = pRam->CTX_SUFF(pNext);
3010	if (RT_UNLIKELY(!pRam))
3011	break;
3012	off = GCPhys - pRam->GCPhys;
3013	} while (off >= pRam->cb);
3014	}
3015	return pRam;
3016	}
3017
3018
3019	/**
3020	* Gets the PGMPAGE structure for a guest page.
3021	*
3022	* @returns Pointer to the page on success.
3023	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3024	*
3025	* @param pPGM PGM handle.
3026	* @param GCPhys The GC physical address.
3027	*/
3028	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3029	{
3030	/*
3031	* Optimize for the first range.
3032	*/
3033	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3034	RTGCPHYS off = GCPhys - pRam->GCPhys;
3035	if (RT_UNLIKELY(off >= pRam->cb))
3036	{
3037	do
3038	{
3039	pRam = pRam->CTX_SUFF(pNext);
3040	if (RT_UNLIKELY(!pRam))
3041	return NULL;
3042	off = GCPhys - pRam->GCPhys;
3043	} while (off >= pRam->cb);
3044	}
3045	return &pRam->aPages[off >> PAGE_SHIFT];
3046	}
3047
3048
3049	/**
3050	* Gets the PGMPAGE structure for a guest page.
3051	*
3052	* Old Phys code: Will make sure the page is present.
3053	*
3054	* @returns VBox status code.
3055	* @retval VINF_SUCCESS and a valid *ppPage on success.
3056	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3057	*
3058	* @param pPGM PGM handle.
3059	* @param GCPhys The GC physical address.
3060	* @param ppPage Where to store the page poitner on success.
3061	*/
3062	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3063	{
3064	/*
3065	* Optimize for the first range.
3066	*/
3067	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3068	RTGCPHYS off = GCPhys - pRam->GCPhys;
3069	if (RT_UNLIKELY(off >= pRam->cb))
3070	{
3071	do
3072	{
3073	pRam = pRam->CTX_SUFF(pNext);
3074	if (RT_UNLIKELY(!pRam))
3075	{
3076	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3077	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3078	}
3079	off = GCPhys - pRam->GCPhys;
3080	} while (off >= pRam->cb);
3081	}
3082	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3083	#ifndef VBOX_WITH_NEW_PHYS_CODE
3084
3085	/*
3086	* Make sure it's present.
3087	*/
3088	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3089	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3090	{
3091	#ifdef IN_RING3
3092	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3093	#else
3094	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3095	#endif
3096	if (RT_FAILURE(rc))
3097	{
3098	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3099	return rc;
3100	}
3101	Assert(rc == VINF_SUCCESS);
3102	}
3103	#endif
3104	return VINF_SUCCESS;
3105	}
3106
3107
3108
3109
3110	/**
3111	* Gets the PGMPAGE structure for a guest page.
3112	*
3113	* Old Phys code: Will make sure the page is present.
3114	*
3115	* @returns VBox status code.
3116	* @retval VINF_SUCCESS and a valid *ppPage on success.
3117	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3118	*
3119	* @param pPGM PGM handle.
3120	* @param GCPhys The GC physical address.
3121	* @param ppPage Where to store the page poitner on success.
3122	* @param ppRamHint Where to read and store the ram list hint.
3123	* The caller initializes this to NULL before the call.
3124	*/
3125	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3126	{
3127	RTGCPHYS off;
3128	PPGMRAMRANGE pRam = *ppRamHint;
3129	if ( !pRam
3130	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3131	{
3132	pRam = pPGM->CTX_SUFF(pRamRanges);
3133	off = GCPhys - pRam->GCPhys;
3134	if (RT_UNLIKELY(off >= pRam->cb))
3135	{
3136	do
3137	{
3138	pRam = pRam->CTX_SUFF(pNext);
3139	if (RT_UNLIKELY(!pRam))
3140	{
3141	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3142	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3143	}
3144	off = GCPhys - pRam->GCPhys;
3145	} while (off >= pRam->cb);
3146	}
3147	*ppRamHint = pRam;
3148	}
3149	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3150	#ifndef VBOX_WITH_NEW_PHYS_CODE
3151
3152	/*
3153	* Make sure it's present.
3154	*/
3155	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3156	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3157	{
3158	#ifdef IN_RING3
3159	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3160	#else
3161	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3162	#endif
3163	if (RT_FAILURE(rc))
3164	{
3165	ppPage = NULL; / Shut up annoying smart ass. */
3166	return rc;
3167	}
3168	Assert(rc == VINF_SUCCESS);
3169	}
3170	#endif
3171	return VINF_SUCCESS;
3172	}
3173
3174
3175	/**
3176	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3177	*
3178	* @returns Pointer to the page on success.
3179	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3180	*
3181	* @param pPGM PGM handle.
3182	* @param GCPhys The GC physical address.
3183	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3184	*/
3185	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3186	{
3187	/*
3188	* Optimize for the first range.
3189	*/
3190	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3191	RTGCPHYS off = GCPhys - pRam->GCPhys;
3192	if (RT_UNLIKELY(off >= pRam->cb))
3193	{
3194	do
3195	{
3196	pRam = pRam->CTX_SUFF(pNext);
3197	if (RT_UNLIKELY(!pRam))
3198	return NULL;
3199	off = GCPhys - pRam->GCPhys;
3200	} while (off >= pRam->cb);
3201	}
3202	*ppRam = pRam;
3203	return &pRam->aPages[off >> PAGE_SHIFT];
3204	}
3205
3206
3207	/**
3208	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3209	*
3210	* @returns Pointer to the page on success.
3211	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3212	*
3213	* @param pPGM PGM handle.
3214	* @param GCPhys The GC physical address.
3215	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3216	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3217	*/
3218	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3219	{
3220	/*
3221	* Optimize for the first range.
3222	*/
3223	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3224	RTGCPHYS off = GCPhys - pRam->GCPhys;
3225	if (RT_UNLIKELY(off >= pRam->cb))
3226	{
3227	do
3228	{
3229	pRam = pRam->CTX_SUFF(pNext);
3230	if (RT_UNLIKELY(!pRam))
3231	{
3232	ppRam = NULL; / Shut up silly GCC warnings. */
3233	ppPage = NULL; / ditto */
3234	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3235	}
3236	off = GCPhys - pRam->GCPhys;
3237	} while (off >= pRam->cb);
3238	}
3239	*ppRam = pRam;
3240	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3241	#ifndef VBOX_WITH_NEW_PHYS_CODE
3242
3243	/*
3244	* Make sure it's present.
3245	*/
3246	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3247	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3248	{
3249	#ifdef IN_RING3
3250	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3251	#else
3252	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3253	#endif
3254	if (RT_FAILURE(rc))
3255	{
3256	ppPage = NULL; / Shut up silly GCC warnings. */
3257	ppPage = NULL; / ditto */
3258	return rc;
3259	}
3260	Assert(rc == VINF_SUCCESS);
3261
3262	}
3263	#endif
3264	return VINF_SUCCESS;
3265	}
3266
3267
3268	/**
3269	* Convert GC Phys to HC Phys.
3270	*
3271	* @returns VBox status.
3272	* @param pPGM PGM handle.
3273	* @param GCPhys The GC physical address.
3274	* @param pHCPhys Where to store the corresponding HC physical address.
3275	*
3276	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3277	* Avoid when writing new code!
3278	*/
3279	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3280	{
3281	PPGMPAGE pPage;
3282	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3283	if (RT_FAILURE(rc))
3284	return rc;
3285	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3286	return VINF_SUCCESS;
3287	}
3288
3289	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3290
3291	/**
3292	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3293	* optimizes access to pages already in the set.
3294	*
3295	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3296	* @param pPGM Pointer to the PVM instance data.
3297	* @param HCPhys The physical address of the page.
3298	* @param ppv Where to store the mapping address.
3299	*/
3300	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3301	{
3302	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3303	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3304	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3305	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3306
3307	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3308	unsigned iEntry = pSet->aiHashTable[iHash];
3309	if ( iEntry < pSet->cEntries
3310	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3311	{
3312	*ppv = pSet->aEntries[iEntry].pvPage;
3313	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3314	}
3315	else
3316	{
3317	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3318	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3319	}
3320
3321	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3322	return VINF_SUCCESS;
3323	}
3324
3325
3326	/**
3327	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3328	* access to pages already in the set.
3329	*
3330	* @returns See PGMDynMapGCPage.
3331	* @param pPGM Pointer to the PVM instance data.
3332	* @param HCPhys The physical address of the page.
3333	* @param ppv Where to store the mapping address.
3334	*/
3335	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3336	{
3337	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3338	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3339
3340	/*
3341	* Get the ram range.
3342	*/
3343	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3344	RTGCPHYS off = GCPhys - pRam->GCPhys;
3345	if (RT_UNLIKELY(off >= pRam->cb
3346	/** @todo \|\| page state stuff */))
3347	{
3348	/* This case is not counted into StatR0DynMapGCPageInl. */
3349	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3350	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3351	}
3352
3353	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3354	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3355
3356	/*
3357	* pgmR0DynMapHCPageInlined with out stats.
3358	*/
3359	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3360	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3361	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3362
3363	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3364	unsigned iEntry = pSet->aiHashTable[iHash];
3365	if ( iEntry < pSet->cEntries
3366	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3367	{
3368	*ppv = pSet->aEntries[iEntry].pvPage;
3369	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3370	}
3371	else
3372	{
3373	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3374	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3375	}
3376
3377	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3378	return VINF_SUCCESS;
3379	}
3380
3381	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3382
3383	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3384	/**
3385	* Maps the page into current context (RC and maybe R0).
3386	*
3387	* @returns pointer to the mapping.
3388	* @param pVM Pointer to the PGM instance data.
3389	* @param pPage The page.
3390	*/
3391	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3392	{
3393	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3394	{
3395	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3396	void *pv;
3397	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3398	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3399	# else
3400	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3401	# endif
3402	return pv;
3403	}
3404	return pgmPoolMapPageFallback(pPGM, pPage);
3405	}
3406
3407	/**
3408	* Temporarily maps one host page specified by HC physical address, returning
3409	* pointer within the page.
3410	*
3411	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3412	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3413	*
3414	* @returns The address corresponding to HCPhys.
3415	* @param pPGM Pointer to the PVM instance data.
3416	* @param HCPhys HC Physical address of the page.
3417	*/
3418	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3419	{
3420	void *pv;
3421	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3422	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3423	# else
3424	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3425	# endif
3426	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3427	return pv;
3428	}
3429	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3430
3431
3432	#ifndef IN_RC
3433	/**
3434	* Queries the Physical TLB entry for a physical guest page,
3435	* attemting to load the TLB entry if necessary.
3436	*
3437	* @returns VBox status code.
3438	* @retval VINF_SUCCESS on success
3439	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3440	* @param pPGM The PGM instance handle.
3441	* @param GCPhys The address of the guest page.
3442	* @param ppTlbe Where to store the pointer to the TLB entry.
3443	*/
3444
3445	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3446	{
3447	int rc;
3448	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3449	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3450	{
3451	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3452	rc = VINF_SUCCESS;
3453	}
3454	else
3455	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3456	*ppTlbe = pTlbe;
3457	return rc;
3458	}
3459	#endif /* !IN_RC */
3460
3461	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3462
3463	# ifndef VBOX_WITH_NEW_PHYS_CODE
3464	/**
3465	* Convert GC Phys to HC Virt.
3466	*
3467	* @returns VBox status.
3468	* @param pPGM PGM handle.
3469	* @param GCPhys The GC physical address.
3470	* @param pHCPtr Where to store the corresponding HC virtual address.
3471	*
3472	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3473	* pgmPoolMonitorGCPtr2CCPtr.
3474	*/
3475	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3476	{
3477	PPGMRAMRANGE pRam;
3478	PPGMPAGE pPage;
3479	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3480	if (RT_FAILURE(rc))
3481	{
3482	pHCPtr = 0; / Shut up silly GCC warnings. */
3483	return rc;
3484	}
3485	RTGCPHYS off = GCPhys - pRam->GCPhys;
3486
3487	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3488	{
3489	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3490	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3491	return VINF_SUCCESS;
3492	}
3493	if (pRam->pvR3)
3494	{
3495	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3496	return VINF_SUCCESS;
3497	}
3498	pHCPtr = 0; / Shut up silly GCC warnings. */
3499	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3500	}
3501	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3502	#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3503
3504	/**
3505	* Convert GC Phys to HC Virt and HC Phys.
3506	*
3507	* @returns VBox status.
3508	* @param pPGM PGM handle.
3509	* @param GCPhys The GC physical address.
3510	* @param pHCPtr Where to store the corresponding HC virtual address.
3511	* @param pHCPhys Where to store the HC Physical address and its flags.
3512	*
3513	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3514	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3515	*/
3516	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3517	{
3518	PPGMRAMRANGE pRam;
3519	PPGMPAGE pPage;
3520	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3521	if (RT_FAILURE(rc))
3522	{
3523	pHCPtr = 0; / Shut up crappy GCC warnings */
3524	pHCPhys = 0; / ditto */
3525	return rc;
3526	}
3527	RTGCPHYS off = GCPhys - pRam->GCPhys;
3528
3529	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3530	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3531	{
3532	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3533	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3534	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3535	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3536	#else
3537	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3538	#endif
3539	return VINF_SUCCESS;
3540	}
3541	if (pRam->pvR3)
3542	{
3543	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3544	return VINF_SUCCESS;
3545	}
3546	*pHCPtr = 0;
3547	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3548	}
3549
3550
3551	/**
3552	* Clears flags associated with a RAM address.
3553	*
3554	* @returns VBox status code.
3555	* @param pPGM PGM handle.
3556	* @param GCPhys Guest context physical address.
3557	* @param fFlags fFlags to clear. (Bits 0-11.)
3558	*/
3559	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3560	{
3561	PPGMPAGE pPage;
3562	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3563	if (RT_FAILURE(rc))
3564	return rc;
3565
3566	fFlags &= ~X86_PTE_PAE_PG_MASK;
3567	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3568	return VINF_SUCCESS;
3569	}
3570
3571
3572	/**
3573	* Clears flags associated with a RAM address.
3574	*
3575	* @returns VBox status code.
3576	* @param pPGM PGM handle.
3577	* @param GCPhys Guest context physical address.
3578	* @param fFlags fFlags to clear. (Bits 0-11.)
3579	* @param ppRamHint Where to read and store the ram list hint.
3580	* The caller initializes this to NULL before the call.
3581	*/
3582	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3583	{
3584	PPGMPAGE pPage;
3585	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3586	if (RT_FAILURE(rc))
3587	return rc;
3588
3589	fFlags &= ~X86_PTE_PAE_PG_MASK;
3590	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3591	return VINF_SUCCESS;
3592	}
3593
3594
3595	/**
3596	* Sets (bitwise OR) flags associated with a RAM address.
3597	*
3598	* @returns VBox status code.
3599	* @param pPGM PGM handle.
3600	* @param GCPhys Guest context physical address.
3601	* @param fFlags fFlags to set clear. (Bits 0-11.)
3602	*/
3603	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3604	{
3605	PPGMPAGE pPage;
3606	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3607	if (RT_FAILURE(rc))
3608	return rc;
3609
3610	fFlags &= ~X86_PTE_PAE_PG_MASK;
3611	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3612	return VINF_SUCCESS;
3613	}
3614
3615
3616	/**
3617	* Sets (bitwise OR) flags associated with a RAM address.
3618	*
3619	* @returns VBox status code.
3620	* @param pPGM PGM handle.
3621	* @param GCPhys Guest context physical address.
3622	* @param fFlags fFlags to set clear. (Bits 0-11.)
3623	* @param ppRamHint Where to read and store the ram list hint.
3624	* The caller initializes this to NULL before the call.
3625	*/
3626	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3627	{
3628	PPGMPAGE pPage;
3629	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3630	if (RT_FAILURE(rc))
3631	return rc;
3632
3633	fFlags &= ~X86_PTE_PAE_PG_MASK;
3634	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3635	return VINF_SUCCESS;
3636	}
3637
3638
3639	/**
3640	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3641	* Takes PSE-36 into account.
3642	*
3643	* @returns guest physical address
3644	* @param pPGM Pointer to the PGM instance data.
3645	* @param Pde Guest Pde
3646	*/
3647	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3648	{
3649	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3650	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3651
3652	return GCPhys & pPGM->GCPhys4MBPSEMask;
3653	}
3654
3655
3656	/**
3657	* Gets the page directory entry for the specified address (32-bit paging).
3658	*
3659	* @returns The page directory entry in question.
3660	* @param pPGM Pointer to the PGM instance data.
3661	* @param GCPtr The address.
3662	*/
3663	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3664	{
3665	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3666	PCX86PD pGuestPD = 0;
3667	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3668	if (RT_FAILURE(rc))
3669	{
3670	X86PDE ZeroPde = {0};
3671	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3672	}
3673	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3674	#else
3675	return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3676	#endif
3677	}
3678
3679
3680	/**
3681	* Gets the address of a specific page directory entry (32-bit paging).
3682	*
3683	* @returns Pointer the page directory entry in question.
3684	* @param pPGM Pointer to the PGM instance data.
3685	* @param GCPtr The address.
3686	*/
3687	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3688	{
3689	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3690	PX86PD pGuestPD = 0;
3691	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3692	AssertRCReturn(rc, 0);
3693	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3694	#else
3695	return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3696	#endif
3697	}
3698
3699
3700	/**
3701	* Gets the address the guest page directory (32-bit paging).
3702	*
3703	* @returns Pointer the page directory entry in question.
3704	* @param pPGM Pointer to the PGM instance data.
3705	*/
3706	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3707	{
3708	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3709	PX86PD pGuestPD = 0;
3710	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3711	AssertRCReturn(rc, 0);
3712	return pGuestPD;
3713	#else
3714	return pPGM->CTX_SUFF(pGst32BitPd);
3715	#endif
3716	}
3717
3718
3719	/**
3720	* Gets the guest page directory pointer table.
3721	*
3722	* @returns Pointer to the page directory in question.
3723	* @returns NULL if the page directory is not present or on an invalid page.
3724	* @param pPGM Pointer to the PGM instance data.
3725	*/
3726	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3727	{
3728	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3729	PX86PDPT pGuestPDPT = 0;
3730	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3731	AssertRCReturn(rc, 0);
3732	return pGuestPDPT;
3733	#else
3734	return pPGM->CTX_SUFF(pGstPaePdpt);
3735	#endif
3736	}
3737
3738
3739	/**
3740	* Gets the guest page directory pointer table entry for the specified address.
3741	*
3742	* @returns Pointer to the page directory in question.
3743	* @returns NULL if the page directory is not present or on an invalid page.
3744	* @param pPGM Pointer to the PGM instance data.
3745	* @param GCPtr The address.
3746	*/
3747	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3748	{
3749	AssertGCPtr32(GCPtr);
3750
3751	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3752	PX86PDPT pGuestPDPT = 0;
3753	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3754	AssertRCReturn(rc, 0);
3755	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3756	#else
3757	return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3758	#endif
3759	}
3760
3761
3762	/**
3763	* Gets the page directory for the specified address.
3764	*
3765	* @returns Pointer to the page directory in question.
3766	* @returns NULL if the page directory is not present or on an invalid page.
3767	* @param pPGM Pointer to the PGM instance data.
3768	* @param GCPtr The address.
3769	*/
3770	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3771	{
3772	AssertGCPtr32(GCPtr);
3773
3774	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3775	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3776	AssertReturn(pGuestPDPT, 0);
3777	#else
3778	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3779	#endif
3780	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3781	if (pGuestPDPT->a[iPdPt].n.u1Present)
3782	{
3783	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3784	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3785	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3786	#endif
3787
3788	/* cache is out-of-sync. */
3789	PX86PDPAE pPD;
3790	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3791	if (RT_SUCCESS(rc))
3792	return pPD;
3793	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3794	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3795	}
3796	return NULL;
3797	}
3798
3799
3800	/**
3801	* Gets the page directory entry for the specified address.
3802	*
3803	* @returns Pointer to the page directory entry in question.
3804	* @returns NULL if the page directory is not present or on an invalid page.
3805	* @param pPGM Pointer to the PGM instance data.
3806	* @param GCPtr The address.
3807	*/
3808	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3809	{
3810	AssertGCPtr32(GCPtr);
3811
3812	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3813	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3814	AssertReturn(pGuestPDPT, 0);
3815	#else
3816	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3817	#endif
3818	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3819	if (pGuestPDPT->a[iPdPt].n.u1Present)
3820	{
3821	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3822	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3823	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3824	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3825	#endif
3826
3827	/* The cache is out-of-sync. */
3828	PX86PDPAE pPD;
3829	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3830	if (RT_SUCCESS(rc))
3831	return &pPD->a[iPD];
3832	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3833	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3834	}
3835	return NULL;
3836	}
3837
3838
3839	/**
3840	* Gets the page directory entry for the specified address.
3841	*
3842	* @returns The page directory entry in question.
3843	* @returns A non-present entry if the page directory is not present or on an invalid page.
3844	* @param pPGM Pointer to the PGM instance data.
3845	* @param GCPtr The address.
3846	*/
3847	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3848	{
3849	AssertGCPtr32(GCPtr);
3850
3851	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3852	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3853	if (RT_LIKELY(pGuestPDPT))
3854	#else
3855	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3856	#endif
3857	{
3858	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3859	if (pGuestPDPT->a[iPdPt].n.u1Present)
3860	{
3861	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3862	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3863	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3864	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3865	#endif
3866
3867	/* cache is out-of-sync. */
3868	PX86PDPAE pPD;
3869	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3870	if (RT_SUCCESS(rc))
3871	return pPD->a[iPD];
3872	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3873	}
3874	}
3875	X86PDEPAE ZeroPde = {0};
3876	return ZeroPde;
3877	}
3878
3879
3880	/**
3881	* Gets the page directory pointer table entry for the specified address
3882	* and returns the index into the page directory
3883	*
3884	* @returns Pointer to the page directory in question.
3885	* @returns NULL if the page directory is not present or on an invalid page.
3886	* @param pPGM Pointer to the PGM instance data.
3887	* @param GCPtr The address.
3888	* @param piPD Receives the index into the returned page directory
3889	* @param pPdpe Receives the page directory pointer entry. Optional.
3890	*/
3891	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3892	{
3893	AssertGCPtr32(GCPtr);
3894
3895	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3896	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3897	AssertReturn(pGuestPDPT, 0);
3898	#else
3899	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3900	#endif
3901	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3902	if (pPdpe)
3903	*pPdpe = pGuestPDPT->a[iPdPt];
3904	if (pGuestPDPT->a[iPdPt].n.u1Present)
3905	{
3906	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3907	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3908	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3909	{
3910	*piPD = iPD;
3911	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3912	}
3913	#endif
3914
3915	/* cache is out-of-sync. */
3916	PX86PDPAE pPD;
3917	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3918	if (RT_SUCCESS(rc))
3919	{
3920	*piPD = iPD;
3921	return pPD;
3922	}
3923	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3924	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3925	}
3926	return NULL;
3927	}
3928
3929	#ifndef IN_RC
3930
3931	/**
3932	* Gets the page map level-4 pointer for the guest.
3933	*
3934	* @returns Pointer to the PML4 page.
3935	* @param pPGM Pointer to the PGM instance data.
3936	*/
3937	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3938	{
3939	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3940	PX86PML4 pGuestPml4;
3941	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3942	AssertRCReturn(rc, NULL);
3943	return pGuestPml4;
3944	#else
3945	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3946	return pPGM->CTX_SUFF(pGstAmd64Pml4);
3947	#endif
3948	}
3949
3950
3951	/**
3952	* Gets the pointer to a page map level-4 entry.
3953	*
3954	* @returns Pointer to the PML4 entry.
3955	* @param pPGM Pointer to the PGM instance data.
3956	* @param iPml4 The index.
3957	*/
3958	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3959	{
3960	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3961	PX86PML4 pGuestPml4;
3962	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3963	AssertRCReturn(rc, NULL);
3964	return &pGuestPml4->a[iPml4];
3965	#else
3966	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3967	return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3968	#endif
3969	}
3970
3971
3972	/**
3973	* Gets a page map level-4 entry.
3974	*
3975	* @returns The PML4 entry.
3976	* @param pPGM Pointer to the PGM instance data.
3977	* @param iPml4 The index.
3978	*/
3979	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3980	{
3981	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3982	PX86PML4 pGuestPml4;
3983	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3984	if (RT_FAILURE(rc))
3985	{
3986	X86PML4E ZeroPml4e = {0};
3987	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3988	}
3989	return pGuestPml4->a[iPml4];
3990	#else
3991	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3992	return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3993	#endif
3994	}
3995
3996
3997	/**
3998	* Gets the page directory pointer entry for the specified address.
3999	*
4000	* @returns Pointer to the page directory pointer entry in question.
4001	* @returns NULL if the page directory is not present or on an invalid page.
4002	* @param pPGM Pointer to the PGM instance data.
4003	* @param GCPtr The address.
4004	* @param ppPml4e Page Map Level-4 Entry (out)
4005	*/
4006	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4007	{
4008	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4009	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4010	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4011	if (pPml4e->n.u1Present)
4012	{
4013	PX86PDPT pPdpt;
4014	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4015	AssertRCReturn(rc, NULL);
4016
4017	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4018	return &pPdpt->a[iPdPt];
4019	}
4020	return NULL;
4021	}
4022
4023
4024	/**
4025	* Gets the page directory entry for the specified address.
4026	*
4027	* @returns The page directory entry in question.
4028	* @returns A non-present entry if the page directory is not present or on an invalid page.
4029	* @param pPGM Pointer to the PGM instance data.
4030	* @param GCPtr The address.
4031	* @param ppPml4e Page Map Level-4 Entry (out)
4032	* @param pPdpe Page directory pointer table entry (out)
4033	*/
4034	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4035	{
4036	X86PDEPAE ZeroPde = {0};
4037	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4038	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4039	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4040	if (pPml4e->n.u1Present)
4041	{
4042	PCX86PDPT pPdptTemp;
4043	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4044	AssertRCReturn(rc, ZeroPde);
4045
4046	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4047	*pPdpe = pPdptTemp->a[iPdPt];
4048	if (pPdptTemp->a[iPdPt].n.u1Present)
4049	{
4050	PCX86PDPAE pPD;
4051	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4052	AssertRCReturn(rc, ZeroPde);
4053
4054	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4055	return pPD->a[iPD];
4056	}
4057	}
4058
4059	return ZeroPde;
4060	}
4061
4062
4063	/**
4064	* Gets the page directory entry for the specified address.
4065	*
4066	* @returns The page directory entry in question.
4067	* @returns A non-present entry if the page directory is not present or on an invalid page.
4068	* @param pPGM Pointer to the PGM instance data.
4069	* @param GCPtr The address.
4070	*/
4071	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4072	{
4073	X86PDEPAE ZeroPde = {0};
4074	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4075	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4076	if (pGuestPml4->a[iPml4].n.u1Present)
4077	{
4078	PCX86PDPT pPdptTemp;
4079	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4080	AssertRCReturn(rc, ZeroPde);
4081
4082	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4083	if (pPdptTemp->a[iPdPt].n.u1Present)
4084	{
4085	PCX86PDPAE pPD;
4086	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4087	AssertRCReturn(rc, ZeroPde);
4088
4089	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4090	return pPD->a[iPD];
4091	}
4092	}
4093	return ZeroPde;
4094	}
4095
4096
4097	/**
4098	* Gets the page directory entry for the specified address.
4099	*
4100	* @returns Pointer to the page directory entry in question.
4101	* @returns NULL if the page directory is not present or on an invalid page.
4102	* @param pPGM Pointer to the PGM instance data.
4103	* @param GCPtr The address.
4104	*/
4105	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4106	{
4107	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4108	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4109	if (pGuestPml4->a[iPml4].n.u1Present)
4110	{
4111	PCX86PDPT pPdptTemp;
4112	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4113	AssertRCReturn(rc, NULL);
4114
4115	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4116	if (pPdptTemp->a[iPdPt].n.u1Present)
4117	{
4118	PX86PDPAE pPD;
4119	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4120	AssertRCReturn(rc, NULL);
4121
4122	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4123	return &pPD->a[iPD];
4124	}
4125	}
4126	return NULL;
4127	}
4128
4129
4130	/**
4131	* Gets the GUEST page directory pointer for the specified address.
4132	*
4133	* @returns The page directory in question.
4134	* @returns NULL if the page directory is not present or on an invalid page.
4135	* @param pPGM Pointer to the PGM instance data.
4136	* @param GCPtr The address.
4137	* @param ppPml4e Page Map Level-4 Entry (out)
4138	* @param pPdpe Page directory pointer table entry (out)
4139	* @param piPD Receives the index into the returned page directory
4140	*/
4141	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4142	{
4143	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4144	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4145	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4146	if (pPml4e->n.u1Present)
4147	{
4148	PCX86PDPT pPdptTemp;
4149	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4150	AssertRCReturn(rc, NULL);
4151
4152	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4153	*pPdpe = pPdptTemp->a[iPdPt];
4154	if (pPdptTemp->a[iPdPt].n.u1Present)
4155	{
4156	PX86PDPAE pPD;
4157	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4158	AssertRCReturn(rc, NULL);
4159
4160	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4161	return pPD;
4162	}
4163	}
4164	return 0;
4165	}
4166
4167	#endif /* !IN_RC */
4168
4169
4170	/**
4171	* Gets the shadow page directory, 32-bit.
4172	*
4173	* @returns Pointer to the shadow 32-bit PD.
4174	* @param pPGM Pointer to the PGM instance data.
4175	*/
4176	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4177	{
4178	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4179	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4180	#else
4181	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4182	PX86PD pShwPd;
4183	Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4184	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4185	AssertRCReturn(rc, NULL);
4186	return pShwPd;
4187	# else
4188	return pPGM->CTX_SUFF(pShw32BitPd);
4189	# endif
4190	#endif
4191	}
4192
4193
4194	/**
4195	* Gets the shadow page directory entry for the specified address, 32-bit.
4196	*
4197	* @returns Shadow 32-bit PDE.
4198	* @param pPGM Pointer to the PGM instance data.
4199	* @param GCPtr The address.
4200	*/
4201	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4202	{
4203	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4204
4205	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4206	if (!pShwPde)
4207	{
4208	X86PDE ZeroPde = {0};
4209	return ZeroPde;
4210	}
4211	return pShwPde->a[iPd];
4212	}
4213
4214
4215	/**
4216	* Gets the pointer to the shadow page directory entry for the specified
4217	* address, 32-bit.
4218	*
4219	* @returns Pointer to the shadow 32-bit PDE.
4220	* @param pPGM Pointer to the PGM instance data.
4221	* @param GCPtr The address.
4222	*/
4223	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4224	{
4225	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4226
4227	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4228	AssertReturn(pPde, NULL);
4229	return &pPde->a[iPd];
4230	}
4231
4232
4233	/**
4234	* Gets the shadow page pointer table, PAE.
4235	*
4236	* @returns Pointer to the shadow PAE PDPT.
4237	* @param pPGM Pointer to the PGM instance data.
4238	*/
4239	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4240	{
4241	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4242	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4243	#else
4244	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4245	PX86PDPT pShwPdpt;
4246	Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4247	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4248	AssertRCReturn(rc, 0);
4249	return pShwPdpt;
4250	# else
4251	return pPGM->CTX_SUFF(pShwPaePdpt);
4252	# endif
4253	#endif
4254	}
4255
4256
4257	/**
4258	* Gets the shadow page directory for the specified address, PAE.
4259	*
4260	* @returns Pointer to the shadow PD.
4261	* @param pPGM Pointer to the PGM instance data.
4262	* @param GCPtr The address.
4263	*/
4264	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4265	{
4266	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4267	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4268	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4269
4270	if (!pPdpt->a[iPdpt].n.u1Present)
4271	return NULL;
4272
4273	/* Fetch the pgm pool shadow descriptor. */
4274	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4275	AssertReturn(pShwPde, NULL);
4276
4277	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4278	#else
4279	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4280	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4281	PX86PDPAE pPD;
4282	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4283	AssertRCReturn(rc, 0);
4284	return pPD;
4285	# else
4286	PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4287	Assert(pPD);
4288	return pPD;
4289	# endif
4290	#endif
4291	}
4292
4293	/**
4294	* Gets the shadow page directory for the specified address, PAE.
4295	*
4296	* @returns Pointer to the shadow PD.
4297	* @param pPGM Pointer to the PGM instance data.
4298	* @param GCPtr The address.
4299	*/
4300	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4301	{
4302	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4303	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4304
4305	if (!pPdpt->a[iPdpt].n.u1Present)
4306	return NULL;
4307
4308	/* Fetch the pgm pool shadow descriptor. */
4309	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4310	AssertReturn(pShwPde, NULL);
4311
4312	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4313	#else
4314	AssertFailed();
4315	return NULL;
4316	#endif
4317	}
4318
4319	/**
4320	* Gets the shadow page directory entry, PAE.
4321	*
4322	* @returns PDE.
4323	* @param pPGM Pointer to the PGM instance data.
4324	* @param GCPtr The address.
4325	*/
4326	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4327	{
4328	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4329
4330	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4331	if (!pShwPde)
4332	{
4333	X86PDEPAE ZeroPde = {0};
4334	return ZeroPde;
4335	}
4336	return pShwPde->a[iPd];
4337	}
4338
4339
4340	/**
4341	* Gets the pointer to the shadow page directory entry for an address, PAE.
4342	*
4343	* @returns Pointer to the PDE.
4344	* @param pPGM Pointer to the PGM instance data.
4345	* @param GCPtr The address.
4346	*/
4347	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4348	{
4349	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4350
4351	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4352	AssertReturn(pPde, NULL);
4353	return &pPde->a[iPd];
4354	}
4355
4356	#ifndef IN_RC
4357	/**
4358	* Gets the shadow page map level-4 pointer.
4359	*
4360	* @returns Pointer to the shadow PML4.
4361	* @param pPGM Pointer to the PGM instance data.
4362	*/
4363	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4364	{
4365	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4366	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4367	#else
4368	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4369	PX86PML4 pShwPml4;
4370	Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4371	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4372	AssertRCReturn(rc, 0);
4373	return pShwPml4;
4374	# else
4375	Assert(pPGM->CTX_SUFF(pShwRoot));
4376	return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4377	# endif
4378	#endif
4379	}
4380
4381
4382	/**
4383	* Gets the shadow page map level-4 entry for the specified address.
4384	*
4385	* @returns The entry.
4386	* @param pPGM Pointer to the PGM instance data.
4387	* @param GCPtr The address.
4388	*/
4389	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4390	{
4391	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4392	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4393
4394	if (!pShwPml4)
4395	{
4396	X86PML4E ZeroPml4e = {0};
4397	return ZeroPml4e;
4398	}
4399	return pShwPml4->a[iPml4];
4400	}
4401
4402
4403	/**
4404	* Gets the pointer to the specified shadow page map level-4 entry.
4405	*
4406	* @returns The entry.
4407	* @param pPGM Pointer to the PGM instance data.
4408	* @param iPml4 The PML4 index.
4409	*/
4410	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4411	{
4412	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4413	if (!pShwPml4)
4414	return NULL;
4415	return &pShwPml4->a[iPml4];
4416	}
4417
4418
4419	/**
4420	* Gets the GUEST page directory pointer for the specified address.
4421	*
4422	* @returns The page directory in question.
4423	* @returns NULL if the page directory is not present or on an invalid page.
4424	* @param pPGM Pointer to the PGM instance data.
4425	* @param GCPtr The address.
4426	* @param piPD Receives the index into the returned page directory
4427	*/
4428	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4429	{
4430	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4431	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4432	if (pGuestPml4->a[iPml4].n.u1Present)
4433	{
4434	PCX86PDPT pPdptTemp;
4435	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4436	AssertRCReturn(rc, NULL);
4437
4438	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4439	if (pPdptTemp->a[iPdPt].n.u1Present)
4440	{
4441	PX86PDPAE pPD;
4442	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4443	AssertRCReturn(rc, NULL);
4444
4445	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4446	return pPD;
4447	}
4448	}
4449	return NULL;
4450	}
4451
4452	#endif /* !IN_RC */
4453
4454	/**
4455	* Checks if any of the specified page flags are set for the given page.
4456	*
4457	* @returns true if any of the flags are set.
4458	* @returns false if all the flags are clear.
4459	* @param pPGM PGM handle.
4460	* @param GCPhys The GC physical address.
4461	* @param fFlags The flags to check for.
4462	*/
4463	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4464	{
4465	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4466	return pPage
4467	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4468	}
4469
4470
4471	/**
4472	* Gets the page state for a physical handler.
4473	*
4474	* @returns The physical handler page state.
4475	* @param pCur The physical handler in question.
4476	*/
4477	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4478	{
4479	switch (pCur->enmType)
4480	{
4481	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4482	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4483
4484	case PGMPHYSHANDLERTYPE_MMIO:
4485	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4486	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4487
4488	default:
4489	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4490	}
4491	}
4492
4493
4494	/**
4495	* Gets the page state for a virtual handler.
4496	*
4497	* @returns The virtual handler page state.
4498	* @param pCur The virtual handler in question.
4499	* @remarks This should never be used on a hypervisor access handler.
4500	*/
4501	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4502	{
4503	switch (pCur->enmType)
4504	{
4505	case PGMVIRTHANDLERTYPE_WRITE:
4506	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4507	case PGMVIRTHANDLERTYPE_ALL:
4508	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4509	default:
4510	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4511	}
4512	}
4513
4514
4515	/**
4516	* Clears one physical page of a virtual handler
4517	*
4518	* @param pPGM Pointer to the PGM instance.
4519	* @param pCur Virtual handler structure
4520	* @param iPage Physical page index
4521	*
4522	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4523	* need to care about other handlers in the same page.
4524	*/
4525	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4526	{
4527	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4528
4529	/*
4530	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4531	*/
4532	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4533	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4534	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4535	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4536	#endif
4537	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4538	{
4539	/* We're the head of the alias chain. */
4540	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4541	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4542	AssertReleaseMsg(pRemove != NULL,
4543	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4544	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4545	AssertReleaseMsg(pRemove == pPhys2Virt,
4546	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4547	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4548	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4549	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4550	#endif
4551	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4552	{
4553	/* Insert the next list in the alias chain into the tree. */
4554	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4555	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4556	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4557	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4558	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4559	#endif
4560	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4561	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4562	AssertRelease(fRc);
4563	}
4564	}
4565	else
4566	{
4567	/* Locate the previous node in the alias chain. */
4568	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4569	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4570	AssertReleaseMsg(pPrev != pPhys2Virt,
4571	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4572	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4573	#endif
4574	for (;;)
4575	{
4576	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4577	if (pNext == pPhys2Virt)
4578	{
4579	/* unlink. */
4580	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4581	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4582	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4583	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4584	else
4585	{
4586	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4587	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4588	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4589	}
4590	break;
4591	}
4592
4593	/* next */
4594	if (pNext == pPrev)
4595	{
4596	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4597	AssertReleaseMsg(pNext != pPrev,
4598	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4599	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4600	#endif
4601	break;
4602	}
4603	pPrev = pNext;
4604	}
4605	}
4606	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4607	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4608	pPhys2Virt->offNextAlias = 0;
4609	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4610
4611	/*
4612	* Clear the ram flags for this page.
4613	*/
4614	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4615	AssertReturnVoid(pPage);
4616	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4617	}
4618
4619
4620	/**
4621	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4622	*
4623	* @returns Pointer to the shadow page structure.
4624	* @param pPool The pool.
4625	* @param HCPhys The HC physical address of the shadow page.
4626	*/
4627	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4628	{
4629	/*
4630	* Look up the page.
4631	*/
4632	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4633	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4634	return pPage;
4635	}
4636
4637
4638	/**
4639	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4640	*
4641	* @returns Pointer to the shadow page structure.
4642	* @param pPool The pool.
4643	* @param idx The pool page index.
4644	*/
4645	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4646	{
4647	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4648	return &pPool->aPages[idx];
4649	}
4650
4651
4652	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4653	/**
4654	* Clear references to guest physical memory.
4655	*
4656	* @param pPool The pool.
4657	* @param pPoolPage The pool page.
4658	* @param pPhysPage The physical guest page tracking structure.
4659	*/
4660	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4661	{
4662	/*
4663	* Just deal with the simple case here.
4664	*/
4665	# ifdef LOG_ENABLED
4666	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4667	# endif
4668	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4669	if (cRefs == 1)
4670	{
4671	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4672	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4673	}
4674	else
4675	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4676	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4677	}
4678	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4679
4680
4681	#ifdef PGMPOOL_WITH_CACHE
4682	/**
4683	* Moves the page to the head of the age list.
4684	*
4685	* This is done when the cached page is used in one way or another.
4686	*
4687	* @param pPool The pool.
4688	* @param pPage The cached page.
4689	* @todo inline in PGMInternal.h!
4690	*/
4691	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4692	{
4693	/*
4694	* Move to the head of the age list.
4695	*/
4696	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4697	{
4698	/* unlink */
4699	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4700	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4701	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4702	else
4703	pPool->iAgeTail = pPage->iAgePrev;
4704
4705	/* insert at head */
4706	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4707	pPage->iAgeNext = pPool->iAgeHead;
4708	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4709	pPool->iAgeHead = pPage->idx;
4710	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4711	}
4712	}
4713	#endif /* PGMPOOL_WITH_CACHE */
4714
4715	/**
4716	* Tells if mappings are to be put into the shadow page table or not
4717	*
4718	* @returns boolean result
4719	* @param pVM VM handle.
4720	*/
4721
4722	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4723	{
4724	#ifdef IN_RING0
4725	/* There are no mappings in VT-x and AMD-V mode. */
4726	Assert(pPGM->fDisableMappings);
4727	return false;
4728	#else
4729	return !pPGM->fDisableMappings;
4730	#endif
4731	}
4732
4733	/** @} */
4734
4735	#endif
4736

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 16840

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