VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17177

Last change on this file since 17177 was 17140, checked in by vboxsync, 16 years ago

VBOX_WITH_PGMPOOL_PAGING_ONLY: compile fixes
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1/* $Id: PGMInternal.h 17140 2009-02-25 16:43:48Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59//#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** Mark a dynamic map entry (PGMDynMapHCPage) as locked. */
188#define PGM_PTFLAGS_DYN_LOCKED RT_BIT(9)
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGM
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page when in GC does nothing in HC.
333 *
334 * @param GCVirt The virtual address of the page to invalidate.
335 */
336#ifdef IN_RC
337# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
338#elif defined(IN_RING0)
339# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340#else
341# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
342#endif
343
344/** @def PGM_INVL_BIG_PG
345 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
346 *
347 * @param GCVirt The virtual address within the page directory to invalidate.
348 */
349#ifdef IN_RC
350# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
351#elif defined(IN_RING0)
352# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353#else
354# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
355#endif
356
357/** @def PGM_INVL_GUEST_TLBS()
358 * Invalidates all guest TLBs.
359 */
360#ifdef IN_RC
361# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
362#elif defined(IN_RING0)
363# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364#else
365# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
366#endif
367
368
369/**
370 * Structure for tracking GC Mappings.
371 *
372 * This structure is used by linked list in both GC and HC.
373 */
374typedef struct PGMMAPPING
375{
376 /** Pointer to next entry. */
377 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378 /** Pointer to next entry. */
379 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380 /** Pointer to next entry. */
381 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382 /** Indicate whether this entry is finalized. */
383 bool fFinalized;
384 /** Start Virtual address. */
385 RTGCPTR GCPtr;
386 /** Last Virtual address (inclusive). */
387 RTGCPTR GCPtrLast;
388 /** Range size (bytes). */
389 RTGCPTR cb;
390 /** Pointer to relocation callback function. */
391 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392 /** User argument to the callback. */
393 R3PTRTYPE(void *) pvUser;
394 /** Mapping description / name. For easing debugging. */
395 R3PTRTYPE(const char *) pszDesc;
396 /** Number of page tables. */
397 uint32_t cPTs;
398#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
399 uint32_t uPadding1; /**< Alignment padding. */
400#endif
401 /** Array of page table mapping data. Each entry
402 * describes one page table. The array can be longer
403 * than the declared length.
404 */
405 struct
406 {
407 /** The HC physical address of the page table. */
408 RTHCPHYS HCPhysPT;
409 /** The HC physical address of the first PAE page table. */
410 RTHCPHYS HCPhysPaePT0;
411 /** The HC physical address of the second PAE page table. */
412 RTHCPHYS HCPhysPaePT1;
413 /** The HC virtual address of the 32-bit page table. */
414 R3PTRTYPE(PX86PT) pPTR3;
415 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
416 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
417 /** The GC virtual address of the 32-bit page table. */
418 RCPTRTYPE(PX86PT) pPTRC;
419 /** The GC virtual address of the two PAE page table. */
420 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
421 /** The GC virtual address of the 32-bit page table. */
422 R0PTRTYPE(PX86PT) pPTR0;
423 /** The GC virtual address of the two PAE page table. */
424 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
425 } aPTs[1];
426} PGMMAPPING;
427/** Pointer to structure for tracking GC Mappings. */
428typedef struct PGMMAPPING *PPGMMAPPING;
429
430
431/**
432 * Physical page access handler structure.
433 *
434 * This is used to keep track of physical address ranges
435 * which are being monitored in some kind of way.
436 */
437typedef struct PGMPHYSHANDLER
438{
439 AVLROGCPHYSNODECORE Core;
440 /** Access type. */
441 PGMPHYSHANDLERTYPE enmType;
442 /** Number of pages to update. */
443 uint32_t cPages;
444 /** Pointer to R3 callback function. */
445 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
446 /** User argument for R3 handlers. */
447 R3PTRTYPE(void *) pvUserR3;
448 /** Pointer to R0 callback function. */
449 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
450 /** User argument for R0 handlers. */
451 R0PTRTYPE(void *) pvUserR0;
452 /** Pointer to GC callback function. */
453 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
454 /** User argument for RC handlers. */
455 RCPTRTYPE(void *) pvUserRC;
456 /** Description / Name. For easing debugging. */
457 R3PTRTYPE(const char *) pszDesc;
458#ifdef VBOX_WITH_STATISTICS
459 /** Profiling of this handler. */
460 STAMPROFILE Stat;
461#endif
462} PGMPHYSHANDLER;
463/** Pointer to a physical page access handler structure. */
464typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
465
466
467/**
468 * Cache node for the physical addresses covered by a virtual handler.
469 */
470typedef struct PGMPHYS2VIRTHANDLER
471{
472 /** Core node for the tree based on physical ranges. */
473 AVLROGCPHYSNODECORE Core;
474 /** Offset from this struct to the PGMVIRTHANDLER structure. */
475 int32_t offVirtHandler;
476 /** Offset of the next alias relative to this one.
477 * Bit 0 is used for indicating whether we're in the tree.
478 * Bit 1 is used for indicating that we're the head node.
479 */
480 int32_t offNextAlias;
481} PGMPHYS2VIRTHANDLER;
482/** Pointer to a phys to virtual handler structure. */
483typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
484
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the tree. */
487#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
488/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489 * node is in the head of an alias chain.
490 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
491#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
492/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
493#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
494
495
496/**
497 * Virtual page access handler structure.
498 *
499 * This is used to keep track of virtual address ranges
500 * which are being monitored in some kind of way.
501 */
502typedef struct PGMVIRTHANDLER
503{
504 /** Core node for the tree based on virtual ranges. */
505 AVLROGCPTRNODECORE Core;
506 /** Size of the range (in bytes). */
507 RTGCPTR cb;
508 /** Number of cache pages. */
509 uint32_t cPages;
510 /** Access type. */
511 PGMVIRTHANDLERTYPE enmType;
512 /** Pointer to the RC callback function. */
513 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
514#if HC_ARCH_BITS == 64
515 RTRCPTR padding;
516#endif
517 /** Pointer to the R3 callback function for invalidation. */
518 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
519 /** Pointer to the R3 callback function. */
520 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
521 /** Description / Name. For easing debugging. */
522 R3PTRTYPE(const char *) pszDesc;
523#ifdef VBOX_WITH_STATISTICS
524 /** Profiling of this handler. */
525 STAMPROFILE Stat;
526#endif
527 /** Array of cached physical addresses for the monitored ranged. */
528 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
529} PGMVIRTHANDLER;
530/** Pointer to a virtual page access handler structure. */
531typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
532
533
534/**
535 * Page type.
536 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
537 * @todo convert to \#defines.
538 */
539typedef enum PGMPAGETYPE
540{
541 /** The usual invalid zero entry. */
542 PGMPAGETYPE_INVALID = 0,
543 /** RAM page. (RWX) */
544 PGMPAGETYPE_RAM,
545 /** MMIO2 page. (RWX) */
546 PGMPAGETYPE_MMIO2,
547 /** Shadowed ROM. (RWX) */
548 PGMPAGETYPE_ROM_SHADOW,
549 /** ROM page. (R-X) */
550 PGMPAGETYPE_ROM,
551 /** MMIO page. (---) */
552 PGMPAGETYPE_MMIO,
553 /** End of valid entries. */
554 PGMPAGETYPE_END
555} PGMPAGETYPE;
556AssertCompile(PGMPAGETYPE_END < 7);
557
558/** @name Page type predicates.
559 * @{ */
560#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
561#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
562#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
563#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
565/** @} */
566
567
568/**
569 * A Physical Guest Page tracking structure.
570 *
571 * The format of this structure is complicated because we have to fit a lot
572 * of information into as few bits as possible. The format is also subject
573 * to change (there is one comming up soon). Which means that for we'll be
574 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
575 * accessess to the structure.
576 */
577typedef struct PGMPAGE
578{
579 /** The physical address and a whole lot of other stuff. All bits are used! */
580 RTHCPHYS HCPhys;
581 /** The page state. */
582 uint32_t u2StateX : 2;
583 /** Flag indicating that a write monitored page was written to when set. */
584 uint32_t fWrittenToX : 1;
585 /** For later. */
586 uint32_t fSomethingElse : 1;
587 /** The Page ID.
588 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
589 * The HCPhys will be 100% static. */
590 uint32_t idPageX : 28;
591 /** The page type (PGMPAGETYPE). */
592 uint32_t u3Type : 3;
593 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
594 uint32_t u2HandlerPhysStateX : 2;
595 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
596 uint32_t u2HandlerVirtStateX : 2;
597 uint32_t u29B : 25;
598} PGMPAGE;
599AssertCompileSize(PGMPAGE, 16);
600/** Pointer to a physical guest page. */
601typedef PGMPAGE *PPGMPAGE;
602/** Pointer to a const physical guest page. */
603typedef const PGMPAGE *PCPGMPAGE;
604/** Pointer to a physical guest page pointer. */
605typedef PPGMPAGE *PPPGMPAGE;
606
607
608/**
609 * Clears the page structure.
610 * @param pPage Pointer to the physical guest page tracking structure.
611 */
612#define PGM_PAGE_CLEAR(pPage) \
613 do { \
614 (pPage)->HCPhys = 0; \
615 (pPage)->u2StateX = 0; \
616 (pPage)->fWrittenToX = 0; \
617 (pPage)->fSomethingElse = 0; \
618 (pPage)->idPageX = 0; \
619 (pPage)->u3Type = 0; \
620 (pPage)->u29B = 0; \
621 } while (0)
622
623/**
624 * Initializes the page structure.
625 * @param pPage Pointer to the physical guest page tracking structure.
626 */
627#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
628 do { \
629 (pPage)->HCPhys = (_HCPhys); \
630 (pPage)->u2StateX = (_uState); \
631 (pPage)->fWrittenToX = 0; \
632 (pPage)->fSomethingElse = 0; \
633 (pPage)->idPageX = (_idPage); \
634 /*(pPage)->u3Type = (_uType); - later */ \
635 PGM_PAGE_SET_TYPE(pPage, _uType); \
636 (pPage)->u29B = 0; \
637 } while (0)
638
639/**
640 * Initializes the page structure of a ZERO page.
641 * @param pPage Pointer to the physical guest page tracking structure.
642 */
643#ifdef VBOX_WITH_NEW_PHYS_CODE
644# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
645 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
646#else
647# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
648 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649#endif
650/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
651# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
652 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
653
654
655/** @name The Page state, PGMPAGE::u2StateX.
656 * @{ */
657/** The zero page.
658 * This is a per-VM page that's never ever mapped writable. */
659#define PGM_PAGE_STATE_ZERO 0
660/** A allocated page.
661 * This is a per-VM page allocated from the page pool (or wherever
662 * we get MMIO2 pages from if the type is MMIO2).
663 */
664#define PGM_PAGE_STATE_ALLOCATED 1
665/** A allocated page that's being monitored for writes.
666 * The shadow page table mappings are read-only. When a write occurs, the
667 * fWrittenTo member is set, the page remapped as read-write and the state
668 * moved back to allocated. */
669#define PGM_PAGE_STATE_WRITE_MONITORED 2
670/** The page is shared, aka. copy-on-write.
671 * This is a page that's shared with other VMs. */
672#define PGM_PAGE_STATE_SHARED 3
673/** @} */
674
675
676/**
677 * Gets the page state.
678 * @returns page state (PGM_PAGE_STATE_*).
679 * @param pPage Pointer to the physical guest page tracking structure.
680 */
681#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
682
683/**
684 * Sets the page state.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 * @param _uState The new page state.
687 */
688#define PGM_PAGE_SET_STATE(pPage, _uState) \
689 do { (pPage)->u2StateX = (_uState); } while (0)
690
691
692/**
693 * Gets the host physical address of the guest page.
694 * @returns host physical address (RTHCPHYS).
695 * @param pPage Pointer to the physical guest page tracking structure.
696 */
697#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
698
699/**
700 * Sets the host physical address of the guest page.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 * @param _HCPhys The new host physical address.
703 */
704#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
705 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
706 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
707
708/**
709 * Get the Page ID.
710 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
711 * @param pPage Pointer to the physical guest page tracking structure.
712 */
713#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
714/* later:
715#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
716 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
717*/
718/**
719 * Sets the Page ID.
720 * @param pPage Pointer to the physical guest page tracking structure.
721 */
722#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
723/* later:
724#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
725 | ((_idPage) & 0xfff) \
726 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
727*/
728
729/**
730 * Get the Chunk ID.
731 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
732 * @param pPage Pointer to the physical guest page tracking structure.
733 */
734#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
735/* later:
736#if GMM_CHUNKID_SHIFT == 12
737# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
738#elif GMM_CHUNKID_SHIFT > 12
739# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
740#elif GMM_CHUNKID_SHIFT < 12
741# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
742 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
743#else
744# error "GMM_CHUNKID_SHIFT isn't defined or something."
745#endif
746*/
747
748/**
749 * Get the index of the page within the allocaiton chunk.
750 * @returns The page index.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
754/* later:
755#if GMM_CHUNKID_SHIFT <= 12
756# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
757#else
758# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
759 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
760#endif
761*/
762
763
764/**
765 * Gets the page type.
766 * @returns The page type.
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
770
771/**
772 * Sets the page type.
773 * @param pPage Pointer to the physical guest page tracking structure.
774 * @param _enmType The new page type (PGMPAGETYPE).
775 */
776#ifdef VBOX_WITH_NEW_PHYS_CODE
777#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
778 do { (pPage)->u3Type = (_enmType); } while (0)
779#else
780#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
781 do { \
782 (pPage)->u3Type = (_enmType); \
783 if ((_enmType) == PGMPAGETYPE_ROM) \
784 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
785 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
786 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
787 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
788 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
789 } while (0)
790#endif
791
792
793/**
794 * Checks if the page is 'reserved'.
795 * @returns true/false.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
799
800/**
801 * Checks if the page is marked for MMIO.
802 * @returns true/false.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
806
807/**
808 * Checks if the page is backed by the ZERO page.
809 * @returns true/false.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
813
814/**
815 * Checks if the page is backed by a SHARED page.
816 * @returns true/false.
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
820
821
822/**
823 * Marks the paget as written to (for GMM change monitoring).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
827
828/**
829 * Clears the written-to indicator.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 */
832#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
833
834/**
835 * Checks if the page was marked as written-to.
836 * @returns true/false.
837 * @param pPage Pointer to the physical guest page tracking structure.
838 */
839#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
840
841
842/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
843 *
844 * @remarks The values are assigned in order of priority, so we can calculate
845 * the correct state for a page with different handlers installed.
846 * @{ */
847/** No handler installed. */
848#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
849/** Monitoring is temporarily disabled. */
850#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
851/** Write access is monitored. */
852#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
853/** All access is monitored. */
854#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
855/** @} */
856
857/**
858 * Gets the physical access handler state of a page.
859 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
860 * @param pPage Pointer to the physical guest page tracking structure.
861 */
862#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
863
864/**
865 * Sets the physical access handler state of a page.
866 * @param pPage Pointer to the physical guest page tracking structure.
867 * @param _uState The new state value.
868 */
869#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
870 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
871
872/**
873 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
874 * @returns true/false
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
878
879/**
880 * Checks if the page has any active physical access handlers.
881 * @returns true/false
882 * @param pPage Pointer to the physical guest page tracking structure.
883 */
884#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
885
886
887/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
888 *
889 * @remarks The values are assigned in order of priority, so we can calculate
890 * the correct state for a page with different handlers installed.
891 * @{ */
892/** No handler installed. */
893#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
894/* 1 is reserved so the lineup is identical with the physical ones. */
895/** Write access is monitored. */
896#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
897/** All access is monitored. */
898#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
899/** @} */
900
901/**
902 * Gets the virtual access handler state of a page.
903 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
904 * @param pPage Pointer to the physical guest page tracking structure.
905 */
906#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
907
908/**
909 * Sets the virtual access handler state of a page.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 * @param _uState The new state value.
912 */
913#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
914 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
915
916/**
917 * Checks if the page has any virtual access handlers.
918 * @returns true/false
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
922
923/**
924 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
925 * virtual handlers.
926 * @returns true/false
927 * @param pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
930
931
932
933/**
934 * Checks if the page has any access handlers, including temporarily disabled ones.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
939 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
940 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
941
942/**
943 * Checks if the page has any active access handlers.
944 * @returns true/false
945 * @param pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
948 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
949 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
950
951/**
952 * Checks if the page has any active access handlers catching all accesses.
953 * @returns true/false
954 * @param pPage Pointer to the physical guest page tracking structure.
955 */
956#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
957 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
958 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
959
960
961/**
962 * Ram range for GC Phys to HC Phys conversion.
963 *
964 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
965 * conversions too, but we'll let MM handle that for now.
966 *
967 * This structure is used by linked lists in both GC and HC.
968 */
969typedef struct PGMRAMRANGE
970{
971 /** Pointer to the next RAM range - for R3. */
972 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
973 /** Pointer to the next RAM range - for R0. */
974 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
975 /** Pointer to the next RAM range - for RC. */
976 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
977 /** Pointer alignment. */
978 RTRCPTR RCPtrAlignment;
979 /** Start of the range. Page aligned. */
980 RTGCPHYS GCPhys;
981 /** Last address in the range (inclusive). Page aligned (-1). */
982 RTGCPHYS GCPhysLast;
983 /** Size of the range. (Page aligned of course). */
984 RTGCPHYS cb;
985 /** MM_RAM_* flags */
986 uint32_t fFlags;
987 uint32_t u32Alignment; /**< alignment. */
988#ifndef VBOX_WITH_NEW_PHYS_CODE
989 /** R3 virtual lookup ranges for chunks.
990 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
991 * @remarks This is occationally accessed from ring-0!! (not darwin) */
992# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
993 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
994# else
995 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
996# endif
997#endif
998 /** Start of the HC mapping of the range. This is only used for MMIO2. */
999 R3PTRTYPE(void *) pvR3;
1000 /** The range description. */
1001 R3PTRTYPE(const char *) pszDesc;
1002
1003 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1004#ifdef VBOX_WITH_NEW_PHYS_CODE
1005 uint32_t au32Reserved[2];
1006#elif HC_ARCH_BITS == 32
1007 uint32_t au32Reserved[1];
1008#endif
1009
1010 /** Array of physical guest page tracking structures. */
1011 PGMPAGE aPages[1];
1012} PGMRAMRANGE;
1013/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1014typedef PGMRAMRANGE *PPGMRAMRANGE;
1015
1016/** Return hc ptr corresponding to the ram range and physical offset */
1017#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1018 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1019 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1020
1021/**
1022 * Per page tracking structure for ROM image.
1023 *
1024 * A ROM image may have a shadow page, in which case we may have
1025 * two pages backing it. This structure contains the PGMPAGE for
1026 * both while PGMRAMRANGE have a copy of the active one. It is
1027 * important that these aren't out of sync in any regard other
1028 * than page pool tracking data.
1029 */
1030typedef struct PGMROMPAGE
1031{
1032 /** The page structure for the virgin ROM page. */
1033 PGMPAGE Virgin;
1034 /** The page structure for the shadow RAM page. */
1035 PGMPAGE Shadow;
1036 /** The current protection setting. */
1037 PGMROMPROT enmProt;
1038 /** Pad the structure size to a multiple of 8. */
1039 uint32_t u32Padding;
1040} PGMROMPAGE;
1041/** Pointer to a ROM page tracking structure. */
1042typedef PGMROMPAGE *PPGMROMPAGE;
1043
1044
1045/**
1046 * A registered ROM image.
1047 *
1048 * This is needed to keep track of ROM image since they generally
1049 * intrude into a PGMRAMRANGE. It also keeps track of additional
1050 * info like the two page sets (read-only virgin and read-write shadow),
1051 * the current state of each page.
1052 *
1053 * Because access handlers cannot easily be executed in a different
1054 * context, the ROM ranges needs to be accessible and in all contexts.
1055 */
1056typedef struct PGMROMRANGE
1057{
1058 /** Pointer to the next range - R3. */
1059 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1060 /** Pointer to the next range - R0. */
1061 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1062 /** Pointer to the next range - RC. */
1063 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1064 /** Pointer alignment */
1065 RTRCPTR GCPtrAlignment;
1066 /** Address of the range. */
1067 RTGCPHYS GCPhys;
1068 /** Address of the last byte in the range. */
1069 RTGCPHYS GCPhysLast;
1070 /** Size of the range. */
1071 RTGCPHYS cb;
1072 /** The flags (PGMPHYS_ROM_FLAG_*). */
1073 uint32_t fFlags;
1074 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1075 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1076 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1077 * This is used for strictness checks. */
1078 R3PTRTYPE(const void *) pvOriginal;
1079 /** The ROM description. */
1080 R3PTRTYPE(const char *) pszDesc;
1081 /** The per page tracking structures. */
1082 PGMROMPAGE aPages[1];
1083} PGMROMRANGE;
1084/** Pointer to a ROM range. */
1085typedef PGMROMRANGE *PPGMROMRANGE;
1086
1087
1088/**
1089 * A registered MMIO2 (= Device RAM) range.
1090 *
1091 * There are a few reason why we need to keep track of these
1092 * registrations. One of them is the deregistration & cleanup
1093 * stuff, while another is that the PGMRAMRANGE associated with
1094 * such a region may have to be removed from the ram range list.
1095 *
1096 * Overlapping with a RAM range has to be 100% or none at all. The
1097 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1098 * meditation will be raised if a partial overlap or an overlap of
1099 * ROM pages is encountered. On an overlap we will free all the
1100 * existing RAM pages and put in the ram range pages instead.
1101 */
1102typedef struct PGMMMIO2RANGE
1103{
1104 /** The owner of the range. (a device) */
1105 PPDMDEVINSR3 pDevInsR3;
1106 /** Pointer to the ring-3 mapping of the allocation. */
1107 RTR3PTR pvR3;
1108 /** Pointer to the next range - R3. */
1109 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1110 /** Whether it's mapped or not. */
1111 bool fMapped;
1112 /** Whether it's overlapping or not. */
1113 bool fOverlapping;
1114 /** The PCI region number.
1115 * @remarks This ASSUMES that nobody will ever really need to have multiple
1116 * PCI devices with matching MMIO region numbers on a single device. */
1117 uint8_t iRegion;
1118 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1119 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1120 /** The associated RAM range. */
1121 PGMRAMRANGE RamRange;
1122} PGMMMIO2RANGE;
1123/** Pointer to a MMIO2 range. */
1124typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1125
1126
1127
1128
1129/**
1130 * PGMPhysRead/Write cache entry
1131 */
1132typedef struct PGMPHYSCACHEENTRY
1133{
1134 /** R3 pointer to physical page. */
1135 R3PTRTYPE(uint8_t *) pbR3;
1136 /** GC Physical address for cache entry */
1137 RTGCPHYS GCPhys;
1138#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1139 RTGCPHYS u32Padding0; /**< alignment padding. */
1140#endif
1141} PGMPHYSCACHEENTRY;
1142
1143/**
1144 * PGMPhysRead/Write cache to reduce REM memory access overhead
1145 */
1146typedef struct PGMPHYSCACHE
1147{
1148 /** Bitmap of valid cache entries */
1149 uint64_t aEntries;
1150 /** Cache entries */
1151 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1152} PGMPHYSCACHE;
1153
1154
1155/** Pointer to an allocation chunk ring-3 mapping. */
1156typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1157/** Pointer to an allocation chunk ring-3 mapping pointer. */
1158typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1159
1160/**
1161 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1162 *
1163 * The primary tree (Core) uses the chunk id as key.
1164 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1165 */
1166typedef struct PGMCHUNKR3MAP
1167{
1168 /** The key is the chunk id. */
1169 AVLU32NODECORE Core;
1170 /** The key is the ageing sequence number. */
1171 AVLLU32NODECORE AgeCore;
1172 /** The current age thingy. */
1173 uint32_t iAge;
1174 /** The current reference count. */
1175 uint32_t volatile cRefs;
1176 /** The current permanent reference count. */
1177 uint32_t volatile cPermRefs;
1178 /** The mapping address. */
1179 void *pv;
1180} PGMCHUNKR3MAP;
1181
1182/**
1183 * Allocation chunk ring-3 mapping TLB entry.
1184 */
1185typedef struct PGMCHUNKR3MAPTLBE
1186{
1187 /** The chunk id. */
1188 uint32_t volatile idChunk;
1189#if HC_ARCH_BITS == 64
1190 uint32_t u32Padding; /**< alignment padding. */
1191#endif
1192 /** The chunk map. */
1193#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1194 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1195#else
1196 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1197#endif
1198} PGMCHUNKR3MAPTLBE;
1199/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1200typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1201
1202/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1203 * @remark Must be a power of two value. */
1204#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1205
1206/**
1207 * Allocation chunk ring-3 mapping TLB.
1208 *
1209 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1210 * At first glance this might look kinda odd since AVL trees are
1211 * supposed to give the most optimial lookup times of all trees
1212 * due to their balancing. However, take a tree with 1023 nodes
1213 * in it, that's 10 levels, meaning that most searches has to go
1214 * down 9 levels before they find what they want. This isn't fast
1215 * compared to a TLB hit. There is the factor of cache misses,
1216 * and of course the problem with trees and branch prediction.
1217 * This is why we use TLBs in front of most of the trees.
1218 *
1219 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1220 * difficult when we switch to the new inlined AVL trees (from kStuff).
1221 */
1222typedef struct PGMCHUNKR3MAPTLB
1223{
1224 /** The TLB entries. */
1225 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1226} PGMCHUNKR3MAPTLB;
1227
1228/**
1229 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1230 * @returns Chunk TLB index.
1231 * @param idChunk The Chunk ID.
1232 */
1233#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1234
1235
1236/**
1237 * Ring-3 guest page mapping TLB entry.
1238 * @remarks used in ring-0 as well at the moment.
1239 */
1240typedef struct PGMPAGER3MAPTLBE
1241{
1242 /** Address of the page. */
1243 RTGCPHYS volatile GCPhys;
1244 /** The guest page. */
1245#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1246 R3PTRTYPE(PPGMPAGE) volatile pPage;
1247#else
1248 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1249#endif
1250 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1251#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1252 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1253#else
1254 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1255#endif
1256 /** The address */
1257#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1258 R3PTRTYPE(void *) volatile pv;
1259#else
1260 R3R0PTRTYPE(void *) volatile pv;
1261#endif
1262#if HC_ARCH_BITS == 32
1263 uint32_t u32Padding; /**< alignment padding. */
1264#endif
1265} PGMPAGER3MAPTLBE;
1266/** Pointer to an entry in the HC physical TLB. */
1267typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1268
1269
1270/** The number of entries in the ring-3 guest page mapping TLB.
1271 * @remarks The value must be a power of two. */
1272#define PGM_PAGER3MAPTLB_ENTRIES 64
1273
1274/**
1275 * Ring-3 guest page mapping TLB.
1276 * @remarks used in ring-0 as well at the moment.
1277 */
1278typedef struct PGMPAGER3MAPTLB
1279{
1280 /** The TLB entries. */
1281 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1282} PGMPAGER3MAPTLB;
1283/** Pointer to the ring-3 guest page mapping TLB. */
1284typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1285
1286/**
1287 * Calculates the index of the TLB entry for the specified guest page.
1288 * @returns Physical TLB index.
1289 * @param GCPhys The guest physical address.
1290 */
1291#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1292
1293
1294/**
1295 * Mapping cache usage set entry.
1296 *
1297 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1298 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1299 * cache. If it's extended to include ring-3, well, then something will
1300 * have be changed here...
1301 */
1302typedef struct PGMMAPSETENTRY
1303{
1304 /** The mapping cache index. */
1305 uint16_t iPage;
1306 /** The number of references.
1307 * The max is UINT16_MAX - 1. */
1308 uint16_t cRefs;
1309 /** Pointer to the page. */
1310 RTR0PTR pvPage;
1311 /** The physical address for this entry. */
1312 RTHCPHYS HCPhys;
1313} PGMMAPSETENTRY;
1314/** Pointer to a mapping cache usage set entry. */
1315typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1316
1317/**
1318 * Mapping cache usage set.
1319 *
1320 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1321 * done during exits / traps. The set is
1322 */
1323typedef struct PGMMAPSET
1324{
1325 /** The number of occupied entries.
1326 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1327 * dynamic mappings. */
1328 uint32_t cEntries;
1329 /** The start of the current subset.
1330 * This is UINT32_MAX if no subset is currently open. */
1331 uint32_t iSubset;
1332 /** The index of the current CPU, only valid if the set is open. */
1333 int32_t iCpu;
1334 /** The entries. */
1335 PGMMAPSETENTRY aEntries[64];
1336 /** HCPhys -> iEntry fast lookup table.
1337 * Use PGMMAPSET_HASH for hashing.
1338 * The entries may or may not be valid, check against cEntries. */
1339 uint8_t aiHashTable[128];
1340} PGMMAPSET;
1341/** Pointer to the mapping cache set. */
1342typedef PGMMAPSET *PPGMMAPSET;
1343
1344/** PGMMAPSET::cEntries value for a closed set. */
1345#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1346
1347/** Hash function for aiHashTable. */
1348#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1349
1350/** The max fill size (strict builds). */
1351#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1352
1353
1354/** @name Context neutrual page mapper TLB.
1355 *
1356 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1357 * code is writting in a kind of context neutrual way. Time will show whether
1358 * this actually makes sense or not...
1359 *
1360 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1361 * context ends up using a global mapping cache on some platforms
1362 * (darwin).
1363 *
1364 * @{ */
1365/** @typedef PPGMPAGEMAPTLB
1366 * The page mapper TLB pointer type for the current context. */
1367/** @typedef PPGMPAGEMAPTLB
1368 * The page mapper TLB entry pointer type for the current context. */
1369/** @typedef PPGMPAGEMAPTLB
1370 * The page mapper TLB entry pointer pointer type for the current context. */
1371/** @def PGM_PAGEMAPTLB_ENTRIES
1372 * The number of TLB entries in the page mapper TLB for the current context. */
1373/** @def PGM_PAGEMAPTLB_IDX
1374 * Calculate the TLB index for a guest physical address.
1375 * @returns The TLB index.
1376 * @param GCPhys The guest physical address. */
1377/** @typedef PPGMPAGEMAP
1378 * Pointer to a page mapper unit for current context. */
1379/** @typedef PPPGMPAGEMAP
1380 * Pointer to a page mapper unit pointer for current context. */
1381#ifdef IN_RC
1382// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1383// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1384// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1385# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1386# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1387 typedef void * PPGMPAGEMAP;
1388 typedef void ** PPPGMPAGEMAP;
1389//#elif IN_RING0
1390// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1391// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1392// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1393//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1394//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1395// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1396// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1397#else
1398 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1399 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1400 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1401# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1402# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1403 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1404 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1405#endif
1406/** @} */
1407
1408
1409/** @name PGM Pool Indexes.
1410 * Aka. the unique shadow page identifier.
1411 * @{ */
1412/** NIL page pool IDX. */
1413#define NIL_PGMPOOL_IDX 0
1414/** The first normal index. */
1415#define PGMPOOL_IDX_FIRST_SPECIAL 1
1416#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1417/** Page directory (32-bit root). */
1418#define PGMPOOL_IDX_PD 1
1419/** Page Directory Pointer Table (PAE root). */
1420#define PGMPOOL_IDX_PDPT 2
1421/** AMD64 CR3 level index.*/
1422#define PGMPOOL_IDX_AMD64_CR3 3
1423/** Nested paging root.*/
1424#define PGMPOOL_IDX_NESTED_ROOT 4
1425/** The first normal index. */
1426#define PGMPOOL_IDX_FIRST 5
1427#else
1428/** Page directory (32-bit root). */
1429#define PGMPOOL_IDX_PD 1
1430/** The extended PAE page directory (2048 entries, works as root currently). */
1431#define PGMPOOL_IDX_PAE_PD 2
1432/** PAE Page Directory Table 0. */
1433#define PGMPOOL_IDX_PAE_PD_0 3
1434/** PAE Page Directory Table 1. */
1435#define PGMPOOL_IDX_PAE_PD_1 4
1436/** PAE Page Directory Table 2. */
1437#define PGMPOOL_IDX_PAE_PD_2 5
1438/** PAE Page Directory Table 3. */
1439#define PGMPOOL_IDX_PAE_PD_3 6
1440/** Page Directory Pointer Table (PAE root, not currently used). */
1441#define PGMPOOL_IDX_PDPT 7
1442/** AMD64 CR3 level index.*/
1443#define PGMPOOL_IDX_AMD64_CR3 8
1444/** Nested paging root.*/
1445#define PGMPOOL_IDX_NESTED_ROOT 9
1446/** The first normal index. */
1447#define PGMPOOL_IDX_FIRST 10
1448#endif
1449/** The last valid index. (inclusive, 14 bits) */
1450#define PGMPOOL_IDX_LAST 0x3fff
1451/** @} */
1452
1453/** The NIL index for the parent chain. */
1454#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1455
1456/**
1457 * Node in the chain linking a shadowed page to it's parent (user).
1458 */
1459#pragma pack(1)
1460typedef struct PGMPOOLUSER
1461{
1462 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1463 uint16_t iNext;
1464 /** The user page index. */
1465 uint16_t iUser;
1466 /** Index into the user table. */
1467 uint32_t iUserTable;
1468} PGMPOOLUSER, *PPGMPOOLUSER;
1469typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1470#pragma pack()
1471
1472
1473/** The NIL index for the phys ext chain. */
1474#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1475
1476/**
1477 * Node in the chain of physical cross reference extents.
1478 */
1479#pragma pack(1)
1480typedef struct PGMPOOLPHYSEXT
1481{
1482 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1483 uint16_t iNext;
1484 /** The user page index. */
1485 uint16_t aidx[3];
1486} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1487typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1488#pragma pack()
1489
1490
1491/**
1492 * The kind of page that's being shadowed.
1493 */
1494typedef enum PGMPOOLKIND
1495{
1496 /** The virtual invalid 0 entry. */
1497 PGMPOOLKIND_INVALID = 0,
1498 /** The entry is free (=unused). */
1499 PGMPOOLKIND_FREE,
1500
1501 /** Shw: 32-bit page table; Gst: no paging */
1502 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1503 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1504 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1505 /** Shw: 32-bit page table; Gst: 4MB page. */
1506 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1507 /** Shw: PAE page table; Gst: no paging */
1508 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1509 /** Shw: PAE page table; Gst: 32-bit page table. */
1510 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1511 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1512 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1513 /** Shw: PAE page table; Gst: PAE page table. */
1514 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1515 /** Shw: PAE page table; Gst: 2MB page. */
1516 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1517
1518 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1519 PGMPOOLKIND_32BIT_PD,
1520 /** Shw: 32-bit page directory. Gst: no paging. */
1521 PGMPOOLKIND_32BIT_PD_PHYS,
1522 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1523 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1524 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1525 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1526 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1527 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1528 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1529 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1530 /** Shw: PAE page directory; Gst: PAE page directory. */
1531 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1532 /** Shw: PAE page directory; Gst: no paging. */
1533 PGMPOOLKIND_PAE_PD_PHYS,
1534
1535 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1536 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1537 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1538 PGMPOOLKIND_PAE_PDPT,
1539 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1540 PGMPOOLKIND_PAE_PDPT_PHYS,
1541
1542 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1543 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1544 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1545 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1546 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1547 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1548 /** Shw: 64-bit page directory table; Gst: no paging */
1549 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1550
1551 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1552 PGMPOOLKIND_64BIT_PML4,
1553
1554 /** Shw: EPT page directory pointer table; Gst: no paging */
1555 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1556 /** Shw: EPT page directory table; Gst: no paging */
1557 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1558 /** Shw: EPT page table; Gst: no paging */
1559 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1560
1561#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1562 /** Shw: Root 32-bit page directory. */
1563 PGMPOOLKIND_ROOT_32BIT_PD,
1564 /** Shw: Root PAE page directory */
1565 PGMPOOLKIND_ROOT_PAE_PD,
1566 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1567 PGMPOOLKIND_ROOT_PDPT,
1568#endif
1569 /** Shw: Root Nested paging table. */
1570 PGMPOOLKIND_ROOT_NESTED,
1571
1572 /** The last valid entry. */
1573 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1574} PGMPOOLKIND;
1575
1576
1577/**
1578 * The tracking data for a page in the pool.
1579 */
1580typedef struct PGMPOOLPAGE
1581{
1582 /** AVL node code with the (R3) physical address of this page. */
1583 AVLOHCPHYSNODECORE Core;
1584 /** Pointer to the R3 mapping of the page. */
1585#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1586 R3PTRTYPE(void *) pvPageR3;
1587#else
1588 R3R0PTRTYPE(void *) pvPageR3;
1589#endif
1590 /** The guest physical address. */
1591#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1592 uint32_t Alignment0;
1593#endif
1594 RTGCPHYS GCPhys;
1595 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1596 uint8_t enmKind;
1597 uint8_t bPadding;
1598 /** The index of this page. */
1599 uint16_t idx;
1600 /** The next entry in the list this page currently resides in.
1601 * It's either in the free list or in the GCPhys hash. */
1602 uint16_t iNext;
1603#ifdef PGMPOOL_WITH_USER_TRACKING
1604 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1605 uint16_t iUserHead;
1606 /** The number of present entries. */
1607 uint16_t cPresent;
1608 /** The first entry in the table which is present. */
1609 uint16_t iFirstPresent;
1610#endif
1611#ifdef PGMPOOL_WITH_MONITORING
1612 /** The number of modifications to the monitored page. */
1613 uint16_t cModifications;
1614 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1615 uint16_t iModifiedNext;
1616 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1617 uint16_t iModifiedPrev;
1618 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1619 uint16_t iMonitoredNext;
1620 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1621 uint16_t iMonitoredPrev;
1622#endif
1623#ifdef PGMPOOL_WITH_CACHE
1624 /** The next page in the age list. */
1625 uint16_t iAgeNext;
1626 /** The previous page in the age list. */
1627 uint16_t iAgePrev;
1628#endif /* PGMPOOL_WITH_CACHE */
1629 /** Used to indicate that the page is zeroed. */
1630 bool fZeroed;
1631 /** Used to indicate that a PT has non-global entries. */
1632 bool fSeenNonGlobal;
1633 /** Used to indicate that we're monitoring writes to the guest page. */
1634 bool fMonitored;
1635 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1636 * (All pages are in the age list.) */
1637 bool fCached;
1638 /** This is used by the R3 access handlers when invoked by an async thread.
1639 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1640 bool volatile fReusedFlushPending;
1641#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1642 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1643 bool fLocked;
1644#else
1645 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1646 * In these cases the access handler acts differently and will check
1647 * for mapping conflicts like the normal CR3 handler.
1648 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1649 * replaced by a list of pages which share access handler.
1650 */
1651 bool fCR3Mix;
1652#endif
1653} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1654
1655
1656#ifdef PGMPOOL_WITH_CACHE
1657/** The hash table size. */
1658# define PGMPOOL_HASH_SIZE 0x40
1659/** The hash function. */
1660# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1661#endif
1662
1663
1664/**
1665 * The shadow page pool instance data.
1666 *
1667 * It's all one big allocation made at init time, except for the
1668 * pages that is. The user nodes follows immediatly after the
1669 * page structures.
1670 */
1671typedef struct PGMPOOL
1672{
1673 /** The VM handle - R3 Ptr. */
1674 PVMR3 pVMR3;
1675 /** The VM handle - R0 Ptr. */
1676 PVMR0 pVMR0;
1677 /** The VM handle - RC Ptr. */
1678 PVMRC pVMRC;
1679 /** The max pool size. This includes the special IDs. */
1680 uint16_t cMaxPages;
1681 /** The current pool size. */
1682 uint16_t cCurPages;
1683 /** The head of the free page list. */
1684 uint16_t iFreeHead;
1685 /* Padding. */
1686 uint16_t u16Padding;
1687#ifdef PGMPOOL_WITH_USER_TRACKING
1688 /** Head of the chain of free user nodes. */
1689 uint16_t iUserFreeHead;
1690 /** The number of user nodes we've allocated. */
1691 uint16_t cMaxUsers;
1692 /** The number of present page table entries in the entire pool. */
1693 uint32_t cPresent;
1694 /** Pointer to the array of user nodes - RC pointer. */
1695 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1696 /** Pointer to the array of user nodes - R3 pointer. */
1697 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1698 /** Pointer to the array of user nodes - R0 pointer. */
1699 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1700#endif /* PGMPOOL_WITH_USER_TRACKING */
1701#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1702 /** Head of the chain of free phys ext nodes. */
1703 uint16_t iPhysExtFreeHead;
1704 /** The number of user nodes we've allocated. */
1705 uint16_t cMaxPhysExts;
1706 /** Pointer to the array of physical xref extent - RC pointer. */
1707 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1708 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1709 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1710 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1711 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1712#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1713#ifdef PGMPOOL_WITH_CACHE
1714 /** Hash table for GCPhys addresses. */
1715 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1716 /** The head of the age list. */
1717 uint16_t iAgeHead;
1718 /** The tail of the age list. */
1719 uint16_t iAgeTail;
1720 /** Set if the cache is enabled. */
1721 bool fCacheEnabled;
1722#endif /* PGMPOOL_WITH_CACHE */
1723#ifdef PGMPOOL_WITH_MONITORING
1724 /** Head of the list of modified pages. */
1725 uint16_t iModifiedHead;
1726 /** The current number of modified pages. */
1727 uint16_t cModifiedPages;
1728 /** Access handler, RC. */
1729 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1730 /** Access handler, R0. */
1731 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1732 /** Access handler, R3. */
1733 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1734 /** The access handler description (HC ptr). */
1735 R3PTRTYPE(const char *) pszAccessHandler;
1736#endif /* PGMPOOL_WITH_MONITORING */
1737 /** The number of pages currently in use. */
1738 uint16_t cUsedPages;
1739#ifdef VBOX_WITH_STATISTICS
1740 /** The high wather mark for cUsedPages. */
1741 uint16_t cUsedPagesHigh;
1742 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1743 /** Profiling pgmPoolAlloc(). */
1744 STAMPROFILEADV StatAlloc;
1745 /** Profiling pgmPoolClearAll(). */
1746 STAMPROFILE StatClearAll;
1747 /** Profiling pgmPoolFlushAllInt(). */
1748 STAMPROFILE StatFlushAllInt;
1749 /** Profiling pgmPoolFlushPage(). */
1750 STAMPROFILE StatFlushPage;
1751 /** Profiling pgmPoolFree(). */
1752 STAMPROFILE StatFree;
1753 /** Profiling time spent zeroing pages. */
1754 STAMPROFILE StatZeroPage;
1755# ifdef PGMPOOL_WITH_USER_TRACKING
1756 /** Profiling of pgmPoolTrackDeref. */
1757 STAMPROFILE StatTrackDeref;
1758 /** Profiling pgmTrackFlushGCPhysPT. */
1759 STAMPROFILE StatTrackFlushGCPhysPT;
1760 /** Profiling pgmTrackFlushGCPhysPTs. */
1761 STAMPROFILE StatTrackFlushGCPhysPTs;
1762 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1763 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1764 /** Number of times we've been out of user records. */
1765 STAMCOUNTER StatTrackFreeUpOneUser;
1766# endif
1767# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1768 /** Profiling deref activity related tracking GC physical pages. */
1769 STAMPROFILE StatTrackDerefGCPhys;
1770 /** Number of linear searches for a HCPhys in the ram ranges. */
1771 STAMCOUNTER StatTrackLinearRamSearches;
1772 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1773 STAMCOUNTER StamTrackPhysExtAllocFailures;
1774# endif
1775# ifdef PGMPOOL_WITH_MONITORING
1776 /** Profiling the RC/R0 access handler. */
1777 STAMPROFILE StatMonitorRZ;
1778 /** Times we've failed interpreting the instruction. */
1779 STAMCOUNTER StatMonitorRZEmulateInstr;
1780 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1781 STAMPROFILE StatMonitorRZFlushPage;
1782 /** Times we've detected fork(). */
1783 STAMCOUNTER StatMonitorRZFork;
1784 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1785 STAMPROFILE StatMonitorRZHandled;
1786 /** Times we've failed interpreting a patch code instruction. */
1787 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1788 /** Times we've failed interpreting a patch code instruction during flushing. */
1789 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1790 /** The number of times we've seen rep prefixes we can't handle. */
1791 STAMCOUNTER StatMonitorRZRepPrefix;
1792 /** Profiling the REP STOSD cases we've handled. */
1793 STAMPROFILE StatMonitorRZRepStosd;
1794
1795 /** Profiling the R3 access handler. */
1796 STAMPROFILE StatMonitorR3;
1797 /** Times we've failed interpreting the instruction. */
1798 STAMCOUNTER StatMonitorR3EmulateInstr;
1799 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1800 STAMPROFILE StatMonitorR3FlushPage;
1801 /** Times we've detected fork(). */
1802 STAMCOUNTER StatMonitorR3Fork;
1803 /** Profiling the R3 access we've handled (except REP STOSD). */
1804 STAMPROFILE StatMonitorR3Handled;
1805 /** The number of times we've seen rep prefixes we can't handle. */
1806 STAMCOUNTER StatMonitorR3RepPrefix;
1807 /** Profiling the REP STOSD cases we've handled. */
1808 STAMPROFILE StatMonitorR3RepStosd;
1809 /** The number of times we're called in an async thread an need to flush. */
1810 STAMCOUNTER StatMonitorR3Async;
1811 /** The high wather mark for cModifiedPages. */
1812 uint16_t cModifiedPagesHigh;
1813 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1814# endif
1815# ifdef PGMPOOL_WITH_CACHE
1816 /** The number of cache hits. */
1817 STAMCOUNTER StatCacheHits;
1818 /** The number of cache misses. */
1819 STAMCOUNTER StatCacheMisses;
1820 /** The number of times we've got a conflict of 'kind' in the cache. */
1821 STAMCOUNTER StatCacheKindMismatches;
1822 /** Number of times we've been out of pages. */
1823 STAMCOUNTER StatCacheFreeUpOne;
1824 /** The number of cacheable allocations. */
1825 STAMCOUNTER StatCacheCacheable;
1826 /** The number of uncacheable allocations. */
1827 STAMCOUNTER StatCacheUncacheable;
1828# endif
1829#elif HC_ARCH_BITS == 64
1830 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1831#endif
1832 /** The AVL tree for looking up a page by its HC physical address. */
1833 AVLOHCPHYSTREE HCPhysTree;
1834 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1835 /** Array of pages. (cMaxPages in length)
1836 * The Id is the index into thist array.
1837 */
1838 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1839} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1840
1841
1842/** @def PGMPOOL_PAGE_2_PTR
1843 * Maps a pool page pool into the current context.
1844 *
1845 * @returns VBox status code.
1846 * @param pVM The VM handle.
1847 * @param pPage The pool page.
1848 *
1849 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1850 * small page window employeed by that function. Be careful.
1851 * @remark There is no need to assert on the result.
1852 */
1853#if defined(IN_RC)
1854# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1855#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1856# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1857#elif defined(VBOX_STRICT)
1858# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1859DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1860{
1861 Assert(pPage->pvPageR3);
1862 return pPage->pvPageR3;
1863}
1864#else
1865# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1866#endif
1867
1868/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1869 * Maps a pool page pool into the current context.
1870 *
1871 * @returns VBox status code.
1872 * @param pPGM Pointer to the PGM instance data.
1873 * @param pPage The pool page.
1874 *
1875 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1876 * small page window employeed by that function. Be careful.
1877 * @remark There is no need to assert on the result.
1878 */
1879#if defined(IN_RC)
1880# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1881#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1882# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1883#else
1884# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1885#endif
1886
1887
1888
1889/**
1890 * Trees are using self relative offsets as pointers.
1891 * So, all its data, including the root pointer, must be in the heap for HC and GC
1892 * to have the same layout.
1893 */
1894typedef struct PGMTREES
1895{
1896 /** Physical access handlers (AVL range+offsetptr tree). */
1897 AVLROGCPHYSTREE PhysHandlers;
1898 /** Virtual access handlers (AVL range + GC ptr tree). */
1899 AVLROGCPTRTREE VirtHandlers;
1900 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1901 AVLROGCPHYSTREE PhysToVirtHandlers;
1902 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1903 AVLROGCPTRTREE HyperVirtHandlers;
1904} PGMTREES;
1905/** Pointer to PGM trees. */
1906typedef PGMTREES *PPGMTREES;
1907
1908
1909/** @name Paging mode macros
1910 * @{ */
1911#ifdef IN_RC
1912# define PGM_CTX(a,b) a##RC##b
1913# define PGM_CTX_STR(a,b) a "GC" b
1914# define PGM_CTX_DECL(type) VMMRCDECL(type)
1915#else
1916# ifdef IN_RING3
1917# define PGM_CTX(a,b) a##R3##b
1918# define PGM_CTX_STR(a,b) a "R3" b
1919# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1920# else
1921# define PGM_CTX(a,b) a##R0##b
1922# define PGM_CTX_STR(a,b) a "R0" b
1923# define PGM_CTX_DECL(type) VMMDECL(type)
1924# endif
1925#endif
1926
1927#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1928#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1929#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1930#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1931#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1932#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1933#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1934#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1935#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1936#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1937#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1938#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1939#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1940#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1941#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1942#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1943#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1944
1945#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1946#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1947#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1948#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1949#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1950#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1951#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1952#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1953#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1954#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1955#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1956#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1957#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1958#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1959#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1960#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1961#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1962
1963/* Shw_Gst */
1964#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1965#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1966#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1967#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1968#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1969#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1970#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1971#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1972#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1973#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1974#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1975#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1976#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1977#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1978#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1979#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1980#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1981#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1982#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1983
1984#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1985#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1986#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1987#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1988#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1989#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1990#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1991#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1992#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1993#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1994#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1995#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1996#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1997#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1998#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1999#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2000#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2001#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2002#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2003#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2004#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2005#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2006#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2007#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2008#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2009#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2010#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2011#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2012#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2013#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2014#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2015#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2016#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2017#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2018#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2019#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2020#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2021
2022#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2023#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2024/** @} */
2025
2026/**
2027 * Data for each paging mode.
2028 */
2029typedef struct PGMMODEDATA
2030{
2031 /** The guest mode type. */
2032 uint32_t uGstType;
2033 /** The shadow mode type. */
2034 uint32_t uShwType;
2035
2036 /** @name Function pointers for Shadow paging.
2037 * @{
2038 */
2039 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2040 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2041 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2042 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2043
2044 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2045 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2046
2047 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2048 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2049 /** @} */
2050
2051 /** @name Function pointers for Guest paging.
2052 * @{
2053 */
2054 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2055 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2056 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2057 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2058 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2059#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2060 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2061 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2062#endif
2063#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2064 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2065 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2066 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2067 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2068#endif
2069 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2070 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2071 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2072#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2073 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2074 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2075#endif
2076#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2077 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2078 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2079#endif
2080 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2081 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2082 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2083#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2084 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2085 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2086#endif
2087#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2088 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2089 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2090#endif
2091 /** @} */
2092
2093 /** @name Function pointers for Both Shadow and Guest paging.
2094 * @{
2095 */
2096 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2097 /* no pfnR3BthTrap0eHandler */
2098 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2099 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2100 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2101 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2102 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2103#ifdef VBOX_STRICT
2104 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2105#endif
2106 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2107 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2108
2109 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2110 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2111 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2112 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2113 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2114 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2115#ifdef VBOX_STRICT
2116 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2117#endif
2118 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2119 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2120
2121 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2122 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2123 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2124 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2125 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2126 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2127#ifdef VBOX_STRICT
2128 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2129#endif
2130 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2131 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2132 /** @} */
2133} PGMMODEDATA, *PPGMMODEDATA;
2134
2135
2136
2137/**
2138 * Converts a PGM pointer into a VM pointer.
2139 * @returns Pointer to the VM structure the PGM is part of.
2140 * @param pPGM Pointer to PGM instance data.
2141 */
2142#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2143
2144/**
2145 * PGM Data (part of VM)
2146 */
2147typedef struct PGM
2148{
2149 /** Offset to the VM structure. */
2150 RTINT offVM;
2151 /** Offset of the PGMCPU structure relative to VMCPU. */
2152 int32_t offVCpu;
2153 /** Alignment padding. */
2154 int32_t i32Alignment;
2155
2156 /*
2157 * This will be redefined at least two more times before we're done, I'm sure.
2158 * The current code is only to get on with the coding.
2159 * - 2004-06-10: initial version, bird.
2160 * - 2004-07-02: 1st time, bird.
2161 * - 2004-10-18: 2nd time, bird.
2162 * - 2005-07-xx: 3rd time, bird.
2163 */
2164
2165 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2166 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2167 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2168 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2169
2170 /** The host paging mode. (This is what SUPLib reports.) */
2171 SUPPAGINGMODE enmHostMode;
2172 /** The shadow paging mode. */
2173 PGMMODE enmShadowMode;
2174 /** The guest paging mode. */
2175 PGMMODE enmGuestMode;
2176
2177 /** The current physical address representing in the guest CR3 register. */
2178 RTGCPHYS GCPhysCR3;
2179 /** Pointer to the 5 page CR3 content mapping.
2180 * The first page is always the CR3 (in some form) while the 4 other pages
2181 * are used of the PDs in PAE mode. */
2182 RTGCPTR GCPtrCR3Mapping;
2183#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2184 uint32_t u32Alignment;
2185#endif
2186#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2187 /** The physical address of the currently monitored guest CR3 page.
2188 * When this value is NIL_RTGCPHYS no page is being monitored. */
2189 RTGCPHYS GCPhysGstCR3Monitored;
2190#endif
2191 /** @name 32-bit Guest Paging.
2192 * @{ */
2193 /** The guest's page directory, R3 pointer. */
2194 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2195#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2196 /** The guest's page directory, R0 pointer. */
2197 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2198#endif
2199 /** The guest's page directory, static RC mapping. */
2200 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2201 /** @} */
2202
2203 /** @name PAE Guest Paging.
2204 * @{ */
2205 /** The guest's page directory pointer table, static RC mapping. */
2206 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2207 /** The guest's page directory pointer table, R3 pointer. */
2208 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2209#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2210 /** The guest's page directory pointer table, R0 pointer. */
2211 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2212#endif
2213
2214 /** The guest's page directories, R3 pointers.
2215 * These are individual pointers and don't have to be adjecent.
2216 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2217 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2218 /** The guest's page directories, R0 pointers.
2219 * Same restrictions as apGstPaePDsR3. */
2220#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2221 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2222#endif
2223 /** The guest's page directories, static GC mapping.
2224 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2225 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2226 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2227 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2228 RTGCPHYS aGCPhysGstPaePDs[4];
2229 /** The physical addresses of the monitored guest page directories (PAE). */
2230 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2231 /** @} */
2232
2233 /** @name AMD64 Guest Paging.
2234 * @{ */
2235 /** The guest's page directory pointer table, R3 pointer. */
2236 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2237#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2238 /** The guest's page directory pointer table, R0 pointer. */
2239 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2240#endif
2241 /** @} */
2242
2243 /** @name Shadow paging
2244 * @{ */
2245 /** The root page table - R3 Ptr. */
2246 R3PTRTYPE(void *) pShwRootR3;
2247# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2248 /** The root page table - R0 Ptr. */
2249 R0PTRTYPE(void *) pShwRootR0;
2250# endif
2251 /** The root page table - RC Ptr. */
2252 RCPTRTYPE(void *) pShwRootRC;
2253# if HC_ARCH_BITS == 64
2254 uint32_t u32Padding1; /**< alignment padding. */
2255# endif
2256 /** The Physical Address (HC) of the current active shadow CR3. */
2257 RTHCPHYS HCPhysShwCR3;
2258 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2259 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2260 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2261 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2262 /** Pointer to the page of the current active CR3 - RC Ptr. */
2263 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2264 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2265 uint32_t iShwUser;
2266 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2267 uint32_t iShwUserTable;
2268# if HC_ARCH_BITS == 64
2269 RTRCPTR alignment6; /**< structure size alignment. */
2270# endif
2271 /** @} */
2272#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2273 /** @name 32-bit Shadow Paging
2274 * @{ */
2275 /** The 32-Bit PD - R3 Ptr. */
2276 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2277 /** The 32-Bit PD - R0 Ptr. */
2278 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2279 /** The 32-Bit PD - RC Ptr. */
2280 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2281# if HC_ARCH_BITS == 64
2282 uint32_t u32Padding10; /**< alignment padding. */
2283# endif
2284 /** The Physical Address (HC) of the 32-Bit PD. */
2285 RTHCPHYS HCPhysShw32BitPD;
2286 /** @} */
2287
2288 /** @name PAE Shadow Paging
2289 * @{ */
2290 /** The four PDs for the low 4GB - R3 Ptr.
2291 * Even though these are 4 pointers, what they point at is a single table.
2292 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2293 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2294# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2295 /** The four PDs for the low 4GB - R0 Ptr.
2296 * Same kind of mapping as apHCPaePDs. */
2297 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2298# endif
2299 /** The four PDs for the low 4GB - RC Ptr.
2300 * Same kind of mapping as apHCPaePDs. */
2301 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2302 /** The Physical Address (HC) of the four PDs for the low 4GB.
2303 * These are *NOT* 4 contiguous pages. */
2304 RTHCPHYS aHCPhysPaePDs[4];
2305 /** The Physical Address (HC) of the PAE PDPT. */
2306 RTHCPHYS HCPhysShwPaePdpt;
2307 /** The PAE PDPT - R3 Ptr. */
2308 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2309 /** The PAE PDPT - R0 Ptr. */
2310 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2311 /** The PAE PDPT - RC Ptr. */
2312 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2313 /** @} */
2314# if HC_ARCH_BITS == 64
2315 RTRCPTR alignment5; /**< structure size alignment. */
2316# endif
2317#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2318 /** @name Nested Shadow Paging
2319 * @{ */
2320 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2321 RTR3PTR pShwNestedRootR3;
2322# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2323 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2324 RTR0PTR pShwNestedRootR0;
2325# endif
2326 /** The Physical Address (HC) of the nested paging root. */
2327 RTHCPHYS HCPhysShwNestedRoot;
2328 /** @} */
2329
2330 /** @name Function pointers for Shadow paging.
2331 * @{
2332 */
2333 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2334 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2335 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2336 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2337
2338 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2339 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2340
2341 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2342 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2343
2344 /** @} */
2345
2346 /** @name Function pointers for Guest paging.
2347 * @{
2348 */
2349 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2350 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2351 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2352 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2353 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2354#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2355 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2356 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2357#endif
2358#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2359 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2360 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2361 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2362 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2363#endif
2364 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2365 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2366 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2367#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2368 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2369 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2370#endif
2371#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2372 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2373 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2374#endif
2375#if HC_ARCH_BITS == 64
2376 RTRCPTR alignment3; /**< structure size alignment. */
2377#endif
2378
2379 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2380 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2381 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2382#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2383 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2384 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2385#endif
2386#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2387 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2388 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2389#endif
2390 /** @} */
2391
2392 /** @name Function pointers for Both Shadow and Guest paging.
2393 * @{
2394 */
2395 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2396 /* no pfnR3BthTrap0eHandler */
2397 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2398 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2399 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2400 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2401 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2402 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2403 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2404 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2405
2406 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2407 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2408 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2409 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2410 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2411 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2412 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2413 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2414 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2415
2416 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2417 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2418 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2419 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2420 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2421 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2422 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2423 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2424 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2425#if HC_ARCH_BITS == 64
2426 RTRCPTR alignment2; /**< structure size alignment. */
2427#endif
2428 /** @} */
2429
2430 /** Pointer to SHW+GST mode data (function pointers).
2431 * The index into this table is made up from */
2432 R3PTRTYPE(PPGMMODEDATA) paModeData;
2433
2434 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2435 * This is sorted by physical address and contains no overlapping ranges. */
2436 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2437 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2438 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2439 /** RC pointer corresponding to PGM::pRamRangesR3. */
2440 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2441 /** The configured RAM size. */
2442 RTUINT cbRamSize;
2443
2444 /** Pointer to the list of ROM ranges - for R3.
2445 * This is sorted by physical address and contains no overlapping ranges. */
2446 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2447 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2448 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2449 /** RC pointer corresponding to PGM::pRomRangesR3. */
2450 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2451 /** Alignment padding. */
2452 RTRCPTR GCPtrPadding2;
2453
2454 /** Pointer to the list of MMIO2 ranges - for R3.
2455 * Registration order. */
2456 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2457
2458 /** PGM offset based trees - R3 Ptr. */
2459 R3PTRTYPE(PPGMTREES) pTreesR3;
2460 /** PGM offset based trees - R0 Ptr. */
2461 R0PTRTYPE(PPGMTREES) pTreesR0;
2462 /** PGM offset based trees - RC Ptr. */
2463 RCPTRTYPE(PPGMTREES) pTreesRC;
2464
2465 /** Linked list of GC mappings - for RC.
2466 * The list is sorted ascending on address.
2467 */
2468 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2469 /** Linked list of GC mappings - for HC.
2470 * The list is sorted ascending on address.
2471 */
2472 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2473 /** Linked list of GC mappings - for R0.
2474 * The list is sorted ascending on address.
2475 */
2476 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2477
2478 /** Indicates that PGMR3FinalizeMappings has been called and that further
2479 * PGMR3MapIntermediate calls will be rejected. */
2480 bool fFinalizedMappings;
2481 /** If set no conflict checks are required. (boolean) */
2482 bool fMappingsFixed;
2483 /** If set, then no mappings are put into the shadow page table. (boolean) */
2484 bool fDisableMappings;
2485 /** Size of fixed mapping */
2486 uint32_t cbMappingFixed;
2487 /** Base address (GC) of fixed mapping */
2488 RTGCPTR GCPtrMappingFixed;
2489#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2490 uint32_t u32Padding0; /**< alignment padding. */
2491#endif
2492
2493
2494 /** @name Intermediate Context
2495 * @{ */
2496 /** Pointer to the intermediate page directory - Normal. */
2497 R3PTRTYPE(PX86PD) pInterPD;
2498 /** Pointer to the intermedate page tables - Normal.
2499 * There are two page tables, one for the identity mapping and one for
2500 * the host context mapping (of the core code). */
2501 R3PTRTYPE(PX86PT) apInterPTs[2];
2502 /** Pointer to the intermedate page tables - PAE. */
2503 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2504 /** Pointer to the intermedate page directory - PAE. */
2505 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2506 /** Pointer to the intermedate page directory - PAE. */
2507 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2508 /** Pointer to the intermedate page-map level 4 - AMD64. */
2509 R3PTRTYPE(PX86PML4) pInterPaePML4;
2510 /** Pointer to the intermedate page directory - AMD64. */
2511 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2512 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2513 RTHCPHYS HCPhysInterPD;
2514 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2515 RTHCPHYS HCPhysInterPaePDPT;
2516 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2517 RTHCPHYS HCPhysInterPaePML4;
2518 /** @} */
2519
2520 /** Base address of the dynamic page mapping area.
2521 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2522 */
2523 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2524 /** The index of the last entry used in the dynamic page mapping area. */
2525 RTUINT iDynPageMapLast;
2526 /** Cache containing the last entries in the dynamic page mapping area.
2527 * The cache size is covering half of the mapping area. */
2528 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2529
2530 /** The address of the ring-0 mapping cache if we're making use of it. */
2531 RTR0PTR pvR0DynMapUsed;
2532#if HC_ARCH_BITS == 32
2533 RTR0PTR R0PtrPadding0; /**< Alignment. */
2534#endif
2535
2536
2537 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2538 RTGCPHYS GCPhys4MBPSEMask;
2539
2540 /** A20 gate mask.
2541 * Our current approach to A20 emulation is to let REM do it and don't bother
2542 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2543 * But whould need arrise, we'll subject physical addresses to this mask. */
2544 RTGCPHYS GCPhysA20Mask;
2545 /** A20 gate state - boolean! */
2546 RTUINT fA20Enabled;
2547
2548 /** What needs syncing (PGM_SYNC_*).
2549 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2550 * PGMFlushTLB, and PGMR3Load. */
2551 RTUINT fSyncFlags;
2552
2553 /** PGM critical section.
2554 * This protects the physical & virtual access handlers, ram ranges,
2555 * and the page flag updating (some of it anyway).
2556 */
2557 PDMCRITSECT CritSect;
2558
2559 /** Shadow Page Pool - R3 Ptr. */
2560 R3PTRTYPE(PPGMPOOL) pPoolR3;
2561 /** Shadow Page Pool - R0 Ptr. */
2562 R0PTRTYPE(PPGMPOOL) pPoolR0;
2563 /** Shadow Page Pool - RC Ptr. */
2564 RCPTRTYPE(PPGMPOOL) pPoolRC;
2565
2566 /** We're not in a state which permits writes to guest memory.
2567 * (Only used in strict builds.) */
2568 bool fNoMorePhysWrites;
2569
2570 /** Flush the cache on the next access. */
2571 bool fPhysCacheFlushPending;
2572/** @todo r=bird: Fix member names!*/
2573 /** PGMPhysRead cache */
2574 PGMPHYSCACHE pgmphysreadcache;
2575 /** PGMPhysWrite cache */
2576 PGMPHYSCACHE pgmphyswritecache;
2577
2578 /**
2579 * Data associated with managing the ring-3 mappings of the allocation chunks.
2580 */
2581 struct
2582 {
2583 /** The chunk tree, ordered by chunk id. */
2584#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2585 R3PTRTYPE(PAVLU32NODECORE) pTree;
2586#else
2587 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2588#endif
2589 /** The chunk mapping TLB. */
2590 PGMCHUNKR3MAPTLB Tlb;
2591 /** The number of mapped chunks. */
2592 uint32_t c;
2593 /** The maximum number of mapped chunks.
2594 * @cfgm PGM/MaxRing3Chunks */
2595 uint32_t cMax;
2596 /** The chunk age tree, ordered by ageing sequence number. */
2597 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2598 /** The current time. */
2599 uint32_t iNow;
2600 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2601 uint32_t AgeingCountdown;
2602 } ChunkR3Map;
2603
2604 /**
2605 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2606 */
2607 PGMPAGER3MAPTLB PhysTlbHC;
2608
2609 /** @name The zero page.
2610 * @{ */
2611 /** The host physical address of the zero page. */
2612 RTHCPHYS HCPhysZeroPg;
2613 /** The ring-3 mapping of the zero page. */
2614 RTR3PTR pvZeroPgR3;
2615 /** The ring-0 mapping of the zero page. */
2616 RTR0PTR pvZeroPgR0;
2617 /** The GC mapping of the zero page. */
2618 RTGCPTR pvZeroPgGC;
2619#if GC_ARCH_BITS != 32
2620 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2621#endif
2622 /** @}*/
2623
2624 /** The number of handy pages. */
2625 uint32_t cHandyPages;
2626 /**
2627 * Array of handy pages.
2628 *
2629 * This array is used in a two way communication between pgmPhysAllocPage
2630 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2631 * an intermediary.
2632 *
2633 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2634 * (The current size of 32 pages, means 128 KB of handy memory.)
2635 */
2636 GMMPAGEDESC aHandyPages[32];
2637
2638 /** @name Release Statistics
2639 * @{ */
2640 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2641 uint32_t cPrivatePages; /**< The number of private pages. */
2642 uint32_t cSharedPages; /**< The number of shared pages. */
2643 uint32_t cZeroPages; /**< The number of zero backed pages. */
2644 /** The number of times the guest has switched mode since last reset or statistics reset. */
2645 STAMCOUNTER cGuestModeChanges;
2646 /** The number of times we were forced to change the hypervisor region location. */
2647 STAMCOUNTER cRelocations;
2648 /** @} */
2649
2650#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2651 /** RC: Which statistic this \#PF should be attributed to. */
2652 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2653 RTRCPTR padding0;
2654 /** R0: Which statistic this \#PF should be attributed to. */
2655 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2656 RTR0PTR padding1;
2657
2658 /* Common */
2659# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2660 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2661 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2662 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2663 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2664 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2665 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2666# endif
2667 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2668 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2669
2670 /* R3 only: */
2671 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2672 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2673 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2674 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2675 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2676 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2677
2678 /* R0 only: */
2679 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2680 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2681 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2682 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2683 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2684 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2685 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2686 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2687 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2688 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2689 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2690 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2691 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2692 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2693 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2694 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2695 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2696 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2697 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2698 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2699 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2700 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2701 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2702 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2703 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2704 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2705
2706 /* RC only: */
2707 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2708 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2709 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2710 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2711
2712 /* RZ only: */
2713 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2714 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2715 STAMPROFILE StatRZTrap0eTimeSyncPT;
2716 STAMPROFILE StatRZTrap0eTimeMapping;
2717 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2718 STAMPROFILE StatRZTrap0eTimeHandlers;
2719 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2720 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2721 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2722 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2723 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2724 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2725 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2726 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2727 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2728 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2729 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2730 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2731 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2732 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2733 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2734 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2735 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2736 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2737 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2738 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2739 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2740 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2741 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2742 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2743 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2744 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2745 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2746 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2747 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2748 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2749 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2750 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2751 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2752 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2753 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2754 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2755 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2756 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2757 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2758 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2759 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2760 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2761 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2762
2763 /* HC - R3 and (maybe) R0: */
2764
2765 /* RZ & R3: */
2766 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2767 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2768 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2769 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2770 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2771 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2772 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2773 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2774 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2775 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2776 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2777 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2778 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2779 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2780 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2781 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2782 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2783 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2784 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2785 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2786 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2787 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2788 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2789 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2790 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2791 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2792 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2793 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2794 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2795 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2796 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2797 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2798 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2799 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2800 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2801 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2802 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2803 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2804 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2805 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2806 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2807 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2808 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2809 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2810 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2811 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2812 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2813/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2814 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2815 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2816 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2817 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2818 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2819 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2820
2821 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2822 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2823 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2824 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2825 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2826 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2827 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2828 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2829 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2830 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2831 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2832 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2833 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2834 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2835 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2836 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2837 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2838 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2839 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2840 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2841 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2842 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2843 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2844 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2845 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2846 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2847 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2848 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2849 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2850 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2851 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2852 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2853 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2854 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2855 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2856 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2857 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2858 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2859 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2860 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2861 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2862 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2863 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2864 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2865 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2866 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2867 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2868/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2869 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2870 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2871 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2872 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2873 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2874 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2875#endif /* VBOX_WITH_STATISTICS */
2876} PGM;
2877/** Pointer to the PGM instance data. */
2878typedef PGM *PPGM;
2879
2880
2881/**
2882 * PGMCPU Data (part of VMCPU).
2883 */
2884typedef struct PGMCPU
2885{
2886 /** Offset to the VMCPU structure. */
2887 RTINT offVMCPU;
2888 /** Automatically tracked physical memory mapping set.
2889 * Ring-0 and strict raw-mode builds. */
2890 PGMMAPSET AutoSet;
2891} PGMCPU;
2892/** Pointer to the per-cpu PGM data. */
2893typedef PGMCPU *PPGMCPU;
2894
2895
2896/** @name PGM::fSyncFlags Flags
2897 * @{
2898 */
2899/** Updates the virtual access handler state bit in PGMPAGE. */
2900#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2901/** Always sync CR3. */
2902#define PGM_SYNC_ALWAYS RT_BIT(1)
2903/** Check monitoring on next CR3 (re)load and invalidate page. */
2904#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2905/** Check guest mapping in SyncCR3. */
2906#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2907/** Clear the page pool (a light weight flush). */
2908#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2909/** @} */
2910
2911
2912__BEGIN_DECLS
2913
2914int pgmLock(PVM pVM);
2915void pgmUnlock(PVM pVM);
2916
2917VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2918VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2919
2920int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2921int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2922PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2923void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2924DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2925
2926void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2927bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2928int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2929DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2930#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2931void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2932#else
2933# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2934#endif
2935DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2936
2937
2938void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2939int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2940int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2941int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2942#ifdef IN_RING3
2943int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2944int pgmR3PhysRamReset(PVM pVM);
2945int pgmR3PhysRomReset(PVM pVM);
2946# ifndef VBOX_WITH_NEW_PHYS_CODE
2947int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2948# endif
2949
2950int pgmR3PoolInit(PVM pVM);
2951void pgmR3PoolRelocate(PVM pVM);
2952void pgmR3PoolReset(PVM pVM);
2953
2954#endif /* IN_RING3 */
2955#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2956int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2957#endif
2958#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2959void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2960#endif
2961int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2962PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2963void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2964void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2965int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2966void pgmPoolFlushAll(PVM pVM);
2967void pgmPoolClearAll(PVM pVM);
2968int pgmPoolSyncCR3(PVM pVM);
2969void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2970void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2971int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2972PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2973void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2974void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2975uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2976void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2977#ifdef PGMPOOL_WITH_MONITORING
2978void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2979int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2980void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2981void pgmPoolMonitorModifiedClearAll(PVM pVM);
2982int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2983int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2984#endif
2985
2986#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2987int pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2988int pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2989
2990bool pgmPoolIsPageLocked(PVM pVM, PPGMPOOLPAGE pPage);
2991
2992void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
2993void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2994int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2995#endif
2996int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2997int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2998
2999#ifndef IN_RC
3000int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3001#endif
3002int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3003
3004__END_DECLS
3005
3006
3007/**
3008 * Gets the PGMRAMRANGE structure for a guest page.
3009 *
3010 * @returns Pointer to the RAM range on success.
3011 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3012 *
3013 * @param pPGM PGM handle.
3014 * @param GCPhys The GC physical address.
3015 */
3016DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3017{
3018 /*
3019 * Optimize for the first range.
3020 */
3021 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3022 RTGCPHYS off = GCPhys - pRam->GCPhys;
3023 if (RT_UNLIKELY(off >= pRam->cb))
3024 {
3025 do
3026 {
3027 pRam = pRam->CTX_SUFF(pNext);
3028 if (RT_UNLIKELY(!pRam))
3029 break;
3030 off = GCPhys - pRam->GCPhys;
3031 } while (off >= pRam->cb);
3032 }
3033 return pRam;
3034}
3035
3036
3037/**
3038 * Gets the PGMPAGE structure for a guest page.
3039 *
3040 * @returns Pointer to the page on success.
3041 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3042 *
3043 * @param pPGM PGM handle.
3044 * @param GCPhys The GC physical address.
3045 */
3046DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3047{
3048 /*
3049 * Optimize for the first range.
3050 */
3051 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3052 RTGCPHYS off = GCPhys - pRam->GCPhys;
3053 if (RT_UNLIKELY(off >= pRam->cb))
3054 {
3055 do
3056 {
3057 pRam = pRam->CTX_SUFF(pNext);
3058 if (RT_UNLIKELY(!pRam))
3059 return NULL;
3060 off = GCPhys - pRam->GCPhys;
3061 } while (off >= pRam->cb);
3062 }
3063 return &pRam->aPages[off >> PAGE_SHIFT];
3064}
3065
3066
3067/**
3068 * Gets the PGMPAGE structure for a guest page.
3069 *
3070 * Old Phys code: Will make sure the page is present.
3071 *
3072 * @returns VBox status code.
3073 * @retval VINF_SUCCESS and a valid *ppPage on success.
3074 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3075 *
3076 * @param pPGM PGM handle.
3077 * @param GCPhys The GC physical address.
3078 * @param ppPage Where to store the page poitner on success.
3079 */
3080DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3081{
3082 /*
3083 * Optimize for the first range.
3084 */
3085 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3086 RTGCPHYS off = GCPhys - pRam->GCPhys;
3087 if (RT_UNLIKELY(off >= pRam->cb))
3088 {
3089 do
3090 {
3091 pRam = pRam->CTX_SUFF(pNext);
3092 if (RT_UNLIKELY(!pRam))
3093 {
3094 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3095 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3096 }
3097 off = GCPhys - pRam->GCPhys;
3098 } while (off >= pRam->cb);
3099 }
3100 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3101#ifndef VBOX_WITH_NEW_PHYS_CODE
3102
3103 /*
3104 * Make sure it's present.
3105 */
3106 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3107 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3108 {
3109#ifdef IN_RING3
3110 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3111#else
3112 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3113#endif
3114 if (RT_FAILURE(rc))
3115 {
3116 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3117 return rc;
3118 }
3119 Assert(rc == VINF_SUCCESS);
3120 }
3121#endif
3122 return VINF_SUCCESS;
3123}
3124
3125
3126
3127
3128/**
3129 * Gets the PGMPAGE structure for a guest page.
3130 *
3131 * Old Phys code: Will make sure the page is present.
3132 *
3133 * @returns VBox status code.
3134 * @retval VINF_SUCCESS and a valid *ppPage on success.
3135 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3136 *
3137 * @param pPGM PGM handle.
3138 * @param GCPhys The GC physical address.
3139 * @param ppPage Where to store the page poitner on success.
3140 * @param ppRamHint Where to read and store the ram list hint.
3141 * The caller initializes this to NULL before the call.
3142 */
3143DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3144{
3145 RTGCPHYS off;
3146 PPGMRAMRANGE pRam = *ppRamHint;
3147 if ( !pRam
3148 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3149 {
3150 pRam = pPGM->CTX_SUFF(pRamRanges);
3151 off = GCPhys - pRam->GCPhys;
3152 if (RT_UNLIKELY(off >= pRam->cb))
3153 {
3154 do
3155 {
3156 pRam = pRam->CTX_SUFF(pNext);
3157 if (RT_UNLIKELY(!pRam))
3158 {
3159 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3160 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3161 }
3162 off = GCPhys - pRam->GCPhys;
3163 } while (off >= pRam->cb);
3164 }
3165 *ppRamHint = pRam;
3166 }
3167 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3168#ifndef VBOX_WITH_NEW_PHYS_CODE
3169
3170 /*
3171 * Make sure it's present.
3172 */
3173 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3174 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3175 {
3176#ifdef IN_RING3
3177 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3178#else
3179 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3180#endif
3181 if (RT_FAILURE(rc))
3182 {
3183 *ppPage = NULL; /* Shut up annoying smart ass. */
3184 return rc;
3185 }
3186 Assert(rc == VINF_SUCCESS);
3187 }
3188#endif
3189 return VINF_SUCCESS;
3190}
3191
3192
3193/**
3194 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3195 *
3196 * @returns Pointer to the page on success.
3197 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3198 *
3199 * @param pPGM PGM handle.
3200 * @param GCPhys The GC physical address.
3201 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3202 */
3203DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3204{
3205 /*
3206 * Optimize for the first range.
3207 */
3208 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3209 RTGCPHYS off = GCPhys - pRam->GCPhys;
3210 if (RT_UNLIKELY(off >= pRam->cb))
3211 {
3212 do
3213 {
3214 pRam = pRam->CTX_SUFF(pNext);
3215 if (RT_UNLIKELY(!pRam))
3216 return NULL;
3217 off = GCPhys - pRam->GCPhys;
3218 } while (off >= pRam->cb);
3219 }
3220 *ppRam = pRam;
3221 return &pRam->aPages[off >> PAGE_SHIFT];
3222}
3223
3224
3225/**
3226 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3227 *
3228 * @returns Pointer to the page on success.
3229 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3230 *
3231 * @param pPGM PGM handle.
3232 * @param GCPhys The GC physical address.
3233 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3234 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3235 */
3236DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3237{
3238 /*
3239 * Optimize for the first range.
3240 */
3241 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3242 RTGCPHYS off = GCPhys - pRam->GCPhys;
3243 if (RT_UNLIKELY(off >= pRam->cb))
3244 {
3245 do
3246 {
3247 pRam = pRam->CTX_SUFF(pNext);
3248 if (RT_UNLIKELY(!pRam))
3249 {
3250 *ppRam = NULL; /* Shut up silly GCC warnings. */
3251 *ppPage = NULL; /* ditto */
3252 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3253 }
3254 off = GCPhys - pRam->GCPhys;
3255 } while (off >= pRam->cb);
3256 }
3257 *ppRam = pRam;
3258 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3259#ifndef VBOX_WITH_NEW_PHYS_CODE
3260
3261 /*
3262 * Make sure it's present.
3263 */
3264 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3265 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3266 {
3267#ifdef IN_RING3
3268 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3269#else
3270 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3271#endif
3272 if (RT_FAILURE(rc))
3273 {
3274 *ppPage = NULL; /* Shut up silly GCC warnings. */
3275 *ppPage = NULL; /* ditto */
3276 return rc;
3277 }
3278 Assert(rc == VINF_SUCCESS);
3279
3280 }
3281#endif
3282 return VINF_SUCCESS;
3283}
3284
3285
3286/**
3287 * Convert GC Phys to HC Phys.
3288 *
3289 * @returns VBox status.
3290 * @param pPGM PGM handle.
3291 * @param GCPhys The GC physical address.
3292 * @param pHCPhys Where to store the corresponding HC physical address.
3293 *
3294 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3295 * Avoid when writing new code!
3296 */
3297DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3298{
3299 PPGMPAGE pPage;
3300 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3301 if (RT_FAILURE(rc))
3302 return rc;
3303 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3304 return VINF_SUCCESS;
3305}
3306
3307#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3308
3309/**
3310 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3311 * optimizes access to pages already in the set.
3312 *
3313 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3314 * @param pPGM Pointer to the PVM instance data.
3315 * @param HCPhys The physical address of the page.
3316 * @param ppv Where to store the mapping address.
3317 */
3318DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3319{
3320 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3321 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3322 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3323 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3324
3325 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3326 unsigned iEntry = pSet->aiHashTable[iHash];
3327 if ( iEntry < pSet->cEntries
3328 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3329 {
3330 *ppv = pSet->aEntries[iEntry].pvPage;
3331 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3332 }
3333 else
3334 {
3335 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3336 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3337 }
3338
3339 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3340 return VINF_SUCCESS;
3341}
3342
3343
3344/**
3345 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3346 * access to pages already in the set.
3347 *
3348 * @returns See PGMDynMapGCPage.
3349 * @param pPGM Pointer to the PVM instance data.
3350 * @param HCPhys The physical address of the page.
3351 * @param ppv Where to store the mapping address.
3352 */
3353DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3354{
3355 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3356 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3357
3358 /*
3359 * Get the ram range.
3360 */
3361 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3362 RTGCPHYS off = GCPhys - pRam->GCPhys;
3363 if (RT_UNLIKELY(off >= pRam->cb
3364 /** @todo || page state stuff */))
3365 {
3366 /* This case is not counted into StatR0DynMapGCPageInl. */
3367 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3368 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3369 }
3370
3371 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3372 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3373
3374 /*
3375 * pgmR0DynMapHCPageInlined with out stats.
3376 */
3377 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3378 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3379 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3380
3381 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3382 unsigned iEntry = pSet->aiHashTable[iHash];
3383 if ( iEntry < pSet->cEntries
3384 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3385 {
3386 *ppv = pSet->aEntries[iEntry].pvPage;
3387 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3388 }
3389 else
3390 {
3391 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3392 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3393 }
3394
3395 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3396 return VINF_SUCCESS;
3397}
3398
3399#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3400
3401#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3402/**
3403 * Maps the page into current context (RC and maybe R0).
3404 *
3405 * @returns pointer to the mapping.
3406 * @param pVM Pointer to the PGM instance data.
3407 * @param pPage The page.
3408 */
3409DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3410{
3411 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3412 {
3413 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3414 void *pv;
3415# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3416 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3417# else
3418 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3419# endif
3420 return pv;
3421 }
3422 return pgmPoolMapPageFallback(pPGM, pPage);
3423}
3424
3425/**
3426 * Temporarily maps one host page specified by HC physical address, returning
3427 * pointer within the page.
3428 *
3429 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3430 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3431 *
3432 * @returns The address corresponding to HCPhys.
3433 * @param pPGM Pointer to the PVM instance data.
3434 * @param HCPhys HC Physical address of the page.
3435 */
3436DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3437{
3438 void *pv;
3439# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3440 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3441# else
3442 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3443# endif
3444 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3445 return pv;
3446}
3447#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3448
3449
3450#ifndef IN_RC
3451/**
3452 * Queries the Physical TLB entry for a physical guest page,
3453 * attemting to load the TLB entry if necessary.
3454 *
3455 * @returns VBox status code.
3456 * @retval VINF_SUCCESS on success
3457 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3458 * @param pPGM The PGM instance handle.
3459 * @param GCPhys The address of the guest page.
3460 * @param ppTlbe Where to store the pointer to the TLB entry.
3461 */
3462
3463DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3464{
3465 int rc;
3466 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3467 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3468 {
3469 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3470 rc = VINF_SUCCESS;
3471 }
3472 else
3473 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3474 *ppTlbe = pTlbe;
3475 return rc;
3476}
3477#endif /* !IN_RC */
3478
3479#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3480
3481# ifndef VBOX_WITH_NEW_PHYS_CODE
3482/**
3483 * Convert GC Phys to HC Virt.
3484 *
3485 * @returns VBox status.
3486 * @param pPGM PGM handle.
3487 * @param GCPhys The GC physical address.
3488 * @param pHCPtr Where to store the corresponding HC virtual address.
3489 *
3490 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3491 * pgmPoolMonitorGCPtr2CCPtr.
3492 */
3493DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3494{
3495 PPGMRAMRANGE pRam;
3496 PPGMPAGE pPage;
3497 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3498 if (RT_FAILURE(rc))
3499 {
3500 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3501 return rc;
3502 }
3503 RTGCPHYS off = GCPhys - pRam->GCPhys;
3504
3505 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3506 {
3507 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3508 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3509 return VINF_SUCCESS;
3510 }
3511 if (pRam->pvR3)
3512 {
3513 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3514 return VINF_SUCCESS;
3515 }
3516 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3517 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3518}
3519# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3520#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3521
3522/**
3523 * Convert GC Phys to HC Virt and HC Phys.
3524 *
3525 * @returns VBox status.
3526 * @param pPGM PGM handle.
3527 * @param GCPhys The GC physical address.
3528 * @param pHCPtr Where to store the corresponding HC virtual address.
3529 * @param pHCPhys Where to store the HC Physical address and its flags.
3530 *
3531 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3532 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3533 */
3534DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3535{
3536 PPGMRAMRANGE pRam;
3537 PPGMPAGE pPage;
3538 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3539 if (RT_FAILURE(rc))
3540 {
3541 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3542 *pHCPhys = 0; /* ditto */
3543 return rc;
3544 }
3545 RTGCPHYS off = GCPhys - pRam->GCPhys;
3546
3547 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3548 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3549 {
3550 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3551#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3552 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3553 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3554#else
3555 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3556#endif
3557 return VINF_SUCCESS;
3558 }
3559 if (pRam->pvR3)
3560 {
3561 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3562 return VINF_SUCCESS;
3563 }
3564 *pHCPtr = 0;
3565 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3566}
3567
3568
3569/**
3570 * Clears flags associated with a RAM address.
3571 *
3572 * @returns VBox status code.
3573 * @param pPGM PGM handle.
3574 * @param GCPhys Guest context physical address.
3575 * @param fFlags fFlags to clear. (Bits 0-11.)
3576 */
3577DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3578{
3579 PPGMPAGE pPage;
3580 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3581 if (RT_FAILURE(rc))
3582 return rc;
3583
3584 fFlags &= ~X86_PTE_PAE_PG_MASK;
3585 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3586 return VINF_SUCCESS;
3587}
3588
3589
3590/**
3591 * Clears flags associated with a RAM address.
3592 *
3593 * @returns VBox status code.
3594 * @param pPGM PGM handle.
3595 * @param GCPhys Guest context physical address.
3596 * @param fFlags fFlags to clear. (Bits 0-11.)
3597 * @param ppRamHint Where to read and store the ram list hint.
3598 * The caller initializes this to NULL before the call.
3599 */
3600DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3601{
3602 PPGMPAGE pPage;
3603 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3604 if (RT_FAILURE(rc))
3605 return rc;
3606
3607 fFlags &= ~X86_PTE_PAE_PG_MASK;
3608 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3609 return VINF_SUCCESS;
3610}
3611
3612
3613/**
3614 * Sets (bitwise OR) flags associated with a RAM address.
3615 *
3616 * @returns VBox status code.
3617 * @param pPGM PGM handle.
3618 * @param GCPhys Guest context physical address.
3619 * @param fFlags fFlags to set clear. (Bits 0-11.)
3620 */
3621DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3622{
3623 PPGMPAGE pPage;
3624 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3625 if (RT_FAILURE(rc))
3626 return rc;
3627
3628 fFlags &= ~X86_PTE_PAE_PG_MASK;
3629 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3630 return VINF_SUCCESS;
3631}
3632
3633
3634/**
3635 * Sets (bitwise OR) flags associated with a RAM address.
3636 *
3637 * @returns VBox status code.
3638 * @param pPGM PGM handle.
3639 * @param GCPhys Guest context physical address.
3640 * @param fFlags fFlags to set clear. (Bits 0-11.)
3641 * @param ppRamHint Where to read and store the ram list hint.
3642 * The caller initializes this to NULL before the call.
3643 */
3644DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3645{
3646 PPGMPAGE pPage;
3647 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3648 if (RT_FAILURE(rc))
3649 return rc;
3650
3651 fFlags &= ~X86_PTE_PAE_PG_MASK;
3652 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3653 return VINF_SUCCESS;
3654}
3655
3656
3657/**
3658 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3659 * Takes PSE-36 into account.
3660 *
3661 * @returns guest physical address
3662 * @param pPGM Pointer to the PGM instance data.
3663 * @param Pde Guest Pde
3664 */
3665DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3666{
3667 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3668 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3669
3670 return GCPhys & pPGM->GCPhys4MBPSEMask;
3671}
3672
3673
3674/**
3675 * Gets the page directory entry for the specified address (32-bit paging).
3676 *
3677 * @returns The page directory entry in question.
3678 * @param pPGM Pointer to the PGM instance data.
3679 * @param GCPtr The address.
3680 */
3681DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3682{
3683#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3684 PCX86PD pGuestPD = 0;
3685 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3686 if (RT_FAILURE(rc))
3687 {
3688 X86PDE ZeroPde = {0};
3689 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3690 }
3691 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3692#else
3693 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3694#endif
3695}
3696
3697
3698/**
3699 * Gets the address of a specific page directory entry (32-bit paging).
3700 *
3701 * @returns Pointer the page directory entry in question.
3702 * @param pPGM Pointer to the PGM instance data.
3703 * @param GCPtr The address.
3704 */
3705DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3706{
3707#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3708 PX86PD pGuestPD = 0;
3709 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3710 AssertRCReturn(rc, 0);
3711 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3712#else
3713 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3714#endif
3715}
3716
3717
3718/**
3719 * Gets the address the guest page directory (32-bit paging).
3720 *
3721 * @returns Pointer the page directory entry in question.
3722 * @param pPGM Pointer to the PGM instance data.
3723 */
3724DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3725{
3726#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3727 PX86PD pGuestPD = 0;
3728 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3729 AssertRCReturn(rc, 0);
3730 return pGuestPD;
3731#else
3732 return pPGM->CTX_SUFF(pGst32BitPd);
3733#endif
3734}
3735
3736
3737/**
3738 * Gets the guest page directory pointer table.
3739 *
3740 * @returns Pointer to the page directory in question.
3741 * @returns NULL if the page directory is not present or on an invalid page.
3742 * @param pPGM Pointer to the PGM instance data.
3743 */
3744DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3745{
3746#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3747 PX86PDPT pGuestPDPT = 0;
3748 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3749 AssertRCReturn(rc, 0);
3750 return pGuestPDPT;
3751#else
3752 return pPGM->CTX_SUFF(pGstPaePdpt);
3753#endif
3754}
3755
3756
3757/**
3758 * Gets the guest page directory pointer table entry for the specified address.
3759 *
3760 * @returns Pointer to the page directory in question.
3761 * @returns NULL if the page directory is not present or on an invalid page.
3762 * @param pPGM Pointer to the PGM instance data.
3763 * @param GCPtr The address.
3764 */
3765DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3766{
3767 AssertGCPtr32(GCPtr);
3768
3769#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3770 PX86PDPT pGuestPDPT = 0;
3771 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3772 AssertRCReturn(rc, 0);
3773 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3774#else
3775 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3776#endif
3777}
3778
3779
3780/**
3781 * Gets the page directory for the specified address.
3782 *
3783 * @returns Pointer to the page directory in question.
3784 * @returns NULL if the page directory is not present or on an invalid page.
3785 * @param pPGM Pointer to the PGM instance data.
3786 * @param GCPtr The address.
3787 */
3788DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3789{
3790 AssertGCPtr32(GCPtr);
3791
3792#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3793 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3794 AssertReturn(pGuestPDPT, 0);
3795#else
3796 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3797#endif
3798 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3799 if (pGuestPDPT->a[iPdPt].n.u1Present)
3800 {
3801#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3802 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3803 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3804#endif
3805
3806 /* cache is out-of-sync. */
3807 PX86PDPAE pPD;
3808 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3809 if (RT_SUCCESS(rc))
3810 return pPD;
3811 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3812 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3813 }
3814 return NULL;
3815}
3816
3817
3818/**
3819 * Gets the page directory entry for the specified address.
3820 *
3821 * @returns Pointer to the page directory entry in question.
3822 * @returns NULL if the page directory is not present or on an invalid page.
3823 * @param pPGM Pointer to the PGM instance data.
3824 * @param GCPtr The address.
3825 */
3826DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3827{
3828 AssertGCPtr32(GCPtr);
3829
3830#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3831 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3832 AssertReturn(pGuestPDPT, 0);
3833#else
3834 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3835#endif
3836 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3837 if (pGuestPDPT->a[iPdPt].n.u1Present)
3838 {
3839 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3840#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3841 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3842 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3843#endif
3844
3845 /* The cache is out-of-sync. */
3846 PX86PDPAE pPD;
3847 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3848 if (RT_SUCCESS(rc))
3849 return &pPD->a[iPD];
3850 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3851 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3852 }
3853 return NULL;
3854}
3855
3856
3857/**
3858 * Gets the page directory entry for the specified address.
3859 *
3860 * @returns The page directory entry in question.
3861 * @returns A non-present entry if the page directory is not present or on an invalid page.
3862 * @param pPGM Pointer to the PGM instance data.
3863 * @param GCPtr The address.
3864 */
3865DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3866{
3867 AssertGCPtr32(GCPtr);
3868
3869#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3870 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3871 if (RT_LIKELY(pGuestPDPT))
3872#else
3873 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3874#endif
3875 {
3876 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3877 if (pGuestPDPT->a[iPdPt].n.u1Present)
3878 {
3879 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3880#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3881 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3882 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3883#endif
3884
3885 /* cache is out-of-sync. */
3886 PX86PDPAE pPD;
3887 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3888 if (RT_SUCCESS(rc))
3889 return pPD->a[iPD];
3890 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3891 }
3892 }
3893 X86PDEPAE ZeroPde = {0};
3894 return ZeroPde;
3895}
3896
3897
3898/**
3899 * Gets the page directory pointer table entry for the specified address
3900 * and returns the index into the page directory
3901 *
3902 * @returns Pointer to the page directory in question.
3903 * @returns NULL if the page directory is not present or on an invalid page.
3904 * @param pPGM Pointer to the PGM instance data.
3905 * @param GCPtr The address.
3906 * @param piPD Receives the index into the returned page directory
3907 * @param pPdpe Receives the page directory pointer entry. Optional.
3908 */
3909DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3910{
3911 AssertGCPtr32(GCPtr);
3912
3913#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3914 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3915 AssertReturn(pGuestPDPT, 0);
3916#else
3917 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3918#endif
3919 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3920 if (pPdpe)
3921 *pPdpe = pGuestPDPT->a[iPdPt];
3922 if (pGuestPDPT->a[iPdPt].n.u1Present)
3923 {
3924 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3925#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3926 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3927 {
3928 *piPD = iPD;
3929 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3930 }
3931#endif
3932
3933 /* cache is out-of-sync. */
3934 PX86PDPAE pPD;
3935 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3936 if (RT_SUCCESS(rc))
3937 {
3938 *piPD = iPD;
3939 return pPD;
3940 }
3941 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3942 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3943 }
3944 return NULL;
3945}
3946
3947#ifndef IN_RC
3948
3949/**
3950 * Gets the page map level-4 pointer for the guest.
3951 *
3952 * @returns Pointer to the PML4 page.
3953 * @param pPGM Pointer to the PGM instance data.
3954 */
3955DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3956{
3957#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3958 PX86PML4 pGuestPml4;
3959 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3960 AssertRCReturn(rc, NULL);
3961 return pGuestPml4;
3962#else
3963 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3964 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3965#endif
3966}
3967
3968
3969/**
3970 * Gets the pointer to a page map level-4 entry.
3971 *
3972 * @returns Pointer to the PML4 entry.
3973 * @param pPGM Pointer to the PGM instance data.
3974 * @param iPml4 The index.
3975 */
3976DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3977{
3978#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3979 PX86PML4 pGuestPml4;
3980 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3981 AssertRCReturn(rc, NULL);
3982 return &pGuestPml4->a[iPml4];
3983#else
3984 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3985 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3986#endif
3987}
3988
3989
3990/**
3991 * Gets a page map level-4 entry.
3992 *
3993 * @returns The PML4 entry.
3994 * @param pPGM Pointer to the PGM instance data.
3995 * @param iPml4 The index.
3996 */
3997DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3998{
3999#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4000 PX86PML4 pGuestPml4;
4001 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4002 if (RT_FAILURE(rc))
4003 {
4004 X86PML4E ZeroPml4e = {0};
4005 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4006 }
4007 return pGuestPml4->a[iPml4];
4008#else
4009 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4010 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4011#endif
4012}
4013
4014
4015/**
4016 * Gets the page directory pointer entry for the specified address.
4017 *
4018 * @returns Pointer to the page directory pointer entry in question.
4019 * @returns NULL if the page directory is not present or on an invalid page.
4020 * @param pPGM Pointer to the PGM instance data.
4021 * @param GCPtr The address.
4022 * @param ppPml4e Page Map Level-4 Entry (out)
4023 */
4024DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4025{
4026 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4027 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4028 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4029 if (pPml4e->n.u1Present)
4030 {
4031 PX86PDPT pPdpt;
4032 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4033 AssertRCReturn(rc, NULL);
4034
4035 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4036 return &pPdpt->a[iPdPt];
4037 }
4038 return NULL;
4039}
4040
4041
4042/**
4043 * Gets the page directory entry for the specified address.
4044 *
4045 * @returns The page directory entry in question.
4046 * @returns A non-present entry if the page directory is not present or on an invalid page.
4047 * @param pPGM Pointer to the PGM instance data.
4048 * @param GCPtr The address.
4049 * @param ppPml4e Page Map Level-4 Entry (out)
4050 * @param pPdpe Page directory pointer table entry (out)
4051 */
4052DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4053{
4054 X86PDEPAE ZeroPde = {0};
4055 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4056 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4057 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4058 if (pPml4e->n.u1Present)
4059 {
4060 PCX86PDPT pPdptTemp;
4061 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4062 AssertRCReturn(rc, ZeroPde);
4063
4064 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4065 *pPdpe = pPdptTemp->a[iPdPt];
4066 if (pPdptTemp->a[iPdPt].n.u1Present)
4067 {
4068 PCX86PDPAE pPD;
4069 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4070 AssertRCReturn(rc, ZeroPde);
4071
4072 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4073 return pPD->a[iPD];
4074 }
4075 }
4076
4077 return ZeroPde;
4078}
4079
4080
4081/**
4082 * Gets the page directory entry for the specified address.
4083 *
4084 * @returns The page directory entry in question.
4085 * @returns A non-present entry if the page directory is not present or on an invalid page.
4086 * @param pPGM Pointer to the PGM instance data.
4087 * @param GCPtr The address.
4088 */
4089DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4090{
4091 X86PDEPAE ZeroPde = {0};
4092 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4093 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4094 if (pGuestPml4->a[iPml4].n.u1Present)
4095 {
4096 PCX86PDPT pPdptTemp;
4097 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4098 AssertRCReturn(rc, ZeroPde);
4099
4100 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4101 if (pPdptTemp->a[iPdPt].n.u1Present)
4102 {
4103 PCX86PDPAE pPD;
4104 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4105 AssertRCReturn(rc, ZeroPde);
4106
4107 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4108 return pPD->a[iPD];
4109 }
4110 }
4111 return ZeroPde;
4112}
4113
4114
4115/**
4116 * Gets the page directory entry for the specified address.
4117 *
4118 * @returns Pointer to the page directory entry in question.
4119 * @returns NULL if the page directory is not present or on an invalid page.
4120 * @param pPGM Pointer to the PGM instance data.
4121 * @param GCPtr The address.
4122 */
4123DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4124{
4125 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4126 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4127 if (pGuestPml4->a[iPml4].n.u1Present)
4128 {
4129 PCX86PDPT pPdptTemp;
4130 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4131 AssertRCReturn(rc, NULL);
4132
4133 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4134 if (pPdptTemp->a[iPdPt].n.u1Present)
4135 {
4136 PX86PDPAE pPD;
4137 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4138 AssertRCReturn(rc, NULL);
4139
4140 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4141 return &pPD->a[iPD];
4142 }
4143 }
4144 return NULL;
4145}
4146
4147
4148/**
4149 * Gets the GUEST page directory pointer for the specified address.
4150 *
4151 * @returns The page directory in question.
4152 * @returns NULL if the page directory is not present or on an invalid page.
4153 * @param pPGM Pointer to the PGM instance data.
4154 * @param GCPtr The address.
4155 * @param ppPml4e Page Map Level-4 Entry (out)
4156 * @param pPdpe Page directory pointer table entry (out)
4157 * @param piPD Receives the index into the returned page directory
4158 */
4159DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4160{
4161 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4162 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4163 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4164 if (pPml4e->n.u1Present)
4165 {
4166 PCX86PDPT pPdptTemp;
4167 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4168 AssertRCReturn(rc, NULL);
4169
4170 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4171 *pPdpe = pPdptTemp->a[iPdPt];
4172 if (pPdptTemp->a[iPdPt].n.u1Present)
4173 {
4174 PX86PDPAE pPD;
4175 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4176 AssertRCReturn(rc, NULL);
4177
4178 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4179 return pPD;
4180 }
4181 }
4182 return 0;
4183}
4184
4185#endif /* !IN_RC */
4186
4187
4188/**
4189 * Gets the shadow page directory, 32-bit.
4190 *
4191 * @returns Pointer to the shadow 32-bit PD.
4192 * @param pPGM Pointer to the PGM instance data.
4193 */
4194DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4195{
4196#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4197 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4198#else
4199# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4200 PX86PD pShwPd;
4201 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4202 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4203 AssertRCReturn(rc, NULL);
4204 return pShwPd;
4205# else
4206 return pPGM->CTX_SUFF(pShw32BitPd);
4207# endif
4208#endif
4209}
4210
4211
4212/**
4213 * Gets the shadow page directory entry for the specified address, 32-bit.
4214 *
4215 * @returns Shadow 32-bit PDE.
4216 * @param pPGM Pointer to the PGM instance data.
4217 * @param GCPtr The address.
4218 */
4219DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4220{
4221 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4222
4223 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4224 if (!pShwPde)
4225 {
4226 X86PDE ZeroPde = {0};
4227 return ZeroPde;
4228 }
4229 return pShwPde->a[iPd];
4230}
4231
4232
4233/**
4234 * Gets the pointer to the shadow page directory entry for the specified
4235 * address, 32-bit.
4236 *
4237 * @returns Pointer to the shadow 32-bit PDE.
4238 * @param pPGM Pointer to the PGM instance data.
4239 * @param GCPtr The address.
4240 */
4241DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4242{
4243 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4244
4245 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4246 AssertReturn(pPde, NULL);
4247 return &pPde->a[iPd];
4248}
4249
4250
4251/**
4252 * Gets the shadow page pointer table, PAE.
4253 *
4254 * @returns Pointer to the shadow PAE PDPT.
4255 * @param pPGM Pointer to the PGM instance data.
4256 */
4257DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4258{
4259#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4260 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4261#else
4262# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4263 PX86PDPT pShwPdpt;
4264 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4265 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4266 AssertRCReturn(rc, 0);
4267 return pShwPdpt;
4268# else
4269 return pPGM->CTX_SUFF(pShwPaePdpt);
4270# endif
4271#endif
4272}
4273
4274
4275/**
4276 * Gets the shadow page directory for the specified address, PAE.
4277 *
4278 * @returns Pointer to the shadow PD.
4279 * @param pPGM Pointer to the PGM instance data.
4280 * @param GCPtr The address.
4281 */
4282DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4283{
4284#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4285 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4286 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4287
4288 if (!pPdpt->a[iPdpt].n.u1Present)
4289 return NULL;
4290
4291 /* Fetch the pgm pool shadow descriptor. */
4292 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4293 AssertReturn(pShwPde, NULL);
4294
4295 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4296#else
4297 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4298# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4299 PX86PDPAE pPD;
4300 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4301 AssertRCReturn(rc, 0);
4302 return pPD;
4303# else
4304 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4305 Assert(pPD);
4306 return pPD;
4307# endif
4308#endif
4309}
4310
4311/**
4312 * Gets the shadow page directory for the specified address, PAE.
4313 *
4314 * @returns Pointer to the shadow PD.
4315 * @param pPGM Pointer to the PGM instance data.
4316 * @param GCPtr The address.
4317 */
4318DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4319{
4320#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4321 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4322
4323 if (!pPdpt->a[iPdpt].n.u1Present)
4324 return NULL;
4325
4326 /* Fetch the pgm pool shadow descriptor. */
4327 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4328 AssertReturn(pShwPde, NULL);
4329
4330 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4331#else
4332 AssertFailed();
4333 return NULL;
4334#endif
4335}
4336
4337/**
4338 * Gets the shadow page directory entry, PAE.
4339 *
4340 * @returns PDE.
4341 * @param pPGM Pointer to the PGM instance data.
4342 * @param GCPtr The address.
4343 */
4344DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4345{
4346 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4347
4348 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4349 if (!pShwPde)
4350 {
4351 X86PDEPAE ZeroPde = {0};
4352 return ZeroPde;
4353 }
4354 return pShwPde->a[iPd];
4355}
4356
4357
4358/**
4359 * Gets the pointer to the shadow page directory entry for an address, PAE.
4360 *
4361 * @returns Pointer to the PDE.
4362 * @param pPGM Pointer to the PGM instance data.
4363 * @param GCPtr The address.
4364 */
4365DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4366{
4367 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4368
4369 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4370 AssertReturn(pPde, NULL);
4371 return &pPde->a[iPd];
4372}
4373
4374#ifndef IN_RC
4375/**
4376 * Gets the shadow page map level-4 pointer.
4377 *
4378 * @returns Pointer to the shadow PML4.
4379 * @param pPGM Pointer to the PGM instance data.
4380 */
4381DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4382{
4383#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4384 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4385#else
4386# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4387 PX86PML4 pShwPml4;
4388 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4389 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4390 AssertRCReturn(rc, 0);
4391 return pShwPml4;
4392# else
4393 Assert(pPGM->CTX_SUFF(pShwRoot));
4394 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4395# endif
4396#endif
4397}
4398
4399
4400/**
4401 * Gets the shadow page map level-4 entry for the specified address.
4402 *
4403 * @returns The entry.
4404 * @param pPGM Pointer to the PGM instance data.
4405 * @param GCPtr The address.
4406 */
4407DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4408{
4409 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4410 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4411
4412 if (!pShwPml4)
4413 {
4414 X86PML4E ZeroPml4e = {0};
4415 return ZeroPml4e;
4416 }
4417 return pShwPml4->a[iPml4];
4418}
4419
4420
4421/**
4422 * Gets the pointer to the specified shadow page map level-4 entry.
4423 *
4424 * @returns The entry.
4425 * @param pPGM Pointer to the PGM instance data.
4426 * @param iPml4 The PML4 index.
4427 */
4428DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4429{
4430 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4431 if (!pShwPml4)
4432 return NULL;
4433 return &pShwPml4->a[iPml4];
4434}
4435
4436
4437/**
4438 * Gets the GUEST page directory pointer for the specified address.
4439 *
4440 * @returns The page directory in question.
4441 * @returns NULL if the page directory is not present or on an invalid page.
4442 * @param pPGM Pointer to the PGM instance data.
4443 * @param GCPtr The address.
4444 * @param piPD Receives the index into the returned page directory
4445 */
4446DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4447{
4448 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4449 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4450 if (pGuestPml4->a[iPml4].n.u1Present)
4451 {
4452 PCX86PDPT pPdptTemp;
4453 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4454 AssertRCReturn(rc, NULL);
4455
4456 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4457 if (pPdptTemp->a[iPdPt].n.u1Present)
4458 {
4459 PX86PDPAE pPD;
4460 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4461 AssertRCReturn(rc, NULL);
4462
4463 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4464 return pPD;
4465 }
4466 }
4467 return NULL;
4468}
4469
4470#endif /* !IN_RC */
4471
4472/**
4473 * Checks if any of the specified page flags are set for the given page.
4474 *
4475 * @returns true if any of the flags are set.
4476 * @returns false if all the flags are clear.
4477 * @param pPGM PGM handle.
4478 * @param GCPhys The GC physical address.
4479 * @param fFlags The flags to check for.
4480 */
4481DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4482{
4483 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4484 return pPage
4485 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4486}
4487
4488
4489/**
4490 * Gets the page state for a physical handler.
4491 *
4492 * @returns The physical handler page state.
4493 * @param pCur The physical handler in question.
4494 */
4495DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4496{
4497 switch (pCur->enmType)
4498 {
4499 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4500 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4501
4502 case PGMPHYSHANDLERTYPE_MMIO:
4503 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4504 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4505
4506 default:
4507 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4508 }
4509}
4510
4511
4512/**
4513 * Gets the page state for a virtual handler.
4514 *
4515 * @returns The virtual handler page state.
4516 * @param pCur The virtual handler in question.
4517 * @remarks This should never be used on a hypervisor access handler.
4518 */
4519DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4520{
4521 switch (pCur->enmType)
4522 {
4523 case PGMVIRTHANDLERTYPE_WRITE:
4524 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4525 case PGMVIRTHANDLERTYPE_ALL:
4526 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4527 default:
4528 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4529 }
4530}
4531
4532
4533/**
4534 * Clears one physical page of a virtual handler
4535 *
4536 * @param pPGM Pointer to the PGM instance.
4537 * @param pCur Virtual handler structure
4538 * @param iPage Physical page index
4539 *
4540 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4541 * need to care about other handlers in the same page.
4542 */
4543DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4544{
4545 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4546
4547 /*
4548 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4549 */
4550#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4551 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4552 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4553 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4554#endif
4555 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4556 {
4557 /* We're the head of the alias chain. */
4558 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4559#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4560 AssertReleaseMsg(pRemove != NULL,
4561 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4562 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4563 AssertReleaseMsg(pRemove == pPhys2Virt,
4564 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4565 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4566 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4567 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4568#endif
4569 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4570 {
4571 /* Insert the next list in the alias chain into the tree. */
4572 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4573#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4574 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4575 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4576 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4577#endif
4578 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4579 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4580 AssertRelease(fRc);
4581 }
4582 }
4583 else
4584 {
4585 /* Locate the previous node in the alias chain. */
4586 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4587#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4588 AssertReleaseMsg(pPrev != pPhys2Virt,
4589 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4590 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4591#endif
4592 for (;;)
4593 {
4594 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4595 if (pNext == pPhys2Virt)
4596 {
4597 /* unlink. */
4598 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4599 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4600 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4601 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4602 else
4603 {
4604 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4605 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4606 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4607 }
4608 break;
4609 }
4610
4611 /* next */
4612 if (pNext == pPrev)
4613 {
4614#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4615 AssertReleaseMsg(pNext != pPrev,
4616 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4617 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4618#endif
4619 break;
4620 }
4621 pPrev = pNext;
4622 }
4623 }
4624 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4625 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4626 pPhys2Virt->offNextAlias = 0;
4627 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4628
4629 /*
4630 * Clear the ram flags for this page.
4631 */
4632 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4633 AssertReturnVoid(pPage);
4634 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4635}
4636
4637
4638/**
4639 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4640 *
4641 * @returns Pointer to the shadow page structure.
4642 * @param pPool The pool.
4643 * @param HCPhys The HC physical address of the shadow page.
4644 */
4645DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4646{
4647 /*
4648 * Look up the page.
4649 */
4650 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4651 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4652 return pPage;
4653}
4654
4655
4656/**
4657 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4658 *
4659 * @returns Pointer to the shadow page structure.
4660 * @param pPool The pool.
4661 * @param idx The pool page index.
4662 */
4663DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4664{
4665 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4666 return &pPool->aPages[idx];
4667}
4668
4669
4670#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4671/**
4672 * Clear references to guest physical memory.
4673 *
4674 * @param pPool The pool.
4675 * @param pPoolPage The pool page.
4676 * @param pPhysPage The physical guest page tracking structure.
4677 */
4678DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4679{
4680 /*
4681 * Just deal with the simple case here.
4682 */
4683# ifdef LOG_ENABLED
4684 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4685# endif
4686 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4687 if (cRefs == 1)
4688 {
4689 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4690 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4691 }
4692 else
4693 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4694 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4695}
4696#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4697
4698
4699#ifdef PGMPOOL_WITH_CACHE
4700/**
4701 * Moves the page to the head of the age list.
4702 *
4703 * This is done when the cached page is used in one way or another.
4704 *
4705 * @param pPool The pool.
4706 * @param pPage The cached page.
4707 * @todo inline in PGMInternal.h!
4708 */
4709DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4710{
4711 /*
4712 * Move to the head of the age list.
4713 */
4714 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4715 {
4716 /* unlink */
4717 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4718 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4719 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4720 else
4721 pPool->iAgeTail = pPage->iAgePrev;
4722
4723 /* insert at head */
4724 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4725 pPage->iAgeNext = pPool->iAgeHead;
4726 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4727 pPool->iAgeHead = pPage->idx;
4728 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4729 }
4730}
4731#endif /* PGMPOOL_WITH_CACHE */
4732
4733#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4734/**
4735 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4736 *
4737 * @returns VBox status code.
4738 * @param pVM VM Handle.
4739 * @param pPage PGM pool page
4740 */
4741DECLINLINE(int) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4742{
4743 Assert(!pPage->fLocked);
4744 pPage->fLocked = true;
4745 return VINF_SUCCESS;
4746}
4747
4748/**
4749 * Unlocks a page to allow flushing again
4750 *
4751 * @returns VBox status code.
4752 * @param pVM VM Handle.
4753 * @param pPage PGM pool page
4754 */
4755DECLINLINE(int) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4756{
4757 Assert(pPage->fLocked);
4758 pPage->fLocked = false;
4759 return VINF_SUCCESS;
4760}
4761
4762/**
4763 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4764 *
4765 * @returns VBox status code.
4766 * @param pPage PGM pool page
4767 */
4768DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4769{
4770 if (pPage->fLocked)
4771 {
4772 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4773 if (pPage->cModifications)
4774 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4775 return true;
4776 }
4777 return false;
4778}
4779#endif
4780
4781/**
4782 * Tells if mappings are to be put into the shadow page table or not
4783 *
4784 * @returns boolean result
4785 * @param pVM VM handle.
4786 */
4787
4788DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4789{
4790#ifdef IN_RING0
4791 /* There are no mappings in VT-x and AMD-V mode. */
4792 Assert(pPGM->fDisableMappings);
4793 return false;
4794#else
4795 return !pPGM->fDisableMappings;
4796#endif
4797}
4798
4799/** @} */
4800
4801#endif
4802
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