VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17327

Last change on this file since 17327 was 17316, checked in by vboxsync, 16 years ago

PGM: Use %R[pgmpage] instead of logging PGMPAGE::HCPhys.
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1/* $Id: PGMInternal.h 17316 2009-03-03 20:04:53Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** Mark a dynamic map entry (PGMDynMapHCPage) as locked. */
188#define PGM_PTFLAGS_DYN_LOCKED RT_BIT(9)
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGM
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page when in GC does nothing in HC.
333 *
334 * @param GCVirt The virtual address of the page to invalidate.
335 */
336#ifdef IN_RC
337# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
338#elif defined(IN_RING0)
339# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340#else
341# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
342#endif
343
344/** @def PGM_INVL_BIG_PG
345 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
346 *
347 * @param GCVirt The virtual address within the page directory to invalidate.
348 */
349#ifdef IN_RC
350# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
351#elif defined(IN_RING0)
352# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353#else
354# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
355#endif
356
357/** @def PGM_INVL_GUEST_TLBS()
358 * Invalidates all guest TLBs.
359 */
360#ifdef IN_RC
361# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
362#elif defined(IN_RING0)
363# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364#else
365# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
366#endif
367
368
369/**
370 * Structure for tracking GC Mappings.
371 *
372 * This structure is used by linked list in both GC and HC.
373 */
374typedef struct PGMMAPPING
375{
376 /** Pointer to next entry. */
377 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378 /** Pointer to next entry. */
379 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380 /** Pointer to next entry. */
381 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382 /** Indicate whether this entry is finalized. */
383 bool fFinalized;
384 /** Start Virtual address. */
385 RTGCPTR GCPtr;
386 /** Last Virtual address (inclusive). */
387 RTGCPTR GCPtrLast;
388 /** Range size (bytes). */
389 RTGCPTR cb;
390 /** Pointer to relocation callback function. */
391 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392 /** User argument to the callback. */
393 R3PTRTYPE(void *) pvUser;
394 /** Mapping description / name. For easing debugging. */
395 R3PTRTYPE(const char *) pszDesc;
396 /** Number of page tables. */
397 uint32_t cPTs;
398#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
399 uint32_t uPadding1; /**< Alignment padding. */
400#endif
401 /** Array of page table mapping data. Each entry
402 * describes one page table. The array can be longer
403 * than the declared length.
404 */
405 struct
406 {
407 /** The HC physical address of the page table. */
408 RTHCPHYS HCPhysPT;
409 /** The HC physical address of the first PAE page table. */
410 RTHCPHYS HCPhysPaePT0;
411 /** The HC physical address of the second PAE page table. */
412 RTHCPHYS HCPhysPaePT1;
413 /** The HC virtual address of the 32-bit page table. */
414 R3PTRTYPE(PX86PT) pPTR3;
415 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
416 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
417 /** The GC virtual address of the 32-bit page table. */
418 RCPTRTYPE(PX86PT) pPTRC;
419 /** The GC virtual address of the two PAE page table. */
420 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
421 /** The GC virtual address of the 32-bit page table. */
422 R0PTRTYPE(PX86PT) pPTR0;
423 /** The GC virtual address of the two PAE page table. */
424 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
425 } aPTs[1];
426} PGMMAPPING;
427/** Pointer to structure for tracking GC Mappings. */
428typedef struct PGMMAPPING *PPGMMAPPING;
429
430
431/**
432 * Physical page access handler structure.
433 *
434 * This is used to keep track of physical address ranges
435 * which are being monitored in some kind of way.
436 */
437typedef struct PGMPHYSHANDLER
438{
439 AVLROGCPHYSNODECORE Core;
440 /** Access type. */
441 PGMPHYSHANDLERTYPE enmType;
442 /** Number of pages to update. */
443 uint32_t cPages;
444 /** Pointer to R3 callback function. */
445 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
446 /** User argument for R3 handlers. */
447 R3PTRTYPE(void *) pvUserR3;
448 /** Pointer to R0 callback function. */
449 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
450 /** User argument for R0 handlers. */
451 R0PTRTYPE(void *) pvUserR0;
452 /** Pointer to GC callback function. */
453 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
454 /** User argument for RC handlers. */
455 RCPTRTYPE(void *) pvUserRC;
456 /** Description / Name. For easing debugging. */
457 R3PTRTYPE(const char *) pszDesc;
458#ifdef VBOX_WITH_STATISTICS
459 /** Profiling of this handler. */
460 STAMPROFILE Stat;
461#endif
462} PGMPHYSHANDLER;
463/** Pointer to a physical page access handler structure. */
464typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
465
466
467/**
468 * Cache node for the physical addresses covered by a virtual handler.
469 */
470typedef struct PGMPHYS2VIRTHANDLER
471{
472 /** Core node for the tree based on physical ranges. */
473 AVLROGCPHYSNODECORE Core;
474 /** Offset from this struct to the PGMVIRTHANDLER structure. */
475 int32_t offVirtHandler;
476 /** Offset of the next alias relative to this one.
477 * Bit 0 is used for indicating whether we're in the tree.
478 * Bit 1 is used for indicating that we're the head node.
479 */
480 int32_t offNextAlias;
481} PGMPHYS2VIRTHANDLER;
482/** Pointer to a phys to virtual handler structure. */
483typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
484
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the tree. */
487#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
488/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489 * node is in the head of an alias chain.
490 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
491#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
492/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
493#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
494
495
496/**
497 * Virtual page access handler structure.
498 *
499 * This is used to keep track of virtual address ranges
500 * which are being monitored in some kind of way.
501 */
502typedef struct PGMVIRTHANDLER
503{
504 /** Core node for the tree based on virtual ranges. */
505 AVLROGCPTRNODECORE Core;
506 /** Size of the range (in bytes). */
507 RTGCPTR cb;
508 /** Number of cache pages. */
509 uint32_t cPages;
510 /** Access type. */
511 PGMVIRTHANDLERTYPE enmType;
512 /** Pointer to the RC callback function. */
513 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
514#if HC_ARCH_BITS == 64
515 RTRCPTR padding;
516#endif
517 /** Pointer to the R3 callback function for invalidation. */
518 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
519 /** Pointer to the R3 callback function. */
520 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
521 /** Description / Name. For easing debugging. */
522 R3PTRTYPE(const char *) pszDesc;
523#ifdef VBOX_WITH_STATISTICS
524 /** Profiling of this handler. */
525 STAMPROFILE Stat;
526#endif
527 /** Array of cached physical addresses for the monitored ranged. */
528 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
529} PGMVIRTHANDLER;
530/** Pointer to a virtual page access handler structure. */
531typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
532
533
534/**
535 * Page type.
536 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
537 * @todo convert to \#defines.
538 */
539typedef enum PGMPAGETYPE
540{
541 /** The usual invalid zero entry. */
542 PGMPAGETYPE_INVALID = 0,
543 /** RAM page. (RWX) */
544 PGMPAGETYPE_RAM,
545 /** MMIO2 page. (RWX) */
546 PGMPAGETYPE_MMIO2,
547 /** MMIO2 page aliased over an MMIO page. (RWX)
548 * See PGMHandlerPhysicalPageAlias(). */
549 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
550 /** Shadowed ROM. (RWX) */
551 PGMPAGETYPE_ROM_SHADOW,
552 /** ROM page. (R-X) */
553 PGMPAGETYPE_ROM,
554 /** MMIO page. (---) */
555 PGMPAGETYPE_MMIO,
556 /** End of valid entries. */
557 PGMPAGETYPE_END
558} PGMPAGETYPE;
559AssertCompile(PGMPAGETYPE_END <= 7);
560
561/** @name Page type predicates.
562 * @{ */
563#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
565#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
566#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
567#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
568/** @} */
569
570
571/**
572 * A Physical Guest Page tracking structure.
573 *
574 * The format of this structure is complicated because we have to fit a lot
575 * of information into as few bits as possible. The format is also subject
576 * to change (there is one comming up soon). Which means that for we'll be
577 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
578 * accessess to the structure.
579 */
580typedef struct PGMPAGE
581{
582 /** The physical address and a whole lot of other stuff. All bits are used! */
583#ifdef VBOX_WITH_NEW_PHYS_CODE
584 RTHCPHYS HCPhysX;
585#else
586 RTHCPHYS HCPhys;
587#define HCPhysX HCPhys /**< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. */
588#endif
589 /** The page state. */
590 uint32_t u2StateX : 2;
591 /** Flag indicating that a write monitored page was written to when set. */
592 uint32_t fWrittenToX : 1;
593 /** For later. */
594 uint32_t fSomethingElse : 1;
595 /** The Page ID.
596 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
597 * The HCPhysX will then be 100% static. */
598 uint32_t idPageX : 28;
599 /** The page type (PGMPAGETYPE). */
600 uint32_t u3Type : 3;
601 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
602 uint32_t u2HandlerPhysStateX : 2;
603 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
604 uint32_t u2HandlerVirtStateX : 2;
605 uint32_t u29B : 25;
606} PGMPAGE;
607AssertCompileSize(PGMPAGE, 16);
608/** Pointer to a physical guest page. */
609typedef PGMPAGE *PPGMPAGE;
610/** Pointer to a const physical guest page. */
611typedef const PGMPAGE *PCPGMPAGE;
612/** Pointer to a physical guest page pointer. */
613typedef PPGMPAGE *PPPGMPAGE;
614
615
616/**
617 * Clears the page structure.
618 * @param pPage Pointer to the physical guest page tracking structure.
619 */
620#define PGM_PAGE_CLEAR(pPage) \
621 do { \
622 (pPage)->HCPhysX = 0; \
623 (pPage)->u2StateX = 0; \
624 (pPage)->fWrittenToX = 0; \
625 (pPage)->fSomethingElse = 0; \
626 (pPage)->idPageX = 0; \
627 (pPage)->u3Type = 0; \
628 (pPage)->u29B = 0; \
629 } while (0)
630
631/**
632 * Initializes the page structure.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
636 do { \
637 (pPage)->HCPhysX = (_HCPhys); \
638 (pPage)->u2StateX = (_uState); \
639 (pPage)->fWrittenToX = 0; \
640 (pPage)->fSomethingElse = 0; \
641 (pPage)->idPageX = (_idPage); \
642 /*(pPage)->u3Type = (_uType); - later */ \
643 PGM_PAGE_SET_TYPE(pPage, _uType); \
644 (pPage)->u29B = 0; \
645 } while (0)
646
647/**
648 * Initializes the page structure of a ZERO page.
649 * @param pPage Pointer to the physical guest page tracking structure.
650 */
651#ifdef VBOX_WITH_NEW_PHYS_CODE
652# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
653 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
654#else
655# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
656 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
657#endif
658/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
659# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
660 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
661
662
663/** @name The Page state, PGMPAGE::u2StateX.
664 * @{ */
665/** The zero page.
666 * This is a per-VM page that's never ever mapped writable. */
667#define PGM_PAGE_STATE_ZERO 0
668/** A allocated page.
669 * This is a per-VM page allocated from the page pool (or wherever
670 * we get MMIO2 pages from if the type is MMIO2).
671 */
672#define PGM_PAGE_STATE_ALLOCATED 1
673/** A allocated page that's being monitored for writes.
674 * The shadow page table mappings are read-only. When a write occurs, the
675 * fWrittenTo member is set, the page remapped as read-write and the state
676 * moved back to allocated. */
677#define PGM_PAGE_STATE_WRITE_MONITORED 2
678/** The page is shared, aka. copy-on-write.
679 * This is a page that's shared with other VMs. */
680#define PGM_PAGE_STATE_SHARED 3
681/** @} */
682
683
684/**
685 * Gets the page state.
686 * @returns page state (PGM_PAGE_STATE_*).
687 * @param pPage Pointer to the physical guest page tracking structure.
688 */
689#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
690
691/**
692 * Sets the page state.
693 * @param pPage Pointer to the physical guest page tracking structure.
694 * @param _uState The new page state.
695 */
696#define PGM_PAGE_SET_STATE(pPage, _uState) \
697 do { (pPage)->u2StateX = (_uState); } while (0)
698
699
700/**
701 * Gets the host physical address of the guest page.
702 * @returns host physical address (RTHCPHYS).
703 * @param pPage Pointer to the physical guest page tracking structure.
704 */
705#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
706
707/**
708 * Sets the host physical address of the guest page.
709 * @param pPage Pointer to the physical guest page tracking structure.
710 * @param _HCPhys The new host physical address.
711 */
712#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
713 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
714 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
715
716/**
717 * Get the Page ID.
718 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
719 * @param pPage Pointer to the physical guest page tracking structure.
720 */
721#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
722/* later:
723#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
724 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
725*/
726/**
727 * Sets the Page ID.
728 * @param pPage Pointer to the physical guest page tracking structure.
729 */
730#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
731/* later:
732#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
733 | ((_idPage) & 0xfff) \
734 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
735*/
736
737/**
738 * Get the Chunk ID.
739 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
743/* later:
744#if GMM_CHUNKID_SHIFT == 12
745# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
746#elif GMM_CHUNKID_SHIFT > 12
747# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
748#elif GMM_CHUNKID_SHIFT < 12
749# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
750 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
751#else
752# error "GMM_CHUNKID_SHIFT isn't defined or something."
753#endif
754*/
755
756/**
757 * Get the index of the page within the allocaiton chunk.
758 * @returns The page index.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
762/* later:
763#if GMM_CHUNKID_SHIFT <= 12
764# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
765#else
766# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
767 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
768#endif
769*/
770
771
772/**
773 * Gets the page type.
774 * @returns The page type.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 */
777#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
778
779/**
780 * Sets the page type.
781 * @param pPage Pointer to the physical guest page tracking structure.
782 * @param _enmType The new page type (PGMPAGETYPE).
783 */
784#ifdef VBOX_WITH_NEW_PHYS_CODE
785#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
786 do { (pPage)->u3Type = (_enmType); } while (0)
787#else
788#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
789 do { \
790 (pPage)->u3Type = (_enmType); \
791 if ((_enmType) == PGMPAGETYPE_ROM) \
792 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM; \
793 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
794 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
795 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
796 (pPage)->HCPhysX |= MM_RAM_FLAGS_MMIO2; \
797 } while (0)
798#endif
799
800
801/**
802 * Checks if the page is 'reserved'.
803 * @returns true/false.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
807
808/**
809 * Checks if the page is marked for MMIO.
810 * @returns true/false.
811 * @param pPage Pointer to the physical guest page tracking structure.
812 */
813#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
814
815/**
816 * Checks if the page is backed by the ZERO page.
817 * @returns true/false.
818 * @param pPage Pointer to the physical guest page tracking structure.
819 */
820#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
821
822/**
823 * Checks if the page is backed by a SHARED page.
824 * @returns true/false.
825 * @param pPage Pointer to the physical guest page tracking structure.
826 */
827#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
828
829
830/**
831 * Marks the paget as written to (for GMM change monitoring).
832 * @param pPage Pointer to the physical guest page tracking structure.
833 */
834#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
835
836/**
837 * Clears the written-to indicator.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
841
842/**
843 * Checks if the page was marked as written-to.
844 * @returns true/false.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
848
849
850/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
851 *
852 * @remarks The values are assigned in order of priority, so we can calculate
853 * the correct state for a page with different handlers installed.
854 * @{ */
855/** No handler installed. */
856#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
857/** Monitoring is temporarily disabled. */
858#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
859/** Write access is monitored. */
860#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
861/** All access is monitored. */
862#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
863/** @} */
864
865/**
866 * Gets the physical access handler state of a page.
867 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
871
872/**
873 * Sets the physical access handler state of a page.
874 * @param pPage Pointer to the physical guest page tracking structure.
875 * @param _uState The new state value.
876 */
877#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
878 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
879
880/**
881 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
882 * @returns true/false
883 * @param pPage Pointer to the physical guest page tracking structure.
884 */
885#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
886
887/**
888 * Checks if the page has any active physical access handlers.
889 * @returns true/false
890 * @param pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
893
894
895/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
896 *
897 * @remarks The values are assigned in order of priority, so we can calculate
898 * the correct state for a page with different handlers installed.
899 * @{ */
900/** No handler installed. */
901#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
902/* 1 is reserved so the lineup is identical with the physical ones. */
903/** Write access is monitored. */
904#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
905/** All access is monitored. */
906#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
907/** @} */
908
909/**
910 * Gets the virtual access handler state of a page.
911 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
912 * @param pPage Pointer to the physical guest page tracking structure.
913 */
914#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
915
916/**
917 * Sets the virtual access handler state of a page.
918 * @param pPage Pointer to the physical guest page tracking structure.
919 * @param _uState The new state value.
920 */
921#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
922 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
923
924/**
925 * Checks if the page has any virtual access handlers.
926 * @returns true/false
927 * @param pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
930
931/**
932 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
933 * virtual handlers.
934 * @returns true/false
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
938
939
940
941/**
942 * Checks if the page has any access handlers, including temporarily disabled ones.
943 * @returns true/false
944 * @param pPage Pointer to the physical guest page tracking structure.
945 */
946#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
947 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
948 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
949
950/**
951 * Checks if the page has any active access handlers.
952 * @returns true/false
953 * @param pPage Pointer to the physical guest page tracking structure.
954 */
955#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
956 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
957 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
958
959/**
960 * Checks if the page has any active access handlers catching all accesses.
961 * @returns true/false
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
965 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
966 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
967
968
969
970
971/** @def PGM_PAGE_GET_TRACKING
972 * Gets the packed shadow page pool tracking data associated with a guest page.
973 * @returns uint16_t containing the data.
974 * @param pPage Pointer to the physical guest page tracking structure.
975 */
976#define PGM_PAGE_GET_TRACKING(pPage) \
977 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
978
979/** @def PGM_PAGE_SET_TRACKING
980 * Sets the packed shadow page pool tracking data associated with a guest page.
981 * @param pPage Pointer to the physical guest page tracking structure.
982 * @param u16TrackingData The tracking data to store.
983 */
984#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
985 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
986
987/** @def PGM_PAGE_GET_TD_CREFS
988 * Gets the @a cRefs tracking data member.
989 * @returns cRefs.
990 * @param pPage Pointer to the physical guest page tracking structure.
991 */
992#define PGM_PAGE_GET_TD_CREFS(pPage) \
993 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
994
995#define PGM_PAGE_GET_TD_IDX(pPage) \
996 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
997
998/**
999 * Ram range for GC Phys to HC Phys conversion.
1000 *
1001 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1002 * conversions too, but we'll let MM handle that for now.
1003 *
1004 * This structure is used by linked lists in both GC and HC.
1005 */
1006typedef struct PGMRAMRANGE
1007{
1008 /** Pointer to the next RAM range - for R3. */
1009 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1010 /** Pointer to the next RAM range - for R0. */
1011 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1012 /** Pointer to the next RAM range - for RC. */
1013 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1014 /** Pointer alignment. */
1015 RTRCPTR RCPtrAlignment;
1016 /** Start of the range. Page aligned. */
1017 RTGCPHYS GCPhys;
1018 /** Last address in the range (inclusive). Page aligned (-1). */
1019 RTGCPHYS GCPhysLast;
1020 /** Size of the range. (Page aligned of course). */
1021 RTGCPHYS cb;
1022 /** MM_RAM_* flags */
1023 uint32_t fFlags;
1024 uint32_t u32Alignment; /**< alignment. */
1025#ifndef VBOX_WITH_NEW_PHYS_CODE
1026 /** R3 virtual lookup ranges for chunks.
1027 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1028 * @remarks This is occationally accessed from ring-0!! (not darwin) */
1029# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1030 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1031# else
1032 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1033# endif
1034#endif
1035 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1036 R3PTRTYPE(void *) pvR3;
1037 /** The range description. */
1038 R3PTRTYPE(const char *) pszDesc;
1039
1040 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1041#ifdef VBOX_WITH_NEW_PHYS_CODE
1042 uint32_t au32Reserved[2];
1043#elif HC_ARCH_BITS == 32
1044 uint32_t au32Reserved[1];
1045#endif
1046
1047 /** Array of physical guest page tracking structures. */
1048 PGMPAGE aPages[1];
1049} PGMRAMRANGE;
1050/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1051typedef PGMRAMRANGE *PPGMRAMRANGE;
1052
1053/** Return hc ptr corresponding to the ram range and physical offset */
1054#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1055 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1056 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1057
1058/**
1059 * Per page tracking structure for ROM image.
1060 *
1061 * A ROM image may have a shadow page, in which case we may have
1062 * two pages backing it. This structure contains the PGMPAGE for
1063 * both while PGMRAMRANGE have a copy of the active one. It is
1064 * important that these aren't out of sync in any regard other
1065 * than page pool tracking data.
1066 */
1067typedef struct PGMROMPAGE
1068{
1069 /** The page structure for the virgin ROM page. */
1070 PGMPAGE Virgin;
1071 /** The page structure for the shadow RAM page. */
1072 PGMPAGE Shadow;
1073 /** The current protection setting. */
1074 PGMROMPROT enmProt;
1075 /** Pad the structure size to a multiple of 8. */
1076 uint32_t u32Padding;
1077} PGMROMPAGE;
1078/** Pointer to a ROM page tracking structure. */
1079typedef PGMROMPAGE *PPGMROMPAGE;
1080
1081
1082/**
1083 * A registered ROM image.
1084 *
1085 * This is needed to keep track of ROM image since they generally
1086 * intrude into a PGMRAMRANGE. It also keeps track of additional
1087 * info like the two page sets (read-only virgin and read-write shadow),
1088 * the current state of each page.
1089 *
1090 * Because access handlers cannot easily be executed in a different
1091 * context, the ROM ranges needs to be accessible and in all contexts.
1092 */
1093typedef struct PGMROMRANGE
1094{
1095 /** Pointer to the next range - R3. */
1096 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1097 /** Pointer to the next range - R0. */
1098 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1099 /** Pointer to the next range - RC. */
1100 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1101 /** Pointer alignment */
1102 RTRCPTR GCPtrAlignment;
1103 /** Address of the range. */
1104 RTGCPHYS GCPhys;
1105 /** Address of the last byte in the range. */
1106 RTGCPHYS GCPhysLast;
1107 /** Size of the range. */
1108 RTGCPHYS cb;
1109 /** The flags (PGMPHYS_ROM_FLAG_*). */
1110 uint32_t fFlags;
1111 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1112 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1113 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1114 * This is used for strictness checks. */
1115 R3PTRTYPE(const void *) pvOriginal;
1116 /** The ROM description. */
1117 R3PTRTYPE(const char *) pszDesc;
1118 /** The per page tracking structures. */
1119 PGMROMPAGE aPages[1];
1120} PGMROMRANGE;
1121/** Pointer to a ROM range. */
1122typedef PGMROMRANGE *PPGMROMRANGE;
1123
1124
1125/**
1126 * A registered MMIO2 (= Device RAM) range.
1127 *
1128 * There are a few reason why we need to keep track of these
1129 * registrations. One of them is the deregistration & cleanup
1130 * stuff, while another is that the PGMRAMRANGE associated with
1131 * such a region may have to be removed from the ram range list.
1132 *
1133 * Overlapping with a RAM range has to be 100% or none at all. The
1134 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1135 * meditation will be raised if a partial overlap or an overlap of
1136 * ROM pages is encountered. On an overlap we will free all the
1137 * existing RAM pages and put in the ram range pages instead.
1138 */
1139typedef struct PGMMMIO2RANGE
1140{
1141 /** The owner of the range. (a device) */
1142 PPDMDEVINSR3 pDevInsR3;
1143 /** Pointer to the ring-3 mapping of the allocation. */
1144 RTR3PTR pvR3;
1145 /** Pointer to the next range - R3. */
1146 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1147 /** Whether it's mapped or not. */
1148 bool fMapped;
1149 /** Whether it's overlapping or not. */
1150 bool fOverlapping;
1151 /** The PCI region number.
1152 * @remarks This ASSUMES that nobody will ever really need to have multiple
1153 * PCI devices with matching MMIO region numbers on a single device. */
1154 uint8_t iRegion;
1155 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1156 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1157 /** The associated RAM range. */
1158 PGMRAMRANGE RamRange;
1159} PGMMMIO2RANGE;
1160/** Pointer to a MMIO2 range. */
1161typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1162
1163
1164
1165
1166/**
1167 * PGMPhysRead/Write cache entry
1168 */
1169typedef struct PGMPHYSCACHEENTRY
1170{
1171 /** R3 pointer to physical page. */
1172 R3PTRTYPE(uint8_t *) pbR3;
1173 /** GC Physical address for cache entry */
1174 RTGCPHYS GCPhys;
1175#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1176 RTGCPHYS u32Padding0; /**< alignment padding. */
1177#endif
1178} PGMPHYSCACHEENTRY;
1179
1180/**
1181 * PGMPhysRead/Write cache to reduce REM memory access overhead
1182 */
1183typedef struct PGMPHYSCACHE
1184{
1185 /** Bitmap of valid cache entries */
1186 uint64_t aEntries;
1187 /** Cache entries */
1188 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1189} PGMPHYSCACHE;
1190
1191
1192/** Pointer to an allocation chunk ring-3 mapping. */
1193typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1194/** Pointer to an allocation chunk ring-3 mapping pointer. */
1195typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1196
1197/**
1198 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1199 *
1200 * The primary tree (Core) uses the chunk id as key.
1201 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1202 */
1203typedef struct PGMCHUNKR3MAP
1204{
1205 /** The key is the chunk id. */
1206 AVLU32NODECORE Core;
1207 /** The key is the ageing sequence number. */
1208 AVLLU32NODECORE AgeCore;
1209 /** The current age thingy. */
1210 uint32_t iAge;
1211 /** The current reference count. */
1212 uint32_t volatile cRefs;
1213 /** The current permanent reference count. */
1214 uint32_t volatile cPermRefs;
1215 /** The mapping address. */
1216 void *pv;
1217} PGMCHUNKR3MAP;
1218
1219/**
1220 * Allocation chunk ring-3 mapping TLB entry.
1221 */
1222typedef struct PGMCHUNKR3MAPTLBE
1223{
1224 /** The chunk id. */
1225 uint32_t volatile idChunk;
1226#if HC_ARCH_BITS == 64
1227 uint32_t u32Padding; /**< alignment padding. */
1228#endif
1229 /** The chunk map. */
1230#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1231 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1232#else
1233 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1234#endif
1235} PGMCHUNKR3MAPTLBE;
1236/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1237typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1238
1239/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1240 * @remark Must be a power of two value. */
1241#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1242
1243/**
1244 * Allocation chunk ring-3 mapping TLB.
1245 *
1246 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1247 * At first glance this might look kinda odd since AVL trees are
1248 * supposed to give the most optimial lookup times of all trees
1249 * due to their balancing. However, take a tree with 1023 nodes
1250 * in it, that's 10 levels, meaning that most searches has to go
1251 * down 9 levels before they find what they want. This isn't fast
1252 * compared to a TLB hit. There is the factor of cache misses,
1253 * and of course the problem with trees and branch prediction.
1254 * This is why we use TLBs in front of most of the trees.
1255 *
1256 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1257 * difficult when we switch to the new inlined AVL trees (from kStuff).
1258 */
1259typedef struct PGMCHUNKR3MAPTLB
1260{
1261 /** The TLB entries. */
1262 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1263} PGMCHUNKR3MAPTLB;
1264
1265/**
1266 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1267 * @returns Chunk TLB index.
1268 * @param idChunk The Chunk ID.
1269 */
1270#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1271
1272
1273/**
1274 * Ring-3 guest page mapping TLB entry.
1275 * @remarks used in ring-0 as well at the moment.
1276 */
1277typedef struct PGMPAGER3MAPTLBE
1278{
1279 /** Address of the page. */
1280 RTGCPHYS volatile GCPhys;
1281 /** The guest page. */
1282#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1283 R3PTRTYPE(PPGMPAGE) volatile pPage;
1284#else
1285 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1286#endif
1287 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1288#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1289 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1290#else
1291 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1292#endif
1293 /** The address */
1294#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1295 R3PTRTYPE(void *) volatile pv;
1296#else
1297 R3R0PTRTYPE(void *) volatile pv;
1298#endif
1299#if HC_ARCH_BITS == 32
1300 uint32_t u32Padding; /**< alignment padding. */
1301#endif
1302} PGMPAGER3MAPTLBE;
1303/** Pointer to an entry in the HC physical TLB. */
1304typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1305
1306
1307/** The number of entries in the ring-3 guest page mapping TLB.
1308 * @remarks The value must be a power of two. */
1309#define PGM_PAGER3MAPTLB_ENTRIES 64
1310
1311/**
1312 * Ring-3 guest page mapping TLB.
1313 * @remarks used in ring-0 as well at the moment.
1314 */
1315typedef struct PGMPAGER3MAPTLB
1316{
1317 /** The TLB entries. */
1318 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1319} PGMPAGER3MAPTLB;
1320/** Pointer to the ring-3 guest page mapping TLB. */
1321typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1322
1323/**
1324 * Calculates the index of the TLB entry for the specified guest page.
1325 * @returns Physical TLB index.
1326 * @param GCPhys The guest physical address.
1327 */
1328#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1329
1330
1331/**
1332 * Mapping cache usage set entry.
1333 *
1334 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1335 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1336 * cache. If it's extended to include ring-3, well, then something will
1337 * have be changed here...
1338 */
1339typedef struct PGMMAPSETENTRY
1340{
1341 /** The mapping cache index. */
1342 uint16_t iPage;
1343 /** The number of references.
1344 * The max is UINT16_MAX - 1. */
1345 uint16_t cRefs;
1346 /** Pointer to the page. */
1347 RTR0PTR pvPage;
1348 /** The physical address for this entry. */
1349 RTHCPHYS HCPhys;
1350} PGMMAPSETENTRY;
1351/** Pointer to a mapping cache usage set entry. */
1352typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1353
1354/**
1355 * Mapping cache usage set.
1356 *
1357 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1358 * done during exits / traps. The set is
1359 */
1360typedef struct PGMMAPSET
1361{
1362 /** The number of occupied entries.
1363 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1364 * dynamic mappings. */
1365 uint32_t cEntries;
1366 /** The start of the current subset.
1367 * This is UINT32_MAX if no subset is currently open. */
1368 uint32_t iSubset;
1369 /** The index of the current CPU, only valid if the set is open. */
1370 int32_t iCpu;
1371 /** The entries. */
1372 PGMMAPSETENTRY aEntries[64];
1373 /** HCPhys -> iEntry fast lookup table.
1374 * Use PGMMAPSET_HASH for hashing.
1375 * The entries may or may not be valid, check against cEntries. */
1376 uint8_t aiHashTable[128];
1377} PGMMAPSET;
1378/** Pointer to the mapping cache set. */
1379typedef PGMMAPSET *PPGMMAPSET;
1380
1381/** PGMMAPSET::cEntries value for a closed set. */
1382#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1383
1384/** Hash function for aiHashTable. */
1385#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1386
1387/** The max fill size (strict builds). */
1388#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1389
1390
1391/** @name Context neutrual page mapper TLB.
1392 *
1393 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1394 * code is writting in a kind of context neutrual way. Time will show whether
1395 * this actually makes sense or not...
1396 *
1397 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1398 * context ends up using a global mapping cache on some platforms
1399 * (darwin).
1400 *
1401 * @{ */
1402/** @typedef PPGMPAGEMAPTLB
1403 * The page mapper TLB pointer type for the current context. */
1404/** @typedef PPGMPAGEMAPTLB
1405 * The page mapper TLB entry pointer type for the current context. */
1406/** @typedef PPGMPAGEMAPTLB
1407 * The page mapper TLB entry pointer pointer type for the current context. */
1408/** @def PGM_PAGEMAPTLB_ENTRIES
1409 * The number of TLB entries in the page mapper TLB for the current context. */
1410/** @def PGM_PAGEMAPTLB_IDX
1411 * Calculate the TLB index for a guest physical address.
1412 * @returns The TLB index.
1413 * @param GCPhys The guest physical address. */
1414/** @typedef PPGMPAGEMAP
1415 * Pointer to a page mapper unit for current context. */
1416/** @typedef PPPGMPAGEMAP
1417 * Pointer to a page mapper unit pointer for current context. */
1418#ifdef IN_RC
1419// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1420// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1421// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1422# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1423# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1424 typedef void * PPGMPAGEMAP;
1425 typedef void ** PPPGMPAGEMAP;
1426//#elif IN_RING0
1427// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1428// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1429// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1430//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1431//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1432// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1433// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1434#else
1435 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1436 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1437 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1438# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1439# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1440 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1441 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1442#endif
1443/** @} */
1444
1445
1446/** @name PGM Pool Indexes.
1447 * Aka. the unique shadow page identifier.
1448 * @{ */
1449/** NIL page pool IDX. */
1450#define NIL_PGMPOOL_IDX 0
1451/** The first normal index. */
1452#define PGMPOOL_IDX_FIRST_SPECIAL 1
1453#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1454/** Page directory (32-bit root). */
1455#define PGMPOOL_IDX_PD 1
1456/** Page Directory Pointer Table (PAE root). */
1457#define PGMPOOL_IDX_PDPT 2
1458/** AMD64 CR3 level index.*/
1459#define PGMPOOL_IDX_AMD64_CR3 3
1460/** Nested paging root.*/
1461#define PGMPOOL_IDX_NESTED_ROOT 4
1462/** The first normal index. */
1463#define PGMPOOL_IDX_FIRST 5
1464#else
1465/** Page directory (32-bit root). */
1466#define PGMPOOL_IDX_PD 1
1467/** The extended PAE page directory (2048 entries, works as root currently). */
1468#define PGMPOOL_IDX_PAE_PD 2
1469/** PAE Page Directory Table 0. */
1470#define PGMPOOL_IDX_PAE_PD_0 3
1471/** PAE Page Directory Table 1. */
1472#define PGMPOOL_IDX_PAE_PD_1 4
1473/** PAE Page Directory Table 2. */
1474#define PGMPOOL_IDX_PAE_PD_2 5
1475/** PAE Page Directory Table 3. */
1476#define PGMPOOL_IDX_PAE_PD_3 6
1477/** Page Directory Pointer Table (PAE root, not currently used). */
1478#define PGMPOOL_IDX_PDPT 7
1479/** AMD64 CR3 level index.*/
1480#define PGMPOOL_IDX_AMD64_CR3 8
1481/** Nested paging root.*/
1482#define PGMPOOL_IDX_NESTED_ROOT 9
1483/** The first normal index. */
1484#define PGMPOOL_IDX_FIRST 10
1485#endif
1486/** The last valid index. (inclusive, 14 bits) */
1487#define PGMPOOL_IDX_LAST 0x3fff
1488/** @} */
1489
1490/** The NIL index for the parent chain. */
1491#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1492
1493/**
1494 * Node in the chain linking a shadowed page to it's parent (user).
1495 */
1496#pragma pack(1)
1497typedef struct PGMPOOLUSER
1498{
1499 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1500 uint16_t iNext;
1501 /** The user page index. */
1502 uint16_t iUser;
1503 /** Index into the user table. */
1504 uint32_t iUserTable;
1505} PGMPOOLUSER, *PPGMPOOLUSER;
1506typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1507#pragma pack()
1508
1509
1510/** The NIL index for the phys ext chain. */
1511#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1512
1513/**
1514 * Node in the chain of physical cross reference extents.
1515 * @todo Calling this an 'extent' is not quite right, find a better name.
1516 */
1517#pragma pack(1)
1518typedef struct PGMPOOLPHYSEXT
1519{
1520 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1521 uint16_t iNext;
1522 /** The user page index. */
1523 uint16_t aidx[3];
1524} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1525typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1526#pragma pack()
1527
1528
1529/**
1530 * The kind of page that's being shadowed.
1531 */
1532typedef enum PGMPOOLKIND
1533{
1534 /** The virtual invalid 0 entry. */
1535 PGMPOOLKIND_INVALID = 0,
1536 /** The entry is free (=unused). */
1537 PGMPOOLKIND_FREE,
1538
1539 /** Shw: 32-bit page table; Gst: no paging */
1540 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1541 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1542 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1543 /** Shw: 32-bit page table; Gst: 4MB page. */
1544 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1545 /** Shw: PAE page table; Gst: no paging */
1546 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1547 /** Shw: PAE page table; Gst: 32-bit page table. */
1548 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1549 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1550 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1551 /** Shw: PAE page table; Gst: PAE page table. */
1552 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1553 /** Shw: PAE page table; Gst: 2MB page. */
1554 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1555
1556 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1557 PGMPOOLKIND_32BIT_PD,
1558 /** Shw: 32-bit page directory. Gst: no paging. */
1559 PGMPOOLKIND_32BIT_PD_PHYS,
1560 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1561 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1562 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1563 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1564 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1565 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1566 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1567 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1568 /** Shw: PAE page directory; Gst: PAE page directory. */
1569 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1570 /** Shw: PAE page directory; Gst: no paging. */
1571 PGMPOOLKIND_PAE_PD_PHYS,
1572
1573 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1574 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1575 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1576 PGMPOOLKIND_PAE_PDPT,
1577 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1578 PGMPOOLKIND_PAE_PDPT_PHYS,
1579
1580 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1581 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1582 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1583 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1584 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1585 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1586 /** Shw: 64-bit page directory table; Gst: no paging */
1587 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1588
1589 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1590 PGMPOOLKIND_64BIT_PML4,
1591
1592 /** Shw: EPT page directory pointer table; Gst: no paging */
1593 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1594 /** Shw: EPT page directory table; Gst: no paging */
1595 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1596 /** Shw: EPT page table; Gst: no paging */
1597 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1598
1599#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1600 /** Shw: Root 32-bit page directory. */
1601 PGMPOOLKIND_ROOT_32BIT_PD,
1602 /** Shw: Root PAE page directory */
1603 PGMPOOLKIND_ROOT_PAE_PD,
1604 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1605 PGMPOOLKIND_ROOT_PDPT,
1606#endif
1607 /** Shw: Root Nested paging table. */
1608 PGMPOOLKIND_ROOT_NESTED,
1609
1610 /** The last valid entry. */
1611 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1612} PGMPOOLKIND;
1613
1614
1615/**
1616 * The tracking data for a page in the pool.
1617 */
1618typedef struct PGMPOOLPAGE
1619{
1620 /** AVL node code with the (R3) physical address of this page. */
1621 AVLOHCPHYSNODECORE Core;
1622 /** Pointer to the R3 mapping of the page. */
1623#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1624 R3PTRTYPE(void *) pvPageR3;
1625#else
1626 R3R0PTRTYPE(void *) pvPageR3;
1627#endif
1628 /** The guest physical address. */
1629#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1630 uint32_t Alignment0;
1631#endif
1632 RTGCPHYS GCPhys;
1633 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1634 uint8_t enmKind;
1635 uint8_t bPadding;
1636 /** The index of this page. */
1637 uint16_t idx;
1638 /** The next entry in the list this page currently resides in.
1639 * It's either in the free list or in the GCPhys hash. */
1640 uint16_t iNext;
1641#ifdef PGMPOOL_WITH_USER_TRACKING
1642 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1643 uint16_t iUserHead;
1644 /** The number of present entries. */
1645 uint16_t cPresent;
1646 /** The first entry in the table which is present. */
1647 uint16_t iFirstPresent;
1648#endif
1649#ifdef PGMPOOL_WITH_MONITORING
1650 /** The number of modifications to the monitored page. */
1651 uint16_t cModifications;
1652 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1653 uint16_t iModifiedNext;
1654 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1655 uint16_t iModifiedPrev;
1656 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1657 uint16_t iMonitoredNext;
1658 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1659 uint16_t iMonitoredPrev;
1660#endif
1661#ifdef PGMPOOL_WITH_CACHE
1662 /** The next page in the age list. */
1663 uint16_t iAgeNext;
1664 /** The previous page in the age list. */
1665 uint16_t iAgePrev;
1666#endif /* PGMPOOL_WITH_CACHE */
1667 /** Used to indicate that the page is zeroed. */
1668 bool fZeroed;
1669 /** Used to indicate that a PT has non-global entries. */
1670 bool fSeenNonGlobal;
1671 /** Used to indicate that we're monitoring writes to the guest page. */
1672 bool fMonitored;
1673 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1674 * (All pages are in the age list.) */
1675 bool fCached;
1676 /** This is used by the R3 access handlers when invoked by an async thread.
1677 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1678 bool volatile fReusedFlushPending;
1679#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1680 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1681 bool fLocked;
1682#else
1683 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1684 * In these cases the access handler acts differently and will check
1685 * for mapping conflicts like the normal CR3 handler.
1686 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1687 * replaced by a list of pages which share access handler.
1688 */
1689 bool fCR3Mix;
1690#endif
1691} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1692
1693
1694#ifdef PGMPOOL_WITH_CACHE
1695/** The hash table size. */
1696# define PGMPOOL_HASH_SIZE 0x40
1697/** The hash function. */
1698# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1699#endif
1700
1701
1702/**
1703 * The shadow page pool instance data.
1704 *
1705 * It's all one big allocation made at init time, except for the
1706 * pages that is. The user nodes follows immediatly after the
1707 * page structures.
1708 */
1709typedef struct PGMPOOL
1710{
1711 /** The VM handle - R3 Ptr. */
1712 PVMR3 pVMR3;
1713 /** The VM handle - R0 Ptr. */
1714 PVMR0 pVMR0;
1715 /** The VM handle - RC Ptr. */
1716 PVMRC pVMRC;
1717 /** The max pool size. This includes the special IDs. */
1718 uint16_t cMaxPages;
1719 /** The current pool size. */
1720 uint16_t cCurPages;
1721 /** The head of the free page list. */
1722 uint16_t iFreeHead;
1723 /* Padding. */
1724 uint16_t u16Padding;
1725#ifdef PGMPOOL_WITH_USER_TRACKING
1726 /** Head of the chain of free user nodes. */
1727 uint16_t iUserFreeHead;
1728 /** The number of user nodes we've allocated. */
1729 uint16_t cMaxUsers;
1730 /** The number of present page table entries in the entire pool. */
1731 uint32_t cPresent;
1732 /** Pointer to the array of user nodes - RC pointer. */
1733 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1734 /** Pointer to the array of user nodes - R3 pointer. */
1735 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1736 /** Pointer to the array of user nodes - R0 pointer. */
1737 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1738#endif /* PGMPOOL_WITH_USER_TRACKING */
1739#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1740 /** Head of the chain of free phys ext nodes. */
1741 uint16_t iPhysExtFreeHead;
1742 /** The number of user nodes we've allocated. */
1743 uint16_t cMaxPhysExts;
1744 /** Pointer to the array of physical xref extent - RC pointer. */
1745 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1746 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1747 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1748 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1749 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1750#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1751#ifdef PGMPOOL_WITH_CACHE
1752 /** Hash table for GCPhys addresses. */
1753 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1754 /** The head of the age list. */
1755 uint16_t iAgeHead;
1756 /** The tail of the age list. */
1757 uint16_t iAgeTail;
1758 /** Set if the cache is enabled. */
1759 bool fCacheEnabled;
1760#endif /* PGMPOOL_WITH_CACHE */
1761#ifdef PGMPOOL_WITH_MONITORING
1762 /** Head of the list of modified pages. */
1763 uint16_t iModifiedHead;
1764 /** The current number of modified pages. */
1765 uint16_t cModifiedPages;
1766 /** Access handler, RC. */
1767 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1768 /** Access handler, R0. */
1769 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1770 /** Access handler, R3. */
1771 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1772 /** The access handler description (HC ptr). */
1773 R3PTRTYPE(const char *) pszAccessHandler;
1774#endif /* PGMPOOL_WITH_MONITORING */
1775 /** The number of pages currently in use. */
1776 uint16_t cUsedPages;
1777#ifdef VBOX_WITH_STATISTICS
1778 /** The high wather mark for cUsedPages. */
1779 uint16_t cUsedPagesHigh;
1780 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1781 /** Profiling pgmPoolAlloc(). */
1782 STAMPROFILEADV StatAlloc;
1783 /** Profiling pgmPoolClearAll(). */
1784 STAMPROFILE StatClearAll;
1785 /** Profiling pgmPoolFlushAllInt(). */
1786 STAMPROFILE StatFlushAllInt;
1787 /** Profiling pgmPoolFlushPage(). */
1788 STAMPROFILE StatFlushPage;
1789 /** Profiling pgmPoolFree(). */
1790 STAMPROFILE StatFree;
1791 /** Profiling time spent zeroing pages. */
1792 STAMPROFILE StatZeroPage;
1793# ifdef PGMPOOL_WITH_USER_TRACKING
1794 /** Profiling of pgmPoolTrackDeref. */
1795 STAMPROFILE StatTrackDeref;
1796 /** Profiling pgmTrackFlushGCPhysPT. */
1797 STAMPROFILE StatTrackFlushGCPhysPT;
1798 /** Profiling pgmTrackFlushGCPhysPTs. */
1799 STAMPROFILE StatTrackFlushGCPhysPTs;
1800 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1801 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1802 /** Number of times we've been out of user records. */
1803 STAMCOUNTER StatTrackFreeUpOneUser;
1804# endif
1805# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1806 /** Profiling deref activity related tracking GC physical pages. */
1807 STAMPROFILE StatTrackDerefGCPhys;
1808 /** Number of linear searches for a HCPhys in the ram ranges. */
1809 STAMCOUNTER StatTrackLinearRamSearches;
1810 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1811 STAMCOUNTER StamTrackPhysExtAllocFailures;
1812# endif
1813# ifdef PGMPOOL_WITH_MONITORING
1814 /** Profiling the RC/R0 access handler. */
1815 STAMPROFILE StatMonitorRZ;
1816 /** Times we've failed interpreting the instruction. */
1817 STAMCOUNTER StatMonitorRZEmulateInstr;
1818 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1819 STAMPROFILE StatMonitorRZFlushPage;
1820 /** Times we've detected fork(). */
1821 STAMCOUNTER StatMonitorRZFork;
1822 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1823 STAMPROFILE StatMonitorRZHandled;
1824 /** Times we've failed interpreting a patch code instruction. */
1825 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1826 /** Times we've failed interpreting a patch code instruction during flushing. */
1827 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1828 /** The number of times we've seen rep prefixes we can't handle. */
1829 STAMCOUNTER StatMonitorRZRepPrefix;
1830 /** Profiling the REP STOSD cases we've handled. */
1831 STAMPROFILE StatMonitorRZRepStosd;
1832
1833 /** Profiling the R3 access handler. */
1834 STAMPROFILE StatMonitorR3;
1835 /** Times we've failed interpreting the instruction. */
1836 STAMCOUNTER StatMonitorR3EmulateInstr;
1837 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1838 STAMPROFILE StatMonitorR3FlushPage;
1839 /** Times we've detected fork(). */
1840 STAMCOUNTER StatMonitorR3Fork;
1841 /** Profiling the R3 access we've handled (except REP STOSD). */
1842 STAMPROFILE StatMonitorR3Handled;
1843 /** The number of times we've seen rep prefixes we can't handle. */
1844 STAMCOUNTER StatMonitorR3RepPrefix;
1845 /** Profiling the REP STOSD cases we've handled. */
1846 STAMPROFILE StatMonitorR3RepStosd;
1847 /** The number of times we're called in an async thread an need to flush. */
1848 STAMCOUNTER StatMonitorR3Async;
1849 /** The high wather mark for cModifiedPages. */
1850 uint16_t cModifiedPagesHigh;
1851 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1852# endif
1853# ifdef PGMPOOL_WITH_CACHE
1854 /** The number of cache hits. */
1855 STAMCOUNTER StatCacheHits;
1856 /** The number of cache misses. */
1857 STAMCOUNTER StatCacheMisses;
1858 /** The number of times we've got a conflict of 'kind' in the cache. */
1859 STAMCOUNTER StatCacheKindMismatches;
1860 /** Number of times we've been out of pages. */
1861 STAMCOUNTER StatCacheFreeUpOne;
1862 /** The number of cacheable allocations. */
1863 STAMCOUNTER StatCacheCacheable;
1864 /** The number of uncacheable allocations. */
1865 STAMCOUNTER StatCacheUncacheable;
1866# endif
1867#elif HC_ARCH_BITS == 64
1868 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1869#endif
1870 /** The AVL tree for looking up a page by its HC physical address. */
1871 AVLOHCPHYSTREE HCPhysTree;
1872 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1873 /** Array of pages. (cMaxPages in length)
1874 * The Id is the index into thist array.
1875 */
1876 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1877} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1878
1879
1880/** @def PGMPOOL_PAGE_2_PTR
1881 * Maps a pool page pool into the current context.
1882 *
1883 * @returns VBox status code.
1884 * @param pVM The VM handle.
1885 * @param pPage The pool page.
1886 *
1887 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1888 * small page window employeed by that function. Be careful.
1889 * @remark There is no need to assert on the result.
1890 */
1891#if defined(IN_RC)
1892# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1893#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1894# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1895#elif defined(VBOX_STRICT)
1896# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1897DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1898{
1899 Assert(pPage->pvPageR3);
1900 return pPage->pvPageR3;
1901}
1902#else
1903# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1904#endif
1905
1906/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1907 * Maps a pool page pool into the current context.
1908 *
1909 * @returns VBox status code.
1910 * @param pPGM Pointer to the PGM instance data.
1911 * @param pPage The pool page.
1912 *
1913 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1914 * small page window employeed by that function. Be careful.
1915 * @remark There is no need to assert on the result.
1916 */
1917#if defined(IN_RC)
1918# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1919#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1920# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1921#else
1922# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1923#endif
1924
1925
1926/** @name Per guest page tracking data.
1927 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1928 * is to use more bits for it and split it up later on. But for now we'll play
1929 * safe and change as little as possible.
1930 *
1931 * The 16-bit word has two parts:
1932 *
1933 * The first 14-bit forms the @a idx field. It is either the index of a page in
1934 * the shadow page pool, or and index into the extent list.
1935 *
1936 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1937 * shadow page pool references to the page. If cRefs equals
1938 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1939 * (misnomer) table and not the shadow page pool.
1940 *
1941 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1942 * the 16-bit word.
1943 *
1944 * @{ */
1945/** The shift count for getting to the cRefs part. */
1946#define PGMPOOL_TD_CREFS_SHIFT 14
1947/** The mask applied after shifting the tracking data down by
1948 * PGMPOOL_TD_CREFS_SHIFT. */
1949#define PGMPOOL_TD_CREFS_MASK 0x3
1950/** The cRef value used to indiciate that the idx is the head of a
1951 * physical cross reference list. */
1952#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1953/** The shift used to get idx. */
1954#define PGMPOOL_TD_IDX_SHIFT 0
1955/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1956#define PGMPOOL_TD_IDX_MASK 0x3fff
1957/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1958 * simply too many mappings of this page. */
1959#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1960
1961/** @def PGMPOOL_TD_MAKE
1962 * Makes a 16-bit tracking data word.
1963 *
1964 * @returns tracking data.
1965 * @param cRefs The @a cRefs field. Must be within bounds!
1966 * @param idx The @a idx field. Must also be within bounds! */
1967#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1968
1969/** @def PGMPOOL_TD_GET_CREFS
1970 * Get the @a cRefs field from a tracking data word.
1971 *
1972 * @returns The @a cRefs field
1973 * @param u16 The tracking data word. */
1974#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1975
1976/** @def PGMPOOL_TD_GET_IDX
1977 * Get the @a idx field from a tracking data word.
1978 *
1979 * @returns The @a idx field
1980 * @param u16 The tracking data word. */
1981#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1982/** @} */
1983
1984
1985/**
1986 * Trees are using self relative offsets as pointers.
1987 * So, all its data, including the root pointer, must be in the heap for HC and GC
1988 * to have the same layout.
1989 */
1990typedef struct PGMTREES
1991{
1992 /** Physical access handlers (AVL range+offsetptr tree). */
1993 AVLROGCPHYSTREE PhysHandlers;
1994 /** Virtual access handlers (AVL range + GC ptr tree). */
1995 AVLROGCPTRTREE VirtHandlers;
1996 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1997 AVLROGCPHYSTREE PhysToVirtHandlers;
1998 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1999 AVLROGCPTRTREE HyperVirtHandlers;
2000} PGMTREES;
2001/** Pointer to PGM trees. */
2002typedef PGMTREES *PPGMTREES;
2003
2004
2005/** @name Paging mode macros
2006 * @{ */
2007#ifdef IN_RC
2008# define PGM_CTX(a,b) a##RC##b
2009# define PGM_CTX_STR(a,b) a "GC" b
2010# define PGM_CTX_DECL(type) VMMRCDECL(type)
2011#else
2012# ifdef IN_RING3
2013# define PGM_CTX(a,b) a##R3##b
2014# define PGM_CTX_STR(a,b) a "R3" b
2015# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2016# else
2017# define PGM_CTX(a,b) a##R0##b
2018# define PGM_CTX_STR(a,b) a "R0" b
2019# define PGM_CTX_DECL(type) VMMDECL(type)
2020# endif
2021#endif
2022
2023#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2024#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2025#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2026#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2027#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2028#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2029#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2030#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2031#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2032#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2033#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2034#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2035#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2036#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2037#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2038#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2039#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2040
2041#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2042#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2043#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2044#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2045#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2046#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2047#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2048#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2049#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2050#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2051#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2052#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2053#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2054#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2055#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2056#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2057#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2058
2059/* Shw_Gst */
2060#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2061#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2062#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2063#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2064#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2065#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2066#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2067#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2068#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2069#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2070#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2071#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2072#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2073#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2074#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2075#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2076#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2077#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2078#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2079
2080#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2081#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2082#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2083#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2084#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2085#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2086#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2087#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2088#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2089#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2090#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2091#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2092#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2093#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2094#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2095#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2096#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2097#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2098#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2099#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2100#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2101#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2102#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2103#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2104#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2105#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2106#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2107#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2108#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2109#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2110#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2111#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2112#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2113#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2114#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2115#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2116#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2117
2118#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2119#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2120/** @} */
2121
2122/**
2123 * Data for each paging mode.
2124 */
2125typedef struct PGMMODEDATA
2126{
2127 /** The guest mode type. */
2128 uint32_t uGstType;
2129 /** The shadow mode type. */
2130 uint32_t uShwType;
2131
2132 /** @name Function pointers for Shadow paging.
2133 * @{
2134 */
2135 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2136 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2137 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2138 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2139
2140 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2141 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2142
2143 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2144 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2145 /** @} */
2146
2147 /** @name Function pointers for Guest paging.
2148 * @{
2149 */
2150 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2151 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2152 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2153 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2154 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2155#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2156 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2157 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2158#endif
2159#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2160 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2161 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2162 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2163 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2164#endif
2165 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2166 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2167 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2168#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2169 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2170 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2171#endif
2172#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2173 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2174 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2175#endif
2176 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2177 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2178 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2179#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2180 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2181 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2182#endif
2183#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2184 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2185 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2186#endif
2187 /** @} */
2188
2189 /** @name Function pointers for Both Shadow and Guest paging.
2190 * @{
2191 */
2192 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2193 /* no pfnR3BthTrap0eHandler */
2194 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2195 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2196 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2197 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2198 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2199#ifdef VBOX_STRICT
2200 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2201#endif
2202 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2203 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2204
2205 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2206 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2207 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2208 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2209 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2210 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2211#ifdef VBOX_STRICT
2212 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2213#endif
2214 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2215 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2216
2217 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2218 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2219 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2220 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2221 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2222 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2223#ifdef VBOX_STRICT
2224 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2225#endif
2226 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2227 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2228 /** @} */
2229} PGMMODEDATA, *PPGMMODEDATA;
2230
2231
2232
2233/**
2234 * Converts a PGM pointer into a VM pointer.
2235 * @returns Pointer to the VM structure the PGM is part of.
2236 * @param pPGM Pointer to PGM instance data.
2237 */
2238#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2239
2240/**
2241 * PGM Data (part of VM)
2242 */
2243typedef struct PGM
2244{
2245 /** Offset to the VM structure. */
2246 RTINT offVM;
2247 /** Offset of the PGMCPU structure relative to VMCPU. */
2248 int32_t offVCpu;
2249 /** Alignment padding. */
2250 int32_t i32Alignment;
2251
2252 /*
2253 * This will be redefined at least two more times before we're done, I'm sure.
2254 * The current code is only to get on with the coding.
2255 * - 2004-06-10: initial version, bird.
2256 * - 2004-07-02: 1st time, bird.
2257 * - 2004-10-18: 2nd time, bird.
2258 * - 2005-07-xx: 3rd time, bird.
2259 */
2260
2261 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2262 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2263 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2264 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2265
2266 /** The host paging mode. (This is what SUPLib reports.) */
2267 SUPPAGINGMODE enmHostMode;
2268 /** The shadow paging mode. */
2269 PGMMODE enmShadowMode;
2270 /** The guest paging mode. */
2271 PGMMODE enmGuestMode;
2272
2273 /** The current physical address representing in the guest CR3 register. */
2274 RTGCPHYS GCPhysCR3;
2275 /** Pointer to the 5 page CR3 content mapping.
2276 * The first page is always the CR3 (in some form) while the 4 other pages
2277 * are used of the PDs in PAE mode. */
2278 RTGCPTR GCPtrCR3Mapping;
2279#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2280 uint32_t u32Alignment;
2281#endif
2282#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2283 /** The physical address of the currently monitored guest CR3 page.
2284 * When this value is NIL_RTGCPHYS no page is being monitored. */
2285 RTGCPHYS GCPhysGstCR3Monitored;
2286#endif
2287 /** @name 32-bit Guest Paging.
2288 * @{ */
2289 /** The guest's page directory, R3 pointer. */
2290 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2291#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2292 /** The guest's page directory, R0 pointer. */
2293 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2294#endif
2295 /** The guest's page directory, static RC mapping. */
2296 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2297 /** @} */
2298
2299 /** @name PAE Guest Paging.
2300 * @{ */
2301 /** The guest's page directory pointer table, static RC mapping. */
2302 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2303 /** The guest's page directory pointer table, R3 pointer. */
2304 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2305#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2306 /** The guest's page directory pointer table, R0 pointer. */
2307 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2308#endif
2309
2310 /** The guest's page directories, R3 pointers.
2311 * These are individual pointers and don't have to be adjecent.
2312 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2313 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2314 /** The guest's page directories, R0 pointers.
2315 * Same restrictions as apGstPaePDsR3. */
2316#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2317 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2318#endif
2319 /** The guest's page directories, static GC mapping.
2320 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2321 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2322 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2323 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2324 RTGCPHYS aGCPhysGstPaePDs[4];
2325 /** The physical addresses of the monitored guest page directories (PAE). */
2326 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2327 /** @} */
2328
2329 /** @name AMD64 Guest Paging.
2330 * @{ */
2331 /** The guest's page directory pointer table, R3 pointer. */
2332 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2333#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2334 /** The guest's page directory pointer table, R0 pointer. */
2335 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2336#endif
2337 /** @} */
2338
2339 /** @name Shadow paging
2340 * @{ */
2341 /** The root page table - R3 Ptr. */
2342 R3PTRTYPE(void *) pShwRootR3;
2343# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2344 /** The root page table - R0 Ptr. */
2345 R0PTRTYPE(void *) pShwRootR0;
2346# endif
2347 /** The root page table - RC Ptr. */
2348 RCPTRTYPE(void *) pShwRootRC;
2349# if HC_ARCH_BITS == 64
2350 uint32_t u32Padding1; /**< alignment padding. */
2351# endif
2352 /** The Physical Address (HC) of the current active shadow CR3. */
2353 RTHCPHYS HCPhysShwCR3;
2354 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2355 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2356 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2357 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2358 /** Pointer to the page of the current active CR3 - RC Ptr. */
2359 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2360 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2361 uint32_t iShwUser;
2362 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2363 uint32_t iShwUserTable;
2364# if HC_ARCH_BITS == 64
2365 RTRCPTR alignment6; /**< structure size alignment. */
2366# endif
2367 /** @} */
2368#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2369 /** @name 32-bit Shadow Paging
2370 * @{ */
2371 /** The 32-Bit PD - R3 Ptr. */
2372 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2373 /** The 32-Bit PD - R0 Ptr. */
2374 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2375 /** The 32-Bit PD - RC Ptr. */
2376 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2377# if HC_ARCH_BITS == 64
2378 uint32_t u32Padding10; /**< alignment padding. */
2379# endif
2380 /** The Physical Address (HC) of the 32-Bit PD. */
2381 RTHCPHYS HCPhysShw32BitPD;
2382 /** @} */
2383
2384 /** @name PAE Shadow Paging
2385 * @{ */
2386 /** The four PDs for the low 4GB - R3 Ptr.
2387 * Even though these are 4 pointers, what they point at is a single table.
2388 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2389 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2390# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2391 /** The four PDs for the low 4GB - R0 Ptr.
2392 * Same kind of mapping as apHCPaePDs. */
2393 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2394# endif
2395 /** The four PDs for the low 4GB - RC Ptr.
2396 * Same kind of mapping as apHCPaePDs. */
2397 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2398 /** The Physical Address (HC) of the four PDs for the low 4GB.
2399 * These are *NOT* 4 contiguous pages. */
2400 RTHCPHYS aHCPhysPaePDs[4];
2401 /** The Physical Address (HC) of the PAE PDPT. */
2402 RTHCPHYS HCPhysShwPaePdpt;
2403 /** The PAE PDPT - R3 Ptr. */
2404 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2405 /** The PAE PDPT - R0 Ptr. */
2406 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2407 /** The PAE PDPT - RC Ptr. */
2408 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2409 /** @} */
2410# if HC_ARCH_BITS == 64
2411 RTRCPTR alignment5; /**< structure size alignment. */
2412# endif
2413#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2414 /** @name Nested Shadow Paging
2415 * @{ */
2416 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2417 RTR3PTR pShwNestedRootR3;
2418# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2419 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2420 RTR0PTR pShwNestedRootR0;
2421# endif
2422 /** The Physical Address (HC) of the nested paging root. */
2423 RTHCPHYS HCPhysShwNestedRoot;
2424 /** @} */
2425
2426 /** @name Function pointers for Shadow paging.
2427 * @{
2428 */
2429 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2430 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2431 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2432 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2433
2434 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2435 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2436
2437 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2438 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2439
2440 /** @} */
2441
2442 /** @name Function pointers for Guest paging.
2443 * @{
2444 */
2445 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2446 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2447 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2448 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2449 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2450#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2451 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2452 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2453#endif
2454#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2455 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2456 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2457 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2458 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2459#endif
2460 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2461 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2462 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2463#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2464 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2465 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2466#endif
2467#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2468 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2469 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2470#endif
2471#if HC_ARCH_BITS == 64
2472 RTRCPTR alignment3; /**< structure size alignment. */
2473#endif
2474
2475 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2476 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2477 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2478#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2479 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2480 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2481#endif
2482#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2483 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2484 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2485#endif
2486 /** @} */
2487
2488 /** @name Function pointers for Both Shadow and Guest paging.
2489 * @{
2490 */
2491 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2492 /* no pfnR3BthTrap0eHandler */
2493 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2494 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2495 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2496 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2497 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2498 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2499 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2500 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2501
2502 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2503 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2504 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2505 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2506 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2507 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2508 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2509 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2510 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2511
2512 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2513 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2514 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2515 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2516 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2517 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2518 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2519 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2520 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2521#if HC_ARCH_BITS == 64
2522 RTRCPTR alignment2; /**< structure size alignment. */
2523#endif
2524 /** @} */
2525
2526 /** Pointer to SHW+GST mode data (function pointers).
2527 * The index into this table is made up from */
2528 R3PTRTYPE(PPGMMODEDATA) paModeData;
2529
2530 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2531 * This is sorted by physical address and contains no overlapping ranges. */
2532 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2533 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2534 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2535 /** RC pointer corresponding to PGM::pRamRangesR3. */
2536 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2537 /** The configured RAM size. */
2538 RTUINT cbRamSize;
2539
2540 /** Pointer to the list of ROM ranges - for R3.
2541 * This is sorted by physical address and contains no overlapping ranges. */
2542 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2543 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2544 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2545 /** RC pointer corresponding to PGM::pRomRangesR3. */
2546 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2547 /** Alignment padding. */
2548 RTRCPTR GCPtrPadding2;
2549
2550 /** Pointer to the list of MMIO2 ranges - for R3.
2551 * Registration order. */
2552 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2553
2554 /** PGM offset based trees - R3 Ptr. */
2555 R3PTRTYPE(PPGMTREES) pTreesR3;
2556 /** PGM offset based trees - R0 Ptr. */
2557 R0PTRTYPE(PPGMTREES) pTreesR0;
2558 /** PGM offset based trees - RC Ptr. */
2559 RCPTRTYPE(PPGMTREES) pTreesRC;
2560
2561 /** Linked list of GC mappings - for RC.
2562 * The list is sorted ascending on address.
2563 */
2564 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2565 /** Linked list of GC mappings - for HC.
2566 * The list is sorted ascending on address.
2567 */
2568 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2569 /** Linked list of GC mappings - for R0.
2570 * The list is sorted ascending on address.
2571 */
2572 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2573
2574 /** Indicates that PGMR3FinalizeMappings has been called and that further
2575 * PGMR3MapIntermediate calls will be rejected. */
2576 bool fFinalizedMappings;
2577 /** If set no conflict checks are required. (boolean) */
2578 bool fMappingsFixed;
2579 /** If set, then no mappings are put into the shadow page table. (boolean) */
2580 bool fDisableMappings;
2581 /** Size of fixed mapping */
2582 uint32_t cbMappingFixed;
2583 /** Base address (GC) of fixed mapping */
2584 RTGCPTR GCPtrMappingFixed;
2585#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2586 uint32_t u32Padding0; /**< alignment padding. */
2587#endif
2588
2589
2590 /** @name Intermediate Context
2591 * @{ */
2592 /** Pointer to the intermediate page directory - Normal. */
2593 R3PTRTYPE(PX86PD) pInterPD;
2594 /** Pointer to the intermedate page tables - Normal.
2595 * There are two page tables, one for the identity mapping and one for
2596 * the host context mapping (of the core code). */
2597 R3PTRTYPE(PX86PT) apInterPTs[2];
2598 /** Pointer to the intermedate page tables - PAE. */
2599 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2600 /** Pointer to the intermedate page directory - PAE. */
2601 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2602 /** Pointer to the intermedate page directory - PAE. */
2603 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2604 /** Pointer to the intermedate page-map level 4 - AMD64. */
2605 R3PTRTYPE(PX86PML4) pInterPaePML4;
2606 /** Pointer to the intermedate page directory - AMD64. */
2607 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2608 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2609 RTHCPHYS HCPhysInterPD;
2610 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2611 RTHCPHYS HCPhysInterPaePDPT;
2612 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2613 RTHCPHYS HCPhysInterPaePML4;
2614 /** @} */
2615
2616 /** Base address of the dynamic page mapping area.
2617 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2618 */
2619 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2620 /** The index of the last entry used in the dynamic page mapping area. */
2621 RTUINT iDynPageMapLast;
2622 /** Cache containing the last entries in the dynamic page mapping area.
2623 * The cache size is covering half of the mapping area. */
2624 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2625
2626 /** The address of the ring-0 mapping cache if we're making use of it. */
2627 RTR0PTR pvR0DynMapUsed;
2628#if HC_ARCH_BITS == 32
2629 RTR0PTR R0PtrPadding0; /**< Alignment. */
2630#endif
2631
2632
2633 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2634 RTGCPHYS GCPhys4MBPSEMask;
2635
2636 /** A20 gate mask.
2637 * Our current approach to A20 emulation is to let REM do it and don't bother
2638 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2639 * But whould need arrise, we'll subject physical addresses to this mask. */
2640 RTGCPHYS GCPhysA20Mask;
2641 /** A20 gate state - boolean! */
2642 RTUINT fA20Enabled;
2643
2644 /** What needs syncing (PGM_SYNC_*).
2645 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2646 * PGMFlushTLB, and PGMR3Load. */
2647 RTUINT fSyncFlags;
2648
2649 /** PGM critical section.
2650 * This protects the physical & virtual access handlers, ram ranges,
2651 * and the page flag updating (some of it anyway).
2652 */
2653 PDMCRITSECT CritSect;
2654
2655 /** Shadow Page Pool - R3 Ptr. */
2656 R3PTRTYPE(PPGMPOOL) pPoolR3;
2657 /** Shadow Page Pool - R0 Ptr. */
2658 R0PTRTYPE(PPGMPOOL) pPoolR0;
2659 /** Shadow Page Pool - RC Ptr. */
2660 RCPTRTYPE(PPGMPOOL) pPoolRC;
2661
2662 /** We're not in a state which permits writes to guest memory.
2663 * (Only used in strict builds.) */
2664 bool fNoMorePhysWrites;
2665
2666 /** Flush the cache on the next access. */
2667 bool fPhysCacheFlushPending;
2668/** @todo r=bird: Fix member names!*/
2669 /** PGMPhysRead cache */
2670 PGMPHYSCACHE pgmphysreadcache;
2671 /** PGMPhysWrite cache */
2672 PGMPHYSCACHE pgmphyswritecache;
2673
2674 /**
2675 * Data associated with managing the ring-3 mappings of the allocation chunks.
2676 */
2677 struct
2678 {
2679 /** The chunk tree, ordered by chunk id. */
2680#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2681 R3PTRTYPE(PAVLU32NODECORE) pTree;
2682#else
2683 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2684#endif
2685 /** The chunk mapping TLB. */
2686 PGMCHUNKR3MAPTLB Tlb;
2687 /** The number of mapped chunks. */
2688 uint32_t c;
2689 /** The maximum number of mapped chunks.
2690 * @cfgm PGM/MaxRing3Chunks */
2691 uint32_t cMax;
2692 /** The chunk age tree, ordered by ageing sequence number. */
2693 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2694 /** The current time. */
2695 uint32_t iNow;
2696 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2697 uint32_t AgeingCountdown;
2698 } ChunkR3Map;
2699
2700 /**
2701 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2702 */
2703 PGMPAGER3MAPTLB PhysTlbHC;
2704
2705 /** @name The zero page.
2706 * @{ */
2707 /** The host physical address of the zero page. */
2708 RTHCPHYS HCPhysZeroPg;
2709 /** The ring-3 mapping of the zero page. */
2710 RTR3PTR pvZeroPgR3;
2711 /** The ring-0 mapping of the zero page. */
2712 RTR0PTR pvZeroPgR0;
2713 /** The GC mapping of the zero page. */
2714 RTGCPTR pvZeroPgGC;
2715#if GC_ARCH_BITS != 32
2716 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2717#endif
2718 /** @}*/
2719
2720 /** The number of handy pages. */
2721 uint32_t cHandyPages;
2722 /**
2723 * Array of handy pages.
2724 *
2725 * This array is used in a two way communication between pgmPhysAllocPage
2726 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2727 * an intermediary.
2728 *
2729 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2730 * (The current size of 32 pages, means 128 KB of handy memory.)
2731 */
2732 GMMPAGEDESC aHandyPages[32];
2733
2734 /** @name Release Statistics
2735 * @{ */
2736 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2737 uint32_t cPrivatePages; /**< The number of private pages. */
2738 uint32_t cSharedPages; /**< The number of shared pages. */
2739 uint32_t cZeroPages; /**< The number of zero backed pages. */
2740 /** The number of times the guest has switched mode since last reset or statistics reset. */
2741 STAMCOUNTER cGuestModeChanges;
2742 /** The number of times we were forced to change the hypervisor region location. */
2743 STAMCOUNTER cRelocations;
2744 /** @} */
2745
2746#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2747 /** RC: Which statistic this \#PF should be attributed to. */
2748 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2749 RTRCPTR padding0;
2750 /** R0: Which statistic this \#PF should be attributed to. */
2751 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2752 RTR0PTR padding1;
2753
2754 /* Common */
2755# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2756 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2757 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2758 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2759 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2760 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2761 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2762# endif
2763 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2764 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2765
2766 /* R3 only: */
2767 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2768 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2769 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2770 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2771 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2772 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2773
2774 /* R0 only: */
2775 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2776 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2777 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2778 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2779 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2780 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2781 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2782 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2783 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2784 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2785 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2786 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2787 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2788 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2789 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2790 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2791 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2792 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2793 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2794 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2795 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2796 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2797 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2798 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2799 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2800 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2801
2802 /* RC only: */
2803 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2804 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2805 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2806 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2807
2808 /* RZ only: */
2809 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2810 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2811 STAMPROFILE StatRZTrap0eTimeSyncPT;
2812 STAMPROFILE StatRZTrap0eTimeMapping;
2813 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2814 STAMPROFILE StatRZTrap0eTimeHandlers;
2815 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2816 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2817 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2818 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2819 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2820 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2821 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2822 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2823 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2824 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2825 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2826 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2827 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2828 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2829 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2830 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2831 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2832 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2833 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2834 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2835 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2836 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2837 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2838 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2839 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2840 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2841 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2842 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2843 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2844 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2845 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2846 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2847 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2848 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2849 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2850 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2851 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2852 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2853 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2854 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2855 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2856 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2857 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2858
2859 /* HC - R3 and (maybe) R0: */
2860
2861 /* RZ & R3: */
2862 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2863 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2864 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2865 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2866 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2867 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2868 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2869 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2870 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2871 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2872 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2873 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2874 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2875 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2876 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2877 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2878 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2879 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2880 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2881 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2882 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2883 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2884 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2885 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2886 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2887 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2888 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2889 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2890 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2891 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2892 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2893 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2894 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2895 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2896 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2897 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2898 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2899 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2900 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2901 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2902 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2903 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2904 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2905 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2906 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2907 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2908 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2909/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2910 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2911 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2912 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2913 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2914 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2915 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2916
2917 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2918 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2919 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2920 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2921 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2922 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2923 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2924 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2925 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2926 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2927 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2928 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2929 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2930 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2931 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2932 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2933 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2934 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2935 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2936 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2937 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2938 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2939 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2940 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2941 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2942 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2943 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2944 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2945 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2946 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2947 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2948 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2949 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2950 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2951 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2952 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2953 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2954 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2955 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2956 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2957 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2958 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2959 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2960 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2961 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2962 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2963 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2964/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2965 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2966 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2967 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2968 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2969 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2970 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2971#endif /* VBOX_WITH_STATISTICS */
2972} PGM;
2973/** Pointer to the PGM instance data. */
2974typedef PGM *PPGM;
2975
2976
2977/**
2978 * PGMCPU Data (part of VMCPU).
2979 */
2980typedef struct PGMCPU
2981{
2982 /** Offset to the VMCPU structure. */
2983 RTINT offVMCPU;
2984 /** Automatically tracked physical memory mapping set.
2985 * Ring-0 and strict raw-mode builds. */
2986 PGMMAPSET AutoSet;
2987} PGMCPU;
2988/** Pointer to the per-cpu PGM data. */
2989typedef PGMCPU *PPGMCPU;
2990
2991
2992/** @name PGM::fSyncFlags Flags
2993 * @{
2994 */
2995/** Updates the virtual access handler state bit in PGMPAGE. */
2996#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2997/** Always sync CR3. */
2998#define PGM_SYNC_ALWAYS RT_BIT(1)
2999/** Check monitoring on next CR3 (re)load and invalidate page. */
3000#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3001/** Check guest mapping in SyncCR3. */
3002#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3003/** Clear the page pool (a light weight flush). */
3004#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
3005/** @} */
3006
3007
3008__BEGIN_DECLS
3009
3010int pgmLock(PVM pVM);
3011void pgmUnlock(PVM pVM);
3012
3013VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3014VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3015
3016int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3017int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3018PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3019void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3020DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3021
3022void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3023bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3024int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3025DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3026#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3027void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3028#else
3029# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3030#endif
3031DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3032
3033
3034void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3035int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3036int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3037int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3038#ifdef IN_RING3
3039int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3040int pgmR3PhysRamReset(PVM pVM);
3041int pgmR3PhysRomReset(PVM pVM);
3042# ifndef VBOX_WITH_NEW_PHYS_CODE
3043int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3044# endif
3045
3046int pgmR3PoolInit(PVM pVM);
3047void pgmR3PoolRelocate(PVM pVM);
3048void pgmR3PoolReset(PVM pVM);
3049
3050#endif /* IN_RING3 */
3051#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3052int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3053#endif
3054#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3055void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3056#endif
3057int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3058PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3059void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3060void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3061int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3062void pgmPoolFlushAll(PVM pVM);
3063void pgmPoolClearAll(PVM pVM);
3064int pgmPoolSyncCR3(PVM pVM);
3065void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3066void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3067int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3068PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3069void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3070void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3071uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3072void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3073#ifdef PGMPOOL_WITH_MONITORING
3074void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3075int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3076void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3077void pgmPoolMonitorModifiedClearAll(PVM pVM);
3078int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3079int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3080#endif
3081
3082#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3083void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3084void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3085int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3086#endif
3087int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3088int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3089
3090#ifndef IN_RC
3091int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3092#endif
3093int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3094
3095__END_DECLS
3096
3097
3098/**
3099 * Gets the PGMRAMRANGE structure for a guest page.
3100 *
3101 * @returns Pointer to the RAM range on success.
3102 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3103 *
3104 * @param pPGM PGM handle.
3105 * @param GCPhys The GC physical address.
3106 */
3107DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3108{
3109 /*
3110 * Optimize for the first range.
3111 */
3112 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3113 RTGCPHYS off = GCPhys - pRam->GCPhys;
3114 if (RT_UNLIKELY(off >= pRam->cb))
3115 {
3116 do
3117 {
3118 pRam = pRam->CTX_SUFF(pNext);
3119 if (RT_UNLIKELY(!pRam))
3120 break;
3121 off = GCPhys - pRam->GCPhys;
3122 } while (off >= pRam->cb);
3123 }
3124 return pRam;
3125}
3126
3127
3128/**
3129 * Gets the PGMPAGE structure for a guest page.
3130 *
3131 * @returns Pointer to the page on success.
3132 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3133 *
3134 * @param pPGM PGM handle.
3135 * @param GCPhys The GC physical address.
3136 */
3137DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3138{
3139 /*
3140 * Optimize for the first range.
3141 */
3142 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3143 RTGCPHYS off = GCPhys - pRam->GCPhys;
3144 if (RT_UNLIKELY(off >= pRam->cb))
3145 {
3146 do
3147 {
3148 pRam = pRam->CTX_SUFF(pNext);
3149 if (RT_UNLIKELY(!pRam))
3150 return NULL;
3151 off = GCPhys - pRam->GCPhys;
3152 } while (off >= pRam->cb);
3153 }
3154 return &pRam->aPages[off >> PAGE_SHIFT];
3155}
3156
3157
3158/**
3159 * Gets the PGMPAGE structure for a guest page.
3160 *
3161 * Old Phys code: Will make sure the page is present.
3162 *
3163 * @returns VBox status code.
3164 * @retval VINF_SUCCESS and a valid *ppPage on success.
3165 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3166 *
3167 * @param pPGM PGM handle.
3168 * @param GCPhys The GC physical address.
3169 * @param ppPage Where to store the page poitner on success.
3170 */
3171DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3172{
3173 /*
3174 * Optimize for the first range.
3175 */
3176 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3177 RTGCPHYS off = GCPhys - pRam->GCPhys;
3178 if (RT_UNLIKELY(off >= pRam->cb))
3179 {
3180 do
3181 {
3182 pRam = pRam->CTX_SUFF(pNext);
3183 if (RT_UNLIKELY(!pRam))
3184 {
3185 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3186 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3187 }
3188 off = GCPhys - pRam->GCPhys;
3189 } while (off >= pRam->cb);
3190 }
3191 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3192#ifndef VBOX_WITH_NEW_PHYS_CODE
3193
3194 /*
3195 * Make sure it's present.
3196 */
3197 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3198 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3199 {
3200#ifdef IN_RING3
3201 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3202#else
3203 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3204#endif
3205 if (RT_FAILURE(rc))
3206 {
3207 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3208 return rc;
3209 }
3210 Assert(rc == VINF_SUCCESS);
3211 }
3212#endif
3213 return VINF_SUCCESS;
3214}
3215
3216
3217
3218
3219/**
3220 * Gets the PGMPAGE structure for a guest page.
3221 *
3222 * Old Phys code: Will make sure the page is present.
3223 *
3224 * @returns VBox status code.
3225 * @retval VINF_SUCCESS and a valid *ppPage on success.
3226 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3227 *
3228 * @param pPGM PGM handle.
3229 * @param GCPhys The GC physical address.
3230 * @param ppPage Where to store the page poitner on success.
3231 * @param ppRamHint Where to read and store the ram list hint.
3232 * The caller initializes this to NULL before the call.
3233 */
3234DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3235{
3236 RTGCPHYS off;
3237 PPGMRAMRANGE pRam = *ppRamHint;
3238 if ( !pRam
3239 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3240 {
3241 pRam = pPGM->CTX_SUFF(pRamRanges);
3242 off = GCPhys - pRam->GCPhys;
3243 if (RT_UNLIKELY(off >= pRam->cb))
3244 {
3245 do
3246 {
3247 pRam = pRam->CTX_SUFF(pNext);
3248 if (RT_UNLIKELY(!pRam))
3249 {
3250 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3251 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3252 }
3253 off = GCPhys - pRam->GCPhys;
3254 } while (off >= pRam->cb);
3255 }
3256 *ppRamHint = pRam;
3257 }
3258 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3259#ifndef VBOX_WITH_NEW_PHYS_CODE
3260
3261 /*
3262 * Make sure it's present.
3263 */
3264 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3265 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3266 {
3267#ifdef IN_RING3
3268 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3269#else
3270 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3271#endif
3272 if (RT_FAILURE(rc))
3273 {
3274 *ppPage = NULL; /* Shut up annoying smart ass. */
3275 return rc;
3276 }
3277 Assert(rc == VINF_SUCCESS);
3278 }
3279#endif
3280 return VINF_SUCCESS;
3281}
3282
3283
3284/**
3285 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3286 *
3287 * @returns Pointer to the page on success.
3288 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3289 *
3290 * @param pPGM PGM handle.
3291 * @param GCPhys The GC physical address.
3292 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3293 */
3294DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3295{
3296 /*
3297 * Optimize for the first range.
3298 */
3299 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3300 RTGCPHYS off = GCPhys - pRam->GCPhys;
3301 if (RT_UNLIKELY(off >= pRam->cb))
3302 {
3303 do
3304 {
3305 pRam = pRam->CTX_SUFF(pNext);
3306 if (RT_UNLIKELY(!pRam))
3307 return NULL;
3308 off = GCPhys - pRam->GCPhys;
3309 } while (off >= pRam->cb);
3310 }
3311 *ppRam = pRam;
3312 return &pRam->aPages[off >> PAGE_SHIFT];
3313}
3314
3315
3316/**
3317 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3318 *
3319 * @returns Pointer to the page on success.
3320 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3321 *
3322 * @param pPGM PGM handle.
3323 * @param GCPhys The GC physical address.
3324 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3325 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3326 */
3327DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3328{
3329 /*
3330 * Optimize for the first range.
3331 */
3332 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3333 RTGCPHYS off = GCPhys - pRam->GCPhys;
3334 if (RT_UNLIKELY(off >= pRam->cb))
3335 {
3336 do
3337 {
3338 pRam = pRam->CTX_SUFF(pNext);
3339 if (RT_UNLIKELY(!pRam))
3340 {
3341 *ppRam = NULL; /* Shut up silly GCC warnings. */
3342 *ppPage = NULL; /* ditto */
3343 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3344 }
3345 off = GCPhys - pRam->GCPhys;
3346 } while (off >= pRam->cb);
3347 }
3348 *ppRam = pRam;
3349 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3350#ifndef VBOX_WITH_NEW_PHYS_CODE
3351
3352 /*
3353 * Make sure it's present.
3354 */
3355 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3356 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3357 {
3358#ifdef IN_RING3
3359 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3360#else
3361 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3362#endif
3363 if (RT_FAILURE(rc))
3364 {
3365 *ppPage = NULL; /* Shut up silly GCC warnings. */
3366 *ppPage = NULL; /* ditto */
3367 return rc;
3368 }
3369 Assert(rc == VINF_SUCCESS);
3370
3371 }
3372#endif
3373 return VINF_SUCCESS;
3374}
3375
3376
3377/**
3378 * Convert GC Phys to HC Phys.
3379 *
3380 * @returns VBox status.
3381 * @param pPGM PGM handle.
3382 * @param GCPhys The GC physical address.
3383 * @param pHCPhys Where to store the corresponding HC physical address.
3384 *
3385 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3386 * Avoid when writing new code!
3387 */
3388DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3389{
3390 PPGMPAGE pPage;
3391 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3392 if (RT_FAILURE(rc))
3393 return rc;
3394 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3395 return VINF_SUCCESS;
3396}
3397
3398#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3399
3400/**
3401 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3402 * optimizes access to pages already in the set.
3403 *
3404 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3405 * @param pPGM Pointer to the PVM instance data.
3406 * @param HCPhys The physical address of the page.
3407 * @param ppv Where to store the mapping address.
3408 */
3409DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3410{
3411 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3412 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3413 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3414 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3415
3416 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3417 unsigned iEntry = pSet->aiHashTable[iHash];
3418 if ( iEntry < pSet->cEntries
3419 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3420 {
3421 *ppv = pSet->aEntries[iEntry].pvPage;
3422 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3423 }
3424 else
3425 {
3426 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3427 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3428 }
3429
3430 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3431 return VINF_SUCCESS;
3432}
3433
3434
3435/**
3436 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3437 * access to pages already in the set.
3438 *
3439 * @returns See PGMDynMapGCPage.
3440 * @param pPGM Pointer to the PVM instance data.
3441 * @param HCPhys The physical address of the page.
3442 * @param ppv Where to store the mapping address.
3443 */
3444DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3445{
3446 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3447 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3448
3449 /*
3450 * Get the ram range.
3451 */
3452 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3453 RTGCPHYS off = GCPhys - pRam->GCPhys;
3454 if (RT_UNLIKELY(off >= pRam->cb
3455 /** @todo || page state stuff */))
3456 {
3457 /* This case is not counted into StatR0DynMapGCPageInl. */
3458 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3459 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3460 }
3461
3462 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3463 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3464
3465 /*
3466 * pgmR0DynMapHCPageInlined with out stats.
3467 */
3468 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3469 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3470 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3471
3472 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3473 unsigned iEntry = pSet->aiHashTable[iHash];
3474 if ( iEntry < pSet->cEntries
3475 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3476 {
3477 *ppv = pSet->aEntries[iEntry].pvPage;
3478 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3479 }
3480 else
3481 {
3482 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3483 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3484 }
3485
3486 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3487 return VINF_SUCCESS;
3488}
3489
3490#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3491#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3492
3493/**
3494 * Maps the page into current context (RC and maybe R0).
3495 *
3496 * @returns pointer to the mapping.
3497 * @param pVM Pointer to the PGM instance data.
3498 * @param pPage The page.
3499 */
3500DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3501{
3502 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3503 {
3504 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3505 void *pv;
3506# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3507 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3508# else
3509 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3510# endif
3511 return pv;
3512 }
3513 return pgmPoolMapPageFallback(pPGM, pPage);
3514}
3515
3516/**
3517 * Temporarily maps one host page specified by HC physical address, returning
3518 * pointer within the page.
3519 *
3520 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3521 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3522 *
3523 * @returns The address corresponding to HCPhys.
3524 * @param pPGM Pointer to the PVM instance data.
3525 * @param HCPhys HC Physical address of the page.
3526 */
3527DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3528{
3529 void *pv;
3530# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3531 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3532# else
3533 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3534# endif
3535 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3536 return pv;
3537}
3538
3539#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3540
3541#ifndef IN_RC
3542/**
3543 * Queries the Physical TLB entry for a physical guest page,
3544 * attemting to load the TLB entry if necessary.
3545 *
3546 * @returns VBox status code.
3547 * @retval VINF_SUCCESS on success
3548 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3549 * @param pPGM The PGM instance handle.
3550 * @param GCPhys The address of the guest page.
3551 * @param ppTlbe Where to store the pointer to the TLB entry.
3552 */
3553
3554DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3555{
3556 int rc;
3557 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3558 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3559 {
3560 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3561 rc = VINF_SUCCESS;
3562 }
3563 else
3564 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3565 *ppTlbe = pTlbe;
3566 return rc;
3567}
3568#endif /* !IN_RC */
3569
3570
3571/**
3572 * Convert GC Phys to HC Virt and HC Phys.
3573 *
3574 * @returns VBox status.
3575 * @param pPGM PGM handle.
3576 * @param GCPhys The GC physical address.
3577 * @param pHCPtr Where to store the corresponding HC virtual address.
3578 * @param pHCPhys Where to store the HC Physical address and its flags.
3579 *
3580 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3581 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3582 * Either way, we have to make sure the page is writable in MapCR3.
3583 */
3584DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3585{
3586 PPGMRAMRANGE pRam;
3587 PPGMPAGE pPage;
3588 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3589 if (RT_FAILURE(rc))
3590 {
3591 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3592 *pHCPhys = 0; /* ditto */
3593 return rc;
3594 }
3595 RTGCPHYS off = GCPhys - pRam->GCPhys;
3596
3597 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3598 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3599 {
3600 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3601#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3602 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3603 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3604#else
3605 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3606#endif
3607 return VINF_SUCCESS;
3608 }
3609 if (pRam->pvR3)
3610 {
3611 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3612 return VINF_SUCCESS;
3613 }
3614 *pHCPtr = 0;
3615 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3616}
3617
3618
3619/**
3620 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3621 * Takes PSE-36 into account.
3622 *
3623 * @returns guest physical address
3624 * @param pPGM Pointer to the PGM instance data.
3625 * @param Pde Guest Pde
3626 */
3627DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3628{
3629 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3630 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3631
3632 return GCPhys & pPGM->GCPhys4MBPSEMask;
3633}
3634
3635
3636/**
3637 * Gets the page directory entry for the specified address (32-bit paging).
3638 *
3639 * @returns The page directory entry in question.
3640 * @param pPGM Pointer to the PGM instance data.
3641 * @param GCPtr The address.
3642 */
3643DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3644{
3645#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3646 PCX86PD pGuestPD = 0;
3647 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3648 if (RT_FAILURE(rc))
3649 {
3650 X86PDE ZeroPde = {0};
3651 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3652 }
3653 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3654#else
3655 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3656#endif
3657}
3658
3659
3660/**
3661 * Gets the address of a specific page directory entry (32-bit paging).
3662 *
3663 * @returns Pointer the page directory entry in question.
3664 * @param pPGM Pointer to the PGM instance data.
3665 * @param GCPtr The address.
3666 */
3667DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3668{
3669#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3670 PX86PD pGuestPD = 0;
3671 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3672 AssertRCReturn(rc, 0);
3673 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3674#else
3675 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3676#endif
3677}
3678
3679
3680/**
3681 * Gets the address the guest page directory (32-bit paging).
3682 *
3683 * @returns Pointer the page directory entry in question.
3684 * @param pPGM Pointer to the PGM instance data.
3685 */
3686DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3687{
3688#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3689 PX86PD pGuestPD = 0;
3690 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3691 AssertRCReturn(rc, 0);
3692 return pGuestPD;
3693#else
3694 return pPGM->CTX_SUFF(pGst32BitPd);
3695#endif
3696}
3697
3698
3699/**
3700 * Gets the guest page directory pointer table.
3701 *
3702 * @returns Pointer to the page directory in question.
3703 * @returns NULL if the page directory is not present or on an invalid page.
3704 * @param pPGM Pointer to the PGM instance data.
3705 */
3706DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3707{
3708#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3709 PX86PDPT pGuestPDPT = 0;
3710 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3711 AssertRCReturn(rc, 0);
3712 return pGuestPDPT;
3713#else
3714 return pPGM->CTX_SUFF(pGstPaePdpt);
3715#endif
3716}
3717
3718
3719/**
3720 * Gets the guest page directory pointer table entry for the specified address.
3721 *
3722 * @returns Pointer to the page directory in question.
3723 * @returns NULL if the page directory is not present or on an invalid page.
3724 * @param pPGM Pointer to the PGM instance data.
3725 * @param GCPtr The address.
3726 */
3727DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3728{
3729 AssertGCPtr32(GCPtr);
3730
3731#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3732 PX86PDPT pGuestPDPT = 0;
3733 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3734 AssertRCReturn(rc, 0);
3735 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3736#else
3737 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3738#endif
3739}
3740
3741
3742/**
3743 * Gets the page directory for the specified address.
3744 *
3745 * @returns Pointer to the page directory in question.
3746 * @returns NULL if the page directory is not present or on an invalid page.
3747 * @param pPGM Pointer to the PGM instance data.
3748 * @param GCPtr The address.
3749 */
3750DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3751{
3752 AssertGCPtr32(GCPtr);
3753
3754#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3755 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3756 AssertReturn(pGuestPDPT, 0);
3757#else
3758 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3759#endif
3760 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3761 if (pGuestPDPT->a[iPdPt].n.u1Present)
3762 {
3763#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3764 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3765 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3766#endif
3767
3768 /* cache is out-of-sync. */
3769 PX86PDPAE pPD;
3770 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3771 if (RT_SUCCESS(rc))
3772 return pPD;
3773 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3774 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3775 }
3776 return NULL;
3777}
3778
3779
3780/**
3781 * Gets the page directory entry for the specified address.
3782 *
3783 * @returns Pointer to the page directory entry in question.
3784 * @returns NULL if the page directory is not present or on an invalid page.
3785 * @param pPGM Pointer to the PGM instance data.
3786 * @param GCPtr The address.
3787 */
3788DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3789{
3790 AssertGCPtr32(GCPtr);
3791
3792#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3793 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3794 AssertReturn(pGuestPDPT, 0);
3795#else
3796 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3797#endif
3798 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3799 if (pGuestPDPT->a[iPdPt].n.u1Present)
3800 {
3801 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3802#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3803 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3804 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3805#endif
3806
3807 /* The cache is out-of-sync. */
3808 PX86PDPAE pPD;
3809 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3810 if (RT_SUCCESS(rc))
3811 return &pPD->a[iPD];
3812 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3813 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3814 }
3815 return NULL;
3816}
3817
3818
3819/**
3820 * Gets the page directory entry for the specified address.
3821 *
3822 * @returns The page directory entry in question.
3823 * @returns A non-present entry if the page directory is not present or on an invalid page.
3824 * @param pPGM Pointer to the PGM instance data.
3825 * @param GCPtr The address.
3826 */
3827DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3828{
3829 AssertGCPtr32(GCPtr);
3830
3831#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3832 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3833 if (RT_LIKELY(pGuestPDPT))
3834#else
3835 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3836#endif
3837 {
3838 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3839 if (pGuestPDPT->a[iPdPt].n.u1Present)
3840 {
3841 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3842#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3843 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3844 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3845#endif
3846
3847 /* cache is out-of-sync. */
3848 PX86PDPAE pPD;
3849 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3850 if (RT_SUCCESS(rc))
3851 return pPD->a[iPD];
3852 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3853 }
3854 }
3855 X86PDEPAE ZeroPde = {0};
3856 return ZeroPde;
3857}
3858
3859
3860/**
3861 * Gets the page directory pointer table entry for the specified address
3862 * and returns the index into the page directory
3863 *
3864 * @returns Pointer to the page directory in question.
3865 * @returns NULL if the page directory is not present or on an invalid page.
3866 * @param pPGM Pointer to the PGM instance data.
3867 * @param GCPtr The address.
3868 * @param piPD Receives the index into the returned page directory
3869 * @param pPdpe Receives the page directory pointer entry. Optional.
3870 */
3871DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3872{
3873 AssertGCPtr32(GCPtr);
3874
3875#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3876 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3877 AssertReturn(pGuestPDPT, 0);
3878#else
3879 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3880#endif
3881 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3882 if (pPdpe)
3883 *pPdpe = pGuestPDPT->a[iPdPt];
3884 if (pGuestPDPT->a[iPdPt].n.u1Present)
3885 {
3886 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3887#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3888 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3889 {
3890 *piPD = iPD;
3891 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3892 }
3893#endif
3894
3895 /* cache is out-of-sync. */
3896 PX86PDPAE pPD;
3897 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3898 if (RT_SUCCESS(rc))
3899 {
3900 *piPD = iPD;
3901 return pPD;
3902 }
3903 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3904 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3905 }
3906 return NULL;
3907}
3908
3909#ifndef IN_RC
3910
3911/**
3912 * Gets the page map level-4 pointer for the guest.
3913 *
3914 * @returns Pointer to the PML4 page.
3915 * @param pPGM Pointer to the PGM instance data.
3916 */
3917DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3918{
3919#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3920 PX86PML4 pGuestPml4;
3921 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3922 AssertRCReturn(rc, NULL);
3923 return pGuestPml4;
3924#else
3925 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3926 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3927#endif
3928}
3929
3930
3931/**
3932 * Gets the pointer to a page map level-4 entry.
3933 *
3934 * @returns Pointer to the PML4 entry.
3935 * @param pPGM Pointer to the PGM instance data.
3936 * @param iPml4 The index.
3937 */
3938DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3939{
3940#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3941 PX86PML4 pGuestPml4;
3942 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3943 AssertRCReturn(rc, NULL);
3944 return &pGuestPml4->a[iPml4];
3945#else
3946 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3947 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3948#endif
3949}
3950
3951
3952/**
3953 * Gets a page map level-4 entry.
3954 *
3955 * @returns The PML4 entry.
3956 * @param pPGM Pointer to the PGM instance data.
3957 * @param iPml4 The index.
3958 */
3959DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3960{
3961#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3962 PX86PML4 pGuestPml4;
3963 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3964 if (RT_FAILURE(rc))
3965 {
3966 X86PML4E ZeroPml4e = {0};
3967 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3968 }
3969 return pGuestPml4->a[iPml4];
3970#else
3971 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3972 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3973#endif
3974}
3975
3976
3977/**
3978 * Gets the page directory pointer entry for the specified address.
3979 *
3980 * @returns Pointer to the page directory pointer entry in question.
3981 * @returns NULL if the page directory is not present or on an invalid page.
3982 * @param pPGM Pointer to the PGM instance data.
3983 * @param GCPtr The address.
3984 * @param ppPml4e Page Map Level-4 Entry (out)
3985 */
3986DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3987{
3988 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3989 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3990 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3991 if (pPml4e->n.u1Present)
3992 {
3993 PX86PDPT pPdpt;
3994 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3995 AssertRCReturn(rc, NULL);
3996
3997 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3998 return &pPdpt->a[iPdPt];
3999 }
4000 return NULL;
4001}
4002
4003
4004/**
4005 * Gets the page directory entry for the specified address.
4006 *
4007 * @returns The page directory entry in question.
4008 * @returns A non-present entry if the page directory is not present or on an invalid page.
4009 * @param pPGM Pointer to the PGM instance data.
4010 * @param GCPtr The address.
4011 * @param ppPml4e Page Map Level-4 Entry (out)
4012 * @param pPdpe Page directory pointer table entry (out)
4013 */
4014DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4015{
4016 X86PDEPAE ZeroPde = {0};
4017 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4018 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4019 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4020 if (pPml4e->n.u1Present)
4021 {
4022 PCX86PDPT pPdptTemp;
4023 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4024 AssertRCReturn(rc, ZeroPde);
4025
4026 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4027 *pPdpe = pPdptTemp->a[iPdPt];
4028 if (pPdptTemp->a[iPdPt].n.u1Present)
4029 {
4030 PCX86PDPAE pPD;
4031 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4032 AssertRCReturn(rc, ZeroPde);
4033
4034 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4035 return pPD->a[iPD];
4036 }
4037 }
4038
4039 return ZeroPde;
4040}
4041
4042
4043/**
4044 * Gets the page directory entry for the specified address.
4045 *
4046 * @returns The page directory entry in question.
4047 * @returns A non-present entry if the page directory is not present or on an invalid page.
4048 * @param pPGM Pointer to the PGM instance data.
4049 * @param GCPtr The address.
4050 */
4051DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4052{
4053 X86PDEPAE ZeroPde = {0};
4054 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4055 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4056 if (pGuestPml4->a[iPml4].n.u1Present)
4057 {
4058 PCX86PDPT pPdptTemp;
4059 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4060 AssertRCReturn(rc, ZeroPde);
4061
4062 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4063 if (pPdptTemp->a[iPdPt].n.u1Present)
4064 {
4065 PCX86PDPAE pPD;
4066 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4067 AssertRCReturn(rc, ZeroPde);
4068
4069 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4070 return pPD->a[iPD];
4071 }
4072 }
4073 return ZeroPde;
4074}
4075
4076
4077/**
4078 * Gets the page directory entry for the specified address.
4079 *
4080 * @returns Pointer to the page directory entry in question.
4081 * @returns NULL if the page directory is not present or on an invalid page.
4082 * @param pPGM Pointer to the PGM instance data.
4083 * @param GCPtr The address.
4084 */
4085DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4086{
4087 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4088 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4089 if (pGuestPml4->a[iPml4].n.u1Present)
4090 {
4091 PCX86PDPT pPdptTemp;
4092 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4093 AssertRCReturn(rc, NULL);
4094
4095 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4096 if (pPdptTemp->a[iPdPt].n.u1Present)
4097 {
4098 PX86PDPAE pPD;
4099 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4100 AssertRCReturn(rc, NULL);
4101
4102 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4103 return &pPD->a[iPD];
4104 }
4105 }
4106 return NULL;
4107}
4108
4109
4110/**
4111 * Gets the GUEST page directory pointer for the specified address.
4112 *
4113 * @returns The page directory in question.
4114 * @returns NULL if the page directory is not present or on an invalid page.
4115 * @param pPGM Pointer to the PGM instance data.
4116 * @param GCPtr The address.
4117 * @param ppPml4e Page Map Level-4 Entry (out)
4118 * @param pPdpe Page directory pointer table entry (out)
4119 * @param piPD Receives the index into the returned page directory
4120 */
4121DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4122{
4123 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4124 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4125 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4126 if (pPml4e->n.u1Present)
4127 {
4128 PCX86PDPT pPdptTemp;
4129 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4130 AssertRCReturn(rc, NULL);
4131
4132 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4133 *pPdpe = pPdptTemp->a[iPdPt];
4134 if (pPdptTemp->a[iPdPt].n.u1Present)
4135 {
4136 PX86PDPAE pPD;
4137 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4138 AssertRCReturn(rc, NULL);
4139
4140 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4141 return pPD;
4142 }
4143 }
4144 return 0;
4145}
4146
4147#endif /* !IN_RC */
4148
4149/**
4150 * Gets the shadow page directory, 32-bit.
4151 *
4152 * @returns Pointer to the shadow 32-bit PD.
4153 * @param pPGM Pointer to the PGM instance data.
4154 */
4155DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4156{
4157#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4158 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4159#else
4160# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4161 PX86PD pShwPd;
4162 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4163 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4164 AssertRCReturn(rc, NULL);
4165 return pShwPd;
4166# else
4167 return pPGM->CTX_SUFF(pShw32BitPd);
4168# endif
4169#endif
4170}
4171
4172
4173/**
4174 * Gets the shadow page directory entry for the specified address, 32-bit.
4175 *
4176 * @returns Shadow 32-bit PDE.
4177 * @param pPGM Pointer to the PGM instance data.
4178 * @param GCPtr The address.
4179 */
4180DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4181{
4182 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4183
4184 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4185 if (!pShwPde)
4186 {
4187 X86PDE ZeroPde = {0};
4188 return ZeroPde;
4189 }
4190 return pShwPde->a[iPd];
4191}
4192
4193
4194/**
4195 * Gets the pointer to the shadow page directory entry for the specified
4196 * address, 32-bit.
4197 *
4198 * @returns Pointer to the shadow 32-bit PDE.
4199 * @param pPGM Pointer to the PGM instance data.
4200 * @param GCPtr The address.
4201 */
4202DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4203{
4204 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4205
4206 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4207 AssertReturn(pPde, NULL);
4208 return &pPde->a[iPd];
4209}
4210
4211
4212/**
4213 * Gets the shadow page pointer table, PAE.
4214 *
4215 * @returns Pointer to the shadow PAE PDPT.
4216 * @param pPGM Pointer to the PGM instance data.
4217 */
4218DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4219{
4220#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4221 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4222#else
4223# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4224 PX86PDPT pShwPdpt;
4225 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4226 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4227 AssertRCReturn(rc, 0);
4228 return pShwPdpt;
4229# else
4230 return pPGM->CTX_SUFF(pShwPaePdpt);
4231# endif
4232#endif
4233}
4234
4235
4236/**
4237 * Gets the shadow page directory for the specified address, PAE.
4238 *
4239 * @returns Pointer to the shadow PD.
4240 * @param pPGM Pointer to the PGM instance data.
4241 * @param GCPtr The address.
4242 */
4243DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4244{
4245#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4246 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4247 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4248
4249 if (!pPdpt->a[iPdpt].n.u1Present)
4250 return NULL;
4251
4252 /* Fetch the pgm pool shadow descriptor. */
4253 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4254 AssertReturn(pShwPde, NULL);
4255
4256 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4257#else
4258 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4259# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4260 PX86PDPAE pPD;
4261 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4262 AssertRCReturn(rc, 0);
4263 return pPD;
4264# else
4265 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4266 Assert(pPD);
4267 return pPD;
4268# endif
4269#endif
4270}
4271
4272
4273/**
4274 * Gets the shadow page directory for the specified address, PAE.
4275 *
4276 * @returns Pointer to the shadow PD.
4277 * @param pPGM Pointer to the PGM instance data.
4278 * @param GCPtr The address.
4279 */
4280DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4281{
4282#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4283 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4284
4285 if (!pPdpt->a[iPdpt].n.u1Present)
4286 return NULL;
4287
4288 /* Fetch the pgm pool shadow descriptor. */
4289 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4290 AssertReturn(pShwPde, NULL);
4291
4292 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4293#else
4294 AssertFailed();
4295 return NULL;
4296#endif
4297}
4298
4299
4300/**
4301 * Gets the shadow page directory entry, PAE.
4302 *
4303 * @returns PDE.
4304 * @param pPGM Pointer to the PGM instance data.
4305 * @param GCPtr The address.
4306 */
4307DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4308{
4309 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4310
4311 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4312 if (!pShwPde)
4313 {
4314 X86PDEPAE ZeroPde = {0};
4315 return ZeroPde;
4316 }
4317 return pShwPde->a[iPd];
4318}
4319
4320
4321/**
4322 * Gets the pointer to the shadow page directory entry for an address, PAE.
4323 *
4324 * @returns Pointer to the PDE.
4325 * @param pPGM Pointer to the PGM instance data.
4326 * @param GCPtr The address.
4327 */
4328DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4329{
4330 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4331
4332 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4333 AssertReturn(pPde, NULL);
4334 return &pPde->a[iPd];
4335}
4336
4337#ifndef IN_RC
4338
4339/**
4340 * Gets the shadow page map level-4 pointer.
4341 *
4342 * @returns Pointer to the shadow PML4.
4343 * @param pPGM Pointer to the PGM instance data.
4344 */
4345DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4346{
4347#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4348 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4349#else
4350# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4351 PX86PML4 pShwPml4;
4352 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4353 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4354 AssertRCReturn(rc, 0);
4355 return pShwPml4;
4356# else
4357 Assert(pPGM->CTX_SUFF(pShwRoot));
4358 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4359# endif
4360#endif
4361}
4362
4363
4364/**
4365 * Gets the shadow page map level-4 entry for the specified address.
4366 *
4367 * @returns The entry.
4368 * @param pPGM Pointer to the PGM instance data.
4369 * @param GCPtr The address.
4370 */
4371DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4372{
4373 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4374 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4375
4376 if (!pShwPml4)
4377 {
4378 X86PML4E ZeroPml4e = {0};
4379 return ZeroPml4e;
4380 }
4381 return pShwPml4->a[iPml4];
4382}
4383
4384
4385/**
4386 * Gets the pointer to the specified shadow page map level-4 entry.
4387 *
4388 * @returns The entry.
4389 * @param pPGM Pointer to the PGM instance data.
4390 * @param iPml4 The PML4 index.
4391 */
4392DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4393{
4394 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4395 if (!pShwPml4)
4396 return NULL;
4397 return &pShwPml4->a[iPml4];
4398}
4399
4400
4401/**
4402 * Gets the GUEST page directory pointer for the specified address.
4403 *
4404 * @returns The page directory in question.
4405 * @returns NULL if the page directory is not present or on an invalid page.
4406 * @param pPGM Pointer to the PGM instance data.
4407 * @param GCPtr The address.
4408 * @param piPD Receives the index into the returned page directory
4409 */
4410DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4411{
4412 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4413 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4414 if (pGuestPml4->a[iPml4].n.u1Present)
4415 {
4416 PCX86PDPT pPdptTemp;
4417 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4418 AssertRCReturn(rc, NULL);
4419
4420 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4421 if (pPdptTemp->a[iPdPt].n.u1Present)
4422 {
4423 PX86PDPAE pPD;
4424 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4425 AssertRCReturn(rc, NULL);
4426
4427 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4428 return pPD;
4429 }
4430 }
4431 return NULL;
4432}
4433
4434#endif /* !IN_RC */
4435
4436/**
4437 * Gets the page state for a physical handler.
4438 *
4439 * @returns The physical handler page state.
4440 * @param pCur The physical handler in question.
4441 */
4442DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4443{
4444 switch (pCur->enmType)
4445 {
4446 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4447 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4448
4449 case PGMPHYSHANDLERTYPE_MMIO:
4450 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4451 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4452
4453 default:
4454 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4455 }
4456}
4457
4458
4459/**
4460 * Gets the page state for a virtual handler.
4461 *
4462 * @returns The virtual handler page state.
4463 * @param pCur The virtual handler in question.
4464 * @remarks This should never be used on a hypervisor access handler.
4465 */
4466DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4467{
4468 switch (pCur->enmType)
4469 {
4470 case PGMVIRTHANDLERTYPE_WRITE:
4471 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4472 case PGMVIRTHANDLERTYPE_ALL:
4473 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4474 default:
4475 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4476 }
4477}
4478
4479
4480/**
4481 * Clears one physical page of a virtual handler
4482 *
4483 * @param pPGM Pointer to the PGM instance.
4484 * @param pCur Virtual handler structure
4485 * @param iPage Physical page index
4486 *
4487 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4488 * need to care about other handlers in the same page.
4489 */
4490DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4491{
4492 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4493
4494 /*
4495 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4496 */
4497#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4498 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4499 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4500 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4501#endif
4502 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4503 {
4504 /* We're the head of the alias chain. */
4505 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4506#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4507 AssertReleaseMsg(pRemove != NULL,
4508 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4509 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4510 AssertReleaseMsg(pRemove == pPhys2Virt,
4511 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4512 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4513 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4514 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4515#endif
4516 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4517 {
4518 /* Insert the next list in the alias chain into the tree. */
4519 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4520#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4521 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4522 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4523 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4524#endif
4525 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4526 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4527 AssertRelease(fRc);
4528 }
4529 }
4530 else
4531 {
4532 /* Locate the previous node in the alias chain. */
4533 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4534#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4535 AssertReleaseMsg(pPrev != pPhys2Virt,
4536 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4537 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4538#endif
4539 for (;;)
4540 {
4541 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4542 if (pNext == pPhys2Virt)
4543 {
4544 /* unlink. */
4545 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4546 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4547 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4548 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4549 else
4550 {
4551 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4552 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4553 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4554 }
4555 break;
4556 }
4557
4558 /* next */
4559 if (pNext == pPrev)
4560 {
4561#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4562 AssertReleaseMsg(pNext != pPrev,
4563 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4564 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4565#endif
4566 break;
4567 }
4568 pPrev = pNext;
4569 }
4570 }
4571 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4572 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4573 pPhys2Virt->offNextAlias = 0;
4574 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4575
4576 /*
4577 * Clear the ram flags for this page.
4578 */
4579 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4580 AssertReturnVoid(pPage);
4581 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4582}
4583
4584
4585/**
4586 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4587 *
4588 * @returns Pointer to the shadow page structure.
4589 * @param pPool The pool.
4590 * @param HCPhys The HC physical address of the shadow page.
4591 */
4592DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4593{
4594 /*
4595 * Look up the page.
4596 */
4597 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4598 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4599 return pPage;
4600}
4601
4602
4603/**
4604 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4605 *
4606 * @returns Pointer to the shadow page structure.
4607 * @param pPool The pool.
4608 * @param idx The pool page index.
4609 */
4610DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4611{
4612 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4613 return &pPool->aPages[idx];
4614}
4615
4616
4617#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4618/**
4619 * Clear references to guest physical memory.
4620 *
4621 * @param pPool The pool.
4622 * @param pPoolPage The pool page.
4623 * @param pPhysPage The physical guest page tracking structure.
4624 */
4625DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4626{
4627 /*
4628 * Just deal with the simple case here.
4629 */
4630# ifdef LOG_ENABLED
4631 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4632# endif
4633 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4634 if (cRefs == 1)
4635 {
4636 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4637 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4638 }
4639 else
4640 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4641 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4642}
4643#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4644
4645
4646#ifdef PGMPOOL_WITH_CACHE
4647/**
4648 * Moves the page to the head of the age list.
4649 *
4650 * This is done when the cached page is used in one way or another.
4651 *
4652 * @param pPool The pool.
4653 * @param pPage The cached page.
4654 * @todo inline in PGMInternal.h!
4655 */
4656DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4657{
4658 /*
4659 * Move to the head of the age list.
4660 */
4661 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4662 {
4663 /* unlink */
4664 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4665 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4666 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4667 else
4668 pPool->iAgeTail = pPage->iAgePrev;
4669
4670 /* insert at head */
4671 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4672 pPage->iAgeNext = pPool->iAgeHead;
4673 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4674 pPool->iAgeHead = pPage->idx;
4675 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4676 }
4677}
4678#endif /* PGMPOOL_WITH_CACHE */
4679
4680#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4681
4682/**
4683 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4684 *
4685 * @returns VBox status code.
4686 * @param pVM VM Handle.
4687 * @param pPage PGM pool page
4688 */
4689DECLINLINE(int) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4690{
4691 Assert(!pPage->fLocked);
4692 pPage->fLocked = true;
4693 return VINF_SUCCESS;
4694}
4695
4696
4697/**
4698 * Unlocks a page to allow flushing again
4699 *
4700 * @returns VBox status code.
4701 * @param pVM VM Handle.
4702 * @param pPage PGM pool page
4703 */
4704DECLINLINE(int) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4705{
4706 Assert(pPage->fLocked);
4707 pPage->fLocked = false;
4708 return VINF_SUCCESS;
4709}
4710
4711
4712/**
4713 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4714 *
4715 * @returns VBox status code.
4716 * @param pPage PGM pool page
4717 */
4718DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4719{
4720 if (pPage->fLocked)
4721 {
4722 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4723 if (pPage->cModifications)
4724 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4725 return true;
4726 }
4727 return false;
4728}
4729
4730#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4731
4732/**
4733 * Tells if mappings are to be put into the shadow page table or not
4734 *
4735 * @returns boolean result
4736 * @param pVM VM handle.
4737 */
4738DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4739{
4740#ifdef IN_RING0
4741 /* There are no mappings in VT-x and AMD-V mode. */
4742 Assert(pPGM->fDisableMappings);
4743 return false;
4744#else
4745 return !pPGM->fDisableMappings;
4746#endif
4747}
4748
4749/** @} */
4750
4751#endif
4752
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