VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 23485

Last change on this file since 23485 was 23485, checked in by vboxsync, 16 years ago

PGMPAGE: Optimized tests accessing both u2HandlerPhysStateY and u2HandlerVirtStateY. (saving ~2KB on linux/amd64)
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1/* $Id: PGMInternal.h 23485 2009-10-01 14:14:29Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#if 0 /* disabled again while debugging */
72#ifndef IN_RC
73# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
74#endif
75#endif
76
77/**
78 * Sync N pages instead of a whole page table
79 */
80#define PGM_SYNC_N_PAGES
81
82/**
83 * Number of pages to sync during a page fault
84 *
85 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
86 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
87 *
88 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
89 * world switch overhead, so let's sync more.
90 */
91# ifdef IN_RING0
92/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
93 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
94 * but ~5% fewer faults.
95 */
96# define PGM_SYNC_NR_PAGES 32
97#else
98# define PGM_SYNC_NR_PAGES 8
99#endif
100
101/**
102 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
103 */
104#define PGM_MAX_PHYSCACHE_ENTRIES 64
105#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
106
107/** @def PGMPOOL_WITH_CACHE
108 * Enable agressive caching using the page pool.
109 *
110 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
111 */
112#define PGMPOOL_WITH_CACHE
113
114/** @def PGMPOOL_WITH_MIXED_PT_CR3
115 * When defined, we'll deal with 'uncachable' pages.
116 */
117#ifdef PGMPOOL_WITH_CACHE
118# define PGMPOOL_WITH_MIXED_PT_CR3
119#endif
120
121/** @def PGMPOOL_WITH_MONITORING
122 * Monitor the guest pages which are shadowed.
123 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
124 * be enabled as well.
125 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
126 */
127#ifdef PGMPOOL_WITH_CACHE
128# define PGMPOOL_WITH_MONITORING
129#endif
130
131/** @def PGMPOOL_WITH_GCPHYS_TRACKING
132 * Tracking the of shadow pages mapping guest physical pages.
133 *
134 * This is very expensive, the current cache prototype is trying to figure out
135 * whether it will be acceptable with an agressive caching policy.
136 */
137#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
138# define PGMPOOL_WITH_GCPHYS_TRACKING
139#endif
140
141/** @def PGMPOOL_WITH_USER_TRACKING
142 * Tracking users of shadow pages. This is required for the linking of shadow page
143 * tables and physical guest addresses.
144 */
145#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
146# define PGMPOOL_WITH_USER_TRACKING
147#endif
148
149/** @def PGMPOOL_CFG_MAX_GROW
150 * The maximum number of pages to add to the pool in one go.
151 */
152#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
153
154/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
155 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
156 */
157#ifdef VBOX_STRICT
158# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
159#endif
160
161/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
162 * Enables the experimental lazy page allocation code. */
163/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED 6
213#define PGM_TYPE_EPT 7
214#define PGM_TYPE_MAX PGM_TYPE_EPT
215/** @} */
216
217/** Macro for checking if the guest is using paging.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_PAGING(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_32BIT \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227/** Macro for checking if the guest supports the NX bit.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_NX(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_PAE \
234 && (uShwType) != PGM_TYPE_NESTED \
235 && (uShwType) != PGM_TYPE_EPT)
236
237
238/** @def PGM_HCPHYS_2_PTR
239 * Maps a HC physical page pool address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM handle.
243 * @param HCPhys The HC physical address to map to a virtual one.
244 * @param ppv Where to store the virtual address. No need to cast this.
245 *
246 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
247 * small page window employeed by that function. Be careful.
248 * @remark There is no need to assert on the result.
249 */
250#ifdef IN_RC
251# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
252 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
253#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
258 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_HCPHYS_2_PTR_BY_PGM
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pPGM The PGM instance data.
266 * @param HCPhys The HC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
275 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
276#else
277# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
278 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
279#endif
280
281/** @def PGM_GCPHYS_2_PTR
282 * Maps a GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The VM handle.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290 * small page window employeed by that function. Be careful.
291 * @remark There is no need to assert on the result.
292 */
293#ifdef IN_RC
294# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
295 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
296#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
297# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
301 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pPGM Pointer to the PGM instance data.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
317# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
318 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
321 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
322#endif
323
324/** @def PGM_GCPHYS_2_PTR_EX
325 * Maps a unaligned GC physical page address to a virtual address.
326 *
327 * @returns VBox status code.
328 * @param pVM The VM handle.
329 * @param GCPhys The GC physical address to map to a virtual one.
330 * @param ppv Where to store the virtual address. No need to cast this.
331 *
332 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
333 * small page window employeed by that function. Be careful.
334 * @remark There is no need to assert on the result.
335 */
336#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
339#else
340# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
341 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
342#endif
343
344/** @def PGM_INVL_PG
345 * Invalidates a page.
346 *
347 * @param pVCpu The VMCPU handle.
348 * @param GCVirt The virtual address of the page to invalidate.
349 */
350#ifdef IN_RC
351# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
352#elif defined(IN_RING0)
353# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354#else
355# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356#endif
357
358/** @def PGM_INVL_PG_ALL_VCPU
359 * Invalidates a page on all VCPUs
360 *
361 * @param pVM The VM handle.
362 * @param GCVirt The virtual address of the page to invalidate.
363 */
364#ifdef IN_RC
365# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
366#elif defined(IN_RING0)
367# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368#else
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370#endif
371
372/** @def PGM_INVL_BIG_PG
373 * Invalidates a 4MB page directory entry.
374 *
375 * @param pVCpu The VMCPU handle.
376 * @param GCVirt The virtual address within the page directory to invalidate.
377 */
378#ifdef IN_RC
379# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_VCPU_TLBS()
387 * Invalidates the TLBs of the specified VCPU
388 *
389 * @param pVCpu The VMCPU handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_ALL_VCPU_TLBS()
400 * Invalidates the TLBs of all VCPUs
401 *
402 * @param pVM The VM handle.
403 */
404#ifdef IN_RC
405# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408#else
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410#endif
411
412/** Size of the GCPtrConflict array in PGMMAPPING.
413 * @remarks Must be a power of two. */
414#define PGMMAPPING_CONFLICT_MAX 8
415
416/**
417 * Structure for tracking GC Mappings.
418 *
419 * This structure is used by linked list in both GC and HC.
420 */
421typedef struct PGMMAPPING
422{
423 /** Pointer to next entry. */
424 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425 /** Pointer to next entry. */
426 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427 /** Pointer to next entry. */
428 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429 /** Indicate whether this entry is finalized. */
430 bool fFinalized;
431 /** Start Virtual address. */
432 RTGCPTR GCPtr;
433 /** Last Virtual address (inclusive). */
434 RTGCPTR GCPtrLast;
435 /** Range size (bytes). */
436 RTGCPTR cb;
437 /** Pointer to relocation callback function. */
438 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439 /** User argument to the callback. */
440 R3PTRTYPE(void *) pvUser;
441 /** Mapping description / name. For easing debugging. */
442 R3PTRTYPE(const char *) pszDesc;
443 /** Last 8 addresses that caused conflicts. */
444 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445 /** Number of conflicts for this hypervisor mapping. */
446 uint32_t cConflicts;
447 /** Number of page tables. */
448 uint32_t cPTs;
449
450 /** Array of page table mapping data. Each entry
451 * describes one page table. The array can be longer
452 * than the declared length.
453 */
454 struct
455 {
456 /** The HC physical address of the page table. */
457 RTHCPHYS HCPhysPT;
458 /** The HC physical address of the first PAE page table. */
459 RTHCPHYS HCPhysPaePT0;
460 /** The HC physical address of the second PAE page table. */
461 RTHCPHYS HCPhysPaePT1;
462 /** The HC virtual address of the 32-bit page table. */
463 R3PTRTYPE(PX86PT) pPTR3;
464 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466 /** The RC virtual address of the 32-bit page table. */
467 RCPTRTYPE(PX86PT) pPTRC;
468 /** The RC virtual address of the two PAE page table. */
469 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470 /** The R0 virtual address of the 32-bit page table. */
471 R0PTRTYPE(PX86PT) pPTR0;
472 /** The R0 virtual address of the two PAE page table. */
473 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474 } aPTs[1];
475} PGMMAPPING;
476/** Pointer to structure for tracking GC Mappings. */
477typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480/**
481 * Physical page access handler structure.
482 *
483 * This is used to keep track of physical address ranges
484 * which are being monitored in some kind of way.
485 */
486typedef struct PGMPHYSHANDLER
487{
488 AVLROGCPHYSNODECORE Core;
489 /** Access type. */
490 PGMPHYSHANDLERTYPE enmType;
491 /** Number of pages to update. */
492 uint32_t cPages;
493 /** Pointer to R3 callback function. */
494 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495 /** User argument for R3 handlers. */
496 R3PTRTYPE(void *) pvUserR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499 /** User argument for R0 handlers. */
500 R0PTRTYPE(void *) pvUserR0;
501 /** Pointer to RC callback function. */
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503 /** User argument for RC handlers. */
504 RCPTRTYPE(void *) pvUserRC;
505 /** Description / Name. For easing debugging. */
506 R3PTRTYPE(const char *) pszDesc;
507#ifdef VBOX_WITH_STATISTICS
508 /** Profiling of this handler. */
509 STAMPROFILE Stat;
510#endif
511} PGMPHYSHANDLER;
512/** Pointer to a physical page access handler structure. */
513typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516/**
517 * Cache node for the physical addresses covered by a virtual handler.
518 */
519typedef struct PGMPHYS2VIRTHANDLER
520{
521 /** Core node for the tree based on physical ranges. */
522 AVLROGCPHYSNODECORE Core;
523 /** Offset from this struct to the PGMVIRTHANDLER structure. */
524 int32_t offVirtHandler;
525 /** Offset of the next alias relative to this one.
526 * Bit 0 is used for indicating whether we're in the tree.
527 * Bit 1 is used for indicating that we're the head node.
528 */
529 int32_t offNextAlias;
530} PGMPHYS2VIRTHANDLER;
531/** Pointer to a phys to virtual handler structure. */
532typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535 * node is in the tree. */
536#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538 * node is in the head of an alias chain.
539 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545/**
546 * Virtual page access handler structure.
547 *
548 * This is used to keep track of virtual address ranges
549 * which are being monitored in some kind of way.
550 */
551typedef struct PGMVIRTHANDLER
552{
553 /** Core node for the tree based on virtual ranges. */
554 AVLROGCPTRNODECORE Core;
555 /** Size of the range (in bytes). */
556 RTGCPTR cb;
557 /** Number of cache pages. */
558 uint32_t cPages;
559 /** Access type. */
560 PGMVIRTHANDLERTYPE enmType;
561 /** Pointer to the RC callback function. */
562 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563#if HC_ARCH_BITS == 64
564 RTRCPTR padding;
565#endif
566 /** Pointer to the R3 callback function for invalidation. */
567 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568 /** Pointer to the R3 callback function. */
569 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570 /** Description / Name. For easing debugging. */
571 R3PTRTYPE(const char *) pszDesc;
572#ifdef VBOX_WITH_STATISTICS
573 /** Profiling of this handler. */
574 STAMPROFILE Stat;
575#endif
576 /** Array of cached physical addresses for the monitored ranged. */
577 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578} PGMVIRTHANDLER;
579/** Pointer to a virtual page access handler structure. */
580typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583/**
584 * Page type.
585 *
586 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587 * @remarks This is used in the saved state, so changes to it requires bumping
588 * the saved state version.
589 * @todo So, convert to \#defines!
590 */
591typedef enum PGMPAGETYPE
592{
593 /** The usual invalid zero entry. */
594 PGMPAGETYPE_INVALID = 0,
595 /** RAM page. (RWX) */
596 PGMPAGETYPE_RAM,
597 /** MMIO2 page. (RWX) */
598 PGMPAGETYPE_MMIO2,
599 /** MMIO2 page aliased over an MMIO page. (RWX)
600 * See PGMHandlerPhysicalPageAlias(). */
601 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602 /** Shadowed ROM. (RWX) */
603 PGMPAGETYPE_ROM_SHADOW,
604 /** ROM page. (R-X) */
605 PGMPAGETYPE_ROM,
606 /** MMIO page. (---) */
607 PGMPAGETYPE_MMIO,
608 /** End of valid entries. */
609 PGMPAGETYPE_END
610} PGMPAGETYPE;
611AssertCompile(PGMPAGETYPE_END <= 7);
612
613/** @name Page type predicates.
614 * @{ */
615#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620/** @} */
621
622
623/**
624 * A Physical Guest Page tracking structure.
625 *
626 * The format of this structure is complicated because we have to fit a lot
627 * of information into as few bits as possible. The format is also subject
628 * to change (there is one comming up soon). Which means that for we'll be
629 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
630 * accesses to the structure.
631 */
632typedef struct PGMPAGE
633{
634 /** The physical address and the Page ID. */
635 RTHCPHYS HCPhysAndPageID;
636 /** The page state.
637 * Only 2 bits are really needed for this. */
638 uint8_t uStateY;
639 /** The page type (PGMPAGETYPE).
640 * Only 3 bits are really needed for this. */
641 uint8_t uTypeY;
642
643 /** Combination of:
644 * - [0-7]: u2HandlerPhysStateY - the physical handler state
645 * (PGM_PAGE_HNDL_PHYS_STATE_*).
646 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
647 * (PGM_PAGE_HNDL_VIRT_STATE_*).
648 * - [15]: fWrittenToY - flag indicating that a write monitored page was
649 * written to when set.
650 * - [10-14]: 5 unused bits.
651 * @remarks Warning! All accesses to the bits are hardcoded.
652 */
653 RTUINT16U u16MiscY;
654
655 /** Usage tracking (page pool). */
656 uint16_t u16TrackingY;
657 /** The number of read locks on this page. */
658 uint8_t cReadLocksY;
659 /** The number of write locks on this page. */
660 uint8_t cWriteLocksY;
661} PGMPAGE;
662AssertCompileSize(PGMPAGE, 16);
663/** Pointer to a physical guest page. */
664typedef PGMPAGE *PPGMPAGE;
665/** Pointer to a const physical guest page. */
666typedef const PGMPAGE *PCPGMPAGE;
667/** Pointer to a physical guest page pointer. */
668typedef PPGMPAGE *PPPGMPAGE;
669
670
671/**
672 * Clears the page structure.
673 * @param pPage Pointer to the physical guest page tracking structure.
674 */
675#define PGM_PAGE_CLEAR(pPage) \
676 do { \
677 (pPage)->HCPhysAndPageID = 0; \
678 (pPage)->uStateY = 0; \
679 (pPage)->uTypeY = 0; \
680 (pPage)->u16MiscY.u = 0; \
681 (pPage)->u16TrackingY = 0; \
682 (pPage)->cReadLocksY = 0; \
683 (pPage)->cWriteLocksY = 0; \
684 } while (0)
685
686/**
687 * Initializes the page structure.
688 * @param pPage Pointer to the physical guest page tracking structure.
689 */
690#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
691 do { \
692 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
693 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
694 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
695 (pPage)->uStateY = (_uState); \
696 (pPage)->uTypeY = (_uType); \
697 (pPage)->u16MiscY.u = 0; \
698 (pPage)->u16TrackingY = 0; \
699 (pPage)->cReadLocksY = 0; \
700 (pPage)->cWriteLocksY = 0; \
701 } while (0)
702
703/**
704 * Initializes the page structure of a ZERO page.
705 * @param pPage Pointer to the physical guest page tracking structure.
706 * @param pVM The VM handle (for getting the zero page address).
707 * @param uType The page type (PGMPAGETYPE).
708 */
709#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
710 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
711
712
713/** @name The Page state, PGMPAGE::uStateY.
714 * @{ */
715/** The zero page.
716 * This is a per-VM page that's never ever mapped writable. */
717#define PGM_PAGE_STATE_ZERO 0
718/** A allocated page.
719 * This is a per-VM page allocated from the page pool (or wherever
720 * we get MMIO2 pages from if the type is MMIO2).
721 */
722#define PGM_PAGE_STATE_ALLOCATED 1
723/** A allocated page that's being monitored for writes.
724 * The shadow page table mappings are read-only. When a write occurs, the
725 * fWrittenTo member is set, the page remapped as read-write and the state
726 * moved back to allocated. */
727#define PGM_PAGE_STATE_WRITE_MONITORED 2
728/** The page is shared, aka. copy-on-write.
729 * This is a page that's shared with other VMs. */
730#define PGM_PAGE_STATE_SHARED 3
731/** @} */
732
733
734/**
735 * Gets the page state.
736 * @returns page state (PGM_PAGE_STATE_*).
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
740
741/**
742 * Sets the page state.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 * @param _uState The new page state.
745 */
746#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
747
748
749/**
750 * Gets the host physical address of the guest page.
751 * @returns host physical address (RTHCPHYS).
752 * @param pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
755
756/**
757 * Sets the host physical address of the guest page.
758 * @param pPage Pointer to the physical guest page tracking structure.
759 * @param _HCPhys The new host physical address.
760 */
761#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
762 do { \
763 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
764 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
765 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
766 | (SetHCPhysTmp << (28-12)); \
767 } while (0)
768
769/**
770 * Get the Page ID.
771 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
775
776/**
777 * Sets the Page ID.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 */
780#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
781 do { \
782 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
783 | ((_idPage) & UINT32_C(0x0fffffff)); \
784 } while (0)
785
786/**
787 * Get the Chunk ID.
788 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
789 * @param pPage Pointer to the physical guest page tracking structure.
790 */
791#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
792
793/**
794 * Get the index of the page within the allocation chunk.
795 * @returns The page index.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
799
800/**
801 * Gets the page type.
802 * @returns The page type.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
806
807/**
808 * Sets the page type.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 * @param _enmType The new page type (PGMPAGETYPE).
811 */
812#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
813
814/**
815 * Checks if the page is marked for MMIO.
816 * @returns true/false.
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
820
821/**
822 * Checks if the page is backed by the ZERO page.
823 * @returns true/false.
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
827
828/**
829 * Checks if the page is backed by a SHARED page.
830 * @returns true/false.
831 * @param pPage Pointer to the physical guest page tracking structure.
832 */
833#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
834
835
836/**
837 * Marks the paget as written to (for GMM change monitoring).
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
841
842/**
843 * Clears the written-to indicator.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
847
848/**
849 * Checks if the page was marked as written-to.
850 * @returns true/false.
851 * @param pPage Pointer to the physical guest page tracking structure.
852 */
853#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
854
855
856/** Enabled optimized access handler tests.
857 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
858 * layout. When enabled, the compiler should normally generate more compact
859 * code.
860 */
861#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
862
863/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
864 *
865 * @remarks The values are assigned in order of priority, so we can calculate
866 * the correct state for a page with different handlers installed.
867 * @{ */
868/** No handler installed. */
869#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
870/** Monitoring is temporarily disabled. */
871#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
872/** Write access is monitored. */
873#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
874/** All access is monitored. */
875#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
876/** @} */
877
878/**
879 * Gets the physical access handler state of a page.
880 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 */
883#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
884 ( (pPage)->u16MiscY.au8[0] )
885
886/**
887 * Sets the physical access handler state of a page.
888 * @param pPage Pointer to the physical guest page tracking structure.
889 * @param _uState The new state value.
890 */
891#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
892 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
893
894/**
895 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
896 * @returns true/false
897 * @param pPage Pointer to the physical guest page tracking structure.
898 */
899#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
900 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
901
902/**
903 * Checks if the page has any active physical access handlers.
904 * @returns true/false
905 * @param pPage Pointer to the physical guest page tracking structure.
906 */
907#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
908 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
909
910
911/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
912 *
913 * @remarks The values are assigned in order of priority, so we can calculate
914 * the correct state for a page with different handlers installed.
915 * @{ */
916/** No handler installed. */
917#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
918/* 1 is reserved so the lineup is identical with the physical ones. */
919/** Write access is monitored. */
920#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
921/** All access is monitored. */
922#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
923/** @} */
924
925/**
926 * Gets the virtual access handler state of a page.
927 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) )
931
932/**
933 * Sets the virtual access handler state of a page.
934 * @param pPage Pointer to the physical guest page tracking structure.
935 * @param _uState The new state value.
936 */
937#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
938 do { \
939 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
940 | ((_uState) & UINT8_C(0x03)); \
941 } while (0)
942
943/**
944 * Checks if the page has any virtual access handlers.
945 * @returns true/false
946 * @param pPage Pointer to the physical guest page tracking structure.
947 */
948#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
949 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951/**
952 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
953 * virtual handlers.
954 * @returns true/false
955 * @param pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
958 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
959
960
961/**
962 * Checks if the page has any access handlers, including temporarily disabled ones.
963 * @returns true/false
964 * @param pPage Pointer to the physical guest page tracking structure.
965 */
966#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
967# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
968 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
969#else
970# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
971 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
972 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
973#endif
974
975/**
976 * Checks if the page has any active access handlers.
977 * @returns true/false
978 * @param pPage Pointer to the physical guest page tracking structure.
979 */
980#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
981# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
982 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
983#else
984# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
985 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
986 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
987#endif
988
989/**
990 * Checks if the page has any active access handlers catching all accesses.
991 * @returns true/false
992 * @param pPage Pointer to the physical guest page tracking structure.
993 */
994#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
995# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
996 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
997 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
998#else
999# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1000 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1001 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1002#endif
1003
1004
1005/** @def PGM_PAGE_GET_TRACKING
1006 * Gets the packed shadow page pool tracking data associated with a guest page.
1007 * @returns uint16_t containing the data.
1008 * @param pPage Pointer to the physical guest page tracking structure.
1009 */
1010#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1011
1012/** @def PGM_PAGE_SET_TRACKING
1013 * Sets the packed shadow page pool tracking data associated with a guest page.
1014 * @param pPage Pointer to the physical guest page tracking structure.
1015 * @param u16TrackingData The tracking data to store.
1016 */
1017#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1018 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1019
1020/** @def PGM_PAGE_GET_TD_CREFS
1021 * Gets the @a cRefs tracking data member.
1022 * @returns cRefs.
1023 * @param pPage Pointer to the physical guest page tracking structure.
1024 */
1025#define PGM_PAGE_GET_TD_CREFS(pPage) \
1026 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1027
1028/** @def PGM_PAGE_GET_TD_IDX
1029 * Gets the @a idx tracking data member.
1030 * @returns idx.
1031 * @param pPage Pointer to the physical guest page tracking structure.
1032 */
1033#define PGM_PAGE_GET_TD_IDX(pPage) \
1034 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1035
1036
1037/** Max number of locks on a page. */
1038#define PGM_PAGE_MAX_LOCKS 254
1039
1040/** Get the read lock count.
1041 * @returns count.
1042 * @param pPage Pointer to the physical guest page tracking structure.
1043 */
1044#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1045
1046/** Get the write lock count.
1047 * @returns count.
1048 * @param pPage Pointer to the physical guest page tracking structure.
1049 */
1050#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1051
1052/** Decrement the read lock counter.
1053 * @param pPage Pointer to the physical guest page tracking structure.
1054 */
1055#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1056
1057/** Decrement the write lock counter.
1058 * @param pPage Pointer to the physical guest page tracking structure.
1059 */
1060#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1061
1062/** Increment the read lock counter.
1063 * @param pPage Pointer to the physical guest page tracking structure.
1064 */
1065#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1066
1067/** Increment the write lock counter.
1068 * @param pPage Pointer to the physical guest page tracking structure.
1069 */
1070#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1071
1072
1073
1074/**
1075 * Per page live save tracking data.
1076 */
1077typedef struct PGMLIVESAVEPAGE
1078{
1079 /** The pass number where this page was last saved. */
1080 uint32_t uPassSaved;
1081 /** Number of times it has been dirtied. */
1082 uint32_t cDirtied : 24;
1083 /** Whether it is currently dirty. */
1084 uint32_t fDirty : 1;
1085 /** Ignore the page.
1086 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1087 * deal with these after pausing the VM and DevPCI have said it bit about
1088 * remappings. */
1089 uint32_t fIgnore : 1;
1090 /** Was a ZERO page last time around. */
1091 uint32_t fZero : 1;
1092 /** Was a SHARED page last time around. */
1093 uint32_t fShared : 1;
1094 /** Whether the page is/was write monitored in a previous pass. */
1095 uint32_t fWriteMonitored : 1;
1096 /** Whether the page is/was write monitored earlier in this pass. */
1097 uint32_t fWriteMonitoredJustNow : 1;
1098 /** Bits reserved for future use. */
1099 uint32_t u2Reserved : 2;
1100} PGMLIVESAVEPAGE;
1101AssertCompileSize(PGMLIVESAVEPAGE, 8);
1102/** Pointer to the per page live save tracking data. */
1103typedef PGMLIVESAVEPAGE *PPGMLIVESAVEPAGE;
1104
1105/** The max value of PGMLIVESAVEPAGE::cDirtied. */
1106#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1107
1108
1109/**
1110 * Ram range for GC Phys to HC Phys conversion.
1111 *
1112 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1113 * conversions too, but we'll let MM handle that for now.
1114 *
1115 * This structure is used by linked lists in both GC and HC.
1116 */
1117typedef struct PGMRAMRANGE
1118{
1119 /** Start of the range. Page aligned. */
1120 RTGCPHYS GCPhys;
1121 /** Size of the range. (Page aligned of course). */
1122 RTGCPHYS cb;
1123 /** Pointer to the next RAM range - for R3. */
1124 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1125 /** Pointer to the next RAM range - for R0. */
1126 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1127 /** Pointer to the next RAM range - for RC. */
1128 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1129 /** PGM_RAM_RANGE_FLAGS_* flags. */
1130 uint32_t fFlags;
1131 /** Last address in the range (inclusive). Page aligned (-1). */
1132 RTGCPHYS GCPhysLast;
1133 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1134 R3PTRTYPE(void *) pvR3;
1135 /** Live save per page tracking data. */
1136 R3PTRTYPE(PPGMLIVESAVEPAGE) paLSPages;
1137 /** The range description. */
1138 R3PTRTYPE(const char *) pszDesc;
1139 /** Pointer to self - R0 pointer. */
1140 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1141 /** Pointer to self - RC pointer. */
1142 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1143 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1144 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1145 /** Array of physical guest page tracking structures. */
1146 PGMPAGE aPages[1];
1147} PGMRAMRANGE;
1148/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1149typedef PGMRAMRANGE *PPGMRAMRANGE;
1150
1151/** @name PGMRAMRANGE::fFlags
1152 * @{ */
1153/** The RAM range is floating around as an independent guest mapping. */
1154#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1155/** Ad hoc RAM range for an ROM mapping. */
1156#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1157/** Ad hoc RAM range for an MMIO mapping. */
1158#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1159/** Ad hoc RAM range for an MMIO2 mapping. */
1160#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1161/** @} */
1162
1163/** Tests if a RAM range is an ad hoc one or not.
1164 * @returns true/false.
1165 * @param pRam The RAM range.
1166 */
1167#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1168 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1169
1170
1171/**
1172 * Per page tracking structure for ROM image.
1173 *
1174 * A ROM image may have a shadow page, in which case we may have two pages
1175 * backing it. This structure contains the PGMPAGE for both while
1176 * PGMRAMRANGE have a copy of the active one. It is important that these
1177 * aren't out of sync in any regard other than page pool tracking data.
1178 */
1179typedef struct PGMROMPAGE
1180{
1181 /** The page structure for the virgin ROM page. */
1182 PGMPAGE Virgin;
1183 /** The page structure for the shadow RAM page. */
1184 PGMPAGE Shadow;
1185 /** The current protection setting. */
1186 PGMROMPROT enmProt;
1187 /** Live save status information. Makes use of unused alignment space. */
1188 struct
1189 {
1190 /** The previous protection value. */
1191 uint8_t u8Prot;
1192 /** Written to flag set by the handler. */
1193 bool fWrittenTo;
1194 /** Whether the shadow page is dirty or not. */
1195 bool fDirty;
1196 /** Whether it was dirtied in the recently. */
1197 bool fDirtiedRecently;
1198 } LiveSave;
1199} PGMROMPAGE;
1200AssertCompileSizeAlignment(PGMROMPAGE, 8);
1201/** Pointer to a ROM page tracking structure. */
1202typedef PGMROMPAGE *PPGMROMPAGE;
1203
1204
1205/**
1206 * A registered ROM image.
1207 *
1208 * This is needed to keep track of ROM image since they generally intrude
1209 * into a PGMRAMRANGE. It also keeps track of additional info like the
1210 * two page sets (read-only virgin and read-write shadow), the current
1211 * state of each page.
1212 *
1213 * Because access handlers cannot easily be executed in a different
1214 * context, the ROM ranges needs to be accessible and in all contexts.
1215 */
1216typedef struct PGMROMRANGE
1217{
1218 /** Pointer to the next range - R3. */
1219 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1220 /** Pointer to the next range - R0. */
1221 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1222 /** Pointer to the next range - RC. */
1223 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1224 /** Pointer alignment */
1225 RTRCPTR RCPtrAlignment;
1226 /** Address of the range. */
1227 RTGCPHYS GCPhys;
1228 /** Address of the last byte in the range. */
1229 RTGCPHYS GCPhysLast;
1230 /** Size of the range. */
1231 RTGCPHYS cb;
1232 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1233 uint32_t fFlags;
1234 /** The saved state range ID. */
1235 uint8_t idSavedState;
1236 /** Alignment padding. */
1237 uint8_t au8Alignment[3];
1238 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1239 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1240 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1241 * This is used for strictness checks. */
1242 R3PTRTYPE(const void *) pvOriginal;
1243 /** The ROM description. */
1244 R3PTRTYPE(const char *) pszDesc;
1245 /** The per page tracking structures. */
1246 PGMROMPAGE aPages[1];
1247} PGMROMRANGE;
1248/** Pointer to a ROM range. */
1249typedef PGMROMRANGE *PPGMROMRANGE;
1250
1251
1252/**
1253 * A registered MMIO2 (= Device RAM) range.
1254 *
1255 * There are a few reason why we need to keep track of these
1256 * registrations. One of them is the deregistration & cleanup stuff,
1257 * while another is that the PGMRAMRANGE associated with such a region may
1258 * have to be removed from the ram range list.
1259 *
1260 * Overlapping with a RAM range has to be 100% or none at all. The pages
1261 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1262 * will be raised if a partial overlap or an overlap of ROM pages is
1263 * encountered. On an overlap we will free all the existing RAM pages and
1264 * put in the ram range pages instead.
1265 */
1266typedef struct PGMMMIO2RANGE
1267{
1268 /** The owner of the range. (a device) */
1269 PPDMDEVINSR3 pDevInsR3;
1270 /** Pointer to the ring-3 mapping of the allocation. */
1271 RTR3PTR pvR3;
1272 /** Pointer to the next range - R3. */
1273 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1274 /** Whether it's mapped or not. */
1275 bool fMapped;
1276 /** Whether it's overlapping or not. */
1277 bool fOverlapping;
1278 /** The PCI region number.
1279 * @remarks This ASSUMES that nobody will ever really need to have multiple
1280 * PCI devices with matching MMIO region numbers on a single device. */
1281 uint8_t iRegion;
1282 /** The saved state range ID. */
1283 uint8_t idSavedState;
1284#if HC_ARCH_BITS != 32
1285 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1286 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 0 : 4];
1287#endif
1288 /** The associated RAM range. */
1289 PGMRAMRANGE RamRange;
1290} PGMMMIO2RANGE;
1291/** Pointer to a MMIO2 range. */
1292typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1293
1294
1295
1296
1297/**
1298 * PGMPhysRead/Write cache entry
1299 */
1300typedef struct PGMPHYSCACHEENTRY
1301{
1302 /** R3 pointer to physical page. */
1303 R3PTRTYPE(uint8_t *) pbR3;
1304 /** GC Physical address for cache entry */
1305 RTGCPHYS GCPhys;
1306#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1307 RTGCPHYS u32Padding0; /**< alignment padding. */
1308#endif
1309} PGMPHYSCACHEENTRY;
1310
1311/**
1312 * PGMPhysRead/Write cache to reduce REM memory access overhead
1313 */
1314typedef struct PGMPHYSCACHE
1315{
1316 /** Bitmap of valid cache entries */
1317 uint64_t aEntries;
1318 /** Cache entries */
1319 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1320} PGMPHYSCACHE;
1321
1322
1323/** Pointer to an allocation chunk ring-3 mapping. */
1324typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1325/** Pointer to an allocation chunk ring-3 mapping pointer. */
1326typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1327
1328/**
1329 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1330 *
1331 * The primary tree (Core) uses the chunk id as key.
1332 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1333 */
1334typedef struct PGMCHUNKR3MAP
1335{
1336 /** The key is the chunk id. */
1337 AVLU32NODECORE Core;
1338 /** The key is the ageing sequence number. */
1339 AVLLU32NODECORE AgeCore;
1340 /** The current age thingy. */
1341 uint32_t iAge;
1342 /** The current reference count. */
1343 uint32_t volatile cRefs;
1344 /** The current permanent reference count. */
1345 uint32_t volatile cPermRefs;
1346 /** The mapping address. */
1347 void *pv;
1348} PGMCHUNKR3MAP;
1349
1350/**
1351 * Allocation chunk ring-3 mapping TLB entry.
1352 */
1353typedef struct PGMCHUNKR3MAPTLBE
1354{
1355 /** The chunk id. */
1356 uint32_t volatile idChunk;
1357#if HC_ARCH_BITS == 64
1358 uint32_t u32Padding; /**< alignment padding. */
1359#endif
1360 /** The chunk map. */
1361#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1362 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1363#else
1364 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1365#endif
1366} PGMCHUNKR3MAPTLBE;
1367/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1368typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1369
1370/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1371 * @remark Must be a power of two value. */
1372#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1373
1374/**
1375 * Allocation chunk ring-3 mapping TLB.
1376 *
1377 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1378 * At first glance this might look kinda odd since AVL trees are
1379 * supposed to give the most optimial lookup times of all trees
1380 * due to their balancing. However, take a tree with 1023 nodes
1381 * in it, that's 10 levels, meaning that most searches has to go
1382 * down 9 levels before they find what they want. This isn't fast
1383 * compared to a TLB hit. There is the factor of cache misses,
1384 * and of course the problem with trees and branch prediction.
1385 * This is why we use TLBs in front of most of the trees.
1386 *
1387 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1388 * difficult when we switch to the new inlined AVL trees (from kStuff).
1389 */
1390typedef struct PGMCHUNKR3MAPTLB
1391{
1392 /** The TLB entries. */
1393 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1394} PGMCHUNKR3MAPTLB;
1395
1396/**
1397 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1398 * @returns Chunk TLB index.
1399 * @param idChunk The Chunk ID.
1400 */
1401#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1402
1403
1404/**
1405 * Ring-3 guest page mapping TLB entry.
1406 * @remarks used in ring-0 as well at the moment.
1407 */
1408typedef struct PGMPAGER3MAPTLBE
1409{
1410 /** Address of the page. */
1411 RTGCPHYS volatile GCPhys;
1412 /** The guest page. */
1413#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1414 R3PTRTYPE(PPGMPAGE) volatile pPage;
1415#else
1416 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1417#endif
1418 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1419#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1420 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1421#else
1422 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1423#endif
1424 /** The address */
1425#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1426 R3PTRTYPE(void *) volatile pv;
1427#else
1428 R3R0PTRTYPE(void *) volatile pv;
1429#endif
1430#if HC_ARCH_BITS == 32
1431 uint32_t u32Padding; /**< alignment padding. */
1432#endif
1433} PGMPAGER3MAPTLBE;
1434/** Pointer to an entry in the HC physical TLB. */
1435typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1436
1437
1438/** The number of entries in the ring-3 guest page mapping TLB.
1439 * @remarks The value must be a power of two. */
1440#define PGM_PAGER3MAPTLB_ENTRIES 64
1441
1442/**
1443 * Ring-3 guest page mapping TLB.
1444 * @remarks used in ring-0 as well at the moment.
1445 */
1446typedef struct PGMPAGER3MAPTLB
1447{
1448 /** The TLB entries. */
1449 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1450} PGMPAGER3MAPTLB;
1451/** Pointer to the ring-3 guest page mapping TLB. */
1452typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1453
1454/**
1455 * Calculates the index of the TLB entry for the specified guest page.
1456 * @returns Physical TLB index.
1457 * @param GCPhys The guest physical address.
1458 */
1459#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1460
1461
1462/**
1463 * Mapping cache usage set entry.
1464 *
1465 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1466 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1467 * cache. If it's extended to include ring-3, well, then something will
1468 * have be changed here...
1469 */
1470typedef struct PGMMAPSETENTRY
1471{
1472 /** The mapping cache index. */
1473 uint16_t iPage;
1474 /** The number of references.
1475 * The max is UINT16_MAX - 1. */
1476 uint16_t cRefs;
1477#if HC_ARCH_BITS == 64
1478 uint32_t alignment;
1479#endif
1480 /** Pointer to the page. */
1481 RTR0PTR pvPage;
1482 /** The physical address for this entry. */
1483 RTHCPHYS HCPhys;
1484} PGMMAPSETENTRY;
1485/** Pointer to a mapping cache usage set entry. */
1486typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1487
1488/**
1489 * Mapping cache usage set.
1490 *
1491 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1492 * done during exits / traps. The set is
1493 */
1494typedef struct PGMMAPSET
1495{
1496 /** The number of occupied entries.
1497 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1498 * dynamic mappings. */
1499 uint32_t cEntries;
1500 /** The start of the current subset.
1501 * This is UINT32_MAX if no subset is currently open. */
1502 uint32_t iSubset;
1503 /** The index of the current CPU, only valid if the set is open. */
1504 int32_t iCpu;
1505#if HC_ARCH_BITS == 64
1506 uint32_t alignment;
1507#endif
1508 /** The entries. */
1509 PGMMAPSETENTRY aEntries[64];
1510 /** HCPhys -> iEntry fast lookup table.
1511 * Use PGMMAPSET_HASH for hashing.
1512 * The entries may or may not be valid, check against cEntries. */
1513 uint8_t aiHashTable[128];
1514} PGMMAPSET;
1515/** Pointer to the mapping cache set. */
1516typedef PGMMAPSET *PPGMMAPSET;
1517
1518/** PGMMAPSET::cEntries value for a closed set. */
1519#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1520
1521/** Hash function for aiHashTable. */
1522#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1523
1524/** The max fill size (strict builds). */
1525#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1526
1527
1528/** @name Context neutrual page mapper TLB.
1529 *
1530 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1531 * code is writting in a kind of context neutrual way. Time will show whether
1532 * this actually makes sense or not...
1533 *
1534 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1535 * context ends up using a global mapping cache on some platforms
1536 * (darwin).
1537 *
1538 * @{ */
1539/** @typedef PPGMPAGEMAPTLB
1540 * The page mapper TLB pointer type for the current context. */
1541/** @typedef PPGMPAGEMAPTLB
1542 * The page mapper TLB entry pointer type for the current context. */
1543/** @typedef PPGMPAGEMAPTLB
1544 * The page mapper TLB entry pointer pointer type for the current context. */
1545/** @def PGM_PAGEMAPTLB_ENTRIES
1546 * The number of TLB entries in the page mapper TLB for the current context. */
1547/** @def PGM_PAGEMAPTLB_IDX
1548 * Calculate the TLB index for a guest physical address.
1549 * @returns The TLB index.
1550 * @param GCPhys The guest physical address. */
1551/** @typedef PPGMPAGEMAP
1552 * Pointer to a page mapper unit for current context. */
1553/** @typedef PPPGMPAGEMAP
1554 * Pointer to a page mapper unit pointer for current context. */
1555#ifdef IN_RC
1556// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1557// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1558// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1559# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1560# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1561 typedef void * PPGMPAGEMAP;
1562 typedef void ** PPPGMPAGEMAP;
1563//#elif IN_RING0
1564// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1565// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1566// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1567//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1568//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1569// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1570// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1571#else
1572 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1573 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1574 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1575# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1576# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1577 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1578 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1579#endif
1580/** @} */
1581
1582
1583/** @name PGM Pool Indexes.
1584 * Aka. the unique shadow page identifier.
1585 * @{ */
1586/** NIL page pool IDX. */
1587#define NIL_PGMPOOL_IDX 0
1588/** The first normal index. */
1589#define PGMPOOL_IDX_FIRST_SPECIAL 1
1590/** Page directory (32-bit root). */
1591#define PGMPOOL_IDX_PD 1
1592/** Page Directory Pointer Table (PAE root). */
1593#define PGMPOOL_IDX_PDPT 2
1594/** AMD64 CR3 level index.*/
1595#define PGMPOOL_IDX_AMD64_CR3 3
1596/** Nested paging root.*/
1597#define PGMPOOL_IDX_NESTED_ROOT 4
1598/** The first normal index. */
1599#define PGMPOOL_IDX_FIRST 5
1600/** The last valid index. (inclusive, 14 bits) */
1601#define PGMPOOL_IDX_LAST 0x3fff
1602/** @} */
1603
1604/** The NIL index for the parent chain. */
1605#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1606#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1607
1608/**
1609 * Node in the chain linking a shadowed page to it's parent (user).
1610 */
1611#pragma pack(1)
1612typedef struct PGMPOOLUSER
1613{
1614 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1615 uint16_t iNext;
1616 /** The user page index. */
1617 uint16_t iUser;
1618 /** Index into the user table. */
1619 uint32_t iUserTable;
1620} PGMPOOLUSER, *PPGMPOOLUSER;
1621typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1622#pragma pack()
1623
1624
1625/** The NIL index for the phys ext chain. */
1626#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1627
1628/**
1629 * Node in the chain of physical cross reference extents.
1630 * @todo Calling this an 'extent' is not quite right, find a better name.
1631 */
1632#pragma pack(1)
1633typedef struct PGMPOOLPHYSEXT
1634{
1635 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1636 uint16_t iNext;
1637 /** The user page index. */
1638 uint16_t aidx[3];
1639} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1640typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1641#pragma pack()
1642
1643
1644/**
1645 * The kind of page that's being shadowed.
1646 */
1647typedef enum PGMPOOLKIND
1648{
1649 /** The virtual invalid 0 entry. */
1650 PGMPOOLKIND_INVALID = 0,
1651 /** The entry is free (=unused). */
1652 PGMPOOLKIND_FREE,
1653
1654 /** Shw: 32-bit page table; Gst: no paging */
1655 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1656 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1657 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1658 /** Shw: 32-bit page table; Gst: 4MB page. */
1659 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1660 /** Shw: PAE page table; Gst: no paging */
1661 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1662 /** Shw: PAE page table; Gst: 32-bit page table. */
1663 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1664 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1665 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1666 /** Shw: PAE page table; Gst: PAE page table. */
1667 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1668 /** Shw: PAE page table; Gst: 2MB page. */
1669 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1670
1671 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1672 PGMPOOLKIND_32BIT_PD,
1673 /** Shw: 32-bit page directory. Gst: no paging. */
1674 PGMPOOLKIND_32BIT_PD_PHYS,
1675 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1676 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1677 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1678 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1679 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1680 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1681 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1682 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1683 /** Shw: PAE page directory; Gst: PAE page directory. */
1684 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1685 /** Shw: PAE page directory; Gst: no paging. */
1686 PGMPOOLKIND_PAE_PD_PHYS,
1687
1688 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1689 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1690 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1691 PGMPOOLKIND_PAE_PDPT,
1692 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1693 PGMPOOLKIND_PAE_PDPT_PHYS,
1694
1695 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1696 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1697 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1698 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1699 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1700 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1701 /** Shw: 64-bit page directory table; Gst: no paging */
1702 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1703
1704 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1705 PGMPOOLKIND_64BIT_PML4,
1706
1707 /** Shw: EPT page directory pointer table; Gst: no paging */
1708 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1709 /** Shw: EPT page directory table; Gst: no paging */
1710 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1711 /** Shw: EPT page table; Gst: no paging */
1712 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1713
1714 /** Shw: Root Nested paging table. */
1715 PGMPOOLKIND_ROOT_NESTED,
1716
1717 /** The last valid entry. */
1718 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1719} PGMPOOLKIND;
1720
1721/**
1722 * The access attributes of the page; only applies to big pages.
1723 */
1724typedef enum
1725{
1726 PGMPOOLACCESS_DONTCARE = 0,
1727 PGMPOOLACCESS_USER_RW,
1728 PGMPOOLACCESS_USER_R,
1729 PGMPOOLACCESS_USER_RW_NX,
1730 PGMPOOLACCESS_USER_R_NX,
1731 PGMPOOLACCESS_SUPERVISOR_RW,
1732 PGMPOOLACCESS_SUPERVISOR_R,
1733 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1734 PGMPOOLACCESS_SUPERVISOR_R_NX
1735} PGMPOOLACCESS;
1736
1737/**
1738 * The tracking data for a page in the pool.
1739 */
1740typedef struct PGMPOOLPAGE
1741{
1742 /** AVL node code with the (R3) physical address of this page. */
1743 AVLOHCPHYSNODECORE Core;
1744 /** Pointer to the R3 mapping of the page. */
1745#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1746 R3PTRTYPE(void *) pvPageR3;
1747#else
1748 R3R0PTRTYPE(void *) pvPageR3;
1749#endif
1750 /** The guest physical address. */
1751#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1752 uint32_t Alignment0;
1753#endif
1754 RTGCPHYS GCPhys;
1755
1756 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1757 RTGCPTR pvLastAccessHandlerRip;
1758 RTGCPTR pvLastAccessHandlerFault;
1759 uint64_t cLastAccessHandlerCount;
1760
1761 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1762 uint8_t enmKind;
1763 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1764 uint8_t enmAccess;
1765 /** The index of this page. */
1766 uint16_t idx;
1767 /** The next entry in the list this page currently resides in.
1768 * It's either in the free list or in the GCPhys hash. */
1769 uint16_t iNext;
1770#ifdef PGMPOOL_WITH_USER_TRACKING
1771 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1772 uint16_t iUserHead;
1773 /** The number of present entries. */
1774 uint16_t cPresent;
1775 /** The first entry in the table which is present. */
1776 uint16_t iFirstPresent;
1777#endif
1778#ifdef PGMPOOL_WITH_MONITORING
1779 /** The number of modifications to the monitored page. */
1780 uint16_t cModifications;
1781 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1782 uint16_t iModifiedNext;
1783 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1784 uint16_t iModifiedPrev;
1785 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1786 uint16_t iMonitoredNext;
1787 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1788 uint16_t iMonitoredPrev;
1789#endif
1790#ifdef PGMPOOL_WITH_CACHE
1791 /** The next page in the age list. */
1792 uint16_t iAgeNext;
1793 /** The previous page in the age list. */
1794 uint16_t iAgePrev;
1795#endif /* PGMPOOL_WITH_CACHE */
1796 /** Used to indicate that the page is zeroed. */
1797 bool fZeroed;
1798 /** Used to indicate that a PT has non-global entries. */
1799 bool fSeenNonGlobal;
1800 /** Used to indicate that we're monitoring writes to the guest page. */
1801 bool fMonitored;
1802 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1803 * (All pages are in the age list.) */
1804 bool fCached;
1805 /** This is used by the R3 access handlers when invoked by an async thread.
1806 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1807 bool volatile fReusedFlushPending;
1808 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1809 bool fDirty;
1810
1811 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1812 uint32_t cLocked;
1813 uint32_t idxDirty;
1814 RTGCPTR pvDirtyFault;
1815} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1816/** Pointer to a const pool page. */
1817typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1818
1819
1820#ifdef PGMPOOL_WITH_CACHE
1821/** The hash table size. */
1822# define PGMPOOL_HASH_SIZE 0x40
1823/** The hash function. */
1824# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1825#endif
1826
1827
1828/**
1829 * The shadow page pool instance data.
1830 *
1831 * It's all one big allocation made at init time, except for the
1832 * pages that is. The user nodes follows immediatly after the
1833 * page structures.
1834 */
1835typedef struct PGMPOOL
1836{
1837 /** The VM handle - R3 Ptr. */
1838 PVMR3 pVMR3;
1839 /** The VM handle - R0 Ptr. */
1840 PVMR0 pVMR0;
1841 /** The VM handle - RC Ptr. */
1842 PVMRC pVMRC;
1843 /** The max pool size. This includes the special IDs. */
1844 uint16_t cMaxPages;
1845 /** The current pool size. */
1846 uint16_t cCurPages;
1847 /** The head of the free page list. */
1848 uint16_t iFreeHead;
1849 /* Padding. */
1850 uint16_t u16Padding;
1851#ifdef PGMPOOL_WITH_USER_TRACKING
1852 /** Head of the chain of free user nodes. */
1853 uint16_t iUserFreeHead;
1854 /** The number of user nodes we've allocated. */
1855 uint16_t cMaxUsers;
1856 /** The number of present page table entries in the entire pool. */
1857 uint32_t cPresent;
1858 /** Pointer to the array of user nodes - RC pointer. */
1859 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1860 /** Pointer to the array of user nodes - R3 pointer. */
1861 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1862 /** Pointer to the array of user nodes - R0 pointer. */
1863 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1864#endif /* PGMPOOL_WITH_USER_TRACKING */
1865#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1866 /** Head of the chain of free phys ext nodes. */
1867 uint16_t iPhysExtFreeHead;
1868 /** The number of user nodes we've allocated. */
1869 uint16_t cMaxPhysExts;
1870 /** Pointer to the array of physical xref extent - RC pointer. */
1871 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1872 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1873 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1874 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1875 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1876#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1877#ifdef PGMPOOL_WITH_CACHE
1878 /** Hash table for GCPhys addresses. */
1879 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1880 /** The head of the age list. */
1881 uint16_t iAgeHead;
1882 /** The tail of the age list. */
1883 uint16_t iAgeTail;
1884 /** Set if the cache is enabled. */
1885 bool fCacheEnabled;
1886 /** Alignment padding. */
1887 bool afPadding1[3];
1888#endif /* PGMPOOL_WITH_CACHE */
1889#ifdef PGMPOOL_WITH_MONITORING
1890 /** Head of the list of modified pages. */
1891 uint16_t iModifiedHead;
1892 /** The current number of modified pages. */
1893 uint16_t cModifiedPages;
1894 /** Access handler, RC. */
1895 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1896 /** Access handler, R0. */
1897 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1898 /** Access handler, R3. */
1899 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1900 /** The access handler description (R3 ptr). */
1901 R3PTRTYPE(const char *) pszAccessHandler;
1902# if HC_ARCH_BITS == 32
1903 /** Alignment padding. */
1904 uint32_t u32Padding2;
1905# endif
1906 /* Next available slot. */
1907 uint32_t idxFreeDirtyPage;
1908 /* Number of active dirty pages. */
1909 uint32_t cDirtyPages;
1910 /* Array of current dirty pgm pool page indices. */
1911 uint16_t aIdxDirtyPages[16];
1912 uint64_t aDirtyPages[16][512];
1913#endif /* PGMPOOL_WITH_MONITORING */
1914 /** The number of pages currently in use. */
1915 uint16_t cUsedPages;
1916#ifdef VBOX_WITH_STATISTICS
1917 /** The high water mark for cUsedPages. */
1918 uint16_t cUsedPagesHigh;
1919 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1920 /** Profiling pgmPoolAlloc(). */
1921 STAMPROFILEADV StatAlloc;
1922 /** Profiling pgmR3PoolClearDoIt(). */
1923 STAMPROFILE StatClearAll;
1924 /** Profiling pgmR3PoolReset(). */
1925 STAMPROFILE StatR3Reset;
1926 /** Profiling pgmPoolFlushPage(). */
1927 STAMPROFILE StatFlushPage;
1928 /** Profiling pgmPoolFree(). */
1929 STAMPROFILE StatFree;
1930 /** Counting explicit flushes by PGMPoolFlushPage(). */
1931 STAMCOUNTER StatForceFlushPage;
1932 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1933 STAMCOUNTER StatForceFlushDirtyPage;
1934 /** Counting flushes for reused pages. */
1935 STAMCOUNTER StatForceFlushReused;
1936 /** Profiling time spent zeroing pages. */
1937 STAMPROFILE StatZeroPage;
1938# ifdef PGMPOOL_WITH_USER_TRACKING
1939 /** Profiling of pgmPoolTrackDeref. */
1940 STAMPROFILE StatTrackDeref;
1941 /** Profiling pgmTrackFlushGCPhysPT. */
1942 STAMPROFILE StatTrackFlushGCPhysPT;
1943 /** Profiling pgmTrackFlushGCPhysPTs. */
1944 STAMPROFILE StatTrackFlushGCPhysPTs;
1945 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1946 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1947 /** Number of times we've been out of user records. */
1948 STAMCOUNTER StatTrackFreeUpOneUser;
1949 /** Nr of flushed entries. */
1950 STAMCOUNTER StatTrackFlushEntry;
1951 /** Nr of updated entries. */
1952 STAMCOUNTER StatTrackFlushEntryKeep;
1953# endif
1954# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1955 /** Profiling deref activity related tracking GC physical pages. */
1956 STAMPROFILE StatTrackDerefGCPhys;
1957 /** Number of linear searches for a HCPhys in the ram ranges. */
1958 STAMCOUNTER StatTrackLinearRamSearches;
1959 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1960 STAMCOUNTER StamTrackPhysExtAllocFailures;
1961# endif
1962# ifdef PGMPOOL_WITH_MONITORING
1963 /** Profiling the RC/R0 access handler. */
1964 STAMPROFILE StatMonitorRZ;
1965 /** Times we've failed interpreting the instruction. */
1966 STAMCOUNTER StatMonitorRZEmulateInstr;
1967 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1968 STAMPROFILE StatMonitorRZFlushPage;
1969 /* Times we've detected a page table reinit. */
1970 STAMCOUNTER StatMonitorRZFlushReinit;
1971 /** Counting flushes for pages that are modified too often. */
1972 STAMCOUNTER StatMonitorRZFlushModOverflow;
1973 /** Times we've detected fork(). */
1974 STAMCOUNTER StatMonitorRZFork;
1975 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1976 STAMPROFILE StatMonitorRZHandled;
1977 /** Times we've failed interpreting a patch code instruction. */
1978 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1979 /** Times we've failed interpreting a patch code instruction during flushing. */
1980 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1981 /** The number of times we've seen rep prefixes we can't handle. */
1982 STAMCOUNTER StatMonitorRZRepPrefix;
1983 /** Profiling the REP STOSD cases we've handled. */
1984 STAMPROFILE StatMonitorRZRepStosd;
1985 /** Nr of handled PT faults. */
1986 STAMCOUNTER StatMonitorRZFaultPT;
1987 /** Nr of handled PD faults. */
1988 STAMCOUNTER StatMonitorRZFaultPD;
1989 /** Nr of handled PDPT faults. */
1990 STAMCOUNTER StatMonitorRZFaultPDPT;
1991 /** Nr of handled PML4 faults. */
1992 STAMCOUNTER StatMonitorRZFaultPML4;
1993
1994 /** Profiling the R3 access handler. */
1995 STAMPROFILE StatMonitorR3;
1996 /** Times we've failed interpreting the instruction. */
1997 STAMCOUNTER StatMonitorR3EmulateInstr;
1998 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1999 STAMPROFILE StatMonitorR3FlushPage;
2000 /* Times we've detected a page table reinit. */
2001 STAMCOUNTER StatMonitorR3FlushReinit;
2002 /** Counting flushes for pages that are modified too often. */
2003 STAMCOUNTER StatMonitorR3FlushModOverflow;
2004 /** Times we've detected fork(). */
2005 STAMCOUNTER StatMonitorR3Fork;
2006 /** Profiling the R3 access we've handled (except REP STOSD). */
2007 STAMPROFILE StatMonitorR3Handled;
2008 /** The number of times we've seen rep prefixes we can't handle. */
2009 STAMCOUNTER StatMonitorR3RepPrefix;
2010 /** Profiling the REP STOSD cases we've handled. */
2011 STAMPROFILE StatMonitorR3RepStosd;
2012 /** Nr of handled PT faults. */
2013 STAMCOUNTER StatMonitorR3FaultPT;
2014 /** Nr of handled PD faults. */
2015 STAMCOUNTER StatMonitorR3FaultPD;
2016 /** Nr of handled PDPT faults. */
2017 STAMCOUNTER StatMonitorR3FaultPDPT;
2018 /** Nr of handled PML4 faults. */
2019 STAMCOUNTER StatMonitorR3FaultPML4;
2020 /** The number of times we're called in an async thread an need to flush. */
2021 STAMCOUNTER StatMonitorR3Async;
2022 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2023 STAMCOUNTER StatResetDirtyPages;
2024 /** Times we've called pgmPoolAddDirtyPage. */
2025 STAMCOUNTER StatDirtyPage;
2026 /** Times we've had to flush duplicates for dirty page management. */
2027 STAMCOUNTER StatDirtyPageDupFlush;
2028 /** Times we've had to flush because of overflow. */
2029 STAMCOUNTER StatDirtyPageOverFlowFlush;
2030
2031 /** The high wather mark for cModifiedPages. */
2032 uint16_t cModifiedPagesHigh;
2033 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2034# endif
2035# ifdef PGMPOOL_WITH_CACHE
2036 /** The number of cache hits. */
2037 STAMCOUNTER StatCacheHits;
2038 /** The number of cache misses. */
2039 STAMCOUNTER StatCacheMisses;
2040 /** The number of times we've got a conflict of 'kind' in the cache. */
2041 STAMCOUNTER StatCacheKindMismatches;
2042 /** Number of times we've been out of pages. */
2043 STAMCOUNTER StatCacheFreeUpOne;
2044 /** The number of cacheable allocations. */
2045 STAMCOUNTER StatCacheCacheable;
2046 /** The number of uncacheable allocations. */
2047 STAMCOUNTER StatCacheUncacheable;
2048# endif
2049#else
2050 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2051#endif
2052 /** The AVL tree for looking up a page by its HC physical address. */
2053 AVLOHCPHYSTREE HCPhysTree;
2054 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2055 /** Array of pages. (cMaxPages in length)
2056 * The Id is the index into thist array.
2057 */
2058 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2059} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2060#ifdef PGMPOOL_WITH_MONITORING
2061AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2062AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2063#endif
2064AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2065#ifdef VBOX_WITH_STATISTICS
2066AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2067#endif
2068AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2069
2070
2071/** @def PGMPOOL_PAGE_2_PTR
2072 * Maps a pool page pool into the current context.
2073 *
2074 * @returns VBox status code.
2075 * @param pVM The VM handle.
2076 * @param pPage The pool page.
2077 *
2078 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2079 * small page window employeed by that function. Be careful.
2080 * @remark There is no need to assert on the result.
2081 */
2082#if defined(IN_RC)
2083# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2084#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2085# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2086#elif defined(VBOX_STRICT)
2087# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2088DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2089{
2090 Assert(pPage && pPage->pvPageR3);
2091 return pPage->pvPageR3;
2092}
2093#else
2094# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2095#endif
2096
2097/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2098 * Maps a pool page pool into the current context.
2099 *
2100 * @returns VBox status code.
2101 * @param pPGM Pointer to the PGM instance data.
2102 * @param pPage The pool page.
2103 *
2104 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2105 * small page window employeed by that function. Be careful.
2106 * @remark There is no need to assert on the result.
2107 */
2108#if defined(IN_RC)
2109# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2110#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2111# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2112#else
2113# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2114#endif
2115
2116/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2117 * Maps a pool page pool into the current context.
2118 *
2119 * @returns VBox status code.
2120 * @param pPGM Pointer to the PGMCPU instance data.
2121 * @param pPage The pool page.
2122 *
2123 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2124 * small page window employeed by that function. Be careful.
2125 * @remark There is no need to assert on the result.
2126 */
2127#if defined(IN_RC)
2128# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2129#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2130# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2131#else
2132# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2133#endif
2134
2135
2136/** @name Per guest page tracking data.
2137 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2138 * is to use more bits for it and split it up later on. But for now we'll play
2139 * safe and change as little as possible.
2140 *
2141 * The 16-bit word has two parts:
2142 *
2143 * The first 14-bit forms the @a idx field. It is either the index of a page in
2144 * the shadow page pool, or and index into the extent list.
2145 *
2146 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2147 * shadow page pool references to the page. If cRefs equals
2148 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2149 * (misnomer) table and not the shadow page pool.
2150 *
2151 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2152 * the 16-bit word.
2153 *
2154 * @{ */
2155/** The shift count for getting to the cRefs part. */
2156#define PGMPOOL_TD_CREFS_SHIFT 14
2157/** The mask applied after shifting the tracking data down by
2158 * PGMPOOL_TD_CREFS_SHIFT. */
2159#define PGMPOOL_TD_CREFS_MASK 0x3
2160/** The cRef value used to indiciate that the idx is the head of a
2161 * physical cross reference list. */
2162#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2163/** The shift used to get idx. */
2164#define PGMPOOL_TD_IDX_SHIFT 0
2165/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2166#define PGMPOOL_TD_IDX_MASK 0x3fff
2167/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2168 * simply too many mappings of this page. */
2169#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2170
2171/** @def PGMPOOL_TD_MAKE
2172 * Makes a 16-bit tracking data word.
2173 *
2174 * @returns tracking data.
2175 * @param cRefs The @a cRefs field. Must be within bounds!
2176 * @param idx The @a idx field. Must also be within bounds! */
2177#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2178
2179/** @def PGMPOOL_TD_GET_CREFS
2180 * Get the @a cRefs field from a tracking data word.
2181 *
2182 * @returns The @a cRefs field
2183 * @param u16 The tracking data word. */
2184#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2185
2186/** @def PGMPOOL_TD_GET_IDX
2187 * Get the @a idx field from a tracking data word.
2188 *
2189 * @returns The @a idx field
2190 * @param u16 The tracking data word. */
2191#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2192/** @} */
2193
2194
2195/**
2196 * Trees are using self relative offsets as pointers.
2197 * So, all its data, including the root pointer, must be in the heap for HC and GC
2198 * to have the same layout.
2199 */
2200typedef struct PGMTREES
2201{
2202 /** Physical access handlers (AVL range+offsetptr tree). */
2203 AVLROGCPHYSTREE PhysHandlers;
2204 /** Virtual access handlers (AVL range + GC ptr tree). */
2205 AVLROGCPTRTREE VirtHandlers;
2206 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2207 AVLROGCPHYSTREE PhysToVirtHandlers;
2208 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2209 AVLROGCPTRTREE HyperVirtHandlers;
2210} PGMTREES;
2211/** Pointer to PGM trees. */
2212typedef PGMTREES *PPGMTREES;
2213
2214
2215/** @name Paging mode macros
2216 * @{ */
2217#ifdef IN_RC
2218# define PGM_CTX(a,b) a##RC##b
2219# define PGM_CTX_STR(a,b) a "GC" b
2220# define PGM_CTX_DECL(type) VMMRCDECL(type)
2221#else
2222# ifdef IN_RING3
2223# define PGM_CTX(a,b) a##R3##b
2224# define PGM_CTX_STR(a,b) a "R3" b
2225# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2226# else
2227# define PGM_CTX(a,b) a##R0##b
2228# define PGM_CTX_STR(a,b) a "R0" b
2229# define PGM_CTX_DECL(type) VMMDECL(type)
2230# endif
2231#endif
2232
2233#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2234#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2235#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2236#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2237#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2238#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2239#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2240#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2241#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2242#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2243#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2244#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2245#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2246#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2247#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2248#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2249#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2250
2251#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2252#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2253#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2254#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2255#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2256#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2257#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2258#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2259#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2260#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2261#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2262#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2263#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2264#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2265#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2266#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2267#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2268
2269/* Shw_Gst */
2270#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2271#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2272#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2273#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2274#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2275#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2276#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2277#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2278#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2279#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2280#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2281#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2282#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2283#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2284#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2285#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2286#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2287#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2288#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2289
2290#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2291#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2292#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2293#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2294#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2295#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2296#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2297#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2298#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2299#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2300#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2301#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2302#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2303#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2304#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2305#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2306#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2307#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2308#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2309#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2310#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2311#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2312#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2313#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2314#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2315#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2316#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2317#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2318#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2319#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2320#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2321#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2322#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2323#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2324#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2325#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2326#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2327
2328#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2329#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2330/** @} */
2331
2332/**
2333 * Data for each paging mode.
2334 */
2335typedef struct PGMMODEDATA
2336{
2337 /** The guest mode type. */
2338 uint32_t uGstType;
2339 /** The shadow mode type. */
2340 uint32_t uShwType;
2341
2342 /** @name Function pointers for Shadow paging.
2343 * @{
2344 */
2345 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2346 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2347 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2348 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2349
2350 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2351 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2352
2353 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2354 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2355 /** @} */
2356
2357 /** @name Function pointers for Guest paging.
2358 * @{
2359 */
2360 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2361 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2362 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2363 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2364 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2365 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2366 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2367 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2368 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2369 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2370 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2371 /** @} */
2372
2373 /** @name Function pointers for Both Shadow and Guest paging.
2374 * @{
2375 */
2376 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2377 /* no pfnR3BthTrap0eHandler */
2378 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2379 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2380 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2381 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2382 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2383#ifdef VBOX_STRICT
2384 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2385#endif
2386 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2387 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2388
2389 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2390 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2391 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2392 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2393 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2394 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2395#ifdef VBOX_STRICT
2396 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2397#endif
2398 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2399 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2400
2401 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2402 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2403 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2404 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2405 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2406 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2407#ifdef VBOX_STRICT
2408 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2409#endif
2410 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2411 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2412 /** @} */
2413} PGMMODEDATA, *PPGMMODEDATA;
2414
2415
2416
2417/**
2418 * Converts a PGM pointer into a VM pointer.
2419 * @returns Pointer to the VM structure the PGM is part of.
2420 * @param pPGM Pointer to PGM instance data.
2421 */
2422#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2423
2424/**
2425 * PGM Data (part of VM)
2426 */
2427typedef struct PGM
2428{
2429 /** Offset to the VM structure. */
2430 RTINT offVM;
2431 /** Offset of the PGMCPU structure relative to VMCPU. */
2432 RTINT offVCpuPGM;
2433
2434 /** @cfgm{RamPreAlloc, boolean, false}
2435 * Indicates whether the base RAM should all be allocated before starting
2436 * the VM (default), or if it should be allocated when first written to.
2437 */
2438 bool fRamPreAlloc;
2439 /** Indicates whether write monitoring is currently in use.
2440 * This is used to prevent conflicts between live saving and page sharing
2441 * detection. */
2442 bool fPhysWriteMonitoringEngaged;
2443 /** Alignment padding. */
2444 bool afAlignment0[2];
2445
2446 /*
2447 * This will be redefined at least two more times before we're done, I'm sure.
2448 * The current code is only to get on with the coding.
2449 * - 2004-06-10: initial version, bird.
2450 * - 2004-07-02: 1st time, bird.
2451 * - 2004-10-18: 2nd time, bird.
2452 * - 2005-07-xx: 3rd time, bird.
2453 */
2454
2455 /** The host paging mode. (This is what SUPLib reports.) */
2456 SUPPAGINGMODE enmHostMode;
2457
2458 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2459 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2460 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2461 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2462
2463 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2464 RTGCPHYS GCPhys4MBPSEMask;
2465
2466 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2467 * This is sorted by physical address and contains no overlapping ranges. */
2468 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2469 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2470 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2471 /** RC pointer corresponding to PGM::pRamRangesR3. */
2472 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2473 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2474 * range is linked or unlinked. */
2475 uint32_t volatile idRamRangesGen;
2476
2477 /** Pointer to the list of ROM ranges - for R3.
2478 * This is sorted by physical address and contains no overlapping ranges. */
2479 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2480 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2481 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2482 /** RC pointer corresponding to PGM::pRomRangesR3. */
2483 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2484#if HC_ARCH_BITS == 64
2485 /** Alignment padding. */
2486 RTRCPTR GCPtrPadding2;
2487#endif
2488
2489 /** Pointer to the list of MMIO2 ranges - for R3.
2490 * Registration order. */
2491 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2492
2493 /** PGM offset based trees - R3 Ptr. */
2494 R3PTRTYPE(PPGMTREES) pTreesR3;
2495 /** PGM offset based trees - R0 Ptr. */
2496 R0PTRTYPE(PPGMTREES) pTreesR0;
2497 /** PGM offset based trees - RC Ptr. */
2498 RCPTRTYPE(PPGMTREES) pTreesRC;
2499
2500 /** Linked list of GC mappings - for RC.
2501 * The list is sorted ascending on address.
2502 */
2503 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2504 /** Linked list of GC mappings - for HC.
2505 * The list is sorted ascending on address.
2506 */
2507 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2508 /** Linked list of GC mappings - for R0.
2509 * The list is sorted ascending on address.
2510 */
2511 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2512
2513 /** Pointer to the 5 page CR3 content mapping.
2514 * The first page is always the CR3 (in some form) while the 4 other pages
2515 * are used of the PDs in PAE mode. */
2516 RTGCPTR GCPtrCR3Mapping;
2517#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2518 uint32_t u32Alignment1;
2519#endif
2520
2521 /** Indicates that PGMR3FinalizeMappings has been called and that further
2522 * PGMR3MapIntermediate calls will be rejected. */
2523 bool fFinalizedMappings;
2524 /** If set no conflict checks are required. (boolean) */
2525 bool fMappingsFixed;
2526 /** If set, then no mappings are put into the shadow page table. (boolean) */
2527 bool fDisableMappings;
2528 /** Size of fixed mapping */
2529 uint32_t cbMappingFixed;
2530 /** Base address (GC) of fixed mapping */
2531 RTGCPTR GCPtrMappingFixed;
2532 /** The address of the previous RAM range mapping. */
2533 RTGCPTR GCPtrPrevRamRangeMapping;
2534
2535 /** @name Intermediate Context
2536 * @{ */
2537 /** Pointer to the intermediate page directory - Normal. */
2538 R3PTRTYPE(PX86PD) pInterPD;
2539 /** Pointer to the intermedate page tables - Normal.
2540 * There are two page tables, one for the identity mapping and one for
2541 * the host context mapping (of the core code). */
2542 R3PTRTYPE(PX86PT) apInterPTs[2];
2543 /** Pointer to the intermedate page tables - PAE. */
2544 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2545 /** Pointer to the intermedate page directory - PAE. */
2546 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2547 /** Pointer to the intermedate page directory - PAE. */
2548 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2549 /** Pointer to the intermedate page-map level 4 - AMD64. */
2550 R3PTRTYPE(PX86PML4) pInterPaePML4;
2551 /** Pointer to the intermedate page directory - AMD64. */
2552 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2553 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2554 RTHCPHYS HCPhysInterPD;
2555 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2556 RTHCPHYS HCPhysInterPaePDPT;
2557 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2558 RTHCPHYS HCPhysInterPaePML4;
2559 /** @} */
2560
2561 /** Base address of the dynamic page mapping area.
2562 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2563 */
2564 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2565 /** The index of the last entry used in the dynamic page mapping area. */
2566 RTUINT iDynPageMapLast;
2567 /** Cache containing the last entries in the dynamic page mapping area.
2568 * The cache size is covering half of the mapping area. */
2569 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2570 /** Keep a lock counter for the full (!) mapping area. */
2571 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2572
2573 /** The address of the ring-0 mapping cache if we're making use of it. */
2574 RTR0PTR pvR0DynMapUsed;
2575#if HC_ARCH_BITS == 32
2576 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2577 uint32_t u32Alignment2;
2578#endif
2579
2580 /** PGM critical section.
2581 * This protects the physical & virtual access handlers, ram ranges,
2582 * and the page flag updating (some of it anyway).
2583 */
2584 PDMCRITSECT CritSect;
2585
2586 /** Pointer to SHW+GST mode data (function pointers).
2587 * The index into this table is made up from */
2588 R3PTRTYPE(PPGMMODEDATA) paModeData;
2589
2590 /** Shadow Page Pool - R3 Ptr. */
2591 R3PTRTYPE(PPGMPOOL) pPoolR3;
2592 /** Shadow Page Pool - R0 Ptr. */
2593 R0PTRTYPE(PPGMPOOL) pPoolR0;
2594 /** Shadow Page Pool - RC Ptr. */
2595 RCPTRTYPE(PPGMPOOL) pPoolRC;
2596
2597 /** We're not in a state which permits writes to guest memory.
2598 * (Only used in strict builds.) */
2599 bool fNoMorePhysWrites;
2600 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2601 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2602
2603 /**
2604 * Data associated with managing the ring-3 mappings of the allocation chunks.
2605 */
2606 struct
2607 {
2608 /** The chunk tree, ordered by chunk id. */
2609#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2610 R3PTRTYPE(PAVLU32NODECORE) pTree;
2611#else
2612 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2613#endif
2614 /** The chunk age tree, ordered by ageing sequence number. */
2615 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2616 /** The chunk mapping TLB. */
2617 PGMCHUNKR3MAPTLB Tlb;
2618 /** The number of mapped chunks. */
2619 uint32_t c;
2620 /** The maximum number of mapped chunks.
2621 * @cfgm PGM/MaxRing3Chunks */
2622 uint32_t cMax;
2623 /** The current time. */
2624 uint32_t iNow;
2625 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2626 uint32_t AgeingCountdown;
2627 } ChunkR3Map;
2628
2629 /**
2630 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2631 */
2632 PGMPAGER3MAPTLB PhysTlbHC;
2633
2634 /** @name The zero page.
2635 * @{ */
2636 /** The host physical address of the zero page. */
2637 RTHCPHYS HCPhysZeroPg;
2638 /** The ring-3 mapping of the zero page. */
2639 RTR3PTR pvZeroPgR3;
2640 /** The ring-0 mapping of the zero page. */
2641 RTR0PTR pvZeroPgR0;
2642 /** The GC mapping of the zero page. */
2643 RTGCPTR pvZeroPgRC;
2644#if GC_ARCH_BITS != 32
2645 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2646#endif
2647 /** @}*/
2648
2649 /** The number of handy pages. */
2650 uint32_t cHandyPages;
2651 /**
2652 * Array of handy pages.
2653 *
2654 * This array is used in a two way communication between pgmPhysAllocPage
2655 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2656 * an intermediary.
2657 *
2658 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2659 * (The current size of 32 pages, means 128 KB of handy memory.)
2660 */
2661 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2662
2663 /**
2664 * Live save data.
2665 */
2666 struct
2667 {
2668 /** The number of ready pages. */
2669 uint32_t cReadyPages;
2670 /** The number of dirty pages. */
2671 uint32_t cDirtyPages;
2672 /** The number of monitored pages. */
2673 uint32_t cMonitoredPages;
2674 /** The number of ignored pages. */
2675 uint32_t cIgnoredPages;
2676 /** The number of MMIO2 pages. */
2677 uint32_t cMmio2Pages;
2678 /** Indicates that a live save operation is active. */
2679 bool fActive;
2680 /** Padding. */
2681 bool afReserved[3];
2682 } LiveSave;
2683
2684 /** @name Error injection.
2685 * @{ */
2686 /** Inject handy page allocation errors pretending we're completely out of
2687 * memory. */
2688 bool volatile fErrInjHandyPages;
2689 /** Padding. */
2690 bool afReserved[7];
2691 /** @} */
2692
2693 /** @name Release Statistics
2694 * @{ */
2695 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2696 uint32_t cPrivatePages; /**< The number of private pages. */
2697 uint32_t cSharedPages; /**< The number of shared pages. */
2698 uint32_t cZeroPages; /**< The number of zero backed pages. */
2699 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2700 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2701
2702 /** The number of times we were forced to change the hypervisor region location. */
2703 STAMCOUNTER cRelocations;
2704 /** @} */
2705
2706#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2707 /* R3 only: */
2708 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2709 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2710
2711 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2712 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2713 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2714 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2715 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2716 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2717 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2718 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2719 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2720 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2721 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2722 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2723 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2724 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2725 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2726 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2727 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2728 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2729/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2730 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2731 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2732/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2733
2734 /* RC only: */
2735 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2736 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2737 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2738 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2739
2740 STAMCOUNTER StatRZPhysRead;
2741 STAMCOUNTER StatRZPhysReadBytes;
2742 STAMCOUNTER StatRZPhysWrite;
2743 STAMCOUNTER StatRZPhysWriteBytes;
2744 STAMCOUNTER StatR3PhysRead;
2745 STAMCOUNTER StatR3PhysReadBytes;
2746 STAMCOUNTER StatR3PhysWrite;
2747 STAMCOUNTER StatR3PhysWriteBytes;
2748 STAMCOUNTER StatRCPhysRead;
2749 STAMCOUNTER StatRCPhysReadBytes;
2750 STAMCOUNTER StatRCPhysWrite;
2751 STAMCOUNTER StatRCPhysWriteBytes;
2752
2753 STAMCOUNTER StatRZPhysSimpleRead;
2754 STAMCOUNTER StatRZPhysSimpleReadBytes;
2755 STAMCOUNTER StatRZPhysSimpleWrite;
2756 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2757 STAMCOUNTER StatR3PhysSimpleRead;
2758 STAMCOUNTER StatR3PhysSimpleReadBytes;
2759 STAMCOUNTER StatR3PhysSimpleWrite;
2760 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2761 STAMCOUNTER StatRCPhysSimpleRead;
2762 STAMCOUNTER StatRCPhysSimpleReadBytes;
2763 STAMCOUNTER StatRCPhysSimpleWrite;
2764 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2765
2766# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2767 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2768 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2769 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2770 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2771 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2772 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2773# endif
2774#endif
2775} PGM;
2776#ifndef IN_TSTVMSTRUCTGC /* HACK */
2777AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2778AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2779AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2780AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2781AssertCompileMemberAlignment(PGM, CritSect, 8);
2782AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2783AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2784AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2785AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2786AssertCompileMemberAlignment(PGM, cRelocations, 8);
2787#endif /* !IN_TSTVMSTRUCTGC */
2788/** Pointer to the PGM instance data. */
2789typedef PGM *PPGM;
2790
2791
2792/**
2793 * Converts a PGMCPU pointer into a VM pointer.
2794 * @returns Pointer to the VM structure the PGM is part of.
2795 * @param pPGM Pointer to PGMCPU instance data.
2796 */
2797#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2798
2799/**
2800 * Converts a PGMCPU pointer into a PGM pointer.
2801 * @returns Pointer to the VM structure the PGM is part of.
2802 * @param pPGM Pointer to PGMCPU instance data.
2803 */
2804#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2805
2806/**
2807 * PGMCPU Data (part of VMCPU).
2808 */
2809typedef struct PGMCPU
2810{
2811 /** Offset to the VM structure. */
2812 RTINT offVM;
2813 /** Offset to the VMCPU structure. */
2814 RTINT offVCpu;
2815 /** Offset of the PGM structure relative to VMCPU. */
2816 RTINT offPGM;
2817 RTINT uPadding0; /**< structure size alignment. */
2818
2819#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2820 /** Automatically tracked physical memory mapping set.
2821 * Ring-0 and strict raw-mode builds. */
2822 PGMMAPSET AutoSet;
2823#endif
2824
2825 /** A20 gate mask.
2826 * Our current approach to A20 emulation is to let REM do it and don't bother
2827 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2828 * But whould need arrise, we'll subject physical addresses to this mask. */
2829 RTGCPHYS GCPhysA20Mask;
2830 /** A20 gate state - boolean! */
2831 bool fA20Enabled;
2832
2833 /** What needs syncing (PGM_SYNC_*).
2834 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2835 * PGMFlushTLB, and PGMR3Load. */
2836 RTUINT fSyncFlags;
2837
2838 /** The shadow paging mode. */
2839 PGMMODE enmShadowMode;
2840 /** The guest paging mode. */
2841 PGMMODE enmGuestMode;
2842
2843 /** The current physical address representing in the guest CR3 register. */
2844 RTGCPHYS GCPhysCR3;
2845
2846 /** @name 32-bit Guest Paging.
2847 * @{ */
2848 /** The guest's page directory, R3 pointer. */
2849 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2850#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2851 /** The guest's page directory, R0 pointer. */
2852 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2853#endif
2854 /** The guest's page directory, static RC mapping. */
2855 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2856 /** @} */
2857
2858 /** @name PAE Guest Paging.
2859 * @{ */
2860 /** The guest's page directory pointer table, static RC mapping. */
2861 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2862 /** The guest's page directory pointer table, R3 pointer. */
2863 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2864#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2865 /** The guest's page directory pointer table, R0 pointer. */
2866 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2867#endif
2868
2869 /** The guest's page directories, R3 pointers.
2870 * These are individual pointers and don't have to be adjecent.
2871 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2872 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2873 /** The guest's page directories, R0 pointers.
2874 * Same restrictions as apGstPaePDsR3. */
2875#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2876 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2877#endif
2878 /** The guest's page directories, static GC mapping.
2879 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2880 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2881 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2882 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2883 RTGCPHYS aGCPhysGstPaePDs[4];
2884 /** The physical addresses of the monitored guest page directories (PAE). */
2885 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2886 /** @} */
2887
2888 /** @name AMD64 Guest Paging.
2889 * @{ */
2890 /** The guest's page directory pointer table, R3 pointer. */
2891 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2892#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2893 /** The guest's page directory pointer table, R0 pointer. */
2894 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2895#endif
2896 /** @} */
2897
2898 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2899 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2900 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2901 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2902 /** Pointer to the page of the current active CR3 - RC Ptr. */
2903 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2904 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2905 uint32_t iShwUser;
2906 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2907 uint32_t iShwUserTable;
2908# if HC_ARCH_BITS == 64
2909 RTRCPTR alignment6; /**< structure size alignment. */
2910# endif
2911 /** @} */
2912
2913 /** @name Function pointers for Shadow paging.
2914 * @{
2915 */
2916 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2917 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2918 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2919 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2920
2921 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2922 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2923
2924 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2925 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2926
2927 /** @} */
2928
2929 /** @name Function pointers for Guest paging.
2930 * @{
2931 */
2932 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2933 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2934 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2935 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2936 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2937 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2938 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2939 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2940#if HC_ARCH_BITS == 64
2941 RTRCPTR alignment3; /**< structure size alignment. */
2942#endif
2943
2944 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2945 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2946 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2947 /** @} */
2948
2949 /** @name Function pointers for Both Shadow and Guest paging.
2950 * @{
2951 */
2952 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2953 /* no pfnR3BthTrap0eHandler */
2954 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2955 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2956 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2957 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2958 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2959 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2960 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2961 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2962
2963 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2964 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2965 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2966 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2967 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2968 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2969 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2970 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2971 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2972
2973 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2974 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2975 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2976 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2977 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2978 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2979 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2980 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2981 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2982 RTRCPTR alignment2; /**< structure size alignment. */
2983 /** @} */
2984
2985 /** For saving stack space, the disassembler state is allocated here instead of
2986 * on the stack.
2987 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2988 union
2989 {
2990 /** The disassembler scratch space. */
2991 DISCPUSTATE DisState;
2992 /** Padding. */
2993 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2994 };
2995
2996 /* Count the number of pgm pool access handler calls. */
2997 uint64_t cPoolAccessHandler;
2998
2999 /** @name Release Statistics
3000 * @{ */
3001 /** The number of times the guest has switched mode since last reset or statistics reset. */
3002 STAMCOUNTER cGuestModeChanges;
3003 /** @} */
3004
3005#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3006 /** @name Statistics
3007 * @{ */
3008 /** RC: Which statistic this \#PF should be attributed to. */
3009 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3010 RTRCPTR padding0;
3011 /** R0: Which statistic this \#PF should be attributed to. */
3012 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3013 RTR0PTR padding1;
3014
3015 /* Common */
3016 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3017 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3018
3019 /* R0 only: */
3020 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3021 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3022 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3023 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3024 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3025 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3026 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3027 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3028 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3029 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3030 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3031 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3032 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3033 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3034 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3035 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3036 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3037 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3038 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3039 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3040 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3041 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3042 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3043 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3044 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3045 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3046
3047 /* RZ only: */
3048 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3049 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3050 STAMPROFILE StatRZTrap0eTimeSyncPT;
3051 STAMPROFILE StatRZTrap0eTimeMapping;
3052 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3053 STAMPROFILE StatRZTrap0eTimeHandlers;
3054 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3055 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3056 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3057 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3058 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3059 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3060 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3061 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3062 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3063 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3064 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3065 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3066 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3067 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3068 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3069 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3070 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3071 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3072 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3073 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3074 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3075 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
3076 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
3077 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
3078 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
3079 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
3080 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
3081 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
3082 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
3083 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
3084 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
3085 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
3086 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
3087 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
3088 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
3089 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3090 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3091 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
3092 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3093 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3094 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3095 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3096 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3097
3098 /* HC - R3 and (maybe) R0: */
3099
3100 /* RZ & R3: */
3101 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3102 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3103 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3104 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3105 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3106 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3107 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3108 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3109 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3110 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3111 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3112 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3113 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3114 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3115 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3116 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3117 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3118 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3119 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3120 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3121 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3122 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3123 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3124 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3125 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3126 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3127 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3128 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3129 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3130 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3131 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3132 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3133 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3134 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3135 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3136 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3137 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3138 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in #PF. */
3139 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF. */
3140 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3141 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3142 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3143 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3144 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3145 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3146 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3147
3148 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3149 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3150 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3151 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3152 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3153 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3154 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3155 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3156 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3157 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3158 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3159 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3160 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3161 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3162 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3163 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3164 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3165 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3166 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3167 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3168 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3169 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3170 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3171 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3172 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3173 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3174 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3175 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3176 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3177 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3178 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3179 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3180 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3181 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3182 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3183 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3184 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in #PF. */
3185 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in #PF. */
3186 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3187 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3188 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3189 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3190 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3191 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3192 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3193 /** @} */
3194#endif /* VBOX_WITH_STATISTICS */
3195} PGMCPU;
3196/** Pointer to the per-cpu PGM data. */
3197typedef PGMCPU *PPGMCPU;
3198
3199
3200/** @name PGM::fSyncFlags Flags
3201 * @{
3202 */
3203/** Updates the virtual access handler state bit in PGMPAGE. */
3204#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3205/** Always sync CR3. */
3206#define PGM_SYNC_ALWAYS RT_BIT(1)
3207/** Check monitoring on next CR3 (re)load and invalidate page.
3208 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3209#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3210/** Check guest mapping in SyncCR3. */
3211#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3212/** Clear the page pool (a light weight flush). */
3213#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3214#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3215/** @} */
3216
3217
3218RT_C_DECLS_BEGIN
3219
3220int pgmLock(PVM pVM);
3221void pgmUnlock(PVM pVM);
3222
3223int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3224int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3225PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3226void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3227DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3228
3229void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3230bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3231void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3232int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3233DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3234#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3235void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3236#else
3237# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3238#endif
3239DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3240int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3241
3242int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3243int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3244int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3245int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3246int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3247int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3248int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3249int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3250int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3251int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3252int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3253VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3254#ifdef IN_RING3
3255void pgmR3PhysRelinkRamRanges(PVM pVM);
3256int pgmR3PhysRamPreAllocate(PVM pVM);
3257int pgmR3PhysRamReset(PVM pVM);
3258int pgmR3PhysRomReset(PVM pVM);
3259int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3260
3261int pgmR3PoolInit(PVM pVM);
3262void pgmR3PoolRelocate(PVM pVM);
3263void pgmR3PoolReset(PVM pVM);
3264void pgmR3PoolClearAll(PVM pVM);
3265
3266#endif /* IN_RING3 */
3267#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3268int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3269#endif
3270int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3271
3272DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3273{
3274 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3275}
3276
3277void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3278void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3279int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3280void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3281PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3282int pgmPoolSyncCR3(PVMCPU pVCpu);
3283bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3284int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3285DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3286{
3287 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3288}
3289
3290uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3291void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3292void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3293#ifdef PGMPOOL_WITH_MONITORING
3294void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3295int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3296void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3297#endif
3298
3299void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3300void pgmPoolResetDirtyPages(PVM pVM);
3301
3302int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3303int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3304
3305void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3306void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3307int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3308int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3309
3310int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3311#ifndef IN_RC
3312int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3313#endif
3314int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3315
3316PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3317PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3318PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3319PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3320
3321RT_C_DECLS_END
3322
3323
3324/**
3325 * Gets the PGMRAMRANGE structure for a guest page.
3326 *
3327 * @returns Pointer to the RAM range on success.
3328 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3329 *
3330 * @param pPGM PGM handle.
3331 * @param GCPhys The GC physical address.
3332 */
3333DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3334{
3335 /*
3336 * Optimize for the first range.
3337 */
3338 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3339 RTGCPHYS off = GCPhys - pRam->GCPhys;
3340 if (RT_UNLIKELY(off >= pRam->cb))
3341 {
3342 do
3343 {
3344 pRam = pRam->CTX_SUFF(pNext);
3345 if (RT_UNLIKELY(!pRam))
3346 break;
3347 off = GCPhys - pRam->GCPhys;
3348 } while (off >= pRam->cb);
3349 }
3350 return pRam;
3351}
3352
3353
3354/**
3355 * Gets the PGMPAGE structure for a guest page.
3356 *
3357 * @returns Pointer to the page on success.
3358 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3359 *
3360 * @param pPGM PGM handle.
3361 * @param GCPhys The GC physical address.
3362 */
3363DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3364{
3365 /*
3366 * Optimize for the first range.
3367 */
3368 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3369 RTGCPHYS off = GCPhys - pRam->GCPhys;
3370 if (RT_UNLIKELY(off >= pRam->cb))
3371 {
3372 do
3373 {
3374 pRam = pRam->CTX_SUFF(pNext);
3375 if (RT_UNLIKELY(!pRam))
3376 return NULL;
3377 off = GCPhys - pRam->GCPhys;
3378 } while (off >= pRam->cb);
3379 }
3380 return &pRam->aPages[off >> PAGE_SHIFT];
3381}
3382
3383
3384/**
3385 * Gets the PGMPAGE structure for a guest page.
3386 *
3387 * Old Phys code: Will make sure the page is present.
3388 *
3389 * @returns VBox status code.
3390 * @retval VINF_SUCCESS and a valid *ppPage on success.
3391 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3392 *
3393 * @param pPGM PGM handle.
3394 * @param GCPhys The GC physical address.
3395 * @param ppPage Where to store the page pointer on success.
3396 */
3397DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3398{
3399 /*
3400 * Optimize for the first range.
3401 */
3402 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3403 RTGCPHYS off = GCPhys - pRam->GCPhys;
3404 if (RT_UNLIKELY(off >= pRam->cb))
3405 {
3406 do
3407 {
3408 pRam = pRam->CTX_SUFF(pNext);
3409 if (RT_UNLIKELY(!pRam))
3410 {
3411 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3412 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3413 }
3414 off = GCPhys - pRam->GCPhys;
3415 } while (off >= pRam->cb);
3416 }
3417 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3418 return VINF_SUCCESS;
3419}
3420
3421
3422
3423
3424/**
3425 * Gets the PGMPAGE structure for a guest page.
3426 *
3427 * Old Phys code: Will make sure the page is present.
3428 *
3429 * @returns VBox status code.
3430 * @retval VINF_SUCCESS and a valid *ppPage on success.
3431 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3432 *
3433 * @param pPGM PGM handle.
3434 * @param GCPhys The GC physical address.
3435 * @param ppPage Where to store the page pointer on success.
3436 * @param ppRamHint Where to read and store the ram list hint.
3437 * The caller initializes this to NULL before the call.
3438 */
3439DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3440{
3441 RTGCPHYS off;
3442 PPGMRAMRANGE pRam = *ppRamHint;
3443 if ( !pRam
3444 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3445 {
3446 pRam = pPGM->CTX_SUFF(pRamRanges);
3447 off = GCPhys - pRam->GCPhys;
3448 if (RT_UNLIKELY(off >= pRam->cb))
3449 {
3450 do
3451 {
3452 pRam = pRam->CTX_SUFF(pNext);
3453 if (RT_UNLIKELY(!pRam))
3454 {
3455 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3456 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3457 }
3458 off = GCPhys - pRam->GCPhys;
3459 } while (off >= pRam->cb);
3460 }
3461 *ppRamHint = pRam;
3462 }
3463 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3464 return VINF_SUCCESS;
3465}
3466
3467
3468/**
3469 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3470 *
3471 * @returns Pointer to the page on success.
3472 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3473 *
3474 * @param pPGM PGM handle.
3475 * @param GCPhys The GC physical address.
3476 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3477 */
3478DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3479{
3480 /*
3481 * Optimize for the first range.
3482 */
3483 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3484 RTGCPHYS off = GCPhys - pRam->GCPhys;
3485 if (RT_UNLIKELY(off >= pRam->cb))
3486 {
3487 do
3488 {
3489 pRam = pRam->CTX_SUFF(pNext);
3490 if (RT_UNLIKELY(!pRam))
3491 return NULL;
3492 off = GCPhys - pRam->GCPhys;
3493 } while (off >= pRam->cb);
3494 }
3495 *ppRam = pRam;
3496 return &pRam->aPages[off >> PAGE_SHIFT];
3497}
3498
3499
3500/**
3501 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3502 *
3503 * @returns Pointer to the page on success.
3504 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3505 *
3506 * @param pPGM PGM handle.
3507 * @param GCPhys The GC physical address.
3508 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3509 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3510 */
3511DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3512{
3513 /*
3514 * Optimize for the first range.
3515 */
3516 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3517 RTGCPHYS off = GCPhys - pRam->GCPhys;
3518 if (RT_UNLIKELY(off >= pRam->cb))
3519 {
3520 do
3521 {
3522 pRam = pRam->CTX_SUFF(pNext);
3523 if (RT_UNLIKELY(!pRam))
3524 {
3525 *ppRam = NULL; /* Shut up silly GCC warnings. */
3526 *ppPage = NULL; /* ditto */
3527 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3528 }
3529 off = GCPhys - pRam->GCPhys;
3530 } while (off >= pRam->cb);
3531 }
3532 *ppRam = pRam;
3533 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3534 return VINF_SUCCESS;
3535}
3536
3537
3538/**
3539 * Convert GC Phys to HC Phys.
3540 *
3541 * @returns VBox status.
3542 * @param pPGM PGM handle.
3543 * @param GCPhys The GC physical address.
3544 * @param pHCPhys Where to store the corresponding HC physical address.
3545 *
3546 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3547 * Avoid when writing new code!
3548 */
3549DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3550{
3551 PPGMPAGE pPage;
3552 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3553 if (RT_FAILURE(rc))
3554 return rc;
3555 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3556 return VINF_SUCCESS;
3557}
3558
3559#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3560
3561/**
3562 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3563 * optimizes access to pages already in the set.
3564 *
3565 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3566 * @param pPGM Pointer to the PVM instance data.
3567 * @param HCPhys The physical address of the page.
3568 * @param ppv Where to store the mapping address.
3569 */
3570DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3571{
3572 PVM pVM = PGM2VM(pPGM);
3573 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3574 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3575
3576 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3577 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3578 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3579
3580 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3581 unsigned iEntry = pSet->aiHashTable[iHash];
3582 if ( iEntry < pSet->cEntries
3583 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3584 {
3585 *ppv = pSet->aEntries[iEntry].pvPage;
3586 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3587 }
3588 else
3589 {
3590 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3591 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3592 }
3593
3594 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/**
3600 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3601 * access to pages already in the set.
3602 *
3603 * @returns See PGMDynMapGCPage.
3604 * @param pPGM Pointer to the PVM instance data.
3605 * @param HCPhys The physical address of the page.
3606 * @param ppv Where to store the mapping address.
3607 */
3608DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3609{
3610 PVM pVM = PGM2VM(pPGM);
3611 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3612
3613 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3614 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3615
3616 /*
3617 * Get the ram range.
3618 */
3619 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3620 RTGCPHYS off = GCPhys - pRam->GCPhys;
3621 if (RT_UNLIKELY(off >= pRam->cb
3622 /** @todo || page state stuff */))
3623 {
3624 /* This case is not counted into StatR0DynMapGCPageInl. */
3625 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3626 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3627 }
3628
3629 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3630 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3631
3632 /*
3633 * pgmR0DynMapHCPageInlined with out stats.
3634 */
3635 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3636 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3637 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3638
3639 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3640 unsigned iEntry = pSet->aiHashTable[iHash];
3641 if ( iEntry < pSet->cEntries
3642 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3643 {
3644 *ppv = pSet->aEntries[iEntry].pvPage;
3645 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3646 }
3647 else
3648 {
3649 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3650 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3651 }
3652
3653 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3654 return VINF_SUCCESS;
3655}
3656
3657
3658/**
3659 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3660 * access to pages already in the set.
3661 *
3662 * @returns See PGMDynMapGCPage.
3663 * @param pPGM Pointer to the PVM instance data.
3664 * @param HCPhys The physical address of the page.
3665 * @param ppv Where to store the mapping address.
3666 */
3667DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3668{
3669 PVM pVM = PGM2VM(pPGM);
3670 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3671
3672 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3673
3674 /*
3675 * Get the ram range.
3676 */
3677 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3678 RTGCPHYS off = GCPhys - pRam->GCPhys;
3679 if (RT_UNLIKELY(off >= pRam->cb
3680 /** @todo || page state stuff */))
3681 {
3682 /* This case is not counted into StatR0DynMapGCPageInl. */
3683 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3684 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3685 }
3686
3687 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3688 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3689
3690 /*
3691 * pgmR0DynMapHCPageInlined with out stats.
3692 */
3693 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3694 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3695 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3696
3697 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3698 unsigned iEntry = pSet->aiHashTable[iHash];
3699 if ( iEntry < pSet->cEntries
3700 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3701 {
3702 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3703 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3704 }
3705 else
3706 {
3707 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3708 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3709 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3710 }
3711
3712 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3713 return VINF_SUCCESS;
3714}
3715
3716#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3717#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3718
3719/**
3720 * Maps the page into current context (RC and maybe R0).
3721 *
3722 * @returns pointer to the mapping.
3723 * @param pVM Pointer to the PGM instance data.
3724 * @param pPage The page.
3725 */
3726DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3727{
3728 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3729 {
3730 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3731 void *pv;
3732# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3733 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3734# else
3735 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3736# endif
3737 return pv;
3738 }
3739 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3740}
3741
3742/**
3743 * Temporarily maps one host page specified by HC physical address, returning
3744 * pointer within the page.
3745 *
3746 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3747 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3748 *
3749 * @returns The address corresponding to HCPhys.
3750 * @param pPGM Pointer to the PVM instance data.
3751 * @param HCPhys HC Physical address of the page.
3752 */
3753DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3754{
3755 void *pv;
3756# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3757 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3758# else
3759 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3760# endif
3761 pv = (void *)((uintptr_t)pv | ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3762 return pv;
3763}
3764
3765#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3766#ifndef IN_RC
3767
3768/**
3769 * Queries the Physical TLB entry for a physical guest page,
3770 * attempting to load the TLB entry if necessary.
3771 *
3772 * @returns VBox status code.
3773 * @retval VINF_SUCCESS on success
3774 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3775 *
3776 * @param pPGM The PGM instance handle.
3777 * @param GCPhys The address of the guest page.
3778 * @param ppTlbe Where to store the pointer to the TLB entry.
3779 */
3780DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3781{
3782 int rc;
3783 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3784 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3785 {
3786 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3787 rc = VINF_SUCCESS;
3788 }
3789 else
3790 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3791 *ppTlbe = pTlbe;
3792 return rc;
3793}
3794
3795
3796/**
3797 * Queries the Physical TLB entry for a physical guest page,
3798 * attempting to load the TLB entry if necessary.
3799 *
3800 * @returns VBox status code.
3801 * @retval VINF_SUCCESS on success
3802 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3803 *
3804 * @param pPGM The PGM instance handle.
3805 * @param pPage Pointer to the PGMPAGE structure corresponding to
3806 * GCPhys.
3807 * @param GCPhys The address of the guest page.
3808 * @param ppTlbe Where to store the pointer to the TLB entry.
3809 */
3810DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3811{
3812 int rc;
3813 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3814 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3815 {
3816 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3817 rc = VINF_SUCCESS;
3818 }
3819 else
3820 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3821 *ppTlbe = pTlbe;
3822 return rc;
3823}
3824
3825#endif /* !IN_RC */
3826
3827/**
3828 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3829 * Takes PSE-36 into account.
3830 *
3831 * @returns guest physical address
3832 * @param pPGM Pointer to the PGM instance data.
3833 * @param Pde Guest Pde
3834 */
3835DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3836{
3837 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3838 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3839
3840 return GCPhys & pPGM->GCPhys4MBPSEMask;
3841}
3842
3843
3844/**
3845 * Gets the page directory entry for the specified address (32-bit paging).
3846 *
3847 * @returns The page directory entry in question.
3848 * @param pPGM Pointer to the PGM instance data.
3849 * @param GCPtr The address.
3850 */
3851DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3852{
3853#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3854 PCX86PD pGuestPD = NULL;
3855 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3856 if (RT_FAILURE(rc))
3857 {
3858 X86PDE ZeroPde = {0};
3859 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3860 }
3861#else
3862 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3863# ifdef IN_RING3
3864 if (!pGuestPD)
3865 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3866# endif
3867#endif
3868 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3869}
3870
3871
3872/**
3873 * Gets the address of a specific page directory entry (32-bit paging).
3874 *
3875 * @returns Pointer the page directory entry in question.
3876 * @param pPGM Pointer to the PGM instance data.
3877 * @param GCPtr The address.
3878 */
3879DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3880{
3881#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3882 PX86PD pGuestPD = NULL;
3883 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3884 AssertRCReturn(rc, NULL);
3885#else
3886 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3887# ifdef IN_RING3
3888 if (!pGuestPD)
3889 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3890# endif
3891#endif
3892 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3893}
3894
3895
3896/**
3897 * Gets the address the guest page directory (32-bit paging).
3898 *
3899 * @returns Pointer the page directory entry in question.
3900 * @param pPGM Pointer to the PGM instance data.
3901 */
3902DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3903{
3904#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3905 PX86PD pGuestPD = NULL;
3906 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3907 AssertRCReturn(rc, NULL);
3908#else
3909 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3910# ifdef IN_RING3
3911 if (!pGuestPD)
3912 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3913# endif
3914#endif
3915 return pGuestPD;
3916}
3917
3918
3919/**
3920 * Gets the guest page directory pointer table.
3921 *
3922 * @returns Pointer to the page directory in question.
3923 * @returns NULL if the page directory is not present or on an invalid page.
3924 * @param pPGM Pointer to the PGM instance data.
3925 */
3926DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3927{
3928#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3929 PX86PDPT pGuestPDPT = NULL;
3930 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3931 AssertRCReturn(rc, NULL);
3932#else
3933 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3934# ifdef IN_RING3
3935 if (!pGuestPDPT)
3936 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3937# endif
3938#endif
3939 return pGuestPDPT;
3940}
3941
3942
3943/**
3944 * Gets the guest page directory pointer table entry for the specified address.
3945 *
3946 * @returns Pointer to the page directory in question.
3947 * @returns NULL if the page directory is not present or on an invalid page.
3948 * @param pPGM Pointer to the PGM instance data.
3949 * @param GCPtr The address.
3950 */
3951DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3952{
3953 AssertGCPtr32(GCPtr);
3954
3955#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3956 PX86PDPT pGuestPDPT = 0;
3957 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3958 AssertRCReturn(rc, 0);
3959#else
3960 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3961# ifdef IN_RING3
3962 if (!pGuestPDPT)
3963 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3964# endif
3965#endif
3966 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3967}
3968
3969
3970/**
3971 * Gets the page directory for the specified address.
3972 *
3973 * @returns Pointer to the page directory in question.
3974 * @returns NULL if the page directory is not present or on an invalid page.
3975 * @param pPGM Pointer to the PGM instance data.
3976 * @param GCPtr The address.
3977 */
3978DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3979{
3980 AssertGCPtr32(GCPtr);
3981
3982 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3983 AssertReturn(pGuestPDPT, NULL);
3984 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3985 if (pGuestPDPT->a[iPdpt].n.u1Present)
3986 {
3987#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3988 PX86PDPAE pGuestPD = NULL;
3989 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3990 AssertRCReturn(rc, NULL);
3991#else
3992 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3993 if ( !pGuestPD
3994 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3995 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3996#endif
3997 return pGuestPD;
3998 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3999 }
4000 return NULL;
4001}
4002
4003
4004/**
4005 * Gets the page directory entry for the specified address.
4006 *
4007 * @returns Pointer to the page directory entry in question.
4008 * @returns NULL if the page directory is not present or on an invalid page.
4009 * @param pPGM Pointer to the PGM instance data.
4010 * @param GCPtr The address.
4011 */
4012DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4013{
4014 AssertGCPtr32(GCPtr);
4015
4016 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4017 AssertReturn(pGuestPDPT, NULL);
4018 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4019 if (pGuestPDPT->a[iPdpt].n.u1Present)
4020 {
4021 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4022#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4023 PX86PDPAE pGuestPD = NULL;
4024 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4025 AssertRCReturn(rc, NULL);
4026#else
4027 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4028 if ( !pGuestPD
4029 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4030 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4031#endif
4032 return &pGuestPD->a[iPD];
4033 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
4034 }
4035 return NULL;
4036}
4037
4038
4039/**
4040 * Gets the page directory entry for the specified address.
4041 *
4042 * @returns The page directory entry in question.
4043 * @returns A non-present entry if the page directory is not present or on an invalid page.
4044 * @param pPGM Pointer to the PGM instance data.
4045 * @param GCPtr The address.
4046 */
4047DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4048{
4049 AssertGCPtr32(GCPtr);
4050 X86PDEPAE ZeroPde = {0};
4051 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4052 if (RT_LIKELY(pGuestPDPT))
4053 {
4054 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4055 if (pGuestPDPT->a[iPdpt].n.u1Present)
4056 {
4057 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4058#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4059 PX86PDPAE pGuestPD = NULL;
4060 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4061 AssertRCReturn(rc, ZeroPde);
4062#else
4063 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4064 if ( !pGuestPD
4065 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4066 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4067#endif
4068 return pGuestPD->a[iPD];
4069 }
4070 }
4071 return ZeroPde;
4072}
4073
4074
4075/**
4076 * Gets the page directory pointer table entry for the specified address
4077 * and returns the index into the page directory
4078 *
4079 * @returns Pointer to the page directory in question.
4080 * @returns NULL if the page directory is not present or on an invalid page.
4081 * @param pPGM Pointer to the PGM instance data.
4082 * @param GCPtr The address.
4083 * @param piPD Receives the index into the returned page directory
4084 * @param pPdpe Receives the page directory pointer entry. Optional.
4085 */
4086DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4087{
4088 AssertGCPtr32(GCPtr);
4089
4090 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4091 AssertReturn(pGuestPDPT, NULL);
4092 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4093 if (pPdpe)
4094 *pPdpe = pGuestPDPT->a[iPdpt];
4095 if (pGuestPDPT->a[iPdpt].n.u1Present)
4096 {
4097 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4098#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4099 PX86PDPAE pGuestPD = NULL;
4100 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4101 AssertRCReturn(rc, NULL);
4102#else
4103 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4104 if ( !pGuestPD
4105 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4106 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4107#endif
4108 *piPD = iPD;
4109 return pGuestPD;
4110 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4111 }
4112 return NULL;
4113}
4114
4115#ifndef IN_RC
4116
4117/**
4118 * Gets the page map level-4 pointer for the guest.
4119 *
4120 * @returns Pointer to the PML4 page.
4121 * @param pPGM Pointer to the PGM instance data.
4122 */
4123DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4124{
4125#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4126 PX86PML4 pGuestPml4;
4127 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4128 AssertRCReturn(rc, NULL);
4129#else
4130 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4131# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4132 if (!pGuestPml4)
4133 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4134# endif
4135 Assert(pGuestPml4);
4136#endif
4137 return pGuestPml4;
4138}
4139
4140
4141/**
4142 * Gets the pointer to a page map level-4 entry.
4143 *
4144 * @returns Pointer to the PML4 entry.
4145 * @param pPGM Pointer to the PGM instance data.
4146 * @param iPml4 The index.
4147 */
4148DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4149{
4150#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4151 PX86PML4 pGuestPml4;
4152 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4153 AssertRCReturn(rc, NULL);
4154#else
4155 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4156# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4157 if (!pGuestPml4)
4158 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4159# endif
4160 Assert(pGuestPml4);
4161#endif
4162 return &pGuestPml4->a[iPml4];
4163}
4164
4165
4166/**
4167 * Gets a page map level-4 entry.
4168 *
4169 * @returns The PML4 entry.
4170 * @param pPGM Pointer to the PGM instance data.
4171 * @param iPml4 The index.
4172 */
4173DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4174{
4175#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4176 PX86PML4 pGuestPml4;
4177 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4178 if (RT_FAILURE(rc))
4179 {
4180 X86PML4E ZeroPml4e = {0};
4181 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4182 }
4183#else
4184 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4185# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4186 if (!pGuestPml4)
4187 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4188# endif
4189 Assert(pGuestPml4);
4190#endif
4191 return pGuestPml4->a[iPml4];
4192}
4193
4194
4195/**
4196 * Gets the page directory pointer entry for the specified address.
4197 *
4198 * @returns Pointer to the page directory pointer entry in question.
4199 * @returns NULL if the page directory is not present or on an invalid page.
4200 * @param pPGM Pointer to the PGM instance data.
4201 * @param GCPtr The address.
4202 * @param ppPml4e Page Map Level-4 Entry (out)
4203 */
4204DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4205{
4206 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4207 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4208 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4209 if (pPml4e->n.u1Present)
4210 {
4211 PX86PDPT pPdpt;
4212 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4213 AssertRCReturn(rc, NULL);
4214
4215 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4216 return &pPdpt->a[iPdpt];
4217 }
4218 return NULL;
4219}
4220
4221
4222/**
4223 * Gets the page directory entry for the specified address.
4224 *
4225 * @returns The page directory entry in question.
4226 * @returns A non-present entry if the page directory is not present or on an invalid page.
4227 * @param pPGM Pointer to the PGM instance data.
4228 * @param GCPtr The address.
4229 * @param ppPml4e Page Map Level-4 Entry (out)
4230 * @param pPdpe Page directory pointer table entry (out)
4231 */
4232DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4233{
4234 X86PDEPAE ZeroPde = {0};
4235 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4236 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4237 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4238 if (pPml4e->n.u1Present)
4239 {
4240 PCX86PDPT pPdptTemp;
4241 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4242 AssertRCReturn(rc, ZeroPde);
4243
4244 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4245 *pPdpe = pPdptTemp->a[iPdpt];
4246 if (pPdptTemp->a[iPdpt].n.u1Present)
4247 {
4248 PCX86PDPAE pPD;
4249 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4250 AssertRCReturn(rc, ZeroPde);
4251
4252 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4253 return pPD->a[iPD];
4254 }
4255 }
4256
4257 return ZeroPde;
4258}
4259
4260
4261/**
4262 * Gets the page directory entry for the specified address.
4263 *
4264 * @returns The page directory entry in question.
4265 * @returns A non-present entry if the page directory is not present or on an invalid page.
4266 * @param pPGM Pointer to the PGM instance data.
4267 * @param GCPtr The address.
4268 */
4269DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4270{
4271 X86PDEPAE ZeroPde = {0};
4272 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4273 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4274 if (pGuestPml4->a[iPml4].n.u1Present)
4275 {
4276 PCX86PDPT pPdptTemp;
4277 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4278 AssertRCReturn(rc, ZeroPde);
4279
4280 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4281 if (pPdptTemp->a[iPdpt].n.u1Present)
4282 {
4283 PCX86PDPAE pPD;
4284 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4285 AssertRCReturn(rc, ZeroPde);
4286
4287 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4288 return pPD->a[iPD];
4289 }
4290 }
4291 return ZeroPde;
4292}
4293
4294
4295/**
4296 * Gets the page directory entry for the specified address.
4297 *
4298 * @returns Pointer to the page directory entry in question.
4299 * @returns NULL if the page directory is not present or on an invalid page.
4300 * @param pPGM Pointer to the PGM instance data.
4301 * @param GCPtr The address.
4302 */
4303DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4304{
4305 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4306 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4307 if (pGuestPml4->a[iPml4].n.u1Present)
4308 {
4309 PCX86PDPT pPdptTemp;
4310 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4311 AssertRCReturn(rc, NULL);
4312
4313 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4314 if (pPdptTemp->a[iPdpt].n.u1Present)
4315 {
4316 PX86PDPAE pPD;
4317 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4318 AssertRCReturn(rc, NULL);
4319
4320 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4321 return &pPD->a[iPD];
4322 }
4323 }
4324 return NULL;
4325}
4326
4327
4328/**
4329 * Gets the GUEST page directory pointer for the specified address.
4330 *
4331 * @returns The page directory in question.
4332 * @returns NULL if the page directory is not present or on an invalid page.
4333 * @param pPGM Pointer to the PGM instance data.
4334 * @param GCPtr The address.
4335 * @param ppPml4e Page Map Level-4 Entry (out)
4336 * @param pPdpe Page directory pointer table entry (out)
4337 * @param piPD Receives the index into the returned page directory
4338 */
4339DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4340{
4341 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4342 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4343 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4344 if (pPml4e->n.u1Present)
4345 {
4346 PCX86PDPT pPdptTemp;
4347 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4348 AssertRCReturn(rc, NULL);
4349
4350 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4351 *pPdpe = pPdptTemp->a[iPdpt];
4352 if (pPdptTemp->a[iPdpt].n.u1Present)
4353 {
4354 PX86PDPAE pPD;
4355 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4356 AssertRCReturn(rc, NULL);
4357
4358 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4359 return pPD;
4360 }
4361 }
4362 return 0;
4363}
4364
4365#endif /* !IN_RC */
4366
4367/**
4368 * Gets the shadow page directory, 32-bit.
4369 *
4370 * @returns Pointer to the shadow 32-bit PD.
4371 * @param pPGM Pointer to the PGM instance data.
4372 */
4373DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4374{
4375 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4376}
4377
4378
4379/**
4380 * Gets the shadow page directory entry for the specified address, 32-bit.
4381 *
4382 * @returns Shadow 32-bit PDE.
4383 * @param pPGM Pointer to the PGM instance data.
4384 * @param GCPtr The address.
4385 */
4386DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4387{
4388 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4389
4390 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4391 if (!pShwPde)
4392 {
4393 X86PDE ZeroPde = {0};
4394 return ZeroPde;
4395 }
4396 return pShwPde->a[iPd];
4397}
4398
4399
4400/**
4401 * Gets the pointer to the shadow page directory entry for the specified
4402 * address, 32-bit.
4403 *
4404 * @returns Pointer to the shadow 32-bit PDE.
4405 * @param pPGM Pointer to the PGM instance data.
4406 * @param GCPtr The address.
4407 */
4408DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4409{
4410 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4411
4412 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4413 AssertReturn(pPde, NULL);
4414 return &pPde->a[iPd];
4415}
4416
4417
4418/**
4419 * Gets the shadow page pointer table, PAE.
4420 *
4421 * @returns Pointer to the shadow PAE PDPT.
4422 * @param pPGM Pointer to the PGM instance data.
4423 */
4424DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4425{
4426 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4427}
4428
4429
4430/**
4431 * Gets the shadow page directory for the specified address, PAE.
4432 *
4433 * @returns Pointer to the shadow PD.
4434 * @param pPGM Pointer to the PGM instance data.
4435 * @param GCPtr The address.
4436 */
4437DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4438{
4439 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4440 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4441
4442 if (!pPdpt->a[iPdpt].n.u1Present)
4443 return NULL;
4444
4445 /* Fetch the pgm pool shadow descriptor. */
4446 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4447 AssertReturn(pShwPde, NULL);
4448
4449 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4450}
4451
4452
4453/**
4454 * Gets the shadow page directory for the specified address, PAE.
4455 *
4456 * @returns Pointer to the shadow PD.
4457 * @param pPGM Pointer to the PGM instance data.
4458 * @param GCPtr The address.
4459 */
4460DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4461{
4462 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4463
4464 if (!pPdpt->a[iPdpt].n.u1Present)
4465 return NULL;
4466
4467 /* Fetch the pgm pool shadow descriptor. */
4468 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4469 AssertReturn(pShwPde, NULL);
4470
4471 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4472}
4473
4474
4475/**
4476 * Gets the shadow page directory entry, PAE.
4477 *
4478 * @returns PDE.
4479 * @param pPGM Pointer to the PGM instance data.
4480 * @param GCPtr The address.
4481 */
4482DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4483{
4484 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4485
4486 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4487 if (!pShwPde)
4488 {
4489 X86PDEPAE ZeroPde = {0};
4490 return ZeroPde;
4491 }
4492 return pShwPde->a[iPd];
4493}
4494
4495
4496/**
4497 * Gets the pointer to the shadow page directory entry for an address, PAE.
4498 *
4499 * @returns Pointer to the PDE.
4500 * @param pPGM Pointer to the PGM instance data.
4501 * @param GCPtr The address.
4502 */
4503DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4504{
4505 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4506
4507 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4508 AssertReturn(pPde, NULL);
4509 return &pPde->a[iPd];
4510}
4511
4512#ifndef IN_RC
4513
4514/**
4515 * Gets the shadow page map level-4 pointer.
4516 *
4517 * @returns Pointer to the shadow PML4.
4518 * @param pPGM Pointer to the PGM instance data.
4519 */
4520DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4521{
4522 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4523}
4524
4525
4526/**
4527 * Gets the shadow page map level-4 entry for the specified address.
4528 *
4529 * @returns The entry.
4530 * @param pPGM Pointer to the PGM instance data.
4531 * @param GCPtr The address.
4532 */
4533DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4534{
4535 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4536 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4537
4538 if (!pShwPml4)
4539 {
4540 X86PML4E ZeroPml4e = {0};
4541 return ZeroPml4e;
4542 }
4543 return pShwPml4->a[iPml4];
4544}
4545
4546
4547/**
4548 * Gets the pointer to the specified shadow page map level-4 entry.
4549 *
4550 * @returns The entry.
4551 * @param pPGM Pointer to the PGM instance data.
4552 * @param iPml4 The PML4 index.
4553 */
4554DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4555{
4556 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4557 if (!pShwPml4)
4558 return NULL;
4559 return &pShwPml4->a[iPml4];
4560}
4561
4562
4563/**
4564 * Gets the GUEST page directory pointer for the specified address.
4565 *
4566 * @returns The page directory in question.
4567 * @returns NULL if the page directory is not present or on an invalid page.
4568 * @param pPGM Pointer to the PGM instance data.
4569 * @param GCPtr The address.
4570 * @param piPD Receives the index into the returned page directory
4571 */
4572DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4573{
4574 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4575 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4576 if (pGuestPml4->a[iPml4].n.u1Present)
4577 {
4578 PCX86PDPT pPdptTemp;
4579 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4580 AssertRCReturn(rc, NULL);
4581
4582 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4583 if (pPdptTemp->a[iPdpt].n.u1Present)
4584 {
4585 PX86PDPAE pPD;
4586 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4587 AssertRCReturn(rc, NULL);
4588
4589 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4590 return pPD;
4591 }
4592 }
4593 return NULL;
4594}
4595
4596#endif /* !IN_RC */
4597
4598/**
4599 * Gets the page state for a physical handler.
4600 *
4601 * @returns The physical handler page state.
4602 * @param pCur The physical handler in question.
4603 */
4604DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4605{
4606 switch (pCur->enmType)
4607 {
4608 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4609 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4610
4611 case PGMPHYSHANDLERTYPE_MMIO:
4612 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4613 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4614
4615 default:
4616 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4617 }
4618}
4619
4620
4621/**
4622 * Gets the page state for a virtual handler.
4623 *
4624 * @returns The virtual handler page state.
4625 * @param pCur The virtual handler in question.
4626 * @remarks This should never be used on a hypervisor access handler.
4627 */
4628DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4629{
4630 switch (pCur->enmType)
4631 {
4632 case PGMVIRTHANDLERTYPE_WRITE:
4633 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4634 case PGMVIRTHANDLERTYPE_ALL:
4635 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4636 default:
4637 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4638 }
4639}
4640
4641
4642/**
4643 * Clears one physical page of a virtual handler
4644 *
4645 * @param pPGM Pointer to the PGM instance.
4646 * @param pCur Virtual handler structure
4647 * @param iPage Physical page index
4648 *
4649 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4650 * need to care about other handlers in the same page.
4651 */
4652DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4653{
4654 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4655
4656 /*
4657 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4658 */
4659#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4660 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4661 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4662 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4663#endif
4664 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4665 {
4666 /* We're the head of the alias chain. */
4667 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4668#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4669 AssertReleaseMsg(pRemove != NULL,
4670 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4671 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4672 AssertReleaseMsg(pRemove == pPhys2Virt,
4673 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4674 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4675 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4676 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4677#endif
4678 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4679 {
4680 /* Insert the next list in the alias chain into the tree. */
4681 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4682#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4683 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4684 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4685 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4686#endif
4687 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4688 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4689 AssertRelease(fRc);
4690 }
4691 }
4692 else
4693 {
4694 /* Locate the previous node in the alias chain. */
4695 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4696#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4697 AssertReleaseMsg(pPrev != pPhys2Virt,
4698 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4699 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4700#endif
4701 for (;;)
4702 {
4703 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4704 if (pNext == pPhys2Virt)
4705 {
4706 /* unlink. */
4707 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4708 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4709 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4710 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4711 else
4712 {
4713 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4714 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4715 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4716 }
4717 break;
4718 }
4719
4720 /* next */
4721 if (pNext == pPrev)
4722 {
4723#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4724 AssertReleaseMsg(pNext != pPrev,
4725 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4726 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4727#endif
4728 break;
4729 }
4730 pPrev = pNext;
4731 }
4732 }
4733 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4734 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4735 pPhys2Virt->offNextAlias = 0;
4736 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4737
4738 /*
4739 * Clear the ram flags for this page.
4740 */
4741 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4742 AssertReturnVoid(pPage);
4743 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4744}
4745
4746
4747/**
4748 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4749 *
4750 * @returns Pointer to the shadow page structure.
4751 * @param pPool The pool.
4752 * @param idx The pool page index.
4753 */
4754DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4755{
4756 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4757 return &pPool->aPages[idx];
4758}
4759
4760
4761#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4762/**
4763 * Clear references to guest physical memory.
4764 *
4765 * @param pPool The pool.
4766 * @param pPoolPage The pool page.
4767 * @param pPhysPage The physical guest page tracking structure.
4768 */
4769DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4770{
4771 /*
4772 * Just deal with the simple case here.
4773 */
4774# ifdef LOG_ENABLED
4775 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4776# endif
4777 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4778 if (cRefs == 1)
4779 {
4780 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4781 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4782 }
4783 else
4784 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4785 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4786}
4787#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4788
4789
4790#ifdef PGMPOOL_WITH_CACHE
4791/**
4792 * Moves the page to the head of the age list.
4793 *
4794 * This is done when the cached page is used in one way or another.
4795 *
4796 * @param pPool The pool.
4797 * @param pPage The cached page.
4798 */
4799DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4800{
4801 PVM pVM = pPool->CTX_SUFF(pVM);
4802 pgmLock(pVM);
4803
4804 /*
4805 * Move to the head of the age list.
4806 */
4807 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4808 {
4809 /* unlink */
4810 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4811 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4812 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4813 else
4814 pPool->iAgeTail = pPage->iAgePrev;
4815
4816 /* insert at head */
4817 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4818 pPage->iAgeNext = pPool->iAgeHead;
4819 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4820 pPool->iAgeHead = pPage->idx;
4821 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4822 }
4823 pgmUnlock(pVM);
4824}
4825#endif /* PGMPOOL_WITH_CACHE */
4826
4827/**
4828 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4829 *
4830 * @param pVM VM Handle.
4831 * @param pPage PGM pool page
4832 */
4833DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4834{
4835 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4836 ASMAtomicIncU32(&pPage->cLocked);
4837}
4838
4839
4840/**
4841 * Unlocks a page to allow flushing again
4842 *
4843 * @param pVM VM Handle.
4844 * @param pPage PGM pool page
4845 */
4846DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4847{
4848 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4849 Assert(pPage->cLocked);
4850 ASMAtomicDecU32(&pPage->cLocked);
4851}
4852
4853
4854/**
4855 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4856 *
4857 * @returns VBox status code.
4858 * @param pPage PGM pool page
4859 */
4860DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4861{
4862 if (pPage->cLocked)
4863 {
4864 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4865 if (pPage->cModifications)
4866 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4867 return true;
4868 }
4869 return false;
4870}
4871
4872/**
4873 * Tells if mappings are to be put into the shadow page table or not
4874 *
4875 * @returns boolean result
4876 * @param pVM VM handle.
4877 */
4878DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4879{
4880#ifdef IN_RING0
4881 /* There are no mappings in VT-x and AMD-V mode. */
4882 Assert(pPGM->fDisableMappings);
4883 return false;
4884#else
4885 return !pPGM->fDisableMappings;
4886#endif
4887}
4888
4889/** @} */
4890
4891#endif
4892
4893
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