VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 26638

Last change on this file since 26638 was 26625, checked in by vboxsync, 15 years ago

Large page code cleanup
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 155.5 KB
Line 
1/* $Id: PGMInternal.h 26625 2010-02-18 10:39:28Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43#include <iprt/sha.h>
44
45
46
47/** @defgroup grp_pgm_int Internals
48 * @ingroup grp_pgm
49 * @internal
50 * @{
51 */
52
53
54/** @name PGM Compile Time Config
55 * @{
56 */
57
58/**
59 * Indicates that there are no guest mappings to care about.
60 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
61 */
62#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
63# define PGM_WITHOUT_MAPPINGS
64#endif
65
66/**
67 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
68 * Comment it if it will break something.
69 */
70#define PGM_OUT_OF_SYNC_IN_GC
71
72/**
73 * Check and skip global PDEs for non-global flushes
74 */
75#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
76
77/**
78 * Optimization for PAE page tables that are modified often
79 */
80//#if 0 /* disabled again while debugging */
81#ifndef IN_RC
82# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
83#endif
84//#endif
85
86/**
87 * Sync N pages instead of a whole page table
88 */
89#define PGM_SYNC_N_PAGES
90
91/**
92 * Number of pages to sync during a page fault
93 *
94 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
95 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
96 *
97 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
98 * world switch overhead, so let's sync more.
99 */
100# ifdef IN_RING0
101/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
102 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
103 * but ~5% fewer faults.
104 */
105# define PGM_SYNC_NR_PAGES 32
106#else
107# define PGM_SYNC_NR_PAGES 8
108#endif
109
110/**
111 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
112 */
113#define PGM_MAX_PHYSCACHE_ENTRIES 64
114#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
115
116
117/** @def PGMPOOL_CFG_MAX_GROW
118 * The maximum number of pages to add to the pool in one go.
119 */
120#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
121
122/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
123 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
124 */
125#ifdef VBOX_STRICT
126# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
127#endif
128
129/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130 * Enables the experimental lazy page allocation code. */
131/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
132
133/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
134 * Enables real write monitoring of pages, i.e. mapping them read-only and
135 * only making them writable when getting a write access #PF. */
136#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
137
138/** @} */
139
140
141/** @name PDPT and PML4 flags.
142 * These are placed in the three bits available for system programs in
143 * the PDPT and PML4 entries.
144 * @{ */
145/** The entry is a permanent one and it's must always be present.
146 * Never free such an entry. */
147#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
148/** Mapping (hypervisor allocated pagetable). */
149#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
150/** @} */
151
152/** @name Page directory flags.
153 * These are placed in the three bits available for system programs in
154 * the page directory entries.
155 * @{ */
156/** Mapping (hypervisor allocated pagetable). */
157#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
158/** Made read-only to facilitate dirty bit tracking. */
159#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
160/** @} */
161
162/** @name Page flags.
163 * These are placed in the three bits available for system programs in
164 * the page entries.
165 * @{ */
166/** Made read-only to facilitate dirty bit tracking. */
167#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
168
169#ifndef PGM_PTFLAGS_CSAM_VALIDATED
170/** Scanned and approved by CSAM (tm).
171 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
172 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
173#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
174#endif
175
176/** @} */
177
178/** @name Defines used to indicate the shadow and guest paging in the templates.
179 * @{ */
180#define PGM_TYPE_REAL 1
181#define PGM_TYPE_PROT 2
182#define PGM_TYPE_32BIT 3
183#define PGM_TYPE_PAE 4
184#define PGM_TYPE_AMD64 5
185#define PGM_TYPE_NESTED 6
186#define PGM_TYPE_EPT 7
187#define PGM_TYPE_MAX PGM_TYPE_EPT
188/** @} */
189
190/** Macro for checking if the guest is using paging.
191 * @param uGstType PGM_TYPE_*
192 * @param uShwType PGM_TYPE_*
193 * @remark ASSUMES certain order of the PGM_TYPE_* values.
194 */
195#define PGM_WITH_PAGING(uGstType, uShwType) \
196 ( (uGstType) >= PGM_TYPE_32BIT \
197 && (uShwType) != PGM_TYPE_NESTED \
198 && (uShwType) != PGM_TYPE_EPT)
199
200/** Macro for checking if the guest supports the NX bit.
201 * @param uGstType PGM_TYPE_*
202 * @param uShwType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_NX(uGstType, uShwType) \
206 ( (uGstType) >= PGM_TYPE_PAE \
207 && (uShwType) != PGM_TYPE_NESTED \
208 && (uShwType) != PGM_TYPE_EPT)
209
210
211/** @def PGM_HCPHYS_2_PTR
212 * Maps a HC physical page pool address to a virtual address.
213 *
214 * @returns VBox status code.
215 * @param pVM The VM handle.
216 * @param HCPhys The HC physical address to map to a virtual one.
217 * @param ppv Where to store the virtual address. No need to cast this.
218 *
219 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
220 * small page window employeed by that function. Be careful.
221 * @remark There is no need to assert on the result.
222 */
223#ifdef IN_RC
224# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
225 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
226#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
227# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
228 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
229#else
230# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
231 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
232#endif
233
234/** @def PGM_HCPHYS_2_PTR_BY_PGM
235 * Maps a HC physical page pool address to a virtual address.
236 *
237 * @returns VBox status code.
238 * @param pPGM The PGM instance data.
239 * @param HCPhys The HC physical address to map to a virtual one.
240 * @param ppv Where to store the virtual address. No need to cast this.
241 *
242 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
243 * small page window employeed by that function. Be careful.
244 * @remark There is no need to assert on the result.
245 */
246#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
247# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
248 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
249#else
250# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
251 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
252#endif
253
254/** @def PGM_GCPHYS_2_PTR
255 * Maps a GC physical page address to a virtual address.
256 *
257 * @returns VBox status code.
258 * @param pVM The VM handle.
259 * @param GCPhys The GC physical address to map to a virtual one.
260 * @param ppv Where to store the virtual address. No need to cast this.
261 *
262 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
263 * small page window employeed by that function. Be careful.
264 * @remark There is no need to assert on the result.
265 */
266#ifdef IN_RC
267# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
268 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
269#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
270# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
271 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
272#else
273# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
274 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
275#endif
276
277/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
278 * Maps a GC physical page address to a virtual address.
279 *
280 * @returns VBox status code.
281 * @param pPGM Pointer to the PGM instance data.
282 * @param GCPhys The GC physical address to map to a virtual one.
283 * @param ppv Where to store the virtual address. No need to cast this.
284 *
285 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
286 * small page window employeed by that function. Be careful.
287 * @remark There is no need to assert on the result.
288 */
289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
290# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
291 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
292#else
293# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
294 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
295#endif
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
306 * small page window employeed by that function. Be careful.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_INVL_PG
318 * Invalidates a page.
319 *
320 * @param pVCpu The VMCPU handle.
321 * @param GCVirt The virtual address of the page to invalidate.
322 */
323#ifdef IN_RC
324# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
325#elif defined(IN_RING0)
326# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
327#else
328# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
329#endif
330
331/** @def PGM_INVL_PG_ALL_VCPU
332 * Invalidates a page on all VCPUs
333 *
334 * @param pVM The VM handle.
335 * @param GCVirt The virtual address of the page to invalidate.
336 */
337#ifdef IN_RC
338# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
339#elif defined(IN_RING0)
340# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
341#else
342# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
343#endif
344
345/** @def PGM_INVL_BIG_PG
346 * Invalidates a 4MB page directory entry.
347 *
348 * @param pVCpu The VMCPU handle.
349 * @param GCVirt The virtual address within the page directory to invalidate.
350 */
351#ifdef IN_RC
352# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
353#elif defined(IN_RING0)
354# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
355#else
356# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
357#endif
358
359/** @def PGM_INVL_VCPU_TLBS()
360 * Invalidates the TLBs of the specified VCPU
361 *
362 * @param pVCpu The VMCPU handle.
363 */
364#ifdef IN_RC
365# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
366#elif defined(IN_RING0)
367# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
368#else
369# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
370#endif
371
372/** @def PGM_INVL_ALL_VCPU_TLBS()
373 * Invalidates the TLBs of all VCPUs
374 *
375 * @param pVM The VM handle.
376 */
377#ifdef IN_RC
378# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
379#elif defined(IN_RING0)
380# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
381#else
382# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
383#endif
384
385/** Size of the GCPtrConflict array in PGMMAPPING.
386 * @remarks Must be a power of two. */
387#define PGMMAPPING_CONFLICT_MAX 8
388
389/**
390 * Structure for tracking GC Mappings.
391 *
392 * This structure is used by linked list in both GC and HC.
393 */
394typedef struct PGMMAPPING
395{
396 /** Pointer to next entry. */
397 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
398 /** Pointer to next entry. */
399 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
400 /** Pointer to next entry. */
401 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
402 /** Indicate whether this entry is finalized. */
403 bool fFinalized;
404 /** Start Virtual address. */
405 RTGCPTR GCPtr;
406 /** Last Virtual address (inclusive). */
407 RTGCPTR GCPtrLast;
408 /** Range size (bytes). */
409 RTGCPTR cb;
410 /** Pointer to relocation callback function. */
411 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
412 /** User argument to the callback. */
413 R3PTRTYPE(void *) pvUser;
414 /** Mapping description / name. For easing debugging. */
415 R3PTRTYPE(const char *) pszDesc;
416 /** Last 8 addresses that caused conflicts. */
417 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
418 /** Number of conflicts for this hypervisor mapping. */
419 uint32_t cConflicts;
420 /** Number of page tables. */
421 uint32_t cPTs;
422
423 /** Array of page table mapping data. Each entry
424 * describes one page table. The array can be longer
425 * than the declared length.
426 */
427 struct
428 {
429 /** The HC physical address of the page table. */
430 RTHCPHYS HCPhysPT;
431 /** The HC physical address of the first PAE page table. */
432 RTHCPHYS HCPhysPaePT0;
433 /** The HC physical address of the second PAE page table. */
434 RTHCPHYS HCPhysPaePT1;
435 /** The HC virtual address of the 32-bit page table. */
436 R3PTRTYPE(PX86PT) pPTR3;
437 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
438 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
439 /** The RC virtual address of the 32-bit page table. */
440 RCPTRTYPE(PX86PT) pPTRC;
441 /** The RC virtual address of the two PAE page table. */
442 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
443 /** The R0 virtual address of the 32-bit page table. */
444 R0PTRTYPE(PX86PT) pPTR0;
445 /** The R0 virtual address of the two PAE page table. */
446 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
447 } aPTs[1];
448} PGMMAPPING;
449/** Pointer to structure for tracking GC Mappings. */
450typedef struct PGMMAPPING *PPGMMAPPING;
451
452
453/**
454 * Physical page access handler structure.
455 *
456 * This is used to keep track of physical address ranges
457 * which are being monitored in some kind of way.
458 */
459typedef struct PGMPHYSHANDLER
460{
461 AVLROGCPHYSNODECORE Core;
462 /** Access type. */
463 PGMPHYSHANDLERTYPE enmType;
464 /** Number of pages to update. */
465 uint32_t cPages;
466 /** Pointer to R3 callback function. */
467 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
468 /** User argument for R3 handlers. */
469 R3PTRTYPE(void *) pvUserR3;
470 /** Pointer to R0 callback function. */
471 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
472 /** User argument for R0 handlers. */
473 R0PTRTYPE(void *) pvUserR0;
474 /** Pointer to RC callback function. */
475 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
476 /** User argument for RC handlers. */
477 RCPTRTYPE(void *) pvUserRC;
478 /** Description / Name. For easing debugging. */
479 R3PTRTYPE(const char *) pszDesc;
480#ifdef VBOX_WITH_STATISTICS
481 /** Profiling of this handler. */
482 STAMPROFILE Stat;
483#endif
484} PGMPHYSHANDLER;
485/** Pointer to a physical page access handler structure. */
486typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
487
488
489/**
490 * Cache node for the physical addresses covered by a virtual handler.
491 */
492typedef struct PGMPHYS2VIRTHANDLER
493{
494 /** Core node for the tree based on physical ranges. */
495 AVLROGCPHYSNODECORE Core;
496 /** Offset from this struct to the PGMVIRTHANDLER structure. */
497 int32_t offVirtHandler;
498 /** Offset of the next alias relative to this one.
499 * Bit 0 is used for indicating whether we're in the tree.
500 * Bit 1 is used for indicating that we're the head node.
501 */
502 int32_t offNextAlias;
503} PGMPHYS2VIRTHANDLER;
504/** Pointer to a phys to virtual handler structure. */
505typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
506
507/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
508 * node is in the tree. */
509#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
510/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
511 * node is in the head of an alias chain.
512 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
513#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
514/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
515#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
516
517
518/**
519 * Virtual page access handler structure.
520 *
521 * This is used to keep track of virtual address ranges
522 * which are being monitored in some kind of way.
523 */
524typedef struct PGMVIRTHANDLER
525{
526 /** Core node for the tree based on virtual ranges. */
527 AVLROGCPTRNODECORE Core;
528 /** Size of the range (in bytes). */
529 RTGCPTR cb;
530 /** Number of cache pages. */
531 uint32_t cPages;
532 /** Access type. */
533 PGMVIRTHANDLERTYPE enmType;
534 /** Pointer to the RC callback function. */
535 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
536#if HC_ARCH_BITS == 64
537 RTRCPTR padding;
538#endif
539 /** Pointer to the R3 callback function for invalidation. */
540 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
541 /** Pointer to the R3 callback function. */
542 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
543 /** Description / Name. For easing debugging. */
544 R3PTRTYPE(const char *) pszDesc;
545#ifdef VBOX_WITH_STATISTICS
546 /** Profiling of this handler. */
547 STAMPROFILE Stat;
548#endif
549 /** Array of cached physical addresses for the monitored ranged. */
550 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
551} PGMVIRTHANDLER;
552/** Pointer to a virtual page access handler structure. */
553typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
554
555
556/**
557 * Page type.
558 *
559 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
560 * @remarks This is used in the saved state, so changes to it requires bumping
561 * the saved state version.
562 * @todo So, convert to \#defines!
563 */
564typedef enum PGMPAGETYPE
565{
566 /** The usual invalid zero entry. */
567 PGMPAGETYPE_INVALID = 0,
568 /** RAM page. (RWX) */
569 PGMPAGETYPE_RAM,
570 /** MMIO2 page. (RWX) */
571 PGMPAGETYPE_MMIO2,
572 /** MMIO2 page aliased over an MMIO page. (RWX)
573 * See PGMHandlerPhysicalPageAlias(). */
574 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
575 /** Shadowed ROM. (RWX) */
576 PGMPAGETYPE_ROM_SHADOW,
577 /** ROM page. (R-X) */
578 PGMPAGETYPE_ROM,
579 /** MMIO page. (---) */
580 PGMPAGETYPE_MMIO,
581 /** End of valid entries. */
582 PGMPAGETYPE_END
583} PGMPAGETYPE;
584AssertCompile(PGMPAGETYPE_END <= 7);
585
586/** @name Page type predicates.
587 * @{ */
588#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
589#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
590#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
591#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
592#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
593/** @} */
594
595
596/**
597 * A Physical Guest Page tracking structure.
598 *
599 * The format of this structure is complicated because we have to fit a lot
600 * of information into as few bits as possible. The format is also subject
601 * to change (there is one comming up soon). Which means that for we'll be
602 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
603 * accesses to the structure.
604 */
605typedef struct PGMPAGE
606{
607 /** The physical address and the Page ID. */
608 RTHCPHYS HCPhysAndPageID;
609 /** Combination of:
610 * - [0-7]: u2HandlerPhysStateY - the physical handler state
611 * (PGM_PAGE_HNDL_PHYS_STATE_*).
612 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
613 * (PGM_PAGE_HNDL_VIRT_STATE_*).
614 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
615 * - [15]: fWrittenToY - flag indicating that a write monitored page was
616 * written to when set.
617 * - [10-13]: 4 unused bits.
618 * @remarks Warning! All accesses to the bits are hardcoded.
619 *
620 * @todo Change this to a union with both bitfields, u8 and u accessors.
621 * That'll help deal with some of the hardcoded accesses.
622 *
623 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
624 * will make it possible to turn some of the 16-bit accesses into
625 * 32-bit ones, which may be efficient (stalls).
626 */
627 RTUINT16U u16MiscY;
628 /** The page state.
629 * Only 2 bits are really needed for this. */
630 uint8_t uStateY;
631 /** The page type (PGMPAGETYPE).
632 * Only 3 bits are really needed for this. */
633 uint8_t uTypeY;
634 /** Usage tracking (page pool). */
635 uint16_t u16TrackingY;
636 /** The number of read locks on this page. */
637 uint8_t cReadLocksY;
638 /** The number of write locks on this page. */
639 uint8_t cWriteLocksY;
640} PGMPAGE;
641AssertCompileSize(PGMPAGE, 16);
642/** Pointer to a physical guest page. */
643typedef PGMPAGE *PPGMPAGE;
644/** Pointer to a const physical guest page. */
645typedef const PGMPAGE *PCPGMPAGE;
646/** Pointer to a physical guest page pointer. */
647typedef PPGMPAGE *PPPGMPAGE;
648
649
650/**
651 * Clears the page structure.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_CLEAR(pPage) \
655 do { \
656 (pPage)->HCPhysAndPageID = 0; \
657 (pPage)->uStateY = 0; \
658 (pPage)->uTypeY = 0; \
659 (pPage)->u16MiscY.u = 0; \
660 (pPage)->u16TrackingY = 0; \
661 (pPage)->cReadLocksY = 0; \
662 (pPage)->cWriteLocksY = 0; \
663 } while (0)
664
665/**
666 * Initializes the page structure.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670 do { \
671 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
672 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
673 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
674 (pPage)->uStateY = (_uState); \
675 (pPage)->uTypeY = (_uType); \
676 (pPage)->u16MiscY.u = 0; \
677 (pPage)->u16TrackingY = 0; \
678 (pPage)->cReadLocksY = 0; \
679 (pPage)->cWriteLocksY = 0; \
680 } while (0)
681
682/**
683 * Initializes the page structure of a ZERO page.
684 * @param pPage Pointer to the physical guest page tracking structure.
685 * @param pVM The VM handle (for getting the zero page address).
686 * @param uType The page type (PGMPAGETYPE).
687 */
688#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
689 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
690
691
692/** @name The Page state, PGMPAGE::uStateY.
693 * @{ */
694/** The zero page.
695 * This is a per-VM page that's never ever mapped writable. */
696#define PGM_PAGE_STATE_ZERO 0
697/** A allocated page.
698 * This is a per-VM page allocated from the page pool (or wherever
699 * we get MMIO2 pages from if the type is MMIO2).
700 */
701#define PGM_PAGE_STATE_ALLOCATED 1
702/** A allocated page that's being monitored for writes.
703 * The shadow page table mappings are read-only. When a write occurs, the
704 * fWrittenTo member is set, the page remapped as read-write and the state
705 * moved back to allocated. */
706#define PGM_PAGE_STATE_WRITE_MONITORED 2
707/** The page is shared, aka. copy-on-write.
708 * This is a page that's shared with other VMs. */
709#define PGM_PAGE_STATE_SHARED 3
710/** @} */
711
712
713/**
714 * Gets the page state.
715 * @returns page state (PGM_PAGE_STATE_*).
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
719
720/**
721 * Sets the page state.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 * @param _uState The new page state.
724 */
725#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
726
727
728/**
729 * Gets the host physical address of the guest page.
730 * @returns host physical address (RTHCPHYS).
731 * @param pPage Pointer to the physical guest page tracking structure.
732 */
733#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
734
735/**
736 * Sets the host physical address of the guest page.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 * @param _HCPhys The new host physical address.
739 */
740#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
741 do { \
742 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
743 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
744 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
745 | (SetHCPhysTmp << (28-12)); \
746 } while (0)
747
748/**
749 * Get the Page ID.
750 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
754
755/**
756 * Sets the Page ID.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
760 do { \
761 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
762 | ((_idPage) & UINT32_C(0x0fffffff)); \
763 } while (0)
764
765/**
766 * Get the Chunk ID.
767 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
768 * @param pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
771
772/**
773 * Get the index of the page within the allocation chunk.
774 * @returns The page index.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 */
777#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
778
779/**
780 * Gets the page type.
781 * @returns The page type.
782 * @param pPage Pointer to the physical guest page tracking structure.
783 */
784#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
785
786/**
787 * Sets the page type.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 * @param _enmType The new page type (PGMPAGETYPE).
790 */
791#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
792
793/**
794 * Checks if the page is marked for MMIO.
795 * @returns true/false.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
799
800/**
801 * Checks if the page is backed by the ZERO page.
802 * @returns true/false.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
806
807/**
808 * Checks if the page is backed by a SHARED page.
809 * @returns true/false.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
813
814
815/**
816 * Marks the page as written to (for GMM change monitoring).
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
820
821/**
822 * Clears the written-to indicator.
823 * @param pPage Pointer to the physical guest page tracking structure.
824 */
825#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
826
827/**
828 * Checks if the page was marked as written-to.
829 * @returns true/false.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 */
832#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
833
834/** @name PT usage values (PGMPAGE::u2PDEType).
835 *
836 * @{ */
837/** Either as a PT or PDE. */
838#define PGM_PAGE_PDE_TYPE_DONTCARE 0
839/** Must use a page table to map the range. */
840#define PGM_PAGE_PDE_TYPE_PT 1
841/** Can use a page directory entry to map the continous range. */
842#define PGM_PAGE_PDE_TYPE_PDE 2
843/** @} */
844
845/**
846 * Set the PDE type of the page
847 * @param pPage Pointer to the physical guest page tracking structure.
848 * @param uType PGM_PAGE_PDE_TYPE_*
849 */
850#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
851 do { \
852 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
853 | (((uType) & UINT8_C(0x03)) << 5); \
854 } while (0)
855
856/**
857 * Checks if the page was marked being part of a large page
858 * @returns true/false.
859 * @param pPage Pointer to the physical guest page tracking structure.
860 */
861#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
862
863/** Enabled optimized access handler tests.
864 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
865 * layout. When enabled, the compiler should normally generate more compact
866 * code.
867 */
868#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
869
870/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
871 *
872 * @remarks The values are assigned in order of priority, so we can calculate
873 * the correct state for a page with different handlers installed.
874 * @{ */
875/** No handler installed. */
876#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
877/** Monitoring is temporarily disabled. */
878#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
879/** Write access is monitored. */
880#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
881/** All access is monitored. */
882#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
883/** @} */
884
885/**
886 * Gets the physical access handler state of a page.
887 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
891 ( (pPage)->u16MiscY.au8[0] )
892
893/**
894 * Sets the physical access handler state of a page.
895 * @param pPage Pointer to the physical guest page tracking structure.
896 * @param _uState The new state value.
897 */
898#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
899 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
900
901/**
902 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
903 * @returns true/false
904 * @param pPage Pointer to the physical guest page tracking structure.
905 */
906#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
907 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
908
909/**
910 * Checks if the page has any active physical access handlers.
911 * @returns true/false
912 * @param pPage Pointer to the physical guest page tracking structure.
913 */
914#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
915 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
916
917
918/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
919 *
920 * @remarks The values are assigned in order of priority, so we can calculate
921 * the correct state for a page with different handlers installed.
922 * @{ */
923/** No handler installed. */
924#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
925/* 1 is reserved so the lineup is identical with the physical ones. */
926/** Write access is monitored. */
927#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
928/** All access is monitored. */
929#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
930/** @} */
931
932/**
933 * Gets the virtual access handler state of a page.
934 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
938
939/**
940 * Sets the virtual access handler state of a page.
941 * @param pPage Pointer to the physical guest page tracking structure.
942 * @param _uState The new state value.
943 */
944#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
945 do { \
946 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
947 | ((_uState) & UINT8_C(0x03)); \
948 } while (0)
949
950/**
951 * Checks if the page has any virtual access handlers.
952 * @returns true/false
953 * @param pPage Pointer to the physical guest page tracking structure.
954 */
955#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
956 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
957
958/**
959 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
960 * virtual handlers.
961 * @returns true/false
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
965 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
966
967
968/**
969 * Checks if the page has any access handlers, including temporarily disabled ones.
970 * @returns true/false
971 * @param pPage Pointer to the physical guest page tracking structure.
972 */
973#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
974# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
975 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
976#else
977# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
978 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
979 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
980#endif
981
982/**
983 * Checks if the page has any active access handlers.
984 * @returns true/false
985 * @param pPage Pointer to the physical guest page tracking structure.
986 */
987#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
988# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
989 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
990#else
991# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
992 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
993 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
994#endif
995
996/**
997 * Checks if the page has any active access handlers catching all accesses.
998 * @returns true/false
999 * @param pPage Pointer to the physical guest page tracking structure.
1000 */
1001#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1002# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1003 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1004 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1005#else
1006# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1007 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1008 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1009#endif
1010
1011
1012/** @def PGM_PAGE_GET_TRACKING
1013 * Gets the packed shadow page pool tracking data associated with a guest page.
1014 * @returns uint16_t containing the data.
1015 * @param pPage Pointer to the physical guest page tracking structure.
1016 */
1017#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1018
1019/** @def PGM_PAGE_SET_TRACKING
1020 * Sets the packed shadow page pool tracking data associated with a guest page.
1021 * @param pPage Pointer to the physical guest page tracking structure.
1022 * @param u16TrackingData The tracking data to store.
1023 */
1024#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1025 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1026
1027/** @def PGM_PAGE_GET_TD_CREFS
1028 * Gets the @a cRefs tracking data member.
1029 * @returns cRefs.
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#define PGM_PAGE_GET_TD_CREFS(pPage) \
1033 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1034
1035/** @def PGM_PAGE_GET_TD_IDX
1036 * Gets the @a idx tracking data member.
1037 * @returns idx.
1038 * @param pPage Pointer to the physical guest page tracking structure.
1039 */
1040#define PGM_PAGE_GET_TD_IDX(pPage) \
1041 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1042
1043
1044/** Max number of locks on a page. */
1045#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1046
1047/** Get the read lock count.
1048 * @returns count.
1049 * @param pPage Pointer to the physical guest page tracking structure.
1050 */
1051#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1052
1053/** Get the write lock count.
1054 * @returns count.
1055 * @param pPage Pointer to the physical guest page tracking structure.
1056 */
1057#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1058
1059/** Decrement the read lock counter.
1060 * @param pPage Pointer to the physical guest page tracking structure.
1061 */
1062#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1063
1064/** Decrement the write lock counter.
1065 * @param pPage Pointer to the physical guest page tracking structure.
1066 */
1067#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1068
1069/** Increment the read lock counter.
1070 * @param pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1073
1074/** Increment the write lock counter.
1075 * @param pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1078
1079
1080#if 0
1081/** Enables sanity checking of write monitoring using CRC-32. */
1082# define PGMLIVESAVERAMPAGE_WITH_CRC32
1083#endif
1084
1085/**
1086 * Per page live save tracking data.
1087 */
1088typedef struct PGMLIVESAVERAMPAGE
1089{
1090 /** Number of times it has been dirtied. */
1091 uint32_t cDirtied : 24;
1092 /** Whether it is currently dirty. */
1093 uint32_t fDirty : 1;
1094 /** Ignore the page.
1095 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1096 * deal with these after pausing the VM and DevPCI have said it bit about
1097 * remappings. */
1098 uint32_t fIgnore : 1;
1099 /** Was a ZERO page last time around. */
1100 uint32_t fZero : 1;
1101 /** Was a SHARED page last time around. */
1102 uint32_t fShared : 1;
1103 /** Whether the page is/was write monitored in a previous pass. */
1104 uint32_t fWriteMonitored : 1;
1105 /** Whether the page is/was write monitored earlier in this pass. */
1106 uint32_t fWriteMonitoredJustNow : 1;
1107 /** Bits reserved for future use. */
1108 uint32_t u2Reserved : 2;
1109#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1110 /** CRC-32 for the page. This is for internal consistency checks. */
1111 uint32_t u32Crc;
1112#endif
1113} PGMLIVESAVERAMPAGE;
1114#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1115AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1116#else
1117AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1118#endif
1119/** Pointer to the per page live save tracking data. */
1120typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1121
1122/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1123#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1124
1125
1126/**
1127 * Ram range for GC Phys to HC Phys conversion.
1128 *
1129 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1130 * conversions too, but we'll let MM handle that for now.
1131 *
1132 * This structure is used by linked lists in both GC and HC.
1133 */
1134typedef struct PGMRAMRANGE
1135{
1136 /** Start of the range. Page aligned. */
1137 RTGCPHYS GCPhys;
1138 /** Size of the range. (Page aligned of course). */
1139 RTGCPHYS cb;
1140 /** Pointer to the next RAM range - for R3. */
1141 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1142 /** Pointer to the next RAM range - for R0. */
1143 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1144 /** Pointer to the next RAM range - for RC. */
1145 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1146 /** PGM_RAM_RANGE_FLAGS_* flags. */
1147 uint32_t fFlags;
1148 /** Last address in the range (inclusive). Page aligned (-1). */
1149 RTGCPHYS GCPhysLast;
1150 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1151 R3PTRTYPE(void *) pvR3;
1152 /** Live save per page tracking data. */
1153 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1154 /** The range description. */
1155 R3PTRTYPE(const char *) pszDesc;
1156 /** Pointer to self - R0 pointer. */
1157 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1158 /** Pointer to self - RC pointer. */
1159 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1160 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1161 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1162 /** Array of physical guest page tracking structures. */
1163 PGMPAGE aPages[1];
1164} PGMRAMRANGE;
1165/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1166typedef PGMRAMRANGE *PPGMRAMRANGE;
1167
1168/** @name PGMRAMRANGE::fFlags
1169 * @{ */
1170/** The RAM range is floating around as an independent guest mapping. */
1171#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1172/** Ad hoc RAM range for an ROM mapping. */
1173#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1174/** Ad hoc RAM range for an MMIO mapping. */
1175#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1176/** Ad hoc RAM range for an MMIO2 mapping. */
1177#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1178/** @} */
1179
1180/** Tests if a RAM range is an ad hoc one or not.
1181 * @returns true/false.
1182 * @param pRam The RAM range.
1183 */
1184#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1185 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1186
1187
1188/**
1189 * Per page tracking structure for ROM image.
1190 *
1191 * A ROM image may have a shadow page, in which case we may have two pages
1192 * backing it. This structure contains the PGMPAGE for both while
1193 * PGMRAMRANGE have a copy of the active one. It is important that these
1194 * aren't out of sync in any regard other than page pool tracking data.
1195 */
1196typedef struct PGMROMPAGE
1197{
1198 /** The page structure for the virgin ROM page. */
1199 PGMPAGE Virgin;
1200 /** The page structure for the shadow RAM page. */
1201 PGMPAGE Shadow;
1202 /** The current protection setting. */
1203 PGMROMPROT enmProt;
1204 /** Live save status information. Makes use of unused alignment space. */
1205 struct
1206 {
1207 /** The previous protection value. */
1208 uint8_t u8Prot;
1209 /** Written to flag set by the handler. */
1210 bool fWrittenTo;
1211 /** Whether the shadow page is dirty or not. */
1212 bool fDirty;
1213 /** Whether it was dirtied in the recently. */
1214 bool fDirtiedRecently;
1215 } LiveSave;
1216} PGMROMPAGE;
1217AssertCompileSizeAlignment(PGMROMPAGE, 8);
1218/** Pointer to a ROM page tracking structure. */
1219typedef PGMROMPAGE *PPGMROMPAGE;
1220
1221
1222/**
1223 * A registered ROM image.
1224 *
1225 * This is needed to keep track of ROM image since they generally intrude
1226 * into a PGMRAMRANGE. It also keeps track of additional info like the
1227 * two page sets (read-only virgin and read-write shadow), the current
1228 * state of each page.
1229 *
1230 * Because access handlers cannot easily be executed in a different
1231 * context, the ROM ranges needs to be accessible and in all contexts.
1232 */
1233typedef struct PGMROMRANGE
1234{
1235 /** Pointer to the next range - R3. */
1236 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1237 /** Pointer to the next range - R0. */
1238 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1239 /** Pointer to the next range - RC. */
1240 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1241 /** Pointer alignment */
1242 RTRCPTR RCPtrAlignment;
1243 /** Address of the range. */
1244 RTGCPHYS GCPhys;
1245 /** Address of the last byte in the range. */
1246 RTGCPHYS GCPhysLast;
1247 /** Size of the range. */
1248 RTGCPHYS cb;
1249 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1250 uint32_t fFlags;
1251 /** The saved state range ID. */
1252 uint8_t idSavedState;
1253 /** Alignment padding. */
1254 uint8_t au8Alignment[3];
1255 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1256 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1257 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1258 * This is used for strictness checks. */
1259 R3PTRTYPE(const void *) pvOriginal;
1260 /** The ROM description. */
1261 R3PTRTYPE(const char *) pszDesc;
1262 /** The per page tracking structures. */
1263 PGMROMPAGE aPages[1];
1264} PGMROMRANGE;
1265/** Pointer to a ROM range. */
1266typedef PGMROMRANGE *PPGMROMRANGE;
1267
1268
1269/**
1270 * Live save per page data for an MMIO2 page.
1271 *
1272 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1273 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1274 * CRC-32 for detecting changes as well as special handling of zero pages. This
1275 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1276 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1277 * because of speed (2.5x and 6x slower).)
1278 *
1279 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1280 * save but normally is disabled. Since we can write monitore guest
1281 * accesses on our own, we only need this for host accesses. Shouldn't be
1282 * too difficult for DevVGA, VMMDev might be doable, the planned
1283 * networking fun will be fun since it involves ring-0.
1284 */
1285typedef struct PGMLIVESAVEMMIO2PAGE
1286{
1287 /** Set if the page is considered dirty. */
1288 bool fDirty;
1289 /** The number of scans this page has remained unchanged for.
1290 * Only updated for dirty pages. */
1291 uint8_t cUnchangedScans;
1292 /** Whether this page was zero at the last scan. */
1293 bool fZero;
1294 /** Alignment padding. */
1295 bool fReserved;
1296 /** CRC-32 for the first half of the page.
1297 * This is used together with u32CrcH2 to quickly detect changes in the page
1298 * during the non-final passes. */
1299 uint32_t u32CrcH1;
1300 /** CRC-32 for the second half of the page. */
1301 uint32_t u32CrcH2;
1302 /** SHA-1 for the saved page.
1303 * This is used in the final pass to skip pages without changes. */
1304 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1305} PGMLIVESAVEMMIO2PAGE;
1306/** Pointer to a live save status data for an MMIO2 page. */
1307typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1308
1309/**
1310 * A registered MMIO2 (= Device RAM) range.
1311 *
1312 * There are a few reason why we need to keep track of these
1313 * registrations. One of them is the deregistration & cleanup stuff,
1314 * while another is that the PGMRAMRANGE associated with such a region may
1315 * have to be removed from the ram range list.
1316 *
1317 * Overlapping with a RAM range has to be 100% or none at all. The pages
1318 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1319 * will be raised if a partial overlap or an overlap of ROM pages is
1320 * encountered. On an overlap we will free all the existing RAM pages and
1321 * put in the ram range pages instead.
1322 */
1323typedef struct PGMMMIO2RANGE
1324{
1325 /** The owner of the range. (a device) */
1326 PPDMDEVINSR3 pDevInsR3;
1327 /** Pointer to the ring-3 mapping of the allocation. */
1328 RTR3PTR pvR3;
1329 /** Pointer to the next range - R3. */
1330 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1331 /** Whether it's mapped or not. */
1332 bool fMapped;
1333 /** Whether it's overlapping or not. */
1334 bool fOverlapping;
1335 /** The PCI region number.
1336 * @remarks This ASSUMES that nobody will ever really need to have multiple
1337 * PCI devices with matching MMIO region numbers on a single device. */
1338 uint8_t iRegion;
1339 /** The saved state range ID. */
1340 uint8_t idSavedState;
1341 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1342 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1343 /** Live save per page tracking data. */
1344 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1345 /** The associated RAM range. */
1346 PGMRAMRANGE RamRange;
1347} PGMMMIO2RANGE;
1348/** Pointer to a MMIO2 range. */
1349typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1350
1351
1352
1353
1354/**
1355 * PGMPhysRead/Write cache entry
1356 */
1357typedef struct PGMPHYSCACHEENTRY
1358{
1359 /** R3 pointer to physical page. */
1360 R3PTRTYPE(uint8_t *) pbR3;
1361 /** GC Physical address for cache entry */
1362 RTGCPHYS GCPhys;
1363#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1364 RTGCPHYS u32Padding0; /**< alignment padding. */
1365#endif
1366} PGMPHYSCACHEENTRY;
1367
1368/**
1369 * PGMPhysRead/Write cache to reduce REM memory access overhead
1370 */
1371typedef struct PGMPHYSCACHE
1372{
1373 /** Bitmap of valid cache entries */
1374 uint64_t aEntries;
1375 /** Cache entries */
1376 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1377} PGMPHYSCACHE;
1378
1379
1380/** Pointer to an allocation chunk ring-3 mapping. */
1381typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1382/** Pointer to an allocation chunk ring-3 mapping pointer. */
1383typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1384
1385/**
1386 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1387 *
1388 * The primary tree (Core) uses the chunk id as key.
1389 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1390 */
1391typedef struct PGMCHUNKR3MAP
1392{
1393 /** The key is the chunk id. */
1394 AVLU32NODECORE Core;
1395 /** The key is the ageing sequence number. */
1396 AVLLU32NODECORE AgeCore;
1397 /** The current age thingy. */
1398 uint32_t iAge;
1399 /** The current reference count. */
1400 uint32_t volatile cRefs;
1401 /** The current permanent reference count. */
1402 uint32_t volatile cPermRefs;
1403 /** The mapping address. */
1404 void *pv;
1405} PGMCHUNKR3MAP;
1406
1407/**
1408 * Allocation chunk ring-3 mapping TLB entry.
1409 */
1410typedef struct PGMCHUNKR3MAPTLBE
1411{
1412 /** The chunk id. */
1413 uint32_t volatile idChunk;
1414#if HC_ARCH_BITS == 64
1415 uint32_t u32Padding; /**< alignment padding. */
1416#endif
1417 /** The chunk map. */
1418#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1419 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1420#else
1421 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1422#endif
1423} PGMCHUNKR3MAPTLBE;
1424/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1425typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1426
1427/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1428 * @remark Must be a power of two value. */
1429#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1430
1431/**
1432 * Allocation chunk ring-3 mapping TLB.
1433 *
1434 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1435 * At first glance this might look kinda odd since AVL trees are
1436 * supposed to give the most optimial lookup times of all trees
1437 * due to their balancing. However, take a tree with 1023 nodes
1438 * in it, that's 10 levels, meaning that most searches has to go
1439 * down 9 levels before they find what they want. This isn't fast
1440 * compared to a TLB hit. There is the factor of cache misses,
1441 * and of course the problem with trees and branch prediction.
1442 * This is why we use TLBs in front of most of the trees.
1443 *
1444 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1445 * difficult when we switch to the new inlined AVL trees (from kStuff).
1446 */
1447typedef struct PGMCHUNKR3MAPTLB
1448{
1449 /** The TLB entries. */
1450 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1451} PGMCHUNKR3MAPTLB;
1452
1453/**
1454 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1455 * @returns Chunk TLB index.
1456 * @param idChunk The Chunk ID.
1457 */
1458#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1459
1460
1461/**
1462 * Ring-3 guest page mapping TLB entry.
1463 * @remarks used in ring-0 as well at the moment.
1464 */
1465typedef struct PGMPAGER3MAPTLBE
1466{
1467 /** Address of the page. */
1468 RTGCPHYS volatile GCPhys;
1469 /** The guest page. */
1470#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1471 R3PTRTYPE(PPGMPAGE) volatile pPage;
1472#else
1473 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1474#endif
1475 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1476#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1477 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1478#else
1479 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1480#endif
1481 /** The address */
1482#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1483 R3PTRTYPE(void *) volatile pv;
1484#else
1485 R3R0PTRTYPE(void *) volatile pv;
1486#endif
1487#if HC_ARCH_BITS == 32
1488 uint32_t u32Padding; /**< alignment padding. */
1489#endif
1490} PGMPAGER3MAPTLBE;
1491/** Pointer to an entry in the HC physical TLB. */
1492typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1493
1494
1495/** The number of entries in the ring-3 guest page mapping TLB.
1496 * @remarks The value must be a power of two. */
1497#define PGM_PAGER3MAPTLB_ENTRIES 256
1498
1499/**
1500 * Ring-3 guest page mapping TLB.
1501 * @remarks used in ring-0 as well at the moment.
1502 */
1503typedef struct PGMPAGER3MAPTLB
1504{
1505 /** The TLB entries. */
1506 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1507} PGMPAGER3MAPTLB;
1508/** Pointer to the ring-3 guest page mapping TLB. */
1509typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1510
1511/**
1512 * Calculates the index of the TLB entry for the specified guest page.
1513 * @returns Physical TLB index.
1514 * @param GCPhys The guest physical address.
1515 */
1516#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1517
1518
1519/**
1520 * Mapping cache usage set entry.
1521 *
1522 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1523 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1524 * cache. If it's extended to include ring-3, well, then something will
1525 * have be changed here...
1526 */
1527typedef struct PGMMAPSETENTRY
1528{
1529 /** The mapping cache index. */
1530 uint16_t iPage;
1531 /** The number of references.
1532 * The max is UINT16_MAX - 1. */
1533 uint16_t cRefs;
1534#if HC_ARCH_BITS == 64
1535 uint32_t alignment;
1536#endif
1537 /** Pointer to the page. */
1538 RTR0PTR pvPage;
1539 /** The physical address for this entry. */
1540 RTHCPHYS HCPhys;
1541} PGMMAPSETENTRY;
1542/** Pointer to a mapping cache usage set entry. */
1543typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1544
1545/**
1546 * Mapping cache usage set.
1547 *
1548 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1549 * done during exits / traps. The set is
1550 */
1551typedef struct PGMMAPSET
1552{
1553 /** The number of occupied entries.
1554 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1555 * dynamic mappings. */
1556 uint32_t cEntries;
1557 /** The start of the current subset.
1558 * This is UINT32_MAX if no subset is currently open. */
1559 uint32_t iSubset;
1560 /** The index of the current CPU, only valid if the set is open. */
1561 int32_t iCpu;
1562 uint32_t alignment;
1563 /** The entries. */
1564 PGMMAPSETENTRY aEntries[64];
1565 /** HCPhys -> iEntry fast lookup table.
1566 * Use PGMMAPSET_HASH for hashing.
1567 * The entries may or may not be valid, check against cEntries. */
1568 uint8_t aiHashTable[128];
1569} PGMMAPSET;
1570AssertCompileSizeAlignment(PGMMAPSET, 8);
1571/** Pointer to the mapping cache set. */
1572typedef PGMMAPSET *PPGMMAPSET;
1573
1574/** PGMMAPSET::cEntries value for a closed set. */
1575#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1576
1577/** Hash function for aiHashTable. */
1578#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1579
1580/** The max fill size (strict builds). */
1581#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1582
1583
1584/** @name Context neutrual page mapper TLB.
1585 *
1586 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1587 * code is writting in a kind of context neutrual way. Time will show whether
1588 * this actually makes sense or not...
1589 *
1590 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1591 * context ends up using a global mapping cache on some platforms
1592 * (darwin).
1593 *
1594 * @{ */
1595/** @typedef PPGMPAGEMAPTLB
1596 * The page mapper TLB pointer type for the current context. */
1597/** @typedef PPGMPAGEMAPTLB
1598 * The page mapper TLB entry pointer type for the current context. */
1599/** @typedef PPGMPAGEMAPTLB
1600 * The page mapper TLB entry pointer pointer type for the current context. */
1601/** @def PGM_PAGEMAPTLB_ENTRIES
1602 * The number of TLB entries in the page mapper TLB for the current context. */
1603/** @def PGM_PAGEMAPTLB_IDX
1604 * Calculate the TLB index for a guest physical address.
1605 * @returns The TLB index.
1606 * @param GCPhys The guest physical address. */
1607/** @typedef PPGMPAGEMAP
1608 * Pointer to a page mapper unit for current context. */
1609/** @typedef PPPGMPAGEMAP
1610 * Pointer to a page mapper unit pointer for current context. */
1611#ifdef IN_RC
1612// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1613// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1614// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1615# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1616# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1617 typedef void * PPGMPAGEMAP;
1618 typedef void ** PPPGMPAGEMAP;
1619//#elif IN_RING0
1620// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1621// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1622// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1623//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1624//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1625// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1626// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1627#else
1628 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1629 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1630 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1631# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1632# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1633 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1634 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1635#endif
1636/** @} */
1637
1638
1639/** @name PGM Pool Indexes.
1640 * Aka. the unique shadow page identifier.
1641 * @{ */
1642/** NIL page pool IDX. */
1643#define NIL_PGMPOOL_IDX 0
1644/** The first normal index. */
1645#define PGMPOOL_IDX_FIRST_SPECIAL 1
1646/** Page directory (32-bit root). */
1647#define PGMPOOL_IDX_PD 1
1648/** Page Directory Pointer Table (PAE root). */
1649#define PGMPOOL_IDX_PDPT 2
1650/** AMD64 CR3 level index.*/
1651#define PGMPOOL_IDX_AMD64_CR3 3
1652/** Nested paging root.*/
1653#define PGMPOOL_IDX_NESTED_ROOT 4
1654/** The first normal index. */
1655#define PGMPOOL_IDX_FIRST 5
1656/** The last valid index. (inclusive, 14 bits) */
1657#define PGMPOOL_IDX_LAST 0x3fff
1658/** @} */
1659
1660/** The NIL index for the parent chain. */
1661#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1662#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1663
1664/**
1665 * Node in the chain linking a shadowed page to it's parent (user).
1666 */
1667#pragma pack(1)
1668typedef struct PGMPOOLUSER
1669{
1670 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1671 uint16_t iNext;
1672 /** The user page index. */
1673 uint16_t iUser;
1674 /** Index into the user table. */
1675 uint32_t iUserTable;
1676} PGMPOOLUSER, *PPGMPOOLUSER;
1677typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1678#pragma pack()
1679
1680
1681/** The NIL index for the phys ext chain. */
1682#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1683
1684/**
1685 * Node in the chain of physical cross reference extents.
1686 * @todo Calling this an 'extent' is not quite right, find a better name.
1687 */
1688#pragma pack(1)
1689typedef struct PGMPOOLPHYSEXT
1690{
1691 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1692 uint16_t iNext;
1693 /** The user page index. */
1694 uint16_t aidx[3];
1695} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1696typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1697#pragma pack()
1698
1699
1700/**
1701 * The kind of page that's being shadowed.
1702 */
1703typedef enum PGMPOOLKIND
1704{
1705 /** The virtual invalid 0 entry. */
1706 PGMPOOLKIND_INVALID = 0,
1707 /** The entry is free (=unused). */
1708 PGMPOOLKIND_FREE,
1709
1710 /** Shw: 32-bit page table; Gst: no paging */
1711 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1712 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1713 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1714 /** Shw: 32-bit page table; Gst: 4MB page. */
1715 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1716 /** Shw: PAE page table; Gst: no paging */
1717 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1718 /** Shw: PAE page table; Gst: 32-bit page table. */
1719 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1720 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1721 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1722 /** Shw: PAE page table; Gst: PAE page table. */
1723 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1724 /** Shw: PAE page table; Gst: 2MB page. */
1725 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1726
1727 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1728 PGMPOOLKIND_32BIT_PD,
1729 /** Shw: 32-bit page directory. Gst: no paging. */
1730 PGMPOOLKIND_32BIT_PD_PHYS,
1731 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1732 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1733 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1734 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1735 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1736 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1737 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1738 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1739 /** Shw: PAE page directory; Gst: PAE page directory. */
1740 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1741 /** Shw: PAE page directory; Gst: no paging. */
1742 PGMPOOLKIND_PAE_PD_PHYS,
1743
1744 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1745 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1746 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1747 PGMPOOLKIND_PAE_PDPT,
1748 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1749 PGMPOOLKIND_PAE_PDPT_PHYS,
1750
1751 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1752 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1753 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1754 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1755 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1756 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1757 /** Shw: 64-bit page directory table; Gst: no paging */
1758 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1759
1760 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1761 PGMPOOLKIND_64BIT_PML4,
1762
1763 /** Shw: EPT page directory pointer table; Gst: no paging */
1764 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1765 /** Shw: EPT page directory table; Gst: no paging */
1766 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1767 /** Shw: EPT page table; Gst: no paging */
1768 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1769
1770 /** Shw: Root Nested paging table. */
1771 PGMPOOLKIND_ROOT_NESTED,
1772
1773 /** The last valid entry. */
1774 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1775} PGMPOOLKIND;
1776
1777/**
1778 * The access attributes of the page; only applies to big pages.
1779 */
1780typedef enum
1781{
1782 PGMPOOLACCESS_DONTCARE = 0,
1783 PGMPOOLACCESS_USER_RW,
1784 PGMPOOLACCESS_USER_R,
1785 PGMPOOLACCESS_USER_RW_NX,
1786 PGMPOOLACCESS_USER_R_NX,
1787 PGMPOOLACCESS_SUPERVISOR_RW,
1788 PGMPOOLACCESS_SUPERVISOR_R,
1789 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1790 PGMPOOLACCESS_SUPERVISOR_R_NX
1791} PGMPOOLACCESS;
1792
1793/**
1794 * The tracking data for a page in the pool.
1795 */
1796typedef struct PGMPOOLPAGE
1797{
1798 /** AVL node code with the (R3) physical address of this page. */
1799 AVLOHCPHYSNODECORE Core;
1800 /** Pointer to the R3 mapping of the page. */
1801#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1802 R3PTRTYPE(void *) pvPageR3;
1803#else
1804 R3R0PTRTYPE(void *) pvPageR3;
1805#endif
1806 /** The guest physical address. */
1807#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1808 uint32_t Alignment0;
1809#endif
1810 RTGCPHYS GCPhys;
1811
1812 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1813 RTGCPTR pvLastAccessHandlerRip;
1814 RTGCPTR pvLastAccessHandlerFault;
1815 uint64_t cLastAccessHandlerCount;
1816
1817 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1818 uint8_t enmKind;
1819 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1820 uint8_t enmAccess;
1821 /** The index of this page. */
1822 uint16_t idx;
1823 /** The next entry in the list this page currently resides in.
1824 * It's either in the free list or in the GCPhys hash. */
1825 uint16_t iNext;
1826 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1827 uint16_t iUserHead;
1828 /** The number of present entries. */
1829 uint16_t cPresent;
1830 /** The first entry in the table which is present. */
1831 uint16_t iFirstPresent;
1832 /** The number of modifications to the monitored page. */
1833 uint16_t cModifications;
1834 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1835 uint16_t iModifiedNext;
1836 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1837 uint16_t iModifiedPrev;
1838 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1839 uint16_t iMonitoredNext;
1840 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1841 uint16_t iMonitoredPrev;
1842 /** The next page in the age list. */
1843 uint16_t iAgeNext;
1844 /** The previous page in the age list. */
1845 uint16_t iAgePrev;
1846 /** Used to indicate that the page is zeroed. */
1847 bool fZeroed;
1848 /** Used to indicate that a PT has non-global entries. */
1849 bool fSeenNonGlobal;
1850 /** Used to indicate that we're monitoring writes to the guest page. */
1851 bool fMonitored;
1852 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1853 * (All pages are in the age list.) */
1854 bool fCached;
1855 /** This is used by the R3 access handlers when invoked by an async thread.
1856 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1857 bool volatile fReusedFlushPending;
1858 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1859 bool fDirty;
1860
1861 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1862 uint32_t cLocked;
1863 uint32_t idxDirty;
1864 RTGCPTR pvDirtyFault;
1865} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1866/** Pointer to a const pool page. */
1867typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1868
1869
1870/** The hash table size. */
1871# define PGMPOOL_HASH_SIZE 0x40
1872/** The hash function. */
1873# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1874
1875
1876/**
1877 * The shadow page pool instance data.
1878 *
1879 * It's all one big allocation made at init time, except for the
1880 * pages that is. The user nodes follows immediatly after the
1881 * page structures.
1882 */
1883typedef struct PGMPOOL
1884{
1885 /** The VM handle - R3 Ptr. */
1886 PVMR3 pVMR3;
1887 /** The VM handle - R0 Ptr. */
1888 PVMR0 pVMR0;
1889 /** The VM handle - RC Ptr. */
1890 PVMRC pVMRC;
1891 /** The max pool size. This includes the special IDs. */
1892 uint16_t cMaxPages;
1893 /** The current pool size. */
1894 uint16_t cCurPages;
1895 /** The head of the free page list. */
1896 uint16_t iFreeHead;
1897 /* Padding. */
1898 uint16_t u16Padding;
1899 /** Head of the chain of free user nodes. */
1900 uint16_t iUserFreeHead;
1901 /** The number of user nodes we've allocated. */
1902 uint16_t cMaxUsers;
1903 /** The number of present page table entries in the entire pool. */
1904 uint32_t cPresent;
1905 /** Pointer to the array of user nodes - RC pointer. */
1906 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1907 /** Pointer to the array of user nodes - R3 pointer. */
1908 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1909 /** Pointer to the array of user nodes - R0 pointer. */
1910 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1911 /** Head of the chain of free phys ext nodes. */
1912 uint16_t iPhysExtFreeHead;
1913 /** The number of user nodes we've allocated. */
1914 uint16_t cMaxPhysExts;
1915 /** Pointer to the array of physical xref extent - RC pointer. */
1916 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1917 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1918 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1919 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1920 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1921 /** Hash table for GCPhys addresses. */
1922 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1923 /** The head of the age list. */
1924 uint16_t iAgeHead;
1925 /** The tail of the age list. */
1926 uint16_t iAgeTail;
1927 /** Set if the cache is enabled. */
1928 bool fCacheEnabled;
1929 /** Alignment padding. */
1930 bool afPadding1[3];
1931 /** Head of the list of modified pages. */
1932 uint16_t iModifiedHead;
1933 /** The current number of modified pages. */
1934 uint16_t cModifiedPages;
1935 /** Access handler, RC. */
1936 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1937 /** Access handler, R0. */
1938 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1939 /** Access handler, R3. */
1940 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1941 /** The access handler description (R3 ptr). */
1942 R3PTRTYPE(const char *) pszAccessHandler;
1943# if HC_ARCH_BITS == 32
1944 /** Alignment padding. */
1945 uint32_t u32Padding2;
1946# endif
1947 /* Next available slot. */
1948 uint32_t idxFreeDirtyPage;
1949 /* Number of active dirty pages. */
1950 uint32_t cDirtyPages;
1951 /* Array of current dirty pgm pool page indices. */
1952 uint16_t aIdxDirtyPages[16];
1953 uint64_t aDirtyPages[16][512];
1954 /** The number of pages currently in use. */
1955 uint16_t cUsedPages;
1956#ifdef VBOX_WITH_STATISTICS
1957 /** The high water mark for cUsedPages. */
1958 uint16_t cUsedPagesHigh;
1959 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1960 /** Profiling pgmPoolAlloc(). */
1961 STAMPROFILEADV StatAlloc;
1962 /** Profiling pgmR3PoolClearDoIt(). */
1963 STAMPROFILE StatClearAll;
1964 /** Profiling pgmR3PoolReset(). */
1965 STAMPROFILE StatR3Reset;
1966 /** Profiling pgmPoolFlushPage(). */
1967 STAMPROFILE StatFlushPage;
1968 /** Profiling pgmPoolFree(). */
1969 STAMPROFILE StatFree;
1970 /** Counting explicit flushes by PGMPoolFlushPage(). */
1971 STAMCOUNTER StatForceFlushPage;
1972 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1973 STAMCOUNTER StatForceFlushDirtyPage;
1974 /** Counting flushes for reused pages. */
1975 STAMCOUNTER StatForceFlushReused;
1976 /** Profiling time spent zeroing pages. */
1977 STAMPROFILE StatZeroPage;
1978 /** Profiling of pgmPoolTrackDeref. */
1979 STAMPROFILE StatTrackDeref;
1980 /** Profiling pgmTrackFlushGCPhysPT. */
1981 STAMPROFILE StatTrackFlushGCPhysPT;
1982 /** Profiling pgmTrackFlushGCPhysPTs. */
1983 STAMPROFILE StatTrackFlushGCPhysPTs;
1984 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1985 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1986 /** Number of times we've been out of user records. */
1987 STAMCOUNTER StatTrackFreeUpOneUser;
1988 /** Nr of flushed entries. */
1989 STAMCOUNTER StatTrackFlushEntry;
1990 /** Nr of updated entries. */
1991 STAMCOUNTER StatTrackFlushEntryKeep;
1992 /** Profiling deref activity related tracking GC physical pages. */
1993 STAMPROFILE StatTrackDerefGCPhys;
1994 /** Number of linear searches for a HCPhys in the ram ranges. */
1995 STAMCOUNTER StatTrackLinearRamSearches;
1996 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1997 STAMCOUNTER StamTrackPhysExtAllocFailures;
1998 /** Profiling the RC/R0 access handler. */
1999 STAMPROFILE StatMonitorRZ;
2000 /** Times we've failed interpreting the instruction. */
2001 STAMCOUNTER StatMonitorRZEmulateInstr;
2002 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2003 STAMPROFILE StatMonitorRZFlushPage;
2004 /* Times we've detected a page table reinit. */
2005 STAMCOUNTER StatMonitorRZFlushReinit;
2006 /** Counting flushes for pages that are modified too often. */
2007 STAMCOUNTER StatMonitorRZFlushModOverflow;
2008 /** Times we've detected fork(). */
2009 STAMCOUNTER StatMonitorRZFork;
2010 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2011 STAMPROFILE StatMonitorRZHandled;
2012 /** Times we've failed interpreting a patch code instruction. */
2013 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2014 /** Times we've failed interpreting a patch code instruction during flushing. */
2015 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2016 /** The number of times we've seen rep prefixes we can't handle. */
2017 STAMCOUNTER StatMonitorRZRepPrefix;
2018 /** Profiling the REP STOSD cases we've handled. */
2019 STAMPROFILE StatMonitorRZRepStosd;
2020 /** Nr of handled PT faults. */
2021 STAMCOUNTER StatMonitorRZFaultPT;
2022 /** Nr of handled PD faults. */
2023 STAMCOUNTER StatMonitorRZFaultPD;
2024 /** Nr of handled PDPT faults. */
2025 STAMCOUNTER StatMonitorRZFaultPDPT;
2026 /** Nr of handled PML4 faults. */
2027 STAMCOUNTER StatMonitorRZFaultPML4;
2028
2029 /** Profiling the R3 access handler. */
2030 STAMPROFILE StatMonitorR3;
2031 /** Times we've failed interpreting the instruction. */
2032 STAMCOUNTER StatMonitorR3EmulateInstr;
2033 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2034 STAMPROFILE StatMonitorR3FlushPage;
2035 /* Times we've detected a page table reinit. */
2036 STAMCOUNTER StatMonitorR3FlushReinit;
2037 /** Counting flushes for pages that are modified too often. */
2038 STAMCOUNTER StatMonitorR3FlushModOverflow;
2039 /** Times we've detected fork(). */
2040 STAMCOUNTER StatMonitorR3Fork;
2041 /** Profiling the R3 access we've handled (except REP STOSD). */
2042 STAMPROFILE StatMonitorR3Handled;
2043 /** The number of times we've seen rep prefixes we can't handle. */
2044 STAMCOUNTER StatMonitorR3RepPrefix;
2045 /** Profiling the REP STOSD cases we've handled. */
2046 STAMPROFILE StatMonitorR3RepStosd;
2047 /** Nr of handled PT faults. */
2048 STAMCOUNTER StatMonitorR3FaultPT;
2049 /** Nr of handled PD faults. */
2050 STAMCOUNTER StatMonitorR3FaultPD;
2051 /** Nr of handled PDPT faults. */
2052 STAMCOUNTER StatMonitorR3FaultPDPT;
2053 /** Nr of handled PML4 faults. */
2054 STAMCOUNTER StatMonitorR3FaultPML4;
2055 /** The number of times we're called in an async thread an need to flush. */
2056 STAMCOUNTER StatMonitorR3Async;
2057 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2058 STAMCOUNTER StatResetDirtyPages;
2059 /** Times we've called pgmPoolAddDirtyPage. */
2060 STAMCOUNTER StatDirtyPage;
2061 /** Times we've had to flush duplicates for dirty page management. */
2062 STAMCOUNTER StatDirtyPageDupFlush;
2063 /** Times we've had to flush because of overflow. */
2064 STAMCOUNTER StatDirtyPageOverFlowFlush;
2065
2066 /** The high wather mark for cModifiedPages. */
2067 uint16_t cModifiedPagesHigh;
2068 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2069
2070 /** The number of cache hits. */
2071 STAMCOUNTER StatCacheHits;
2072 /** The number of cache misses. */
2073 STAMCOUNTER StatCacheMisses;
2074 /** The number of times we've got a conflict of 'kind' in the cache. */
2075 STAMCOUNTER StatCacheKindMismatches;
2076 /** Number of times we've been out of pages. */
2077 STAMCOUNTER StatCacheFreeUpOne;
2078 /** The number of cacheable allocations. */
2079 STAMCOUNTER StatCacheCacheable;
2080 /** The number of uncacheable allocations. */
2081 STAMCOUNTER StatCacheUncacheable;
2082#else
2083 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2084#endif
2085 /** The AVL tree for looking up a page by its HC physical address. */
2086 AVLOHCPHYSTREE HCPhysTree;
2087 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2088 /** Array of pages. (cMaxPages in length)
2089 * The Id is the index into thist array.
2090 */
2091 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2092} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2093AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2094AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2095AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2096#ifdef VBOX_WITH_STATISTICS
2097AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2098#endif
2099AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2100
2101
2102/** @def PGMPOOL_PAGE_2_PTR
2103 * Maps a pool page pool into the current context.
2104 *
2105 * @returns VBox status code.
2106 * @param pVM The VM handle.
2107 * @param pPage The pool page.
2108 *
2109 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2110 * small page window employeed by that function. Be careful.
2111 * @remark There is no need to assert on the result.
2112 */
2113#if defined(IN_RC)
2114# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2115#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2116# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2117#elif defined(VBOX_STRICT)
2118# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2119DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2120{
2121 Assert(pPage && pPage->pvPageR3);
2122 return pPage->pvPageR3;
2123}
2124#else
2125# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2126#endif
2127
2128/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2129 * Maps a pool page pool into the current context.
2130 *
2131 * @returns VBox status code.
2132 * @param pPGM Pointer to the PGM instance data.
2133 * @param pPage The pool page.
2134 *
2135 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2136 * small page window employeed by that function. Be careful.
2137 * @remark There is no need to assert on the result.
2138 */
2139#if defined(IN_RC)
2140# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2141#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2142# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2143#else
2144# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2145#endif
2146
2147/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2148 * Maps a pool page pool into the current context.
2149 *
2150 * @returns VBox status code.
2151 * @param pPGM Pointer to the PGMCPU instance data.
2152 * @param pPage The pool page.
2153 *
2154 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2155 * small page window employeed by that function. Be careful.
2156 * @remark There is no need to assert on the result.
2157 */
2158#if defined(IN_RC)
2159# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2160#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2161# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2162#else
2163# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2164#endif
2165
2166
2167/** @name Per guest page tracking data.
2168 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2169 * is to use more bits for it and split it up later on. But for now we'll play
2170 * safe and change as little as possible.
2171 *
2172 * The 16-bit word has two parts:
2173 *
2174 * The first 14-bit forms the @a idx field. It is either the index of a page in
2175 * the shadow page pool, or and index into the extent list.
2176 *
2177 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2178 * shadow page pool references to the page. If cRefs equals
2179 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2180 * (misnomer) table and not the shadow page pool.
2181 *
2182 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2183 * the 16-bit word.
2184 *
2185 * @{ */
2186/** The shift count for getting to the cRefs part. */
2187#define PGMPOOL_TD_CREFS_SHIFT 14
2188/** The mask applied after shifting the tracking data down by
2189 * PGMPOOL_TD_CREFS_SHIFT. */
2190#define PGMPOOL_TD_CREFS_MASK 0x3
2191/** The cRef value used to indiciate that the idx is the head of a
2192 * physical cross reference list. */
2193#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2194/** The shift used to get idx. */
2195#define PGMPOOL_TD_IDX_SHIFT 0
2196/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2197#define PGMPOOL_TD_IDX_MASK 0x3fff
2198/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2199 * simply too many mappings of this page. */
2200#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2201
2202/** @def PGMPOOL_TD_MAKE
2203 * Makes a 16-bit tracking data word.
2204 *
2205 * @returns tracking data.
2206 * @param cRefs The @a cRefs field. Must be within bounds!
2207 * @param idx The @a idx field. Must also be within bounds! */
2208#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2209
2210/** @def PGMPOOL_TD_GET_CREFS
2211 * Get the @a cRefs field from a tracking data word.
2212 *
2213 * @returns The @a cRefs field
2214 * @param u16 The tracking data word. */
2215#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2216
2217/** @def PGMPOOL_TD_GET_IDX
2218 * Get the @a idx field from a tracking data word.
2219 *
2220 * @returns The @a idx field
2221 * @param u16 The tracking data word. */
2222#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2223/** @} */
2224
2225
2226/**
2227 * Trees are using self relative offsets as pointers.
2228 * So, all its data, including the root pointer, must be in the heap for HC and GC
2229 * to have the same layout.
2230 */
2231typedef struct PGMTREES
2232{
2233 /** Physical access handlers (AVL range+offsetptr tree). */
2234 AVLROGCPHYSTREE PhysHandlers;
2235 /** Virtual access handlers (AVL range + GC ptr tree). */
2236 AVLROGCPTRTREE VirtHandlers;
2237 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2238 AVLROGCPHYSTREE PhysToVirtHandlers;
2239 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2240 AVLROGCPTRTREE HyperVirtHandlers;
2241} PGMTREES;
2242/** Pointer to PGM trees. */
2243typedef PGMTREES *PPGMTREES;
2244
2245
2246/** @name Paging mode macros
2247 * @{ */
2248#ifdef IN_RC
2249# define PGM_CTX(a,b) a##RC##b
2250# define PGM_CTX_STR(a,b) a "GC" b
2251# define PGM_CTX_DECL(type) VMMRCDECL(type)
2252#else
2253# ifdef IN_RING3
2254# define PGM_CTX(a,b) a##R3##b
2255# define PGM_CTX_STR(a,b) a "R3" b
2256# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2257# else
2258# define PGM_CTX(a,b) a##R0##b
2259# define PGM_CTX_STR(a,b) a "R0" b
2260# define PGM_CTX_DECL(type) VMMDECL(type)
2261# endif
2262#endif
2263
2264#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2265#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2266#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2267#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2268#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2269#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2270#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2271#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2272#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2273#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2274#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2275#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2276#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2277#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2278#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2279#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2280#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2281
2282#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2283#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2284#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2285#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2286#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2287#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2288#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2289#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2290#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2291#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2292#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2293#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2294#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2295#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2296#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2297#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2298#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2299
2300/* Shw_Gst */
2301#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2302#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2303#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2304#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2305#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2306#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2307#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2308#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2309#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2310#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2311#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2312#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2313#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2314#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2315#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2316#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2317#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2318#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2319#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2320
2321#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2322#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2323#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2324#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2325#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2326#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2327#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2328#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2329#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2330#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2331#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2332#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2333#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2334#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2335#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2336#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2337#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2338#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2339#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2340#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2341#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2342#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2343#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2344#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2345#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2346#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2347#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2348#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2349#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2350#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2351#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2352#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2353#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2354#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2355#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2356#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2357#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2358
2359#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2360#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2361/** @} */
2362
2363/**
2364 * Data for each paging mode.
2365 */
2366typedef struct PGMMODEDATA
2367{
2368 /** The guest mode type. */
2369 uint32_t uGstType;
2370 /** The shadow mode type. */
2371 uint32_t uShwType;
2372
2373 /** @name Function pointers for Shadow paging.
2374 * @{
2375 */
2376 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2377 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2378 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2379 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2380
2381 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2382 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2383
2384 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2385 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2386 /** @} */
2387
2388 /** @name Function pointers for Guest paging.
2389 * @{
2390 */
2391 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2392 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2393 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2394 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2395 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2396 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2397 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2398 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2399 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2400 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2401 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2402 /** @} */
2403
2404 /** @name Function pointers for Both Shadow and Guest paging.
2405 * @{
2406 */
2407 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2408 /* no pfnR3BthTrap0eHandler */
2409 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2410 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2411 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2412 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2413 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2414#ifdef VBOX_STRICT
2415 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2416#endif
2417 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2418 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2419
2420 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2421 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2422 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2423 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2424 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2425 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2426#ifdef VBOX_STRICT
2427 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2428#endif
2429 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2430 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2431
2432 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2433 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2434 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2435 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2436 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2437 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2438#ifdef VBOX_STRICT
2439 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2440#endif
2441 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2442 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2443 /** @} */
2444} PGMMODEDATA, *PPGMMODEDATA;
2445
2446
2447
2448/**
2449 * Converts a PGM pointer into a VM pointer.
2450 * @returns Pointer to the VM structure the PGM is part of.
2451 * @param pPGM Pointer to PGM instance data.
2452 */
2453#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2454
2455/**
2456 * PGM Data (part of VM)
2457 */
2458typedef struct PGM
2459{
2460 /** Offset to the VM structure. */
2461 RTINT offVM;
2462 /** Offset of the PGMCPU structure relative to VMCPU. */
2463 RTINT offVCpuPGM;
2464
2465 /** @cfgm{RamPreAlloc, boolean, false}
2466 * Indicates whether the base RAM should all be allocated before starting
2467 * the VM (default), or if it should be allocated when first written to.
2468 */
2469 bool fRamPreAlloc;
2470 /** Indicates whether write monitoring is currently in use.
2471 * This is used to prevent conflicts between live saving and page sharing
2472 * detection. */
2473 bool fPhysWriteMonitoringEngaged;
2474 /** Alignment padding. */
2475 bool afAlignment0[2];
2476
2477 /*
2478 * This will be redefined at least two more times before we're done, I'm sure.
2479 * The current code is only to get on with the coding.
2480 * - 2004-06-10: initial version, bird.
2481 * - 2004-07-02: 1st time, bird.
2482 * - 2004-10-18: 2nd time, bird.
2483 * - 2005-07-xx: 3rd time, bird.
2484 */
2485
2486 /** The host paging mode. (This is what SUPLib reports.) */
2487 SUPPAGINGMODE enmHostMode;
2488
2489 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2490 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2491 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2492 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2493
2494 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2495 RTGCPHYS GCPhys4MBPSEMask;
2496
2497 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2498 * This is sorted by physical address and contains no overlapping ranges. */
2499 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2500 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2501 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2502 /** RC pointer corresponding to PGM::pRamRangesR3. */
2503 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2504 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2505 * range is linked or unlinked. */
2506 uint32_t volatile idRamRangesGen;
2507
2508 /** Pointer to the list of ROM ranges - for R3.
2509 * This is sorted by physical address and contains no overlapping ranges. */
2510 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2511 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2512 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2513 /** RC pointer corresponding to PGM::pRomRangesR3. */
2514 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2515#if HC_ARCH_BITS == 64
2516 /** Alignment padding. */
2517 RTRCPTR GCPtrPadding2;
2518#endif
2519
2520 /** Pointer to the list of MMIO2 ranges - for R3.
2521 * Registration order. */
2522 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2523
2524 /** PGM offset based trees - R3 Ptr. */
2525 R3PTRTYPE(PPGMTREES) pTreesR3;
2526 /** PGM offset based trees - R0 Ptr. */
2527 R0PTRTYPE(PPGMTREES) pTreesR0;
2528 /** PGM offset based trees - RC Ptr. */
2529 RCPTRTYPE(PPGMTREES) pTreesRC;
2530
2531 /** Linked list of GC mappings - for RC.
2532 * The list is sorted ascending on address.
2533 */
2534 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2535 /** Linked list of GC mappings - for HC.
2536 * The list is sorted ascending on address.
2537 */
2538 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2539 /** Linked list of GC mappings - for R0.
2540 * The list is sorted ascending on address.
2541 */
2542 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2543
2544 /** Pointer to the 5 page CR3 content mapping.
2545 * The first page is always the CR3 (in some form) while the 4 other pages
2546 * are used of the PDs in PAE mode. */
2547 RTGCPTR GCPtrCR3Mapping;
2548#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2549 uint32_t u32Alignment1;
2550#endif
2551
2552 /** Indicates that PGMR3FinalizeMappings has been called and that further
2553 * PGMR3MapIntermediate calls will be rejected. */
2554 bool fFinalizedMappings;
2555 /** If set no conflict checks are required. */
2556 bool fMappingsFixed;
2557 /** If set if restored as fixed but we were unable to re-fixate at the old
2558 * location because of room or address incompatibilities. */
2559 bool fMappingsFixedRestored;
2560 /** If set, then no mappings are put into the shadow page table.
2561 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2562 bool fMappingsDisabled;
2563 /** Size of fixed mapping.
2564 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2565 uint32_t cbMappingFixed;
2566 /** Base address (GC) of fixed mapping.
2567 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2568 RTGCPTR GCPtrMappingFixed;
2569 /** The address of the previous RAM range mapping. */
2570 RTGCPTR GCPtrPrevRamRangeMapping;
2571
2572 /** @name Intermediate Context
2573 * @{ */
2574 /** Pointer to the intermediate page directory - Normal. */
2575 R3PTRTYPE(PX86PD) pInterPD;
2576 /** Pointer to the intermedate page tables - Normal.
2577 * There are two page tables, one for the identity mapping and one for
2578 * the host context mapping (of the core code). */
2579 R3PTRTYPE(PX86PT) apInterPTs[2];
2580 /** Pointer to the intermedate page tables - PAE. */
2581 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2582 /** Pointer to the intermedate page directory - PAE. */
2583 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2584 /** Pointer to the intermedate page directory - PAE. */
2585 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2586 /** Pointer to the intermedate page-map level 4 - AMD64. */
2587 R3PTRTYPE(PX86PML4) pInterPaePML4;
2588 /** Pointer to the intermedate page directory - AMD64. */
2589 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2590 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2591 RTHCPHYS HCPhysInterPD;
2592 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2593 RTHCPHYS HCPhysInterPaePDPT;
2594 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2595 RTHCPHYS HCPhysInterPaePML4;
2596 /** @} */
2597
2598 /** Base address of the dynamic page mapping area.
2599 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2600 */
2601 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2602 /** The index of the last entry used in the dynamic page mapping area. */
2603 RTUINT iDynPageMapLast;
2604 /** Cache containing the last entries in the dynamic page mapping area.
2605 * The cache size is covering half of the mapping area. */
2606 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2607 /** Keep a lock counter for the full (!) mapping area. */
2608 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2609
2610 /** The address of the ring-0 mapping cache if we're making use of it. */
2611 RTR0PTR pvR0DynMapUsed;
2612#if HC_ARCH_BITS == 32
2613 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2614 uint32_t u32Alignment2;
2615#endif
2616
2617 /** PGM critical section.
2618 * This protects the physical & virtual access handlers, ram ranges,
2619 * and the page flag updating (some of it anyway).
2620 */
2621 PDMCRITSECT CritSect;
2622
2623 /** Pointer to SHW+GST mode data (function pointers).
2624 * The index into this table is made up from */
2625 R3PTRTYPE(PPGMMODEDATA) paModeData;
2626
2627 /** Shadow Page Pool - R3 Ptr. */
2628 R3PTRTYPE(PPGMPOOL) pPoolR3;
2629 /** Shadow Page Pool - R0 Ptr. */
2630 R0PTRTYPE(PPGMPOOL) pPoolR0;
2631 /** Shadow Page Pool - RC Ptr. */
2632 RCPTRTYPE(PPGMPOOL) pPoolRC;
2633
2634 /** We're not in a state which permits writes to guest memory.
2635 * (Only used in strict builds.) */
2636 bool fNoMorePhysWrites;
2637 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2638 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2639
2640 /**
2641 * Data associated with managing the ring-3 mappings of the allocation chunks.
2642 */
2643 struct
2644 {
2645 /** The chunk tree, ordered by chunk id. */
2646#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2647 R3PTRTYPE(PAVLU32NODECORE) pTree;
2648#else
2649 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2650#endif
2651 /** The chunk age tree, ordered by ageing sequence number. */
2652 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2653 /** The chunk mapping TLB. */
2654 PGMCHUNKR3MAPTLB Tlb;
2655 /** The number of mapped chunks. */
2656 uint32_t c;
2657 /** The maximum number of mapped chunks.
2658 * @cfgm PGM/MaxRing3Chunks */
2659 uint32_t cMax;
2660 /** The current time. */
2661 uint32_t iNow;
2662 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2663 uint32_t AgeingCountdown;
2664 } ChunkR3Map;
2665
2666 /**
2667 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2668 */
2669 PGMPAGER3MAPTLB PhysTlbHC;
2670
2671 /** @name The zero page.
2672 * @{ */
2673 /** The host physical address of the zero page. */
2674 RTHCPHYS HCPhysZeroPg;
2675 /** The ring-3 mapping of the zero page. */
2676 RTR3PTR pvZeroPgR3;
2677 /** The ring-0 mapping of the zero page. */
2678 RTR0PTR pvZeroPgR0;
2679 /** The GC mapping of the zero page. */
2680 RTGCPTR pvZeroPgRC;
2681 /** @}*/
2682
2683 /** The number of handy pages. */
2684 uint32_t cHandyPages;
2685
2686 /** The number of large handy pages. */
2687 uint32_t cLargeHandyPages;
2688
2689 /**
2690 * Array of handy pages.
2691 *
2692 * This array is used in a two way communication between pgmPhysAllocPage
2693 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2694 * an intermediary.
2695 *
2696 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2697 * (The current size of 32 pages, means 128 KB of handy memory.)
2698 */
2699 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2700
2701 /**
2702 * Array of large handy pages. (currently size 1)
2703 *
2704 * This array is used in a two way communication between pgmPhysAllocLargePage
2705 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2706 * an intermediary.
2707 */
2708 GMMPAGEDESC aLargeHandyPage[1];
2709
2710 /**
2711 * Live save data.
2712 */
2713 struct
2714 {
2715 /** Per type statistics. */
2716 struct
2717 {
2718 /** The number of ready pages. */
2719 uint32_t cReadyPages;
2720 /** The number of dirty pages. */
2721 uint32_t cDirtyPages;
2722 /** The number of ready zero pages. */
2723 uint32_t cZeroPages;
2724 /** The number of write monitored pages. */
2725 uint32_t cMonitoredPages;
2726 } Rom,
2727 Mmio2,
2728 Ram;
2729 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2730 uint32_t cIgnoredPages;
2731 /** Indicates that a live save operation is active. */
2732 bool fActive;
2733 /** Padding. */
2734 bool afReserved[2];
2735 /** The next history index. */
2736 uint8_t iDirtyPagesHistory;
2737 /** History of the total amount of dirty pages. */
2738 uint32_t acDirtyPagesHistory[64];
2739 /** Short term dirty page average. */
2740 uint32_t cDirtyPagesShort;
2741 /** Long term dirty page average. */
2742 uint32_t cDirtyPagesLong;
2743 /** The number of saved pages. This is used to get some kind of estimate of the
2744 * link speed so we can decide when we're done. It is reset after the first
2745 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2746 * zero pages. */
2747 uint64_t cSavedPages;
2748 /** The nanosecond timestamp when cSavedPages was 0. */
2749 uint64_t uSaveStartNS;
2750 /** Pages per second (for statistics). */
2751 uint32_t cPagesPerSecond;
2752 uint32_t cAlignment;
2753 } LiveSave;
2754
2755 /** @name Error injection.
2756 * @{ */
2757 /** Inject handy page allocation errors pretending we're completely out of
2758 * memory. */
2759 bool volatile fErrInjHandyPages;
2760 /** Padding. */
2761 bool afReserved[3];
2762 /** @} */
2763
2764 /** @name Release Statistics
2765 * @{ */
2766 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2767 uint32_t cPrivatePages; /**< The number of private pages. */
2768 uint32_t cSharedPages; /**< The number of shared pages. */
2769 uint32_t cZeroPages; /**< The number of zero backed pages. */
2770 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2771 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2772 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2773 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2774 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2775
2776 /** The number of times we were forced to change the hypervisor region location. */
2777 STAMCOUNTER cRelocations;
2778 /** @} */
2779
2780#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2781 STAMCOUNTER StatLargePageUsed; /**< The number of large pages we've used.*/
2782 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2783
2784 /* R3 only: */
2785 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2786 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2787
2788 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2789 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2790 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2791 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2792 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2793 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2794 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2795 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2796 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2797 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2798 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2799 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2800 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2801 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2802 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2803 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2804 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2805 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2806 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2807 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2808/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2809 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2810 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2811/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2812
2813 /* RC only: */
2814 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2815 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2816 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2817 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2818
2819 STAMCOUNTER StatRZPhysRead;
2820 STAMCOUNTER StatRZPhysReadBytes;
2821 STAMCOUNTER StatRZPhysWrite;
2822 STAMCOUNTER StatRZPhysWriteBytes;
2823 STAMCOUNTER StatR3PhysRead;
2824 STAMCOUNTER StatR3PhysReadBytes;
2825 STAMCOUNTER StatR3PhysWrite;
2826 STAMCOUNTER StatR3PhysWriteBytes;
2827 STAMCOUNTER StatRCPhysRead;
2828 STAMCOUNTER StatRCPhysReadBytes;
2829 STAMCOUNTER StatRCPhysWrite;
2830 STAMCOUNTER StatRCPhysWriteBytes;
2831
2832 STAMCOUNTER StatRZPhysSimpleRead;
2833 STAMCOUNTER StatRZPhysSimpleReadBytes;
2834 STAMCOUNTER StatRZPhysSimpleWrite;
2835 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2836 STAMCOUNTER StatR3PhysSimpleRead;
2837 STAMCOUNTER StatR3PhysSimpleReadBytes;
2838 STAMCOUNTER StatR3PhysSimpleWrite;
2839 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2840 STAMCOUNTER StatRCPhysSimpleRead;
2841 STAMCOUNTER StatRCPhysSimpleReadBytes;
2842 STAMCOUNTER StatRCPhysSimpleWrite;
2843 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2844
2845 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2846 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2847 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2848 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2849 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2850 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2851#endif
2852} PGM;
2853#ifndef IN_TSTVMSTRUCTGC /* HACK */
2854AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2855AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2856AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2857AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2858AssertCompileMemberAlignment(PGM, CritSect, 8);
2859AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2860AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2861AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2862AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2863AssertCompileMemberAlignment(PGM, cRelocations, 8);
2864#endif /* !IN_TSTVMSTRUCTGC */
2865/** Pointer to the PGM instance data. */
2866typedef PGM *PPGM;
2867
2868
2869/**
2870 * Converts a PGMCPU pointer into a VM pointer.
2871 * @returns Pointer to the VM structure the PGM is part of.
2872 * @param pPGM Pointer to PGMCPU instance data.
2873 */
2874#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2875
2876/**
2877 * Converts a PGMCPU pointer into a PGM pointer.
2878 * @returns Pointer to the VM structure the PGM is part of.
2879 * @param pPGM Pointer to PGMCPU instance data.
2880 */
2881#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2882
2883/**
2884 * PGMCPU Data (part of VMCPU).
2885 */
2886typedef struct PGMCPU
2887{
2888 /** Offset to the VM structure. */
2889 RTINT offVM;
2890 /** Offset to the VMCPU structure. */
2891 RTINT offVCpu;
2892 /** Offset of the PGM structure relative to VMCPU. */
2893 RTINT offPGM;
2894 RTINT uPadding0; /**< structure size alignment. */
2895
2896#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2897 /** Automatically tracked physical memory mapping set.
2898 * Ring-0 and strict raw-mode builds. */
2899 PGMMAPSET AutoSet;
2900#endif
2901
2902 /** A20 gate mask.
2903 * Our current approach to A20 emulation is to let REM do it and don't bother
2904 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2905 * But whould need arrise, we'll subject physical addresses to this mask. */
2906 RTGCPHYS GCPhysA20Mask;
2907 /** A20 gate state - boolean! */
2908 bool fA20Enabled;
2909
2910 /** What needs syncing (PGM_SYNC_*).
2911 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2912 * PGMFlushTLB, and PGMR3Load. */
2913 RTUINT fSyncFlags;
2914
2915 /** The shadow paging mode. */
2916 PGMMODE enmShadowMode;
2917 /** The guest paging mode. */
2918 PGMMODE enmGuestMode;
2919
2920 /** The current physical address representing in the guest CR3 register. */
2921 RTGCPHYS GCPhysCR3;
2922
2923 /** @name 32-bit Guest Paging.
2924 * @{ */
2925 /** The guest's page directory, R3 pointer. */
2926 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2927#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2928 /** The guest's page directory, R0 pointer. */
2929 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2930#endif
2931 /** The guest's page directory, static RC mapping. */
2932 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2933 /** @} */
2934
2935 /** @name PAE Guest Paging.
2936 * @{ */
2937 /** The guest's page directory pointer table, static RC mapping. */
2938 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2939 /** The guest's page directory pointer table, R3 pointer. */
2940 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2941#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2942 /** The guest's page directory pointer table, R0 pointer. */
2943 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2944#endif
2945
2946 /** The guest's page directories, R3 pointers.
2947 * These are individual pointers and don't have to be adjecent.
2948 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2949 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2950 /** The guest's page directories, R0 pointers.
2951 * Same restrictions as apGstPaePDsR3. */
2952#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2953 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2954#endif
2955 /** The guest's page directories, static GC mapping.
2956 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2957 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2958 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2959 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2960 RTGCPHYS aGCPhysGstPaePDs[4];
2961 /** The physical addresses of the monitored guest page directories (PAE). */
2962 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2963 /** @} */
2964
2965 /** @name AMD64 Guest Paging.
2966 * @{ */
2967 /** The guest's page directory pointer table, R3 pointer. */
2968 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2969#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2970 /** The guest's page directory pointer table, R0 pointer. */
2971 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2972#else
2973 RTR0PTR alignment6b; /**< alignment equalizer. */
2974#endif
2975 /** @} */
2976
2977 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2978 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2979 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2980 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2981 /** Pointer to the page of the current active CR3 - RC Ptr. */
2982 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2983 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2984 uint32_t iShwUser;
2985 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2986 uint32_t iShwUserTable;
2987# if HC_ARCH_BITS == 64
2988 RTRCPTR alignment6; /**< structure size alignment. */
2989# endif
2990 /** @} */
2991
2992 /** @name Function pointers for Shadow paging.
2993 * @{
2994 */
2995 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2996 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2997 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2998 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2999
3000 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3001 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3002
3003 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3004 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3005
3006 /** @} */
3007
3008 /** @name Function pointers for Guest paging.
3009 * @{
3010 */
3011 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3012 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3013 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3014 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3015 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3016 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3017 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3018 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3019#if HC_ARCH_BITS == 64
3020 RTRCPTR alignment3; /**< structure size alignment. */
3021#endif
3022
3023 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3024 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3025 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3026 /** @} */
3027
3028 /** @name Function pointers for Both Shadow and Guest paging.
3029 * @{
3030 */
3031 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3032 /* no pfnR3BthTrap0eHandler */
3033 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3034 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3035 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3036 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3037 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3038 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3039 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3040 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3041
3042 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3043 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3044 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3045 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3046 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3047 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3048 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3049 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3050 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3051
3052 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3053 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3054 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3055 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3056 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3057 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3058 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3059 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3060 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3061 RTRCPTR alignment2; /**< structure size alignment. */
3062 /** @} */
3063
3064 /** For saving stack space, the disassembler state is allocated here instead of
3065 * on the stack.
3066 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3067 union
3068 {
3069 /** The disassembler scratch space. */
3070 DISCPUSTATE DisState;
3071 /** Padding. */
3072 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3073 };
3074
3075 /* Count the number of pgm pool access handler calls. */
3076 uint64_t cPoolAccessHandler;
3077
3078 /** @name Release Statistics
3079 * @{ */
3080 /** The number of times the guest has switched mode since last reset or statistics reset. */
3081 STAMCOUNTER cGuestModeChanges;
3082 /** @} */
3083
3084#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3085 /** @name Statistics
3086 * @{ */
3087 /** RC: Which statistic this \#PF should be attributed to. */
3088 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3089 RTRCPTR padding0;
3090 /** R0: Which statistic this \#PF should be attributed to. */
3091 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3092 RTR0PTR padding1;
3093
3094 /* Common */
3095 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3096 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3097
3098 /* R0 only: */
3099 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3100 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3101 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3102 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3103 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3104 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3105 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3106 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3107 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3108 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3109 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3110 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3111 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3112 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3113 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3114 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3115 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3116 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3117 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3118 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3119 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3120 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3121 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3122 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3123 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3124 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3125
3126 /* RZ only: */
3127 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3128 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3129 STAMPROFILE StatRZTrap0eTimeSyncPT;
3130 STAMPROFILE StatRZTrap0eTimeMapping;
3131 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3132 STAMPROFILE StatRZTrap0eTimeHandlers;
3133 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3134 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3135 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3136 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3137 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3138 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3139 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3140 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3141 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3142 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3143 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3144 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3145 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3146 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3147 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3148 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3149 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3150 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3151 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3152 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3153 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3154 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3155 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3156 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3157 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3158 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3159 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3160 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3161 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3162 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3163 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3164 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3165 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3166 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3167 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3168 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3169 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3170 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3171 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3172 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3173 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3174 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3175 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3176
3177 /* HC - R3 and (maybe) R0: */
3178
3179 /* RZ & R3: */
3180 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3181 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3182 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3183 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3184 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3185 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3186 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3187 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3188 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3189 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3190 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3191 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3192 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3193 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3194 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3195 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3196 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3197 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3198 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3199 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3200 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3201 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3202 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3203 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3204 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3205 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3206 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3207 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3208 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3209 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3210 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3211 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3212 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3213 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3214 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3215 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3216 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3217 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3218 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3219 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3220 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3221 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3222 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3223 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3224 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3225 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3226
3227 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3228 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3229 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3230 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3231 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3232 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3233 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3234 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3235 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3236 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3237 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3238 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3239 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3240 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3241 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3242 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3243 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3244 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3245 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3246 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3247 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3248 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3249 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3250 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3251 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3252 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3253 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3254 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3255 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3256 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3257 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3258 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3259 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3260 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3261 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3262 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3263 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3264 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3265 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3266 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3267 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3268 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3269 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3270 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3271 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3272 /** @} */
3273#endif /* VBOX_WITH_STATISTICS */
3274} PGMCPU;
3275/** Pointer to the per-cpu PGM data. */
3276typedef PGMCPU *PPGMCPU;
3277
3278
3279/** @name PGM::fSyncFlags Flags
3280 * @{
3281 */
3282/** Updates the virtual access handler state bit in PGMPAGE. */
3283#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3284/** Always sync CR3. */
3285#define PGM_SYNC_ALWAYS RT_BIT(1)
3286/** Check monitoring on next CR3 (re)load and invalidate page.
3287 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3288#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3289/** Check guest mapping in SyncCR3. */
3290#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3291/** Clear the page pool (a light weight flush). */
3292#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3293#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3294/** @} */
3295
3296
3297RT_C_DECLS_BEGIN
3298
3299int pgmLock(PVM pVM);
3300void pgmUnlock(PVM pVM);
3301
3302int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3303int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3304int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3305PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3306int pgmMapResolveConflicts(PVM pVM);
3307DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3308
3309void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3310bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3311void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3312int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3313DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3314#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3315void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3316#else
3317# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3318#endif
3319DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3320int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3321
3322int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3323int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys, RTHCPHYS *pHCPhys);
3324int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3325int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3326void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3327int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3328int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3329int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3330int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3331int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3332int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3333int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3334int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3335VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3336#ifdef IN_RING3
3337void pgmR3PhysRelinkRamRanges(PVM pVM);
3338int pgmR3PhysRamPreAllocate(PVM pVM);
3339int pgmR3PhysRamReset(PVM pVM);
3340int pgmR3PhysRomReset(PVM pVM);
3341int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3342
3343int pgmR3PoolInit(PVM pVM);
3344void pgmR3PoolRelocate(PVM pVM);
3345void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3346void pgmR3PoolReset(PVM pVM);
3347void pgmR3PoolClearAll(PVM pVM);
3348DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser);
3349
3350#endif /* IN_RING3 */
3351#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3352int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3353#endif
3354int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3355
3356DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3357{
3358 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3359}
3360
3361void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3362void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3363int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3364void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3365PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3366int pgmPoolSyncCR3(PVMCPU pVCpu);
3367bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3368int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3369void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3370DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3371{
3372 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3373}
3374
3375uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3376void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3377void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3378void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3379int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3380void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3381
3382void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3383void pgmPoolResetDirtyPages(PVM pVM);
3384
3385int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3386int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3387
3388void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3389void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3390int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3391int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3392
3393int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3394#ifndef IN_RC
3395int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3396#endif
3397int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3398
3399PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3400PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3401PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3402PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3403
3404RT_C_DECLS_END
3405
3406/** @} */
3407
3408#endif
3409
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette