VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 13089

Last change on this file since 13089 was 13087, checked in by vboxsync, 16 years ago

#1865: More PGM changes.
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File size: 160.9 KB
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1/* $Id: PGMInternal.h 13087 2008-10-08 15:38:52Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) ((uGstType) >= PGM_TYPE_32BIT && (uShwType) != PGM_TYPE_NESTED && (uShwType) != PGM_TYPE_EPT)
201
202/** Macro for checking if the guest supports the NX bit.
203 * @param uGstType PGM_TYPE_*
204 * @param uShwType PGM_TYPE_*
205 * @remark ASSUMES certain order of the PGM_TYPE_* values.
206 */
207#define PGM_WITH_NX(uGstType, uShwType) ((uGstType) >= PGM_TYPE_PAE && (uShwType) != PGM_TYPE_NESTED && (uShwType) != PGM_TYPE_EPT)
208
209
210/** @def PGM_HCPHYS_2_PTR
211 * Maps a HC physical page pool address to a virtual address.
212 *
213 * @returns VBox status code.
214 * @param pVM The VM handle.
215 * @param HCPhys The HC physical address to map to a virtual one.
216 * @param ppv Where to store the virtual address. No need to cast this.
217 *
218 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
219 * small page window employeed by that function. Be careful.
220 * @remark There is no need to assert on the result.
221 */
222#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
223# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
224#else
225# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
226#endif
227
228/** @def PGM_GCPHYS_2_PTR
229 * Maps a GC physical page address to a virtual address.
230 *
231 * @returns VBox status code.
232 * @param pVM The VM handle.
233 * @param GCPhys The GC physical address to map to a virtual one.
234 * @param ppv Where to store the virtual address. No need to cast this.
235 *
236 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
237 * small page window employeed by that function. Be careful.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
242#else
243# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
244#endif
245
246/** @def PGM_GCPHYS_2_PTR_EX
247 * Maps a unaligned GC physical page address to a virtual address.
248 *
249 * @returns VBox status code.
250 * @param pVM The VM handle.
251 * @param GCPhys The GC physical address to map to a virtual one.
252 * @param ppv Where to store the virtual address. No need to cast this.
253 *
254 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
255 * small page window employeed by that function. Be careful.
256 * @remark There is no need to assert on the result.
257 */
258#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
259# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
260#else
261# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
262#endif
263
264/** @def PGM_INVL_PG
265 * Invalidates a page when in GC does nothing in HC.
266 *
267 * @param GCVirt The virtual address of the page to invalidate.
268 */
269#ifdef IN_GC
270# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
271#elif defined(IN_RING0)
272# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
273#else
274# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
275#endif
276
277/** @def PGM_INVL_BIG_PG
278 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
279 *
280 * @param GCVirt The virtual address within the page directory to invalidate.
281 */
282#ifdef IN_GC
283# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
284#elif defined(IN_RING0)
285# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
286#else
287# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
288#endif
289
290/** @def PGM_INVL_GUEST_TLBS()
291 * Invalidates all guest TLBs.
292 */
293#ifdef IN_GC
294# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
295#elif defined(IN_RING0)
296# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
297#else
298# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
299#endif
300
301
302/**
303 * Structure for tracking GC Mappings.
304 *
305 * This structure is used by linked list in both GC and HC.
306 */
307typedef struct PGMMAPPING
308{
309 /** Pointer to next entry. */
310 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
311 /** Pointer to next entry. */
312 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
313 /** Pointer to next entry. */
314 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
315#if GC_ARCH_BITS == 64
316 RTRCPTR padding0;
317#endif
318 /** Start Virtual address. */
319 RTGCUINTPTR GCPtr;
320 /** Last Virtual address (inclusive). */
321 RTGCUINTPTR GCPtrLast;
322 /** Range size (bytes). */
323 RTGCUINTPTR cb;
324 /** Pointer to relocation callback function. */
325 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
326 /** User argument to the callback. */
327 R3PTRTYPE(void *) pvUser;
328 /** Mapping description / name. For easing debugging. */
329 R3PTRTYPE(const char *) pszDesc;
330 /** Number of page tables. */
331 RTUINT cPTs;
332#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
333 RTUINT uPadding1; /**< Alignment padding. */
334#endif
335 /** Array of page table mapping data. Each entry
336 * describes one page table. The array can be longer
337 * than the declared length.
338 */
339 struct
340 {
341 /** The HC physical address of the page table. */
342 RTHCPHYS HCPhysPT;
343 /** The HC physical address of the first PAE page table. */
344 RTHCPHYS HCPhysPaePT0;
345 /** The HC physical address of the second PAE page table. */
346 RTHCPHYS HCPhysPaePT1;
347 /** The HC virtual address of the 32-bit page table. */
348 R3PTRTYPE(PX86PT) pPTR3;
349 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
350 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
351 /** The GC virtual address of the 32-bit page table. */
352 RCPTRTYPE(PX86PT) pPTRC;
353 /** The GC virtual address of the two PAE page table. */
354 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
355 /** The GC virtual address of the 32-bit page table. */
356 R0PTRTYPE(PX86PT) pPTR0;
357 /** The GC virtual address of the two PAE page table. */
358 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
359 } aPTs[1];
360} PGMMAPPING;
361/** Pointer to structure for tracking GC Mappings. */
362typedef struct PGMMAPPING *PPGMMAPPING;
363
364
365/**
366 * Physical page access handler structure.
367 *
368 * This is used to keep track of physical address ranges
369 * which are being monitored in some kind of way.
370 */
371typedef struct PGMPHYSHANDLER
372{
373 AVLROGCPHYSNODECORE Core;
374 /** Access type. */
375 PGMPHYSHANDLERTYPE enmType;
376 /** Number of pages to update. */
377 uint32_t cPages;
378 /** Pointer to R3 callback function. */
379 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
380 /** User argument for R3 handlers. */
381 R3PTRTYPE(void *) pvUserR3;
382 /** Pointer to R0 callback function. */
383 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
384 /** User argument for R0 handlers. */
385 R0PTRTYPE(void *) pvUserR0;
386 /** Pointer to GC callback function. */
387 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
388 /** User argument for RC handlers. */
389 RCPTRTYPE(void *) pvUserRC;
390 /** Description / Name. For easing debugging. */
391 R3PTRTYPE(const char *) pszDesc;
392#ifdef VBOX_WITH_STATISTICS
393 /** Profiling of this handler. */
394 STAMPROFILE Stat;
395#endif
396} PGMPHYSHANDLER;
397/** Pointer to a physical page access handler structure. */
398typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
399
400
401/**
402 * Cache node for the physical addresses covered by a virtual handler.
403 */
404typedef struct PGMPHYS2VIRTHANDLER
405{
406 /** Core node for the tree based on physical ranges. */
407 AVLROGCPHYSNODECORE Core;
408 /** Offset from this struct to the PGMVIRTHANDLER structure. */
409 int32_t offVirtHandler;
410 /** Offset of the next alias relative to this one.
411 * Bit 0 is used for indicating whether we're in the tree.
412 * Bit 1 is used for indicating that we're the head node.
413 */
414 int32_t offNextAlias;
415} PGMPHYS2VIRTHANDLER;
416/** Pointer to a phys to virtual handler structure. */
417typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
418
419/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
420 * node is in the tree. */
421#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
422/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
423 * node is in the head of an alias chain.
424 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
425#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
426/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
427#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
428
429
430/**
431 * Virtual page access handler structure.
432 *
433 * This is used to keep track of virtual address ranges
434 * which are being monitored in some kind of way.
435 */
436typedef struct PGMVIRTHANDLER
437{
438 /** Core node for the tree based on virtual ranges. */
439 AVLROGCPTRNODECORE Core;
440 /** Size of the range (in bytes). */
441 RTGCUINTPTR cb;
442 /** Number of cache pages. */
443 uint32_t cPages;
444 /** Access type. */
445 PGMVIRTHANDLERTYPE enmType;
446 /** Pointer to the RC callback function. */
447 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
448#if HC_ARCH_BITS == 64
449 RTRCPTR padding;
450#endif
451 /** Pointer to the R3 callback function for invalidation. */
452 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
453 /** Pointer to the R3 callback function. */
454 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
455 /** Description / Name. For easing debugging. */
456 R3PTRTYPE(const char *) pszDesc;
457#ifdef VBOX_WITH_STATISTICS
458 /** Profiling of this handler. */
459 STAMPROFILE Stat;
460#endif
461 /** Array of cached physical addresses for the monitored ranged. */
462 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
463} PGMVIRTHANDLER;
464/** Pointer to a virtual page access handler structure. */
465typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
466
467
468/**
469 * Page type.
470 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
471 * @todo convert to \#defines.
472 */
473typedef enum PGMPAGETYPE
474{
475 /** The usual invalid zero entry. */
476 PGMPAGETYPE_INVALID = 0,
477 /** RAM page. (RWX) */
478 PGMPAGETYPE_RAM,
479 /** MMIO2 page. (RWX) */
480 PGMPAGETYPE_MMIO2,
481 /** Shadowed ROM. (RWX) */
482 PGMPAGETYPE_ROM_SHADOW,
483 /** ROM page. (R-X) */
484 PGMPAGETYPE_ROM,
485 /** MMIO page. (---) */
486 PGMPAGETYPE_MMIO,
487 /** End of valid entries. */
488 PGMPAGETYPE_END
489} PGMPAGETYPE;
490AssertCompile(PGMPAGETYPE_END < 7);
491
492/** @name Page type predicates.
493 * @{ */
494#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
495#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
496#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
497#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
498#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
499/** @} */
500
501
502/**
503 * A Physical Guest Page tracking structure.
504 *
505 * The format of this structure is complicated because we have to fit a lot
506 * of information into as few bits as possible. The format is also subject
507 * to change (there is one comming up soon). Which means that for we'll be
508 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
509 * accessess to the structure.
510 */
511typedef struct PGMPAGE
512{
513 /** The physical address and a whole lot of other stuff. All bits are used! */
514 RTHCPHYS HCPhys;
515 /** The page state. */
516 uint32_t u2StateX : 2;
517 /** Flag indicating that a write monitored page was written to when set. */
518 uint32_t fWrittenToX : 1;
519 /** For later. */
520 uint32_t fSomethingElse : 1;
521 /** The Page ID.
522 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
523 * The HCPhys will be 100% static. */
524 uint32_t idPageX : 28;
525 /** The page type (PGMPAGETYPE). */
526 uint32_t u3Type : 3;
527 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
528 uint32_t u2HandlerPhysStateX : 2;
529 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
530 uint32_t u2HandlerVirtStateX : 2;
531 uint32_t u29B : 25;
532} PGMPAGE;
533AssertCompileSize(PGMPAGE, 16);
534/** Pointer to a physical guest page. */
535typedef PGMPAGE *PPGMPAGE;
536/** Pointer to a const physical guest page. */
537typedef const PGMPAGE *PCPGMPAGE;
538/** Pointer to a physical guest page pointer. */
539typedef PPGMPAGE *PPPGMPAGE;
540
541
542/**
543 * Clears the page structure.
544 * @param pPage Pointer to the physical guest page tracking structure.
545 */
546#define PGM_PAGE_CLEAR(pPage) \
547 do { \
548 (pPage)->HCPhys = 0; \
549 (pPage)->u2StateX = 0; \
550 (pPage)->fWrittenToX = 0; \
551 (pPage)->fSomethingElse = 0; \
552 (pPage)->idPageX = 0; \
553 (pPage)->u3Type = 0; \
554 (pPage)->u29B = 0; \
555 } while (0)
556
557/**
558 * Initializes the page structure.
559 * @param pPage Pointer to the physical guest page tracking structure.
560 */
561#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
562 do { \
563 (pPage)->HCPhys = (_HCPhys); \
564 (pPage)->u2StateX = (_uState); \
565 (pPage)->fWrittenToX = 0; \
566 (pPage)->fSomethingElse = 0; \
567 (pPage)->idPageX = (_idPage); \
568 /*(pPage)->u3Type = (_uType); - later */ \
569 PGM_PAGE_SET_TYPE(pPage, _uType); \
570 (pPage)->u29B = 0; \
571 } while (0)
572
573/**
574 * Initializes the page structure of a ZERO page.
575 * @param pPage Pointer to the physical guest page tracking structure.
576 */
577#ifdef VBOX_WITH_NEW_PHYS_CODE
578# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
579 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
580#else
581# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
582 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
583#endif
584/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
585# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
586 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
587
588
589/** @name The Page state, PGMPAGE::u2StateX.
590 * @{ */
591/** The zero page.
592 * This is a per-VM page that's never ever mapped writable. */
593#define PGM_PAGE_STATE_ZERO 0
594/** A allocated page.
595 * This is a per-VM page allocated from the page pool (or wherever
596 * we get MMIO2 pages from if the type is MMIO2).
597 */
598#define PGM_PAGE_STATE_ALLOCATED 1
599/** A allocated page that's being monitored for writes.
600 * The shadow page table mappings are read-only. When a write occurs, the
601 * fWrittenTo member is set, the page remapped as read-write and the state
602 * moved back to allocated. */
603#define PGM_PAGE_STATE_WRITE_MONITORED 2
604/** The page is shared, aka. copy-on-write.
605 * This is a page that's shared with other VMs. */
606#define PGM_PAGE_STATE_SHARED 3
607/** @} */
608
609
610/**
611 * Gets the page state.
612 * @returns page state (PGM_PAGE_STATE_*).
613 * @param pPage Pointer to the physical guest page tracking structure.
614 */
615#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
616
617/**
618 * Sets the page state.
619 * @param pPage Pointer to the physical guest page tracking structure.
620 * @param _uState The new page state.
621 */
622#define PGM_PAGE_SET_STATE(pPage, _uState) \
623 do { (pPage)->u2StateX = (_uState); } while (0)
624
625
626/**
627 * Gets the host physical address of the guest page.
628 * @returns host physical address (RTHCPHYS).
629 * @param pPage Pointer to the physical guest page tracking structure.
630 */
631#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
632
633/**
634 * Sets the host physical address of the guest page.
635 * @param pPage Pointer to the physical guest page tracking structure.
636 * @param _HCPhys The new host physical address.
637 */
638#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
639 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
640 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
641
642/**
643 * Get the Page ID.
644 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
645 * @param pPage Pointer to the physical guest page tracking structure.
646 */
647#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
648/* later:
649#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
650 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
651*/
652/**
653 * Sets the Page ID.
654 * @param pPage Pointer to the physical guest page tracking structure.
655 */
656#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
657/* later:
658#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
659 | ((_idPage) & 0xfff) \
660 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
661*/
662
663/**
664 * Get the Chunk ID.
665 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
666 * @param pPage Pointer to the physical guest page tracking structure.
667 */
668#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
669/* later:
670#if GMM_CHUNKID_SHIFT == 12
671# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
672#elif GMM_CHUNKID_SHIFT > 12
673# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
674#elif GMM_CHUNKID_SHIFT < 12
675# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
676 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
677#else
678# error "GMM_CHUNKID_SHIFT isn't defined or something."
679#endif
680*/
681
682/**
683 * Get the index of the page within the allocaiton chunk.
684 * @returns The page index.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 */
687#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
688/* later:
689#if GMM_CHUNKID_SHIFT <= 12
690# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
691#else
692# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
693 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
694#endif
695*/
696
697
698/**
699 * Gets the page type.
700 * @returns The page type.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 */
703#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
704
705/**
706 * Sets the page type.
707 * @param pPage Pointer to the physical guest page tracking structure.
708 * @param _enmType The new page type (PGMPAGETYPE).
709 */
710#ifdef VBOX_WITH_NEW_PHYS_CODE
711#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
712 do { (pPage)->u3Type = (_enmType); } while (0)
713#else
714#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
715 do { \
716 (pPage)->u3Type = (_enmType); \
717 if ((_enmType) == PGMPAGETYPE_ROM) \
718 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
719 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
720 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
721 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
722 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
723 } while (0)
724#endif
725
726
727/**
728 * Checks if the page is 'reserved'.
729 * @returns true/false.
730 * @param pPage Pointer to the physical guest page tracking structure.
731 */
732#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
733
734/**
735 * Checks if the page is marked for MMIO.
736 * @returns true/false.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
740
741/**
742 * Checks if the page is backed by the ZERO page.
743 * @returns true/false.
744 * @param pPage Pointer to the physical guest page tracking structure.
745 */
746#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
747
748/**
749 * Checks if the page is backed by a SHARED page.
750 * @returns true/false.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
754
755
756/**
757 * Marks the paget as written to (for GMM change monitoring).
758 * @param pPage Pointer to the physical guest page tracking structure.
759 */
760#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
761
762/**
763 * Clears the written-to indicator.
764 * @param pPage Pointer to the physical guest page tracking structure.
765 */
766#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
767
768/**
769 * Checks if the page was marked as written-to.
770 * @returns true/false.
771 * @param pPage Pointer to the physical guest page tracking structure.
772 */
773#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
774
775
776/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
777 *
778 * @remarks The values are assigned in order of priority, so we can calculate
779 * the correct state for a page with different handlers installed.
780 * @{ */
781/** No handler installed. */
782#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
783/** Monitoring is temporarily disabled. */
784#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
785/** Write access is monitored. */
786#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
787/** All access is monitored. */
788#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
789/** @} */
790
791/**
792 * Gets the physical access handler state of a page.
793 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
797
798/**
799 * Sets the physical access handler state of a page.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 * @param _uState The new state value.
802 */
803#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
804 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
805
806/**
807 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
808 * @returns true/false
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
812
813/**
814 * Checks if the page has any active physical access handlers.
815 * @returns true/false
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
819
820
821/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
822 *
823 * @remarks The values are assigned in order of priority, so we can calculate
824 * the correct state for a page with different handlers installed.
825 * @{ */
826/** No handler installed. */
827#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
828/* 1 is reserved so the lineup is identical with the physical ones. */
829/** Write access is monitored. */
830#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
831/** All access is monitored. */
832#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
833/** @} */
834
835/**
836 * Gets the virtual access handler state of a page.
837 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
841
842/**
843 * Sets the virtual access handler state of a page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 * @param _uState The new state value.
846 */
847#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
848 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
849
850/**
851 * Checks if the page has any virtual access handlers.
852 * @returns true/false
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
856
857/**
858 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
859 * virtual handlers.
860 * @returns true/false
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
864
865
866
867/**
868 * Checks if the page has any access handlers, including temporarily disabled ones.
869 * @returns true/false
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
873 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
874 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
875
876/**
877 * Checks if the page has any active access handlers.
878 * @returns true/false
879 * @param pPage Pointer to the physical guest page tracking structure.
880 */
881#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
882 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
883 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
884
885/**
886 * Checks if the page has any active access handlers catching all accesses.
887 * @returns true/false
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
891 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
892 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
893
894
895/**
896 * Ram range for GC Phys to HC Phys conversion.
897 *
898 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
899 * conversions too, but we'll let MM handle that for now.
900 *
901 * This structure is used by linked lists in both GC and HC.
902 */
903typedef struct PGMRAMRANGE
904{
905 /** Pointer to the next RAM range - for R3. */
906 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
907 /** Pointer to the next RAM range - for R0. */
908 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
909 /** Pointer to the next RAM range - for RC. */
910 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
911 /** Pointer alignment. */
912 RTRCPTR RCPtrAlignment;
913 /** Start of the range. Page aligned. */
914 RTGCPHYS GCPhys;
915 /** Last address in the range (inclusive). Page aligned (-1). */
916 RTGCPHYS GCPhysLast;
917 /** Size of the range. (Page aligned of course). */
918 RTGCPHYS cb;
919 /** MM_RAM_* flags */
920 uint32_t fFlags;
921 uint32_t u32Alignment; /**< alignment. */
922#ifndef VBOX_WITH_NEW_PHYS_CODE
923 /** R3 virtual lookup ranges for chunks.
924 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
925 * @remarks This is occationally accessed from ring-0!! (not darwin) */
926# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
927 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
928# else
929 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
930# endif
931#endif
932 /** Start of the HC mapping of the range. This is only used for MMIO2. */
933 R3PTRTYPE(void *) pvR3;
934 /** The range description. */
935 R3PTRTYPE(const char *) pszDesc;
936
937 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
938#ifdef VBOX_WITH_NEW_PHYS_CODE
939 uint32_t au32Reserved[2];
940#elif HC_ARCH_BITS == 32
941 uint32_t au32Reserved[1];
942#endif
943
944 /** Array of physical guest page tracking structures. */
945 PGMPAGE aPages[1];
946} PGMRAMRANGE;
947/** Pointer to Ram range for GC Phys to HC Phys conversion. */
948typedef PGMRAMRANGE *PPGMRAMRANGE;
949
950/** Return hc ptr corresponding to the ram range and physical offset */
951#define PGMRAMRANGE_GETHCPTR(pRam, off) \
952 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
953 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
954
955/**
956 * Per page tracking structure for ROM image.
957 *
958 * A ROM image may have a shadow page, in which case we may have
959 * two pages backing it. This structure contains the PGMPAGE for
960 * both while PGMRAMRANGE have a copy of the active one. It is
961 * important that these aren't out of sync in any regard other
962 * than page pool tracking data.
963 */
964typedef struct PGMROMPAGE
965{
966 /** The page structure for the virgin ROM page. */
967 PGMPAGE Virgin;
968 /** The page structure for the shadow RAM page. */
969 PGMPAGE Shadow;
970 /** The current protection setting. */
971 PGMROMPROT enmProt;
972 /** Pad the structure size to a multiple of 8. */
973 uint32_t u32Padding;
974} PGMROMPAGE;
975/** Pointer to a ROM page tracking structure. */
976typedef PGMROMPAGE *PPGMROMPAGE;
977
978
979/**
980 * A registered ROM image.
981 *
982 * This is needed to keep track of ROM image since they generally
983 * intrude into a PGMRAMRANGE. It also keeps track of additional
984 * info like the two page sets (read-only virgin and read-write shadow),
985 * the current state of each page.
986 *
987 * Because access handlers cannot easily be executed in a different
988 * context, the ROM ranges needs to be accessible and in all contexts.
989 */
990typedef struct PGMROMRANGE
991{
992 /** Pointer to the next range - R3. */
993 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
994 /** Pointer to the next range - R0. */
995 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
996 /** Pointer to the next range - RC. */
997 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
998 /** Pointer alignment */
999 RTRCPTR GCPtrAlignment;
1000 /** Address of the range. */
1001 RTGCPHYS GCPhys;
1002 /** Address of the last byte in the range. */
1003 RTGCPHYS GCPhysLast;
1004 /** Size of the range. */
1005 RTGCPHYS cb;
1006 /** The flags (PGMPHYS_ROM_FLAG_*). */
1007 uint32_t fFlags;
1008 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1009 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1010 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1011 * This is used for strictness checks. */
1012 R3PTRTYPE(const void *) pvOriginal;
1013 /** The ROM description. */
1014 R3PTRTYPE(const char *) pszDesc;
1015 /** The per page tracking structures. */
1016 PGMROMPAGE aPages[1];
1017} PGMROMRANGE;
1018/** Pointer to a ROM range. */
1019typedef PGMROMRANGE *PPGMROMRANGE;
1020
1021
1022/**
1023 * A registered MMIO2 (= Device RAM) range.
1024 *
1025 * There are a few reason why we need to keep track of these
1026 * registrations. One of them is the deregistration & cleanup
1027 * stuff, while another is that the PGMRAMRANGE associated with
1028 * such a region may have to be removed from the ram range list.
1029 *
1030 * Overlapping with a RAM range has to be 100% or none at all. The
1031 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1032 * meditation will be raised if a partial overlap or an overlap of
1033 * ROM pages is encountered. On an overlap we will free all the
1034 * existing RAM pages and put in the ram range pages instead.
1035 */
1036typedef struct PGMMMIO2RANGE
1037{
1038 /** The owner of the range. (a device) */
1039 PPDMDEVINSR3 pDevInsR3;
1040 /** Pointer to the ring-3 mapping of the allocation. */
1041 RTR3PTR pvR3;
1042 /** Pointer to the next range - R3. */
1043 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1044 /** Whether it's mapped or not. */
1045 bool fMapped;
1046 /** Whether it's overlapping or not. */
1047 bool fOverlapping;
1048 /** The PCI region number.
1049 * @remarks This ASSUMES that nobody will ever really need to have multiple
1050 * PCI devices with matching MMIO region numbers on a single device. */
1051 uint8_t iRegion;
1052 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1053 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1054 /** The associated RAM range. */
1055 PGMRAMRANGE RamRange;
1056} PGMMMIO2RANGE;
1057/** Pointer to a MMIO2 range. */
1058typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1059
1060
1061
1062
1063/**
1064 * PGMPhysRead/Write cache entry
1065 */
1066typedef struct PGMPHYSCACHEENTRY
1067{
1068 /** R3 pointer to physical page. */
1069 R3PTRTYPE(uint8_t *) pbR3;
1070 /** GC Physical address for cache entry */
1071 RTGCPHYS GCPhys;
1072#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1073 RTGCPHYS u32Padding0; /**< alignment padding. */
1074#endif
1075} PGMPHYSCACHEENTRY;
1076
1077/**
1078 * PGMPhysRead/Write cache to reduce REM memory access overhead
1079 */
1080typedef struct PGMPHYSCACHE
1081{
1082 /** Bitmap of valid cache entries */
1083 uint64_t aEntries;
1084 /** Cache entries */
1085 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1086} PGMPHYSCACHE;
1087
1088
1089/** Pointer to an allocation chunk ring-3 mapping. */
1090typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1091/** Pointer to an allocation chunk ring-3 mapping pointer. */
1092typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1093
1094/**
1095 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1096 *
1097 * The primary tree (Core) uses the chunk id as key.
1098 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1099 */
1100typedef struct PGMCHUNKR3MAP
1101{
1102 /** The key is the chunk id. */
1103 AVLU32NODECORE Core;
1104 /** The key is the ageing sequence number. */
1105 AVLLU32NODECORE AgeCore;
1106 /** The current age thingy. */
1107 uint32_t iAge;
1108 /** The current reference count. */
1109 uint32_t volatile cRefs;
1110 /** The current permanent reference count. */
1111 uint32_t volatile cPermRefs;
1112 /** The mapping address. */
1113 void *pv;
1114} PGMCHUNKR3MAP;
1115
1116/**
1117 * Allocation chunk ring-3 mapping TLB entry.
1118 */
1119typedef struct PGMCHUNKR3MAPTLBE
1120{
1121 /** The chunk id. */
1122 uint32_t volatile idChunk;
1123#if HC_ARCH_BITS == 64
1124 uint32_t u32Padding; /**< alignment padding. */
1125#endif
1126 /** The chunk map. */
1127#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1128 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1129#else
1130 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1131#endif
1132} PGMCHUNKR3MAPTLBE;
1133/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1134typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1135
1136/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1137 * @remark Must be a power of two value. */
1138#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1139
1140/**
1141 * Allocation chunk ring-3 mapping TLB.
1142 *
1143 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1144 * At first glance this might look kinda odd since AVL trees are
1145 * supposed to give the most optimial lookup times of all trees
1146 * due to their balancing. However, take a tree with 1023 nodes
1147 * in it, that's 10 levels, meaning that most searches has to go
1148 * down 9 levels before they find what they want. This isn't fast
1149 * compared to a TLB hit. There is the factor of cache misses,
1150 * and of course the problem with trees and branch prediction.
1151 * This is why we use TLBs in front of most of the trees.
1152 *
1153 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1154 * difficult when we switch to inlined AVL trees (from kStuff).
1155 */
1156typedef struct PGMCHUNKR3MAPTLB
1157{
1158 /** The TLB entries. */
1159 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1160} PGMCHUNKR3MAPTLB;
1161
1162/**
1163 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1164 * @returns Chunk TLB index.
1165 * @param idChunk The Chunk ID.
1166 */
1167#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1168
1169
1170/**
1171 * Ring-3 guest page mapping TLB entry.
1172 * @remarks used in ring-0 as well at the moment.
1173 */
1174typedef struct PGMPAGER3MAPTLBE
1175{
1176 /** Address of the page. */
1177 RTGCPHYS volatile GCPhys;
1178 /** The guest page. */
1179#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1180 R3PTRTYPE(PPGMPAGE) volatile pPage;
1181#else
1182 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1183#endif
1184 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1185#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1186 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1187#else
1188 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1189#endif
1190 /** The address */
1191#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1192 R3PTRTYPE(void *) volatile pv;
1193#else
1194 R3R0PTRTYPE(void *) volatile pv;
1195#endif
1196#if HC_ARCH_BITS == 32
1197 uint32_t u32Padding; /**< alignment padding. */
1198#endif
1199} PGMPAGER3MAPTLBE;
1200/** Pointer to an entry in the HC physical TLB. */
1201typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1202
1203
1204/** The number of entries in the ring-3 guest page mapping TLB.
1205 * @remarks The value must be a power of two. */
1206#define PGM_PAGER3MAPTLB_ENTRIES 64
1207
1208/**
1209 * Ring-3 guest page mapping TLB.
1210 * @remarks used in ring-0 as well at the moment.
1211 */
1212typedef struct PGMPAGER3MAPTLB
1213{
1214 /** The TLB entries. */
1215 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1216} PGMPAGER3MAPTLB;
1217/** Pointer to the ring-3 guest page mapping TLB. */
1218typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1219
1220/**
1221 * Calculates the index of the TLB entry for the specified guest page.
1222 * @returns Physical TLB index.
1223 * @param GCPhys The guest physical address.
1224 */
1225#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1226
1227
1228/** @name Context neutrual page mapper TLB.
1229 *
1230 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1231 * code is writting in a kind of context neutrual way. Time will show whether
1232 * this actually makes sense or not...
1233 *
1234 * @{ */
1235/** @typedef PPGMPAGEMAPTLB
1236 * The page mapper TLB pointer type for the current context. */
1237/** @typedef PPGMPAGEMAPTLB
1238 * The page mapper TLB entry pointer type for the current context. */
1239/** @typedef PPGMPAGEMAPTLB
1240 * The page mapper TLB entry pointer pointer type for the current context. */
1241/** @def PGM_PAGEMAPTLB_ENTRIES
1242 * The number of TLB entries in the page mapper TLB for the current context. */
1243/** @def PGM_PAGEMAPTLB_IDX
1244 * Calculate the TLB index for a guest physical address.
1245 * @returns The TLB index.
1246 * @param GCPhys The guest physical address. */
1247/** @typedef PPGMPAGEMAP
1248 * Pointer to a page mapper unit for current context. */
1249/** @typedef PPPGMPAGEMAP
1250 * Pointer to a page mapper unit pointer for current context. */
1251#ifdef IN_GC
1252// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1253// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1254// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1255# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1256# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1257 typedef void * PPGMPAGEMAP;
1258 typedef void ** PPPGMPAGEMAP;
1259//#elif IN_RING0
1260// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1261// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1262// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1263//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1264//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1265// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1266// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1267#else
1268 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1269 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1270 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1271# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1272# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1273 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1274 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1275#endif
1276/** @} */
1277
1278
1279/** @name PGM Pool Indexes.
1280 * Aka. the unique shadow page identifier.
1281 * @{ */
1282/** NIL page pool IDX. */
1283#define NIL_PGMPOOL_IDX 0
1284/** The first normal index. */
1285#define PGMPOOL_IDX_FIRST_SPECIAL 1
1286/** Page directory (32-bit root). */
1287#define PGMPOOL_IDX_PD 1
1288/** The extended PAE page directory (2048 entries, works as root currently). */
1289#define PGMPOOL_IDX_PAE_PD 2
1290/** PAE Page Directory Table 0. */
1291#define PGMPOOL_IDX_PAE_PD_0 3
1292/** PAE Page Directory Table 1. */
1293#define PGMPOOL_IDX_PAE_PD_1 4
1294/** PAE Page Directory Table 2. */
1295#define PGMPOOL_IDX_PAE_PD_2 5
1296/** PAE Page Directory Table 3. */
1297#define PGMPOOL_IDX_PAE_PD_3 6
1298/** Page Directory Pointer Table (PAE root, not currently used). */
1299#define PGMPOOL_IDX_PDPT 7
1300/** AMD64 CR3 level index.*/
1301#define PGMPOOL_IDX_AMD64_CR3 8
1302/** Nested paging root.*/
1303#define PGMPOOL_IDX_NESTED_ROOT 9
1304/** The first normal index. */
1305#define PGMPOOL_IDX_FIRST 10
1306/** The last valid index. (inclusive, 14 bits) */
1307#define PGMPOOL_IDX_LAST 0x3fff
1308/** @} */
1309
1310/** The NIL index for the parent chain. */
1311#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1312
1313/**
1314 * Node in the chain linking a shadowed page to it's parent (user).
1315 */
1316#pragma pack(1)
1317typedef struct PGMPOOLUSER
1318{
1319 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1320 uint16_t iNext;
1321 /** The user page index. */
1322 uint16_t iUser;
1323 /** Index into the user table. */
1324 uint32_t iUserTable;
1325} PGMPOOLUSER, *PPGMPOOLUSER;
1326typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1327#pragma pack()
1328
1329
1330/** The NIL index for the phys ext chain. */
1331#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1332
1333/**
1334 * Node in the chain of physical cross reference extents.
1335 */
1336#pragma pack(1)
1337typedef struct PGMPOOLPHYSEXT
1338{
1339 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1340 uint16_t iNext;
1341 /** The user page index. */
1342 uint16_t aidx[3];
1343} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1344typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1345#pragma pack()
1346
1347
1348/**
1349 * The kind of page that's being shadowed.
1350 */
1351typedef enum PGMPOOLKIND
1352{
1353 /** The virtual invalid 0 entry. */
1354 PGMPOOLKIND_INVALID = 0,
1355 /** The entry is free (=unused). */
1356 PGMPOOLKIND_FREE,
1357
1358 /** Shw: 32-bit page table; Gst: no paging */
1359 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1360 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1361 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1362 /** Shw: 32-bit page table; Gst: 4MB page. */
1363 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1364 /** Shw: PAE page table; Gst: no paging */
1365 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1366 /** Shw: PAE page table; Gst: 32-bit page table. */
1367 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1368 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1369 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1370 /** Shw: PAE page table; Gst: PAE page table. */
1371 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1372 /** Shw: PAE page table; Gst: 2MB page. */
1373 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1374
1375 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1376 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1377 /** Shw: PAE page directory; Gst: PAE page directory. */
1378 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1379
1380 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1381 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1382 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1383 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1384 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1385 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1386 /** Shw: 64-bit page directory table; Gst: no paging */
1387 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1388
1389 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1390 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1391
1392 /** Shw: EPT page directory pointer table; Gst: no paging */
1393 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1394 /** Shw: EPT page directory table; Gst: no paging */
1395 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1396 /** Shw: EPT page table; Gst: no paging */
1397 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1398
1399 /** Shw: Root 32-bit page directory. */
1400 PGMPOOLKIND_ROOT_32BIT_PD,
1401 /** Shw: Root PAE page directory */
1402 PGMPOOLKIND_ROOT_PAE_PD,
1403 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1404 PGMPOOLKIND_ROOT_PDPT,
1405 /** Shw: Root Nested paging table. */
1406 PGMPOOLKIND_ROOT_NESTED,
1407
1408 /** The last valid entry. */
1409 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1410} PGMPOOLKIND;
1411
1412
1413/**
1414 * The tracking data for a page in the pool.
1415 */
1416typedef struct PGMPOOLPAGE
1417{
1418 /** AVL node code with the (R3) physical address of this page. */
1419 AVLOHCPHYSNODECORE Core;
1420 /** Pointer to the R3 mapping of the page. */
1421#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1422 R3PTRTYPE(void *) pvPageR3;
1423#else
1424 R3R0PTRTYPE(void *) pvPageR3;
1425#endif
1426 /** The guest physical address. */
1427#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1428 uint32_t Alignment0;
1429#endif
1430 RTGCPHYS GCPhys;
1431 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1432 uint8_t enmKind;
1433 uint8_t bPadding;
1434 /** The index of this page. */
1435 uint16_t idx;
1436 /** The next entry in the list this page currently resides in.
1437 * It's either in the free list or in the GCPhys hash. */
1438 uint16_t iNext;
1439#ifdef PGMPOOL_WITH_USER_TRACKING
1440 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1441 uint16_t iUserHead;
1442 /** The number of present entries. */
1443 uint16_t cPresent;
1444 /** The first entry in the table which is present. */
1445 uint16_t iFirstPresent;
1446#endif
1447#ifdef PGMPOOL_WITH_MONITORING
1448 /** The number of modifications to the monitored page. */
1449 uint16_t cModifications;
1450 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1451 uint16_t iModifiedNext;
1452 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1453 uint16_t iModifiedPrev;
1454 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1455 uint16_t iMonitoredNext;
1456 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1457 uint16_t iMonitoredPrev;
1458#endif
1459#ifdef PGMPOOL_WITH_CACHE
1460 /** The next page in the age list. */
1461 uint16_t iAgeNext;
1462 /** The previous page in the age list. */
1463 uint16_t iAgePrev;
1464#endif /* PGMPOOL_WITH_CACHE */
1465 /** Used to indicate that the page is zeroed. */
1466 bool fZeroed;
1467 /** Used to indicate that a PT has non-global entries. */
1468 bool fSeenNonGlobal;
1469 /** Used to indicate that we're monitoring writes to the guest page. */
1470 bool fMonitored;
1471 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1472 * (All pages are in the age list.) */
1473 bool fCached;
1474 /** This is used by the R3 access handlers when invoked by an async thread.
1475 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1476 bool volatile fReusedFlushPending;
1477 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1478 * In these cases the access handler acts differently and will check
1479 * for mapping conflicts like the normal CR3 handler.
1480 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1481 * replaced by a list of pages which share access handler.
1482 */
1483 bool fCR3Mix;
1484} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1485
1486
1487#ifdef PGMPOOL_WITH_CACHE
1488/** The hash table size. */
1489# define PGMPOOL_HASH_SIZE 0x40
1490/** The hash function. */
1491# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1492#endif
1493
1494
1495/**
1496 * The shadow page pool instance data.
1497 *
1498 * It's all one big allocation made at init time, except for the
1499 * pages that is. The user nodes follows immediatly after the
1500 * page structures.
1501 */
1502typedef struct PGMPOOL
1503{
1504 /** The VM handle - R3 Ptr. */
1505 PVMR3 pVMR3;
1506 /** The VM handle - R0 Ptr. */
1507 PVMR0 pVMR0;
1508 /** The VM handle - RC Ptr. */
1509 PVMRC pVMRC;
1510 /** The max pool size. This includes the special IDs. */
1511 uint16_t cMaxPages;
1512 /** The current pool size. */
1513 uint16_t cCurPages;
1514 /** The head of the free page list. */
1515 uint16_t iFreeHead;
1516 /* Padding. */
1517 uint16_t u16Padding;
1518#ifdef PGMPOOL_WITH_USER_TRACKING
1519 /** Head of the chain of free user nodes. */
1520 uint16_t iUserFreeHead;
1521 /** The number of user nodes we've allocated. */
1522 uint16_t cMaxUsers;
1523 /** The number of present page table entries in the entire pool. */
1524 uint32_t cPresent;
1525 /** Pointer to the array of user nodes - RC pointer. */
1526 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1527 /** Pointer to the array of user nodes - R3 pointer. */
1528 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1529 /** Pointer to the array of user nodes - R0 pointer. */
1530 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1531#endif /* PGMPOOL_WITH_USER_TRACKING */
1532#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1533 /** Head of the chain of free phys ext nodes. */
1534 uint16_t iPhysExtFreeHead;
1535 /** The number of user nodes we've allocated. */
1536 uint16_t cMaxPhysExts;
1537 /** Pointer to the array of physical xref extent - RC pointer. */
1538 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1539 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1540 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1541 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1542 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1543#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1544#ifdef PGMPOOL_WITH_CACHE
1545 /** Hash table for GCPhys addresses. */
1546 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1547 /** The head of the age list. */
1548 uint16_t iAgeHead;
1549 /** The tail of the age list. */
1550 uint16_t iAgeTail;
1551 /** Set if the cache is enabled. */
1552 bool fCacheEnabled;
1553#endif /* PGMPOOL_WITH_CACHE */
1554#ifdef PGMPOOL_WITH_MONITORING
1555 /** Head of the list of modified pages. */
1556 uint16_t iModifiedHead;
1557 /** The current number of modified pages. */
1558 uint16_t cModifiedPages;
1559 /** Access handler, RC. */
1560 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1561 /** Access handler, R0. */
1562 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1563 /** Access handler, R3. */
1564 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1565 /** The access handler description (HC ptr). */
1566 R3PTRTYPE(const char *) pszAccessHandler;
1567#endif /* PGMPOOL_WITH_MONITORING */
1568 /** The number of pages currently in use. */
1569 uint16_t cUsedPages;
1570#ifdef VBOX_WITH_STATISTICS
1571 /** The high wather mark for cUsedPages. */
1572 uint16_t cUsedPagesHigh;
1573 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1574 /** Profiling pgmPoolAlloc(). */
1575 STAMPROFILEADV StatAlloc;
1576 /** Profiling pgmPoolClearAll(). */
1577 STAMPROFILE StatClearAll;
1578 /** Profiling pgmPoolFlushAllInt(). */
1579 STAMPROFILE StatFlushAllInt;
1580 /** Profiling pgmPoolFlushPage(). */
1581 STAMPROFILE StatFlushPage;
1582 /** Profiling pgmPoolFree(). */
1583 STAMPROFILE StatFree;
1584 /** Profiling time spent zeroing pages. */
1585 STAMPROFILE StatZeroPage;
1586# ifdef PGMPOOL_WITH_USER_TRACKING
1587 /** Profiling of pgmPoolTrackDeref. */
1588 STAMPROFILE StatTrackDeref;
1589 /** Profiling pgmTrackFlushGCPhysPT. */
1590 STAMPROFILE StatTrackFlushGCPhysPT;
1591 /** Profiling pgmTrackFlushGCPhysPTs. */
1592 STAMPROFILE StatTrackFlushGCPhysPTs;
1593 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1594 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1595 /** Number of times we've been out of user records. */
1596 STAMCOUNTER StatTrackFreeUpOneUser;
1597# endif
1598# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1599 /** Profiling deref activity related tracking GC physical pages. */
1600 STAMPROFILE StatTrackDerefGCPhys;
1601 /** Number of linear searches for a HCPhys in the ram ranges. */
1602 STAMCOUNTER StatTrackLinearRamSearches;
1603 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1604 STAMCOUNTER StamTrackPhysExtAllocFailures;
1605# endif
1606# ifdef PGMPOOL_WITH_MONITORING
1607 /** Profiling the GC PT access handler. */
1608 STAMPROFILE StatMonitorGC;
1609 /** Times we've failed interpreting the instruction. */
1610 STAMCOUNTER StatMonitorGCEmulateInstr;
1611 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1612 STAMPROFILE StatMonitorGCFlushPage;
1613 /** Times we've detected fork(). */
1614 STAMCOUNTER StatMonitorGCFork;
1615 /** Profiling the GC access we've handled (except REP STOSD). */
1616 STAMPROFILE StatMonitorGCHandled;
1617 /** Times we've failed interpreting a patch code instruction. */
1618 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1619 /** Times we've failed interpreting a patch code instruction during flushing. */
1620 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1621 /** The number of times we've seen rep prefixes we can't handle. */
1622 STAMCOUNTER StatMonitorGCRepPrefix;
1623 /** Profiling the REP STOSD cases we've handled. */
1624 STAMPROFILE StatMonitorGCRepStosd;
1625
1626 /** Profiling the HC PT access handler. */
1627 STAMPROFILE StatMonitorHC;
1628 /** Times we've failed interpreting the instruction. */
1629 STAMCOUNTER StatMonitorHCEmulateInstr;
1630 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1631 STAMPROFILE StatMonitorHCFlushPage;
1632 /** Times we've detected fork(). */
1633 STAMCOUNTER StatMonitorHCFork;
1634 /** Profiling the HC access we've handled (except REP STOSD). */
1635 STAMPROFILE StatMonitorHCHandled;
1636 /** The number of times we've seen rep prefixes we can't handle. */
1637 STAMCOUNTER StatMonitorHCRepPrefix;
1638 /** Profiling the REP STOSD cases we've handled. */
1639 STAMPROFILE StatMonitorHCRepStosd;
1640 /** The number of times we're called in an async thread an need to flush. */
1641 STAMCOUNTER StatMonitorHCAsync;
1642 /** The high wather mark for cModifiedPages. */
1643 uint16_t cModifiedPagesHigh;
1644 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1645# endif
1646# ifdef PGMPOOL_WITH_CACHE
1647 /** The number of cache hits. */
1648 STAMCOUNTER StatCacheHits;
1649 /** The number of cache misses. */
1650 STAMCOUNTER StatCacheMisses;
1651 /** The number of times we've got a conflict of 'kind' in the cache. */
1652 STAMCOUNTER StatCacheKindMismatches;
1653 /** Number of times we've been out of pages. */
1654 STAMCOUNTER StatCacheFreeUpOne;
1655 /** The number of cacheable allocations. */
1656 STAMCOUNTER StatCacheCacheable;
1657 /** The number of uncacheable allocations. */
1658 STAMCOUNTER StatCacheUncacheable;
1659# endif
1660#elif HC_ARCH_BITS == 64
1661 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1662#endif
1663 /** The AVL tree for looking up a page by its HC physical address. */
1664 AVLOHCPHYSTREE HCPhysTree;
1665 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1666 /** Array of pages. (cMaxPages in length)
1667 * The Id is the index into thist array.
1668 */
1669 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1670} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1671
1672
1673/** @def PGMPOOL_PAGE_2_PTR
1674 * Maps a pool page pool into the current context.
1675 *
1676 * @returns VBox status code.
1677 * @param pVM The VM handle.
1678 * @param pPage The pool page.
1679 *
1680 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1681 * small page window employeed by that function. Be careful.
1682 * @remark There is no need to assert on the result.
1683 */
1684#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1685# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1686#else
1687# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1688#endif
1689
1690
1691/**
1692 * Trees are using self relative offsets as pointers.
1693 * So, all its data, including the root pointer, must be in the heap for HC and GC
1694 * to have the same layout.
1695 */
1696typedef struct PGMTREES
1697{
1698 /** Physical access handlers (AVL range+offsetptr tree). */
1699 AVLROGCPHYSTREE PhysHandlers;
1700 /** Virtual access handlers (AVL range + GC ptr tree). */
1701 AVLROGCPTRTREE VirtHandlers;
1702 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1703 AVLROGCPHYSTREE PhysToVirtHandlers;
1704 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1705 AVLROGCPTRTREE HyperVirtHandlers;
1706} PGMTREES;
1707/** Pointer to PGM trees. */
1708typedef PGMTREES *PPGMTREES;
1709
1710
1711/** @name Paging mode macros
1712 * @{ */
1713#ifdef IN_GC
1714# define PGM_CTX(a,b) a##RC##b
1715# define PGM_CTX_STR(a,b) a "GC" b
1716# define PGM_CTX_DECL(type) VMMRCDECL(type)
1717#else
1718# ifdef IN_RING3
1719# define PGM_CTX(a,b) a##R3##b
1720# define PGM_CTX_STR(a,b) a "R3" b
1721# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1722# else
1723# define PGM_CTX(a,b) a##R0##b
1724# define PGM_CTX_STR(a,b) a "R0" b
1725# define PGM_CTX_DECL(type) VMMDECL(type)
1726# endif
1727#endif
1728
1729#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1730#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1731#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1732#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1733#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1734#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1735#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1736#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1737#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1738#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1739#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1740#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1741#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1742#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1743#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1744#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1745#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1746
1747#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1748#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1749#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1750#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1751#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1752#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1753#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1754#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1755#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1756#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1757#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1758#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1759#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1760#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1761#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1762#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1763#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1764
1765/* Shw_Gst */
1766#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1767#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1768#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1769#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1770#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1771#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1772#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1773#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1774#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1775#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1776#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1777#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1778#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1779#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1780#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1781#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1782#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1783#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1784#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1785
1786#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1787#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1788#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1789#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1790#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1791#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1792#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1793#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1794#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1795#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1796#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1797#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1798#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1799#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1800#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1801#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1802#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1803#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1804#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1805#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1806#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1807#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1808#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1809#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1810#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1811#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1812#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1813#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1814#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1815#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1816#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1817#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1818#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1819#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1820#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1821#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1822#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1823
1824#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1825#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1826/** @} */
1827
1828/**
1829 * Data for each paging mode.
1830 */
1831typedef struct PGMMODEDATA
1832{
1833 /** The guest mode type. */
1834 uint32_t uGstType;
1835 /** The shadow mode type. */
1836 uint32_t uShwType;
1837
1838 /** @name Function pointers for Shadow paging.
1839 * @{
1840 */
1841 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1842 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1843 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1844 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1845
1846 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1847 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1848
1849 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1850 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1851 /** @} */
1852
1853 /** @name Function pointers for Guest paging.
1854 * @{
1855 */
1856 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1857 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1858 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1859 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1860 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1861 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1862 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1863 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1864 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1865 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1866 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1867 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1868 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1869
1870 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1871 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1872 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1873 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1874 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
1875 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1876 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
1877 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
1878 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
1879
1880 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1881 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1882 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1883 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1884 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1885 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1886 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1887 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1888 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1889 /** @} */
1890
1891 /** @name Function pointers for Both Shadow and Guest paging.
1892 * @{
1893 */
1894 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1895 /* no pfnR3BthTrap0eHandler */
1896 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1897 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1898 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1899 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1900 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1901#ifdef VBOX_STRICT
1902 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1903#endif
1904
1905 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1906 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1907 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1908 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1909 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1910 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1911#ifdef VBOX_STRICT
1912 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1913#endif
1914
1915 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1916 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1917 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1918 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1919 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1920 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1921#ifdef VBOX_STRICT
1922 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1923#endif
1924 /** @} */
1925} PGMMODEDATA, *PPGMMODEDATA;
1926
1927
1928
1929/**
1930 * Converts a PGM pointer into a VM pointer.
1931 * @returns Pointer to the VM structure the PGM is part of.
1932 * @param pPGM Pointer to PGM instance data.
1933 */
1934#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1935
1936/**
1937 * PGM Data (part of VM)
1938 */
1939typedef struct PGM
1940{
1941 /** Offset to the VM structure. */
1942 RTINT offVM;
1943
1944 /*
1945 * This will be redefined at least two more times before we're done, I'm sure.
1946 * The current code is only to get on with the coding.
1947 * - 2004-06-10: initial version, bird.
1948 * - 2004-07-02: 1st time, bird.
1949 * - 2004-10-18: 2nd time, bird.
1950 * - 2005-07-xx: 3rd time, bird.
1951 */
1952
1953 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1954 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1955 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1956 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1957
1958 /** The host paging mode. (This is what SUPLib reports.) */
1959 SUPPAGINGMODE enmHostMode;
1960 /** The shadow paging mode. */
1961 PGMMODE enmShadowMode;
1962 /** The guest paging mode. */
1963 PGMMODE enmGuestMode;
1964
1965 /** The current physical address representing in the guest CR3 register. */
1966 RTGCPHYS GCPhysCR3;
1967 /** Pointer to the 5 page CR3 content mapping.
1968 * The first page is always the CR3 (in some form) while the 4 other pages
1969 * are used of the PDs in PAE mode. */
1970 RTGCPTR GCPtrCR3Mapping;
1971#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1972 uint32_t u32Alignment;
1973#endif
1974 /** The physical address of the currently monitored guest CR3 page.
1975 * When this value is NIL_RTGCPHYS no page is being monitored. */
1976 RTGCPHYS GCPhysGstCR3Monitored;
1977
1978 /** @name 32-bit Guest Paging.
1979 * @{ */
1980 /** The guest's page directory, HC pointer. */
1981#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
1982 R3PTRTYPE(PX86PD) pGuestPDHC;
1983#else
1984 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1985#endif
1986 /** The guest's page directory, static GC mapping. */
1987 RCPTRTYPE(PX86PD) pGuestPDGC;
1988 /** @} */
1989
1990 /** @name PAE Guest Paging.
1991 * @{ */
1992 /** The guest's page directory pointer table, static GC mapping. */
1993 RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1994 /** The guest's page directory pointer table, HC pointer. */
1995#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
1996 R3PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1997#else
1998 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1999#endif
2000 /** The guest's page directories, HC pointers.
2001 * These are individual pointers and don't have to be adjecent.
2002 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2003#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2004 R3PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
2005#else
2006 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
2007#endif
2008 /** The guest's page directories, static GC mapping.
2009 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
2010 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2011 RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
2012 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2013 RTGCPHYS aGCPhysGstPaePDs[4];
2014 /** The physical addresses of the monitored guest page directories (PAE). */
2015 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2016 /** @} */
2017
2018 /** @name AMD64 Guest Paging.
2019 * @{ */
2020 /** The guest's page directory pointer table, HC pointer. */
2021#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2022 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
2023#else
2024 R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
2025#endif
2026 /** @} */
2027
2028 /** @name 32-bit Shadow Paging
2029 * @{ */
2030 /** The 32-Bit PD - HC Ptr. */
2031#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2032 R3PTRTYPE(PX86PD) pHC32BitPD;
2033#else
2034 R3R0PTRTYPE(PX86PD) pHC32BitPD;
2035#endif
2036 /** The 32-Bit PD - GC Ptr. */
2037 RCPTRTYPE(PX86PD) pGC32BitPD;
2038#if HC_ARCH_BITS == 64
2039 uint32_t u32Padding1; /**< alignment padding. */
2040#endif
2041 /** The Physical Address (HC) of the 32-Bit PD. */
2042 RTHCPHYS HCPhys32BitPD;
2043 /** @} */
2044
2045 /** @name PAE Shadow Paging
2046 * @{ */
2047 /** The four PDs for the low 4GB - HC Ptr.
2048 * Even though these are 4 pointers, what they point at is a single table.
2049 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2050#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2051 R3PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2052#else
2053 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2054#endif
2055 /** The four PDs for the low 4GB - GC Ptr.
2056 * Same kind of mapping as apHCPaePDs. */
2057 RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
2058 /** The Physical Address (HC) of the four PDs for the low 4GB.
2059 * These are *NOT* 4 contiguous pages. */
2060 RTHCPHYS aHCPhysPaePDs[4];
2061 /** The PAE PDP - HC Ptr. */
2062 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
2063 /** The Physical Address (HC) of the PAE PDPT. */
2064 RTHCPHYS HCPhysPaePDPT;
2065 /** The PAE PDPT - GC Ptr. */
2066 RCPTRTYPE(PX86PDPT) pGCPaePDPT;
2067 /** @} */
2068
2069 /** @name AMD64 Shadow Paging
2070 * Extends PAE Paging.
2071 * @{ */
2072#if HC_ARCH_BITS == 64
2073 RTRCPTR alignment5; /**< structure size alignment. */
2074#endif
2075 /** The Page Map Level 4 table - HC Ptr. */
2076#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2077 R3PTRTYPE(PX86PML4) pHCPaePML4;
2078#else
2079 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2080#endif
2081 /** The Physical Address (HC) of the Page Map Level 4 table. */
2082 RTHCPHYS HCPhysPaePML4;
2083 /** The pgm pool page descriptor for the current active CR3. */
2084#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2085 R3PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2086#else
2087 R3R0PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2088#endif
2089
2090 /** @}*/
2091
2092 /** @name Nested Shadow Paging
2093 * @{ */
2094 /** Root table; format depends on the host paging mode (AMD-V) or EPT */
2095#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2096 R3PTRTYPE(void *) pHCNestedRoot;
2097#else
2098 R3R0PTRTYPE(void *) pHCNestedRoot;
2099#endif
2100 /** The Physical Address (HC) of the nested paging root. */
2101 RTHCPHYS HCPhysNestedRoot;
2102
2103 /** @name Function pointers for Shadow paging.
2104 * @{
2105 */
2106 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2107 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2108 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2109 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2110
2111 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2112 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2113
2114 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2115 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2116
2117 /** @} */
2118
2119 /** @name Function pointers for Guest paging.
2120 * @{
2121 */
2122 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2123 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2124 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2125 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2126 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2127 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2128 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2129 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2130 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2131 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2132 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2133 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2134 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2135
2136 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2137 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2138 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2139 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2140 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2141 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2142 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2143 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2144 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2145#if HC_ARCH_BITS == 64
2146 RTRCPTR alignment3; /**< structure size alignment. */
2147#endif
2148
2149 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2150 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2151 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2152 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2153 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2154 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2155 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2156 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2157 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2158 /** @} */
2159
2160 /** @name Function pointers for Both Shadow and Guest paging.
2161 * @{
2162 */
2163 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2164 /* no pfnR3BthTrap0eHandler */
2165 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2166 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2167 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2168 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2169 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2170 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2171
2172 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2173 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2174 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2175 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2176 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2177 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2178 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2179
2180 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2181 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2182 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2183 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2184 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2185 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2186 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2187#if HC_ARCH_BITS == 64
2188 RTRCPTR alignment2; /**< structure size alignment. */
2189#endif
2190 /** @} */
2191
2192 /** Pointer to SHW+GST mode data (function pointers).
2193 * The index into this table is made up from */
2194 R3PTRTYPE(PPGMMODEDATA) paModeData;
2195
2196 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2197 * This is sorted by physical address and contains no overlapping ranges. */
2198 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2199 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2200 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2201 /** RC pointer corresponding to PGM::pRamRangesR3. */
2202 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2203 /** The configured RAM size. */
2204 RTUINT cbRamSize;
2205
2206 /** Pointer to the list of ROM ranges - for R3.
2207 * This is sorted by physical address and contains no overlapping ranges. */
2208 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2209 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2210 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2211 /** RC pointer corresponding to PGM::pRomRangesR3. */
2212 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2213 /** Alignment padding. */
2214 RTRCPTR GCPtrPadding2;
2215
2216 /** Pointer to the list of MMIO2 ranges - for R3.
2217 * Registration order. */
2218 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2219
2220 /** PGM offset based trees - R3 Ptr. */
2221 R3PTRTYPE(PPGMTREES) pTreesR3;
2222 /** PGM offset based trees - R0 Ptr. */
2223 R0PTRTYPE(PPGMTREES) pTreesR0;
2224 /** PGM offset based trees - RC Ptr. */
2225 RCPTRTYPE(PPGMTREES) pTreesRC;
2226
2227 /** Linked list of GC mappings - for RC.
2228 * The list is sorted ascending on address.
2229 */
2230 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2231 /** Linked list of GC mappings - for HC.
2232 * The list is sorted ascending on address.
2233 */
2234 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2235 /** Linked list of GC mappings - for R0.
2236 * The list is sorted ascending on address.
2237 */
2238 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2239
2240 /** If set no conflict checks are required. (boolean) */
2241 bool fMappingsFixed;
2242 /** If set, then no mappings are put into the shadow page table. (boolean) */
2243 bool fDisableMappings;
2244 /** Size of fixed mapping */
2245 uint32_t cbMappingFixed;
2246 /** Base address (GC) of fixed mapping */
2247 RTGCPTR GCPtrMappingFixed;
2248#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2249 uint32_t u32Padding0; /**< alignment padding. */
2250#endif
2251
2252
2253 /** @name Intermediate Context
2254 * @{ */
2255 /** Pointer to the intermediate page directory - Normal. */
2256 R3PTRTYPE(PX86PD) pInterPD;
2257 /** Pointer to the intermedate page tables - Normal.
2258 * There are two page tables, one for the identity mapping and one for
2259 * the host context mapping (of the core code). */
2260 R3PTRTYPE(PX86PT) apInterPTs[2];
2261 /** Pointer to the intermedate page tables - PAE. */
2262 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2263 /** Pointer to the intermedate page directory - PAE. */
2264 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2265 /** Pointer to the intermedate page directory - PAE. */
2266 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2267 /** Pointer to the intermedate page-map level 4 - AMD64. */
2268 R3PTRTYPE(PX86PML4) pInterPaePML4;
2269 /** Pointer to the intermedate page directory - AMD64. */
2270 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2271 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2272 RTHCPHYS HCPhysInterPD;
2273 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2274 RTHCPHYS HCPhysInterPaePDPT;
2275 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2276 RTHCPHYS HCPhysInterPaePML4;
2277 /** @} */
2278
2279 /** Base address of the dynamic page mapping area.
2280 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2281 */
2282 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2283 /** The index of the last entry used in the dynamic page mapping area. */
2284 RTUINT iDynPageMapLast;
2285 /** Cache containing the last entries in the dynamic page mapping area.
2286 * The cache size is covering half of the mapping area. */
2287 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2288
2289 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2290 RTGCPHYS GCPhys4MBPSEMask;
2291
2292 /** A20 gate mask.
2293 * Our current approach to A20 emulation is to let REM do it and don't bother
2294 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2295 * But whould need arrise, we'll subject physical addresses to this mask. */
2296 RTGCPHYS GCPhysA20Mask;
2297 /** A20 gate state - boolean! */
2298 RTUINT fA20Enabled;
2299
2300 /** What needs syncing (PGM_SYNC_*).
2301 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2302 * PGMFlushTLB, and PGMR3Load. */
2303 RTUINT fSyncFlags;
2304
2305 /** PGM critical section.
2306 * This protects the physical & virtual access handlers, ram ranges,
2307 * and the page flag updating (some of it anyway).
2308 */
2309 PDMCRITSECT CritSect;
2310
2311 /** Shadow Page Pool - R3 Ptr. */
2312 R3PTRTYPE(PPGMPOOL) pPoolR3;
2313 /** Shadow Page Pool - R0 Ptr. */
2314 R0PTRTYPE(PPGMPOOL) pPoolR0;
2315 /** Shadow Page Pool - RC Ptr. */
2316 RCPTRTYPE(PPGMPOOL) pPoolRC;
2317
2318 /** We're not in a state which permits writes to guest memory.
2319 * (Only used in strict builds.) */
2320 bool fNoMorePhysWrites;
2321
2322 /** Flush the cache on the next access. */
2323 bool fPhysCacheFlushPending;
2324/** @todo r=bird: Fix member names!*/
2325 /** PGMPhysRead cache */
2326 PGMPHYSCACHE pgmphysreadcache;
2327 /** PGMPhysWrite cache */
2328 PGMPHYSCACHE pgmphyswritecache;
2329
2330 /**
2331 * Data associated with managing the ring-3 mappings of the allocation chunks.
2332 */
2333 struct
2334 {
2335 /** The chunk tree, ordered by chunk id. */
2336#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2337 R3PTRTYPE(PAVLU32NODECORE) pTree;
2338#else
2339 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2340#endif
2341 /** The chunk mapping TLB. */
2342 PGMCHUNKR3MAPTLB Tlb;
2343 /** The number of mapped chunks. */
2344 uint32_t c;
2345 /** The maximum number of mapped chunks.
2346 * @cfgm PGM/MaxRing3Chunks */
2347 uint32_t cMax;
2348 /** The chunk age tree, ordered by ageing sequence number. */
2349 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2350 /** The current time. */
2351 uint32_t iNow;
2352 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2353 uint32_t AgeingCountdown;
2354 } ChunkR3Map;
2355
2356 /**
2357 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2358 */
2359 PGMPAGER3MAPTLB PhysTlbHC;
2360
2361 /** @name The zero page.
2362 * @{ */
2363 /** The host physical address of the zero page. */
2364 RTHCPHYS HCPhysZeroPg;
2365 /** The ring-3 mapping of the zero page. */
2366 RTR3PTR pvZeroPgR3;
2367 /** The ring-0 mapping of the zero page. */
2368 RTR0PTR pvZeroPgR0;
2369 /** The GC mapping of the zero page. */
2370 RTGCPTR pvZeroPgGC;
2371#if GC_ARCH_BITS != 32
2372 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2373#endif
2374 /** @}*/
2375
2376 /** The number of handy pages. */
2377 uint32_t cHandyPages;
2378 /**
2379 * Array of handy pages.
2380 *
2381 * This array is used in a two way communication between pgmPhysAllocPage
2382 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2383 * an intermediary.
2384 *
2385 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2386 * (The current size of 32 pages, means 128 KB of handy memory.)
2387 */
2388 GMMPAGEDESC aHandyPages[32];
2389
2390 /** @name Release Statistics
2391 * @{ */
2392 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2393 uint32_t cPrivatePages; /**< The number of private pages. */
2394 uint32_t cSharedPages; /**< The number of shared pages. */
2395 uint32_t cZeroPages; /**< The number of zero backed pages. */
2396 /** The number of times the guest has switched mode since last reset or statistics reset. */
2397 STAMCOUNTER cGuestModeChanges;
2398 /** @} */
2399
2400#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2401 /** RC: Which statistic this \#PF should be attributed to. */
2402 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2403 RTRCPTR padding0;
2404 /** R0: Which statistic this \#PF should be attributed to. */
2405 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2406 RTR0PTR padding1;
2407
2408 /* Common */
2409# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2410 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2411 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2412 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2413 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2414 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2415 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2416# endif
2417
2418 /* R3 only: */
2419 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2420 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2421 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2422 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2423
2424 /* RC only: */
2425 STAMPROFILE StatRCInvalidatePage; /**< RC: PGMGCInvalidatePage() profiling. */
2426 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2427 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2428
2429 /* RZ only: */
2430 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2431 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2432 STAMPROFILE StatRZTrap0eTimeSyncPT;
2433 STAMPROFILE StatRZTrap0eTimeMapping;
2434 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2435 STAMPROFILE StatRZTrap0eTimeHandlers;
2436 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2437 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2438 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2439 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2440 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2441 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2442 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2443 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2444 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2445 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2446 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2447 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2448 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2449 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2450 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2451 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2452 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2453 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2454 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2455 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2456 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2457 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2458 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2459 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2460 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2461 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2462 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2463 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2464 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2465 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2466 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2467 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2468 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PF. */
2469 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2470 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2471 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2472 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2473 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2474 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2475 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2476 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2477
2478
2479 /* RZ & R3: */
2480 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2481 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2482 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2483 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2484 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2485 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2486 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2487 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2488 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2489 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2490 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2491 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2492 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2493 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2494 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2495 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2496 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2497 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2498 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2499 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2500 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2501 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2502 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2503 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2504 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2505 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2506 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2507 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2508 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2509 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2510 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2511 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2512 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2513 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2514 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2515 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2516 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2517 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2518 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2519
2520 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2521 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2522 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2523 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2524 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2525 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2526 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2527 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2528 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2529 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2530 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2531 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2532 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2533 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2534 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2535 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2536 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2537 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2538 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2539 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2540 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2541 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2542 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2543 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2544 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2545 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2546 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2547 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2548 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2549 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2550 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2551 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2552 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2553 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2554 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2555 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2556 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2557 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2558 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2559
2560 /* TODO (cleanup): */
2561
2562 STAMCOUNTER StatPageHCMapTlbHits; /** Ring-3/0 page mapper TLB hits. */
2563 STAMCOUNTER StatPageHCMapTlbMisses; /** Ring-3/0 page mapper TLB misses. */
2564 STAMCOUNTER StatChunkR3MapTlbHits; /** Ring-3/0 chunk mapper TLB hits. */
2565 STAMCOUNTER StatChunkR3MapTlbMisses; /** Ring-3/0 chunk mapper TLB misses. */
2566 STAMCOUNTER StatPageReplaceShared; /** Times a shared page has been replaced by a private one. */
2567 STAMCOUNTER StatPageReplaceZero; /** Times the zero page has been replaced by a private one. */
2568 STAMCOUNTER StatPageHandyAllocs; /** The number of times we've executed GMMR3AllocateHandyPages. */
2569
2570 STAMCOUNTER StatDynRamTotal; /** Allocated MBs of guest ram */
2571 STAMCOUNTER StatDynRamGrow; /** Nr of pgmr3PhysGrowRange calls. */
2572
2573 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES];
2574 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2575 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2576
2577
2578 /** GC: Profiling of the PGMGstModifyPage() body */
2579 STAMPROFILE StatGCGstModifyPage;
2580 /** HC: Profiling of the PGMGstModifyPage() body */
2581 STAMPROFILE StatHCGstModifyPage;
2582
2583 STAMCOUNTER StatSynPT4kGC;
2584 STAMCOUNTER StatSynPT4kHC;
2585 STAMCOUNTER StatSynPT4MGC;
2586 STAMCOUNTER StatSynPT4MHC;
2587
2588 /** Profiling of the PGMFlushTLB() body. */
2589 STAMPROFILE StatFlushTLB;
2590 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2591 STAMCOUNTER StatFlushTLBNewCR3;
2592 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2593 STAMCOUNTER StatFlushTLBNewCR3Global;
2594 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2595 STAMCOUNTER StatFlushTLBSameCR3;
2596 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2597 STAMCOUNTER StatFlushTLBSameCR3Global;
2598
2599#endif /* VBOX_WITH_STATISTICS */
2600} PGM, *PPGM;
2601
2602
2603/** @name PGM::fSyncFlags Flags
2604 * @{
2605 */
2606/** Updates the virtual access handler state bit in PGMPAGE. */
2607#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2608/** Always sync CR3. */
2609#define PGM_SYNC_ALWAYS RT_BIT(1)
2610/** Check monitoring on next CR3 (re)load and invalidate page. */
2611#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2612/** Clear the page pool (a light weight flush). */
2613#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2614/** @} */
2615
2616
2617__BEGIN_DECLS
2618
2619int pgmLock(PVM pVM);
2620void pgmUnlock(PVM pVM);
2621
2622VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2623VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2624
2625int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2626int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2627PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2628void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2629DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2630
2631void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2632int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2633DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2634#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2635void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2636#else
2637# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2638#endif
2639DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2640
2641
2642void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2643int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2644int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2645int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2646#ifdef IN_RING3
2647int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2648int pgmR3PhysRamReset(PVM pVM);
2649int pgmR3PhysRomReset(PVM pVM);
2650#ifndef VBOX_WITH_NEW_PHYS_CODE
2651int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2652#endif
2653
2654int pgmR3PoolInit(PVM pVM);
2655void pgmR3PoolRelocate(PVM pVM);
2656void pgmR3PoolReset(PVM pVM);
2657
2658#endif /* IN_RING3 */
2659#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2660void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2661#endif
2662int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2663PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2664void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2665void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2666int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2667void pgmPoolFlushAll(PVM pVM);
2668void pgmPoolClearAll(PVM pVM);
2669int pgmPoolSyncCR3(PVM pVM);
2670void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2671void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2672int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2673PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2674void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2675void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2676uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2677void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2678#ifdef PGMPOOL_WITH_MONITORING
2679# ifdef IN_RING3
2680void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2681# else
2682void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2683# endif
2684int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2685void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2686void pgmPoolMonitorModifiedClearAll(PVM pVM);
2687int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2688int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2689#endif
2690
2691__END_DECLS
2692
2693
2694/**
2695 * Gets the PGMRAMRANGE structure for a guest page.
2696 *
2697 * @returns Pointer to the RAM range on success.
2698 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2699 *
2700 * @param pPGM PGM handle.
2701 * @param GCPhys The GC physical address.
2702 */
2703DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2704{
2705 /*
2706 * Optimize for the first range.
2707 */
2708 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2709 RTGCPHYS off = GCPhys - pRam->GCPhys;
2710 if (RT_UNLIKELY(off >= pRam->cb))
2711 {
2712 do
2713 {
2714 pRam = pRam->CTX_SUFF(pNext);
2715 if (RT_UNLIKELY(!pRam))
2716 break;
2717 off = GCPhys - pRam->GCPhys;
2718 } while (off >= pRam->cb);
2719 }
2720 return pRam;
2721}
2722
2723
2724/**
2725 * Gets the PGMPAGE structure for a guest page.
2726 *
2727 * @returns Pointer to the page on success.
2728 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2729 *
2730 * @param pPGM PGM handle.
2731 * @param GCPhys The GC physical address.
2732 */
2733DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2734{
2735 /*
2736 * Optimize for the first range.
2737 */
2738 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2739 RTGCPHYS off = GCPhys - pRam->GCPhys;
2740 if (RT_UNLIKELY(off >= pRam->cb))
2741 {
2742 do
2743 {
2744 pRam = pRam->CTX_SUFF(pNext);
2745 if (RT_UNLIKELY(!pRam))
2746 return NULL;
2747 off = GCPhys - pRam->GCPhys;
2748 } while (off >= pRam->cb);
2749 }
2750 return &pRam->aPages[off >> PAGE_SHIFT];
2751}
2752
2753
2754/**
2755 * Gets the PGMPAGE structure for a guest page.
2756 *
2757 * Old Phys code: Will make sure the page is present.
2758 *
2759 * @returns VBox status code.
2760 * @retval VINF_SUCCESS and a valid *ppPage on success.
2761 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2762 *
2763 * @param pPGM PGM handle.
2764 * @param GCPhys The GC physical address.
2765 * @param ppPage Where to store the page poitner on success.
2766 */
2767DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2768{
2769 /*
2770 * Optimize for the first range.
2771 */
2772 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2773 RTGCPHYS off = GCPhys - pRam->GCPhys;
2774 if (RT_UNLIKELY(off >= pRam->cb))
2775 {
2776 do
2777 {
2778 pRam = pRam->CTX_SUFF(pNext);
2779 if (RT_UNLIKELY(!pRam))
2780 {
2781 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2782 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2783 }
2784 off = GCPhys - pRam->GCPhys;
2785 } while (off >= pRam->cb);
2786 }
2787 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2788#ifndef VBOX_WITH_NEW_PHYS_CODE
2789
2790 /*
2791 * Make sure it's present.
2792 */
2793 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2794 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2795 {
2796#ifdef IN_RING3
2797 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2798#else
2799 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2800#endif
2801 if (VBOX_FAILURE(rc))
2802 {
2803 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2804 return rc;
2805 }
2806 Assert(rc == VINF_SUCCESS);
2807 }
2808#endif
2809 return VINF_SUCCESS;
2810}
2811
2812
2813
2814
2815/**
2816 * Gets the PGMPAGE structure for a guest page.
2817 *
2818 * Old Phys code: Will make sure the page is present.
2819 *
2820 * @returns VBox status code.
2821 * @retval VINF_SUCCESS and a valid *ppPage on success.
2822 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2823 *
2824 * @param pPGM PGM handle.
2825 * @param GCPhys The GC physical address.
2826 * @param ppPage Where to store the page poitner on success.
2827 * @param ppRamHint Where to read and store the ram list hint.
2828 * The caller initializes this to NULL before the call.
2829 */
2830DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2831{
2832 RTGCPHYS off;
2833 PPGMRAMRANGE pRam = *ppRamHint;
2834 if ( !pRam
2835 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2836 {
2837 pRam = pPGM->CTX_SUFF(pRamRanges);
2838 off = GCPhys - pRam->GCPhys;
2839 if (RT_UNLIKELY(off >= pRam->cb))
2840 {
2841 do
2842 {
2843 pRam = pRam->CTX_SUFF(pNext);
2844 if (RT_UNLIKELY(!pRam))
2845 {
2846 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2847 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2848 }
2849 off = GCPhys - pRam->GCPhys;
2850 } while (off >= pRam->cb);
2851 }
2852 *ppRamHint = pRam;
2853 }
2854 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2855#ifndef VBOX_WITH_NEW_PHYS_CODE
2856
2857 /*
2858 * Make sure it's present.
2859 */
2860 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2861 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2862 {
2863#ifdef IN_RING3
2864 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2865#else
2866 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2867#endif
2868 if (VBOX_FAILURE(rc))
2869 {
2870 *ppPage = NULL; /* Shut up annoying smart ass. */
2871 return rc;
2872 }
2873 Assert(rc == VINF_SUCCESS);
2874 }
2875#endif
2876 return VINF_SUCCESS;
2877}
2878
2879
2880/**
2881 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2882 *
2883 * @returns Pointer to the page on success.
2884 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2885 *
2886 * @param pPGM PGM handle.
2887 * @param GCPhys The GC physical address.
2888 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2889 */
2890DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2891{
2892 /*
2893 * Optimize for the first range.
2894 */
2895 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2896 RTGCPHYS off = GCPhys - pRam->GCPhys;
2897 if (RT_UNLIKELY(off >= pRam->cb))
2898 {
2899 do
2900 {
2901 pRam = pRam->CTX_SUFF(pNext);
2902 if (RT_UNLIKELY(!pRam))
2903 return NULL;
2904 off = GCPhys - pRam->GCPhys;
2905 } while (off >= pRam->cb);
2906 }
2907 *ppRam = pRam;
2908 return &pRam->aPages[off >> PAGE_SHIFT];
2909}
2910
2911
2912
2913
2914/**
2915 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2916 *
2917 * @returns Pointer to the page on success.
2918 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2919 *
2920 * @param pPGM PGM handle.
2921 * @param GCPhys The GC physical address.
2922 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2923 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2924 */
2925DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2926{
2927 /*
2928 * Optimize for the first range.
2929 */
2930 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2931 RTGCPHYS off = GCPhys - pRam->GCPhys;
2932 if (RT_UNLIKELY(off >= pRam->cb))
2933 {
2934 do
2935 {
2936 pRam = pRam->CTX_SUFF(pNext);
2937 if (RT_UNLIKELY(!pRam))
2938 {
2939 *ppRam = NULL; /* Shut up silly GCC warnings. */
2940 *ppPage = NULL; /* ditto */
2941 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2942 }
2943 off = GCPhys - pRam->GCPhys;
2944 } while (off >= pRam->cb);
2945 }
2946 *ppRam = pRam;
2947 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2948#ifndef VBOX_WITH_NEW_PHYS_CODE
2949
2950 /*
2951 * Make sure it's present.
2952 */
2953 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2954 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2955 {
2956#ifdef IN_RING3
2957 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2958#else
2959 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2960#endif
2961 if (VBOX_FAILURE(rc))
2962 {
2963 *ppPage = NULL; /* Shut up silly GCC warnings. */
2964 *ppPage = NULL; /* ditto */
2965 return rc;
2966 }
2967 Assert(rc == VINF_SUCCESS);
2968
2969 }
2970#endif
2971 return VINF_SUCCESS;
2972}
2973
2974
2975/**
2976 * Convert GC Phys to HC Phys.
2977 *
2978 * @returns VBox status.
2979 * @param pPGM PGM handle.
2980 * @param GCPhys The GC physical address.
2981 * @param pHCPhys Where to store the corresponding HC physical address.
2982 *
2983 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2984 * Avoid when writing new code!
2985 */
2986DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2987{
2988 PPGMPAGE pPage;
2989 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2990 if (VBOX_FAILURE(rc))
2991 return rc;
2992 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2993 return VINF_SUCCESS;
2994}
2995
2996
2997#ifndef IN_GC
2998/**
2999 * Queries the Physical TLB entry for a physical guest page,
3000 * attemting to load the TLB entry if necessary.
3001 *
3002 * @returns VBox status code.
3003 * @retval VINF_SUCCESS on success
3004 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3005 * @param pPGM The PGM instance handle.
3006 * @param GCPhys The address of the guest page.
3007 * @param ppTlbe Where to store the pointer to the TLB entry.
3008 */
3009
3010DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3011{
3012 int rc;
3013 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3014 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3015 {
3016 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
3017 rc = VINF_SUCCESS;
3018 }
3019 else
3020 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3021 *ppTlbe = pTlbe;
3022 return rc;
3023}
3024#endif /* !IN_GC */
3025
3026#if !defined(IN_GC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3027
3028# ifndef VBOX_WITH_NEW_PHYS_CODE
3029/**
3030 * Convert GC Phys to HC Virt.
3031 *
3032 * @returns VBox status.
3033 * @param pPGM PGM handle.
3034 * @param GCPhys The GC physical address.
3035 * @param pHCPtr Where to store the corresponding HC virtual address.
3036 *
3037 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3038 */
3039DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3040{
3041 PPGMRAMRANGE pRam;
3042 PPGMPAGE pPage;
3043 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3044 if (VBOX_FAILURE(rc))
3045 {
3046 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3047 return rc;
3048 }
3049 RTGCPHYS off = GCPhys - pRam->GCPhys;
3050
3051 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3052 {
3053 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3054 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3055 return VINF_SUCCESS;
3056 }
3057 if (pRam->pvR3)
3058 {
3059 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3060 return VINF_SUCCESS;
3061 }
3062 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3063 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3064}
3065# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3066
3067
3068/**
3069 * Convert GC Phys to HC Virt.
3070 *
3071 * @returns VBox status.
3072 * @param PVM VM handle.
3073 * @param pRam Ram range
3074 * @param GCPhys The GC physical address.
3075 * @param pHCPtr Where to store the corresponding HC virtual address.
3076 *
3077 * @deprecated This will be eliminated. Don't use it.
3078 */
3079DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3080{
3081 RTGCPHYS off = GCPhys - pRam->GCPhys;
3082 Assert(off < pRam->cb);
3083
3084 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3085 {
3086 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3087 /* Physical chunk in dynamically allocated range not present? */
3088 if (RT_UNLIKELY(!pRam->paChunkR3Ptrs[idx]))
3089 {
3090#ifdef IN_RING3
3091 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3092#else
3093 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3094#endif
3095 if (rc != VINF_SUCCESS)
3096 {
3097 *pHCPtr = 0; /* GCC crap */
3098 return rc;
3099 }
3100 }
3101 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3102 return VINF_SUCCESS;
3103 }
3104 if (pRam->pvR3)
3105 {
3106 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3107 return VINF_SUCCESS;
3108 }
3109 *pHCPtr = 0; /* GCC crap */
3110 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3111}
3112
3113#endif /* !IN_GC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3114
3115/**
3116 * Convert GC Phys to HC Virt and HC Phys.
3117 *
3118 * @returns VBox status.
3119 * @param pPGM PGM handle.
3120 * @param GCPhys The GC physical address.
3121 * @param pHCPtr Where to store the corresponding HC virtual address.
3122 * @param pHCPhys Where to store the HC Physical address and its flags.
3123 *
3124 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3125 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3126 */
3127DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3128{
3129 PPGMRAMRANGE pRam;
3130 PPGMPAGE pPage;
3131 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3132 if (VBOX_FAILURE(rc))
3133 {
3134 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3135 *pHCPhys = 0; /* ditto */
3136 return rc;
3137 }
3138 RTGCPHYS off = GCPhys - pRam->GCPhys;
3139
3140 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3141 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3142 {
3143 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3144#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3145 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3146 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3147#else
3148 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3149#endif
3150 return VINF_SUCCESS;
3151 }
3152 if (pRam->pvR3)
3153 {
3154 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3155 return VINF_SUCCESS;
3156 }
3157 *pHCPtr = 0;
3158 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3159}
3160
3161
3162/**
3163 * Clears flags associated with a RAM address.
3164 *
3165 * @returns VBox status code.
3166 * @param pPGM PGM handle.
3167 * @param GCPhys Guest context physical address.
3168 * @param fFlags fFlags to clear. (Bits 0-11.)
3169 */
3170DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3171{
3172 PPGMPAGE pPage;
3173 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3174 if (VBOX_FAILURE(rc))
3175 return rc;
3176
3177 fFlags &= ~X86_PTE_PAE_PG_MASK;
3178 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3179 return VINF_SUCCESS;
3180}
3181
3182
3183/**
3184 * Clears flags associated with a RAM address.
3185 *
3186 * @returns VBox status code.
3187 * @param pPGM PGM handle.
3188 * @param GCPhys Guest context physical address.
3189 * @param fFlags fFlags to clear. (Bits 0-11.)
3190 * @param ppRamHint Where to read and store the ram list hint.
3191 * The caller initializes this to NULL before the call.
3192 */
3193DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3194{
3195 PPGMPAGE pPage;
3196 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3197 if (VBOX_FAILURE(rc))
3198 return rc;
3199
3200 fFlags &= ~X86_PTE_PAE_PG_MASK;
3201 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3202 return VINF_SUCCESS;
3203}
3204
3205/**
3206 * Sets (bitwise OR) flags associated with a RAM address.
3207 *
3208 * @returns VBox status code.
3209 * @param pPGM PGM handle.
3210 * @param GCPhys Guest context physical address.
3211 * @param fFlags fFlags to set clear. (Bits 0-11.)
3212 */
3213DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3214{
3215 PPGMPAGE pPage;
3216 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3217 if (VBOX_FAILURE(rc))
3218 return rc;
3219
3220 fFlags &= ~X86_PTE_PAE_PG_MASK;
3221 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3222 return VINF_SUCCESS;
3223}
3224
3225
3226/**
3227 * Sets (bitwise OR) flags associated with a RAM address.
3228 *
3229 * @returns VBox status code.
3230 * @param pPGM PGM handle.
3231 * @param GCPhys Guest context physical address.
3232 * @param fFlags fFlags to set clear. (Bits 0-11.)
3233 * @param ppRamHint Where to read and store the ram list hint.
3234 * The caller initializes this to NULL before the call.
3235 */
3236DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3237{
3238 PPGMPAGE pPage;
3239 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3240 if (VBOX_FAILURE(rc))
3241 return rc;
3242
3243 fFlags &= ~X86_PTE_PAE_PG_MASK;
3244 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3245 return VINF_SUCCESS;
3246}
3247
3248/**
3249 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3250 * Takes PSE-36 into account.
3251 *
3252 * @returns guest physical address
3253 * @param pPGM Pointer to the PGM instance data.
3254 * @param Pde Guest Pde
3255 */
3256DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3257{
3258 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3259 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3260
3261 return GCPhys & pPGM->GCPhys4MBPSEMask;
3262}
3263
3264/**
3265 * Gets the page directory for the specified address.
3266 *
3267 * @returns Pointer to the page directory in question.
3268 * @returns NULL if the page directory is not present or on an invalid page.
3269 * @param pPGM Pointer to the PGM instance data.
3270 * @param GCPtr The address.
3271 */
3272DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3273{
3274 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3275 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3276 {
3277 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3278 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3279
3280 /* cache is out-of-sync. */
3281 PX86PDPAE pPD;
3282 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3283 if (VBOX_SUCCESS(rc))
3284 return pPD;
3285 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3286 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3287 }
3288 return NULL;
3289}
3290
3291
3292/**
3293 * Gets the page directory entry for the specified address.
3294 *
3295 * @returns Pointer to the page directory entry in question.
3296 * @returns NULL if the page directory is not present or on an invalid page.
3297 * @param pPGM Pointer to the PGM instance data.
3298 * @param GCPtr The address.
3299 */
3300DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3301{
3302 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3303 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3304 {
3305 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3306 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3307 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3308
3309 /* The cache is out-of-sync. */
3310 PX86PDPAE pPD;
3311 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3312 if (VBOX_SUCCESS(rc))
3313 return &pPD->a[iPD];
3314 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3315 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3316 }
3317 return NULL;
3318}
3319
3320
3321/**
3322 * Gets the page directory entry for the specified address.
3323 *
3324 * @returns The page directory entry in question.
3325 * @returns A non-present entry if the page directory is not present or on an invalid page.
3326 * @param pPGM Pointer to the PGM instance data.
3327 * @param GCPtr The address.
3328 */
3329DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3330{
3331 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3332 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3333 {
3334 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3335 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3336 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3337
3338 /* cache is out-of-sync. */
3339 PX86PDPAE pPD;
3340 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3341 if (VBOX_SUCCESS(rc))
3342 return pPD->a[iPD].u;
3343 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3344 }
3345 return 0ULL;
3346}
3347
3348
3349/**
3350 * Gets the page directory pointer table entry for the specified address
3351 * and returns the index into the page directory
3352 *
3353 * @returns Pointer to the page directory in question.
3354 * @returns NULL if the page directory is not present or on an invalid page.
3355 * @param pPGM Pointer to the PGM instance data.
3356 * @param GCPtr The address.
3357 * @param piPD Receives the index into the returned page directory
3358 */
3359DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3360{
3361 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3362 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3363 {
3364 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3365 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3366 {
3367 *piPD = iPD;
3368 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3369 }
3370
3371 /* cache is out-of-sync. */
3372 PX86PDPAE pPD;
3373 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3374 if (VBOX_SUCCESS(rc))
3375 {
3376 *piPD = iPD;
3377 return pPD;
3378 }
3379 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3380 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3381 }
3382 return NULL;
3383}
3384
3385#ifndef IN_GC
3386/**
3387 * Gets the page directory pointer entry for the specified address.
3388 *
3389 * @returns Pointer to the page directory pointer entry in question.
3390 * @returns NULL if the page directory is not present or on an invalid page.
3391 * @param pPGM Pointer to the PGM instance data.
3392 * @param GCPtr The address.
3393 * @param ppPml4e Page Map Level-4 Entry (out)
3394 */
3395DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3396{
3397 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3398
3399 Assert(pPGM->pGstPaePML4HC);
3400 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3401 if ((*ppPml4e)->n.u1Present)
3402 {
3403 PX86PDPT pPdpt;
3404 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3405 if (VBOX_FAILURE(rc))
3406 {
3407 AssertFailed();
3408 return NULL;
3409 }
3410 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3411 return &pPdpt->a[iPdPt];
3412 }
3413 return NULL;
3414}
3415
3416/**
3417 * Gets the page directory entry for the specified address.
3418 *
3419 * @returns The page directory entry in question.
3420 * @returns A non-present entry if the page directory is not present or on an invalid page.
3421 * @param pPGM Pointer to the PGM instance data.
3422 * @param GCPtr The address.
3423 * @param ppPml4e Page Map Level-4 Entry (out)
3424 * @param pPdpe Page directory pointer table entry (out)
3425 */
3426DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3427{
3428 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3429
3430 Assert(pPGM->pGstPaePML4HC);
3431 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3432 if ((*ppPml4e)->n.u1Present)
3433 {
3434 PX86PDPT pPdptTemp;
3435 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3436 if (VBOX_FAILURE(rc))
3437 {
3438 AssertFailed();
3439 return 0ULL;
3440 }
3441
3442 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3443 *pPdpe = pPdptTemp->a[iPdPt];
3444 if (pPdpe->n.u1Present)
3445 {
3446 PX86PDPAE pPD;
3447
3448 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3449 if (VBOX_FAILURE(rc))
3450 {
3451 AssertFailed();
3452 return 0ULL;
3453 }
3454 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3455 return pPD->a[iPD].u;
3456 }
3457 }
3458 return 0ULL;
3459}
3460
3461/**
3462 * Gets the page directory entry for the specified address.
3463 *
3464 * @returns The page directory entry in question.
3465 * @returns A non-present entry if the page directory is not present or on an invalid page.
3466 * @param pPGM Pointer to the PGM instance data.
3467 * @param GCPtr The address.
3468 */
3469DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3470{
3471 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3472
3473 Assert(pPGM->pGstPaePML4HC);
3474 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3475 {
3476 PX86PDPT pPdptTemp;
3477 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3478 if (VBOX_FAILURE(rc))
3479 {
3480 AssertFailed();
3481 return 0ULL;
3482 }
3483
3484 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3485 if (pPdptTemp->a[iPdPt].n.u1Present)
3486 {
3487 PX86PDPAE pPD;
3488
3489 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3490 if (VBOX_FAILURE(rc))
3491 {
3492 AssertFailed();
3493 return 0ULL;
3494 }
3495 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3496 return pPD->a[iPD].u;
3497 }
3498 }
3499 return 0ULL;
3500}
3501
3502/**
3503 * Gets the page directory entry for the specified address.
3504 *
3505 * @returns Pointer to the page directory entry in question.
3506 * @returns NULL if the page directory is not present or on an invalid page.
3507 * @param pPGM Pointer to the PGM instance data.
3508 * @param GCPtr The address.
3509 */
3510DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3511{
3512 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3513
3514 Assert(pPGM->pGstPaePML4HC);
3515 if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3516 {
3517 PX86PDPT pPdptTemp;
3518 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3519 if (VBOX_FAILURE(rc))
3520 {
3521 AssertFailed();
3522 return NULL;
3523 }
3524
3525 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3526 if (pPdptTemp->a[iPdPt].n.u1Present)
3527 {
3528 PX86PDPAE pPD;
3529
3530 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3531 if (VBOX_FAILURE(rc))
3532 {
3533 AssertFailed();
3534 return NULL;
3535 }
3536 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3537 return &pPD->a[iPD];
3538 }
3539 }
3540 return NULL;
3541}
3542
3543
3544/**
3545 * Gets the GUEST page directory pointer for the specified address.
3546 *
3547 * @returns The page directory in question.
3548 * @returns NULL if the page directory is not present or on an invalid page.
3549 * @param pPGM Pointer to the PGM instance data.
3550 * @param GCPtr The address.
3551 * @param ppPml4e Page Map Level-4 Entry (out)
3552 * @param pPdpe Page directory pointer table entry (out)
3553 * @param piPD Receives the index into the returned page directory
3554 */
3555DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3556{
3557 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3558
3559 Assert(pPGM->pGstPaePML4HC);
3560 *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3561 if ((*ppPml4e)->n.u1Present)
3562 {
3563 PX86PDPT pPdptTemp;
3564 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3565 if (VBOX_FAILURE(rc))
3566 {
3567 AssertFailed();
3568 return 0ULL;
3569 }
3570
3571 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3572 *pPdpe = pPdptTemp->a[iPdPt];
3573 if (pPdpe->n.u1Present)
3574 {
3575 PX86PDPAE pPD;
3576
3577 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3578 if (VBOX_FAILURE(rc))
3579 {
3580 AssertFailed();
3581 return 0ULL;
3582 }
3583 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3584 return pPD;
3585 }
3586 }
3587 return 0ULL;
3588}
3589
3590/**
3591 * Gets the GUEST page directory pointer for the specified address.
3592 *
3593 * @returns The page directory in question.
3594 * @returns NULL if the page directory is not present or on an invalid page.
3595 * @param pPGM Pointer to the PGM instance data.
3596 * @param GCPtr The address.
3597 * @param piPD Receives the index into the returned page directory
3598 */
3599DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3600{
3601 PX86PML4E pPml4e;
3602 PX86PDPE pPdpe;
3603 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3604
3605 Assert(pPGM->pGstPaePML4HC);
3606 pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3607 if (pPml4e->n.u1Present)
3608 {
3609 PX86PDPT pPdptTemp;
3610 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3611 if (VBOX_FAILURE(rc))
3612 {
3613 AssertFailed();
3614 return 0ULL;
3615 }
3616
3617 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3618 pPdpe = &pPdptTemp->a[iPdPt];
3619 if (pPdpe->n.u1Present)
3620 {
3621 PX86PDPAE pPD;
3622
3623 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3624 if (VBOX_FAILURE(rc))
3625 {
3626 AssertFailed();
3627 return 0ULL;
3628 }
3629 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3630 return pPD;
3631 }
3632 }
3633 return 0ULL;
3634}
3635
3636#endif /* !IN_GC */
3637
3638/**
3639 * Checks if any of the specified page flags are set for the given page.
3640 *
3641 * @returns true if any of the flags are set.
3642 * @returns false if all the flags are clear.
3643 * @param pPGM PGM handle.
3644 * @param GCPhys The GC physical address.
3645 * @param fFlags The flags to check for.
3646 */
3647DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3648{
3649 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3650 return pPage
3651 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3652}
3653
3654
3655/**
3656 * Gets the page state for a physical handler.
3657 *
3658 * @returns The physical handler page state.
3659 * @param pCur The physical handler in question.
3660 */
3661DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3662{
3663 switch (pCur->enmType)
3664 {
3665 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3666 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3667
3668 case PGMPHYSHANDLERTYPE_MMIO:
3669 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3670 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3671
3672 default:
3673 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3674 }
3675}
3676
3677
3678/**
3679 * Gets the page state for a virtual handler.
3680 *
3681 * @returns The virtual handler page state.
3682 * @param pCur The virtual handler in question.
3683 * @remarks This should never be used on a hypervisor access handler.
3684 */
3685DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3686{
3687 switch (pCur->enmType)
3688 {
3689 case PGMVIRTHANDLERTYPE_WRITE:
3690 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3691 case PGMVIRTHANDLERTYPE_ALL:
3692 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3693 default:
3694 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3695 }
3696}
3697
3698
3699/**
3700 * Clears one physical page of a virtual handler
3701 *
3702 * @param pPGM Pointer to the PGM instance.
3703 * @param pCur Virtual handler structure
3704 * @param iPage Physical page index
3705 *
3706 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3707 * need to care about other handlers in the same page.
3708 */
3709DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3710{
3711 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3712
3713 /*
3714 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3715 */
3716#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3717 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3718 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3719 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3720#endif
3721 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3722 {
3723 /* We're the head of the alias chain. */
3724 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3725#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3726 AssertReleaseMsg(pRemove != NULL,
3727 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3728 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3729 AssertReleaseMsg(pRemove == pPhys2Virt,
3730 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3731 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3732 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3733 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3734#endif
3735 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3736 {
3737 /* Insert the next list in the alias chain into the tree. */
3738 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3739#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3740 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3741 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3742 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3743#endif
3744 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3745 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3746 AssertRelease(fRc);
3747 }
3748 }
3749 else
3750 {
3751 /* Locate the previous node in the alias chain. */
3752 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3753#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3754 AssertReleaseMsg(pPrev != pPhys2Virt,
3755 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3756 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3757#endif
3758 for (;;)
3759 {
3760 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3761 if (pNext == pPhys2Virt)
3762 {
3763 /* unlink. */
3764 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3765 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3766 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3767 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3768 else
3769 {
3770 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3771 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3772 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3773 }
3774 break;
3775 }
3776
3777 /* next */
3778 if (pNext == pPrev)
3779 {
3780#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3781 AssertReleaseMsg(pNext != pPrev,
3782 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3783 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3784#endif
3785 break;
3786 }
3787 pPrev = pNext;
3788 }
3789 }
3790 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3791 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
3792 pPhys2Virt->offNextAlias = 0;
3793 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3794
3795 /*
3796 * Clear the ram flags for this page.
3797 */
3798 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3799 AssertReturnVoid(pPage);
3800 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3801}
3802
3803
3804/**
3805 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3806 *
3807 * @returns Pointer to the shadow page structure.
3808 * @param pPool The pool.
3809 * @param HCPhys The HC physical address of the shadow page.
3810 */
3811DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3812{
3813 /*
3814 * Look up the page.
3815 */
3816 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3817 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3818 return pPage;
3819}
3820
3821
3822/**
3823 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3824 *
3825 * @returns Pointer to the shadow page structure.
3826 * @param pPool The pool.
3827 * @param idx The pool page index.
3828 */
3829DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3830{
3831 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3832 return &pPool->aPages[idx];
3833}
3834
3835
3836#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3837/**
3838 * Clear references to guest physical memory.
3839 *
3840 * @param pPool The pool.
3841 * @param pPoolPage The pool page.
3842 * @param pPhysPage The physical guest page tracking structure.
3843 */
3844DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3845{
3846 /*
3847 * Just deal with the simple case here.
3848 */
3849#ifdef LOG_ENABLED
3850 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3851#endif
3852 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3853 if (cRefs == 1)
3854 {
3855 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3856 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3857 }
3858 else
3859 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3860 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3861}
3862#endif
3863
3864
3865#ifdef PGMPOOL_WITH_CACHE
3866/**
3867 * Moves the page to the head of the age list.
3868 *
3869 * This is done when the cached page is used in one way or another.
3870 *
3871 * @param pPool The pool.
3872 * @param pPage The cached page.
3873 * @todo inline in PGMInternal.h!
3874 */
3875DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3876{
3877 /*
3878 * Move to the head of the age list.
3879 */
3880 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3881 {
3882 /* unlink */
3883 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3884 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3885 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3886 else
3887 pPool->iAgeTail = pPage->iAgePrev;
3888
3889 /* insert at head */
3890 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3891 pPage->iAgeNext = pPool->iAgeHead;
3892 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3893 pPool->iAgeHead = pPage->idx;
3894 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3895 }
3896}
3897#endif /* PGMPOOL_WITH_CACHE */
3898
3899/**
3900 * Tells if mappings are to be put into the shadow page table or not
3901 *
3902 * @returns boolean result
3903 * @param pVM VM handle.
3904 */
3905
3906DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3907{
3908#ifdef IN_RING0
3909 /* There are no mappings in VT-x and AMD-V mode. */
3910 Assert(pPGM->fDisableMappings);
3911 return false;
3912#else
3913 return !pPGM->fDisableMappings;
3914#endif
3915}
3916
3917/** @} */
3918
3919#endif
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