VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 14145

Last change on this file since 14145 was 14145, checked in by vboxsync, 16 years ago

PGM: Some more uint64_t -> X86union return. (btw. doing this because it saves space and permits const locals).
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File size: 175.9 KB
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1/* $Id: PGMInternal.h 14145 2008-11-12 21:59:25Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) \
201 ( (uGstType) >= PGM_TYPE_32BIT \
202 && (uShwType) != PGM_TYPE_NESTED \
203 && (uShwType) != PGM_TYPE_EPT)
204
205/** Macro for checking if the guest supports the NX bit.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_NX(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_PAE \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215
216/** @def PGM_HCPHYS_2_PTR
217 * Maps a HC physical page pool address to a virtual address.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM handle.
221 * @param HCPhys The HC physical address to map to a virtual one.
222 * @param ppv Where to store the virtual address. No need to cast this.
223 *
224 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225 * small page window employeed by that function. Be careful.
226 * @remark There is no need to assert on the result.
227 */
228#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
229# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231#else
232# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
234#endif
235
236/** @def PGM_GCPHYS_2_PTR
237 * Maps a GC physical page address to a virtual address.
238 *
239 * @returns VBox status code.
240 * @param pVM The VM handle.
241 * @param GCPhys The GC physical address to map to a virtual one.
242 * @param ppv Where to store the virtual address. No need to cast this.
243 *
244 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
245 * small page window employeed by that function. Be careful.
246 * @remark There is no need to assert on the result.
247 */
248#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
249# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
250 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
251#else
252# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
253 PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
254#endif
255
256/** @def PGM_GCPHYS_2_PTR_EX
257 * Maps a unaligned GC physical page address to a virtual address.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM handle.
261 * @param GCPhys The GC physical address to map to a virtual one.
262 * @param ppv Where to store the virtual address. No need to cast this.
263 *
264 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
265 * small page window employeed by that function. Be careful.
266 * @remark There is no need to assert on the result.
267 */
268#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
269# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
270 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
271#else
272# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
273 PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
274#endif
275
276/** @def PGM_INVL_PG
277 * Invalidates a page when in GC does nothing in HC.
278 *
279 * @param GCVirt The virtual address of the page to invalidate.
280 */
281#ifdef IN_RC
282# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
283#elif defined(IN_RING0)
284# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
285#else
286# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
287#endif
288
289/** @def PGM_INVL_BIG_PG
290 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
291 *
292 * @param GCVirt The virtual address within the page directory to invalidate.
293 */
294#ifdef IN_RC
295# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
296#elif defined(IN_RING0)
297# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
298#else
299# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
300#endif
301
302/** @def PGM_INVL_GUEST_TLBS()
303 * Invalidates all guest TLBs.
304 */
305#ifdef IN_RC
306# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
307#elif defined(IN_RING0)
308# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
309#else
310# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
311#endif
312
313
314/**
315 * Structure for tracking GC Mappings.
316 *
317 * This structure is used by linked list in both GC and HC.
318 */
319typedef struct PGMMAPPING
320{
321 /** Pointer to next entry. */
322 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
323 /** Pointer to next entry. */
324 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
325 /** Pointer to next entry. */
326 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
327#if GC_ARCH_BITS == 64
328 RTRCPTR padding0;
329#endif
330 /** Start Virtual address. */
331 RTGCPTR GCPtr;
332 /** Last Virtual address (inclusive). */
333 RTGCPTR GCPtrLast;
334 /** Range size (bytes). */
335 RTGCPTR cb;
336 /** Pointer to relocation callback function. */
337 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
338 /** User argument to the callback. */
339 R3PTRTYPE(void *) pvUser;
340 /** Mapping description / name. For easing debugging. */
341 R3PTRTYPE(const char *) pszDesc;
342 /** Number of page tables. */
343 RTUINT cPTs;
344#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
345 RTUINT uPadding1; /**< Alignment padding. */
346#endif
347 /** Array of page table mapping data. Each entry
348 * describes one page table. The array can be longer
349 * than the declared length.
350 */
351 struct
352 {
353 /** The HC physical address of the page table. */
354 RTHCPHYS HCPhysPT;
355 /** The HC physical address of the first PAE page table. */
356 RTHCPHYS HCPhysPaePT0;
357 /** The HC physical address of the second PAE page table. */
358 RTHCPHYS HCPhysPaePT1;
359 /** The HC virtual address of the 32-bit page table. */
360 R3PTRTYPE(PX86PT) pPTR3;
361 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
362 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
363 /** The GC virtual address of the 32-bit page table. */
364 RCPTRTYPE(PX86PT) pPTRC;
365 /** The GC virtual address of the two PAE page table. */
366 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
367 /** The GC virtual address of the 32-bit page table. */
368 R0PTRTYPE(PX86PT) pPTR0;
369 /** The GC virtual address of the two PAE page table. */
370 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
371 } aPTs[1];
372} PGMMAPPING;
373/** Pointer to structure for tracking GC Mappings. */
374typedef struct PGMMAPPING *PPGMMAPPING;
375
376
377/**
378 * Physical page access handler structure.
379 *
380 * This is used to keep track of physical address ranges
381 * which are being monitored in some kind of way.
382 */
383typedef struct PGMPHYSHANDLER
384{
385 AVLROGCPHYSNODECORE Core;
386 /** Access type. */
387 PGMPHYSHANDLERTYPE enmType;
388 /** Number of pages to update. */
389 uint32_t cPages;
390 /** Pointer to R3 callback function. */
391 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
392 /** User argument for R3 handlers. */
393 R3PTRTYPE(void *) pvUserR3;
394 /** Pointer to R0 callback function. */
395 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
396 /** User argument for R0 handlers. */
397 R0PTRTYPE(void *) pvUserR0;
398 /** Pointer to GC callback function. */
399 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
400 /** User argument for RC handlers. */
401 RCPTRTYPE(void *) pvUserRC;
402 /** Description / Name. For easing debugging. */
403 R3PTRTYPE(const char *) pszDesc;
404#ifdef VBOX_WITH_STATISTICS
405 /** Profiling of this handler. */
406 STAMPROFILE Stat;
407#endif
408} PGMPHYSHANDLER;
409/** Pointer to a physical page access handler structure. */
410typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
411
412
413/**
414 * Cache node for the physical addresses covered by a virtual handler.
415 */
416typedef struct PGMPHYS2VIRTHANDLER
417{
418 /** Core node for the tree based on physical ranges. */
419 AVLROGCPHYSNODECORE Core;
420 /** Offset from this struct to the PGMVIRTHANDLER structure. */
421 int32_t offVirtHandler;
422 /** Offset of the next alias relative to this one.
423 * Bit 0 is used for indicating whether we're in the tree.
424 * Bit 1 is used for indicating that we're the head node.
425 */
426 int32_t offNextAlias;
427} PGMPHYS2VIRTHANDLER;
428/** Pointer to a phys to virtual handler structure. */
429typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
430
431/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
432 * node is in the tree. */
433#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
434/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
435 * node is in the head of an alias chain.
436 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
437#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
438/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
439#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
440
441
442/**
443 * Virtual page access handler structure.
444 *
445 * This is used to keep track of virtual address ranges
446 * which are being monitored in some kind of way.
447 */
448typedef struct PGMVIRTHANDLER
449{
450 /** Core node for the tree based on virtual ranges. */
451 AVLROGCPTRNODECORE Core;
452 /** Size of the range (in bytes). */
453 RTGCPTR cb;
454 /** Number of cache pages. */
455 uint32_t cPages;
456 /** Access type. */
457 PGMVIRTHANDLERTYPE enmType;
458 /** Pointer to the RC callback function. */
459 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
460#if HC_ARCH_BITS == 64
461 RTRCPTR padding;
462#endif
463 /** Pointer to the R3 callback function for invalidation. */
464 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
465 /** Pointer to the R3 callback function. */
466 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
467 /** Description / Name. For easing debugging. */
468 R3PTRTYPE(const char *) pszDesc;
469#ifdef VBOX_WITH_STATISTICS
470 /** Profiling of this handler. */
471 STAMPROFILE Stat;
472#endif
473 /** Array of cached physical addresses for the monitored ranged. */
474 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
475} PGMVIRTHANDLER;
476/** Pointer to a virtual page access handler structure. */
477typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
478
479
480/**
481 * Page type.
482 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
483 * @todo convert to \#defines.
484 */
485typedef enum PGMPAGETYPE
486{
487 /** The usual invalid zero entry. */
488 PGMPAGETYPE_INVALID = 0,
489 /** RAM page. (RWX) */
490 PGMPAGETYPE_RAM,
491 /** MMIO2 page. (RWX) */
492 PGMPAGETYPE_MMIO2,
493 /** Shadowed ROM. (RWX) */
494 PGMPAGETYPE_ROM_SHADOW,
495 /** ROM page. (R-X) */
496 PGMPAGETYPE_ROM,
497 /** MMIO page. (---) */
498 PGMPAGETYPE_MMIO,
499 /** End of valid entries. */
500 PGMPAGETYPE_END
501} PGMPAGETYPE;
502AssertCompile(PGMPAGETYPE_END < 7);
503
504/** @name Page type predicates.
505 * @{ */
506#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
507#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
508#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
509#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
510#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
511/** @} */
512
513
514/**
515 * A Physical Guest Page tracking structure.
516 *
517 * The format of this structure is complicated because we have to fit a lot
518 * of information into as few bits as possible. The format is also subject
519 * to change (there is one comming up soon). Which means that for we'll be
520 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
521 * accessess to the structure.
522 */
523typedef struct PGMPAGE
524{
525 /** The physical address and a whole lot of other stuff. All bits are used! */
526 RTHCPHYS HCPhys;
527 /** The page state. */
528 uint32_t u2StateX : 2;
529 /** Flag indicating that a write monitored page was written to when set. */
530 uint32_t fWrittenToX : 1;
531 /** For later. */
532 uint32_t fSomethingElse : 1;
533 /** The Page ID.
534 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
535 * The HCPhys will be 100% static. */
536 uint32_t idPageX : 28;
537 /** The page type (PGMPAGETYPE). */
538 uint32_t u3Type : 3;
539 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
540 uint32_t u2HandlerPhysStateX : 2;
541 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
542 uint32_t u2HandlerVirtStateX : 2;
543 uint32_t u29B : 25;
544} PGMPAGE;
545AssertCompileSize(PGMPAGE, 16);
546/** Pointer to a physical guest page. */
547typedef PGMPAGE *PPGMPAGE;
548/** Pointer to a const physical guest page. */
549typedef const PGMPAGE *PCPGMPAGE;
550/** Pointer to a physical guest page pointer. */
551typedef PPGMPAGE *PPPGMPAGE;
552
553
554/**
555 * Clears the page structure.
556 * @param pPage Pointer to the physical guest page tracking structure.
557 */
558#define PGM_PAGE_CLEAR(pPage) \
559 do { \
560 (pPage)->HCPhys = 0; \
561 (pPage)->u2StateX = 0; \
562 (pPage)->fWrittenToX = 0; \
563 (pPage)->fSomethingElse = 0; \
564 (pPage)->idPageX = 0; \
565 (pPage)->u3Type = 0; \
566 (pPage)->u29B = 0; \
567 } while (0)
568
569/**
570 * Initializes the page structure.
571 * @param pPage Pointer to the physical guest page tracking structure.
572 */
573#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
574 do { \
575 (pPage)->HCPhys = (_HCPhys); \
576 (pPage)->u2StateX = (_uState); \
577 (pPage)->fWrittenToX = 0; \
578 (pPage)->fSomethingElse = 0; \
579 (pPage)->idPageX = (_idPage); \
580 /*(pPage)->u3Type = (_uType); - later */ \
581 PGM_PAGE_SET_TYPE(pPage, _uType); \
582 (pPage)->u29B = 0; \
583 } while (0)
584
585/**
586 * Initializes the page structure of a ZERO page.
587 * @param pPage Pointer to the physical guest page tracking structure.
588 */
589#ifdef VBOX_WITH_NEW_PHYS_CODE
590# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
591 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
592#else
593# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
594 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
595#endif
596/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
597# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
598 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
599
600
601/** @name The Page state, PGMPAGE::u2StateX.
602 * @{ */
603/** The zero page.
604 * This is a per-VM page that's never ever mapped writable. */
605#define PGM_PAGE_STATE_ZERO 0
606/** A allocated page.
607 * This is a per-VM page allocated from the page pool (or wherever
608 * we get MMIO2 pages from if the type is MMIO2).
609 */
610#define PGM_PAGE_STATE_ALLOCATED 1
611/** A allocated page that's being monitored for writes.
612 * The shadow page table mappings are read-only. When a write occurs, the
613 * fWrittenTo member is set, the page remapped as read-write and the state
614 * moved back to allocated. */
615#define PGM_PAGE_STATE_WRITE_MONITORED 2
616/** The page is shared, aka. copy-on-write.
617 * This is a page that's shared with other VMs. */
618#define PGM_PAGE_STATE_SHARED 3
619/** @} */
620
621
622/**
623 * Gets the page state.
624 * @returns page state (PGM_PAGE_STATE_*).
625 * @param pPage Pointer to the physical guest page tracking structure.
626 */
627#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
628
629/**
630 * Sets the page state.
631 * @param pPage Pointer to the physical guest page tracking structure.
632 * @param _uState The new page state.
633 */
634#define PGM_PAGE_SET_STATE(pPage, _uState) \
635 do { (pPage)->u2StateX = (_uState); } while (0)
636
637
638/**
639 * Gets the host physical address of the guest page.
640 * @returns host physical address (RTHCPHYS).
641 * @param pPage Pointer to the physical guest page tracking structure.
642 */
643#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
644
645/**
646 * Sets the host physical address of the guest page.
647 * @param pPage Pointer to the physical guest page tracking structure.
648 * @param _HCPhys The new host physical address.
649 */
650#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
651 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
652 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
653
654/**
655 * Get the Page ID.
656 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
657 * @param pPage Pointer to the physical guest page tracking structure.
658 */
659#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
660/* later:
661#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
662 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
663*/
664/**
665 * Sets the Page ID.
666 * @param pPage Pointer to the physical guest page tracking structure.
667 */
668#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
669/* later:
670#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
671 | ((_idPage) & 0xfff) \
672 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
673*/
674
675/**
676 * Get the Chunk ID.
677 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
678 * @param pPage Pointer to the physical guest page tracking structure.
679 */
680#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
681/* later:
682#if GMM_CHUNKID_SHIFT == 12
683# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
684#elif GMM_CHUNKID_SHIFT > 12
685# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
686#elif GMM_CHUNKID_SHIFT < 12
687# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
688 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
689#else
690# error "GMM_CHUNKID_SHIFT isn't defined or something."
691#endif
692*/
693
694/**
695 * Get the index of the page within the allocaiton chunk.
696 * @returns The page index.
697 * @param pPage Pointer to the physical guest page tracking structure.
698 */
699#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
700/* later:
701#if GMM_CHUNKID_SHIFT <= 12
702# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
703#else
704# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
705 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
706#endif
707*/
708
709
710/**
711 * Gets the page type.
712 * @returns The page type.
713 * @param pPage Pointer to the physical guest page tracking structure.
714 */
715#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
716
717/**
718 * Sets the page type.
719 * @param pPage Pointer to the physical guest page tracking structure.
720 * @param _enmType The new page type (PGMPAGETYPE).
721 */
722#ifdef VBOX_WITH_NEW_PHYS_CODE
723#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
724 do { (pPage)->u3Type = (_enmType); } while (0)
725#else
726#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
727 do { \
728 (pPage)->u3Type = (_enmType); \
729 if ((_enmType) == PGMPAGETYPE_ROM) \
730 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
731 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
732 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
733 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
734 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
735 } while (0)
736#endif
737
738
739/**
740 * Checks if the page is 'reserved'.
741 * @returns true/false.
742 * @param pPage Pointer to the physical guest page tracking structure.
743 */
744#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
745
746/**
747 * Checks if the page is marked for MMIO.
748 * @returns true/false.
749 * @param pPage Pointer to the physical guest page tracking structure.
750 */
751#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
752
753/**
754 * Checks if the page is backed by the ZERO page.
755 * @returns true/false.
756 * @param pPage Pointer to the physical guest page tracking structure.
757 */
758#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
759
760/**
761 * Checks if the page is backed by a SHARED page.
762 * @returns true/false.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 */
765#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
766
767
768/**
769 * Marks the paget as written to (for GMM change monitoring).
770 * @param pPage Pointer to the physical guest page tracking structure.
771 */
772#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
773
774/**
775 * Clears the written-to indicator.
776 * @param pPage Pointer to the physical guest page tracking structure.
777 */
778#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
779
780/**
781 * Checks if the page was marked as written-to.
782 * @returns true/false.
783 * @param pPage Pointer to the physical guest page tracking structure.
784 */
785#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
786
787
788/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
789 *
790 * @remarks The values are assigned in order of priority, so we can calculate
791 * the correct state for a page with different handlers installed.
792 * @{ */
793/** No handler installed. */
794#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
795/** Monitoring is temporarily disabled. */
796#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
797/** Write access is monitored. */
798#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
799/** All access is monitored. */
800#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
801/** @} */
802
803/**
804 * Gets the physical access handler state of a page.
805 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
806 * @param pPage Pointer to the physical guest page tracking structure.
807 */
808#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
809
810/**
811 * Sets the physical access handler state of a page.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 * @param _uState The new state value.
814 */
815#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
816 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
817
818/**
819 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
820 * @returns true/false
821 * @param pPage Pointer to the physical guest page tracking structure.
822 */
823#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
824
825/**
826 * Checks if the page has any active physical access handlers.
827 * @returns true/false
828 * @param pPage Pointer to the physical guest page tracking structure.
829 */
830#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
831
832
833/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
834 *
835 * @remarks The values are assigned in order of priority, so we can calculate
836 * the correct state for a page with different handlers installed.
837 * @{ */
838/** No handler installed. */
839#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
840/* 1 is reserved so the lineup is identical with the physical ones. */
841/** Write access is monitored. */
842#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
843/** All access is monitored. */
844#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
845/** @} */
846
847/**
848 * Gets the virtual access handler state of a page.
849 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
853
854/**
855 * Sets the virtual access handler state of a page.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 * @param _uState The new state value.
858 */
859#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
860 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
861
862/**
863 * Checks if the page has any virtual access handlers.
864 * @returns true/false
865 * @param pPage Pointer to the physical guest page tracking structure.
866 */
867#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
868
869/**
870 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
871 * virtual handlers.
872 * @returns true/false
873 * @param pPage Pointer to the physical guest page tracking structure.
874 */
875#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
876
877
878
879/**
880 * Checks if the page has any access handlers, including temporarily disabled ones.
881 * @returns true/false
882 * @param pPage Pointer to the physical guest page tracking structure.
883 */
884#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
885 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
886 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
887
888/**
889 * Checks if the page has any active access handlers.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
894 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
895 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
896
897/**
898 * Checks if the page has any active access handlers catching all accesses.
899 * @returns true/false
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
903 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
904 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
905
906
907/**
908 * Ram range for GC Phys to HC Phys conversion.
909 *
910 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
911 * conversions too, but we'll let MM handle that for now.
912 *
913 * This structure is used by linked lists in both GC and HC.
914 */
915typedef struct PGMRAMRANGE
916{
917 /** Pointer to the next RAM range - for R3. */
918 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
919 /** Pointer to the next RAM range - for R0. */
920 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
921 /** Pointer to the next RAM range - for RC. */
922 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
923 /** Pointer alignment. */
924 RTRCPTR RCPtrAlignment;
925 /** Start of the range. Page aligned. */
926 RTGCPHYS GCPhys;
927 /** Last address in the range (inclusive). Page aligned (-1). */
928 RTGCPHYS GCPhysLast;
929 /** Size of the range. (Page aligned of course). */
930 RTGCPHYS cb;
931 /** MM_RAM_* flags */
932 uint32_t fFlags;
933 uint32_t u32Alignment; /**< alignment. */
934#ifndef VBOX_WITH_NEW_PHYS_CODE
935 /** R3 virtual lookup ranges for chunks.
936 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
937 * @remarks This is occationally accessed from ring-0!! (not darwin) */
938# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
939 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
940# else
941 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
942# endif
943#endif
944 /** Start of the HC mapping of the range. This is only used for MMIO2. */
945 R3PTRTYPE(void *) pvR3;
946 /** The range description. */
947 R3PTRTYPE(const char *) pszDesc;
948
949 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
950#ifdef VBOX_WITH_NEW_PHYS_CODE
951 uint32_t au32Reserved[2];
952#elif HC_ARCH_BITS == 32
953 uint32_t au32Reserved[1];
954#endif
955
956 /** Array of physical guest page tracking structures. */
957 PGMPAGE aPages[1];
958} PGMRAMRANGE;
959/** Pointer to Ram range for GC Phys to HC Phys conversion. */
960typedef PGMRAMRANGE *PPGMRAMRANGE;
961
962/** Return hc ptr corresponding to the ram range and physical offset */
963#define PGMRAMRANGE_GETHCPTR(pRam, off) \
964 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
965 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
966
967/**
968 * Per page tracking structure for ROM image.
969 *
970 * A ROM image may have a shadow page, in which case we may have
971 * two pages backing it. This structure contains the PGMPAGE for
972 * both while PGMRAMRANGE have a copy of the active one. It is
973 * important that these aren't out of sync in any regard other
974 * than page pool tracking data.
975 */
976typedef struct PGMROMPAGE
977{
978 /** The page structure for the virgin ROM page. */
979 PGMPAGE Virgin;
980 /** The page structure for the shadow RAM page. */
981 PGMPAGE Shadow;
982 /** The current protection setting. */
983 PGMROMPROT enmProt;
984 /** Pad the structure size to a multiple of 8. */
985 uint32_t u32Padding;
986} PGMROMPAGE;
987/** Pointer to a ROM page tracking structure. */
988typedef PGMROMPAGE *PPGMROMPAGE;
989
990
991/**
992 * A registered ROM image.
993 *
994 * This is needed to keep track of ROM image since they generally
995 * intrude into a PGMRAMRANGE. It also keeps track of additional
996 * info like the two page sets (read-only virgin and read-write shadow),
997 * the current state of each page.
998 *
999 * Because access handlers cannot easily be executed in a different
1000 * context, the ROM ranges needs to be accessible and in all contexts.
1001 */
1002typedef struct PGMROMRANGE
1003{
1004 /** Pointer to the next range - R3. */
1005 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1006 /** Pointer to the next range - R0. */
1007 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1008 /** Pointer to the next range - RC. */
1009 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1010 /** Pointer alignment */
1011 RTRCPTR GCPtrAlignment;
1012 /** Address of the range. */
1013 RTGCPHYS GCPhys;
1014 /** Address of the last byte in the range. */
1015 RTGCPHYS GCPhysLast;
1016 /** Size of the range. */
1017 RTGCPHYS cb;
1018 /** The flags (PGMPHYS_ROM_FLAG_*). */
1019 uint32_t fFlags;
1020 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1021 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1022 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1023 * This is used for strictness checks. */
1024 R3PTRTYPE(const void *) pvOriginal;
1025 /** The ROM description. */
1026 R3PTRTYPE(const char *) pszDesc;
1027 /** The per page tracking structures. */
1028 PGMROMPAGE aPages[1];
1029} PGMROMRANGE;
1030/** Pointer to a ROM range. */
1031typedef PGMROMRANGE *PPGMROMRANGE;
1032
1033
1034/**
1035 * A registered MMIO2 (= Device RAM) range.
1036 *
1037 * There are a few reason why we need to keep track of these
1038 * registrations. One of them is the deregistration & cleanup
1039 * stuff, while another is that the PGMRAMRANGE associated with
1040 * such a region may have to be removed from the ram range list.
1041 *
1042 * Overlapping with a RAM range has to be 100% or none at all. The
1043 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1044 * meditation will be raised if a partial overlap or an overlap of
1045 * ROM pages is encountered. On an overlap we will free all the
1046 * existing RAM pages and put in the ram range pages instead.
1047 */
1048typedef struct PGMMMIO2RANGE
1049{
1050 /** The owner of the range. (a device) */
1051 PPDMDEVINSR3 pDevInsR3;
1052 /** Pointer to the ring-3 mapping of the allocation. */
1053 RTR3PTR pvR3;
1054 /** Pointer to the next range - R3. */
1055 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1056 /** Whether it's mapped or not. */
1057 bool fMapped;
1058 /** Whether it's overlapping or not. */
1059 bool fOverlapping;
1060 /** The PCI region number.
1061 * @remarks This ASSUMES that nobody will ever really need to have multiple
1062 * PCI devices with matching MMIO region numbers on a single device. */
1063 uint8_t iRegion;
1064 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1065 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1066 /** The associated RAM range. */
1067 PGMRAMRANGE RamRange;
1068} PGMMMIO2RANGE;
1069/** Pointer to a MMIO2 range. */
1070typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1071
1072
1073
1074
1075/**
1076 * PGMPhysRead/Write cache entry
1077 */
1078typedef struct PGMPHYSCACHEENTRY
1079{
1080 /** R3 pointer to physical page. */
1081 R3PTRTYPE(uint8_t *) pbR3;
1082 /** GC Physical address for cache entry */
1083 RTGCPHYS GCPhys;
1084#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1085 RTGCPHYS u32Padding0; /**< alignment padding. */
1086#endif
1087} PGMPHYSCACHEENTRY;
1088
1089/**
1090 * PGMPhysRead/Write cache to reduce REM memory access overhead
1091 */
1092typedef struct PGMPHYSCACHE
1093{
1094 /** Bitmap of valid cache entries */
1095 uint64_t aEntries;
1096 /** Cache entries */
1097 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1098} PGMPHYSCACHE;
1099
1100
1101/** Pointer to an allocation chunk ring-3 mapping. */
1102typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1103/** Pointer to an allocation chunk ring-3 mapping pointer. */
1104typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1105
1106/**
1107 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1108 *
1109 * The primary tree (Core) uses the chunk id as key.
1110 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1111 */
1112typedef struct PGMCHUNKR3MAP
1113{
1114 /** The key is the chunk id. */
1115 AVLU32NODECORE Core;
1116 /** The key is the ageing sequence number. */
1117 AVLLU32NODECORE AgeCore;
1118 /** The current age thingy. */
1119 uint32_t iAge;
1120 /** The current reference count. */
1121 uint32_t volatile cRefs;
1122 /** The current permanent reference count. */
1123 uint32_t volatile cPermRefs;
1124 /** The mapping address. */
1125 void *pv;
1126} PGMCHUNKR3MAP;
1127
1128/**
1129 * Allocation chunk ring-3 mapping TLB entry.
1130 */
1131typedef struct PGMCHUNKR3MAPTLBE
1132{
1133 /** The chunk id. */
1134 uint32_t volatile idChunk;
1135#if HC_ARCH_BITS == 64
1136 uint32_t u32Padding; /**< alignment padding. */
1137#endif
1138 /** The chunk map. */
1139#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1140 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1141#else
1142 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1143#endif
1144} PGMCHUNKR3MAPTLBE;
1145/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1146typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1147
1148/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1149 * @remark Must be a power of two value. */
1150#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1151
1152/**
1153 * Allocation chunk ring-3 mapping TLB.
1154 *
1155 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1156 * At first glance this might look kinda odd since AVL trees are
1157 * supposed to give the most optimial lookup times of all trees
1158 * due to their balancing. However, take a tree with 1023 nodes
1159 * in it, that's 10 levels, meaning that most searches has to go
1160 * down 9 levels before they find what they want. This isn't fast
1161 * compared to a TLB hit. There is the factor of cache misses,
1162 * and of course the problem with trees and branch prediction.
1163 * This is why we use TLBs in front of most of the trees.
1164 *
1165 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1166 * difficult when we switch to the new inlined AVL trees (from kStuff).
1167 */
1168typedef struct PGMCHUNKR3MAPTLB
1169{
1170 /** The TLB entries. */
1171 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1172} PGMCHUNKR3MAPTLB;
1173
1174/**
1175 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1176 * @returns Chunk TLB index.
1177 * @param idChunk The Chunk ID.
1178 */
1179#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1180
1181
1182/**
1183 * Ring-3 guest page mapping TLB entry.
1184 * @remarks used in ring-0 as well at the moment.
1185 */
1186typedef struct PGMPAGER3MAPTLBE
1187{
1188 /** Address of the page. */
1189 RTGCPHYS volatile GCPhys;
1190 /** The guest page. */
1191#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1192 R3PTRTYPE(PPGMPAGE) volatile pPage;
1193#else
1194 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1195#endif
1196 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1197#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1198 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1199#else
1200 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1201#endif
1202 /** The address */
1203#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1204 R3PTRTYPE(void *) volatile pv;
1205#else
1206 R3R0PTRTYPE(void *) volatile pv;
1207#endif
1208#if HC_ARCH_BITS == 32
1209 uint32_t u32Padding; /**< alignment padding. */
1210#endif
1211} PGMPAGER3MAPTLBE;
1212/** Pointer to an entry in the HC physical TLB. */
1213typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1214
1215
1216/** The number of entries in the ring-3 guest page mapping TLB.
1217 * @remarks The value must be a power of two. */
1218#define PGM_PAGER3MAPTLB_ENTRIES 64
1219
1220/**
1221 * Ring-3 guest page mapping TLB.
1222 * @remarks used in ring-0 as well at the moment.
1223 */
1224typedef struct PGMPAGER3MAPTLB
1225{
1226 /** The TLB entries. */
1227 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1228} PGMPAGER3MAPTLB;
1229/** Pointer to the ring-3 guest page mapping TLB. */
1230typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1231
1232/**
1233 * Calculates the index of the TLB entry for the specified guest page.
1234 * @returns Physical TLB index.
1235 * @param GCPhys The guest physical address.
1236 */
1237#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1238
1239
1240/** @name Context neutrual page mapper TLB.
1241 *
1242 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1243 * code is writting in a kind of context neutrual way. Time will show whether
1244 * this actually makes sense or not...
1245 *
1246 * @{ */
1247/** @typedef PPGMPAGEMAPTLB
1248 * The page mapper TLB pointer type for the current context. */
1249/** @typedef PPGMPAGEMAPTLB
1250 * The page mapper TLB entry pointer type for the current context. */
1251/** @typedef PPGMPAGEMAPTLB
1252 * The page mapper TLB entry pointer pointer type for the current context. */
1253/** @def PGM_PAGEMAPTLB_ENTRIES
1254 * The number of TLB entries in the page mapper TLB for the current context. */
1255/** @def PGM_PAGEMAPTLB_IDX
1256 * Calculate the TLB index for a guest physical address.
1257 * @returns The TLB index.
1258 * @param GCPhys The guest physical address. */
1259/** @typedef PPGMPAGEMAP
1260 * Pointer to a page mapper unit for current context. */
1261/** @typedef PPPGMPAGEMAP
1262 * Pointer to a page mapper unit pointer for current context. */
1263#ifdef IN_RC
1264// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1265// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1266// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1267# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1268# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1269 typedef void * PPGMPAGEMAP;
1270 typedef void ** PPPGMPAGEMAP;
1271//#elif IN_RING0
1272// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1273// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1274// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1275//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1276//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1277// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1278// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1279#else
1280 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1281 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1282 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1283# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1284# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1285 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1286 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1287#endif
1288/** @} */
1289
1290
1291/** @name PGM Pool Indexes.
1292 * Aka. the unique shadow page identifier.
1293 * @{ */
1294/** NIL page pool IDX. */
1295#define NIL_PGMPOOL_IDX 0
1296/** The first normal index. */
1297#define PGMPOOL_IDX_FIRST_SPECIAL 1
1298/** Page directory (32-bit root). */
1299#define PGMPOOL_IDX_PD 1
1300/** The extended PAE page directory (2048 entries, works as root currently). */
1301#define PGMPOOL_IDX_PAE_PD 2
1302/** PAE Page Directory Table 0. */
1303#define PGMPOOL_IDX_PAE_PD_0 3
1304/** PAE Page Directory Table 1. */
1305#define PGMPOOL_IDX_PAE_PD_1 4
1306/** PAE Page Directory Table 2. */
1307#define PGMPOOL_IDX_PAE_PD_2 5
1308/** PAE Page Directory Table 3. */
1309#define PGMPOOL_IDX_PAE_PD_3 6
1310/** Page Directory Pointer Table (PAE root, not currently used). */
1311#define PGMPOOL_IDX_PDPT 7
1312/** AMD64 CR3 level index.*/
1313#define PGMPOOL_IDX_AMD64_CR3 8
1314/** Nested paging root.*/
1315#define PGMPOOL_IDX_NESTED_ROOT 9
1316/** The first normal index. */
1317#define PGMPOOL_IDX_FIRST 10
1318/** The last valid index. (inclusive, 14 bits) */
1319#define PGMPOOL_IDX_LAST 0x3fff
1320/** @} */
1321
1322/** The NIL index for the parent chain. */
1323#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1324
1325/**
1326 * Node in the chain linking a shadowed page to it's parent (user).
1327 */
1328#pragma pack(1)
1329typedef struct PGMPOOLUSER
1330{
1331 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1332 uint16_t iNext;
1333 /** The user page index. */
1334 uint16_t iUser;
1335 /** Index into the user table. */
1336 uint32_t iUserTable;
1337} PGMPOOLUSER, *PPGMPOOLUSER;
1338typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1339#pragma pack()
1340
1341
1342/** The NIL index for the phys ext chain. */
1343#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1344
1345/**
1346 * Node in the chain of physical cross reference extents.
1347 */
1348#pragma pack(1)
1349typedef struct PGMPOOLPHYSEXT
1350{
1351 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1352 uint16_t iNext;
1353 /** The user page index. */
1354 uint16_t aidx[3];
1355} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1356typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1357#pragma pack()
1358
1359
1360/**
1361 * The kind of page that's being shadowed.
1362 */
1363typedef enum PGMPOOLKIND
1364{
1365 /** The virtual invalid 0 entry. */
1366 PGMPOOLKIND_INVALID = 0,
1367 /** The entry is free (=unused). */
1368 PGMPOOLKIND_FREE,
1369
1370 /** Shw: 32-bit page table; Gst: no paging */
1371 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1372 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1373 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1374 /** Shw: 32-bit page table; Gst: 4MB page. */
1375 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1376 /** Shw: PAE page table; Gst: no paging */
1377 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1378 /** Shw: PAE page table; Gst: 32-bit page table. */
1379 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1380 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1381 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1382 /** Shw: PAE page table; Gst: PAE page table. */
1383 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1384 /** Shw: PAE page table; Gst: 2MB page. */
1385 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1386
1387 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1388 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1389 /** Shw: PAE page directory; Gst: PAE page directory. */
1390 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1391
1392 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1393 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1394 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1395 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1396 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1397 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1398 /** Shw: 64-bit page directory table; Gst: no paging */
1399 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1400
1401 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1402 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1403
1404 /** Shw: EPT page directory pointer table; Gst: no paging */
1405 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1406 /** Shw: EPT page directory table; Gst: no paging */
1407 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1408 /** Shw: EPT page table; Gst: no paging */
1409 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1410
1411 /** Shw: Root 32-bit page directory. */
1412 PGMPOOLKIND_ROOT_32BIT_PD,
1413 /** Shw: Root PAE page directory */
1414 PGMPOOLKIND_ROOT_PAE_PD,
1415 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1416 PGMPOOLKIND_ROOT_PDPT,
1417 /** Shw: Root Nested paging table. */
1418 PGMPOOLKIND_ROOT_NESTED,
1419
1420 /** The last valid entry. */
1421 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1422} PGMPOOLKIND;
1423
1424
1425/**
1426 * The tracking data for a page in the pool.
1427 */
1428typedef struct PGMPOOLPAGE
1429{
1430 /** AVL node code with the (R3) physical address of this page. */
1431 AVLOHCPHYSNODECORE Core;
1432 /** Pointer to the R3 mapping of the page. */
1433#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1434 R3PTRTYPE(void *) pvPageR3;
1435#else
1436 R3R0PTRTYPE(void *) pvPageR3;
1437#endif
1438 /** The guest physical address. */
1439#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1440 uint32_t Alignment0;
1441#endif
1442 RTGCPHYS GCPhys;
1443 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1444 uint8_t enmKind;
1445 uint8_t bPadding;
1446 /** The index of this page. */
1447 uint16_t idx;
1448 /** The next entry in the list this page currently resides in.
1449 * It's either in the free list or in the GCPhys hash. */
1450 uint16_t iNext;
1451#ifdef PGMPOOL_WITH_USER_TRACKING
1452 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1453 uint16_t iUserHead;
1454 /** The number of present entries. */
1455 uint16_t cPresent;
1456 /** The first entry in the table which is present. */
1457 uint16_t iFirstPresent;
1458#endif
1459#ifdef PGMPOOL_WITH_MONITORING
1460 /** The number of modifications to the monitored page. */
1461 uint16_t cModifications;
1462 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1463 uint16_t iModifiedNext;
1464 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1465 uint16_t iModifiedPrev;
1466 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1467 uint16_t iMonitoredNext;
1468 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1469 uint16_t iMonitoredPrev;
1470#endif
1471#ifdef PGMPOOL_WITH_CACHE
1472 /** The next page in the age list. */
1473 uint16_t iAgeNext;
1474 /** The previous page in the age list. */
1475 uint16_t iAgePrev;
1476#endif /* PGMPOOL_WITH_CACHE */
1477 /** Used to indicate that the page is zeroed. */
1478 bool fZeroed;
1479 /** Used to indicate that a PT has non-global entries. */
1480 bool fSeenNonGlobal;
1481 /** Used to indicate that we're monitoring writes to the guest page. */
1482 bool fMonitored;
1483 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1484 * (All pages are in the age list.) */
1485 bool fCached;
1486 /** This is used by the R3 access handlers when invoked by an async thread.
1487 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1488 bool volatile fReusedFlushPending;
1489 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1490 * In these cases the access handler acts differently and will check
1491 * for mapping conflicts like the normal CR3 handler.
1492 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1493 * replaced by a list of pages which share access handler.
1494 */
1495 bool fCR3Mix;
1496} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1497
1498
1499#ifdef PGMPOOL_WITH_CACHE
1500/** The hash table size. */
1501# define PGMPOOL_HASH_SIZE 0x40
1502/** The hash function. */
1503# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1504#endif
1505
1506
1507/**
1508 * The shadow page pool instance data.
1509 *
1510 * It's all one big allocation made at init time, except for the
1511 * pages that is. The user nodes follows immediatly after the
1512 * page structures.
1513 */
1514typedef struct PGMPOOL
1515{
1516 /** The VM handle - R3 Ptr. */
1517 PVMR3 pVMR3;
1518 /** The VM handle - R0 Ptr. */
1519 PVMR0 pVMR0;
1520 /** The VM handle - RC Ptr. */
1521 PVMRC pVMRC;
1522 /** The max pool size. This includes the special IDs. */
1523 uint16_t cMaxPages;
1524 /** The current pool size. */
1525 uint16_t cCurPages;
1526 /** The head of the free page list. */
1527 uint16_t iFreeHead;
1528 /* Padding. */
1529 uint16_t u16Padding;
1530#ifdef PGMPOOL_WITH_USER_TRACKING
1531 /** Head of the chain of free user nodes. */
1532 uint16_t iUserFreeHead;
1533 /** The number of user nodes we've allocated. */
1534 uint16_t cMaxUsers;
1535 /** The number of present page table entries in the entire pool. */
1536 uint32_t cPresent;
1537 /** Pointer to the array of user nodes - RC pointer. */
1538 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1539 /** Pointer to the array of user nodes - R3 pointer. */
1540 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1541 /** Pointer to the array of user nodes - R0 pointer. */
1542 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1543#endif /* PGMPOOL_WITH_USER_TRACKING */
1544#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1545 /** Head of the chain of free phys ext nodes. */
1546 uint16_t iPhysExtFreeHead;
1547 /** The number of user nodes we've allocated. */
1548 uint16_t cMaxPhysExts;
1549 /** Pointer to the array of physical xref extent - RC pointer. */
1550 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1551 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1552 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1553 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1554 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1555#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1556#ifdef PGMPOOL_WITH_CACHE
1557 /** Hash table for GCPhys addresses. */
1558 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1559 /** The head of the age list. */
1560 uint16_t iAgeHead;
1561 /** The tail of the age list. */
1562 uint16_t iAgeTail;
1563 /** Set if the cache is enabled. */
1564 bool fCacheEnabled;
1565#endif /* PGMPOOL_WITH_CACHE */
1566#ifdef PGMPOOL_WITH_MONITORING
1567 /** Head of the list of modified pages. */
1568 uint16_t iModifiedHead;
1569 /** The current number of modified pages. */
1570 uint16_t cModifiedPages;
1571 /** Access handler, RC. */
1572 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1573 /** Access handler, R0. */
1574 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1575 /** Access handler, R3. */
1576 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1577 /** The access handler description (HC ptr). */
1578 R3PTRTYPE(const char *) pszAccessHandler;
1579#endif /* PGMPOOL_WITH_MONITORING */
1580 /** The number of pages currently in use. */
1581 uint16_t cUsedPages;
1582#ifdef VBOX_WITH_STATISTICS
1583 /** The high wather mark for cUsedPages. */
1584 uint16_t cUsedPagesHigh;
1585 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1586 /** Profiling pgmPoolAlloc(). */
1587 STAMPROFILEADV StatAlloc;
1588 /** Profiling pgmPoolClearAll(). */
1589 STAMPROFILE StatClearAll;
1590 /** Profiling pgmPoolFlushAllInt(). */
1591 STAMPROFILE StatFlushAllInt;
1592 /** Profiling pgmPoolFlushPage(). */
1593 STAMPROFILE StatFlushPage;
1594 /** Profiling pgmPoolFree(). */
1595 STAMPROFILE StatFree;
1596 /** Profiling time spent zeroing pages. */
1597 STAMPROFILE StatZeroPage;
1598# ifdef PGMPOOL_WITH_USER_TRACKING
1599 /** Profiling of pgmPoolTrackDeref. */
1600 STAMPROFILE StatTrackDeref;
1601 /** Profiling pgmTrackFlushGCPhysPT. */
1602 STAMPROFILE StatTrackFlushGCPhysPT;
1603 /** Profiling pgmTrackFlushGCPhysPTs. */
1604 STAMPROFILE StatTrackFlushGCPhysPTs;
1605 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1606 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1607 /** Number of times we've been out of user records. */
1608 STAMCOUNTER StatTrackFreeUpOneUser;
1609# endif
1610# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1611 /** Profiling deref activity related tracking GC physical pages. */
1612 STAMPROFILE StatTrackDerefGCPhys;
1613 /** Number of linear searches for a HCPhys in the ram ranges. */
1614 STAMCOUNTER StatTrackLinearRamSearches;
1615 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1616 STAMCOUNTER StamTrackPhysExtAllocFailures;
1617# endif
1618# ifdef PGMPOOL_WITH_MONITORING
1619 /** Profiling the RC/R0 access handler. */
1620 STAMPROFILE StatMonitorRZ;
1621 /** Times we've failed interpreting the instruction. */
1622 STAMCOUNTER StatMonitorRZEmulateInstr;
1623 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1624 STAMPROFILE StatMonitorRZFlushPage;
1625 /** Times we've detected fork(). */
1626 STAMCOUNTER StatMonitorRZFork;
1627 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1628 STAMPROFILE StatMonitorRZHandled;
1629 /** Times we've failed interpreting a patch code instruction. */
1630 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1631 /** Times we've failed interpreting a patch code instruction during flushing. */
1632 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1633 /** The number of times we've seen rep prefixes we can't handle. */
1634 STAMCOUNTER StatMonitorRZRepPrefix;
1635 /** Profiling the REP STOSD cases we've handled. */
1636 STAMPROFILE StatMonitorRZRepStosd;
1637
1638 /** Profiling the R3 access handler. */
1639 STAMPROFILE StatMonitorR3;
1640 /** Times we've failed interpreting the instruction. */
1641 STAMCOUNTER StatMonitorR3EmulateInstr;
1642 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1643 STAMPROFILE StatMonitorR3FlushPage;
1644 /** Times we've detected fork(). */
1645 STAMCOUNTER StatMonitorR3Fork;
1646 /** Profiling the R3 access we've handled (except REP STOSD). */
1647 STAMPROFILE StatMonitorR3Handled;
1648 /** The number of times we've seen rep prefixes we can't handle. */
1649 STAMCOUNTER StatMonitorR3RepPrefix;
1650 /** Profiling the REP STOSD cases we've handled. */
1651 STAMPROFILE StatMonitorR3RepStosd;
1652 /** The number of times we're called in an async thread an need to flush. */
1653 STAMCOUNTER StatMonitorR3Async;
1654 /** The high wather mark for cModifiedPages. */
1655 uint16_t cModifiedPagesHigh;
1656 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1657# endif
1658# ifdef PGMPOOL_WITH_CACHE
1659 /** The number of cache hits. */
1660 STAMCOUNTER StatCacheHits;
1661 /** The number of cache misses. */
1662 STAMCOUNTER StatCacheMisses;
1663 /** The number of times we've got a conflict of 'kind' in the cache. */
1664 STAMCOUNTER StatCacheKindMismatches;
1665 /** Number of times we've been out of pages. */
1666 STAMCOUNTER StatCacheFreeUpOne;
1667 /** The number of cacheable allocations. */
1668 STAMCOUNTER StatCacheCacheable;
1669 /** The number of uncacheable allocations. */
1670 STAMCOUNTER StatCacheUncacheable;
1671# endif
1672#elif HC_ARCH_BITS == 64
1673 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1674#endif
1675 /** The AVL tree for looking up a page by its HC physical address. */
1676 AVLOHCPHYSTREE HCPhysTree;
1677 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1678 /** Array of pages. (cMaxPages in length)
1679 * The Id is the index into thist array.
1680 */
1681 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1682} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1683
1684
1685/** @def PGMPOOL_PAGE_2_PTR
1686 * Maps a pool page pool into the current context.
1687 *
1688 * @returns VBox status code.
1689 * @param pVM The VM handle.
1690 * @param pPage The pool page.
1691 *
1692 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1693 * small page window employeed by that function. Be careful.
1694 * @remark There is no need to assert on the result.
1695 */
1696#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1697# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1698#else
1699# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1700#endif
1701
1702
1703/**
1704 * Trees are using self relative offsets as pointers.
1705 * So, all its data, including the root pointer, must be in the heap for HC and GC
1706 * to have the same layout.
1707 */
1708typedef struct PGMTREES
1709{
1710 /** Physical access handlers (AVL range+offsetptr tree). */
1711 AVLROGCPHYSTREE PhysHandlers;
1712 /** Virtual access handlers (AVL range + GC ptr tree). */
1713 AVLROGCPTRTREE VirtHandlers;
1714 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1715 AVLROGCPHYSTREE PhysToVirtHandlers;
1716 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1717 AVLROGCPTRTREE HyperVirtHandlers;
1718} PGMTREES;
1719/** Pointer to PGM trees. */
1720typedef PGMTREES *PPGMTREES;
1721
1722
1723/** @name Paging mode macros
1724 * @{ */
1725#ifdef IN_RC
1726# define PGM_CTX(a,b) a##RC##b
1727# define PGM_CTX_STR(a,b) a "GC" b
1728# define PGM_CTX_DECL(type) VMMRCDECL(type)
1729#else
1730# ifdef IN_RING3
1731# define PGM_CTX(a,b) a##R3##b
1732# define PGM_CTX_STR(a,b) a "R3" b
1733# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1734# else
1735# define PGM_CTX(a,b) a##R0##b
1736# define PGM_CTX_STR(a,b) a "R0" b
1737# define PGM_CTX_DECL(type) VMMDECL(type)
1738# endif
1739#endif
1740
1741#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1742#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1743#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1744#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1745#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1746#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1747#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1748#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1749#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1750#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1751#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1752#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1753#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1754#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1755#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1756#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1757#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1758
1759#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1760#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1761#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1762#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1763#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1764#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1765#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1766#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1767#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1768#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1769#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1770#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1771#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1772#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1773#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1774#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1775#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1776
1777/* Shw_Gst */
1778#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1779#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1780#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1781#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1782#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1783#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1784#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1785#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1786#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1787#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1788#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1789#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1790#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1791#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1792#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1793#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1794#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1795#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1796#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1797
1798#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1799#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1800#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1801#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1802#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1803#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1804#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1805#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1806#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1807#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1808#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1809#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1810#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1811#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1812#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1813#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1814#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1815#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1816#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1817#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1818#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1819#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1820#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1821#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1822#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1823#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1824#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1825#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1826#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1827#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1828#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1829#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1830#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1831#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1832#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1833#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1834#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1835
1836#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1837#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1838/** @} */
1839
1840/**
1841 * Data for each paging mode.
1842 */
1843typedef struct PGMMODEDATA
1844{
1845 /** The guest mode type. */
1846 uint32_t uGstType;
1847 /** The shadow mode type. */
1848 uint32_t uShwType;
1849
1850 /** @name Function pointers for Shadow paging.
1851 * @{
1852 */
1853 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
1854 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1855 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1856 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1857
1858 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1859 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1860
1861 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1862 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1863 /** @} */
1864
1865 /** @name Function pointers for Guest paging.
1866 * @{
1867 */
1868 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
1869 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1870 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1871 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1872 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1873 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1874 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1875 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1876 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1877 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1878 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1879 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1880 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1881
1882 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1883 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1884 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1885 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1886 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
1887 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1888 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
1889 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
1890 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
1891
1892 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1893 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1894 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
1895 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1896 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1897 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1898 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1899 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1900 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1901 /** @} */
1902
1903 /** @name Function pointers for Both Shadow and Guest paging.
1904 * @{
1905 */
1906 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
1907 /* no pfnR3BthTrap0eHandler */
1908 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1909 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1910 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
1911 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
1912 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
1913#ifdef VBOX_STRICT
1914 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
1915#endif
1916
1917 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1918 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1919 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1920 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
1921 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
1922 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
1923#ifdef VBOX_STRICT
1924 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
1925#endif
1926
1927 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1928 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1929 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1930 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
1931 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
1932 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
1933#ifdef VBOX_STRICT
1934 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
1935#endif
1936 /** @} */
1937} PGMMODEDATA, *PPGMMODEDATA;
1938
1939
1940
1941/**
1942 * Converts a PGM pointer into a VM pointer.
1943 * @returns Pointer to the VM structure the PGM is part of.
1944 * @param pPGM Pointer to PGM instance data.
1945 */
1946#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1947
1948/**
1949 * PGM Data (part of VM)
1950 */
1951typedef struct PGM
1952{
1953 /** Offset to the VM structure. */
1954 RTINT offVM;
1955
1956 /*
1957 * This will be redefined at least two more times before we're done, I'm sure.
1958 * The current code is only to get on with the coding.
1959 * - 2004-06-10: initial version, bird.
1960 * - 2004-07-02: 1st time, bird.
1961 * - 2004-10-18: 2nd time, bird.
1962 * - 2005-07-xx: 3rd time, bird.
1963 */
1964
1965 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1966 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1967 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1968 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1969
1970 /** The host paging mode. (This is what SUPLib reports.) */
1971 SUPPAGINGMODE enmHostMode;
1972 /** The shadow paging mode. */
1973 PGMMODE enmShadowMode;
1974 /** The guest paging mode. */
1975 PGMMODE enmGuestMode;
1976
1977 /** The current physical address representing in the guest CR3 register. */
1978 RTGCPHYS GCPhysCR3;
1979 /** Pointer to the 5 page CR3 content mapping.
1980 * The first page is always the CR3 (in some form) while the 4 other pages
1981 * are used of the PDs in PAE mode. */
1982 RTGCPTR GCPtrCR3Mapping;
1983#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1984 uint32_t u32Alignment;
1985#endif
1986 /** The physical address of the currently monitored guest CR3 page.
1987 * When this value is NIL_RTGCPHYS no page is being monitored. */
1988 RTGCPHYS GCPhysGstCR3Monitored;
1989
1990 /** @name 32-bit Guest Paging.
1991 * @{ */
1992 /** The guest's page directory, R3 pointer. */
1993 R3PTRTYPE(PX86PD) pGuestPDR3;
1994#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1995 /** The guest's page directory, R0 pointer. */
1996 R0PTRTYPE(PX86PD) pGuestPDR0;
1997#endif
1998 /** The guest's page directory, static RC mapping. */
1999 RCPTRTYPE(PX86PD) pGuestPDRC;
2000 /** @} */
2001
2002 /** @name PAE Guest Paging.
2003 * @{ */
2004 /** The guest's page directory pointer table, static GC mapping. */
2005 RCPTRTYPE(PX86PDPT) pGstPaePDPTRC;
2006 /** The guest's page directory pointer table, R3 pointer. */
2007 R3PTRTYPE(PX86PDPT) pGstPaePDPTR3;
2008#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2009 /** The guest's page directory pointer table, R0 pointer. */
2010 R0PTRTYPE(PX86PDPT) pGstPaePDPTR0;
2011#endif
2012
2013 /** The guest's page directories, R3 pointers.
2014 * These are individual pointers and don't have to be adjecent.
2015 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2016 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2017 /** The guest's page directories, R0 pointers.
2018 * Same restrictions as apGstPaePDsR3. */
2019#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2020 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2021#endif
2022 /** The guest's page directories, static GC mapping.
2023 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2024 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2025 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2026 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2027 RTGCPHYS aGCPhysGstPaePDs[4];
2028 /** The physical addresses of the monitored guest page directories (PAE). */
2029 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2030 /** @} */
2031
2032 /** @name AMD64 Guest Paging.
2033 * @{ */
2034 /** The guest's page directory pointer table, R3 pointer. */
2035 R3PTRTYPE(PX86PML4) pGstAmd64PML4R3;
2036#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2037 /** The guest's page directory pointer table, R0 pointer. */
2038 R0PTRTYPE(PX86PML4) pGstAmd64PML4R0;
2039#endif
2040 /** @} */
2041
2042 /** @name 32-bit Shadow Paging
2043 * @{ */
2044 /** The 32-Bit PD - HC Ptr. */
2045#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2046 R3PTRTYPE(PX86PD) pHC32BitPD;
2047#else
2048 R3R0PTRTYPE(PX86PD) pHC32BitPD;
2049#endif
2050 /** The 32-Bit PD - GC Ptr. */
2051 RCPTRTYPE(PX86PD) pGC32BitPD;
2052#if HC_ARCH_BITS == 64
2053 uint32_t u32Padding1; /**< alignment padding. */
2054#endif
2055 /** The Physical Address (HC) of the 32-Bit PD. */
2056 RTHCPHYS HCPhys32BitPD;
2057 /** @} */
2058
2059 /** @name PAE Shadow Paging
2060 * @{ */
2061 /** The four PDs for the low 4GB - R3 Ptr.
2062 * Even though these are 4 pointers, what they point at is a single table.
2063 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2064 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2065#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2066 /** The four PDs for the low 4GB - R0 Ptr.
2067 * Same kind of mapping as apHCPaePDs. */
2068 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2069#endif
2070 /** The four PDs for the low 4GB - RC Ptr.
2071 * Same kind of mapping as apHCPaePDs. */
2072 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2073 /** The Physical Address (HC) of the four PDs for the low 4GB.
2074 * These are *NOT* 4 contiguous pages. */
2075 RTHCPHYS aHCPhysPaePDs[4];
2076 /** The Physical Address (HC) of the PAE PDPT. */
2077 RTHCPHYS HCPhysPaePDPT;
2078 /** The PAE PDPT - R3 Ptr. */
2079 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2080 /** The PAE PDPT - R0 Ptr. */
2081 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2082 /** The PAE PDPT - RC Ptr. */
2083 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2084 /** @} */
2085#if HC_ARCH_BITS == 64
2086 RTRCPTR alignment5; /**< structure size alignment. */
2087#endif
2088
2089 /** @name AMD64 Shadow Paging
2090 * Extends PAE Paging.
2091 * @{ */
2092 /** The Page Map Level 4 table - R3 Ptr. */
2093 R3PTRTYPE(PX86PML4) pShwPaePml4R3;
2094#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2095 /** The Page Map Level 4 table - R0 Ptr. */
2096 R0PTRTYPE(PX86PML4) pShwPaePml4R0;
2097#endif
2098 /** The Physical Address (HC) of the Page Map Level 4 table. */
2099 RTHCPHYS HCPhysPaePML4;
2100 /** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
2101 R3PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R3;
2102 /** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
2103 R0PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R0;
2104 /** @}*/
2105
2106 /** @name Nested Shadow Paging
2107 * @{ */
2108 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2109 RTR3PTR pShwNestedRootR3;
2110#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2111 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2112 RTR0PTR pShwNestedRootR0;
2113#endif
2114 /** The Physical Address (HC) of the nested paging root. */
2115 RTHCPHYS HCPhysNestedRoot;
2116 /** @} */
2117
2118 /** @name Function pointers for Shadow paging.
2119 * @{
2120 */
2121 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2122 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2123 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2124 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2125
2126 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2127 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2128
2129 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2130 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2131
2132 /** @} */
2133
2134 /** @name Function pointers for Guest paging.
2135 * @{
2136 */
2137 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2138 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2139 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2140 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2141 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2142 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2143 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2144 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2145 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2146 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2147 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2148 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2149 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2150
2151 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2152 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2153 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2154 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2155 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2156 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2157 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2158 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2159 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2160#if HC_ARCH_BITS == 64
2161 RTRCPTR alignment3; /**< structure size alignment. */
2162#endif
2163
2164 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2165 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2166 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2167 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2168 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2169 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2170 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2171 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2172 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2173 /** @} */
2174
2175 /** @name Function pointers for Both Shadow and Guest paging.
2176 * @{
2177 */
2178 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2179 /* no pfnR3BthTrap0eHandler */
2180 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2181 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2182 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2183 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2184 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2185 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2186
2187 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2188 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2189 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2190 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2191 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2192 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2193 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2194
2195 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2196 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2197 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2198 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2199 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2200 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2201 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2202#if HC_ARCH_BITS == 64
2203 RTRCPTR alignment2; /**< structure size alignment. */
2204#endif
2205 /** @} */
2206
2207 /** Pointer to SHW+GST mode data (function pointers).
2208 * The index into this table is made up from */
2209 R3PTRTYPE(PPGMMODEDATA) paModeData;
2210
2211 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2212 * This is sorted by physical address and contains no overlapping ranges. */
2213 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2214 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2215 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2216 /** RC pointer corresponding to PGM::pRamRangesR3. */
2217 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2218 /** The configured RAM size. */
2219 RTUINT cbRamSize;
2220
2221 /** Pointer to the list of ROM ranges - for R3.
2222 * This is sorted by physical address and contains no overlapping ranges. */
2223 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2224 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2225 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2226 /** RC pointer corresponding to PGM::pRomRangesR3. */
2227 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2228 /** Alignment padding. */
2229 RTRCPTR GCPtrPadding2;
2230
2231 /** Pointer to the list of MMIO2 ranges - for R3.
2232 * Registration order. */
2233 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2234
2235 /** PGM offset based trees - R3 Ptr. */
2236 R3PTRTYPE(PPGMTREES) pTreesR3;
2237 /** PGM offset based trees - R0 Ptr. */
2238 R0PTRTYPE(PPGMTREES) pTreesR0;
2239 /** PGM offset based trees - RC Ptr. */
2240 RCPTRTYPE(PPGMTREES) pTreesRC;
2241
2242 /** Linked list of GC mappings - for RC.
2243 * The list is sorted ascending on address.
2244 */
2245 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2246 /** Linked list of GC mappings - for HC.
2247 * The list is sorted ascending on address.
2248 */
2249 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2250 /** Linked list of GC mappings - for R0.
2251 * The list is sorted ascending on address.
2252 */
2253 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2254
2255 /** If set no conflict checks are required. (boolean) */
2256 bool fMappingsFixed;
2257 /** If set, then no mappings are put into the shadow page table. (boolean) */
2258 bool fDisableMappings;
2259 /** Size of fixed mapping */
2260 uint32_t cbMappingFixed;
2261 /** Base address (GC) of fixed mapping */
2262 RTGCPTR GCPtrMappingFixed;
2263#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2264 uint32_t u32Padding0; /**< alignment padding. */
2265#endif
2266
2267
2268 /** @name Intermediate Context
2269 * @{ */
2270 /** Pointer to the intermediate page directory - Normal. */
2271 R3PTRTYPE(PX86PD) pInterPD;
2272 /** Pointer to the intermedate page tables - Normal.
2273 * There are two page tables, one for the identity mapping and one for
2274 * the host context mapping (of the core code). */
2275 R3PTRTYPE(PX86PT) apInterPTs[2];
2276 /** Pointer to the intermedate page tables - PAE. */
2277 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2278 /** Pointer to the intermedate page directory - PAE. */
2279 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2280 /** Pointer to the intermedate page directory - PAE. */
2281 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2282 /** Pointer to the intermedate page-map level 4 - AMD64. */
2283 R3PTRTYPE(PX86PML4) pInterPaePML4;
2284 /** Pointer to the intermedate page directory - AMD64. */
2285 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2286 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2287 RTHCPHYS HCPhysInterPD;
2288 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2289 RTHCPHYS HCPhysInterPaePDPT;
2290 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2291 RTHCPHYS HCPhysInterPaePML4;
2292 /** @} */
2293
2294 /** Base address of the dynamic page mapping area.
2295 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2296 */
2297 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2298 /** The index of the last entry used in the dynamic page mapping area. */
2299 RTUINT iDynPageMapLast;
2300 /** Cache containing the last entries in the dynamic page mapping area.
2301 * The cache size is covering half of the mapping area. */
2302 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2303
2304 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2305 RTGCPHYS GCPhys4MBPSEMask;
2306
2307 /** A20 gate mask.
2308 * Our current approach to A20 emulation is to let REM do it and don't bother
2309 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2310 * But whould need arrise, we'll subject physical addresses to this mask. */
2311 RTGCPHYS GCPhysA20Mask;
2312 /** A20 gate state - boolean! */
2313 RTUINT fA20Enabled;
2314
2315 /** What needs syncing (PGM_SYNC_*).
2316 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2317 * PGMFlushTLB, and PGMR3Load. */
2318 RTUINT fSyncFlags;
2319
2320 /** PGM critical section.
2321 * This protects the physical & virtual access handlers, ram ranges,
2322 * and the page flag updating (some of it anyway).
2323 */
2324 PDMCRITSECT CritSect;
2325
2326 /** Shadow Page Pool - R3 Ptr. */
2327 R3PTRTYPE(PPGMPOOL) pPoolR3;
2328 /** Shadow Page Pool - R0 Ptr. */
2329 R0PTRTYPE(PPGMPOOL) pPoolR0;
2330 /** Shadow Page Pool - RC Ptr. */
2331 RCPTRTYPE(PPGMPOOL) pPoolRC;
2332
2333 /** We're not in a state which permits writes to guest memory.
2334 * (Only used in strict builds.) */
2335 bool fNoMorePhysWrites;
2336
2337 /** Flush the cache on the next access. */
2338 bool fPhysCacheFlushPending;
2339/** @todo r=bird: Fix member names!*/
2340 /** PGMPhysRead cache */
2341 PGMPHYSCACHE pgmphysreadcache;
2342 /** PGMPhysWrite cache */
2343 PGMPHYSCACHE pgmphyswritecache;
2344
2345 /**
2346 * Data associated with managing the ring-3 mappings of the allocation chunks.
2347 */
2348 struct
2349 {
2350 /** The chunk tree, ordered by chunk id. */
2351#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2352 R3PTRTYPE(PAVLU32NODECORE) pTree;
2353#else
2354 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2355#endif
2356 /** The chunk mapping TLB. */
2357 PGMCHUNKR3MAPTLB Tlb;
2358 /** The number of mapped chunks. */
2359 uint32_t c;
2360 /** The maximum number of mapped chunks.
2361 * @cfgm PGM/MaxRing3Chunks */
2362 uint32_t cMax;
2363 /** The chunk age tree, ordered by ageing sequence number. */
2364 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2365 /** The current time. */
2366 uint32_t iNow;
2367 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2368 uint32_t AgeingCountdown;
2369 } ChunkR3Map;
2370
2371 /**
2372 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2373 */
2374 PGMPAGER3MAPTLB PhysTlbHC;
2375
2376 /** @name The zero page.
2377 * @{ */
2378 /** The host physical address of the zero page. */
2379 RTHCPHYS HCPhysZeroPg;
2380 /** The ring-3 mapping of the zero page. */
2381 RTR3PTR pvZeroPgR3;
2382 /** The ring-0 mapping of the zero page. */
2383 RTR0PTR pvZeroPgR0;
2384 /** The GC mapping of the zero page. */
2385 RTGCPTR pvZeroPgGC;
2386#if GC_ARCH_BITS != 32
2387 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2388#endif
2389 /** @}*/
2390
2391 /** The number of handy pages. */
2392 uint32_t cHandyPages;
2393 /**
2394 * Array of handy pages.
2395 *
2396 * This array is used in a two way communication between pgmPhysAllocPage
2397 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2398 * an intermediary.
2399 *
2400 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2401 * (The current size of 32 pages, means 128 KB of handy memory.)
2402 */
2403 GMMPAGEDESC aHandyPages[32];
2404
2405 /** @name Release Statistics
2406 * @{ */
2407 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2408 uint32_t cPrivatePages; /**< The number of private pages. */
2409 uint32_t cSharedPages; /**< The number of shared pages. */
2410 uint32_t cZeroPages; /**< The number of zero backed pages. */
2411 /** The number of times the guest has switched mode since last reset or statistics reset. */
2412 STAMCOUNTER cGuestModeChanges;
2413 /** @} */
2414
2415#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2416 /** RC: Which statistic this \#PF should be attributed to. */
2417 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2418 RTRCPTR padding0;
2419 /** R0: Which statistic this \#PF should be attributed to. */
2420 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2421 RTR0PTR padding1;
2422
2423 /* Common */
2424# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2425 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2426 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2427 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2428 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2429 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2430 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2431# endif
2432 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2433 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2434
2435 /* R3 only: */
2436 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2437 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2438 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2439 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2440 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2441 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2442
2443 /* RC only: */
2444 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2445 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2446 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2447 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2448
2449 /* RZ only: */
2450 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2451 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2452 STAMPROFILE StatRZTrap0eTimeSyncPT;
2453 STAMPROFILE StatRZTrap0eTimeMapping;
2454 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2455 STAMPROFILE StatRZTrap0eTimeHandlers;
2456 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2457 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2458 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2459 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2460 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2461 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2462 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2463 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2464 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2465 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2466 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2467 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2468 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2469 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2470 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2471 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2472 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2473 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2474 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2475 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2476 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2477 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2478 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2479 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2480 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2481 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2482 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2483 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2484 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2485 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2486 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2487 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2488 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2489 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2490 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2491 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2492 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2493 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2494 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2495 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2496 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2497 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2498 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2499
2500 /* HC - R3 and (maybe) R0: */
2501
2502 /* RZ & R3: */
2503 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2504 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2505 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2506 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2507 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2508 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2509 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2510 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2511 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2512 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2513 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2514 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2515 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2516 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2517 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2518 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2519 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2520 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2521 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2522 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2523 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2524 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2525 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2526 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2527 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2528 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2529 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2530 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2531 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2532 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2533 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2534 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2535 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2536 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2537 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2538 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2539 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2540 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2541 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2542 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2543 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2544 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2545 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2546 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2547 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2548 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2549 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2550/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2551 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2552 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2553 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2554 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2555 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2556 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2557
2558 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2559 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2560 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2561 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2562 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2563 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2564 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2565 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2566 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2567 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2568 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2569 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2570 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2571 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2572 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2573 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2574 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2575 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2576 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2577 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2578 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2579 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2580 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2581 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2582 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2583 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2584 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2585 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2586 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2587 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2588 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2589 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2590 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2591 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2592 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2593 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2594 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2595 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2596 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2597 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2598 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2599 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2600 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2601 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2602 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2603 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2604 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2605/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2606 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2607 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2608 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2609 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2610 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2611 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2612#endif /* VBOX_WITH_STATISTICS */
2613} PGM;
2614/** Pointer to the PGM instance data. */
2615typedef PGM *PPGM;
2616
2617
2618/**
2619 * PGMCPU Data (part of VMCPU).
2620 */
2621typedef struct PGMCPU
2622{
2623 /** Offset to the VMCPU structure. */
2624 RTINT offVMCPU;
2625} PGMCPU;
2626/** Pointer to the per-cpu PGM data. */
2627typedef PGMCPU *PPGMCPU;
2628
2629
2630/** @name PGM::fSyncFlags Flags
2631 * @{
2632 */
2633/** Updates the virtual access handler state bit in PGMPAGE. */
2634#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2635/** Always sync CR3. */
2636#define PGM_SYNC_ALWAYS RT_BIT(1)
2637/** Check monitoring on next CR3 (re)load and invalidate page. */
2638#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2639/** Clear the page pool (a light weight flush). */
2640#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2641/** @} */
2642
2643
2644__BEGIN_DECLS
2645
2646int pgmLock(PVM pVM);
2647void pgmUnlock(PVM pVM);
2648
2649VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2650VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2651
2652int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2653int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2654PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2655void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2656DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2657
2658void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2659int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2660DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2661#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2662void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2663#else
2664# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2665#endif
2666DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2667
2668
2669void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2670int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2671int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2672int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2673#ifdef IN_RING3
2674int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2675int pgmR3PhysRamReset(PVM pVM);
2676int pgmR3PhysRomReset(PVM pVM);
2677#ifndef VBOX_WITH_NEW_PHYS_CODE
2678int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2679#endif
2680
2681int pgmR3PoolInit(PVM pVM);
2682void pgmR3PoolRelocate(PVM pVM);
2683void pgmR3PoolReset(PVM pVM);
2684
2685#endif /* IN_RING3 */
2686#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2687void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2688#endif
2689int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2690PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2691void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2692void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2693int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2694void pgmPoolFlushAll(PVM pVM);
2695void pgmPoolClearAll(PVM pVM);
2696int pgmPoolSyncCR3(PVM pVM);
2697void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2698void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2699int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2700PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2701void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2702void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2703uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2704void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2705#ifdef PGMPOOL_WITH_MONITORING
2706# ifdef IN_RING3
2707void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2708# else
2709void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2710# endif
2711int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2712void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2713void pgmPoolMonitorModifiedClearAll(PVM pVM);
2714int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2715int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2716#endif
2717
2718__END_DECLS
2719
2720
2721/**
2722 * Gets the PGMRAMRANGE structure for a guest page.
2723 *
2724 * @returns Pointer to the RAM range on success.
2725 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2726 *
2727 * @param pPGM PGM handle.
2728 * @param GCPhys The GC physical address.
2729 */
2730DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2731{
2732 /*
2733 * Optimize for the first range.
2734 */
2735 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2736 RTGCPHYS off = GCPhys - pRam->GCPhys;
2737 if (RT_UNLIKELY(off >= pRam->cb))
2738 {
2739 do
2740 {
2741 pRam = pRam->CTX_SUFF(pNext);
2742 if (RT_UNLIKELY(!pRam))
2743 break;
2744 off = GCPhys - pRam->GCPhys;
2745 } while (off >= pRam->cb);
2746 }
2747 return pRam;
2748}
2749
2750
2751/**
2752 * Gets the PGMPAGE structure for a guest page.
2753 *
2754 * @returns Pointer to the page on success.
2755 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2756 *
2757 * @param pPGM PGM handle.
2758 * @param GCPhys The GC physical address.
2759 */
2760DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2761{
2762 /*
2763 * Optimize for the first range.
2764 */
2765 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2766 RTGCPHYS off = GCPhys - pRam->GCPhys;
2767 if (RT_UNLIKELY(off >= pRam->cb))
2768 {
2769 do
2770 {
2771 pRam = pRam->CTX_SUFF(pNext);
2772 if (RT_UNLIKELY(!pRam))
2773 return NULL;
2774 off = GCPhys - pRam->GCPhys;
2775 } while (off >= pRam->cb);
2776 }
2777 return &pRam->aPages[off >> PAGE_SHIFT];
2778}
2779
2780
2781/**
2782 * Gets the PGMPAGE structure for a guest page.
2783 *
2784 * Old Phys code: Will make sure the page is present.
2785 *
2786 * @returns VBox status code.
2787 * @retval VINF_SUCCESS and a valid *ppPage on success.
2788 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2789 *
2790 * @param pPGM PGM handle.
2791 * @param GCPhys The GC physical address.
2792 * @param ppPage Where to store the page poitner on success.
2793 */
2794DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2795{
2796 /*
2797 * Optimize for the first range.
2798 */
2799 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2800 RTGCPHYS off = GCPhys - pRam->GCPhys;
2801 if (RT_UNLIKELY(off >= pRam->cb))
2802 {
2803 do
2804 {
2805 pRam = pRam->CTX_SUFF(pNext);
2806 if (RT_UNLIKELY(!pRam))
2807 {
2808 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2809 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2810 }
2811 off = GCPhys - pRam->GCPhys;
2812 } while (off >= pRam->cb);
2813 }
2814 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2815#ifndef VBOX_WITH_NEW_PHYS_CODE
2816
2817 /*
2818 * Make sure it's present.
2819 */
2820 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2821 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2822 {
2823#ifdef IN_RING3
2824 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2825#else
2826 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2827#endif
2828 if (RT_FAILURE(rc))
2829 {
2830 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2831 return rc;
2832 }
2833 Assert(rc == VINF_SUCCESS);
2834 }
2835#endif
2836 return VINF_SUCCESS;
2837}
2838
2839
2840
2841
2842/**
2843 * Gets the PGMPAGE structure for a guest page.
2844 *
2845 * Old Phys code: Will make sure the page is present.
2846 *
2847 * @returns VBox status code.
2848 * @retval VINF_SUCCESS and a valid *ppPage on success.
2849 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2850 *
2851 * @param pPGM PGM handle.
2852 * @param GCPhys The GC physical address.
2853 * @param ppPage Where to store the page poitner on success.
2854 * @param ppRamHint Where to read and store the ram list hint.
2855 * The caller initializes this to NULL before the call.
2856 */
2857DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2858{
2859 RTGCPHYS off;
2860 PPGMRAMRANGE pRam = *ppRamHint;
2861 if ( !pRam
2862 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2863 {
2864 pRam = pPGM->CTX_SUFF(pRamRanges);
2865 off = GCPhys - pRam->GCPhys;
2866 if (RT_UNLIKELY(off >= pRam->cb))
2867 {
2868 do
2869 {
2870 pRam = pRam->CTX_SUFF(pNext);
2871 if (RT_UNLIKELY(!pRam))
2872 {
2873 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2874 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2875 }
2876 off = GCPhys - pRam->GCPhys;
2877 } while (off >= pRam->cb);
2878 }
2879 *ppRamHint = pRam;
2880 }
2881 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2882#ifndef VBOX_WITH_NEW_PHYS_CODE
2883
2884 /*
2885 * Make sure it's present.
2886 */
2887 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2888 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2889 {
2890#ifdef IN_RING3
2891 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2892#else
2893 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2894#endif
2895 if (RT_FAILURE(rc))
2896 {
2897 *ppPage = NULL; /* Shut up annoying smart ass. */
2898 return rc;
2899 }
2900 Assert(rc == VINF_SUCCESS);
2901 }
2902#endif
2903 return VINF_SUCCESS;
2904}
2905
2906
2907/**
2908 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2909 *
2910 * @returns Pointer to the page on success.
2911 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2912 *
2913 * @param pPGM PGM handle.
2914 * @param GCPhys The GC physical address.
2915 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2916 */
2917DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2918{
2919 /*
2920 * Optimize for the first range.
2921 */
2922 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2923 RTGCPHYS off = GCPhys - pRam->GCPhys;
2924 if (RT_UNLIKELY(off >= pRam->cb))
2925 {
2926 do
2927 {
2928 pRam = pRam->CTX_SUFF(pNext);
2929 if (RT_UNLIKELY(!pRam))
2930 return NULL;
2931 off = GCPhys - pRam->GCPhys;
2932 } while (off >= pRam->cb);
2933 }
2934 *ppRam = pRam;
2935 return &pRam->aPages[off >> PAGE_SHIFT];
2936}
2937
2938
2939/**
2940 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2941 *
2942 * @returns Pointer to the page on success.
2943 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2944 *
2945 * @param pPGM PGM handle.
2946 * @param GCPhys The GC physical address.
2947 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2948 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2949 */
2950DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2951{
2952 /*
2953 * Optimize for the first range.
2954 */
2955 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2956 RTGCPHYS off = GCPhys - pRam->GCPhys;
2957 if (RT_UNLIKELY(off >= pRam->cb))
2958 {
2959 do
2960 {
2961 pRam = pRam->CTX_SUFF(pNext);
2962 if (RT_UNLIKELY(!pRam))
2963 {
2964 *ppRam = NULL; /* Shut up silly GCC warnings. */
2965 *ppPage = NULL; /* ditto */
2966 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2967 }
2968 off = GCPhys - pRam->GCPhys;
2969 } while (off >= pRam->cb);
2970 }
2971 *ppRam = pRam;
2972 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2973#ifndef VBOX_WITH_NEW_PHYS_CODE
2974
2975 /*
2976 * Make sure it's present.
2977 */
2978 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2979 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2980 {
2981#ifdef IN_RING3
2982 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2983#else
2984 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2985#endif
2986 if (RT_FAILURE(rc))
2987 {
2988 *ppPage = NULL; /* Shut up silly GCC warnings. */
2989 *ppPage = NULL; /* ditto */
2990 return rc;
2991 }
2992 Assert(rc == VINF_SUCCESS);
2993
2994 }
2995#endif
2996 return VINF_SUCCESS;
2997}
2998
2999
3000/**
3001 * Convert GC Phys to HC Phys.
3002 *
3003 * @returns VBox status.
3004 * @param pPGM PGM handle.
3005 * @param GCPhys The GC physical address.
3006 * @param pHCPhys Where to store the corresponding HC physical address.
3007 *
3008 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3009 * Avoid when writing new code!
3010 */
3011DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3012{
3013 PPGMPAGE pPage;
3014 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3015 if (RT_FAILURE(rc))
3016 return rc;
3017 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3018 return VINF_SUCCESS;
3019}
3020
3021
3022#ifndef IN_RC
3023/**
3024 * Queries the Physical TLB entry for a physical guest page,
3025 * attemting to load the TLB entry if necessary.
3026 *
3027 * @returns VBox status code.
3028 * @retval VINF_SUCCESS on success
3029 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3030 * @param pPGM The PGM instance handle.
3031 * @param GCPhys The address of the guest page.
3032 * @param ppTlbe Where to store the pointer to the TLB entry.
3033 */
3034
3035DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3036{
3037 int rc;
3038 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3039 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3040 {
3041 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3042 rc = VINF_SUCCESS;
3043 }
3044 else
3045 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3046 *ppTlbe = pTlbe;
3047 return rc;
3048}
3049#endif /* !IN_RC */
3050
3051#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3052
3053# ifndef VBOX_WITH_NEW_PHYS_CODE
3054/**
3055 * Convert GC Phys to HC Virt.
3056 *
3057 * @returns VBox status.
3058 * @param pPGM PGM handle.
3059 * @param GCPhys The GC physical address.
3060 * @param pHCPtr Where to store the corresponding HC virtual address.
3061 *
3062 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3063 */
3064DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3065{
3066 PPGMRAMRANGE pRam;
3067 PPGMPAGE pPage;
3068 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3069 if (RT_FAILURE(rc))
3070 {
3071 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3072 return rc;
3073 }
3074 RTGCPHYS off = GCPhys - pRam->GCPhys;
3075
3076 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3077 {
3078 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3079 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3080 return VINF_SUCCESS;
3081 }
3082 if (pRam->pvR3)
3083 {
3084 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3085 return VINF_SUCCESS;
3086 }
3087 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3088 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3089}
3090# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3091
3092
3093/**
3094 * Convert GC Phys to HC Virt.
3095 *
3096 * @returns VBox status.
3097 * @param PVM VM handle.
3098 * @param pRam Ram range
3099 * @param GCPhys The GC physical address.
3100 * @param pHCPtr Where to store the corresponding HC virtual address.
3101 *
3102 * @deprecated This will be eliminated. Don't use it.
3103 */
3104DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3105{
3106 RTGCPHYS off = GCPhys - pRam->GCPhys;
3107 Assert(off < pRam->cb);
3108
3109 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3110 {
3111 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3112 /* Physical chunk in dynamically allocated range not present? */
3113 if (RT_UNLIKELY(!pRam->paChunkR3Ptrs[idx]))
3114 {
3115#ifdef IN_RING3
3116 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3117#else
3118 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3119#endif
3120 if (rc != VINF_SUCCESS)
3121 {
3122 *pHCPtr = 0; /* GCC crap */
3123 return rc;
3124 }
3125 }
3126 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3127 return VINF_SUCCESS;
3128 }
3129 if (pRam->pvR3)
3130 {
3131 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3132 return VINF_SUCCESS;
3133 }
3134 *pHCPtr = 0; /* GCC crap */
3135 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3136}
3137
3138#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3139
3140/**
3141 * Convert GC Phys to HC Virt and HC Phys.
3142 *
3143 * @returns VBox status.
3144 * @param pPGM PGM handle.
3145 * @param GCPhys The GC physical address.
3146 * @param pHCPtr Where to store the corresponding HC virtual address.
3147 * @param pHCPhys Where to store the HC Physical address and its flags.
3148 *
3149 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3150 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3151 */
3152DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3153{
3154 PPGMRAMRANGE pRam;
3155 PPGMPAGE pPage;
3156 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3157 if (RT_FAILURE(rc))
3158 {
3159 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3160 *pHCPhys = 0; /* ditto */
3161 return rc;
3162 }
3163 RTGCPHYS off = GCPhys - pRam->GCPhys;
3164
3165 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3166 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3167 {
3168 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3169#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3170 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3171 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3172#else
3173 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3174#endif
3175 return VINF_SUCCESS;
3176 }
3177 if (pRam->pvR3)
3178 {
3179 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /** @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3180 return VINF_SUCCESS;
3181 }
3182 *pHCPtr = 0;
3183 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3184}
3185
3186
3187/**
3188 * Clears flags associated with a RAM address.
3189 *
3190 * @returns VBox status code.
3191 * @param pPGM PGM handle.
3192 * @param GCPhys Guest context physical address.
3193 * @param fFlags fFlags to clear. (Bits 0-11.)
3194 */
3195DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3196{
3197 PPGMPAGE pPage;
3198 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3199 if (RT_FAILURE(rc))
3200 return rc;
3201
3202 fFlags &= ~X86_PTE_PAE_PG_MASK;
3203 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3204 return VINF_SUCCESS;
3205}
3206
3207
3208/**
3209 * Clears flags associated with a RAM address.
3210 *
3211 * @returns VBox status code.
3212 * @param pPGM PGM handle.
3213 * @param GCPhys Guest context physical address.
3214 * @param fFlags fFlags to clear. (Bits 0-11.)
3215 * @param ppRamHint Where to read and store the ram list hint.
3216 * The caller initializes this to NULL before the call.
3217 */
3218DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3219{
3220 PPGMPAGE pPage;
3221 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3222 if (RT_FAILURE(rc))
3223 return rc;
3224
3225 fFlags &= ~X86_PTE_PAE_PG_MASK;
3226 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3227 return VINF_SUCCESS;
3228}
3229
3230
3231/**
3232 * Sets (bitwise OR) flags associated with a RAM address.
3233 *
3234 * @returns VBox status code.
3235 * @param pPGM PGM handle.
3236 * @param GCPhys Guest context physical address.
3237 * @param fFlags fFlags to set clear. (Bits 0-11.)
3238 */
3239DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3240{
3241 PPGMPAGE pPage;
3242 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3243 if (RT_FAILURE(rc))
3244 return rc;
3245
3246 fFlags &= ~X86_PTE_PAE_PG_MASK;
3247 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3248 return VINF_SUCCESS;
3249}
3250
3251
3252/**
3253 * Sets (bitwise OR) flags associated with a RAM address.
3254 *
3255 * @returns VBox status code.
3256 * @param pPGM PGM handle.
3257 * @param GCPhys Guest context physical address.
3258 * @param fFlags fFlags to set clear. (Bits 0-11.)
3259 * @param ppRamHint Where to read and store the ram list hint.
3260 * The caller initializes this to NULL before the call.
3261 */
3262DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3263{
3264 PPGMPAGE pPage;
3265 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3266 if (RT_FAILURE(rc))
3267 return rc;
3268
3269 fFlags &= ~X86_PTE_PAE_PG_MASK;
3270 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3271 return VINF_SUCCESS;
3272}
3273
3274
3275/**
3276 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3277 * Takes PSE-36 into account.
3278 *
3279 * @returns guest physical address
3280 * @param pPGM Pointer to the PGM instance data.
3281 * @param Pde Guest Pde
3282 */
3283DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3284{
3285 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3286 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3287
3288 return GCPhys & pPGM->GCPhys4MBPSEMask;
3289}
3290
3291
3292/**
3293 * Gets the page directory entry for the specified address (32-bit paging).
3294 *
3295 * @returns The page directory entry in question.
3296 * @param pPGM Pointer to the PGM instance data.
3297 * @param GCPtr The address.
3298 */
3299DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3300{
3301#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3302 PCX86PD pGuestPD = 0;
3303 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3304 if (RT_FAILURE(rc))
3305 {
3306 X86PDE ZeroPde = {0};
3307 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3308 }
3309 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3310#else
3311 return pPGM->CTX_SUFF(pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
3312#endif
3313}
3314
3315
3316/**
3317 * Gets the address of a specific page directory entry (32-bit paging).
3318 *
3319 * @returns Pointer the page directory entry in question.
3320 * @param pPGM Pointer to the PGM instance data.
3321 * @param GCPtr The address.
3322 */
3323DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3324{
3325#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3326 PX86PD pGuestPD = 0;
3327 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3328 AssertRCReturn(rc, 0);
3329 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3330#else
3331 return &pPGM->CTX_SUFF(pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
3332#endif
3333}
3334
3335
3336/**
3337 * Gets the address the guest page directory (32-bit paging).
3338 *
3339 * @returns Pointer the page directory entry in question.
3340 * @param pPGM Pointer to the PGM instance data.
3341 */
3342DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3343{
3344#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3345 PX86PD pGuestPD = 0;
3346 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPD);
3347 AssertRCReturn(rc, 0);
3348 return pGuestPD;
3349#else
3350 return pPGM->CTX_SUFF(pGuestPD);
3351#endif
3352}
3353
3354
3355/**
3356 * Gets the guest page directory pointer table.
3357 *
3358 * @returns Pointer to the page directory in question.
3359 * @returns NULL if the page directory is not present or on an invalid page.
3360 * @param pPGM Pointer to the PGM instance data.
3361 */
3362DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3363{
3364#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3365 PX86PDPT pGuestPDPT = 0;
3366 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPDPT);
3367 AssertRCReturn(rc, 0);
3368 return pGuestPDPT;
3369#else
3370 return pPGM->CTX_SUFF(pGstPaePDPT);
3371#endif
3372}
3373
3374
3375/**
3376 * Gets the guest page directory pointer table entry for the specified address.
3377 *
3378 * @returns Pointer to the page directory in question.
3379 * @returns NULL if the page directory is not present or on an invalid page.
3380 * @param pPGM Pointer to the PGM instance data.
3381 * @param GCPtr The address.
3382 */
3383DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3384{
3385 AssertGCPtr32(GCPtr);
3386
3387#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3388 PX86PDPT pGuestPDPT = 0;
3389 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPDPT);
3390 AssertRCReturn(rc, 0);
3391 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3392#else
3393 return &pPGM->CTX_SUFF(pGstPaePDPT)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3394#endif
3395}
3396
3397
3398/**
3399 * Gets the page directory for the specified address.
3400 *
3401 * @returns Pointer to the page directory in question.
3402 * @returns NULL if the page directory is not present or on an invalid page.
3403 * @param pPGM Pointer to the PGM instance data.
3404 * @param GCPtr The address.
3405 */
3406DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3407{
3408 AssertGCPtr32(GCPtr);
3409
3410#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3411 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3412 AssertReturn(pGuestPDPT, 0);
3413#else
3414 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePDPT);
3415#endif
3416 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3417 if (pGuestPDPT->a[iPdPt].n.u1Present)
3418 {
3419#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3420 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3421 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3422#endif
3423
3424 /* cache is out-of-sync. */
3425 PX86PDPAE pPD;
3426 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3427 if (RT_SUCCESS(rc))
3428 return pPD;
3429 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3430 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3431 }
3432 return NULL;
3433}
3434
3435
3436/**
3437 * Gets the page directory entry for the specified address.
3438 *
3439 * @returns Pointer to the page directory entry in question.
3440 * @returns NULL if the page directory is not present or on an invalid page.
3441 * @param pPGM Pointer to the PGM instance data.
3442 * @param GCPtr The address.
3443 */
3444DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3445{
3446 AssertGCPtr32(GCPtr);
3447
3448#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3449 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3450 AssertReturn(pGuestPDPT, 0);
3451#else
3452 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePDPT);
3453#endif
3454 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3455 if (pGuestPDPT->a[iPdPt].n.u1Present)
3456 {
3457 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3458#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3459 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3460 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3461#endif
3462
3463 /* The cache is out-of-sync. */
3464 PX86PDPAE pPD;
3465 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3466 if (RT_SUCCESS(rc))
3467 return &pPD->a[iPD];
3468 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3469 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3470 }
3471 return NULL;
3472}
3473
3474
3475/**
3476 * Gets the page directory entry for the specified address.
3477 *
3478 * @returns The page directory entry in question.
3479 * @returns A non-present entry if the page directory is not present or on an invalid page.
3480 * @param pPGM Pointer to the PGM instance data.
3481 * @param GCPtr The address.
3482 */
3483DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3484{
3485 AssertGCPtr32(GCPtr);
3486
3487#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3488 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3489 if (LIKELY(pGuestPDPT))
3490#else
3491 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePDPT);
3492#endif
3493 {
3494 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3495 if (pGuestPDPT->a[iPdPt].n.u1Present)
3496 {
3497 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3498#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3499 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3500 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3501#endif
3502
3503 /* cache is out-of-sync. */
3504 PX86PDPAE pPD;
3505 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3506 if (RT_SUCCESS(rc))
3507 return pPD->a[iPD];
3508 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3509 }
3510 }
3511 X86PDEPAE ZeroPde = {0};
3512 return ZeroPde;
3513}
3514
3515
3516/**
3517 * Gets the page directory pointer table entry for the specified address
3518 * and returns the index into the page directory
3519 *
3520 * @returns Pointer to the page directory in question.
3521 * @returns NULL if the page directory is not present or on an invalid page.
3522 * @param pPGM Pointer to the PGM instance data.
3523 * @param GCPtr The address.
3524 * @param piPD Receives the index into the returned page directory
3525 * @param pPdpe Receives the page directory pointer entry. Optional.
3526 */
3527DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3528{
3529 AssertGCPtr32(GCPtr);
3530
3531#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3532 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3533 AssertReturn(pGuestPDPT, 0);
3534#else
3535 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePDPT);
3536#endif
3537 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3538 if (pPdpe)
3539 *pPdpe = pGuestPDPT->a[iPdPt];
3540 if (pGuestPDPT->a[iPdPt].n.u1Present)
3541 {
3542 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3543#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3544 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3545 {
3546 *piPD = iPD;
3547 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3548 }
3549#endif
3550
3551 /* cache is out-of-sync. */
3552 PX86PDPAE pPD;
3553 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3554 if (RT_SUCCESS(rc))
3555 {
3556 *piPD = iPD;
3557 return pPD;
3558 }
3559 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3560 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3561 }
3562 return NULL;
3563}
3564
3565#ifndef IN_RC
3566
3567/**
3568 * Gets the page map level-4 pointer for the guest.
3569 *
3570 * @returns Pointer to the PML4 page.
3571 * @param pPGM Pointer to the PGM instance data.
3572 */
3573DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3574{
3575#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3576 PX86PML4 pGuestPml4;
3577 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3578 AssertRCReturn(rc, NULL);
3579 return pGuestPml4;
3580#else
3581 Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
3582 return pPGM->CTX_SUFF(pGstAmd64PML4);
3583#endif
3584}
3585
3586
3587/**
3588 * Gets the pointer to a page map level-4 entry.
3589 *
3590 * @returns Pointer to the PML4 entry.
3591 * @param pPGM Pointer to the PGM instance data.
3592 * @param iPml4 The index.
3593 */
3594DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3595{
3596#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3597 PX86PML4 pGuestPml4;
3598 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3599 AssertRCReturn(rc, NULL);
3600 return &pGuestPml4->a[iPml4];
3601#else
3602 Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
3603 return &pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4];
3604#endif
3605}
3606
3607
3608/**
3609 * Gets a page map level-4 entry.
3610 *
3611 * @returns The PML4 entry.
3612 * @param pPGM Pointer to the PGM instance data.
3613 * @param iPml4 The index.
3614 */
3615DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3616{
3617#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3618 PX86PML4 pGuestPml4;
3619 int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
3620 if (RT_FAILURE(rc))
3621 {
3622 X86PML4E ZeroPml4e = {0};
3623 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3624 }
3625 return pGuestPml4->a[iPml4];
3626#else
3627 Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
3628 return pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4];
3629#endif
3630}
3631
3632
3633/**
3634 * Gets the page directory pointer entry for the specified address.
3635 *
3636 * @returns Pointer to the page directory pointer entry in question.
3637 * @returns NULL if the page directory is not present or on an invalid page.
3638 * @param pPGM Pointer to the PGM instance data.
3639 * @param GCPtr The address.
3640 * @param ppPml4e Page Map Level-4 Entry (out)
3641 */
3642DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3643{
3644 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3645 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3646 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3647 if (pPml4e->n.u1Present)
3648 {
3649 PX86PDPT pPdpt;
3650 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3651 AssertRCReturn(rc, NULL);
3652
3653 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3654 return &pPdpt->a[iPdPt];
3655 }
3656 return NULL;
3657}
3658
3659
3660/**
3661 * Gets the page directory entry for the specified address.
3662 *
3663 * @returns The page directory entry in question.
3664 * @returns A non-present entry if the page directory is not present or on an invalid page.
3665 * @param pPGM Pointer to the PGM instance data.
3666 * @param GCPtr The address.
3667 * @param ppPml4e Page Map Level-4 Entry (out)
3668 * @param pPdpe Page directory pointer table entry (out)
3669 */
3670DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3671{
3672 X86PDEPAE ZeroPde = {0};
3673 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3674 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3675 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3676 if (pPml4e->n.u1Present)
3677 {
3678 PCX86PDPT pPdptTemp;
3679 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3680 AssertRCReturn(rc, ZeroPde);
3681
3682 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3683 *pPdpe = pPdptTemp->a[iPdPt];
3684 if (pPdptTemp->a[iPdPt].n.u1Present)
3685 {
3686 PCX86PDPAE pPD;
3687 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3688 AssertRCReturn(rc, ZeroPde);
3689
3690 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3691 return pPD->a[iPD];
3692 }
3693 }
3694
3695 return ZeroPde;
3696}
3697
3698
3699/**
3700 * Gets the page directory entry for the specified address.
3701 *
3702 * @returns The page directory entry in question.
3703 * @returns A non-present entry if the page directory is not present or on an invalid page.
3704 * @param pPGM Pointer to the PGM instance data.
3705 * @param GCPtr The address.
3706 */
3707DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
3708{
3709 X86PDEPAE ZeroPde = {0};
3710 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3711 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3712 if (pGuestPml4->a[iPml4].n.u1Present)
3713 {
3714 PCX86PDPT pPdptTemp;
3715 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3716 AssertRCReturn(rc, ZeroPde);
3717
3718 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3719 if (pPdptTemp->a[iPdPt].n.u1Present)
3720 {
3721 PCX86PDPAE pPD;
3722 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3723 AssertRCReturn(rc, ZeroPde);
3724
3725 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3726 return pPD->a[iPD];
3727 }
3728 }
3729 return ZeroPde;
3730}
3731
3732
3733/**
3734 * Gets the page directory entry for the specified address.
3735 *
3736 * @returns Pointer to the page directory entry in question.
3737 * @returns NULL if the page directory is not present or on an invalid page.
3738 * @param pPGM Pointer to the PGM instance data.
3739 * @param GCPtr The address.
3740 */
3741DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
3742{
3743 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3744 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3745 if (pGuestPml4->a[iPml4].n.u1Present)
3746 {
3747 PCX86PDPT pPdptTemp;
3748 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3749 AssertRCReturn(rc, NULL);
3750
3751 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3752 if (pPdptTemp->a[iPdPt].n.u1Present)
3753 {
3754 PX86PDPAE pPD;
3755 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3756 AssertRCReturn(rc, NULL);
3757
3758 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3759 return &pPD->a[iPD];
3760 }
3761 }
3762 return NULL;
3763}
3764
3765
3766/**
3767 * Gets the GUEST page directory pointer for the specified address.
3768 *
3769 * @returns The page directory in question.
3770 * @returns NULL if the page directory is not present or on an invalid page.
3771 * @param pPGM Pointer to the PGM instance data.
3772 * @param GCPtr The address.
3773 * @param ppPml4e Page Map Level-4 Entry (out)
3774 * @param pPdpe Page directory pointer table entry (out)
3775 * @param piPD Receives the index into the returned page directory
3776 */
3777DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3778{
3779 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3780 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3781 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3782 if (pPml4e->n.u1Present)
3783 {
3784 PCX86PDPT pPdptTemp;
3785 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3786 AssertRCReturn(rc, NULL);
3787
3788 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3789 *pPdpe = pPdptTemp->a[iPdPt];
3790 if (pPdptTemp->a[iPdPt].n.u1Present)
3791 {
3792 PX86PDPAE pPD;
3793 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3794 AssertRCReturn(rc, NULL);
3795
3796 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3797 return pPD;
3798 }
3799 }
3800 return 0;
3801}
3802
3803#endif /* !IN_RC */
3804
3805/**
3806 * Gets the shadow page pointer table, PAE.
3807 *
3808 * @returns Pointer to the shadow PAE PDPT.
3809 * @param pPGM Pointer to the PGM instance data.
3810 */
3811DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
3812{
3813#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3814 PX86PDPT pShwPdpt;
3815 Assert(pPGM->HCPhysPaePDPT != 0 && pPGM->HCPhysPaePDPT != NIL_RTHCPHYS);
3816 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysPaePDPT, &pShwPdpt);
3817 AssertRCReturn(rc, 0);
3818 return pShwPdpt;
3819#else
3820 return pPGM->CTX_SUFF(pShwPaePdpt);
3821#endif
3822}
3823
3824
3825/**
3826 * Gets the shadow page directory for the specified address, PAE.
3827 *
3828 * @returns Pointer to the shadow PD.
3829 * @param pPGM Pointer to the PGM instance data.
3830 * @param GCPtr Address.
3831 */
3832DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
3833{
3834 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3835#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3836 PX86PDPAE pPD;
3837 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
3838 AssertRCReturn(rc, 0);
3839 return pPD;
3840#else
3841 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
3842 Assert(pPD);
3843 return pPD;
3844#endif
3845}
3846
3847
3848/**
3849 * Gets the shadow page directory entry, PAE.
3850 *
3851 * @returns PDE.
3852 * @param pPGM Pointer to the PGM instance data.
3853 * @param GCPtr Address.
3854 */
3855DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3856{
3857 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3858 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3859#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3860 PCX86PDPAE pPD;
3861 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
3862 if (RT_FAILURE(rc))
3863 {
3864 X86PDEPAE ZeroPde = {0};
3865 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3866 }
3867 return pPD->a[iPd];
3868#else
3869 return pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]->a[iPd];
3870#endif
3871}
3872
3873
3874/**
3875 * Gets the pointer to the shadow page directory entry for an address, PAE.
3876 *
3877 * @returns Pointer to the PDE.
3878 * @param pPGM Pointer to the PGM instance data.
3879 * @param GCPtr Address.
3880 */
3881DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3882{
3883 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3884 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3885#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3886 PX86PDPAE pPD;
3887 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
3888 AssertRCReturn(rc, 0);
3889 return &pPD->a[iPd];
3890#else
3891 Assert(pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]);
3892 return &pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]->a[iPd];
3893#endif
3894}
3895
3896#ifndef IN_RC
3897
3898/**
3899 * Gets the shadow page map level-4 pointer.
3900 *
3901 * @returns Pointer to the shadow PML4.
3902 * @param pPGM Pointer to the PGM instance data.
3903 */
3904DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
3905{
3906#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3907 PX86PML4 pShwPml4;
3908 Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
3909 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysPaePML4, &pShwPml4);
3910 AssertRCReturn(rc, 0);
3911 return pShwPml4;
3912#else
3913 Assert(pPGM->CTX_SUFF(pShwPaePml4));
3914 return pPGM->CTX_SUFF(pShwPaePml4);
3915#endif
3916}
3917
3918
3919/**
3920 * Gets the shadow page map level-4 entry for the specified address.
3921 *
3922 * @returns The entry.
3923 * @param pPGM Pointer to the PGM instance data.
3924 * @param GCPtr The address.
3925 */
3926DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
3927{
3928 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3929# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3930 PCX86PML4 pShwPml4;
3931 Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
3932 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysPaePML4, &pShwPml4);
3933 if (RT_FAILURE(rc))
3934 {
3935 X86PML4E ZeroPml4e = {0};
3936 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3937 }
3938 return pShwPml4->a[iPml4];
3939# else
3940 Assert(pPGM->CTX_SUFF(pShwPaePml4));
3941 return pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4];
3942# endif
3943}
3944
3945
3946/**
3947 * Gets the pointer to the specified shadow page map level-4 entry.
3948 *
3949 * @returns The entry.
3950 * @param pPGM Pointer to the PGM instance data.
3951 * @param iPml4 The PML4 index.
3952 */
3953DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3954{
3955# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3956 PX86PML4 pShwPml4;
3957 Assert(pPGM->HCPhysPaePML4 != 0 && pPGM->HCPhysPaePML4 != NIL_RTHCPHYS);
3958 int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysPaePML4, &pShwPml4);
3959 AssertRCReturn(rc, 0);
3960 return &pShwPml4->a[iPml4];
3961# else
3962 Assert(pPGM->CTX_SUFF(pShwPaePml4));
3963 return &pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4];
3964# endif
3965}
3966
3967
3968/**
3969 * Gets the GUEST page directory pointer for the specified address.
3970 *
3971 * @returns The page directory in question.
3972 * @returns NULL if the page directory is not present or on an invalid page.
3973 * @param pPGM Pointer to the PGM instance data.
3974 * @param GCPtr The address.
3975 * @param piPD Receives the index into the returned page directory
3976 */
3977DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
3978{
3979 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3980 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3981 if (pGuestPml4->a[iPml4].n.u1Present)
3982 {
3983 PCX86PDPT pPdptTemp;
3984 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3985 AssertRCReturn(rc, NULL);
3986
3987 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3988 if (pPdptTemp->a[iPdPt].n.u1Present)
3989 {
3990 PX86PDPAE pPD;
3991 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3992 AssertRCReturn(rc, NULL);
3993
3994 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3995 return pPD;
3996 }
3997 }
3998 return NULL;
3999}
4000
4001#endif /* !IN_RC */
4002
4003/**
4004 * Checks if any of the specified page flags are set for the given page.
4005 *
4006 * @returns true if any of the flags are set.
4007 * @returns false if all the flags are clear.
4008 * @param pPGM PGM handle.
4009 * @param GCPhys The GC physical address.
4010 * @param fFlags The flags to check for.
4011 */
4012DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4013{
4014 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4015 return pPage
4016 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4017}
4018
4019
4020/**
4021 * Gets the page state for a physical handler.
4022 *
4023 * @returns The physical handler page state.
4024 * @param pCur The physical handler in question.
4025 */
4026DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4027{
4028 switch (pCur->enmType)
4029 {
4030 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4031 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4032
4033 case PGMPHYSHANDLERTYPE_MMIO:
4034 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4035 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4036
4037 default:
4038 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4039 }
4040}
4041
4042
4043/**
4044 * Gets the page state for a virtual handler.
4045 *
4046 * @returns The virtual handler page state.
4047 * @param pCur The virtual handler in question.
4048 * @remarks This should never be used on a hypervisor access handler.
4049 */
4050DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4051{
4052 switch (pCur->enmType)
4053 {
4054 case PGMVIRTHANDLERTYPE_WRITE:
4055 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4056 case PGMVIRTHANDLERTYPE_ALL:
4057 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4058 default:
4059 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4060 }
4061}
4062
4063
4064/**
4065 * Clears one physical page of a virtual handler
4066 *
4067 * @param pPGM Pointer to the PGM instance.
4068 * @param pCur Virtual handler structure
4069 * @param iPage Physical page index
4070 *
4071 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4072 * need to care about other handlers in the same page.
4073 */
4074DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4075{
4076 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4077
4078 /*
4079 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4080 */
4081#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4082 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4083 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4084 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4085#endif
4086 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4087 {
4088 /* We're the head of the alias chain. */
4089 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4090#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4091 AssertReleaseMsg(pRemove != NULL,
4092 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4093 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4094 AssertReleaseMsg(pRemove == pPhys2Virt,
4095 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4096 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4097 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4098 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4099#endif
4100 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4101 {
4102 /* Insert the next list in the alias chain into the tree. */
4103 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4104#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4105 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4106 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4107 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4108#endif
4109 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4110 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4111 AssertRelease(fRc);
4112 }
4113 }
4114 else
4115 {
4116 /* Locate the previous node in the alias chain. */
4117 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4118#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4119 AssertReleaseMsg(pPrev != pPhys2Virt,
4120 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4121 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4122#endif
4123 for (;;)
4124 {
4125 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4126 if (pNext == pPhys2Virt)
4127 {
4128 /* unlink. */
4129 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4130 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4131 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4132 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4133 else
4134 {
4135 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4136 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4137 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4138 }
4139 break;
4140 }
4141
4142 /* next */
4143 if (pNext == pPrev)
4144 {
4145#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4146 AssertReleaseMsg(pNext != pPrev,
4147 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4148 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4149#endif
4150 break;
4151 }
4152 pPrev = pNext;
4153 }
4154 }
4155 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4156 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4157 pPhys2Virt->offNextAlias = 0;
4158 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4159
4160 /*
4161 * Clear the ram flags for this page.
4162 */
4163 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4164 AssertReturnVoid(pPage);
4165 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4166}
4167
4168
4169/**
4170 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4171 *
4172 * @returns Pointer to the shadow page structure.
4173 * @param pPool The pool.
4174 * @param HCPhys The HC physical address of the shadow page.
4175 */
4176DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4177{
4178 /*
4179 * Look up the page.
4180 */
4181 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4182 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
4183 return pPage;
4184}
4185
4186
4187/**
4188 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4189 *
4190 * @returns Pointer to the shadow page structure.
4191 * @param pPool The pool.
4192 * @param idx The pool page index.
4193 */
4194DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4195{
4196 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4197 return &pPool->aPages[idx];
4198}
4199
4200
4201#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4202/**
4203 * Clear references to guest physical memory.
4204 *
4205 * @param pPool The pool.
4206 * @param pPoolPage The pool page.
4207 * @param pPhysPage The physical guest page tracking structure.
4208 */
4209DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4210{
4211 /*
4212 * Just deal with the simple case here.
4213 */
4214# ifdef LOG_ENABLED
4215 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4216# endif
4217 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4218 if (cRefs == 1)
4219 {
4220 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4221 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4222 }
4223 else
4224 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4225 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4226}
4227#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4228
4229
4230#ifdef PGMPOOL_WITH_CACHE
4231/**
4232 * Moves the page to the head of the age list.
4233 *
4234 * This is done when the cached page is used in one way or another.
4235 *
4236 * @param pPool The pool.
4237 * @param pPage The cached page.
4238 * @todo inline in PGMInternal.h!
4239 */
4240DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4241{
4242 /*
4243 * Move to the head of the age list.
4244 */
4245 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4246 {
4247 /* unlink */
4248 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4249 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4250 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4251 else
4252 pPool->iAgeTail = pPage->iAgePrev;
4253
4254 /* insert at head */
4255 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4256 pPage->iAgeNext = pPool->iAgeHead;
4257 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4258 pPool->iAgeHead = pPage->idx;
4259 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4260 }
4261}
4262#endif /* PGMPOOL_WITH_CACHE */
4263
4264/**
4265 * Tells if mappings are to be put into the shadow page table or not
4266 *
4267 * @returns boolean result
4268 * @param pVM VM handle.
4269 */
4270
4271DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4272{
4273#ifdef IN_RING0
4274 /* There are no mappings in VT-x and AMD-V mode. */
4275 Assert(pPGM->fDisableMappings);
4276 return false;
4277#else
4278 return !pPGM->fDisableMappings;
4279#endif
4280}
4281
4282/** @} */
4283
4284#endif
4285
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