VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 15344

Last change on this file since 15344 was 15344, checked in by vboxsync, 16 years ago

#3202: Optimizations of the dynamic page mapping code (ring-0). Do lots of the stuff inline, using the set as a 2st level cache and not releasing it for each inner VT-x iteration.

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1/* $Id: PGMInternal.h 15344 2008-12-12 00:13:56Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) \
201 ( (uGstType) >= PGM_TYPE_32BIT \
202 && (uShwType) != PGM_TYPE_NESTED \
203 && (uShwType) != PGM_TYPE_EPT)
204
205/** Macro for checking if the guest supports the NX bit.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_NX(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_PAE \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215
216/** @def PGM_HCPHYS_2_PTR
217 * Maps a HC physical page pool address to a virtual address.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM handle.
221 * @param HCPhys The HC physical address to map to a virtual one.
222 * @param ppv Where to store the virtual address. No need to cast this.
223 *
224 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225 * small page window employeed by that function. Be careful.
226 * @remark There is no need to assert on the result.
227 */
228#ifdef IN_RC
229# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
232# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
234#else
235# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
237#endif
238
239/** @def PGM_HCPHYS_2_PTR_BY_PGM
240 * Maps a HC physical page pool address to a virtual address.
241 *
242 * @returns VBox status code.
243 * @param pPGM The PGM instance data.
244 * @param HCPhys The HC physical address to map to a virtual one.
245 * @param ppv Where to store the virtual address. No need to cast this.
246 *
247 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
248 * small page window employeed by that function. Be careful.
249 * @remark There is no need to assert on the result.
250 */
251#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
252# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
253 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
254#else
255# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
256 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
257#endif
258
259/** @def PGM_GCPHYS_2_PTR
260 * Maps a GC physical page address to a virtual address.
261 *
262 * @returns VBox status code.
263 * @param pVM The VM handle.
264 * @param GCPhys The GC physical address to map to a virtual one.
265 * @param ppv Where to store the virtual address. No need to cast this.
266 *
267 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
268 * small page window employeed by that function. Be careful.
269 * @remark There is no need to assert on the result.
270 */
271#ifdef IN_RC
272# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
273 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
274#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
275# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
276 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
277#else
278# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
280#endif
281
282/** @def PGM_GCPHYS_2_PTR_BY_PGM
283 * Maps a GC physical page address to a virtual address.
284 *
285 * @returns VBox status code.
286 * @param pPGM Pointer to the PGM instance data.
287 * @param GCPhys The GC physical address to map to a virtual one.
288 * @param ppv Where to store the virtual address. No need to cast this.
289 *
290 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
291 * small page window employeed by that function. Be careful.
292 * @remark There is no need to assert on the result.
293 */
294#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
295# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
296 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
297#else
298# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
299 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
300#endif
301
302/** @def PGM_GCPHYS_2_PTR_EX
303 * Maps a unaligned GC physical page address to a virtual address.
304 *
305 * @returns VBox status code.
306 * @param pVM The VM handle.
307 * @param GCPhys The GC physical address to map to a virtual one.
308 * @param ppv Where to store the virtual address. No need to cast this.
309 *
310 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
311 * small page window employeed by that function. Be careful.
312 * @remark There is no need to assert on the result.
313 */
314#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
315# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
316 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
317#else
318# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
319 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
320#endif
321
322/** @def PGM_INVL_PG
323 * Invalidates a page when in GC does nothing in HC.
324 *
325 * @param GCVirt The virtual address of the page to invalidate.
326 */
327#ifdef IN_RC
328# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
329#elif defined(IN_RING0)
330# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
331#else
332# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
333#endif
334
335/** @def PGM_INVL_BIG_PG
336 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
337 *
338 * @param GCVirt The virtual address within the page directory to invalidate.
339 */
340#ifdef IN_RC
341# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
342#elif defined(IN_RING0)
343# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
344#else
345# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
346#endif
347
348/** @def PGM_INVL_GUEST_TLBS()
349 * Invalidates all guest TLBs.
350 */
351#ifdef IN_RC
352# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
353#elif defined(IN_RING0)
354# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
355#else
356# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
357#endif
358
359
360/**
361 * Structure for tracking GC Mappings.
362 *
363 * This structure is used by linked list in both GC and HC.
364 */
365typedef struct PGMMAPPING
366{
367 /** Pointer to next entry. */
368 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
369 /** Pointer to next entry. */
370 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
371 /** Pointer to next entry. */
372 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
373#if GC_ARCH_BITS == 64
374 RTRCPTR padding0;
375#endif
376 /** Start Virtual address. */
377 RTGCPTR GCPtr;
378 /** Last Virtual address (inclusive). */
379 RTGCPTR GCPtrLast;
380 /** Range size (bytes). */
381 RTGCPTR cb;
382 /** Pointer to relocation callback function. */
383 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
384 /** User argument to the callback. */
385 R3PTRTYPE(void *) pvUser;
386 /** Mapping description / name. For easing debugging. */
387 R3PTRTYPE(const char *) pszDesc;
388 /** Number of page tables. */
389 RTUINT cPTs;
390#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
391 RTUINT uPadding1; /**< Alignment padding. */
392#endif
393 /** Array of page table mapping data. Each entry
394 * describes one page table. The array can be longer
395 * than the declared length.
396 */
397 struct
398 {
399 /** The HC physical address of the page table. */
400 RTHCPHYS HCPhysPT;
401 /** The HC physical address of the first PAE page table. */
402 RTHCPHYS HCPhysPaePT0;
403 /** The HC physical address of the second PAE page table. */
404 RTHCPHYS HCPhysPaePT1;
405 /** The HC virtual address of the 32-bit page table. */
406 R3PTRTYPE(PX86PT) pPTR3;
407 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
408 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
409 /** The GC virtual address of the 32-bit page table. */
410 RCPTRTYPE(PX86PT) pPTRC;
411 /** The GC virtual address of the two PAE page table. */
412 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
413 /** The GC virtual address of the 32-bit page table. */
414 R0PTRTYPE(PX86PT) pPTR0;
415 /** The GC virtual address of the two PAE page table. */
416 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
417 } aPTs[1];
418} PGMMAPPING;
419/** Pointer to structure for tracking GC Mappings. */
420typedef struct PGMMAPPING *PPGMMAPPING;
421
422
423/**
424 * Physical page access handler structure.
425 *
426 * This is used to keep track of physical address ranges
427 * which are being monitored in some kind of way.
428 */
429typedef struct PGMPHYSHANDLER
430{
431 AVLROGCPHYSNODECORE Core;
432 /** Access type. */
433 PGMPHYSHANDLERTYPE enmType;
434 /** Number of pages to update. */
435 uint32_t cPages;
436 /** Pointer to R3 callback function. */
437 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
438 /** User argument for R3 handlers. */
439 R3PTRTYPE(void *) pvUserR3;
440 /** Pointer to R0 callback function. */
441 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
442 /** User argument for R0 handlers. */
443 R0PTRTYPE(void *) pvUserR0;
444 /** Pointer to GC callback function. */
445 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
446 /** User argument for RC handlers. */
447 RCPTRTYPE(void *) pvUserRC;
448 /** Description / Name. For easing debugging. */
449 R3PTRTYPE(const char *) pszDesc;
450#ifdef VBOX_WITH_STATISTICS
451 /** Profiling of this handler. */
452 STAMPROFILE Stat;
453#endif
454} PGMPHYSHANDLER;
455/** Pointer to a physical page access handler structure. */
456typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
457
458
459/**
460 * Cache node for the physical addresses covered by a virtual handler.
461 */
462typedef struct PGMPHYS2VIRTHANDLER
463{
464 /** Core node for the tree based on physical ranges. */
465 AVLROGCPHYSNODECORE Core;
466 /** Offset from this struct to the PGMVIRTHANDLER structure. */
467 int32_t offVirtHandler;
468 /** Offset of the next alias relative to this one.
469 * Bit 0 is used for indicating whether we're in the tree.
470 * Bit 1 is used for indicating that we're the head node.
471 */
472 int32_t offNextAlias;
473} PGMPHYS2VIRTHANDLER;
474/** Pointer to a phys to virtual handler structure. */
475typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
476
477/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
478 * node is in the tree. */
479#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
480/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
481 * node is in the head of an alias chain.
482 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
483#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
484/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
485#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
486
487
488/**
489 * Virtual page access handler structure.
490 *
491 * This is used to keep track of virtual address ranges
492 * which are being monitored in some kind of way.
493 */
494typedef struct PGMVIRTHANDLER
495{
496 /** Core node for the tree based on virtual ranges. */
497 AVLROGCPTRNODECORE Core;
498 /** Size of the range (in bytes). */
499 RTGCPTR cb;
500 /** Number of cache pages. */
501 uint32_t cPages;
502 /** Access type. */
503 PGMVIRTHANDLERTYPE enmType;
504 /** Pointer to the RC callback function. */
505 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
506#if HC_ARCH_BITS == 64
507 RTRCPTR padding;
508#endif
509 /** Pointer to the R3 callback function for invalidation. */
510 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
511 /** Pointer to the R3 callback function. */
512 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
513 /** Description / Name. For easing debugging. */
514 R3PTRTYPE(const char *) pszDesc;
515#ifdef VBOX_WITH_STATISTICS
516 /** Profiling of this handler. */
517 STAMPROFILE Stat;
518#endif
519 /** Array of cached physical addresses for the monitored ranged. */
520 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
521} PGMVIRTHANDLER;
522/** Pointer to a virtual page access handler structure. */
523typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
524
525
526/**
527 * Page type.
528 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
529 * @todo convert to \#defines.
530 */
531typedef enum PGMPAGETYPE
532{
533 /** The usual invalid zero entry. */
534 PGMPAGETYPE_INVALID = 0,
535 /** RAM page. (RWX) */
536 PGMPAGETYPE_RAM,
537 /** MMIO2 page. (RWX) */
538 PGMPAGETYPE_MMIO2,
539 /** Shadowed ROM. (RWX) */
540 PGMPAGETYPE_ROM_SHADOW,
541 /** ROM page. (R-X) */
542 PGMPAGETYPE_ROM,
543 /** MMIO page. (---) */
544 PGMPAGETYPE_MMIO,
545 /** End of valid entries. */
546 PGMPAGETYPE_END
547} PGMPAGETYPE;
548AssertCompile(PGMPAGETYPE_END < 7);
549
550/** @name Page type predicates.
551 * @{ */
552#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
553#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
554#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
555#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
556#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
557/** @} */
558
559
560/**
561 * A Physical Guest Page tracking structure.
562 *
563 * The format of this structure is complicated because we have to fit a lot
564 * of information into as few bits as possible. The format is also subject
565 * to change (there is one comming up soon). Which means that for we'll be
566 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
567 * accessess to the structure.
568 */
569typedef struct PGMPAGE
570{
571 /** The physical address and a whole lot of other stuff. All bits are used! */
572 RTHCPHYS HCPhys;
573 /** The page state. */
574 uint32_t u2StateX : 2;
575 /** Flag indicating that a write monitored page was written to when set. */
576 uint32_t fWrittenToX : 1;
577 /** For later. */
578 uint32_t fSomethingElse : 1;
579 /** The Page ID.
580 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
581 * The HCPhys will be 100% static. */
582 uint32_t idPageX : 28;
583 /** The page type (PGMPAGETYPE). */
584 uint32_t u3Type : 3;
585 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
586 uint32_t u2HandlerPhysStateX : 2;
587 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
588 uint32_t u2HandlerVirtStateX : 2;
589 uint32_t u29B : 25;
590} PGMPAGE;
591AssertCompileSize(PGMPAGE, 16);
592/** Pointer to a physical guest page. */
593typedef PGMPAGE *PPGMPAGE;
594/** Pointer to a const physical guest page. */
595typedef const PGMPAGE *PCPGMPAGE;
596/** Pointer to a physical guest page pointer. */
597typedef PPGMPAGE *PPPGMPAGE;
598
599
600/**
601 * Clears the page structure.
602 * @param pPage Pointer to the physical guest page tracking structure.
603 */
604#define PGM_PAGE_CLEAR(pPage) \
605 do { \
606 (pPage)->HCPhys = 0; \
607 (pPage)->u2StateX = 0; \
608 (pPage)->fWrittenToX = 0; \
609 (pPage)->fSomethingElse = 0; \
610 (pPage)->idPageX = 0; \
611 (pPage)->u3Type = 0; \
612 (pPage)->u29B = 0; \
613 } while (0)
614
615/**
616 * Initializes the page structure.
617 * @param pPage Pointer to the physical guest page tracking structure.
618 */
619#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
620 do { \
621 (pPage)->HCPhys = (_HCPhys); \
622 (pPage)->u2StateX = (_uState); \
623 (pPage)->fWrittenToX = 0; \
624 (pPage)->fSomethingElse = 0; \
625 (pPage)->idPageX = (_idPage); \
626 /*(pPage)->u3Type = (_uType); - later */ \
627 PGM_PAGE_SET_TYPE(pPage, _uType); \
628 (pPage)->u29B = 0; \
629 } while (0)
630
631/**
632 * Initializes the page structure of a ZERO page.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#ifdef VBOX_WITH_NEW_PHYS_CODE
636# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
637 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
638#else
639# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
640 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
641#endif
642/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
643# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
644 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645
646
647/** @name The Page state, PGMPAGE::u2StateX.
648 * @{ */
649/** The zero page.
650 * This is a per-VM page that's never ever mapped writable. */
651#define PGM_PAGE_STATE_ZERO 0
652/** A allocated page.
653 * This is a per-VM page allocated from the page pool (or wherever
654 * we get MMIO2 pages from if the type is MMIO2).
655 */
656#define PGM_PAGE_STATE_ALLOCATED 1
657/** A allocated page that's being monitored for writes.
658 * The shadow page table mappings are read-only. When a write occurs, the
659 * fWrittenTo member is set, the page remapped as read-write and the state
660 * moved back to allocated. */
661#define PGM_PAGE_STATE_WRITE_MONITORED 2
662/** The page is shared, aka. copy-on-write.
663 * This is a page that's shared with other VMs. */
664#define PGM_PAGE_STATE_SHARED 3
665/** @} */
666
667
668/**
669 * Gets the page state.
670 * @returns page state (PGM_PAGE_STATE_*).
671 * @param pPage Pointer to the physical guest page tracking structure.
672 */
673#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
674
675/**
676 * Sets the page state.
677 * @param pPage Pointer to the physical guest page tracking structure.
678 * @param _uState The new page state.
679 */
680#define PGM_PAGE_SET_STATE(pPage, _uState) \
681 do { (pPage)->u2StateX = (_uState); } while (0)
682
683
684/**
685 * Gets the host physical address of the guest page.
686 * @returns host physical address (RTHCPHYS).
687 * @param pPage Pointer to the physical guest page tracking structure.
688 */
689#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
690
691/**
692 * Sets the host physical address of the guest page.
693 * @param pPage Pointer to the physical guest page tracking structure.
694 * @param _HCPhys The new host physical address.
695 */
696#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
697 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
698 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
699
700/**
701 * Get the Page ID.
702 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
703 * @param pPage Pointer to the physical guest page tracking structure.
704 */
705#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
706/* later:
707#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
708 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
709*/
710/**
711 * Sets the Page ID.
712 * @param pPage Pointer to the physical guest page tracking structure.
713 */
714#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
715/* later:
716#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
717 | ((_idPage) & 0xfff) \
718 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
719*/
720
721/**
722 * Get the Chunk ID.
723 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
724 * @param pPage Pointer to the physical guest page tracking structure.
725 */
726#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
727/* later:
728#if GMM_CHUNKID_SHIFT == 12
729# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
730#elif GMM_CHUNKID_SHIFT > 12
731# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
732#elif GMM_CHUNKID_SHIFT < 12
733# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
734 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
735#else
736# error "GMM_CHUNKID_SHIFT isn't defined or something."
737#endif
738*/
739
740/**
741 * Get the index of the page within the allocaiton chunk.
742 * @returns The page index.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 */
745#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
746/* later:
747#if GMM_CHUNKID_SHIFT <= 12
748# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
749#else
750# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
751 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
752#endif
753*/
754
755
756/**
757 * Gets the page type.
758 * @returns The page type.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
762
763/**
764 * Sets the page type.
765 * @param pPage Pointer to the physical guest page tracking structure.
766 * @param _enmType The new page type (PGMPAGETYPE).
767 */
768#ifdef VBOX_WITH_NEW_PHYS_CODE
769#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
770 do { (pPage)->u3Type = (_enmType); } while (0)
771#else
772#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
773 do { \
774 (pPage)->u3Type = (_enmType); \
775 if ((_enmType) == PGMPAGETYPE_ROM) \
776 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
777 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
778 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
779 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
780 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
781 } while (0)
782#endif
783
784
785/**
786 * Checks if the page is 'reserved'.
787 * @returns true/false.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
791
792/**
793 * Checks if the page is marked for MMIO.
794 * @returns true/false.
795 * @param pPage Pointer to the physical guest page tracking structure.
796 */
797#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
798
799/**
800 * Checks if the page is backed by the ZERO page.
801 * @returns true/false.
802 * @param pPage Pointer to the physical guest page tracking structure.
803 */
804#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
805
806/**
807 * Checks if the page is backed by a SHARED page.
808 * @returns true/false.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
812
813
814/**
815 * Marks the paget as written to (for GMM change monitoring).
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
819
820/**
821 * Clears the written-to indicator.
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
825
826/**
827 * Checks if the page was marked as written-to.
828 * @returns true/false.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
832
833
834/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
835 *
836 * @remarks The values are assigned in order of priority, so we can calculate
837 * the correct state for a page with different handlers installed.
838 * @{ */
839/** No handler installed. */
840#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
841/** Monitoring is temporarily disabled. */
842#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
843/** Write access is monitored. */
844#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
845/** All access is monitored. */
846#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
847/** @} */
848
849/**
850 * Gets the physical access handler state of a page.
851 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
852 * @param pPage Pointer to the physical guest page tracking structure.
853 */
854#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
855
856/**
857 * Sets the physical access handler state of a page.
858 * @param pPage Pointer to the physical guest page tracking structure.
859 * @param _uState The new state value.
860 */
861#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
862 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
863
864/**
865 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
866 * @returns true/false
867 * @param pPage Pointer to the physical guest page tracking structure.
868 */
869#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
870
871/**
872 * Checks if the page has any active physical access handlers.
873 * @returns true/false
874 * @param pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
877
878
879/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
880 *
881 * @remarks The values are assigned in order of priority, so we can calculate
882 * the correct state for a page with different handlers installed.
883 * @{ */
884/** No handler installed. */
885#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
886/* 1 is reserved so the lineup is identical with the physical ones. */
887/** Write access is monitored. */
888#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
889/** All access is monitored. */
890#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
891/** @} */
892
893/**
894 * Gets the virtual access handler state of a page.
895 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
896 * @param pPage Pointer to the physical guest page tracking structure.
897 */
898#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
899
900/**
901 * Sets the virtual access handler state of a page.
902 * @param pPage Pointer to the physical guest page tracking structure.
903 * @param _uState The new state value.
904 */
905#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
906 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
907
908/**
909 * Checks if the page has any virtual access handlers.
910 * @returns true/false
911 * @param pPage Pointer to the physical guest page tracking structure.
912 */
913#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
914
915/**
916 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
917 * virtual handlers.
918 * @returns true/false
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
922
923
924
925/**
926 * Checks if the page has any access handlers, including temporarily disabled ones.
927 * @returns true/false
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
931 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
932 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
933
934/**
935 * Checks if the page has any active access handlers.
936 * @returns true/false
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
940 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
941 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
942
943/**
944 * Checks if the page has any active access handlers catching all accesses.
945 * @returns true/false
946 * @param pPage Pointer to the physical guest page tracking structure.
947 */
948#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
949 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
950 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
951
952
953/**
954 * Ram range for GC Phys to HC Phys conversion.
955 *
956 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
957 * conversions too, but we'll let MM handle that for now.
958 *
959 * This structure is used by linked lists in both GC and HC.
960 */
961typedef struct PGMRAMRANGE
962{
963 /** Pointer to the next RAM range - for R3. */
964 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
965 /** Pointer to the next RAM range - for R0. */
966 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
967 /** Pointer to the next RAM range - for RC. */
968 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
969 /** Pointer alignment. */
970 RTRCPTR RCPtrAlignment;
971 /** Start of the range. Page aligned. */
972 RTGCPHYS GCPhys;
973 /** Last address in the range (inclusive). Page aligned (-1). */
974 RTGCPHYS GCPhysLast;
975 /** Size of the range. (Page aligned of course). */
976 RTGCPHYS cb;
977 /** MM_RAM_* flags */
978 uint32_t fFlags;
979 uint32_t u32Alignment; /**< alignment. */
980#ifndef VBOX_WITH_NEW_PHYS_CODE
981 /** R3 virtual lookup ranges for chunks.
982 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
983 * @remarks This is occationally accessed from ring-0!! (not darwin) */
984# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
986# else
987 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
988# endif
989#endif
990 /** Start of the HC mapping of the range. This is only used for MMIO2. */
991 R3PTRTYPE(void *) pvR3;
992 /** The range description. */
993 R3PTRTYPE(const char *) pszDesc;
994
995 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
996#ifdef VBOX_WITH_NEW_PHYS_CODE
997 uint32_t au32Reserved[2];
998#elif HC_ARCH_BITS == 32
999 uint32_t au32Reserved[1];
1000#endif
1001
1002 /** Array of physical guest page tracking structures. */
1003 PGMPAGE aPages[1];
1004} PGMRAMRANGE;
1005/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1006typedef PGMRAMRANGE *PPGMRAMRANGE;
1007
1008/** Return hc ptr corresponding to the ram range and physical offset */
1009#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1010 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1011 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1012
1013/**
1014 * Per page tracking structure for ROM image.
1015 *
1016 * A ROM image may have a shadow page, in which case we may have
1017 * two pages backing it. This structure contains the PGMPAGE for
1018 * both while PGMRAMRANGE have a copy of the active one. It is
1019 * important that these aren't out of sync in any regard other
1020 * than page pool tracking data.
1021 */
1022typedef struct PGMROMPAGE
1023{
1024 /** The page structure for the virgin ROM page. */
1025 PGMPAGE Virgin;
1026 /** The page structure for the shadow RAM page. */
1027 PGMPAGE Shadow;
1028 /** The current protection setting. */
1029 PGMROMPROT enmProt;
1030 /** Pad the structure size to a multiple of 8. */
1031 uint32_t u32Padding;
1032} PGMROMPAGE;
1033/** Pointer to a ROM page tracking structure. */
1034typedef PGMROMPAGE *PPGMROMPAGE;
1035
1036
1037/**
1038 * A registered ROM image.
1039 *
1040 * This is needed to keep track of ROM image since they generally
1041 * intrude into a PGMRAMRANGE. It also keeps track of additional
1042 * info like the two page sets (read-only virgin and read-write shadow),
1043 * the current state of each page.
1044 *
1045 * Because access handlers cannot easily be executed in a different
1046 * context, the ROM ranges needs to be accessible and in all contexts.
1047 */
1048typedef struct PGMROMRANGE
1049{
1050 /** Pointer to the next range - R3. */
1051 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1052 /** Pointer to the next range - R0. */
1053 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1054 /** Pointer to the next range - RC. */
1055 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1056 /** Pointer alignment */
1057 RTRCPTR GCPtrAlignment;
1058 /** Address of the range. */
1059 RTGCPHYS GCPhys;
1060 /** Address of the last byte in the range. */
1061 RTGCPHYS GCPhysLast;
1062 /** Size of the range. */
1063 RTGCPHYS cb;
1064 /** The flags (PGMPHYS_ROM_FLAG_*). */
1065 uint32_t fFlags;
1066 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1067 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1068 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1069 * This is used for strictness checks. */
1070 R3PTRTYPE(const void *) pvOriginal;
1071 /** The ROM description. */
1072 R3PTRTYPE(const char *) pszDesc;
1073 /** The per page tracking structures. */
1074 PGMROMPAGE aPages[1];
1075} PGMROMRANGE;
1076/** Pointer to a ROM range. */
1077typedef PGMROMRANGE *PPGMROMRANGE;
1078
1079
1080/**
1081 * A registered MMIO2 (= Device RAM) range.
1082 *
1083 * There are a few reason why we need to keep track of these
1084 * registrations. One of them is the deregistration & cleanup
1085 * stuff, while another is that the PGMRAMRANGE associated with
1086 * such a region may have to be removed from the ram range list.
1087 *
1088 * Overlapping with a RAM range has to be 100% or none at all. The
1089 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1090 * meditation will be raised if a partial overlap or an overlap of
1091 * ROM pages is encountered. On an overlap we will free all the
1092 * existing RAM pages and put in the ram range pages instead.
1093 */
1094typedef struct PGMMMIO2RANGE
1095{
1096 /** The owner of the range. (a device) */
1097 PPDMDEVINSR3 pDevInsR3;
1098 /** Pointer to the ring-3 mapping of the allocation. */
1099 RTR3PTR pvR3;
1100 /** Pointer to the next range - R3. */
1101 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1102 /** Whether it's mapped or not. */
1103 bool fMapped;
1104 /** Whether it's overlapping or not. */
1105 bool fOverlapping;
1106 /** The PCI region number.
1107 * @remarks This ASSUMES that nobody will ever really need to have multiple
1108 * PCI devices with matching MMIO region numbers on a single device. */
1109 uint8_t iRegion;
1110 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1111 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1112 /** The associated RAM range. */
1113 PGMRAMRANGE RamRange;
1114} PGMMMIO2RANGE;
1115/** Pointer to a MMIO2 range. */
1116typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1117
1118
1119
1120
1121/**
1122 * PGMPhysRead/Write cache entry
1123 */
1124typedef struct PGMPHYSCACHEENTRY
1125{
1126 /** R3 pointer to physical page. */
1127 R3PTRTYPE(uint8_t *) pbR3;
1128 /** GC Physical address for cache entry */
1129 RTGCPHYS GCPhys;
1130#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1131 RTGCPHYS u32Padding0; /**< alignment padding. */
1132#endif
1133} PGMPHYSCACHEENTRY;
1134
1135/**
1136 * PGMPhysRead/Write cache to reduce REM memory access overhead
1137 */
1138typedef struct PGMPHYSCACHE
1139{
1140 /** Bitmap of valid cache entries */
1141 uint64_t aEntries;
1142 /** Cache entries */
1143 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1144} PGMPHYSCACHE;
1145
1146
1147/** Pointer to an allocation chunk ring-3 mapping. */
1148typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1149/** Pointer to an allocation chunk ring-3 mapping pointer. */
1150typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1151
1152/**
1153 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1154 *
1155 * The primary tree (Core) uses the chunk id as key.
1156 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1157 */
1158typedef struct PGMCHUNKR3MAP
1159{
1160 /** The key is the chunk id. */
1161 AVLU32NODECORE Core;
1162 /** The key is the ageing sequence number. */
1163 AVLLU32NODECORE AgeCore;
1164 /** The current age thingy. */
1165 uint32_t iAge;
1166 /** The current reference count. */
1167 uint32_t volatile cRefs;
1168 /** The current permanent reference count. */
1169 uint32_t volatile cPermRefs;
1170 /** The mapping address. */
1171 void *pv;
1172} PGMCHUNKR3MAP;
1173
1174/**
1175 * Allocation chunk ring-3 mapping TLB entry.
1176 */
1177typedef struct PGMCHUNKR3MAPTLBE
1178{
1179 /** The chunk id. */
1180 uint32_t volatile idChunk;
1181#if HC_ARCH_BITS == 64
1182 uint32_t u32Padding; /**< alignment padding. */
1183#endif
1184 /** The chunk map. */
1185#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1186 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1187#else
1188 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1189#endif
1190} PGMCHUNKR3MAPTLBE;
1191/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1192typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1193
1194/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1195 * @remark Must be a power of two value. */
1196#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1197
1198/**
1199 * Allocation chunk ring-3 mapping TLB.
1200 *
1201 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1202 * At first glance this might look kinda odd since AVL trees are
1203 * supposed to give the most optimial lookup times of all trees
1204 * due to their balancing. However, take a tree with 1023 nodes
1205 * in it, that's 10 levels, meaning that most searches has to go
1206 * down 9 levels before they find what they want. This isn't fast
1207 * compared to a TLB hit. There is the factor of cache misses,
1208 * and of course the problem with trees and branch prediction.
1209 * This is why we use TLBs in front of most of the trees.
1210 *
1211 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1212 * difficult when we switch to the new inlined AVL trees (from kStuff).
1213 */
1214typedef struct PGMCHUNKR3MAPTLB
1215{
1216 /** The TLB entries. */
1217 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1218} PGMCHUNKR3MAPTLB;
1219
1220/**
1221 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1222 * @returns Chunk TLB index.
1223 * @param idChunk The Chunk ID.
1224 */
1225#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1226
1227
1228/**
1229 * Ring-3 guest page mapping TLB entry.
1230 * @remarks used in ring-0 as well at the moment.
1231 */
1232typedef struct PGMPAGER3MAPTLBE
1233{
1234 /** Address of the page. */
1235 RTGCPHYS volatile GCPhys;
1236 /** The guest page. */
1237#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1238 R3PTRTYPE(PPGMPAGE) volatile pPage;
1239#else
1240 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1241#endif
1242 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1243#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1244 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1245#else
1246 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1247#endif
1248 /** The address */
1249#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250 R3PTRTYPE(void *) volatile pv;
1251#else
1252 R3R0PTRTYPE(void *) volatile pv;
1253#endif
1254#if HC_ARCH_BITS == 32
1255 uint32_t u32Padding; /**< alignment padding. */
1256#endif
1257} PGMPAGER3MAPTLBE;
1258/** Pointer to an entry in the HC physical TLB. */
1259typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1260
1261
1262/** The number of entries in the ring-3 guest page mapping TLB.
1263 * @remarks The value must be a power of two. */
1264#define PGM_PAGER3MAPTLB_ENTRIES 64
1265
1266/**
1267 * Ring-3 guest page mapping TLB.
1268 * @remarks used in ring-0 as well at the moment.
1269 */
1270typedef struct PGMPAGER3MAPTLB
1271{
1272 /** The TLB entries. */
1273 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1274} PGMPAGER3MAPTLB;
1275/** Pointer to the ring-3 guest page mapping TLB. */
1276typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1277
1278/**
1279 * Calculates the index of the TLB entry for the specified guest page.
1280 * @returns Physical TLB index.
1281 * @param GCPhys The guest physical address.
1282 */
1283#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1284
1285
1286/**
1287 * Mapping cache usage set entry.
1288 *
1289 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1290 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1291 * cache. If it's extended to include ring-3, well, then something will
1292 * have be changed here...
1293 */
1294typedef struct PGMMAPSETENTRY
1295{
1296 /** The mapping cache index. */
1297 uint16_t iPage;
1298 /** The number of references.
1299 * The max is UINT16_MAX - 1. */
1300 uint16_t cRefs;
1301 /** Pointer to the page. */
1302 RTR0PTR pvPage;
1303 /** The physical address for this entry. */
1304 RTHCPHYS HCPhys;
1305} PGMMAPSETENTRY;
1306/** Pointer to a mapping cache usage set entry. */
1307typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1308
1309/**
1310 * Mapping cache usage set.
1311 *
1312 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1313 * done during exits / traps. The set is
1314 */
1315typedef struct PGMMAPSET
1316{
1317 /** The number of occupied.
1318 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1319 * dynamic mappings. */
1320 uint32_t cEntries;
1321 /** The entries. */
1322 PGMMAPSETENTRY aEntries[32];
1323 /** HCPhys -> iEntry fast lookup table.
1324 * Use PGMMAPSET_HASH for hashing.
1325 * The entries may or may not be valid, check against cEntries. */
1326 uint8_t aiHashTable[64];
1327} PGMMAPSET;
1328/** Pointer to the mapping cache set. */
1329typedef PGMMAPSET *PPGMMAPSET;
1330
1331/** PGMMAPSET::cEntries value for a closed set. */
1332#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1333
1334/** Hash function for aiHashTable. */
1335#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 63)
1336
1337
1338/** @name Context neutrual page mapper TLB.
1339 *
1340 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1341 * code is writting in a kind of context neutrual way. Time will show whether
1342 * this actually makes sense or not...
1343 *
1344 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1345 * context ends up using a global mapping cache on some platforms
1346 * (darwin).
1347 *
1348 * @{ */
1349/** @typedef PPGMPAGEMAPTLB
1350 * The page mapper TLB pointer type for the current context. */
1351/** @typedef PPGMPAGEMAPTLB
1352 * The page mapper TLB entry pointer type for the current context. */
1353/** @typedef PPGMPAGEMAPTLB
1354 * The page mapper TLB entry pointer pointer type for the current context. */
1355/** @def PGM_PAGEMAPTLB_ENTRIES
1356 * The number of TLB entries in the page mapper TLB for the current context. */
1357/** @def PGM_PAGEMAPTLB_IDX
1358 * Calculate the TLB index for a guest physical address.
1359 * @returns The TLB index.
1360 * @param GCPhys The guest physical address. */
1361/** @typedef PPGMPAGEMAP
1362 * Pointer to a page mapper unit for current context. */
1363/** @typedef PPPGMPAGEMAP
1364 * Pointer to a page mapper unit pointer for current context. */
1365#ifdef IN_RC
1366// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1367// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1368// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1369# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1370# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1371 typedef void * PPGMPAGEMAP;
1372 typedef void ** PPPGMPAGEMAP;
1373//#elif IN_RING0
1374// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1375// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1376// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1377//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1378//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1379// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1380// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1381#else
1382 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1383 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1384 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1385# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1386# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1387 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1388 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1389#endif
1390/** @} */
1391
1392
1393/** @name PGM Pool Indexes.
1394 * Aka. the unique shadow page identifier.
1395 * @{ */
1396/** NIL page pool IDX. */
1397#define NIL_PGMPOOL_IDX 0
1398/** The first normal index. */
1399#define PGMPOOL_IDX_FIRST_SPECIAL 1
1400/** Page directory (32-bit root). */
1401#define PGMPOOL_IDX_PD 1
1402#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1403/** Page directory (32-bit root). */
1404#define PGMPOOL_IDX_PD 1
1405/** Page Directory Pointer Table (PAE root). */
1406#define PGMPOOL_IDX_PDPT 2
1407/** AMD64 CR3 level index.*/
1408#define PGMPOOL_IDX_AMD64_CR3 3
1409/** Nested paging root.*/
1410#define PGMPOOL_IDX_NESTED_ROOT 4
1411/** The first normal index. */
1412#define PGMPOOL_IDX_FIRST 5
1413#else
1414/** The extended PAE page directory (2048 entries, works as root currently). */
1415#define PGMPOOL_IDX_PAE_PD 2
1416/** PAE Page Directory Table 0. */
1417#define PGMPOOL_IDX_PAE_PD_0 3
1418/** PAE Page Directory Table 1. */
1419#define PGMPOOL_IDX_PAE_PD_1 4
1420/** PAE Page Directory Table 2. */
1421#define PGMPOOL_IDX_PAE_PD_2 5
1422/** PAE Page Directory Table 3. */
1423#define PGMPOOL_IDX_PAE_PD_3 6
1424/** Page Directory Pointer Table (PAE root, not currently used). */
1425#define PGMPOOL_IDX_PDPT 7
1426/** AMD64 CR3 level index.*/
1427#define PGMPOOL_IDX_AMD64_CR3 8
1428/** Nested paging root.*/
1429#define PGMPOOL_IDX_NESTED_ROOT 9
1430/** The first normal index. */
1431#define PGMPOOL_IDX_FIRST 10
1432#endif
1433/** The last valid index. (inclusive, 14 bits) */
1434#define PGMPOOL_IDX_LAST 0x3fff
1435/** @} */
1436
1437/** The NIL index for the parent chain. */
1438#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1439
1440/**
1441 * Node in the chain linking a shadowed page to it's parent (user).
1442 */
1443#pragma pack(1)
1444typedef struct PGMPOOLUSER
1445{
1446 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1447 uint16_t iNext;
1448 /** The user page index. */
1449 uint16_t iUser;
1450 /** Index into the user table. */
1451 uint32_t iUserTable;
1452} PGMPOOLUSER, *PPGMPOOLUSER;
1453typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1454#pragma pack()
1455
1456
1457/** The NIL index for the phys ext chain. */
1458#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1459
1460/**
1461 * Node in the chain of physical cross reference extents.
1462 */
1463#pragma pack(1)
1464typedef struct PGMPOOLPHYSEXT
1465{
1466 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1467 uint16_t iNext;
1468 /** The user page index. */
1469 uint16_t aidx[3];
1470} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1471typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1472#pragma pack()
1473
1474
1475/**
1476 * The kind of page that's being shadowed.
1477 */
1478typedef enum PGMPOOLKIND
1479{
1480 /** The virtual invalid 0 entry. */
1481 PGMPOOLKIND_INVALID = 0,
1482 /** The entry is free (=unused). */
1483 PGMPOOLKIND_FREE,
1484
1485 /** Shw: 32-bit page table; Gst: no paging */
1486 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1487 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1488 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1489 /** Shw: 32-bit page table; Gst: 4MB page. */
1490 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1491 /** Shw: PAE page table; Gst: no paging */
1492 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1493 /** Shw: PAE page table; Gst: 32-bit page table. */
1494 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1495 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1496 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1497 /** Shw: PAE page table; Gst: PAE page table. */
1498 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1499 /** Shw: PAE page table; Gst: 2MB page. */
1500 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1501
1502 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1503 PGMPOOLKIND_32BIT_PD,
1504 /** Shw: 32-bit page directory. Gst: real mode. */
1505 PGMPOOLKIND_32BIT_PD_PHYS_REAL,
1506 /** Shw: 32-bit page directory. Gst: protected mode without paging. */
1507 PGMPOOLKIND_32BIT_PD_PHYS_PROT,
1508 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1509 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1510 /** Shw: PAE page directory; Gst: PAE page directory. */
1511 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1512 /** Shw: PAE page directory; Gst: real mode. */
1513 PGMPOOLKIND_PAE_PD_PHYS_REAL,
1514 /** Shw: PAE page directory; Gst: protected mode without paging. */
1515 PGMPOOLKIND_PAE_PD_PHYS_PROT,
1516
1517 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1518 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1519 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1520 PGMPOOLKIND_PAE_PDPT,
1521
1522 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1523 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1524 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1525 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1526 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1527 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1528 /** Shw: 64-bit page directory table; Gst: no paging */
1529 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1530
1531 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1532 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1533
1534 /** Shw: EPT page directory pointer table; Gst: no paging */
1535 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1536 /** Shw: EPT page directory table; Gst: no paging */
1537 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1538 /** Shw: EPT page table; Gst: no paging */
1539 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1540
1541#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1542 /** Shw: Root 32-bit page directory. */
1543 PGMPOOLKIND_ROOT_32BIT_PD,
1544 /** Shw: Root PAE page directory */
1545 PGMPOOLKIND_ROOT_PAE_PD,
1546 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1547 PGMPOOLKIND_ROOT_PDPT,
1548#endif
1549 /** Shw: Root Nested paging table. */
1550 PGMPOOLKIND_ROOT_NESTED,
1551
1552 /** The last valid entry. */
1553 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1554} PGMPOOLKIND;
1555
1556
1557/**
1558 * The tracking data for a page in the pool.
1559 */
1560typedef struct PGMPOOLPAGE
1561{
1562 /** AVL node code with the (R3) physical address of this page. */
1563 AVLOHCPHYSNODECORE Core;
1564 /** Pointer to the R3 mapping of the page. */
1565#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1566 R3PTRTYPE(void *) pvPageR3;
1567#else
1568 R3R0PTRTYPE(void *) pvPageR3;
1569#endif
1570 /** The guest physical address. */
1571#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1572 uint32_t Alignment0;
1573#endif
1574 RTGCPHYS GCPhys;
1575 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1576 uint8_t enmKind;
1577 uint8_t bPadding;
1578 /** The index of this page. */
1579 uint16_t idx;
1580 /** The next entry in the list this page currently resides in.
1581 * It's either in the free list or in the GCPhys hash. */
1582 uint16_t iNext;
1583#ifdef PGMPOOL_WITH_USER_TRACKING
1584 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1585 uint16_t iUserHead;
1586 /** The number of present entries. */
1587 uint16_t cPresent;
1588 /** The first entry in the table which is present. */
1589 uint16_t iFirstPresent;
1590#endif
1591#ifdef PGMPOOL_WITH_MONITORING
1592 /** The number of modifications to the monitored page. */
1593 uint16_t cModifications;
1594 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1595 uint16_t iModifiedNext;
1596 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1597 uint16_t iModifiedPrev;
1598 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1599 uint16_t iMonitoredNext;
1600 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1601 uint16_t iMonitoredPrev;
1602#endif
1603#ifdef PGMPOOL_WITH_CACHE
1604 /** The next page in the age list. */
1605 uint16_t iAgeNext;
1606 /** The previous page in the age list. */
1607 uint16_t iAgePrev;
1608#endif /* PGMPOOL_WITH_CACHE */
1609 /** Used to indicate that the page is zeroed. */
1610 bool fZeroed;
1611 /** Used to indicate that a PT has non-global entries. */
1612 bool fSeenNonGlobal;
1613 /** Used to indicate that we're monitoring writes to the guest page. */
1614 bool fMonitored;
1615 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1616 * (All pages are in the age list.) */
1617 bool fCached;
1618 /** This is used by the R3 access handlers when invoked by an async thread.
1619 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1620 bool volatile fReusedFlushPending;
1621 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1622 * In these cases the access handler acts differently and will check
1623 * for mapping conflicts like the normal CR3 handler.
1624 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1625 * replaced by a list of pages which share access handler.
1626 */
1627 bool fCR3Mix;
1628} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1629
1630
1631#ifdef PGMPOOL_WITH_CACHE
1632/** The hash table size. */
1633# define PGMPOOL_HASH_SIZE 0x40
1634/** The hash function. */
1635# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1636#endif
1637
1638
1639/**
1640 * The shadow page pool instance data.
1641 *
1642 * It's all one big allocation made at init time, except for the
1643 * pages that is. The user nodes follows immediatly after the
1644 * page structures.
1645 */
1646typedef struct PGMPOOL
1647{
1648 /** The VM handle - R3 Ptr. */
1649 PVMR3 pVMR3;
1650 /** The VM handle - R0 Ptr. */
1651 PVMR0 pVMR0;
1652 /** The VM handle - RC Ptr. */
1653 PVMRC pVMRC;
1654 /** The max pool size. This includes the special IDs. */
1655 uint16_t cMaxPages;
1656 /** The current pool size. */
1657 uint16_t cCurPages;
1658 /** The head of the free page list. */
1659 uint16_t iFreeHead;
1660 /* Padding. */
1661 uint16_t u16Padding;
1662#ifdef PGMPOOL_WITH_USER_TRACKING
1663 /** Head of the chain of free user nodes. */
1664 uint16_t iUserFreeHead;
1665 /** The number of user nodes we've allocated. */
1666 uint16_t cMaxUsers;
1667 /** The number of present page table entries in the entire pool. */
1668 uint32_t cPresent;
1669 /** Pointer to the array of user nodes - RC pointer. */
1670 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1671 /** Pointer to the array of user nodes - R3 pointer. */
1672 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1673 /** Pointer to the array of user nodes - R0 pointer. */
1674 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1675#endif /* PGMPOOL_WITH_USER_TRACKING */
1676#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1677 /** Head of the chain of free phys ext nodes. */
1678 uint16_t iPhysExtFreeHead;
1679 /** The number of user nodes we've allocated. */
1680 uint16_t cMaxPhysExts;
1681 /** Pointer to the array of physical xref extent - RC pointer. */
1682 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1683 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1684 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1685 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1686 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1687#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1688#ifdef PGMPOOL_WITH_CACHE
1689 /** Hash table for GCPhys addresses. */
1690 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1691 /** The head of the age list. */
1692 uint16_t iAgeHead;
1693 /** The tail of the age list. */
1694 uint16_t iAgeTail;
1695 /** Set if the cache is enabled. */
1696 bool fCacheEnabled;
1697#endif /* PGMPOOL_WITH_CACHE */
1698#ifdef PGMPOOL_WITH_MONITORING
1699 /** Head of the list of modified pages. */
1700 uint16_t iModifiedHead;
1701 /** The current number of modified pages. */
1702 uint16_t cModifiedPages;
1703 /** Access handler, RC. */
1704 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1705 /** Access handler, R0. */
1706 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1707 /** Access handler, R3. */
1708 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1709 /** The access handler description (HC ptr). */
1710 R3PTRTYPE(const char *) pszAccessHandler;
1711#endif /* PGMPOOL_WITH_MONITORING */
1712 /** The number of pages currently in use. */
1713 uint16_t cUsedPages;
1714#ifdef VBOX_WITH_STATISTICS
1715 /** The high wather mark for cUsedPages. */
1716 uint16_t cUsedPagesHigh;
1717 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1718 /** Profiling pgmPoolAlloc(). */
1719 STAMPROFILEADV StatAlloc;
1720 /** Profiling pgmPoolClearAll(). */
1721 STAMPROFILE StatClearAll;
1722 /** Profiling pgmPoolFlushAllInt(). */
1723 STAMPROFILE StatFlushAllInt;
1724 /** Profiling pgmPoolFlushPage(). */
1725 STAMPROFILE StatFlushPage;
1726 /** Profiling pgmPoolFree(). */
1727 STAMPROFILE StatFree;
1728 /** Profiling time spent zeroing pages. */
1729 STAMPROFILE StatZeroPage;
1730# ifdef PGMPOOL_WITH_USER_TRACKING
1731 /** Profiling of pgmPoolTrackDeref. */
1732 STAMPROFILE StatTrackDeref;
1733 /** Profiling pgmTrackFlushGCPhysPT. */
1734 STAMPROFILE StatTrackFlushGCPhysPT;
1735 /** Profiling pgmTrackFlushGCPhysPTs. */
1736 STAMPROFILE StatTrackFlushGCPhysPTs;
1737 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1738 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1739 /** Number of times we've been out of user records. */
1740 STAMCOUNTER StatTrackFreeUpOneUser;
1741# endif
1742# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1743 /** Profiling deref activity related tracking GC physical pages. */
1744 STAMPROFILE StatTrackDerefGCPhys;
1745 /** Number of linear searches for a HCPhys in the ram ranges. */
1746 STAMCOUNTER StatTrackLinearRamSearches;
1747 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1748 STAMCOUNTER StamTrackPhysExtAllocFailures;
1749# endif
1750# ifdef PGMPOOL_WITH_MONITORING
1751 /** Profiling the RC/R0 access handler. */
1752 STAMPROFILE StatMonitorRZ;
1753 /** Times we've failed interpreting the instruction. */
1754 STAMCOUNTER StatMonitorRZEmulateInstr;
1755 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1756 STAMPROFILE StatMonitorRZFlushPage;
1757 /** Times we've detected fork(). */
1758 STAMCOUNTER StatMonitorRZFork;
1759 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1760 STAMPROFILE StatMonitorRZHandled;
1761 /** Times we've failed interpreting a patch code instruction. */
1762 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1763 /** Times we've failed interpreting a patch code instruction during flushing. */
1764 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1765 /** The number of times we've seen rep prefixes we can't handle. */
1766 STAMCOUNTER StatMonitorRZRepPrefix;
1767 /** Profiling the REP STOSD cases we've handled. */
1768 STAMPROFILE StatMonitorRZRepStosd;
1769
1770 /** Profiling the R3 access handler. */
1771 STAMPROFILE StatMonitorR3;
1772 /** Times we've failed interpreting the instruction. */
1773 STAMCOUNTER StatMonitorR3EmulateInstr;
1774 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1775 STAMPROFILE StatMonitorR3FlushPage;
1776 /** Times we've detected fork(). */
1777 STAMCOUNTER StatMonitorR3Fork;
1778 /** Profiling the R3 access we've handled (except REP STOSD). */
1779 STAMPROFILE StatMonitorR3Handled;
1780 /** The number of times we've seen rep prefixes we can't handle. */
1781 STAMCOUNTER StatMonitorR3RepPrefix;
1782 /** Profiling the REP STOSD cases we've handled. */
1783 STAMPROFILE StatMonitorR3RepStosd;
1784 /** The number of times we're called in an async thread an need to flush. */
1785 STAMCOUNTER StatMonitorR3Async;
1786 /** The high wather mark for cModifiedPages. */
1787 uint16_t cModifiedPagesHigh;
1788 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1789# endif
1790# ifdef PGMPOOL_WITH_CACHE
1791 /** The number of cache hits. */
1792 STAMCOUNTER StatCacheHits;
1793 /** The number of cache misses. */
1794 STAMCOUNTER StatCacheMisses;
1795 /** The number of times we've got a conflict of 'kind' in the cache. */
1796 STAMCOUNTER StatCacheKindMismatches;
1797 /** Number of times we've been out of pages. */
1798 STAMCOUNTER StatCacheFreeUpOne;
1799 /** The number of cacheable allocations. */
1800 STAMCOUNTER StatCacheCacheable;
1801 /** The number of uncacheable allocations. */
1802 STAMCOUNTER StatCacheUncacheable;
1803# endif
1804#elif HC_ARCH_BITS == 64
1805 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1806#endif
1807 /** The AVL tree for looking up a page by its HC physical address. */
1808 AVLOHCPHYSTREE HCPhysTree;
1809 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1810 /** Array of pages. (cMaxPages in length)
1811 * The Id is the index into thist array.
1812 */
1813 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1814} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1815
1816
1817/** @def PGMPOOL_PAGE_2_PTR
1818 * Maps a pool page pool into the current context.
1819 *
1820 * @returns VBox status code.
1821 * @param pVM The VM handle.
1822 * @param pPage The pool page.
1823 *
1824 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1825 * small page window employeed by that function. Be careful.
1826 * @remark There is no need to assert on the result.
1827 */
1828#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1829# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1830#else
1831 DECLINLINE(R3R0PTRTYPE(void *)) PGMPOOL_PAGE_2_PTR(PVM pVM, PPGMPOOLPAGE pPage)
1832 {
1833 Assert(pPage->pvPageR3);
1834 return pPage->pvPageR3;
1835 }
1836#endif
1837
1838
1839/**
1840 * Trees are using self relative offsets as pointers.
1841 * So, all its data, including the root pointer, must be in the heap for HC and GC
1842 * to have the same layout.
1843 */
1844typedef struct PGMTREES
1845{
1846 /** Physical access handlers (AVL range+offsetptr tree). */
1847 AVLROGCPHYSTREE PhysHandlers;
1848 /** Virtual access handlers (AVL range + GC ptr tree). */
1849 AVLROGCPTRTREE VirtHandlers;
1850 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1851 AVLROGCPHYSTREE PhysToVirtHandlers;
1852 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1853 AVLROGCPTRTREE HyperVirtHandlers;
1854} PGMTREES;
1855/** Pointer to PGM trees. */
1856typedef PGMTREES *PPGMTREES;
1857
1858
1859/** @name Paging mode macros
1860 * @{ */
1861#ifdef IN_RC
1862# define PGM_CTX(a,b) a##RC##b
1863# define PGM_CTX_STR(a,b) a "GC" b
1864# define PGM_CTX_DECL(type) VMMRCDECL(type)
1865#else
1866# ifdef IN_RING3
1867# define PGM_CTX(a,b) a##R3##b
1868# define PGM_CTX_STR(a,b) a "R3" b
1869# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1870# else
1871# define PGM_CTX(a,b) a##R0##b
1872# define PGM_CTX_STR(a,b) a "R0" b
1873# define PGM_CTX_DECL(type) VMMDECL(type)
1874# endif
1875#endif
1876
1877#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1878#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1879#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1880#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1881#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1882#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1883#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1884#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1885#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1886#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1887#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1888#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1889#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1890#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1891#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1892#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1893#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1894
1895#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1896#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1897#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1898#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1899#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1900#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1901#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1902#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1903#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1904#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1905#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1906#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1907#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1908#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1909#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1910#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1911#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1912
1913/* Shw_Gst */
1914#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1915#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1916#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1917#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1918#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1919#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1920#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1921#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1922#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1923#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1924#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1925#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1926#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1927#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1928#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1929#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1930#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1931#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1932#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1933
1934#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1935#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1936#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1937#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1938#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1939#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1940#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1941#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1942#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1943#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1944#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1945#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1946#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1947#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1948#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1949#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1950#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1951#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1952#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1953#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1954#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1955#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1956#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1957#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1958#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1959#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1960#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1961#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1962#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1963#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1964#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1965#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1966#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1967#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1968#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1969#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1970#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1971
1972#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1973#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1974/** @} */
1975
1976/**
1977 * Data for each paging mode.
1978 */
1979typedef struct PGMMODEDATA
1980{
1981 /** The guest mode type. */
1982 uint32_t uGstType;
1983 /** The shadow mode type. */
1984 uint32_t uShwType;
1985
1986 /** @name Function pointers for Shadow paging.
1987 * @{
1988 */
1989 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
1990 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1991 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1992 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1993
1994 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1995 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1996
1997 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1998 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1999 /** @} */
2000
2001 /** @name Function pointers for Guest paging.
2002 * @{
2003 */
2004 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2005 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2006 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2007 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2008 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2009#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2010 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2011 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2012#endif
2013 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2014 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2015#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2016 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2017 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2018 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2019 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2020#endif
2021 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2022 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2023 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2024#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2025 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2026 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2027#endif
2028 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2029 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2030#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2031 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2032 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2033#endif
2034 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2035 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2036 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2037#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2038 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2039 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2040#endif
2041 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2042 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2043#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2044 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2045 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2046#endif
2047 /** @} */
2048
2049 /** @name Function pointers for Both Shadow and Guest paging.
2050 * @{
2051 */
2052 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2053 /* no pfnR3BthTrap0eHandler */
2054 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2055 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2056 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2057 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2058 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2059#ifdef VBOX_STRICT
2060 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2061#endif
2062
2063 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2064 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2065 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2066 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2067 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2068 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2069#ifdef VBOX_STRICT
2070 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2071#endif
2072
2073 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2074 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2075 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2076 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2077 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2078 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2079#ifdef VBOX_STRICT
2080 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2081#endif
2082 /** @} */
2083} PGMMODEDATA, *PPGMMODEDATA;
2084
2085
2086
2087/**
2088 * Converts a PGM pointer into a VM pointer.
2089 * @returns Pointer to the VM structure the PGM is part of.
2090 * @param pPGM Pointer to PGM instance data.
2091 */
2092#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2093
2094/**
2095 * PGM Data (part of VM)
2096 */
2097typedef struct PGM
2098{
2099 /** Offset to the VM structure. */
2100 RTINT offVM;
2101 /** Offset of the PGMCPU structure relative to VMCPU. */
2102 int32_t offVCpu;
2103 /** Alignment padding. */
2104 int32_t i32Alignment;
2105
2106 /*
2107 * This will be redefined at least two more times before we're done, I'm sure.
2108 * The current code is only to get on with the coding.
2109 * - 2004-06-10: initial version, bird.
2110 * - 2004-07-02: 1st time, bird.
2111 * - 2004-10-18: 2nd time, bird.
2112 * - 2005-07-xx: 3rd time, bird.
2113 */
2114
2115 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2116 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2117 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2118 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2119
2120 /** The host paging mode. (This is what SUPLib reports.) */
2121 SUPPAGINGMODE enmHostMode;
2122 /** The shadow paging mode. */
2123 PGMMODE enmShadowMode;
2124 /** The guest paging mode. */
2125 PGMMODE enmGuestMode;
2126
2127 /** The current physical address representing in the guest CR3 register. */
2128 RTGCPHYS GCPhysCR3;
2129 /** Pointer to the 5 page CR3 content mapping.
2130 * The first page is always the CR3 (in some form) while the 4 other pages
2131 * are used of the PDs in PAE mode. */
2132 RTGCPTR GCPtrCR3Mapping;
2133#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2134 uint32_t u32Alignment;
2135#endif
2136 /** The physical address of the currently monitored guest CR3 page.
2137 * When this value is NIL_RTGCPHYS no page is being monitored. */
2138 RTGCPHYS GCPhysGstCR3Monitored;
2139
2140 /** @name 32-bit Guest Paging.
2141 * @{ */
2142 /** The guest's page directory, R3 pointer. */
2143 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2144#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2145 /** The guest's page directory, R0 pointer. */
2146 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2147#endif
2148 /** The guest's page directory, static RC mapping. */
2149 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2150 /** @} */
2151
2152 /** @name PAE Guest Paging.
2153 * @{ */
2154 /** The guest's page directory pointer table, static RC mapping. */
2155 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2156 /** The guest's page directory pointer table, R3 pointer. */
2157 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2158#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2159 /** The guest's page directory pointer table, R0 pointer. */
2160 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2161#endif
2162
2163 /** The guest's page directories, R3 pointers.
2164 * These are individual pointers and don't have to be adjecent.
2165 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2166 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2167 /** The guest's page directories, R0 pointers.
2168 * Same restrictions as apGstPaePDsR3. */
2169#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2170 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2171#endif
2172 /** The guest's page directories, static GC mapping.
2173 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2174 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2175 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2176 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2177 RTGCPHYS aGCPhysGstPaePDs[4];
2178 /** The physical addresses of the monitored guest page directories (PAE). */
2179 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2180 /** @} */
2181
2182 /** @name AMD64 Guest Paging.
2183 * @{ */
2184 /** The guest's page directory pointer table, R3 pointer. */
2185 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2186#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2187 /** The guest's page directory pointer table, R0 pointer. */
2188 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2189#endif
2190 /** @} */
2191
2192 /** @name 32-bit Shadow Paging
2193 * @{ */
2194#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2195 /** The Physical Address (HC) of the current active shadow CR3. */
2196 RTHCPHYS HCPhysShwCR3;
2197 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2198 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2199 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2200 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2201 /** Pointer to the page of the current active CR3 - RC Ptr. */
2202 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2203# if HC_ARCH_BITS == 64
2204 RTRCPTR alignment6; /**< structure size alignment. */
2205# endif
2206#else
2207 /** The 32-Bit PD - R3 Ptr. */
2208 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2209 /** The 32-Bit PD - R0 Ptr. */
2210 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2211 /** The 32-Bit PD - RC Ptr. */
2212 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2213# if HC_ARCH_BITS == 64
2214 uint32_t u32Padding1; /**< alignment padding. */
2215# endif
2216 /** The Physical Address (HC) of the 32-Bit PD. */
2217 RTHCPHYS HCPhysShw32BitPD;
2218 /** @} */
2219
2220 /** @name PAE Shadow Paging
2221 * @{ */
2222 /** The four PDs for the low 4GB - R3 Ptr.
2223 * Even though these are 4 pointers, what they point at is a single table.
2224 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2225 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2226# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2227 /** The four PDs for the low 4GB - R0 Ptr.
2228 * Same kind of mapping as apHCPaePDs. */
2229 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2230# endif
2231 /** The four PDs for the low 4GB - RC Ptr.
2232 * Same kind of mapping as apHCPaePDs. */
2233 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2234 /** The Physical Address (HC) of the four PDs for the low 4GB.
2235 * These are *NOT* 4 contiguous pages. */
2236 RTHCPHYS aHCPhysPaePDs[4];
2237 /** The Physical Address (HC) of the PAE PDPT. */
2238 RTHCPHYS HCPhysShwPaePdpt;
2239 /** The PAE PDPT - R3 Ptr. */
2240 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2241 /** The PAE PDPT - R0 Ptr. */
2242 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2243 /** The PAE PDPT - RC Ptr. */
2244 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2245 /** @} */
2246# if HC_ARCH_BITS == 64
2247 RTRCPTR alignment5; /**< structure size alignment. */
2248# endif
2249
2250 /** @name AMD64 Shadow Paging
2251 * Extends PAE Paging.
2252 * @{ */
2253 /** The Page Map Level 4 table - R3 Ptr. */
2254 R3PTRTYPE(PX86PML4) pShwPaePml4R3;
2255# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2256 /** The Page Map Level 4 table - R0 Ptr. */
2257 R0PTRTYPE(PX86PML4) pShwPaePml4R0;
2258# endif
2259 /** The Physical Address (HC) of the Page Map Level 4 table. */
2260 RTHCPHYS HCPhysShwPaePml4;
2261 /** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
2262 R3PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R3;
2263 /** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
2264 R0PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R0;
2265 /** @}*/
2266
2267 /** @name Nested Shadow Paging
2268 * @{ */
2269 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2270 RTR3PTR pShwNestedRootR3;
2271# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2272 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2273 RTR0PTR pShwNestedRootR0;
2274# endif
2275 /** The Physical Address (HC) of the nested paging root. */
2276 RTHCPHYS HCPhysShwNestedRoot;
2277#endif
2278 /** @} */
2279
2280 /** @name Function pointers for Shadow paging.
2281 * @{
2282 */
2283 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2284 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2285 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2286 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2287
2288 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2289 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2290
2291 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2292 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2293
2294 /** @} */
2295
2296 /** @name Function pointers for Guest paging.
2297 * @{
2298 */
2299 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2300 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2301 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2302 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2303 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2304#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2305 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2306 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2307#endif
2308 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2309 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2310#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2311 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2312 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2313 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2314 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2315#endif
2316 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2317 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2318 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2319#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2320 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2321 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2322#endif
2323 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2324 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2325#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2326 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2327 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2328#endif
2329#if HC_ARCH_BITS == 64
2330 RTRCPTR alignment3; /**< structure size alignment. */
2331#endif
2332
2333 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2334 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2335 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2336#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2337 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2338 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2339#endif
2340 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2341 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2342#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2343 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2344 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2345#endif
2346 /** @} */
2347
2348 /** @name Function pointers for Both Shadow and Guest paging.
2349 * @{
2350 */
2351 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2352 /* no pfnR3BthTrap0eHandler */
2353 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2354 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2355 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2356 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2357 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2358 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2359
2360 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2361 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2362 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2363 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2364 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2365 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2366 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2367
2368 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2369 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2370 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2371 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2372 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2373 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2374 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2375#if HC_ARCH_BITS == 64
2376 RTRCPTR alignment2; /**< structure size alignment. */
2377#endif
2378 /** @} */
2379
2380 /** Pointer to SHW+GST mode data (function pointers).
2381 * The index into this table is made up from */
2382 R3PTRTYPE(PPGMMODEDATA) paModeData;
2383
2384 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2385 * This is sorted by physical address and contains no overlapping ranges. */
2386 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2387 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2388 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2389 /** RC pointer corresponding to PGM::pRamRangesR3. */
2390 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2391 /** The configured RAM size. */
2392 RTUINT cbRamSize;
2393
2394 /** Pointer to the list of ROM ranges - for R3.
2395 * This is sorted by physical address and contains no overlapping ranges. */
2396 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2397 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2398 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2399 /** RC pointer corresponding to PGM::pRomRangesR3. */
2400 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2401 /** Alignment padding. */
2402 RTRCPTR GCPtrPadding2;
2403
2404 /** Pointer to the list of MMIO2 ranges - for R3.
2405 * Registration order. */
2406 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2407
2408 /** PGM offset based trees - R3 Ptr. */
2409 R3PTRTYPE(PPGMTREES) pTreesR3;
2410 /** PGM offset based trees - R0 Ptr. */
2411 R0PTRTYPE(PPGMTREES) pTreesR0;
2412 /** PGM offset based trees - RC Ptr. */
2413 RCPTRTYPE(PPGMTREES) pTreesRC;
2414
2415 /** Linked list of GC mappings - for RC.
2416 * The list is sorted ascending on address.
2417 */
2418 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2419 /** Linked list of GC mappings - for HC.
2420 * The list is sorted ascending on address.
2421 */
2422 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2423 /** Linked list of GC mappings - for R0.
2424 * The list is sorted ascending on address.
2425 */
2426 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2427
2428 /** If set no conflict checks are required. (boolean) */
2429 bool fMappingsFixed;
2430 /** If set, then no mappings are put into the shadow page table. (boolean) */
2431 bool fDisableMappings;
2432 /** Size of fixed mapping */
2433 uint32_t cbMappingFixed;
2434 /** Base address (GC) of fixed mapping */
2435 RTGCPTR GCPtrMappingFixed;
2436#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2437 uint32_t u32Padding0; /**< alignment padding. */
2438#endif
2439
2440
2441 /** @name Intermediate Context
2442 * @{ */
2443 /** Pointer to the intermediate page directory - Normal. */
2444 R3PTRTYPE(PX86PD) pInterPD;
2445 /** Pointer to the intermedate page tables - Normal.
2446 * There are two page tables, one for the identity mapping and one for
2447 * the host context mapping (of the core code). */
2448 R3PTRTYPE(PX86PT) apInterPTs[2];
2449 /** Pointer to the intermedate page tables - PAE. */
2450 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2451 /** Pointer to the intermedate page directory - PAE. */
2452 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2453 /** Pointer to the intermedate page directory - PAE. */
2454 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2455 /** Pointer to the intermedate page-map level 4 - AMD64. */
2456 R3PTRTYPE(PX86PML4) pInterPaePML4;
2457 /** Pointer to the intermedate page directory - AMD64. */
2458 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2459 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2460 RTHCPHYS HCPhysInterPD;
2461 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2462 RTHCPHYS HCPhysInterPaePDPT;
2463 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2464 RTHCPHYS HCPhysInterPaePML4;
2465 /** @} */
2466
2467 /** Base address of the dynamic page mapping area.
2468 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2469 */
2470 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2471 /** The index of the last entry used in the dynamic page mapping area. */
2472 RTUINT iDynPageMapLast;
2473 /** Cache containing the last entries in the dynamic page mapping area.
2474 * The cache size is covering half of the mapping area. */
2475 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2476
2477 /** The address of the ring-0 mapping cache if we're making use of it. */
2478 RTR0PTR pvR0DynMapUsed;
2479#if HC_ARCH_BITS == 32
2480 RTR0PTR R0PtrPadding0; /**< Alignment. */
2481#endif
2482
2483
2484 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2485 RTGCPHYS GCPhys4MBPSEMask;
2486
2487 /** A20 gate mask.
2488 * Our current approach to A20 emulation is to let REM do it and don't bother
2489 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2490 * But whould need arrise, we'll subject physical addresses to this mask. */
2491 RTGCPHYS GCPhysA20Mask;
2492 /** A20 gate state - boolean! */
2493 RTUINT fA20Enabled;
2494
2495 /** What needs syncing (PGM_SYNC_*).
2496 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2497 * PGMFlushTLB, and PGMR3Load. */
2498 RTUINT fSyncFlags;
2499
2500 /** PGM critical section.
2501 * This protects the physical & virtual access handlers, ram ranges,
2502 * and the page flag updating (some of it anyway).
2503 */
2504 PDMCRITSECT CritSect;
2505
2506 /** Shadow Page Pool - R3 Ptr. */
2507 R3PTRTYPE(PPGMPOOL) pPoolR3;
2508 /** Shadow Page Pool - R0 Ptr. */
2509 R0PTRTYPE(PPGMPOOL) pPoolR0;
2510 /** Shadow Page Pool - RC Ptr. */
2511 RCPTRTYPE(PPGMPOOL) pPoolRC;
2512
2513 /** We're not in a state which permits writes to guest memory.
2514 * (Only used in strict builds.) */
2515 bool fNoMorePhysWrites;
2516
2517 /** Flush the cache on the next access. */
2518 bool fPhysCacheFlushPending;
2519/** @todo r=bird: Fix member names!*/
2520 /** PGMPhysRead cache */
2521 PGMPHYSCACHE pgmphysreadcache;
2522 /** PGMPhysWrite cache */
2523 PGMPHYSCACHE pgmphyswritecache;
2524
2525 /**
2526 * Data associated with managing the ring-3 mappings of the allocation chunks.
2527 */
2528 struct
2529 {
2530 /** The chunk tree, ordered by chunk id. */
2531#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2532 R3PTRTYPE(PAVLU32NODECORE) pTree;
2533#else
2534 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2535#endif
2536 /** The chunk mapping TLB. */
2537 PGMCHUNKR3MAPTLB Tlb;
2538 /** The number of mapped chunks. */
2539 uint32_t c;
2540 /** The maximum number of mapped chunks.
2541 * @cfgm PGM/MaxRing3Chunks */
2542 uint32_t cMax;
2543 /** The chunk age tree, ordered by ageing sequence number. */
2544 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2545 /** The current time. */
2546 uint32_t iNow;
2547 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2548 uint32_t AgeingCountdown;
2549 } ChunkR3Map;
2550
2551 /**
2552 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2553 */
2554 PGMPAGER3MAPTLB PhysTlbHC;
2555
2556 /** @name The zero page.
2557 * @{ */
2558 /** The host physical address of the zero page. */
2559 RTHCPHYS HCPhysZeroPg;
2560 /** The ring-3 mapping of the zero page. */
2561 RTR3PTR pvZeroPgR3;
2562 /** The ring-0 mapping of the zero page. */
2563 RTR0PTR pvZeroPgR0;
2564 /** The GC mapping of the zero page. */
2565 RTGCPTR pvZeroPgGC;
2566#if GC_ARCH_BITS != 32
2567 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2568#endif
2569 /** @}*/
2570
2571 /** The number of handy pages. */
2572 uint32_t cHandyPages;
2573 /**
2574 * Array of handy pages.
2575 *
2576 * This array is used in a two way communication between pgmPhysAllocPage
2577 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2578 * an intermediary.
2579 *
2580 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2581 * (The current size of 32 pages, means 128 KB of handy memory.)
2582 */
2583 GMMPAGEDESC aHandyPages[32];
2584
2585 /** @name Release Statistics
2586 * @{ */
2587 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2588 uint32_t cPrivatePages; /**< The number of private pages. */
2589 uint32_t cSharedPages; /**< The number of shared pages. */
2590 uint32_t cZeroPages; /**< The number of zero backed pages. */
2591 /** The number of times the guest has switched mode since last reset or statistics reset. */
2592 STAMCOUNTER cGuestModeChanges;
2593 /** @} */
2594
2595#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2596 /** RC: Which statistic this \#PF should be attributed to. */
2597 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2598 RTRCPTR padding0;
2599 /** R0: Which statistic this \#PF should be attributed to. */
2600 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2601 RTR0PTR padding1;
2602
2603 /* Common */
2604# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2605 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2606 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2607 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2608 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2609 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2610 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2611# endif
2612 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2613 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2614
2615 /* R3 only: */
2616 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2617 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2618 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2619 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2620 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2621 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2622
2623 /* R0 only: */
2624 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2625 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2626 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2627 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2628 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2629 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2630 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2631 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2632 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2633 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2634 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2635 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2636 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2637 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2638 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2639 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2640 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2641 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2642 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2643 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2644 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2645 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2646
2647 /* RC only: */
2648 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2649 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2650 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2651 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2652
2653 /* RZ only: */
2654 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2655 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2656 STAMPROFILE StatRZTrap0eTimeSyncPT;
2657 STAMPROFILE StatRZTrap0eTimeMapping;
2658 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2659 STAMPROFILE StatRZTrap0eTimeHandlers;
2660 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2661 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2662 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2663 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2664 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2665 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2666 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2667 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2668 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2669 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2670 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2671 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2672 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2673 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2674 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2675 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2676 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2677 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2678 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2679 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2680 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2681 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2682 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2683 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2684 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2685 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2686 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2687 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2688 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2689 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2690 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2691 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2692 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2693 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2694 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2695 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2696 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2697 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2698 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2699 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2700 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2701 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2702 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2703
2704 /* HC - R3 and (maybe) R0: */
2705
2706 /* RZ & R3: */
2707 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2708 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2709 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2710 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2711 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2712 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2713 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2714 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2715 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2716 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2717 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2718 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2719 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2720 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2721 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2722 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2723 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2724 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2725 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2726 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2727 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2728 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2729 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2730 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2731 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2732 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2733 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2734 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2735 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2736 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2737 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2738 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2739 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2740 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2741 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2742 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2743 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2744 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2745 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2746 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2747 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2748 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2749 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2750 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2751 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2752 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2753 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2754/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2755 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2756 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2757 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2758 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2759 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2760 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2761
2762 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2763 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2764 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2765 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2766 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2767 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2768 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2769 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2770 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2771 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2772 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2773 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2774 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2775 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2776 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2777 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2778 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2779 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2780 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2781 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2782 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2783 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2784 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2785 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2786 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2787 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2788 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2789 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2790 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2791 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2792 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2793 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2794 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2795 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2796 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2797 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2798 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2799 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2800 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2801 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2802 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2803 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2804 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2805 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2806 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2807 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2808 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2809/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2810 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2811 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2812 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2813 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2814 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2815 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2816#endif /* VBOX_WITH_STATISTICS */
2817} PGM;
2818/** Pointer to the PGM instance data. */
2819typedef PGM *PPGM;
2820
2821
2822/**
2823 * PGMCPU Data (part of VMCPU).
2824 */
2825typedef struct PGMCPU
2826{
2827 /** Offset to the VMCPU structure. */
2828 RTINT offVMCPU;
2829 /** Automatically tracked physical memory mapping set.
2830 * Ring-0 and strict raw-mode builds. */
2831 PGMMAPSET AutoSet;
2832} PGMCPU;
2833/** Pointer to the per-cpu PGM data. */
2834typedef PGMCPU *PPGMCPU;
2835
2836
2837/** @name PGM::fSyncFlags Flags
2838 * @{
2839 */
2840/** Updates the virtual access handler state bit in PGMPAGE. */
2841#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2842/** Always sync CR3. */
2843#define PGM_SYNC_ALWAYS RT_BIT(1)
2844/** Check monitoring on next CR3 (re)load and invalidate page. */
2845#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2846/** Clear the page pool (a light weight flush). */
2847#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2848/** @} */
2849
2850
2851__BEGIN_DECLS
2852
2853int pgmLock(PVM pVM);
2854void pgmUnlock(PVM pVM);
2855
2856VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2857VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2858
2859int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2860int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2861PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2862void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2863DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2864
2865void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2866int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2867DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2868#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2869void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2870#else
2871# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2872#endif
2873DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2874
2875
2876void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2877int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2878int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2879int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2880#ifdef IN_RING3
2881int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2882int pgmR3PhysRamReset(PVM pVM);
2883int pgmR3PhysRomReset(PVM pVM);
2884# ifndef VBOX_WITH_NEW_PHYS_CODE
2885int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2886# endif
2887
2888int pgmR3PoolInit(PVM pVM);
2889void pgmR3PoolRelocate(PVM pVM);
2890void pgmR3PoolReset(PVM pVM);
2891
2892#endif /* IN_RING3 */
2893#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2894int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2895#endif
2896#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2897void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2898#endif
2899int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2900PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2901void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2902void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2903int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2904void pgmPoolFlushAll(PVM pVM);
2905void pgmPoolClearAll(PVM pVM);
2906int pgmPoolSyncCR3(PVM pVM);
2907void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2908void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2909int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2910PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2911void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2912void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2913uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2914void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2915#ifdef PGMPOOL_WITH_MONITORING
2916# ifdef IN_RING3
2917void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2918# else
2919void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2920# endif
2921int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2922void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2923void pgmPoolMonitorModifiedClearAll(PVM pVM);
2924int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2925int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2926#endif
2927
2928__END_DECLS
2929
2930
2931/**
2932 * Gets the PGMRAMRANGE structure for a guest page.
2933 *
2934 * @returns Pointer to the RAM range on success.
2935 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2936 *
2937 * @param pPGM PGM handle.
2938 * @param GCPhys The GC physical address.
2939 */
2940DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2941{
2942 /*
2943 * Optimize for the first range.
2944 */
2945 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2946 RTGCPHYS off = GCPhys - pRam->GCPhys;
2947 if (RT_UNLIKELY(off >= pRam->cb))
2948 {
2949 do
2950 {
2951 pRam = pRam->CTX_SUFF(pNext);
2952 if (RT_UNLIKELY(!pRam))
2953 break;
2954 off = GCPhys - pRam->GCPhys;
2955 } while (off >= pRam->cb);
2956 }
2957 return pRam;
2958}
2959
2960
2961/**
2962 * Gets the PGMPAGE structure for a guest page.
2963 *
2964 * @returns Pointer to the page on success.
2965 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2966 *
2967 * @param pPGM PGM handle.
2968 * @param GCPhys The GC physical address.
2969 */
2970DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2971{
2972 /*
2973 * Optimize for the first range.
2974 */
2975 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2976 RTGCPHYS off = GCPhys - pRam->GCPhys;
2977 if (RT_UNLIKELY(off >= pRam->cb))
2978 {
2979 do
2980 {
2981 pRam = pRam->CTX_SUFF(pNext);
2982 if (RT_UNLIKELY(!pRam))
2983 return NULL;
2984 off = GCPhys - pRam->GCPhys;
2985 } while (off >= pRam->cb);
2986 }
2987 return &pRam->aPages[off >> PAGE_SHIFT];
2988}
2989
2990
2991/**
2992 * Gets the PGMPAGE structure for a guest page.
2993 *
2994 * Old Phys code: Will make sure the page is present.
2995 *
2996 * @returns VBox status code.
2997 * @retval VINF_SUCCESS and a valid *ppPage on success.
2998 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2999 *
3000 * @param pPGM PGM handle.
3001 * @param GCPhys The GC physical address.
3002 * @param ppPage Where to store the page poitner on success.
3003 */
3004DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3005{
3006 /*
3007 * Optimize for the first range.
3008 */
3009 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3010 RTGCPHYS off = GCPhys - pRam->GCPhys;
3011 if (RT_UNLIKELY(off >= pRam->cb))
3012 {
3013 do
3014 {
3015 pRam = pRam->CTX_SUFF(pNext);
3016 if (RT_UNLIKELY(!pRam))
3017 {
3018 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3019 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3020 }
3021 off = GCPhys - pRam->GCPhys;
3022 } while (off >= pRam->cb);
3023 }
3024 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3025#ifndef VBOX_WITH_NEW_PHYS_CODE
3026
3027 /*
3028 * Make sure it's present.
3029 */
3030 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3031 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3032 {
3033#ifdef IN_RING3
3034 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3035#else
3036 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3037#endif
3038 if (RT_FAILURE(rc))
3039 {
3040 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3041 return rc;
3042 }
3043 Assert(rc == VINF_SUCCESS);
3044 }
3045#endif
3046 return VINF_SUCCESS;
3047}
3048
3049
3050
3051
3052/**
3053 * Gets the PGMPAGE structure for a guest page.
3054 *
3055 * Old Phys code: Will make sure the page is present.
3056 *
3057 * @returns VBox status code.
3058 * @retval VINF_SUCCESS and a valid *ppPage on success.
3059 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3060 *
3061 * @param pPGM PGM handle.
3062 * @param GCPhys The GC physical address.
3063 * @param ppPage Where to store the page poitner on success.
3064 * @param ppRamHint Where to read and store the ram list hint.
3065 * The caller initializes this to NULL before the call.
3066 */
3067DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3068{
3069 RTGCPHYS off;
3070 PPGMRAMRANGE pRam = *ppRamHint;
3071 if ( !pRam
3072 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3073 {
3074 pRam = pPGM->CTX_SUFF(pRamRanges);
3075 off = GCPhys - pRam->GCPhys;
3076 if (RT_UNLIKELY(off >= pRam->cb))
3077 {
3078 do
3079 {
3080 pRam = pRam->CTX_SUFF(pNext);
3081 if (RT_UNLIKELY(!pRam))
3082 {
3083 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3084 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3085 }
3086 off = GCPhys - pRam->GCPhys;
3087 } while (off >= pRam->cb);
3088 }
3089 *ppRamHint = pRam;
3090 }
3091 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3092#ifndef VBOX_WITH_NEW_PHYS_CODE
3093
3094 /*
3095 * Make sure it's present.
3096 */
3097 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3098 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3099 {
3100#ifdef IN_RING3
3101 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3102#else
3103 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3104#endif
3105 if (RT_FAILURE(rc))
3106 {
3107 *ppPage = NULL; /* Shut up annoying smart ass. */
3108 return rc;
3109 }
3110 Assert(rc == VINF_SUCCESS);
3111 }
3112#endif
3113 return VINF_SUCCESS;
3114}
3115
3116
3117/**
3118 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3119 *
3120 * @returns Pointer to the page on success.
3121 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3122 *
3123 * @param pPGM PGM handle.
3124 * @param GCPhys The GC physical address.
3125 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3126 */
3127DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3128{
3129 /*
3130 * Optimize for the first range.
3131 */
3132 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3133 RTGCPHYS off = GCPhys - pRam->GCPhys;
3134 if (RT_UNLIKELY(off >= pRam->cb))
3135 {
3136 do
3137 {
3138 pRam = pRam->CTX_SUFF(pNext);
3139 if (RT_UNLIKELY(!pRam))
3140 return NULL;
3141 off = GCPhys - pRam->GCPhys;
3142 } while (off >= pRam->cb);
3143 }
3144 *ppRam = pRam;
3145 return &pRam->aPages[off >> PAGE_SHIFT];
3146}
3147
3148
3149/**
3150 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3151 *
3152 * @returns Pointer to the page on success.
3153 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3154 *
3155 * @param pPGM PGM handle.
3156 * @param GCPhys The GC physical address.
3157 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3158 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3159 */
3160DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3161{
3162 /*
3163 * Optimize for the first range.
3164 */
3165 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3166 RTGCPHYS off = GCPhys - pRam->GCPhys;
3167 if (RT_UNLIKELY(off >= pRam->cb))
3168 {
3169 do
3170 {
3171 pRam = pRam->CTX_SUFF(pNext);
3172 if (RT_UNLIKELY(!pRam))
3173 {
3174 *ppRam = NULL; /* Shut up silly GCC warnings. */
3175 *ppPage = NULL; /* ditto */
3176 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3177 }
3178 off = GCPhys - pRam->GCPhys;
3179 } while (off >= pRam->cb);
3180 }
3181 *ppRam = pRam;
3182 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3183#ifndef VBOX_WITH_NEW_PHYS_CODE
3184
3185 /*
3186 * Make sure it's present.
3187 */
3188 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3189 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3190 {
3191#ifdef IN_RING3
3192 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3193#else
3194 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3195#endif
3196 if (RT_FAILURE(rc))
3197 {
3198 *ppPage = NULL; /* Shut up silly GCC warnings. */
3199 *ppPage = NULL; /* ditto */
3200 return rc;
3201 }
3202 Assert(rc == VINF_SUCCESS);
3203
3204 }
3205#endif
3206 return VINF_SUCCESS;
3207}
3208
3209
3210/**
3211 * Convert GC Phys to HC Phys.
3212 *
3213 * @returns VBox status.
3214 * @param pPGM PGM handle.
3215 * @param GCPhys The GC physical address.
3216 * @param pHCPhys Where to store the corresponding HC physical address.
3217 *
3218 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3219 * Avoid when writing new code!
3220 */
3221DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3222{
3223 PPGMPAGE pPage;
3224 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3225 if (RT_FAILURE(rc))
3226 return rc;
3227 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3228 return VINF_SUCCESS;
3229}
3230
3231#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3232
3233/**
3234 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3235 * optimizes access to pages already in the set.
3236 *
3237 * @returns See pgmR0DynMapHCPageCommon.
3238 * @param pPGM Pointer to the PVM instance data.
3239 * @param HCPhys The physical address of the page.
3240 * @param ppv Where to store the mapping address.
3241 */
3242DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3243{
3244 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3245 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3246 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3247 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3248 int rc;
3249
3250 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3251 unsigned iEntry = pSet->aiHashTable[iHash];
3252 if ( iEntry < pSet->cEntries
3253 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3254 {
3255 *ppv = pSet->aEntries[iEntry].pvPage;
3256 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3257 rc = VINF_SUCCESS;
3258 }
3259 else
3260 {
3261 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3262 rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3263 }
3264
3265 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3266 return rc;
3267}
3268
3269
3270/**
3271 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3272 * access to pages already in the set.
3273 *
3274 * @returns See pgmR0DynMapHCPageCommon.
3275 * @param pPGM Pointer to the PVM instance data.
3276 * @param HCPhys The physical address of the page.
3277 * @param ppv Where to store the mapping address.
3278 */
3279DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3280{
3281 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3282 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3283
3284 /*
3285 * Get the ram range.
3286 */
3287 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3288 RTGCPHYS off = GCPhys - pRam->GCPhys;
3289 if (RT_UNLIKELY(off >= pRam->cb
3290 /** @todo || page state stuff */))
3291 {
3292 /* This case is not counted into StatR0DynMapGCPageInl. */
3293 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3294 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3295 }
3296
3297 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3298 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3299
3300 /*
3301 * pgmR0DynMapHCPageInlined with out stats.
3302 */
3303 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3304 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3305 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3306 int rc;
3307
3308 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3309 unsigned iEntry = pSet->aiHashTable[iHash];
3310 if ( iEntry < pSet->cEntries
3311 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3312 {
3313 *ppv = pSet->aEntries[iEntry].pvPage;
3314 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3315 rc = VINF_SUCCESS;
3316 }
3317 else
3318 {
3319 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3320 rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3321 }
3322
3323 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3324 return rc;
3325}
3326
3327#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3328
3329#ifndef IN_RC
3330/**
3331 * Queries the Physical TLB entry for a physical guest page,
3332 * attemting to load the TLB entry if necessary.
3333 *
3334 * @returns VBox status code.
3335 * @retval VINF_SUCCESS on success
3336 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3337 * @param pPGM The PGM instance handle.
3338 * @param GCPhys The address of the guest page.
3339 * @param ppTlbe Where to store the pointer to the TLB entry.
3340 */
3341
3342DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3343{
3344 int rc;
3345 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3346 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3347 {
3348 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3349 rc = VINF_SUCCESS;
3350 }
3351 else
3352 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3353 *ppTlbe = pTlbe;
3354 return rc;
3355}
3356#endif /* !IN_RC */
3357
3358#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3359
3360# ifndef VBOX_WITH_NEW_PHYS_CODE
3361/**
3362 * Convert GC Phys to HC Virt.
3363 *
3364 * @returns VBox status.
3365 * @param pPGM PGM handle.
3366 * @param GCPhys The GC physical address.
3367 * @param pHCPtr Where to store the corresponding HC virtual address.
3368 *
3369 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3370 * pgmPoolMonitorGCPtr2CCPtr.
3371 */
3372DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3373{
3374 PPGMRAMRANGE pRam;
3375 PPGMPAGE pPage;
3376 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3377 if (RT_FAILURE(rc))
3378 {
3379 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3380 return rc;
3381 }
3382 RTGCPHYS off = GCPhys - pRam->GCPhys;
3383
3384 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3385 {
3386 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3387 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3388 return VINF_SUCCESS;
3389 }
3390 if (pRam->pvR3)
3391 {
3392 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3393 return VINF_SUCCESS;
3394 }
3395 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3396 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3397}
3398# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3399#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3400
3401/**
3402 * Convert GC Phys to HC Virt and HC Phys.
3403 *
3404 * @returns VBox status.
3405 * @param pPGM PGM handle.
3406 * @param GCPhys The GC physical address.
3407 * @param pHCPtr Where to store the corresponding HC virtual address.
3408 * @param pHCPhys Where to store the HC Physical address and its flags.
3409 *
3410 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3411 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3412 */
3413DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3414{
3415 PPGMRAMRANGE pRam;
3416 PPGMPAGE pPage;
3417 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3418 if (RT_FAILURE(rc))
3419 {
3420 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3421 *pHCPhys = 0; /* ditto */
3422 return rc;
3423 }
3424 RTGCPHYS off = GCPhys - pRam->GCPhys;
3425
3426 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3427 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3428 {
3429 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3430#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3431 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3432 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3433#else
3434 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3435#endif
3436 return VINF_SUCCESS;
3437 }
3438 if (pRam->pvR3)
3439 {
3440 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3441 return VINF_SUCCESS;
3442 }
3443 *pHCPtr = 0;
3444 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3445}
3446
3447
3448/**
3449 * Clears flags associated with a RAM address.
3450 *
3451 * @returns VBox status code.
3452 * @param pPGM PGM handle.
3453 * @param GCPhys Guest context physical address.
3454 * @param fFlags fFlags to clear. (Bits 0-11.)
3455 */
3456DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3457{
3458 PPGMPAGE pPage;
3459 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3460 if (RT_FAILURE(rc))
3461 return rc;
3462
3463 fFlags &= ~X86_PTE_PAE_PG_MASK;
3464 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3465 return VINF_SUCCESS;
3466}
3467
3468
3469/**
3470 * Clears flags associated with a RAM address.
3471 *
3472 * @returns VBox status code.
3473 * @param pPGM PGM handle.
3474 * @param GCPhys Guest context physical address.
3475 * @param fFlags fFlags to clear. (Bits 0-11.)
3476 * @param ppRamHint Where to read and store the ram list hint.
3477 * The caller initializes this to NULL before the call.
3478 */
3479DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3480{
3481 PPGMPAGE pPage;
3482 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3483 if (RT_FAILURE(rc))
3484 return rc;
3485
3486 fFlags &= ~X86_PTE_PAE_PG_MASK;
3487 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3488 return VINF_SUCCESS;
3489}
3490
3491
3492/**
3493 * Sets (bitwise OR) flags associated with a RAM address.
3494 *
3495 * @returns VBox status code.
3496 * @param pPGM PGM handle.
3497 * @param GCPhys Guest context physical address.
3498 * @param fFlags fFlags to set clear. (Bits 0-11.)
3499 */
3500DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3501{
3502 PPGMPAGE pPage;
3503 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3504 if (RT_FAILURE(rc))
3505 return rc;
3506
3507 fFlags &= ~X86_PTE_PAE_PG_MASK;
3508 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3509 return VINF_SUCCESS;
3510}
3511
3512
3513/**
3514 * Sets (bitwise OR) flags associated with a RAM address.
3515 *
3516 * @returns VBox status code.
3517 * @param pPGM PGM handle.
3518 * @param GCPhys Guest context physical address.
3519 * @param fFlags fFlags to set clear. (Bits 0-11.)
3520 * @param ppRamHint Where to read and store the ram list hint.
3521 * The caller initializes this to NULL before the call.
3522 */
3523DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3524{
3525 PPGMPAGE pPage;
3526 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3527 if (RT_FAILURE(rc))
3528 return rc;
3529
3530 fFlags &= ~X86_PTE_PAE_PG_MASK;
3531 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3532 return VINF_SUCCESS;
3533}
3534
3535
3536/**
3537 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3538 * Takes PSE-36 into account.
3539 *
3540 * @returns guest physical address
3541 * @param pPGM Pointer to the PGM instance data.
3542 * @param Pde Guest Pde
3543 */
3544DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3545{
3546 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3547 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3548
3549 return GCPhys & pPGM->GCPhys4MBPSEMask;
3550}
3551
3552
3553/**
3554 * Gets the page directory entry for the specified address (32-bit paging).
3555 *
3556 * @returns The page directory entry in question.
3557 * @param pPGM Pointer to the PGM instance data.
3558 * @param GCPtr The address.
3559 */
3560DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3561{
3562#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3563 PCX86PD pGuestPD = 0;
3564 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3565 if (RT_FAILURE(rc))
3566 {
3567 X86PDE ZeroPde = {0};
3568 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3569 }
3570 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3571#else
3572 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3573#endif
3574}
3575
3576
3577/**
3578 * Gets the address of a specific page directory entry (32-bit paging).
3579 *
3580 * @returns Pointer the page directory entry in question.
3581 * @param pPGM Pointer to the PGM instance data.
3582 * @param GCPtr The address.
3583 */
3584DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3585{
3586#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3587 PX86PD pGuestPD = 0;
3588 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3589 AssertRCReturn(rc, 0);
3590 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3591#else
3592 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3593#endif
3594}
3595
3596
3597/**
3598 * Gets the address the guest page directory (32-bit paging).
3599 *
3600 * @returns Pointer the page directory entry in question.
3601 * @param pPGM Pointer to the PGM instance data.
3602 */
3603DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3604{
3605#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3606 PX86PD pGuestPD = 0;
3607 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3608 AssertRCReturn(rc, 0);
3609 return pGuestPD;
3610#else
3611 return pPGM->CTX_SUFF(pGst32BitPd);
3612#endif
3613}
3614
3615
3616/**
3617 * Gets the guest page directory pointer table.
3618 *
3619 * @returns Pointer to the page directory in question.
3620 * @returns NULL if the page directory is not present or on an invalid page.
3621 * @param pPGM Pointer to the PGM instance data.
3622 */
3623DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3624{
3625#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3626 PX86PDPT pGuestPDPT = 0;
3627 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3628 AssertRCReturn(rc, 0);
3629 return pGuestPDPT;
3630#else
3631 return pPGM->CTX_SUFF(pGstPaePdpt);
3632#endif
3633}
3634
3635
3636/**
3637 * Gets the guest page directory pointer table entry for the specified address.
3638 *
3639 * @returns Pointer to the page directory in question.
3640 * @returns NULL if the page directory is not present or on an invalid page.
3641 * @param pPGM Pointer to the PGM instance data.
3642 * @param GCPtr The address.
3643 */
3644DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3645{
3646 AssertGCPtr32(GCPtr);
3647
3648#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3649 PX86PDPT pGuestPDPT = 0;
3650 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3651 AssertRCReturn(rc, 0);
3652 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3653#else
3654 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3655#endif
3656}
3657
3658
3659/**
3660 * Gets the page directory for the specified address.
3661 *
3662 * @returns Pointer to the page directory in question.
3663 * @returns NULL if the page directory is not present or on an invalid page.
3664 * @param pPGM Pointer to the PGM instance data.
3665 * @param GCPtr The address.
3666 */
3667DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3668{
3669 AssertGCPtr32(GCPtr);
3670
3671#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3672 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3673 AssertReturn(pGuestPDPT, 0);
3674#else
3675 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3676#endif
3677 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3678 if (pGuestPDPT->a[iPdPt].n.u1Present)
3679 {
3680#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3681 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3682 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3683#endif
3684
3685 /* cache is out-of-sync. */
3686 PX86PDPAE pPD;
3687 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3688 if (RT_SUCCESS(rc))
3689 return pPD;
3690 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3691 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3692 }
3693 return NULL;
3694}
3695
3696
3697/**
3698 * Gets the page directory entry for the specified address.
3699 *
3700 * @returns Pointer to the page directory entry in question.
3701 * @returns NULL if the page directory is not present or on an invalid page.
3702 * @param pPGM Pointer to the PGM instance data.
3703 * @param GCPtr The address.
3704 */
3705DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3706{
3707 AssertGCPtr32(GCPtr);
3708
3709#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3710 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3711 AssertReturn(pGuestPDPT, 0);
3712#else
3713 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3714#endif
3715 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3716 if (pGuestPDPT->a[iPdPt].n.u1Present)
3717 {
3718 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3719#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3720 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3721 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3722#endif
3723
3724 /* The cache is out-of-sync. */
3725 PX86PDPAE pPD;
3726 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3727 if (RT_SUCCESS(rc))
3728 return &pPD->a[iPD];
3729 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3730 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3731 }
3732 return NULL;
3733}
3734
3735
3736/**
3737 * Gets the page directory entry for the specified address.
3738 *
3739 * @returns The page directory entry in question.
3740 * @returns A non-present entry if the page directory is not present or on an invalid page.
3741 * @param pPGM Pointer to the PGM instance data.
3742 * @param GCPtr The address.
3743 */
3744DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3745{
3746 AssertGCPtr32(GCPtr);
3747
3748#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3749 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3750 if (RT_LIKELY(pGuestPDPT))
3751#else
3752 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3753#endif
3754 {
3755 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3756 if (pGuestPDPT->a[iPdPt].n.u1Present)
3757 {
3758 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3759#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3760 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3761 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3762#endif
3763
3764 /* cache is out-of-sync. */
3765 PX86PDPAE pPD;
3766 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3767 if (RT_SUCCESS(rc))
3768 return pPD->a[iPD];
3769 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3770 }
3771 }
3772 X86PDEPAE ZeroPde = {0};
3773 return ZeroPde;
3774}
3775
3776
3777/**
3778 * Gets the page directory pointer table entry for the specified address
3779 * and returns the index into the page directory
3780 *
3781 * @returns Pointer to the page directory in question.
3782 * @returns NULL if the page directory is not present or on an invalid page.
3783 * @param pPGM Pointer to the PGM instance data.
3784 * @param GCPtr The address.
3785 * @param piPD Receives the index into the returned page directory
3786 * @param pPdpe Receives the page directory pointer entry. Optional.
3787 */
3788DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3789{
3790 AssertGCPtr32(GCPtr);
3791
3792#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3793 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3794 AssertReturn(pGuestPDPT, 0);
3795#else
3796 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3797#endif
3798 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3799 if (pPdpe)
3800 *pPdpe = pGuestPDPT->a[iPdPt];
3801 if (pGuestPDPT->a[iPdPt].n.u1Present)
3802 {
3803 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3804#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3805 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3806 {
3807 *piPD = iPD;
3808 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3809 }
3810#endif
3811
3812 /* cache is out-of-sync. */
3813 PX86PDPAE pPD;
3814 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3815 if (RT_SUCCESS(rc))
3816 {
3817 *piPD = iPD;
3818 return pPD;
3819 }
3820 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3821 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3822 }
3823 return NULL;
3824}
3825
3826#ifndef IN_RC
3827
3828/**
3829 * Gets the page map level-4 pointer for the guest.
3830 *
3831 * @returns Pointer to the PML4 page.
3832 * @param pPGM Pointer to the PGM instance data.
3833 */
3834DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3835{
3836#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3837 PX86PML4 pGuestPml4;
3838 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3839 AssertRCReturn(rc, NULL);
3840 return pGuestPml4;
3841#else
3842 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3843 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3844#endif
3845}
3846
3847
3848/**
3849 * Gets the pointer to a page map level-4 entry.
3850 *
3851 * @returns Pointer to the PML4 entry.
3852 * @param pPGM Pointer to the PGM instance data.
3853 * @param iPml4 The index.
3854 */
3855DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3856{
3857#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3858 PX86PML4 pGuestPml4;
3859 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3860 AssertRCReturn(rc, NULL);
3861 return &pGuestPml4->a[iPml4];
3862#else
3863 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3864 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3865#endif
3866}
3867
3868
3869/**
3870 * Gets a page map level-4 entry.
3871 *
3872 * @returns The PML4 entry.
3873 * @param pPGM Pointer to the PGM instance data.
3874 * @param iPml4 The index.
3875 */
3876DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3877{
3878#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3879 PX86PML4 pGuestPml4;
3880 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3881 if (RT_FAILURE(rc))
3882 {
3883 X86PML4E ZeroPml4e = {0};
3884 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3885 }
3886 return pGuestPml4->a[iPml4];
3887#else
3888 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3889 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3890#endif
3891}
3892
3893
3894/**
3895 * Gets the page directory pointer entry for the specified address.
3896 *
3897 * @returns Pointer to the page directory pointer entry in question.
3898 * @returns NULL if the page directory is not present or on an invalid page.
3899 * @param pPGM Pointer to the PGM instance data.
3900 * @param GCPtr The address.
3901 * @param ppPml4e Page Map Level-4 Entry (out)
3902 */
3903DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3904{
3905 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3906 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3907 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3908 if (pPml4e->n.u1Present)
3909 {
3910 PX86PDPT pPdpt;
3911 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3912 AssertRCReturn(rc, NULL);
3913
3914 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3915 return &pPdpt->a[iPdPt];
3916 }
3917 return NULL;
3918}
3919
3920
3921/**
3922 * Gets the page directory entry for the specified address.
3923 *
3924 * @returns The page directory entry in question.
3925 * @returns A non-present entry if the page directory is not present or on an invalid page.
3926 * @param pPGM Pointer to the PGM instance data.
3927 * @param GCPtr The address.
3928 * @param ppPml4e Page Map Level-4 Entry (out)
3929 * @param pPdpe Page directory pointer table entry (out)
3930 */
3931DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3932{
3933 X86PDEPAE ZeroPde = {0};
3934 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3935 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3936 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3937 if (pPml4e->n.u1Present)
3938 {
3939 PCX86PDPT pPdptTemp;
3940 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3941 AssertRCReturn(rc, ZeroPde);
3942
3943 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3944 *pPdpe = pPdptTemp->a[iPdPt];
3945 if (pPdptTemp->a[iPdPt].n.u1Present)
3946 {
3947 PCX86PDPAE pPD;
3948 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3949 AssertRCReturn(rc, ZeroPde);
3950
3951 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3952 return pPD->a[iPD];
3953 }
3954 }
3955
3956 return ZeroPde;
3957}
3958
3959
3960/**
3961 * Gets the page directory entry for the specified address.
3962 *
3963 * @returns The page directory entry in question.
3964 * @returns A non-present entry if the page directory is not present or on an invalid page.
3965 * @param pPGM Pointer to the PGM instance data.
3966 * @param GCPtr The address.
3967 */
3968DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
3969{
3970 X86PDEPAE ZeroPde = {0};
3971 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3972 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3973 if (pGuestPml4->a[iPml4].n.u1Present)
3974 {
3975 PCX86PDPT pPdptTemp;
3976 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3977 AssertRCReturn(rc, ZeroPde);
3978
3979 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3980 if (pPdptTemp->a[iPdPt].n.u1Present)
3981 {
3982 PCX86PDPAE pPD;
3983 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3984 AssertRCReturn(rc, ZeroPde);
3985
3986 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3987 return pPD->a[iPD];
3988 }
3989 }
3990 return ZeroPde;
3991}
3992
3993
3994/**
3995 * Gets the page directory entry for the specified address.
3996 *
3997 * @returns Pointer to the page directory entry in question.
3998 * @returns NULL if the page directory is not present or on an invalid page.
3999 * @param pPGM Pointer to the PGM instance data.
4000 * @param GCPtr The address.
4001 */
4002DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4003{
4004 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4005 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4006 if (pGuestPml4->a[iPml4].n.u1Present)
4007 {
4008 PCX86PDPT pPdptTemp;
4009 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4010 AssertRCReturn(rc, NULL);
4011
4012 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4013 if (pPdptTemp->a[iPdPt].n.u1Present)
4014 {
4015 PX86PDPAE pPD;
4016 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4017 AssertRCReturn(rc, NULL);
4018
4019 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4020 return &pPD->a[iPD];
4021 }
4022 }
4023 return NULL;
4024}
4025
4026
4027/**
4028 * Gets the GUEST page directory pointer for the specified address.
4029 *
4030 * @returns The page directory in question.
4031 * @returns NULL if the page directory is not present or on an invalid page.
4032 * @param pPGM Pointer to the PGM instance data.
4033 * @param GCPtr The address.
4034 * @param ppPml4e Page Map Level-4 Entry (out)
4035 * @param pPdpe Page directory pointer table entry (out)
4036 * @param piPD Receives the index into the returned page directory
4037 */
4038DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4039{
4040 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4041 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4042 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4043 if (pPml4e->n.u1Present)
4044 {
4045 PCX86PDPT pPdptTemp;
4046 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4047 AssertRCReturn(rc, NULL);
4048
4049 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4050 *pPdpe = pPdptTemp->a[iPdPt];
4051 if (pPdptTemp->a[iPdPt].n.u1Present)
4052 {
4053 PX86PDPAE pPD;
4054 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4055 AssertRCReturn(rc, NULL);
4056
4057 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4058 return pPD;
4059 }
4060 }
4061 return 0;
4062}
4063
4064#endif /* !IN_RC */
4065
4066
4067/**
4068 * Gets the shadow page directory, 32-bit.
4069 *
4070 * @returns Pointer to the shadow 32-bit PD.
4071 * @param pPGM Pointer to the PGM instance data.
4072 */
4073DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4074{
4075#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4076 return (PX86PD)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4077#else
4078# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4079 PX86PD pShwPd;
4080 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4081 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4082 AssertRCReturn(rc, NULL);
4083 return pShwPd;
4084# else
4085 return pPGM->CTX_SUFF(pShw32BitPd);
4086# endif
4087#endif
4088}
4089
4090
4091/**
4092 * Gets the shadow page directory entry for the specified address, 32-bit.
4093 *
4094 * @returns Shadow 32-bit PDE.
4095 * @param pPGM Pointer to the PGM instance data.
4096 * @param GCPtr The address.
4097 */
4098DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4099{
4100 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4101
4102 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4103 if (!pShwPde)
4104 {
4105 X86PDE ZeroPde = {0};
4106 return ZeroPde;
4107 }
4108 return pShwPde->a[iPd];
4109}
4110
4111
4112/**
4113 * Gets the pointer to the shadow page directory entry for the specified
4114 * address, 32-bit.
4115 *
4116 * @returns Pointer to the shadow 32-bit PDE.
4117 * @param pPGM Pointer to the PGM instance data.
4118 * @param GCPtr The address.
4119 */
4120DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4121{
4122 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4123
4124 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4125 AssertReturn(pPde, NULL);
4126 return &pPde->a[iPd];
4127}
4128
4129
4130/**
4131 * Gets the shadow page pointer table, PAE.
4132 *
4133 * @returns Pointer to the shadow PAE PDPT.
4134 * @param pPGM Pointer to the PGM instance data.
4135 */
4136DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4137{
4138#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4139 return (PX86PDPT)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4140#else
4141# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4142 PX86PDPT pShwPdpt;
4143 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4144 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4145 AssertRCReturn(rc, 0);
4146 return pShwPdpt;
4147# else
4148 return pPGM->CTX_SUFF(pShwPaePdpt);
4149# endif
4150#endif
4151}
4152
4153
4154/**
4155 * Gets the shadow page directory for the specified address, PAE.
4156 *
4157 * @returns Pointer to the shadow PD.
4158 * @param pPGM Pointer to the PGM instance data.
4159 * @param GCPtr The address.
4160 */
4161DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4162{
4163#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4164 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4165 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4166
4167 /* Fetch the pgm pool shadow descriptor. */
4168 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4169 AssertReturn(pShwPde, NULL);
4170
4171 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pShwPde);
4172#else
4173 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4174# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4175 PX86PDPAE pPD;
4176 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4177 AssertRCReturn(rc, 0);
4178 return pPD;
4179# else
4180 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4181 Assert(pPD);
4182 return pPD;
4183# endif
4184#endif
4185}
4186
4187
4188/**
4189 * Gets the shadow page directory entry, PAE.
4190 *
4191 * @returns PDE.
4192 * @param pPGM Pointer to the PGM instance data.
4193 * @param GCPtr The address.
4194 */
4195DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4196{
4197 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4198
4199 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4200 if (!pShwPde)
4201 {
4202 X86PDEPAE ZeroPde = {0};
4203 return ZeroPde;
4204 }
4205 return pShwPde->a[iPd];
4206}
4207
4208
4209/**
4210 * Gets the pointer to the shadow page directory entry for an address, PAE.
4211 *
4212 * @returns Pointer to the PDE.
4213 * @param pPGM Pointer to the PGM instance data.
4214 * @param GCPtr The address.
4215 */
4216DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4217{
4218 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4219
4220 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4221 AssertReturn(pPde, NULL);
4222 return &pPde->a[iPd];
4223}
4224
4225#ifndef IN_RC
4226
4227/**
4228 * Gets the shadow page map level-4 pointer.
4229 *
4230 * @returns Pointer to the shadow PML4.
4231 * @param pPGM Pointer to the PGM instance data.
4232 */
4233DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4234{
4235#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4236 return (PX86PML4)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4237#else
4238# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4239 PX86PML4 pShwPml4;
4240 Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
4241 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePml4, &pShwPml4);
4242 AssertRCReturn(rc, 0);
4243 return pShwPml4;
4244# else
4245 Assert(pPGM->CTX_SUFF(pShwPaePml4));
4246 return pPGM->CTX_SUFF(pShwPaePml4);
4247# endif
4248#endif
4249}
4250
4251
4252/**
4253 * Gets the shadow page map level-4 entry for the specified address.
4254 *
4255 * @returns The entry.
4256 * @param pPGM Pointer to the PGM instance data.
4257 * @param GCPtr The address.
4258 */
4259DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4260{
4261 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4262 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4263
4264 if (!pShwPml4)
4265 {
4266 X86PML4E ZeroPml4e = {0};
4267 return ZeroPml4e;
4268 }
4269 return pShwPml4->a[iPml4];
4270}
4271
4272
4273/**
4274 * Gets the pointer to the specified shadow page map level-4 entry.
4275 *
4276 * @returns The entry.
4277 * @param pPGM Pointer to the PGM instance data.
4278 * @param iPml4 The PML4 index.
4279 */
4280DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4281{
4282 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4283
4284 if (!pShwPml4)
4285 return NULL;
4286
4287 return &pShwPml4->a[iPml4];
4288}
4289
4290
4291/**
4292 * Gets the GUEST page directory pointer for the specified address.
4293 *
4294 * @returns The page directory in question.
4295 * @returns NULL if the page directory is not present or on an invalid page.
4296 * @param pPGM Pointer to the PGM instance data.
4297 * @param GCPtr The address.
4298 * @param piPD Receives the index into the returned page directory
4299 */
4300DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4301{
4302 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4303 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4304 if (pGuestPml4->a[iPml4].n.u1Present)
4305 {
4306 PCX86PDPT pPdptTemp;
4307 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4308 AssertRCReturn(rc, NULL);
4309
4310 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4311 if (pPdptTemp->a[iPdPt].n.u1Present)
4312 {
4313 PX86PDPAE pPD;
4314 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4315 AssertRCReturn(rc, NULL);
4316
4317 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4318 return pPD;
4319 }
4320 }
4321 return NULL;
4322}
4323
4324#endif /* !IN_RC */
4325
4326/**
4327 * Checks if any of the specified page flags are set for the given page.
4328 *
4329 * @returns true if any of the flags are set.
4330 * @returns false if all the flags are clear.
4331 * @param pPGM PGM handle.
4332 * @param GCPhys The GC physical address.
4333 * @param fFlags The flags to check for.
4334 */
4335DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4336{
4337 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4338 return pPage
4339 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4340}
4341
4342
4343/**
4344 * Gets the page state for a physical handler.
4345 *
4346 * @returns The physical handler page state.
4347 * @param pCur The physical handler in question.
4348 */
4349DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4350{
4351 switch (pCur->enmType)
4352 {
4353 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4354 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4355
4356 case PGMPHYSHANDLERTYPE_MMIO:
4357 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4358 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4359
4360 default:
4361 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4362 }
4363}
4364
4365
4366/**
4367 * Gets the page state for a virtual handler.
4368 *
4369 * @returns The virtual handler page state.
4370 * @param pCur The virtual handler in question.
4371 * @remarks This should never be used on a hypervisor access handler.
4372 */
4373DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4374{
4375 switch (pCur->enmType)
4376 {
4377 case PGMVIRTHANDLERTYPE_WRITE:
4378 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4379 case PGMVIRTHANDLERTYPE_ALL:
4380 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4381 default:
4382 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4383 }
4384}
4385
4386
4387/**
4388 * Clears one physical page of a virtual handler
4389 *
4390 * @param pPGM Pointer to the PGM instance.
4391 * @param pCur Virtual handler structure
4392 * @param iPage Physical page index
4393 *
4394 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4395 * need to care about other handlers in the same page.
4396 */
4397DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4398{
4399 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4400
4401 /*
4402 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4403 */
4404#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4405 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4406 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4407 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4408#endif
4409 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4410 {
4411 /* We're the head of the alias chain. */
4412 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4413#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4414 AssertReleaseMsg(pRemove != NULL,
4415 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4416 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4417 AssertReleaseMsg(pRemove == pPhys2Virt,
4418 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4419 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4420 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4421 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4422#endif
4423 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4424 {
4425 /* Insert the next list in the alias chain into the tree. */
4426 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4427#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4428 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4429 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4430 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4431#endif
4432 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4433 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4434 AssertRelease(fRc);
4435 }
4436 }
4437 else
4438 {
4439 /* Locate the previous node in the alias chain. */
4440 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4441#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4442 AssertReleaseMsg(pPrev != pPhys2Virt,
4443 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4444 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4445#endif
4446 for (;;)
4447 {
4448 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4449 if (pNext == pPhys2Virt)
4450 {
4451 /* unlink. */
4452 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4453 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4454 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4455 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4456 else
4457 {
4458 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4459 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4460 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4461 }
4462 break;
4463 }
4464
4465 /* next */
4466 if (pNext == pPrev)
4467 {
4468#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4469 AssertReleaseMsg(pNext != pPrev,
4470 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4471 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4472#endif
4473 break;
4474 }
4475 pPrev = pNext;
4476 }
4477 }
4478 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4479 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4480 pPhys2Virt->offNextAlias = 0;
4481 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4482
4483 /*
4484 * Clear the ram flags for this page.
4485 */
4486 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4487 AssertReturnVoid(pPage);
4488 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4489}
4490
4491
4492/**
4493 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4494 *
4495 * @returns Pointer to the shadow page structure.
4496 * @param pPool The pool.
4497 * @param HCPhys The HC physical address of the shadow page.
4498 */
4499DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4500{
4501 /*
4502 * Look up the page.
4503 */
4504 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4505 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4506 return pPage;
4507}
4508
4509
4510/**
4511 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4512 *
4513 * @returns Pointer to the shadow page structure.
4514 * @param pPool The pool.
4515 * @param idx The pool page index.
4516 */
4517DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4518{
4519 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4520 return &pPool->aPages[idx];
4521}
4522
4523
4524#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4525/**
4526 * Clear references to guest physical memory.
4527 *
4528 * @param pPool The pool.
4529 * @param pPoolPage The pool page.
4530 * @param pPhysPage The physical guest page tracking structure.
4531 */
4532DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4533{
4534 /*
4535 * Just deal with the simple case here.
4536 */
4537# ifdef LOG_ENABLED
4538 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4539# endif
4540 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4541 if (cRefs == 1)
4542 {
4543 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4544 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4545 }
4546 else
4547 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4548 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4549}
4550#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4551
4552
4553#ifdef PGMPOOL_WITH_CACHE
4554/**
4555 * Moves the page to the head of the age list.
4556 *
4557 * This is done when the cached page is used in one way or another.
4558 *
4559 * @param pPool The pool.
4560 * @param pPage The cached page.
4561 * @todo inline in PGMInternal.h!
4562 */
4563DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4564{
4565 /*
4566 * Move to the head of the age list.
4567 */
4568 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4569 {
4570 /* unlink */
4571 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4572 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4573 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4574 else
4575 pPool->iAgeTail = pPage->iAgePrev;
4576
4577 /* insert at head */
4578 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4579 pPage->iAgeNext = pPool->iAgeHead;
4580 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4581 pPool->iAgeHead = pPage->idx;
4582 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4583 }
4584}
4585#endif /* PGMPOOL_WITH_CACHE */
4586
4587/**
4588 * Tells if mappings are to be put into the shadow page table or not
4589 *
4590 * @returns boolean result
4591 * @param pVM VM handle.
4592 */
4593
4594DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4595{
4596#ifdef IN_RING0
4597 /* There are no mappings in VT-x and AMD-V mode. */
4598 Assert(pPGM->fDisableMappings);
4599 return false;
4600#else
4601 return !pPGM->fDisableMappings;
4602#endif
4603}
4604
4605/** @} */
4606
4607#endif
4608
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