VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 15346

Last change on this file since 15346 was 15346, checked in by vboxsync, 16 years ago

Avoid a few calls to RTMpCpuId() and RTMCpuIdToSetIndex().
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File size: 187.8 KB
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1/* $Id: PGMInternal.h 15346 2008-12-12 01:23:23Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** Mapping (hypervisor allocated pagetable). */
155#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156/** @} */
157
158/** @name Page directory flags.
159 * These are placed in the three bits available for system programs in
160 * the page directory entries.
161 * @{ */
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164/** Made read-only to facilitate dirty bit tracking. */
165#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166/** @} */
167
168/** @name Page flags.
169 * These are placed in the three bits available for system programs in
170 * the page entries.
171 * @{ */
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176/** Scanned and approved by CSAM (tm).
177 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
178 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180#endif
181/** @} */
182
183/** @name Defines used to indicate the shadow and guest paging in the templates.
184 * @{ */
185#define PGM_TYPE_REAL 1
186#define PGM_TYPE_PROT 2
187#define PGM_TYPE_32BIT 3
188#define PGM_TYPE_PAE 4
189#define PGM_TYPE_AMD64 5
190#define PGM_TYPE_NESTED 6
191#define PGM_TYPE_EPT 7
192#define PGM_TYPE_MAX PGM_TYPE_EPT
193/** @} */
194
195/** Macro for checking if the guest is using paging.
196 * @param uGstType PGM_TYPE_*
197 * @param uShwType PGM_TYPE_*
198 * @remark ASSUMES certain order of the PGM_TYPE_* values.
199 */
200#define PGM_WITH_PAGING(uGstType, uShwType) \
201 ( (uGstType) >= PGM_TYPE_32BIT \
202 && (uShwType) != PGM_TYPE_NESTED \
203 && (uShwType) != PGM_TYPE_EPT)
204
205/** Macro for checking if the guest supports the NX bit.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_NX(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_PAE \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215
216/** @def PGM_HCPHYS_2_PTR
217 * Maps a HC physical page pool address to a virtual address.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM handle.
221 * @param HCPhys The HC physical address to map to a virtual one.
222 * @param ppv Where to store the virtual address. No need to cast this.
223 *
224 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225 * small page window employeed by that function. Be careful.
226 * @remark There is no need to assert on the result.
227 */
228#ifdef IN_RC
229# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
232# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
234#else
235# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
237#endif
238
239/** @def PGM_HCPHYS_2_PTR_BY_PGM
240 * Maps a HC physical page pool address to a virtual address.
241 *
242 * @returns VBox status code.
243 * @param pPGM The PGM instance data.
244 * @param HCPhys The HC physical address to map to a virtual one.
245 * @param ppv Where to store the virtual address. No need to cast this.
246 *
247 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
248 * small page window employeed by that function. Be careful.
249 * @remark There is no need to assert on the result.
250 */
251#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
252# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
253 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
254#else
255# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
256 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
257#endif
258
259/** @def PGM_GCPHYS_2_PTR
260 * Maps a GC physical page address to a virtual address.
261 *
262 * @returns VBox status code.
263 * @param pVM The VM handle.
264 * @param GCPhys The GC physical address to map to a virtual one.
265 * @param ppv Where to store the virtual address. No need to cast this.
266 *
267 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
268 * small page window employeed by that function. Be careful.
269 * @remark There is no need to assert on the result.
270 */
271#ifdef IN_RC
272# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
273 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
274#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
275# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
276 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
277#else
278# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
280#endif
281
282/** @def PGM_GCPHYS_2_PTR_BY_PGM
283 * Maps a GC physical page address to a virtual address.
284 *
285 * @returns VBox status code.
286 * @param pPGM Pointer to the PGM instance data.
287 * @param GCPhys The GC physical address to map to a virtual one.
288 * @param ppv Where to store the virtual address. No need to cast this.
289 *
290 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
291 * small page window employeed by that function. Be careful.
292 * @remark There is no need to assert on the result.
293 */
294#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
295# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
296 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
297#else
298# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
299 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
300#endif
301
302/** @def PGM_GCPHYS_2_PTR_EX
303 * Maps a unaligned GC physical page address to a virtual address.
304 *
305 * @returns VBox status code.
306 * @param pVM The VM handle.
307 * @param GCPhys The GC physical address to map to a virtual one.
308 * @param ppv Where to store the virtual address. No need to cast this.
309 *
310 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
311 * small page window employeed by that function. Be careful.
312 * @remark There is no need to assert on the result.
313 */
314#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
315# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
316 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
317#else
318# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
319 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
320#endif
321
322/** @def PGM_INVL_PG
323 * Invalidates a page when in GC does nothing in HC.
324 *
325 * @param GCVirt The virtual address of the page to invalidate.
326 */
327#ifdef IN_RC
328# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
329#elif defined(IN_RING0)
330# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
331#else
332# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
333#endif
334
335/** @def PGM_INVL_BIG_PG
336 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
337 *
338 * @param GCVirt The virtual address within the page directory to invalidate.
339 */
340#ifdef IN_RC
341# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
342#elif defined(IN_RING0)
343# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
344#else
345# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
346#endif
347
348/** @def PGM_INVL_GUEST_TLBS()
349 * Invalidates all guest TLBs.
350 */
351#ifdef IN_RC
352# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
353#elif defined(IN_RING0)
354# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
355#else
356# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
357#endif
358
359
360/**
361 * Structure for tracking GC Mappings.
362 *
363 * This structure is used by linked list in both GC and HC.
364 */
365typedef struct PGMMAPPING
366{
367 /** Pointer to next entry. */
368 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
369 /** Pointer to next entry. */
370 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
371 /** Pointer to next entry. */
372 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
373#if GC_ARCH_BITS == 64
374 RTRCPTR padding0;
375#endif
376 /** Start Virtual address. */
377 RTGCPTR GCPtr;
378 /** Last Virtual address (inclusive). */
379 RTGCPTR GCPtrLast;
380 /** Range size (bytes). */
381 RTGCPTR cb;
382 /** Pointer to relocation callback function. */
383 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
384 /** User argument to the callback. */
385 R3PTRTYPE(void *) pvUser;
386 /** Mapping description / name. For easing debugging. */
387 R3PTRTYPE(const char *) pszDesc;
388 /** Number of page tables. */
389 RTUINT cPTs;
390#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
391 RTUINT uPadding1; /**< Alignment padding. */
392#endif
393 /** Array of page table mapping data. Each entry
394 * describes one page table. The array can be longer
395 * than the declared length.
396 */
397 struct
398 {
399 /** The HC physical address of the page table. */
400 RTHCPHYS HCPhysPT;
401 /** The HC physical address of the first PAE page table. */
402 RTHCPHYS HCPhysPaePT0;
403 /** The HC physical address of the second PAE page table. */
404 RTHCPHYS HCPhysPaePT1;
405 /** The HC virtual address of the 32-bit page table. */
406 R3PTRTYPE(PX86PT) pPTR3;
407 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
408 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
409 /** The GC virtual address of the 32-bit page table. */
410 RCPTRTYPE(PX86PT) pPTRC;
411 /** The GC virtual address of the two PAE page table. */
412 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
413 /** The GC virtual address of the 32-bit page table. */
414 R0PTRTYPE(PX86PT) pPTR0;
415 /** The GC virtual address of the two PAE page table. */
416 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
417 } aPTs[1];
418} PGMMAPPING;
419/** Pointer to structure for tracking GC Mappings. */
420typedef struct PGMMAPPING *PPGMMAPPING;
421
422
423/**
424 * Physical page access handler structure.
425 *
426 * This is used to keep track of physical address ranges
427 * which are being monitored in some kind of way.
428 */
429typedef struct PGMPHYSHANDLER
430{
431 AVLROGCPHYSNODECORE Core;
432 /** Access type. */
433 PGMPHYSHANDLERTYPE enmType;
434 /** Number of pages to update. */
435 uint32_t cPages;
436 /** Pointer to R3 callback function. */
437 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
438 /** User argument for R3 handlers. */
439 R3PTRTYPE(void *) pvUserR3;
440 /** Pointer to R0 callback function. */
441 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
442 /** User argument for R0 handlers. */
443 R0PTRTYPE(void *) pvUserR0;
444 /** Pointer to GC callback function. */
445 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
446 /** User argument for RC handlers. */
447 RCPTRTYPE(void *) pvUserRC;
448 /** Description / Name. For easing debugging. */
449 R3PTRTYPE(const char *) pszDesc;
450#ifdef VBOX_WITH_STATISTICS
451 /** Profiling of this handler. */
452 STAMPROFILE Stat;
453#endif
454} PGMPHYSHANDLER;
455/** Pointer to a physical page access handler structure. */
456typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
457
458
459/**
460 * Cache node for the physical addresses covered by a virtual handler.
461 */
462typedef struct PGMPHYS2VIRTHANDLER
463{
464 /** Core node for the tree based on physical ranges. */
465 AVLROGCPHYSNODECORE Core;
466 /** Offset from this struct to the PGMVIRTHANDLER structure. */
467 int32_t offVirtHandler;
468 /** Offset of the next alias relative to this one.
469 * Bit 0 is used for indicating whether we're in the tree.
470 * Bit 1 is used for indicating that we're the head node.
471 */
472 int32_t offNextAlias;
473} PGMPHYS2VIRTHANDLER;
474/** Pointer to a phys to virtual handler structure. */
475typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
476
477/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
478 * node is in the tree. */
479#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
480/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
481 * node is in the head of an alias chain.
482 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
483#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
484/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
485#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
486
487
488/**
489 * Virtual page access handler structure.
490 *
491 * This is used to keep track of virtual address ranges
492 * which are being monitored in some kind of way.
493 */
494typedef struct PGMVIRTHANDLER
495{
496 /** Core node for the tree based on virtual ranges. */
497 AVLROGCPTRNODECORE Core;
498 /** Size of the range (in bytes). */
499 RTGCPTR cb;
500 /** Number of cache pages. */
501 uint32_t cPages;
502 /** Access type. */
503 PGMVIRTHANDLERTYPE enmType;
504 /** Pointer to the RC callback function. */
505 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
506#if HC_ARCH_BITS == 64
507 RTRCPTR padding;
508#endif
509 /** Pointer to the R3 callback function for invalidation. */
510 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
511 /** Pointer to the R3 callback function. */
512 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
513 /** Description / Name. For easing debugging. */
514 R3PTRTYPE(const char *) pszDesc;
515#ifdef VBOX_WITH_STATISTICS
516 /** Profiling of this handler. */
517 STAMPROFILE Stat;
518#endif
519 /** Array of cached physical addresses for the monitored ranged. */
520 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
521} PGMVIRTHANDLER;
522/** Pointer to a virtual page access handler structure. */
523typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
524
525
526/**
527 * Page type.
528 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
529 * @todo convert to \#defines.
530 */
531typedef enum PGMPAGETYPE
532{
533 /** The usual invalid zero entry. */
534 PGMPAGETYPE_INVALID = 0,
535 /** RAM page. (RWX) */
536 PGMPAGETYPE_RAM,
537 /** MMIO2 page. (RWX) */
538 PGMPAGETYPE_MMIO2,
539 /** Shadowed ROM. (RWX) */
540 PGMPAGETYPE_ROM_SHADOW,
541 /** ROM page. (R-X) */
542 PGMPAGETYPE_ROM,
543 /** MMIO page. (---) */
544 PGMPAGETYPE_MMIO,
545 /** End of valid entries. */
546 PGMPAGETYPE_END
547} PGMPAGETYPE;
548AssertCompile(PGMPAGETYPE_END < 7);
549
550/** @name Page type predicates.
551 * @{ */
552#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
553#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
554#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
555#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
556#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
557/** @} */
558
559
560/**
561 * A Physical Guest Page tracking structure.
562 *
563 * The format of this structure is complicated because we have to fit a lot
564 * of information into as few bits as possible. The format is also subject
565 * to change (there is one comming up soon). Which means that for we'll be
566 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
567 * accessess to the structure.
568 */
569typedef struct PGMPAGE
570{
571 /** The physical address and a whole lot of other stuff. All bits are used! */
572 RTHCPHYS HCPhys;
573 /** The page state. */
574 uint32_t u2StateX : 2;
575 /** Flag indicating that a write monitored page was written to when set. */
576 uint32_t fWrittenToX : 1;
577 /** For later. */
578 uint32_t fSomethingElse : 1;
579 /** The Page ID.
580 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
581 * The HCPhys will be 100% static. */
582 uint32_t idPageX : 28;
583 /** The page type (PGMPAGETYPE). */
584 uint32_t u3Type : 3;
585 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
586 uint32_t u2HandlerPhysStateX : 2;
587 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
588 uint32_t u2HandlerVirtStateX : 2;
589 uint32_t u29B : 25;
590} PGMPAGE;
591AssertCompileSize(PGMPAGE, 16);
592/** Pointer to a physical guest page. */
593typedef PGMPAGE *PPGMPAGE;
594/** Pointer to a const physical guest page. */
595typedef const PGMPAGE *PCPGMPAGE;
596/** Pointer to a physical guest page pointer. */
597typedef PPGMPAGE *PPPGMPAGE;
598
599
600/**
601 * Clears the page structure.
602 * @param pPage Pointer to the physical guest page tracking structure.
603 */
604#define PGM_PAGE_CLEAR(pPage) \
605 do { \
606 (pPage)->HCPhys = 0; \
607 (pPage)->u2StateX = 0; \
608 (pPage)->fWrittenToX = 0; \
609 (pPage)->fSomethingElse = 0; \
610 (pPage)->idPageX = 0; \
611 (pPage)->u3Type = 0; \
612 (pPage)->u29B = 0; \
613 } while (0)
614
615/**
616 * Initializes the page structure.
617 * @param pPage Pointer to the physical guest page tracking structure.
618 */
619#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
620 do { \
621 (pPage)->HCPhys = (_HCPhys); \
622 (pPage)->u2StateX = (_uState); \
623 (pPage)->fWrittenToX = 0; \
624 (pPage)->fSomethingElse = 0; \
625 (pPage)->idPageX = (_idPage); \
626 /*(pPage)->u3Type = (_uType); - later */ \
627 PGM_PAGE_SET_TYPE(pPage, _uType); \
628 (pPage)->u29B = 0; \
629 } while (0)
630
631/**
632 * Initializes the page structure of a ZERO page.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#ifdef VBOX_WITH_NEW_PHYS_CODE
636# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
637 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
638#else
639# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
640 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
641#endif
642/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
643# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
644 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645
646
647/** @name The Page state, PGMPAGE::u2StateX.
648 * @{ */
649/** The zero page.
650 * This is a per-VM page that's never ever mapped writable. */
651#define PGM_PAGE_STATE_ZERO 0
652/** A allocated page.
653 * This is a per-VM page allocated from the page pool (or wherever
654 * we get MMIO2 pages from if the type is MMIO2).
655 */
656#define PGM_PAGE_STATE_ALLOCATED 1
657/** A allocated page that's being monitored for writes.
658 * The shadow page table mappings are read-only. When a write occurs, the
659 * fWrittenTo member is set, the page remapped as read-write and the state
660 * moved back to allocated. */
661#define PGM_PAGE_STATE_WRITE_MONITORED 2
662/** The page is shared, aka. copy-on-write.
663 * This is a page that's shared with other VMs. */
664#define PGM_PAGE_STATE_SHARED 3
665/** @} */
666
667
668/**
669 * Gets the page state.
670 * @returns page state (PGM_PAGE_STATE_*).
671 * @param pPage Pointer to the physical guest page tracking structure.
672 */
673#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
674
675/**
676 * Sets the page state.
677 * @param pPage Pointer to the physical guest page tracking structure.
678 * @param _uState The new page state.
679 */
680#define PGM_PAGE_SET_STATE(pPage, _uState) \
681 do { (pPage)->u2StateX = (_uState); } while (0)
682
683
684/**
685 * Gets the host physical address of the guest page.
686 * @returns host physical address (RTHCPHYS).
687 * @param pPage Pointer to the physical guest page tracking structure.
688 */
689#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
690
691/**
692 * Sets the host physical address of the guest page.
693 * @param pPage Pointer to the physical guest page tracking structure.
694 * @param _HCPhys The new host physical address.
695 */
696#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
697 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
698 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
699
700/**
701 * Get the Page ID.
702 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
703 * @param pPage Pointer to the physical guest page tracking structure.
704 */
705#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
706/* later:
707#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
708 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
709*/
710/**
711 * Sets the Page ID.
712 * @param pPage Pointer to the physical guest page tracking structure.
713 */
714#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
715/* later:
716#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
717 | ((_idPage) & 0xfff) \
718 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
719*/
720
721/**
722 * Get the Chunk ID.
723 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
724 * @param pPage Pointer to the physical guest page tracking structure.
725 */
726#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
727/* later:
728#if GMM_CHUNKID_SHIFT == 12
729# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
730#elif GMM_CHUNKID_SHIFT > 12
731# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
732#elif GMM_CHUNKID_SHIFT < 12
733# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
734 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
735#else
736# error "GMM_CHUNKID_SHIFT isn't defined or something."
737#endif
738*/
739
740/**
741 * Get the index of the page within the allocaiton chunk.
742 * @returns The page index.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 */
745#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
746/* later:
747#if GMM_CHUNKID_SHIFT <= 12
748# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
749#else
750# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
751 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
752#endif
753*/
754
755
756/**
757 * Gets the page type.
758 * @returns The page type.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
762
763/**
764 * Sets the page type.
765 * @param pPage Pointer to the physical guest page tracking structure.
766 * @param _enmType The new page type (PGMPAGETYPE).
767 */
768#ifdef VBOX_WITH_NEW_PHYS_CODE
769#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
770 do { (pPage)->u3Type = (_enmType); } while (0)
771#else
772#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
773 do { \
774 (pPage)->u3Type = (_enmType); \
775 if ((_enmType) == PGMPAGETYPE_ROM) \
776 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
777 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
778 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
779 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
780 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
781 } while (0)
782#endif
783
784
785/**
786 * Checks if the page is 'reserved'.
787 * @returns true/false.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
791
792/**
793 * Checks if the page is marked for MMIO.
794 * @returns true/false.
795 * @param pPage Pointer to the physical guest page tracking structure.
796 */
797#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
798
799/**
800 * Checks if the page is backed by the ZERO page.
801 * @returns true/false.
802 * @param pPage Pointer to the physical guest page tracking structure.
803 */
804#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
805
806/**
807 * Checks if the page is backed by a SHARED page.
808 * @returns true/false.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
812
813
814/**
815 * Marks the paget as written to (for GMM change monitoring).
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
819
820/**
821 * Clears the written-to indicator.
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
825
826/**
827 * Checks if the page was marked as written-to.
828 * @returns true/false.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
832
833
834/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
835 *
836 * @remarks The values are assigned in order of priority, so we can calculate
837 * the correct state for a page with different handlers installed.
838 * @{ */
839/** No handler installed. */
840#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
841/** Monitoring is temporarily disabled. */
842#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
843/** Write access is monitored. */
844#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
845/** All access is monitored. */
846#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
847/** @} */
848
849/**
850 * Gets the physical access handler state of a page.
851 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
852 * @param pPage Pointer to the physical guest page tracking structure.
853 */
854#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
855
856/**
857 * Sets the physical access handler state of a page.
858 * @param pPage Pointer to the physical guest page tracking structure.
859 * @param _uState The new state value.
860 */
861#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
862 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
863
864/**
865 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
866 * @returns true/false
867 * @param pPage Pointer to the physical guest page tracking structure.
868 */
869#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
870
871/**
872 * Checks if the page has any active physical access handlers.
873 * @returns true/false
874 * @param pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
877
878
879/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
880 *
881 * @remarks The values are assigned in order of priority, so we can calculate
882 * the correct state for a page with different handlers installed.
883 * @{ */
884/** No handler installed. */
885#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
886/* 1 is reserved so the lineup is identical with the physical ones. */
887/** Write access is monitored. */
888#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
889/** All access is monitored. */
890#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
891/** @} */
892
893/**
894 * Gets the virtual access handler state of a page.
895 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
896 * @param pPage Pointer to the physical guest page tracking structure.
897 */
898#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
899
900/**
901 * Sets the virtual access handler state of a page.
902 * @param pPage Pointer to the physical guest page tracking structure.
903 * @param _uState The new state value.
904 */
905#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
906 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
907
908/**
909 * Checks if the page has any virtual access handlers.
910 * @returns true/false
911 * @param pPage Pointer to the physical guest page tracking structure.
912 */
913#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
914
915/**
916 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
917 * virtual handlers.
918 * @returns true/false
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
922
923
924
925/**
926 * Checks if the page has any access handlers, including temporarily disabled ones.
927 * @returns true/false
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
931 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
932 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
933
934/**
935 * Checks if the page has any active access handlers.
936 * @returns true/false
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
940 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
941 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
942
943/**
944 * Checks if the page has any active access handlers catching all accesses.
945 * @returns true/false
946 * @param pPage Pointer to the physical guest page tracking structure.
947 */
948#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
949 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
950 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
951
952
953/**
954 * Ram range for GC Phys to HC Phys conversion.
955 *
956 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
957 * conversions too, but we'll let MM handle that for now.
958 *
959 * This structure is used by linked lists in both GC and HC.
960 */
961typedef struct PGMRAMRANGE
962{
963 /** Pointer to the next RAM range - for R3. */
964 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
965 /** Pointer to the next RAM range - for R0. */
966 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
967 /** Pointer to the next RAM range - for RC. */
968 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
969 /** Pointer alignment. */
970 RTRCPTR RCPtrAlignment;
971 /** Start of the range. Page aligned. */
972 RTGCPHYS GCPhys;
973 /** Last address in the range (inclusive). Page aligned (-1). */
974 RTGCPHYS GCPhysLast;
975 /** Size of the range. (Page aligned of course). */
976 RTGCPHYS cb;
977 /** MM_RAM_* flags */
978 uint32_t fFlags;
979 uint32_t u32Alignment; /**< alignment. */
980#ifndef VBOX_WITH_NEW_PHYS_CODE
981 /** R3 virtual lookup ranges for chunks.
982 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
983 * @remarks This is occationally accessed from ring-0!! (not darwin) */
984# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
986# else
987 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
988# endif
989#endif
990 /** Start of the HC mapping of the range. This is only used for MMIO2. */
991 R3PTRTYPE(void *) pvR3;
992 /** The range description. */
993 R3PTRTYPE(const char *) pszDesc;
994
995 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
996#ifdef VBOX_WITH_NEW_PHYS_CODE
997 uint32_t au32Reserved[2];
998#elif HC_ARCH_BITS == 32
999 uint32_t au32Reserved[1];
1000#endif
1001
1002 /** Array of physical guest page tracking structures. */
1003 PGMPAGE aPages[1];
1004} PGMRAMRANGE;
1005/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1006typedef PGMRAMRANGE *PPGMRAMRANGE;
1007
1008/** Return hc ptr corresponding to the ram range and physical offset */
1009#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1010 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1011 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1012
1013/**
1014 * Per page tracking structure for ROM image.
1015 *
1016 * A ROM image may have a shadow page, in which case we may have
1017 * two pages backing it. This structure contains the PGMPAGE for
1018 * both while PGMRAMRANGE have a copy of the active one. It is
1019 * important that these aren't out of sync in any regard other
1020 * than page pool tracking data.
1021 */
1022typedef struct PGMROMPAGE
1023{
1024 /** The page structure for the virgin ROM page. */
1025 PGMPAGE Virgin;
1026 /** The page structure for the shadow RAM page. */
1027 PGMPAGE Shadow;
1028 /** The current protection setting. */
1029 PGMROMPROT enmProt;
1030 /** Pad the structure size to a multiple of 8. */
1031 uint32_t u32Padding;
1032} PGMROMPAGE;
1033/** Pointer to a ROM page tracking structure. */
1034typedef PGMROMPAGE *PPGMROMPAGE;
1035
1036
1037/**
1038 * A registered ROM image.
1039 *
1040 * This is needed to keep track of ROM image since they generally
1041 * intrude into a PGMRAMRANGE. It also keeps track of additional
1042 * info like the two page sets (read-only virgin and read-write shadow),
1043 * the current state of each page.
1044 *
1045 * Because access handlers cannot easily be executed in a different
1046 * context, the ROM ranges needs to be accessible and in all contexts.
1047 */
1048typedef struct PGMROMRANGE
1049{
1050 /** Pointer to the next range - R3. */
1051 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1052 /** Pointer to the next range - R0. */
1053 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1054 /** Pointer to the next range - RC. */
1055 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1056 /** Pointer alignment */
1057 RTRCPTR GCPtrAlignment;
1058 /** Address of the range. */
1059 RTGCPHYS GCPhys;
1060 /** Address of the last byte in the range. */
1061 RTGCPHYS GCPhysLast;
1062 /** Size of the range. */
1063 RTGCPHYS cb;
1064 /** The flags (PGMPHYS_ROM_FLAG_*). */
1065 uint32_t fFlags;
1066 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1067 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1068 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1069 * This is used for strictness checks. */
1070 R3PTRTYPE(const void *) pvOriginal;
1071 /** The ROM description. */
1072 R3PTRTYPE(const char *) pszDesc;
1073 /** The per page tracking structures. */
1074 PGMROMPAGE aPages[1];
1075} PGMROMRANGE;
1076/** Pointer to a ROM range. */
1077typedef PGMROMRANGE *PPGMROMRANGE;
1078
1079
1080/**
1081 * A registered MMIO2 (= Device RAM) range.
1082 *
1083 * There are a few reason why we need to keep track of these
1084 * registrations. One of them is the deregistration & cleanup
1085 * stuff, while another is that the PGMRAMRANGE associated with
1086 * such a region may have to be removed from the ram range list.
1087 *
1088 * Overlapping with a RAM range has to be 100% or none at all. The
1089 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1090 * meditation will be raised if a partial overlap or an overlap of
1091 * ROM pages is encountered. On an overlap we will free all the
1092 * existing RAM pages and put in the ram range pages instead.
1093 */
1094typedef struct PGMMMIO2RANGE
1095{
1096 /** The owner of the range. (a device) */
1097 PPDMDEVINSR3 pDevInsR3;
1098 /** Pointer to the ring-3 mapping of the allocation. */
1099 RTR3PTR pvR3;
1100 /** Pointer to the next range - R3. */
1101 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1102 /** Whether it's mapped or not. */
1103 bool fMapped;
1104 /** Whether it's overlapping or not. */
1105 bool fOverlapping;
1106 /** The PCI region number.
1107 * @remarks This ASSUMES that nobody will ever really need to have multiple
1108 * PCI devices with matching MMIO region numbers on a single device. */
1109 uint8_t iRegion;
1110 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1111 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1112 /** The associated RAM range. */
1113 PGMRAMRANGE RamRange;
1114} PGMMMIO2RANGE;
1115/** Pointer to a MMIO2 range. */
1116typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1117
1118
1119
1120
1121/**
1122 * PGMPhysRead/Write cache entry
1123 */
1124typedef struct PGMPHYSCACHEENTRY
1125{
1126 /** R3 pointer to physical page. */
1127 R3PTRTYPE(uint8_t *) pbR3;
1128 /** GC Physical address for cache entry */
1129 RTGCPHYS GCPhys;
1130#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1131 RTGCPHYS u32Padding0; /**< alignment padding. */
1132#endif
1133} PGMPHYSCACHEENTRY;
1134
1135/**
1136 * PGMPhysRead/Write cache to reduce REM memory access overhead
1137 */
1138typedef struct PGMPHYSCACHE
1139{
1140 /** Bitmap of valid cache entries */
1141 uint64_t aEntries;
1142 /** Cache entries */
1143 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1144} PGMPHYSCACHE;
1145
1146
1147/** Pointer to an allocation chunk ring-3 mapping. */
1148typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1149/** Pointer to an allocation chunk ring-3 mapping pointer. */
1150typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1151
1152/**
1153 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1154 *
1155 * The primary tree (Core) uses the chunk id as key.
1156 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1157 */
1158typedef struct PGMCHUNKR3MAP
1159{
1160 /** The key is the chunk id. */
1161 AVLU32NODECORE Core;
1162 /** The key is the ageing sequence number. */
1163 AVLLU32NODECORE AgeCore;
1164 /** The current age thingy. */
1165 uint32_t iAge;
1166 /** The current reference count. */
1167 uint32_t volatile cRefs;
1168 /** The current permanent reference count. */
1169 uint32_t volatile cPermRefs;
1170 /** The mapping address. */
1171 void *pv;
1172} PGMCHUNKR3MAP;
1173
1174/**
1175 * Allocation chunk ring-3 mapping TLB entry.
1176 */
1177typedef struct PGMCHUNKR3MAPTLBE
1178{
1179 /** The chunk id. */
1180 uint32_t volatile idChunk;
1181#if HC_ARCH_BITS == 64
1182 uint32_t u32Padding; /**< alignment padding. */
1183#endif
1184 /** The chunk map. */
1185#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1186 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1187#else
1188 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1189#endif
1190} PGMCHUNKR3MAPTLBE;
1191/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1192typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1193
1194/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1195 * @remark Must be a power of two value. */
1196#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1197
1198/**
1199 * Allocation chunk ring-3 mapping TLB.
1200 *
1201 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1202 * At first glance this might look kinda odd since AVL trees are
1203 * supposed to give the most optimial lookup times of all trees
1204 * due to their balancing. However, take a tree with 1023 nodes
1205 * in it, that's 10 levels, meaning that most searches has to go
1206 * down 9 levels before they find what they want. This isn't fast
1207 * compared to a TLB hit. There is the factor of cache misses,
1208 * and of course the problem with trees and branch prediction.
1209 * This is why we use TLBs in front of most of the trees.
1210 *
1211 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1212 * difficult when we switch to the new inlined AVL trees (from kStuff).
1213 */
1214typedef struct PGMCHUNKR3MAPTLB
1215{
1216 /** The TLB entries. */
1217 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1218} PGMCHUNKR3MAPTLB;
1219
1220/**
1221 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1222 * @returns Chunk TLB index.
1223 * @param idChunk The Chunk ID.
1224 */
1225#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1226
1227
1228/**
1229 * Ring-3 guest page mapping TLB entry.
1230 * @remarks used in ring-0 as well at the moment.
1231 */
1232typedef struct PGMPAGER3MAPTLBE
1233{
1234 /** Address of the page. */
1235 RTGCPHYS volatile GCPhys;
1236 /** The guest page. */
1237#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1238 R3PTRTYPE(PPGMPAGE) volatile pPage;
1239#else
1240 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1241#endif
1242 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1243#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1244 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1245#else
1246 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1247#endif
1248 /** The address */
1249#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250 R3PTRTYPE(void *) volatile pv;
1251#else
1252 R3R0PTRTYPE(void *) volatile pv;
1253#endif
1254#if HC_ARCH_BITS == 32
1255 uint32_t u32Padding; /**< alignment padding. */
1256#endif
1257} PGMPAGER3MAPTLBE;
1258/** Pointer to an entry in the HC physical TLB. */
1259typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1260
1261
1262/** The number of entries in the ring-3 guest page mapping TLB.
1263 * @remarks The value must be a power of two. */
1264#define PGM_PAGER3MAPTLB_ENTRIES 64
1265
1266/**
1267 * Ring-3 guest page mapping TLB.
1268 * @remarks used in ring-0 as well at the moment.
1269 */
1270typedef struct PGMPAGER3MAPTLB
1271{
1272 /** The TLB entries. */
1273 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1274} PGMPAGER3MAPTLB;
1275/** Pointer to the ring-3 guest page mapping TLB. */
1276typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1277
1278/**
1279 * Calculates the index of the TLB entry for the specified guest page.
1280 * @returns Physical TLB index.
1281 * @param GCPhys The guest physical address.
1282 */
1283#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1284
1285
1286/**
1287 * Mapping cache usage set entry.
1288 *
1289 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1290 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1291 * cache. If it's extended to include ring-3, well, then something will
1292 * have be changed here...
1293 */
1294typedef struct PGMMAPSETENTRY
1295{
1296 /** The mapping cache index. */
1297 uint16_t iPage;
1298 /** The number of references.
1299 * The max is UINT16_MAX - 1. */
1300 uint16_t cRefs;
1301 /** Pointer to the page. */
1302 RTR0PTR pvPage;
1303 /** The physical address for this entry. */
1304 RTHCPHYS HCPhys;
1305} PGMMAPSETENTRY;
1306/** Pointer to a mapping cache usage set entry. */
1307typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1308
1309/**
1310 * Mapping cache usage set.
1311 *
1312 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1313 * done during exits / traps. The set is
1314 */
1315typedef struct PGMMAPSET
1316{
1317 /** The index of the current CPU, only valid if the set is open. */
1318 int32_t iCpu;
1319 /** The number of occupied.
1320 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1321 * dynamic mappings. */
1322 uint32_t cEntries;
1323 /** The entries. */
1324 PGMMAPSETENTRY aEntries[32];
1325 /** HCPhys -> iEntry fast lookup table.
1326 * Use PGMMAPSET_HASH for hashing.
1327 * The entries may or may not be valid, check against cEntries. */
1328 uint8_t aiHashTable[64];
1329} PGMMAPSET;
1330/** Pointer to the mapping cache set. */
1331typedef PGMMAPSET *PPGMMAPSET;
1332
1333/** PGMMAPSET::cEntries value for a closed set. */
1334#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1335
1336/** Hash function for aiHashTable. */
1337#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 63)
1338
1339
1340/** @name Context neutrual page mapper TLB.
1341 *
1342 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1343 * code is writting in a kind of context neutrual way. Time will show whether
1344 * this actually makes sense or not...
1345 *
1346 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1347 * context ends up using a global mapping cache on some platforms
1348 * (darwin).
1349 *
1350 * @{ */
1351/** @typedef PPGMPAGEMAPTLB
1352 * The page mapper TLB pointer type for the current context. */
1353/** @typedef PPGMPAGEMAPTLB
1354 * The page mapper TLB entry pointer type for the current context. */
1355/** @typedef PPGMPAGEMAPTLB
1356 * The page mapper TLB entry pointer pointer type for the current context. */
1357/** @def PGM_PAGEMAPTLB_ENTRIES
1358 * The number of TLB entries in the page mapper TLB for the current context. */
1359/** @def PGM_PAGEMAPTLB_IDX
1360 * Calculate the TLB index for a guest physical address.
1361 * @returns The TLB index.
1362 * @param GCPhys The guest physical address. */
1363/** @typedef PPGMPAGEMAP
1364 * Pointer to a page mapper unit for current context. */
1365/** @typedef PPPGMPAGEMAP
1366 * Pointer to a page mapper unit pointer for current context. */
1367#ifdef IN_RC
1368// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1369// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1370// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1371# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1372# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1373 typedef void * PPGMPAGEMAP;
1374 typedef void ** PPPGMPAGEMAP;
1375//#elif IN_RING0
1376// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1377// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1378// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1379//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1380//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1381// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1382// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1383#else
1384 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1385 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1386 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1387# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1388# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1389 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1390 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1391#endif
1392/** @} */
1393
1394
1395/** @name PGM Pool Indexes.
1396 * Aka. the unique shadow page identifier.
1397 * @{ */
1398/** NIL page pool IDX. */
1399#define NIL_PGMPOOL_IDX 0
1400/** The first normal index. */
1401#define PGMPOOL_IDX_FIRST_SPECIAL 1
1402/** Page directory (32-bit root). */
1403#define PGMPOOL_IDX_PD 1
1404#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1405/** Page directory (32-bit root). */
1406#define PGMPOOL_IDX_PD 1
1407/** Page Directory Pointer Table (PAE root). */
1408#define PGMPOOL_IDX_PDPT 2
1409/** AMD64 CR3 level index.*/
1410#define PGMPOOL_IDX_AMD64_CR3 3
1411/** Nested paging root.*/
1412#define PGMPOOL_IDX_NESTED_ROOT 4
1413/** The first normal index. */
1414#define PGMPOOL_IDX_FIRST 5
1415#else
1416/** The extended PAE page directory (2048 entries, works as root currently). */
1417#define PGMPOOL_IDX_PAE_PD 2
1418/** PAE Page Directory Table 0. */
1419#define PGMPOOL_IDX_PAE_PD_0 3
1420/** PAE Page Directory Table 1. */
1421#define PGMPOOL_IDX_PAE_PD_1 4
1422/** PAE Page Directory Table 2. */
1423#define PGMPOOL_IDX_PAE_PD_2 5
1424/** PAE Page Directory Table 3. */
1425#define PGMPOOL_IDX_PAE_PD_3 6
1426/** Page Directory Pointer Table (PAE root, not currently used). */
1427#define PGMPOOL_IDX_PDPT 7
1428/** AMD64 CR3 level index.*/
1429#define PGMPOOL_IDX_AMD64_CR3 8
1430/** Nested paging root.*/
1431#define PGMPOOL_IDX_NESTED_ROOT 9
1432/** The first normal index. */
1433#define PGMPOOL_IDX_FIRST 10
1434#endif
1435/** The last valid index. (inclusive, 14 bits) */
1436#define PGMPOOL_IDX_LAST 0x3fff
1437/** @} */
1438
1439/** The NIL index for the parent chain. */
1440#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1441
1442/**
1443 * Node in the chain linking a shadowed page to it's parent (user).
1444 */
1445#pragma pack(1)
1446typedef struct PGMPOOLUSER
1447{
1448 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1449 uint16_t iNext;
1450 /** The user page index. */
1451 uint16_t iUser;
1452 /** Index into the user table. */
1453 uint32_t iUserTable;
1454} PGMPOOLUSER, *PPGMPOOLUSER;
1455typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1456#pragma pack()
1457
1458
1459/** The NIL index for the phys ext chain. */
1460#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1461
1462/**
1463 * Node in the chain of physical cross reference extents.
1464 */
1465#pragma pack(1)
1466typedef struct PGMPOOLPHYSEXT
1467{
1468 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1469 uint16_t iNext;
1470 /** The user page index. */
1471 uint16_t aidx[3];
1472} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1473typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1474#pragma pack()
1475
1476
1477/**
1478 * The kind of page that's being shadowed.
1479 */
1480typedef enum PGMPOOLKIND
1481{
1482 /** The virtual invalid 0 entry. */
1483 PGMPOOLKIND_INVALID = 0,
1484 /** The entry is free (=unused). */
1485 PGMPOOLKIND_FREE,
1486
1487 /** Shw: 32-bit page table; Gst: no paging */
1488 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1489 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1490 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1491 /** Shw: 32-bit page table; Gst: 4MB page. */
1492 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1493 /** Shw: PAE page table; Gst: no paging */
1494 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1495 /** Shw: PAE page table; Gst: 32-bit page table. */
1496 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1497 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1498 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1499 /** Shw: PAE page table; Gst: PAE page table. */
1500 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1501 /** Shw: PAE page table; Gst: 2MB page. */
1502 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1503
1504 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1505 PGMPOOLKIND_32BIT_PD,
1506 /** Shw: 32-bit page directory. Gst: real mode. */
1507 PGMPOOLKIND_32BIT_PD_PHYS_REAL,
1508 /** Shw: 32-bit page directory. Gst: protected mode without paging. */
1509 PGMPOOLKIND_32BIT_PD_PHYS_PROT,
1510 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1511 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1512 /** Shw: PAE page directory; Gst: PAE page directory. */
1513 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1514 /** Shw: PAE page directory; Gst: real mode. */
1515 PGMPOOLKIND_PAE_PD_PHYS_REAL,
1516 /** Shw: PAE page directory; Gst: protected mode without paging. */
1517 PGMPOOLKIND_PAE_PD_PHYS_PROT,
1518
1519 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1520 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1521 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1522 PGMPOOLKIND_PAE_PDPT,
1523
1524 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1525 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1526 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1527 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1528 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1529 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1530 /** Shw: 64-bit page directory table; Gst: no paging */
1531 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1532
1533 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1534 PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1535
1536 /** Shw: EPT page directory pointer table; Gst: no paging */
1537 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1538 /** Shw: EPT page directory table; Gst: no paging */
1539 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1540 /** Shw: EPT page table; Gst: no paging */
1541 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1542
1543#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1544 /** Shw: Root 32-bit page directory. */
1545 PGMPOOLKIND_ROOT_32BIT_PD,
1546 /** Shw: Root PAE page directory */
1547 PGMPOOLKIND_ROOT_PAE_PD,
1548 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1549 PGMPOOLKIND_ROOT_PDPT,
1550#endif
1551 /** Shw: Root Nested paging table. */
1552 PGMPOOLKIND_ROOT_NESTED,
1553
1554 /** The last valid entry. */
1555 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1556} PGMPOOLKIND;
1557
1558
1559/**
1560 * The tracking data for a page in the pool.
1561 */
1562typedef struct PGMPOOLPAGE
1563{
1564 /** AVL node code with the (R3) physical address of this page. */
1565 AVLOHCPHYSNODECORE Core;
1566 /** Pointer to the R3 mapping of the page. */
1567#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1568 R3PTRTYPE(void *) pvPageR3;
1569#else
1570 R3R0PTRTYPE(void *) pvPageR3;
1571#endif
1572 /** The guest physical address. */
1573#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1574 uint32_t Alignment0;
1575#endif
1576 RTGCPHYS GCPhys;
1577 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1578 uint8_t enmKind;
1579 uint8_t bPadding;
1580 /** The index of this page. */
1581 uint16_t idx;
1582 /** The next entry in the list this page currently resides in.
1583 * It's either in the free list or in the GCPhys hash. */
1584 uint16_t iNext;
1585#ifdef PGMPOOL_WITH_USER_TRACKING
1586 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1587 uint16_t iUserHead;
1588 /** The number of present entries. */
1589 uint16_t cPresent;
1590 /** The first entry in the table which is present. */
1591 uint16_t iFirstPresent;
1592#endif
1593#ifdef PGMPOOL_WITH_MONITORING
1594 /** The number of modifications to the monitored page. */
1595 uint16_t cModifications;
1596 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1597 uint16_t iModifiedNext;
1598 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1599 uint16_t iModifiedPrev;
1600 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1601 uint16_t iMonitoredNext;
1602 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1603 uint16_t iMonitoredPrev;
1604#endif
1605#ifdef PGMPOOL_WITH_CACHE
1606 /** The next page in the age list. */
1607 uint16_t iAgeNext;
1608 /** The previous page in the age list. */
1609 uint16_t iAgePrev;
1610#endif /* PGMPOOL_WITH_CACHE */
1611 /** Used to indicate that the page is zeroed. */
1612 bool fZeroed;
1613 /** Used to indicate that a PT has non-global entries. */
1614 bool fSeenNonGlobal;
1615 /** Used to indicate that we're monitoring writes to the guest page. */
1616 bool fMonitored;
1617 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1618 * (All pages are in the age list.) */
1619 bool fCached;
1620 /** This is used by the R3 access handlers when invoked by an async thread.
1621 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1622 bool volatile fReusedFlushPending;
1623 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1624 * In these cases the access handler acts differently and will check
1625 * for mapping conflicts like the normal CR3 handler.
1626 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1627 * replaced by a list of pages which share access handler.
1628 */
1629 bool fCR3Mix;
1630} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1631
1632
1633#ifdef PGMPOOL_WITH_CACHE
1634/** The hash table size. */
1635# define PGMPOOL_HASH_SIZE 0x40
1636/** The hash function. */
1637# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1638#endif
1639
1640
1641/**
1642 * The shadow page pool instance data.
1643 *
1644 * It's all one big allocation made at init time, except for the
1645 * pages that is. The user nodes follows immediatly after the
1646 * page structures.
1647 */
1648typedef struct PGMPOOL
1649{
1650 /** The VM handle - R3 Ptr. */
1651 PVMR3 pVMR3;
1652 /** The VM handle - R0 Ptr. */
1653 PVMR0 pVMR0;
1654 /** The VM handle - RC Ptr. */
1655 PVMRC pVMRC;
1656 /** The max pool size. This includes the special IDs. */
1657 uint16_t cMaxPages;
1658 /** The current pool size. */
1659 uint16_t cCurPages;
1660 /** The head of the free page list. */
1661 uint16_t iFreeHead;
1662 /* Padding. */
1663 uint16_t u16Padding;
1664#ifdef PGMPOOL_WITH_USER_TRACKING
1665 /** Head of the chain of free user nodes. */
1666 uint16_t iUserFreeHead;
1667 /** The number of user nodes we've allocated. */
1668 uint16_t cMaxUsers;
1669 /** The number of present page table entries in the entire pool. */
1670 uint32_t cPresent;
1671 /** Pointer to the array of user nodes - RC pointer. */
1672 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1673 /** Pointer to the array of user nodes - R3 pointer. */
1674 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1675 /** Pointer to the array of user nodes - R0 pointer. */
1676 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1677#endif /* PGMPOOL_WITH_USER_TRACKING */
1678#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1679 /** Head of the chain of free phys ext nodes. */
1680 uint16_t iPhysExtFreeHead;
1681 /** The number of user nodes we've allocated. */
1682 uint16_t cMaxPhysExts;
1683 /** Pointer to the array of physical xref extent - RC pointer. */
1684 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1685 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1686 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1687 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1688 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1689#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1690#ifdef PGMPOOL_WITH_CACHE
1691 /** Hash table for GCPhys addresses. */
1692 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1693 /** The head of the age list. */
1694 uint16_t iAgeHead;
1695 /** The tail of the age list. */
1696 uint16_t iAgeTail;
1697 /** Set if the cache is enabled. */
1698 bool fCacheEnabled;
1699#endif /* PGMPOOL_WITH_CACHE */
1700#ifdef PGMPOOL_WITH_MONITORING
1701 /** Head of the list of modified pages. */
1702 uint16_t iModifiedHead;
1703 /** The current number of modified pages. */
1704 uint16_t cModifiedPages;
1705 /** Access handler, RC. */
1706 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1707 /** Access handler, R0. */
1708 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1709 /** Access handler, R3. */
1710 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1711 /** The access handler description (HC ptr). */
1712 R3PTRTYPE(const char *) pszAccessHandler;
1713#endif /* PGMPOOL_WITH_MONITORING */
1714 /** The number of pages currently in use. */
1715 uint16_t cUsedPages;
1716#ifdef VBOX_WITH_STATISTICS
1717 /** The high wather mark for cUsedPages. */
1718 uint16_t cUsedPagesHigh;
1719 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1720 /** Profiling pgmPoolAlloc(). */
1721 STAMPROFILEADV StatAlloc;
1722 /** Profiling pgmPoolClearAll(). */
1723 STAMPROFILE StatClearAll;
1724 /** Profiling pgmPoolFlushAllInt(). */
1725 STAMPROFILE StatFlushAllInt;
1726 /** Profiling pgmPoolFlushPage(). */
1727 STAMPROFILE StatFlushPage;
1728 /** Profiling pgmPoolFree(). */
1729 STAMPROFILE StatFree;
1730 /** Profiling time spent zeroing pages. */
1731 STAMPROFILE StatZeroPage;
1732# ifdef PGMPOOL_WITH_USER_TRACKING
1733 /** Profiling of pgmPoolTrackDeref. */
1734 STAMPROFILE StatTrackDeref;
1735 /** Profiling pgmTrackFlushGCPhysPT. */
1736 STAMPROFILE StatTrackFlushGCPhysPT;
1737 /** Profiling pgmTrackFlushGCPhysPTs. */
1738 STAMPROFILE StatTrackFlushGCPhysPTs;
1739 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1740 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1741 /** Number of times we've been out of user records. */
1742 STAMCOUNTER StatTrackFreeUpOneUser;
1743# endif
1744# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1745 /** Profiling deref activity related tracking GC physical pages. */
1746 STAMPROFILE StatTrackDerefGCPhys;
1747 /** Number of linear searches for a HCPhys in the ram ranges. */
1748 STAMCOUNTER StatTrackLinearRamSearches;
1749 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1750 STAMCOUNTER StamTrackPhysExtAllocFailures;
1751# endif
1752# ifdef PGMPOOL_WITH_MONITORING
1753 /** Profiling the RC/R0 access handler. */
1754 STAMPROFILE StatMonitorRZ;
1755 /** Times we've failed interpreting the instruction. */
1756 STAMCOUNTER StatMonitorRZEmulateInstr;
1757 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1758 STAMPROFILE StatMonitorRZFlushPage;
1759 /** Times we've detected fork(). */
1760 STAMCOUNTER StatMonitorRZFork;
1761 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1762 STAMPROFILE StatMonitorRZHandled;
1763 /** Times we've failed interpreting a patch code instruction. */
1764 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1765 /** Times we've failed interpreting a patch code instruction during flushing. */
1766 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1767 /** The number of times we've seen rep prefixes we can't handle. */
1768 STAMCOUNTER StatMonitorRZRepPrefix;
1769 /** Profiling the REP STOSD cases we've handled. */
1770 STAMPROFILE StatMonitorRZRepStosd;
1771
1772 /** Profiling the R3 access handler. */
1773 STAMPROFILE StatMonitorR3;
1774 /** Times we've failed interpreting the instruction. */
1775 STAMCOUNTER StatMonitorR3EmulateInstr;
1776 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1777 STAMPROFILE StatMonitorR3FlushPage;
1778 /** Times we've detected fork(). */
1779 STAMCOUNTER StatMonitorR3Fork;
1780 /** Profiling the R3 access we've handled (except REP STOSD). */
1781 STAMPROFILE StatMonitorR3Handled;
1782 /** The number of times we've seen rep prefixes we can't handle. */
1783 STAMCOUNTER StatMonitorR3RepPrefix;
1784 /** Profiling the REP STOSD cases we've handled. */
1785 STAMPROFILE StatMonitorR3RepStosd;
1786 /** The number of times we're called in an async thread an need to flush. */
1787 STAMCOUNTER StatMonitorR3Async;
1788 /** The high wather mark for cModifiedPages. */
1789 uint16_t cModifiedPagesHigh;
1790 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1791# endif
1792# ifdef PGMPOOL_WITH_CACHE
1793 /** The number of cache hits. */
1794 STAMCOUNTER StatCacheHits;
1795 /** The number of cache misses. */
1796 STAMCOUNTER StatCacheMisses;
1797 /** The number of times we've got a conflict of 'kind' in the cache. */
1798 STAMCOUNTER StatCacheKindMismatches;
1799 /** Number of times we've been out of pages. */
1800 STAMCOUNTER StatCacheFreeUpOne;
1801 /** The number of cacheable allocations. */
1802 STAMCOUNTER StatCacheCacheable;
1803 /** The number of uncacheable allocations. */
1804 STAMCOUNTER StatCacheUncacheable;
1805# endif
1806#elif HC_ARCH_BITS == 64
1807 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1808#endif
1809 /** The AVL tree for looking up a page by its HC physical address. */
1810 AVLOHCPHYSTREE HCPhysTree;
1811 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1812 /** Array of pages. (cMaxPages in length)
1813 * The Id is the index into thist array.
1814 */
1815 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1816} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1817
1818
1819/** @def PGMPOOL_PAGE_2_PTR
1820 * Maps a pool page pool into the current context.
1821 *
1822 * @returns VBox status code.
1823 * @param pVM The VM handle.
1824 * @param pPage The pool page.
1825 *
1826 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1827 * small page window employeed by that function. Be careful.
1828 * @remark There is no need to assert on the result.
1829 */
1830#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1831# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1832#else
1833 DECLINLINE(R3R0PTRTYPE(void *)) PGMPOOL_PAGE_2_PTR(PVM pVM, PPGMPOOLPAGE pPage)
1834 {
1835 Assert(pPage->pvPageR3);
1836 return pPage->pvPageR3;
1837 }
1838#endif
1839
1840
1841/**
1842 * Trees are using self relative offsets as pointers.
1843 * So, all its data, including the root pointer, must be in the heap for HC and GC
1844 * to have the same layout.
1845 */
1846typedef struct PGMTREES
1847{
1848 /** Physical access handlers (AVL range+offsetptr tree). */
1849 AVLROGCPHYSTREE PhysHandlers;
1850 /** Virtual access handlers (AVL range + GC ptr tree). */
1851 AVLROGCPTRTREE VirtHandlers;
1852 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1853 AVLROGCPHYSTREE PhysToVirtHandlers;
1854 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1855 AVLROGCPTRTREE HyperVirtHandlers;
1856} PGMTREES;
1857/** Pointer to PGM trees. */
1858typedef PGMTREES *PPGMTREES;
1859
1860
1861/** @name Paging mode macros
1862 * @{ */
1863#ifdef IN_RC
1864# define PGM_CTX(a,b) a##RC##b
1865# define PGM_CTX_STR(a,b) a "GC" b
1866# define PGM_CTX_DECL(type) VMMRCDECL(type)
1867#else
1868# ifdef IN_RING3
1869# define PGM_CTX(a,b) a##R3##b
1870# define PGM_CTX_STR(a,b) a "R3" b
1871# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1872# else
1873# define PGM_CTX(a,b) a##R0##b
1874# define PGM_CTX_STR(a,b) a "R0" b
1875# define PGM_CTX_DECL(type) VMMDECL(type)
1876# endif
1877#endif
1878
1879#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1880#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1881#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1882#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1883#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1884#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1885#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1886#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1887#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1888#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1889#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1890#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1891#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1892#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1893#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1894#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1895#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1896
1897#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1898#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1899#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1900#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1901#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1902#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1903#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1904#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1905#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1906#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1907#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1908#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1909#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1910#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1911#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1912#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1913#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1914
1915/* Shw_Gst */
1916#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1917#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1918#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1919#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1920#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1921#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1922#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1923#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1924#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1925#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1926#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1927#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1928#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1929#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1930#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1931#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1932#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1933#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1934#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1935
1936#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1937#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1938#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1939#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1940#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1941#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1942#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1943#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1944#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1945#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1946#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1947#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1948#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1949#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1950#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1951#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1952#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1953#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1954#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1955#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1956#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1957#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1958#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1959#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1960#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1961#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1962#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1963#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1964#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1965#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1966#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1967#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1968#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1969#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1970#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1971#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1972#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1973
1974#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1975#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1976/** @} */
1977
1978/**
1979 * Data for each paging mode.
1980 */
1981typedef struct PGMMODEDATA
1982{
1983 /** The guest mode type. */
1984 uint32_t uGstType;
1985 /** The shadow mode type. */
1986 uint32_t uShwType;
1987
1988 /** @name Function pointers for Shadow paging.
1989 * @{
1990 */
1991 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
1992 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1993 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1994 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1995
1996 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1997 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1998
1999 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2000 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2001 /** @} */
2002
2003 /** @name Function pointers for Guest paging.
2004 * @{
2005 */
2006 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2007 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2008 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2009 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2010 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2011#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2012 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2013 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2014#endif
2015 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2016 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2017#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2018 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2019 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2020 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2021 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2022#endif
2023 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2024 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2025 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2026#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2027 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2028 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2029#endif
2030 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2031 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2032#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2033 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2034 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2035#endif
2036 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2037 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2038 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2039#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2040 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2041 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2042#endif
2043 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2044 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2045#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2046 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2047 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2048#endif
2049 /** @} */
2050
2051 /** @name Function pointers for Both Shadow and Guest paging.
2052 * @{
2053 */
2054 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2055 /* no pfnR3BthTrap0eHandler */
2056 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2057 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2058 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2059 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2060 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2061#ifdef VBOX_STRICT
2062 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2063#endif
2064
2065 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2066 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2067 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2068 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2069 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2070 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2071#ifdef VBOX_STRICT
2072 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2073#endif
2074
2075 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2076 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2077 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2078 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2079 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2080 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2081#ifdef VBOX_STRICT
2082 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2083#endif
2084 /** @} */
2085} PGMMODEDATA, *PPGMMODEDATA;
2086
2087
2088
2089/**
2090 * Converts a PGM pointer into a VM pointer.
2091 * @returns Pointer to the VM structure the PGM is part of.
2092 * @param pPGM Pointer to PGM instance data.
2093 */
2094#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2095
2096/**
2097 * PGM Data (part of VM)
2098 */
2099typedef struct PGM
2100{
2101 /** Offset to the VM structure. */
2102 RTINT offVM;
2103 /** Offset of the PGMCPU structure relative to VMCPU. */
2104 int32_t offVCpu;
2105 /** Alignment padding. */
2106 int32_t i32Alignment;
2107
2108 /*
2109 * This will be redefined at least two more times before we're done, I'm sure.
2110 * The current code is only to get on with the coding.
2111 * - 2004-06-10: initial version, bird.
2112 * - 2004-07-02: 1st time, bird.
2113 * - 2004-10-18: 2nd time, bird.
2114 * - 2005-07-xx: 3rd time, bird.
2115 */
2116
2117 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2118 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2119 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2120 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2121
2122 /** The host paging mode. (This is what SUPLib reports.) */
2123 SUPPAGINGMODE enmHostMode;
2124 /** The shadow paging mode. */
2125 PGMMODE enmShadowMode;
2126 /** The guest paging mode. */
2127 PGMMODE enmGuestMode;
2128
2129 /** The current physical address representing in the guest CR3 register. */
2130 RTGCPHYS GCPhysCR3;
2131 /** Pointer to the 5 page CR3 content mapping.
2132 * The first page is always the CR3 (in some form) while the 4 other pages
2133 * are used of the PDs in PAE mode. */
2134 RTGCPTR GCPtrCR3Mapping;
2135#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2136 uint32_t u32Alignment;
2137#endif
2138 /** The physical address of the currently monitored guest CR3 page.
2139 * When this value is NIL_RTGCPHYS no page is being monitored. */
2140 RTGCPHYS GCPhysGstCR3Monitored;
2141
2142 /** @name 32-bit Guest Paging.
2143 * @{ */
2144 /** The guest's page directory, R3 pointer. */
2145 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2146#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2147 /** The guest's page directory, R0 pointer. */
2148 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2149#endif
2150 /** The guest's page directory, static RC mapping. */
2151 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2152 /** @} */
2153
2154 /** @name PAE Guest Paging.
2155 * @{ */
2156 /** The guest's page directory pointer table, static RC mapping. */
2157 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2158 /** The guest's page directory pointer table, R3 pointer. */
2159 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2160#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2161 /** The guest's page directory pointer table, R0 pointer. */
2162 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2163#endif
2164
2165 /** The guest's page directories, R3 pointers.
2166 * These are individual pointers and don't have to be adjecent.
2167 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2168 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2169 /** The guest's page directories, R0 pointers.
2170 * Same restrictions as apGstPaePDsR3. */
2171#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2172 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2173#endif
2174 /** The guest's page directories, static GC mapping.
2175 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2176 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2177 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2178 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2179 RTGCPHYS aGCPhysGstPaePDs[4];
2180 /** The physical addresses of the monitored guest page directories (PAE). */
2181 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2182 /** @} */
2183
2184 /** @name AMD64 Guest Paging.
2185 * @{ */
2186 /** The guest's page directory pointer table, R3 pointer. */
2187 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2188#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2189 /** The guest's page directory pointer table, R0 pointer. */
2190 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2191#endif
2192 /** @} */
2193
2194 /** @name 32-bit Shadow Paging
2195 * @{ */
2196#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2197 /** The Physical Address (HC) of the current active shadow CR3. */
2198 RTHCPHYS HCPhysShwCR3;
2199 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2200 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2201 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2202 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2203 /** Pointer to the page of the current active CR3 - RC Ptr. */
2204 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2205# if HC_ARCH_BITS == 64
2206 RTRCPTR alignment6; /**< structure size alignment. */
2207# endif
2208#else
2209 /** The 32-Bit PD - R3 Ptr. */
2210 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2211 /** The 32-Bit PD - R0 Ptr. */
2212 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2213 /** The 32-Bit PD - RC Ptr. */
2214 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2215# if HC_ARCH_BITS == 64
2216 uint32_t u32Padding1; /**< alignment padding. */
2217# endif
2218 /** The Physical Address (HC) of the 32-Bit PD. */
2219 RTHCPHYS HCPhysShw32BitPD;
2220 /** @} */
2221
2222 /** @name PAE Shadow Paging
2223 * @{ */
2224 /** The four PDs for the low 4GB - R3 Ptr.
2225 * Even though these are 4 pointers, what they point at is a single table.
2226 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2227 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2228# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2229 /** The four PDs for the low 4GB - R0 Ptr.
2230 * Same kind of mapping as apHCPaePDs. */
2231 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2232# endif
2233 /** The four PDs for the low 4GB - RC Ptr.
2234 * Same kind of mapping as apHCPaePDs. */
2235 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2236 /** The Physical Address (HC) of the four PDs for the low 4GB.
2237 * These are *NOT* 4 contiguous pages. */
2238 RTHCPHYS aHCPhysPaePDs[4];
2239 /** The Physical Address (HC) of the PAE PDPT. */
2240 RTHCPHYS HCPhysShwPaePdpt;
2241 /** The PAE PDPT - R3 Ptr. */
2242 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2243 /** The PAE PDPT - R0 Ptr. */
2244 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2245 /** The PAE PDPT - RC Ptr. */
2246 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2247 /** @} */
2248# if HC_ARCH_BITS == 64
2249 RTRCPTR alignment5; /**< structure size alignment. */
2250# endif
2251
2252 /** @name AMD64 Shadow Paging
2253 * Extends PAE Paging.
2254 * @{ */
2255 /** The Page Map Level 4 table - R3 Ptr. */
2256 R3PTRTYPE(PX86PML4) pShwPaePml4R3;
2257# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2258 /** The Page Map Level 4 table - R0 Ptr. */
2259 R0PTRTYPE(PX86PML4) pShwPaePml4R0;
2260# endif
2261 /** The Physical Address (HC) of the Page Map Level 4 table. */
2262 RTHCPHYS HCPhysShwPaePml4;
2263 /** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
2264 R3PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R3;
2265 /** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
2266 R0PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R0;
2267 /** @}*/
2268
2269 /** @name Nested Shadow Paging
2270 * @{ */
2271 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2272 RTR3PTR pShwNestedRootR3;
2273# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2274 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2275 RTR0PTR pShwNestedRootR0;
2276# endif
2277 /** The Physical Address (HC) of the nested paging root. */
2278 RTHCPHYS HCPhysShwNestedRoot;
2279#endif
2280 /** @} */
2281
2282 /** @name Function pointers for Shadow paging.
2283 * @{
2284 */
2285 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2286 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2287 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2288 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2289
2290 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2291 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2292
2293 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2294 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2295
2296 /** @} */
2297
2298 /** @name Function pointers for Guest paging.
2299 * @{
2300 */
2301 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2302 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2303 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2304 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2305 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2306#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2307 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2308 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2309#endif
2310 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2311 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2312#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2313 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2314 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2315 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2316 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2317#endif
2318 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2319 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2320 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2321#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2322 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2323 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2324#endif
2325 DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2326 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2327#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2328 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2329 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2330#endif
2331#if HC_ARCH_BITS == 64
2332 RTRCPTR alignment3; /**< structure size alignment. */
2333#endif
2334
2335 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2336 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2337 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2338#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2339 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2340 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2341#endif
2342 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2343 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2344#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2345 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2346 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2347#endif
2348 /** @} */
2349
2350 /** @name Function pointers for Both Shadow and Guest paging.
2351 * @{
2352 */
2353 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2354 /* no pfnR3BthTrap0eHandler */
2355 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2356 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2357 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2358 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2359 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2360 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2361
2362 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2363 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2364 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2365 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2366 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2367 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2368 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2369
2370 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2371 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2372 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2373 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2374 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2375 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2376 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2377#if HC_ARCH_BITS == 64
2378 RTRCPTR alignment2; /**< structure size alignment. */
2379#endif
2380 /** @} */
2381
2382 /** Pointer to SHW+GST mode data (function pointers).
2383 * The index into this table is made up from */
2384 R3PTRTYPE(PPGMMODEDATA) paModeData;
2385
2386 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2387 * This is sorted by physical address and contains no overlapping ranges. */
2388 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2389 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2390 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2391 /** RC pointer corresponding to PGM::pRamRangesR3. */
2392 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2393 /** The configured RAM size. */
2394 RTUINT cbRamSize;
2395
2396 /** Pointer to the list of ROM ranges - for R3.
2397 * This is sorted by physical address and contains no overlapping ranges. */
2398 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2399 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2400 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2401 /** RC pointer corresponding to PGM::pRomRangesR3. */
2402 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2403 /** Alignment padding. */
2404 RTRCPTR GCPtrPadding2;
2405
2406 /** Pointer to the list of MMIO2 ranges - for R3.
2407 * Registration order. */
2408 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2409
2410 /** PGM offset based trees - R3 Ptr. */
2411 R3PTRTYPE(PPGMTREES) pTreesR3;
2412 /** PGM offset based trees - R0 Ptr. */
2413 R0PTRTYPE(PPGMTREES) pTreesR0;
2414 /** PGM offset based trees - RC Ptr. */
2415 RCPTRTYPE(PPGMTREES) pTreesRC;
2416
2417 /** Linked list of GC mappings - for RC.
2418 * The list is sorted ascending on address.
2419 */
2420 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2421 /** Linked list of GC mappings - for HC.
2422 * The list is sorted ascending on address.
2423 */
2424 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2425 /** Linked list of GC mappings - for R0.
2426 * The list is sorted ascending on address.
2427 */
2428 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2429
2430 /** If set no conflict checks are required. (boolean) */
2431 bool fMappingsFixed;
2432 /** If set, then no mappings are put into the shadow page table. (boolean) */
2433 bool fDisableMappings;
2434 /** Size of fixed mapping */
2435 uint32_t cbMappingFixed;
2436 /** Base address (GC) of fixed mapping */
2437 RTGCPTR GCPtrMappingFixed;
2438#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2439 uint32_t u32Padding0; /**< alignment padding. */
2440#endif
2441
2442
2443 /** @name Intermediate Context
2444 * @{ */
2445 /** Pointer to the intermediate page directory - Normal. */
2446 R3PTRTYPE(PX86PD) pInterPD;
2447 /** Pointer to the intermedate page tables - Normal.
2448 * There are two page tables, one for the identity mapping and one for
2449 * the host context mapping (of the core code). */
2450 R3PTRTYPE(PX86PT) apInterPTs[2];
2451 /** Pointer to the intermedate page tables - PAE. */
2452 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2453 /** Pointer to the intermedate page directory - PAE. */
2454 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2455 /** Pointer to the intermedate page directory - PAE. */
2456 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2457 /** Pointer to the intermedate page-map level 4 - AMD64. */
2458 R3PTRTYPE(PX86PML4) pInterPaePML4;
2459 /** Pointer to the intermedate page directory - AMD64. */
2460 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2461 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2462 RTHCPHYS HCPhysInterPD;
2463 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2464 RTHCPHYS HCPhysInterPaePDPT;
2465 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2466 RTHCPHYS HCPhysInterPaePML4;
2467 /** @} */
2468
2469 /** Base address of the dynamic page mapping area.
2470 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2471 */
2472 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2473 /** The index of the last entry used in the dynamic page mapping area. */
2474 RTUINT iDynPageMapLast;
2475 /** Cache containing the last entries in the dynamic page mapping area.
2476 * The cache size is covering half of the mapping area. */
2477 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2478
2479 /** The address of the ring-0 mapping cache if we're making use of it. */
2480 RTR0PTR pvR0DynMapUsed;
2481#if HC_ARCH_BITS == 32
2482 RTR0PTR R0PtrPadding0; /**< Alignment. */
2483#endif
2484
2485
2486 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2487 RTGCPHYS GCPhys4MBPSEMask;
2488
2489 /** A20 gate mask.
2490 * Our current approach to A20 emulation is to let REM do it and don't bother
2491 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2492 * But whould need arrise, we'll subject physical addresses to this mask. */
2493 RTGCPHYS GCPhysA20Mask;
2494 /** A20 gate state - boolean! */
2495 RTUINT fA20Enabled;
2496
2497 /** What needs syncing (PGM_SYNC_*).
2498 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2499 * PGMFlushTLB, and PGMR3Load. */
2500 RTUINT fSyncFlags;
2501
2502 /** PGM critical section.
2503 * This protects the physical & virtual access handlers, ram ranges,
2504 * and the page flag updating (some of it anyway).
2505 */
2506 PDMCRITSECT CritSect;
2507
2508 /** Shadow Page Pool - R3 Ptr. */
2509 R3PTRTYPE(PPGMPOOL) pPoolR3;
2510 /** Shadow Page Pool - R0 Ptr. */
2511 R0PTRTYPE(PPGMPOOL) pPoolR0;
2512 /** Shadow Page Pool - RC Ptr. */
2513 RCPTRTYPE(PPGMPOOL) pPoolRC;
2514
2515 /** We're not in a state which permits writes to guest memory.
2516 * (Only used in strict builds.) */
2517 bool fNoMorePhysWrites;
2518
2519 /** Flush the cache on the next access. */
2520 bool fPhysCacheFlushPending;
2521/** @todo r=bird: Fix member names!*/
2522 /** PGMPhysRead cache */
2523 PGMPHYSCACHE pgmphysreadcache;
2524 /** PGMPhysWrite cache */
2525 PGMPHYSCACHE pgmphyswritecache;
2526
2527 /**
2528 * Data associated with managing the ring-3 mappings of the allocation chunks.
2529 */
2530 struct
2531 {
2532 /** The chunk tree, ordered by chunk id. */
2533#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2534 R3PTRTYPE(PAVLU32NODECORE) pTree;
2535#else
2536 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2537#endif
2538 /** The chunk mapping TLB. */
2539 PGMCHUNKR3MAPTLB Tlb;
2540 /** The number of mapped chunks. */
2541 uint32_t c;
2542 /** The maximum number of mapped chunks.
2543 * @cfgm PGM/MaxRing3Chunks */
2544 uint32_t cMax;
2545 /** The chunk age tree, ordered by ageing sequence number. */
2546 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2547 /** The current time. */
2548 uint32_t iNow;
2549 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2550 uint32_t AgeingCountdown;
2551 } ChunkR3Map;
2552
2553 /**
2554 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2555 */
2556 PGMPAGER3MAPTLB PhysTlbHC;
2557
2558 /** @name The zero page.
2559 * @{ */
2560 /** The host physical address of the zero page. */
2561 RTHCPHYS HCPhysZeroPg;
2562 /** The ring-3 mapping of the zero page. */
2563 RTR3PTR pvZeroPgR3;
2564 /** The ring-0 mapping of the zero page. */
2565 RTR0PTR pvZeroPgR0;
2566 /** The GC mapping of the zero page. */
2567 RTGCPTR pvZeroPgGC;
2568#if GC_ARCH_BITS != 32
2569 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2570#endif
2571 /** @}*/
2572
2573 /** The number of handy pages. */
2574 uint32_t cHandyPages;
2575 /**
2576 * Array of handy pages.
2577 *
2578 * This array is used in a two way communication between pgmPhysAllocPage
2579 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2580 * an intermediary.
2581 *
2582 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2583 * (The current size of 32 pages, means 128 KB of handy memory.)
2584 */
2585 GMMPAGEDESC aHandyPages[32];
2586
2587 /** @name Release Statistics
2588 * @{ */
2589 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2590 uint32_t cPrivatePages; /**< The number of private pages. */
2591 uint32_t cSharedPages; /**< The number of shared pages. */
2592 uint32_t cZeroPages; /**< The number of zero backed pages. */
2593 /** The number of times the guest has switched mode since last reset or statistics reset. */
2594 STAMCOUNTER cGuestModeChanges;
2595 /** @} */
2596
2597#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2598 /** RC: Which statistic this \#PF should be attributed to. */
2599 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2600 RTRCPTR padding0;
2601 /** R0: Which statistic this \#PF should be attributed to. */
2602 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2603 RTR0PTR padding1;
2604
2605 /* Common */
2606# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2607 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2608 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2609 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2610 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2611 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2612 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2613# endif
2614 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2615 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2616
2617 /* R3 only: */
2618 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2619 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2620 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2621 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2622 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2623 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2624
2625 /* R0 only: */
2626 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2627 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2628 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2629 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2630 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2631 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2632 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2633 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2634 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2635 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2636 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2637 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2638 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2639 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2640 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2641 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2642 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2643 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2644 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2645 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2646 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2647 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2648
2649 /* RC only: */
2650 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2651 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2652 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2653 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2654
2655 /* RZ only: */
2656 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2657 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2658 STAMPROFILE StatRZTrap0eTimeSyncPT;
2659 STAMPROFILE StatRZTrap0eTimeMapping;
2660 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2661 STAMPROFILE StatRZTrap0eTimeHandlers;
2662 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2663 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2664 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2665 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2666 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2667 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2668 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2669 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2670 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2671 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2672 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2673 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2674 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2675 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2676 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2677 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2678 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2679 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2680 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2681 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2682 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2683 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2684 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2685 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2686 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2687 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2688 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2689 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2690 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2691 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2692 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2693 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2694 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2695 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2696 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2697 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2698 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2699 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2700 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2701 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2702 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2703 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2704 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2705
2706 /* HC - R3 and (maybe) R0: */
2707
2708 /* RZ & R3: */
2709 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2710 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2711 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2712 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2713 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2714 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2715 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2716 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2717 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2718 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2719 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2720 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2721 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2722 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2723 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2724 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2725 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2726 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2727 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2728 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2729 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2730 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2731 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2732 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2733 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2734 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2735 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2736 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2737 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2738 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2739 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2740 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2741 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2742 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2743 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2744 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2745 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2746 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2747 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2748 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2749 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2750 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2751 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2752 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2753 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2754 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2755 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2756/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2757 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2758 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2759 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2760 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2761 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2762 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2763
2764 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2765 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2766 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2767 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2768 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2769 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2770 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2771 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2772 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2773 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2774 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2775 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2776 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2777 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2778 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2779 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2780 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2781 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2782 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2783 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2784 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2785 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2786 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2787 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2788 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2789 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2790 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2791 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2792 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2793 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2794 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2795 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2796 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2797 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2798 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2799 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2800 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2801 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2802 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2803 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2804 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2805 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2806 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2807 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2808 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2809 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2810 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2811/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2812 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2813 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2814 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2815 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2816 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2817 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2818#endif /* VBOX_WITH_STATISTICS */
2819} PGM;
2820/** Pointer to the PGM instance data. */
2821typedef PGM *PPGM;
2822
2823
2824/**
2825 * PGMCPU Data (part of VMCPU).
2826 */
2827typedef struct PGMCPU
2828{
2829 /** Offset to the VMCPU structure. */
2830 RTINT offVMCPU;
2831 /** Automatically tracked physical memory mapping set.
2832 * Ring-0 and strict raw-mode builds. */
2833 PGMMAPSET AutoSet;
2834} PGMCPU;
2835/** Pointer to the per-cpu PGM data. */
2836typedef PGMCPU *PPGMCPU;
2837
2838
2839/** @name PGM::fSyncFlags Flags
2840 * @{
2841 */
2842/** Updates the virtual access handler state bit in PGMPAGE. */
2843#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2844/** Always sync CR3. */
2845#define PGM_SYNC_ALWAYS RT_BIT(1)
2846/** Check monitoring on next CR3 (re)load and invalidate page. */
2847#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2848/** Clear the page pool (a light weight flush). */
2849#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2850/** @} */
2851
2852
2853__BEGIN_DECLS
2854
2855int pgmLock(PVM pVM);
2856void pgmUnlock(PVM pVM);
2857
2858VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2859VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2860
2861int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2862int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2863PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2864void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2865DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2866
2867void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2868int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2869DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2870#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2871void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2872#else
2873# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2874#endif
2875DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2876
2877
2878void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2879int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2880int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2881int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2882#ifdef IN_RING3
2883int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2884int pgmR3PhysRamReset(PVM pVM);
2885int pgmR3PhysRomReset(PVM pVM);
2886# ifndef VBOX_WITH_NEW_PHYS_CODE
2887int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2888# endif
2889
2890int pgmR3PoolInit(PVM pVM);
2891void pgmR3PoolRelocate(PVM pVM);
2892void pgmR3PoolReset(PVM pVM);
2893
2894#endif /* IN_RING3 */
2895#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2896int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2897#endif
2898#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2899void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2900#endif
2901int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2902PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2903void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2904void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2905int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2906void pgmPoolFlushAll(PVM pVM);
2907void pgmPoolClearAll(PVM pVM);
2908int pgmPoolSyncCR3(PVM pVM);
2909void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2910void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2911int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2912PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2913void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2914void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2915uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2916void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2917#ifdef PGMPOOL_WITH_MONITORING
2918# ifdef IN_RING3
2919void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2920# else
2921void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2922# endif
2923int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2924void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2925void pgmPoolMonitorModifiedClearAll(PVM pVM);
2926int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2927int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2928#endif
2929
2930__END_DECLS
2931
2932
2933/**
2934 * Gets the PGMRAMRANGE structure for a guest page.
2935 *
2936 * @returns Pointer to the RAM range on success.
2937 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2938 *
2939 * @param pPGM PGM handle.
2940 * @param GCPhys The GC physical address.
2941 */
2942DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2943{
2944 /*
2945 * Optimize for the first range.
2946 */
2947 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2948 RTGCPHYS off = GCPhys - pRam->GCPhys;
2949 if (RT_UNLIKELY(off >= pRam->cb))
2950 {
2951 do
2952 {
2953 pRam = pRam->CTX_SUFF(pNext);
2954 if (RT_UNLIKELY(!pRam))
2955 break;
2956 off = GCPhys - pRam->GCPhys;
2957 } while (off >= pRam->cb);
2958 }
2959 return pRam;
2960}
2961
2962
2963/**
2964 * Gets the PGMPAGE structure for a guest page.
2965 *
2966 * @returns Pointer to the page on success.
2967 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2968 *
2969 * @param pPGM PGM handle.
2970 * @param GCPhys The GC physical address.
2971 */
2972DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2973{
2974 /*
2975 * Optimize for the first range.
2976 */
2977 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2978 RTGCPHYS off = GCPhys - pRam->GCPhys;
2979 if (RT_UNLIKELY(off >= pRam->cb))
2980 {
2981 do
2982 {
2983 pRam = pRam->CTX_SUFF(pNext);
2984 if (RT_UNLIKELY(!pRam))
2985 return NULL;
2986 off = GCPhys - pRam->GCPhys;
2987 } while (off >= pRam->cb);
2988 }
2989 return &pRam->aPages[off >> PAGE_SHIFT];
2990}
2991
2992
2993/**
2994 * Gets the PGMPAGE structure for a guest page.
2995 *
2996 * Old Phys code: Will make sure the page is present.
2997 *
2998 * @returns VBox status code.
2999 * @retval VINF_SUCCESS and a valid *ppPage on success.
3000 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3001 *
3002 * @param pPGM PGM handle.
3003 * @param GCPhys The GC physical address.
3004 * @param ppPage Where to store the page poitner on success.
3005 */
3006DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3007{
3008 /*
3009 * Optimize for the first range.
3010 */
3011 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3012 RTGCPHYS off = GCPhys - pRam->GCPhys;
3013 if (RT_UNLIKELY(off >= pRam->cb))
3014 {
3015 do
3016 {
3017 pRam = pRam->CTX_SUFF(pNext);
3018 if (RT_UNLIKELY(!pRam))
3019 {
3020 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3021 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3022 }
3023 off = GCPhys - pRam->GCPhys;
3024 } while (off >= pRam->cb);
3025 }
3026 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3027#ifndef VBOX_WITH_NEW_PHYS_CODE
3028
3029 /*
3030 * Make sure it's present.
3031 */
3032 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3033 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3034 {
3035#ifdef IN_RING3
3036 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3037#else
3038 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3039#endif
3040 if (RT_FAILURE(rc))
3041 {
3042 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3043 return rc;
3044 }
3045 Assert(rc == VINF_SUCCESS);
3046 }
3047#endif
3048 return VINF_SUCCESS;
3049}
3050
3051
3052
3053
3054/**
3055 * Gets the PGMPAGE structure for a guest page.
3056 *
3057 * Old Phys code: Will make sure the page is present.
3058 *
3059 * @returns VBox status code.
3060 * @retval VINF_SUCCESS and a valid *ppPage on success.
3061 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3062 *
3063 * @param pPGM PGM handle.
3064 * @param GCPhys The GC physical address.
3065 * @param ppPage Where to store the page poitner on success.
3066 * @param ppRamHint Where to read and store the ram list hint.
3067 * The caller initializes this to NULL before the call.
3068 */
3069DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3070{
3071 RTGCPHYS off;
3072 PPGMRAMRANGE pRam = *ppRamHint;
3073 if ( !pRam
3074 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3075 {
3076 pRam = pPGM->CTX_SUFF(pRamRanges);
3077 off = GCPhys - pRam->GCPhys;
3078 if (RT_UNLIKELY(off >= pRam->cb))
3079 {
3080 do
3081 {
3082 pRam = pRam->CTX_SUFF(pNext);
3083 if (RT_UNLIKELY(!pRam))
3084 {
3085 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3086 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3087 }
3088 off = GCPhys - pRam->GCPhys;
3089 } while (off >= pRam->cb);
3090 }
3091 *ppRamHint = pRam;
3092 }
3093 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3094#ifndef VBOX_WITH_NEW_PHYS_CODE
3095
3096 /*
3097 * Make sure it's present.
3098 */
3099 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3100 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3101 {
3102#ifdef IN_RING3
3103 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3104#else
3105 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3106#endif
3107 if (RT_FAILURE(rc))
3108 {
3109 *ppPage = NULL; /* Shut up annoying smart ass. */
3110 return rc;
3111 }
3112 Assert(rc == VINF_SUCCESS);
3113 }
3114#endif
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/**
3120 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3121 *
3122 * @returns Pointer to the page on success.
3123 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3124 *
3125 * @param pPGM PGM handle.
3126 * @param GCPhys The GC physical address.
3127 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3128 */
3129DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3130{
3131 /*
3132 * Optimize for the first range.
3133 */
3134 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3135 RTGCPHYS off = GCPhys - pRam->GCPhys;
3136 if (RT_UNLIKELY(off >= pRam->cb))
3137 {
3138 do
3139 {
3140 pRam = pRam->CTX_SUFF(pNext);
3141 if (RT_UNLIKELY(!pRam))
3142 return NULL;
3143 off = GCPhys - pRam->GCPhys;
3144 } while (off >= pRam->cb);
3145 }
3146 *ppRam = pRam;
3147 return &pRam->aPages[off >> PAGE_SHIFT];
3148}
3149
3150
3151/**
3152 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3153 *
3154 * @returns Pointer to the page on success.
3155 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3156 *
3157 * @param pPGM PGM handle.
3158 * @param GCPhys The GC physical address.
3159 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3160 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3161 */
3162DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3163{
3164 /*
3165 * Optimize for the first range.
3166 */
3167 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3168 RTGCPHYS off = GCPhys - pRam->GCPhys;
3169 if (RT_UNLIKELY(off >= pRam->cb))
3170 {
3171 do
3172 {
3173 pRam = pRam->CTX_SUFF(pNext);
3174 if (RT_UNLIKELY(!pRam))
3175 {
3176 *ppRam = NULL; /* Shut up silly GCC warnings. */
3177 *ppPage = NULL; /* ditto */
3178 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3179 }
3180 off = GCPhys - pRam->GCPhys;
3181 } while (off >= pRam->cb);
3182 }
3183 *ppRam = pRam;
3184 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3185#ifndef VBOX_WITH_NEW_PHYS_CODE
3186
3187 /*
3188 * Make sure it's present.
3189 */
3190 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3191 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3192 {
3193#ifdef IN_RING3
3194 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3195#else
3196 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3197#endif
3198 if (RT_FAILURE(rc))
3199 {
3200 *ppPage = NULL; /* Shut up silly GCC warnings. */
3201 *ppPage = NULL; /* ditto */
3202 return rc;
3203 }
3204 Assert(rc == VINF_SUCCESS);
3205
3206 }
3207#endif
3208 return VINF_SUCCESS;
3209}
3210
3211
3212/**
3213 * Convert GC Phys to HC Phys.
3214 *
3215 * @returns VBox status.
3216 * @param pPGM PGM handle.
3217 * @param GCPhys The GC physical address.
3218 * @param pHCPhys Where to store the corresponding HC physical address.
3219 *
3220 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3221 * Avoid when writing new code!
3222 */
3223DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3224{
3225 PPGMPAGE pPage;
3226 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3227 if (RT_FAILURE(rc))
3228 return rc;
3229 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3230 return VINF_SUCCESS;
3231}
3232
3233#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3234
3235/**
3236 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3237 * optimizes access to pages already in the set.
3238 *
3239 * @returns See pgmR0DynMapHCPageCommon.
3240 * @param pPGM Pointer to the PVM instance data.
3241 * @param HCPhys The physical address of the page.
3242 * @param ppv Where to store the mapping address.
3243 */
3244DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3245{
3246 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3247 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3248 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3249 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3250 int rc;
3251
3252 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3253 unsigned iEntry = pSet->aiHashTable[iHash];
3254 if ( iEntry < pSet->cEntries
3255 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3256 {
3257 *ppv = pSet->aEntries[iEntry].pvPage;
3258 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3259 rc = VINF_SUCCESS;
3260 }
3261 else
3262 {
3263 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3264 rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3265 }
3266
3267 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3268 return rc;
3269}
3270
3271
3272/**
3273 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3274 * access to pages already in the set.
3275 *
3276 * @returns See pgmR0DynMapHCPageCommon.
3277 * @param pPGM Pointer to the PVM instance data.
3278 * @param HCPhys The physical address of the page.
3279 * @param ppv Where to store the mapping address.
3280 */
3281DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3282{
3283 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3284 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3285
3286 /*
3287 * Get the ram range.
3288 */
3289 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3290 RTGCPHYS off = GCPhys - pRam->GCPhys;
3291 if (RT_UNLIKELY(off >= pRam->cb
3292 /** @todo || page state stuff */))
3293 {
3294 /* This case is not counted into StatR0DynMapGCPageInl. */
3295 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3296 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3297 }
3298
3299 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3300 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3301
3302 /*
3303 * pgmR0DynMapHCPageInlined with out stats.
3304 */
3305 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3306 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3307 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3308 int rc;
3309
3310 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3311 unsigned iEntry = pSet->aiHashTable[iHash];
3312 if ( iEntry < pSet->cEntries
3313 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3314 {
3315 *ppv = pSet->aEntries[iEntry].pvPage;
3316 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3317 rc = VINF_SUCCESS;
3318 }
3319 else
3320 {
3321 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3322 rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3323 }
3324
3325 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3326 return rc;
3327}
3328
3329#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3330
3331#ifndef IN_RC
3332/**
3333 * Queries the Physical TLB entry for a physical guest page,
3334 * attemting to load the TLB entry if necessary.
3335 *
3336 * @returns VBox status code.
3337 * @retval VINF_SUCCESS on success
3338 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3339 * @param pPGM The PGM instance handle.
3340 * @param GCPhys The address of the guest page.
3341 * @param ppTlbe Where to store the pointer to the TLB entry.
3342 */
3343
3344DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3345{
3346 int rc;
3347 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3348 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3349 {
3350 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3351 rc = VINF_SUCCESS;
3352 }
3353 else
3354 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3355 *ppTlbe = pTlbe;
3356 return rc;
3357}
3358#endif /* !IN_RC */
3359
3360#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3361
3362# ifndef VBOX_WITH_NEW_PHYS_CODE
3363/**
3364 * Convert GC Phys to HC Virt.
3365 *
3366 * @returns VBox status.
3367 * @param pPGM PGM handle.
3368 * @param GCPhys The GC physical address.
3369 * @param pHCPtr Where to store the corresponding HC virtual address.
3370 *
3371 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3372 * pgmPoolMonitorGCPtr2CCPtr.
3373 */
3374DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3375{
3376 PPGMRAMRANGE pRam;
3377 PPGMPAGE pPage;
3378 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3379 if (RT_FAILURE(rc))
3380 {
3381 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3382 return rc;
3383 }
3384 RTGCPHYS off = GCPhys - pRam->GCPhys;
3385
3386 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3387 {
3388 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3389 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3390 return VINF_SUCCESS;
3391 }
3392 if (pRam->pvR3)
3393 {
3394 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3395 return VINF_SUCCESS;
3396 }
3397 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3398 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3399}
3400# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3401#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3402
3403/**
3404 * Convert GC Phys to HC Virt and HC Phys.
3405 *
3406 * @returns VBox status.
3407 * @param pPGM PGM handle.
3408 * @param GCPhys The GC physical address.
3409 * @param pHCPtr Where to store the corresponding HC virtual address.
3410 * @param pHCPhys Where to store the HC Physical address and its flags.
3411 *
3412 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3413 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3414 */
3415DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3416{
3417 PPGMRAMRANGE pRam;
3418 PPGMPAGE pPage;
3419 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3420 if (RT_FAILURE(rc))
3421 {
3422 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3423 *pHCPhys = 0; /* ditto */
3424 return rc;
3425 }
3426 RTGCPHYS off = GCPhys - pRam->GCPhys;
3427
3428 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3429 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3430 {
3431 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3432#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3433 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3434 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3435#else
3436 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3437#endif
3438 return VINF_SUCCESS;
3439 }
3440 if (pRam->pvR3)
3441 {
3442 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3443 return VINF_SUCCESS;
3444 }
3445 *pHCPtr = 0;
3446 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3447}
3448
3449
3450/**
3451 * Clears flags associated with a RAM address.
3452 *
3453 * @returns VBox status code.
3454 * @param pPGM PGM handle.
3455 * @param GCPhys Guest context physical address.
3456 * @param fFlags fFlags to clear. (Bits 0-11.)
3457 */
3458DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3459{
3460 PPGMPAGE pPage;
3461 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3462 if (RT_FAILURE(rc))
3463 return rc;
3464
3465 fFlags &= ~X86_PTE_PAE_PG_MASK;
3466 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3467 return VINF_SUCCESS;
3468}
3469
3470
3471/**
3472 * Clears flags associated with a RAM address.
3473 *
3474 * @returns VBox status code.
3475 * @param pPGM PGM handle.
3476 * @param GCPhys Guest context physical address.
3477 * @param fFlags fFlags to clear. (Bits 0-11.)
3478 * @param ppRamHint Where to read and store the ram list hint.
3479 * The caller initializes this to NULL before the call.
3480 */
3481DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3482{
3483 PPGMPAGE pPage;
3484 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3485 if (RT_FAILURE(rc))
3486 return rc;
3487
3488 fFlags &= ~X86_PTE_PAE_PG_MASK;
3489 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3490 return VINF_SUCCESS;
3491}
3492
3493
3494/**
3495 * Sets (bitwise OR) flags associated with a RAM address.
3496 *
3497 * @returns VBox status code.
3498 * @param pPGM PGM handle.
3499 * @param GCPhys Guest context physical address.
3500 * @param fFlags fFlags to set clear. (Bits 0-11.)
3501 */
3502DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3503{
3504 PPGMPAGE pPage;
3505 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3506 if (RT_FAILURE(rc))
3507 return rc;
3508
3509 fFlags &= ~X86_PTE_PAE_PG_MASK;
3510 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3511 return VINF_SUCCESS;
3512}
3513
3514
3515/**
3516 * Sets (bitwise OR) flags associated with a RAM address.
3517 *
3518 * @returns VBox status code.
3519 * @param pPGM PGM handle.
3520 * @param GCPhys Guest context physical address.
3521 * @param fFlags fFlags to set clear. (Bits 0-11.)
3522 * @param ppRamHint Where to read and store the ram list hint.
3523 * The caller initializes this to NULL before the call.
3524 */
3525DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3526{
3527 PPGMPAGE pPage;
3528 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3529 if (RT_FAILURE(rc))
3530 return rc;
3531
3532 fFlags &= ~X86_PTE_PAE_PG_MASK;
3533 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3534 return VINF_SUCCESS;
3535}
3536
3537
3538/**
3539 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3540 * Takes PSE-36 into account.
3541 *
3542 * @returns guest physical address
3543 * @param pPGM Pointer to the PGM instance data.
3544 * @param Pde Guest Pde
3545 */
3546DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3547{
3548 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3549 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3550
3551 return GCPhys & pPGM->GCPhys4MBPSEMask;
3552}
3553
3554
3555/**
3556 * Gets the page directory entry for the specified address (32-bit paging).
3557 *
3558 * @returns The page directory entry in question.
3559 * @param pPGM Pointer to the PGM instance data.
3560 * @param GCPtr The address.
3561 */
3562DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3563{
3564#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3565 PCX86PD pGuestPD = 0;
3566 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3567 if (RT_FAILURE(rc))
3568 {
3569 X86PDE ZeroPde = {0};
3570 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3571 }
3572 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3573#else
3574 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3575#endif
3576}
3577
3578
3579/**
3580 * Gets the address of a specific page directory entry (32-bit paging).
3581 *
3582 * @returns Pointer the page directory entry in question.
3583 * @param pPGM Pointer to the PGM instance data.
3584 * @param GCPtr The address.
3585 */
3586DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3587{
3588#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3589 PX86PD pGuestPD = 0;
3590 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3591 AssertRCReturn(rc, 0);
3592 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3593#else
3594 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3595#endif
3596}
3597
3598
3599/**
3600 * Gets the address the guest page directory (32-bit paging).
3601 *
3602 * @returns Pointer the page directory entry in question.
3603 * @param pPGM Pointer to the PGM instance data.
3604 */
3605DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3606{
3607#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3608 PX86PD pGuestPD = 0;
3609 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3610 AssertRCReturn(rc, 0);
3611 return pGuestPD;
3612#else
3613 return pPGM->CTX_SUFF(pGst32BitPd);
3614#endif
3615}
3616
3617
3618/**
3619 * Gets the guest page directory pointer table.
3620 *
3621 * @returns Pointer to the page directory in question.
3622 * @returns NULL if the page directory is not present or on an invalid page.
3623 * @param pPGM Pointer to the PGM instance data.
3624 */
3625DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3626{
3627#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3628 PX86PDPT pGuestPDPT = 0;
3629 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3630 AssertRCReturn(rc, 0);
3631 return pGuestPDPT;
3632#else
3633 return pPGM->CTX_SUFF(pGstPaePdpt);
3634#endif
3635}
3636
3637
3638/**
3639 * Gets the guest page directory pointer table entry for the specified address.
3640 *
3641 * @returns Pointer to the page directory in question.
3642 * @returns NULL if the page directory is not present or on an invalid page.
3643 * @param pPGM Pointer to the PGM instance data.
3644 * @param GCPtr The address.
3645 */
3646DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3647{
3648 AssertGCPtr32(GCPtr);
3649
3650#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3651 PX86PDPT pGuestPDPT = 0;
3652 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3653 AssertRCReturn(rc, 0);
3654 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3655#else
3656 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3657#endif
3658}
3659
3660
3661/**
3662 * Gets the page directory for the specified address.
3663 *
3664 * @returns Pointer to the page directory in question.
3665 * @returns NULL if the page directory is not present or on an invalid page.
3666 * @param pPGM Pointer to the PGM instance data.
3667 * @param GCPtr The address.
3668 */
3669DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3670{
3671 AssertGCPtr32(GCPtr);
3672
3673#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3674 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3675 AssertReturn(pGuestPDPT, 0);
3676#else
3677 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3678#endif
3679 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3680 if (pGuestPDPT->a[iPdPt].n.u1Present)
3681 {
3682#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3683 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3684 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3685#endif
3686
3687 /* cache is out-of-sync. */
3688 PX86PDPAE pPD;
3689 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3690 if (RT_SUCCESS(rc))
3691 return pPD;
3692 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3693 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3694 }
3695 return NULL;
3696}
3697
3698
3699/**
3700 * Gets the page directory entry for the specified address.
3701 *
3702 * @returns Pointer to the page directory entry in question.
3703 * @returns NULL if the page directory is not present or on an invalid page.
3704 * @param pPGM Pointer to the PGM instance data.
3705 * @param GCPtr The address.
3706 */
3707DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3708{
3709 AssertGCPtr32(GCPtr);
3710
3711#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3712 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3713 AssertReturn(pGuestPDPT, 0);
3714#else
3715 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3716#endif
3717 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3718 if (pGuestPDPT->a[iPdPt].n.u1Present)
3719 {
3720 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3721#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3722 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3723 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3724#endif
3725
3726 /* The cache is out-of-sync. */
3727 PX86PDPAE pPD;
3728 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3729 if (RT_SUCCESS(rc))
3730 return &pPD->a[iPD];
3731 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3732 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3733 }
3734 return NULL;
3735}
3736
3737
3738/**
3739 * Gets the page directory entry for the specified address.
3740 *
3741 * @returns The page directory entry in question.
3742 * @returns A non-present entry if the page directory is not present or on an invalid page.
3743 * @param pPGM Pointer to the PGM instance data.
3744 * @param GCPtr The address.
3745 */
3746DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3747{
3748 AssertGCPtr32(GCPtr);
3749
3750#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3751 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3752 if (RT_LIKELY(pGuestPDPT))
3753#else
3754 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3755#endif
3756 {
3757 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3758 if (pGuestPDPT->a[iPdPt].n.u1Present)
3759 {
3760 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3761#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3762 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3763 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3764#endif
3765
3766 /* cache is out-of-sync. */
3767 PX86PDPAE pPD;
3768 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3769 if (RT_SUCCESS(rc))
3770 return pPD->a[iPD];
3771 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3772 }
3773 }
3774 X86PDEPAE ZeroPde = {0};
3775 return ZeroPde;
3776}
3777
3778
3779/**
3780 * Gets the page directory pointer table entry for the specified address
3781 * and returns the index into the page directory
3782 *
3783 * @returns Pointer to the page directory in question.
3784 * @returns NULL if the page directory is not present or on an invalid page.
3785 * @param pPGM Pointer to the PGM instance data.
3786 * @param GCPtr The address.
3787 * @param piPD Receives the index into the returned page directory
3788 * @param pPdpe Receives the page directory pointer entry. Optional.
3789 */
3790DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3791{
3792 AssertGCPtr32(GCPtr);
3793
3794#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3795 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3796 AssertReturn(pGuestPDPT, 0);
3797#else
3798 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3799#endif
3800 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3801 if (pPdpe)
3802 *pPdpe = pGuestPDPT->a[iPdPt];
3803 if (pGuestPDPT->a[iPdPt].n.u1Present)
3804 {
3805 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3806#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3807 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3808 {
3809 *piPD = iPD;
3810 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3811 }
3812#endif
3813
3814 /* cache is out-of-sync. */
3815 PX86PDPAE pPD;
3816 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3817 if (RT_SUCCESS(rc))
3818 {
3819 *piPD = iPD;
3820 return pPD;
3821 }
3822 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3823 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3824 }
3825 return NULL;
3826}
3827
3828#ifndef IN_RC
3829
3830/**
3831 * Gets the page map level-4 pointer for the guest.
3832 *
3833 * @returns Pointer to the PML4 page.
3834 * @param pPGM Pointer to the PGM instance data.
3835 */
3836DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3837{
3838#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3839 PX86PML4 pGuestPml4;
3840 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3841 AssertRCReturn(rc, NULL);
3842 return pGuestPml4;
3843#else
3844 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3845 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3846#endif
3847}
3848
3849
3850/**
3851 * Gets the pointer to a page map level-4 entry.
3852 *
3853 * @returns Pointer to the PML4 entry.
3854 * @param pPGM Pointer to the PGM instance data.
3855 * @param iPml4 The index.
3856 */
3857DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3858{
3859#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3860 PX86PML4 pGuestPml4;
3861 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3862 AssertRCReturn(rc, NULL);
3863 return &pGuestPml4->a[iPml4];
3864#else
3865 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3866 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3867#endif
3868}
3869
3870
3871/**
3872 * Gets a page map level-4 entry.
3873 *
3874 * @returns The PML4 entry.
3875 * @param pPGM Pointer to the PGM instance data.
3876 * @param iPml4 The index.
3877 */
3878DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3879{
3880#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3881 PX86PML4 pGuestPml4;
3882 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3883 if (RT_FAILURE(rc))
3884 {
3885 X86PML4E ZeroPml4e = {0};
3886 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3887 }
3888 return pGuestPml4->a[iPml4];
3889#else
3890 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3891 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3892#endif
3893}
3894
3895
3896/**
3897 * Gets the page directory pointer entry for the specified address.
3898 *
3899 * @returns Pointer to the page directory pointer entry in question.
3900 * @returns NULL if the page directory is not present or on an invalid page.
3901 * @param pPGM Pointer to the PGM instance data.
3902 * @param GCPtr The address.
3903 * @param ppPml4e Page Map Level-4 Entry (out)
3904 */
3905DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3906{
3907 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3908 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3909 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3910 if (pPml4e->n.u1Present)
3911 {
3912 PX86PDPT pPdpt;
3913 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3914 AssertRCReturn(rc, NULL);
3915
3916 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3917 return &pPdpt->a[iPdPt];
3918 }
3919 return NULL;
3920}
3921
3922
3923/**
3924 * Gets the page directory entry for the specified address.
3925 *
3926 * @returns The page directory entry in question.
3927 * @returns A non-present entry if the page directory is not present or on an invalid page.
3928 * @param pPGM Pointer to the PGM instance data.
3929 * @param GCPtr The address.
3930 * @param ppPml4e Page Map Level-4 Entry (out)
3931 * @param pPdpe Page directory pointer table entry (out)
3932 */
3933DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3934{
3935 X86PDEPAE ZeroPde = {0};
3936 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3937 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3938 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3939 if (pPml4e->n.u1Present)
3940 {
3941 PCX86PDPT pPdptTemp;
3942 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3943 AssertRCReturn(rc, ZeroPde);
3944
3945 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3946 *pPdpe = pPdptTemp->a[iPdPt];
3947 if (pPdptTemp->a[iPdPt].n.u1Present)
3948 {
3949 PCX86PDPAE pPD;
3950 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3951 AssertRCReturn(rc, ZeroPde);
3952
3953 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3954 return pPD->a[iPD];
3955 }
3956 }
3957
3958 return ZeroPde;
3959}
3960
3961
3962/**
3963 * Gets the page directory entry for the specified address.
3964 *
3965 * @returns The page directory entry in question.
3966 * @returns A non-present entry if the page directory is not present or on an invalid page.
3967 * @param pPGM Pointer to the PGM instance data.
3968 * @param GCPtr The address.
3969 */
3970DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
3971{
3972 X86PDEPAE ZeroPde = {0};
3973 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3974 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3975 if (pGuestPml4->a[iPml4].n.u1Present)
3976 {
3977 PCX86PDPT pPdptTemp;
3978 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3979 AssertRCReturn(rc, ZeroPde);
3980
3981 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3982 if (pPdptTemp->a[iPdPt].n.u1Present)
3983 {
3984 PCX86PDPAE pPD;
3985 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3986 AssertRCReturn(rc, ZeroPde);
3987
3988 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3989 return pPD->a[iPD];
3990 }
3991 }
3992 return ZeroPde;
3993}
3994
3995
3996/**
3997 * Gets the page directory entry for the specified address.
3998 *
3999 * @returns Pointer to the page directory entry in question.
4000 * @returns NULL if the page directory is not present or on an invalid page.
4001 * @param pPGM Pointer to the PGM instance data.
4002 * @param GCPtr The address.
4003 */
4004DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4005{
4006 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4007 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4008 if (pGuestPml4->a[iPml4].n.u1Present)
4009 {
4010 PCX86PDPT pPdptTemp;
4011 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4012 AssertRCReturn(rc, NULL);
4013
4014 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4015 if (pPdptTemp->a[iPdPt].n.u1Present)
4016 {
4017 PX86PDPAE pPD;
4018 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4019 AssertRCReturn(rc, NULL);
4020
4021 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4022 return &pPD->a[iPD];
4023 }
4024 }
4025 return NULL;
4026}
4027
4028
4029/**
4030 * Gets the GUEST page directory pointer for the specified address.
4031 *
4032 * @returns The page directory in question.
4033 * @returns NULL if the page directory is not present or on an invalid page.
4034 * @param pPGM Pointer to the PGM instance data.
4035 * @param GCPtr The address.
4036 * @param ppPml4e Page Map Level-4 Entry (out)
4037 * @param pPdpe Page directory pointer table entry (out)
4038 * @param piPD Receives the index into the returned page directory
4039 */
4040DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4041{
4042 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4043 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4044 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4045 if (pPml4e->n.u1Present)
4046 {
4047 PCX86PDPT pPdptTemp;
4048 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4049 AssertRCReturn(rc, NULL);
4050
4051 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4052 *pPdpe = pPdptTemp->a[iPdPt];
4053 if (pPdptTemp->a[iPdPt].n.u1Present)
4054 {
4055 PX86PDPAE pPD;
4056 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4057 AssertRCReturn(rc, NULL);
4058
4059 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4060 return pPD;
4061 }
4062 }
4063 return 0;
4064}
4065
4066#endif /* !IN_RC */
4067
4068
4069/**
4070 * Gets the shadow page directory, 32-bit.
4071 *
4072 * @returns Pointer to the shadow 32-bit PD.
4073 * @param pPGM Pointer to the PGM instance data.
4074 */
4075DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4076{
4077#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4078 return (PX86PD)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4079#else
4080# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4081 PX86PD pShwPd;
4082 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4083 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4084 AssertRCReturn(rc, NULL);
4085 return pShwPd;
4086# else
4087 return pPGM->CTX_SUFF(pShw32BitPd);
4088# endif
4089#endif
4090}
4091
4092
4093/**
4094 * Gets the shadow page directory entry for the specified address, 32-bit.
4095 *
4096 * @returns Shadow 32-bit PDE.
4097 * @param pPGM Pointer to the PGM instance data.
4098 * @param GCPtr The address.
4099 */
4100DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4101{
4102 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4103
4104 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4105 if (!pShwPde)
4106 {
4107 X86PDE ZeroPde = {0};
4108 return ZeroPde;
4109 }
4110 return pShwPde->a[iPd];
4111}
4112
4113
4114/**
4115 * Gets the pointer to the shadow page directory entry for the specified
4116 * address, 32-bit.
4117 *
4118 * @returns Pointer to the shadow 32-bit PDE.
4119 * @param pPGM Pointer to the PGM instance data.
4120 * @param GCPtr The address.
4121 */
4122DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4123{
4124 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4125
4126 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4127 AssertReturn(pPde, NULL);
4128 return &pPde->a[iPd];
4129}
4130
4131
4132/**
4133 * Gets the shadow page pointer table, PAE.
4134 *
4135 * @returns Pointer to the shadow PAE PDPT.
4136 * @param pPGM Pointer to the PGM instance data.
4137 */
4138DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4139{
4140#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4141 return (PX86PDPT)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4142#else
4143# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4144 PX86PDPT pShwPdpt;
4145 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4146 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4147 AssertRCReturn(rc, 0);
4148 return pShwPdpt;
4149# else
4150 return pPGM->CTX_SUFF(pShwPaePdpt);
4151# endif
4152#endif
4153}
4154
4155
4156/**
4157 * Gets the shadow page directory for the specified address, PAE.
4158 *
4159 * @returns Pointer to the shadow PD.
4160 * @param pPGM Pointer to the PGM instance data.
4161 * @param GCPtr The address.
4162 */
4163DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4164{
4165#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4166 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4167 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4168
4169 /* Fetch the pgm pool shadow descriptor. */
4170 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4171 AssertReturn(pShwPde, NULL);
4172
4173 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pShwPde);
4174#else
4175 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4176# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4177 PX86PDPAE pPD;
4178 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4179 AssertRCReturn(rc, 0);
4180 return pPD;
4181# else
4182 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4183 Assert(pPD);
4184 return pPD;
4185# endif
4186#endif
4187}
4188
4189
4190/**
4191 * Gets the shadow page directory entry, PAE.
4192 *
4193 * @returns PDE.
4194 * @param pPGM Pointer to the PGM instance data.
4195 * @param GCPtr The address.
4196 */
4197DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4198{
4199 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4200
4201 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4202 if (!pShwPde)
4203 {
4204 X86PDEPAE ZeroPde = {0};
4205 return ZeroPde;
4206 }
4207 return pShwPde->a[iPd];
4208}
4209
4210
4211/**
4212 * Gets the pointer to the shadow page directory entry for an address, PAE.
4213 *
4214 * @returns Pointer to the PDE.
4215 * @param pPGM Pointer to the PGM instance data.
4216 * @param GCPtr The address.
4217 */
4218DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4219{
4220 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4221
4222 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4223 AssertReturn(pPde, NULL);
4224 return &pPde->a[iPd];
4225}
4226
4227#ifndef IN_RC
4228
4229/**
4230 * Gets the shadow page map level-4 pointer.
4231 *
4232 * @returns Pointer to the shadow PML4.
4233 * @param pPGM Pointer to the PGM instance data.
4234 */
4235DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4236{
4237#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4238 return (PX86PML4)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
4239#else
4240# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4241 PX86PML4 pShwPml4;
4242 Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
4243 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePml4, &pShwPml4);
4244 AssertRCReturn(rc, 0);
4245 return pShwPml4;
4246# else
4247 Assert(pPGM->CTX_SUFF(pShwPaePml4));
4248 return pPGM->CTX_SUFF(pShwPaePml4);
4249# endif
4250#endif
4251}
4252
4253
4254/**
4255 * Gets the shadow page map level-4 entry for the specified address.
4256 *
4257 * @returns The entry.
4258 * @param pPGM Pointer to the PGM instance data.
4259 * @param GCPtr The address.
4260 */
4261DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4262{
4263 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4264 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4265
4266 if (!pShwPml4)
4267 {
4268 X86PML4E ZeroPml4e = {0};
4269 return ZeroPml4e;
4270 }
4271 return pShwPml4->a[iPml4];
4272}
4273
4274
4275/**
4276 * Gets the pointer to the specified shadow page map level-4 entry.
4277 *
4278 * @returns The entry.
4279 * @param pPGM Pointer to the PGM instance data.
4280 * @param iPml4 The PML4 index.
4281 */
4282DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4283{
4284 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4285
4286 if (!pShwPml4)
4287 return NULL;
4288
4289 return &pShwPml4->a[iPml4];
4290}
4291
4292
4293/**
4294 * Gets the GUEST page directory pointer for the specified address.
4295 *
4296 * @returns The page directory in question.
4297 * @returns NULL if the page directory is not present or on an invalid page.
4298 * @param pPGM Pointer to the PGM instance data.
4299 * @param GCPtr The address.
4300 * @param piPD Receives the index into the returned page directory
4301 */
4302DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4303{
4304 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4305 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4306 if (pGuestPml4->a[iPml4].n.u1Present)
4307 {
4308 PCX86PDPT pPdptTemp;
4309 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4310 AssertRCReturn(rc, NULL);
4311
4312 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4313 if (pPdptTemp->a[iPdPt].n.u1Present)
4314 {
4315 PX86PDPAE pPD;
4316 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4317 AssertRCReturn(rc, NULL);
4318
4319 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4320 return pPD;
4321 }
4322 }
4323 return NULL;
4324}
4325
4326#endif /* !IN_RC */
4327
4328/**
4329 * Checks if any of the specified page flags are set for the given page.
4330 *
4331 * @returns true if any of the flags are set.
4332 * @returns false if all the flags are clear.
4333 * @param pPGM PGM handle.
4334 * @param GCPhys The GC physical address.
4335 * @param fFlags The flags to check for.
4336 */
4337DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4338{
4339 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4340 return pPage
4341 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4342}
4343
4344
4345/**
4346 * Gets the page state for a physical handler.
4347 *
4348 * @returns The physical handler page state.
4349 * @param pCur The physical handler in question.
4350 */
4351DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4352{
4353 switch (pCur->enmType)
4354 {
4355 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4356 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4357
4358 case PGMPHYSHANDLERTYPE_MMIO:
4359 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4360 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4361
4362 default:
4363 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4364 }
4365}
4366
4367
4368/**
4369 * Gets the page state for a virtual handler.
4370 *
4371 * @returns The virtual handler page state.
4372 * @param pCur The virtual handler in question.
4373 * @remarks This should never be used on a hypervisor access handler.
4374 */
4375DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4376{
4377 switch (pCur->enmType)
4378 {
4379 case PGMVIRTHANDLERTYPE_WRITE:
4380 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4381 case PGMVIRTHANDLERTYPE_ALL:
4382 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4383 default:
4384 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4385 }
4386}
4387
4388
4389/**
4390 * Clears one physical page of a virtual handler
4391 *
4392 * @param pPGM Pointer to the PGM instance.
4393 * @param pCur Virtual handler structure
4394 * @param iPage Physical page index
4395 *
4396 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4397 * need to care about other handlers in the same page.
4398 */
4399DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4400{
4401 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4402
4403 /*
4404 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4405 */
4406#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4407 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4408 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4409 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4410#endif
4411 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4412 {
4413 /* We're the head of the alias chain. */
4414 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4415#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4416 AssertReleaseMsg(pRemove != NULL,
4417 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4418 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4419 AssertReleaseMsg(pRemove == pPhys2Virt,
4420 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4421 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4422 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4423 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4424#endif
4425 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4426 {
4427 /* Insert the next list in the alias chain into the tree. */
4428 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4429#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4430 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4431 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4432 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4433#endif
4434 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4435 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4436 AssertRelease(fRc);
4437 }
4438 }
4439 else
4440 {
4441 /* Locate the previous node in the alias chain. */
4442 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4443#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4444 AssertReleaseMsg(pPrev != pPhys2Virt,
4445 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4446 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4447#endif
4448 for (;;)
4449 {
4450 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4451 if (pNext == pPhys2Virt)
4452 {
4453 /* unlink. */
4454 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4455 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4456 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4457 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4458 else
4459 {
4460 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4461 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4462 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4463 }
4464 break;
4465 }
4466
4467 /* next */
4468 if (pNext == pPrev)
4469 {
4470#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4471 AssertReleaseMsg(pNext != pPrev,
4472 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4473 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4474#endif
4475 break;
4476 }
4477 pPrev = pNext;
4478 }
4479 }
4480 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4481 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4482 pPhys2Virt->offNextAlias = 0;
4483 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4484
4485 /*
4486 * Clear the ram flags for this page.
4487 */
4488 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4489 AssertReturnVoid(pPage);
4490 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4491}
4492
4493
4494/**
4495 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4496 *
4497 * @returns Pointer to the shadow page structure.
4498 * @param pPool The pool.
4499 * @param HCPhys The HC physical address of the shadow page.
4500 */
4501DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4502{
4503 /*
4504 * Look up the page.
4505 */
4506 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4507 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4508 return pPage;
4509}
4510
4511
4512/**
4513 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4514 *
4515 * @returns Pointer to the shadow page structure.
4516 * @param pPool The pool.
4517 * @param idx The pool page index.
4518 */
4519DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4520{
4521 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4522 return &pPool->aPages[idx];
4523}
4524
4525
4526#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4527/**
4528 * Clear references to guest physical memory.
4529 *
4530 * @param pPool The pool.
4531 * @param pPoolPage The pool page.
4532 * @param pPhysPage The physical guest page tracking structure.
4533 */
4534DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4535{
4536 /*
4537 * Just deal with the simple case here.
4538 */
4539# ifdef LOG_ENABLED
4540 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4541# endif
4542 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4543 if (cRefs == 1)
4544 {
4545 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4546 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4547 }
4548 else
4549 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4550 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4551}
4552#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4553
4554
4555#ifdef PGMPOOL_WITH_CACHE
4556/**
4557 * Moves the page to the head of the age list.
4558 *
4559 * This is done when the cached page is used in one way or another.
4560 *
4561 * @param pPool The pool.
4562 * @param pPage The cached page.
4563 * @todo inline in PGMInternal.h!
4564 */
4565DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4566{
4567 /*
4568 * Move to the head of the age list.
4569 */
4570 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4571 {
4572 /* unlink */
4573 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4574 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4575 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4576 else
4577 pPool->iAgeTail = pPage->iAgePrev;
4578
4579 /* insert at head */
4580 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4581 pPage->iAgeNext = pPool->iAgeHead;
4582 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4583 pPool->iAgeHead = pPage->idx;
4584 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4585 }
4586}
4587#endif /* PGMPOOL_WITH_CACHE */
4588
4589/**
4590 * Tells if mappings are to be put into the shadow page table or not
4591 *
4592 * @returns boolean result
4593 * @param pVM VM handle.
4594 */
4595
4596DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4597{
4598#ifdef IN_RING0
4599 /* There are no mappings in VT-x and AMD-V mode. */
4600 Assert(pPGM->fDisableMappings);
4601 return false;
4602#else
4603 return !pPGM->fDisableMappings;
4604#endif
4605}
4606
4607/** @} */
4608
4609#endif
4610
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