VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 16462

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1/* $Id: PGMInternal.h 16429 2009-01-30 16:50:00Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59//#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186/** @} */
187
188/** @name Defines used to indicate the shadow and guest paging in the templates.
189 * @{ */
190#define PGM_TYPE_REAL 1
191#define PGM_TYPE_PROT 2
192#define PGM_TYPE_32BIT 3
193#define PGM_TYPE_PAE 4
194#define PGM_TYPE_AMD64 5
195#define PGM_TYPE_NESTED 6
196#define PGM_TYPE_EPT 7
197#define PGM_TYPE_MAX PGM_TYPE_EPT
198/** @} */
199
200/** Macro for checking if the guest is using paging.
201 * @param uGstType PGM_TYPE_*
202 * @param uShwType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_PAGING(uGstType, uShwType) \
206 ( (uGstType) >= PGM_TYPE_32BIT \
207 && (uShwType) != PGM_TYPE_NESTED \
208 && (uShwType) != PGM_TYPE_EPT)
209
210/** Macro for checking if the guest supports the NX bit.
211 * @param uGstType PGM_TYPE_*
212 * @param uShwType PGM_TYPE_*
213 * @remark ASSUMES certain order of the PGM_TYPE_* values.
214 */
215#define PGM_WITH_NX(uGstType, uShwType) \
216 ( (uGstType) >= PGM_TYPE_PAE \
217 && (uShwType) != PGM_TYPE_NESTED \
218 && (uShwType) != PGM_TYPE_EPT)
219
220
221/** @def PGM_HCPHYS_2_PTR
222 * Maps a HC physical page pool address to a virtual address.
223 *
224 * @returns VBox status code.
225 * @param pVM The VM handle.
226 * @param HCPhys The HC physical address to map to a virtual one.
227 * @param ppv Where to store the virtual address. No need to cast this.
228 *
229 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
230 * small page window employeed by that function. Be careful.
231 * @remark There is no need to assert on the result.
232 */
233#ifdef IN_RC
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
236#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
237# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
239#else
240# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
241 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
242#endif
243
244/** @def PGM_HCPHYS_2_PTR_BY_PGM
245 * Maps a HC physical page pool address to a virtual address.
246 *
247 * @returns VBox status code.
248 * @param pPGM The PGM instance data.
249 * @param HCPhys The HC physical address to map to a virtual one.
250 * @param ppv Where to store the virtual address. No need to cast this.
251 *
252 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
253 * small page window employeed by that function. Be careful.
254 * @remark There is no need to assert on the result.
255 */
256#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
257# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
259#else
260# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
261 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
262#endif
263
264/** @def PGM_GCPHYS_2_PTR
265 * Maps a GC physical page address to a virtual address.
266 *
267 * @returns VBox status code.
268 * @param pVM The VM handle.
269 * @param GCPhys The GC physical address to map to a virtual one.
270 * @param ppv Where to store the virtual address. No need to cast this.
271 *
272 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
273 * small page window employeed by that function. Be careful.
274 * @remark There is no need to assert on the result.
275 */
276#ifdef IN_RC
277# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
279#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
280# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
282#else
283# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
284 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
285#endif
286
287/** @def PGM_GCPHYS_2_PTR_BY_PGM
288 * Maps a GC physical page address to a virtual address.
289 *
290 * @returns VBox status code.
291 * @param pPGM Pointer to the PGM instance data.
292 * @param GCPhys The GC physical address to map to a virtual one.
293 * @param ppv Where to store the virtual address. No need to cast this.
294 *
295 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
296 * small page window employeed by that function. Be careful.
297 * @remark There is no need to assert on the result.
298 */
299#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
300# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
301 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
302#else
303# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
304 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
305#endif
306
307/** @def PGM_GCPHYS_2_PTR_EX
308 * Maps a unaligned GC physical page address to a virtual address.
309 *
310 * @returns VBox status code.
311 * @param pVM The VM handle.
312 * @param GCPhys The GC physical address to map to a virtual one.
313 * @param ppv Where to store the virtual address. No need to cast this.
314 *
315 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
316 * small page window employeed by that function. Be careful.
317 * @remark There is no need to assert on the result.
318 */
319#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
320# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
322#else
323# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
324 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
325#endif
326
327/** @def PGM_INVL_PG
328 * Invalidates a page when in GC does nothing in HC.
329 *
330 * @param GCVirt The virtual address of the page to invalidate.
331 */
332#ifdef IN_RC
333# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
334#elif defined(IN_RING0)
335# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
336#else
337# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
338#endif
339
340/** @def PGM_INVL_BIG_PG
341 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
342 *
343 * @param GCVirt The virtual address within the page directory to invalidate.
344 */
345#ifdef IN_RC
346# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
347#elif defined(IN_RING0)
348# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
349#else
350# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
351#endif
352
353/** @def PGM_INVL_GUEST_TLBS()
354 * Invalidates all guest TLBs.
355 */
356#ifdef IN_RC
357# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
358#elif defined(IN_RING0)
359# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
360#else
361# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
362#endif
363
364
365/**
366 * Structure for tracking GC Mappings.
367 *
368 * This structure is used by linked list in both GC and HC.
369 */
370typedef struct PGMMAPPING
371{
372 /** Pointer to next entry. */
373 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
374 /** Pointer to next entry. */
375 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
376 /** Pointer to next entry. */
377 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
378 /** Indicate whether this entry is finalized. */
379 bool fFinalized;
380 /** Start Virtual address. */
381 RTGCPTR GCPtr;
382 /** Last Virtual address (inclusive). */
383 RTGCPTR GCPtrLast;
384 /** Range size (bytes). */
385 RTGCPTR cb;
386 /** Pointer to relocation callback function. */
387 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
388 /** User argument to the callback. */
389 R3PTRTYPE(void *) pvUser;
390 /** Mapping description / name. For easing debugging. */
391 R3PTRTYPE(const char *) pszDesc;
392 /** Number of page tables. */
393 uint32_t cPTs;
394#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
395 uint32_t uPadding1; /**< Alignment padding. */
396#endif
397 /** Array of page table mapping data. Each entry
398 * describes one page table. The array can be longer
399 * than the declared length.
400 */
401 struct
402 {
403 /** The HC physical address of the page table. */
404 RTHCPHYS HCPhysPT;
405 /** The HC physical address of the first PAE page table. */
406 RTHCPHYS HCPhysPaePT0;
407 /** The HC physical address of the second PAE page table. */
408 RTHCPHYS HCPhysPaePT1;
409 /** The HC virtual address of the 32-bit page table. */
410 R3PTRTYPE(PX86PT) pPTR3;
411 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
412 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
413 /** The GC virtual address of the 32-bit page table. */
414 RCPTRTYPE(PX86PT) pPTRC;
415 /** The GC virtual address of the two PAE page table. */
416 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
417 /** The GC virtual address of the 32-bit page table. */
418 R0PTRTYPE(PX86PT) pPTR0;
419 /** The GC virtual address of the two PAE page table. */
420 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
421 } aPTs[1];
422} PGMMAPPING;
423/** Pointer to structure for tracking GC Mappings. */
424typedef struct PGMMAPPING *PPGMMAPPING;
425
426
427/**
428 * Physical page access handler structure.
429 *
430 * This is used to keep track of physical address ranges
431 * which are being monitored in some kind of way.
432 */
433typedef struct PGMPHYSHANDLER
434{
435 AVLROGCPHYSNODECORE Core;
436 /** Access type. */
437 PGMPHYSHANDLERTYPE enmType;
438 /** Number of pages to update. */
439 uint32_t cPages;
440 /** Pointer to R3 callback function. */
441 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
442 /** User argument for R3 handlers. */
443 R3PTRTYPE(void *) pvUserR3;
444 /** Pointer to R0 callback function. */
445 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
446 /** User argument for R0 handlers. */
447 R0PTRTYPE(void *) pvUserR0;
448 /** Pointer to GC callback function. */
449 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
450 /** User argument for RC handlers. */
451 RCPTRTYPE(void *) pvUserRC;
452 /** Description / Name. For easing debugging. */
453 R3PTRTYPE(const char *) pszDesc;
454#ifdef VBOX_WITH_STATISTICS
455 /** Profiling of this handler. */
456 STAMPROFILE Stat;
457#endif
458} PGMPHYSHANDLER;
459/** Pointer to a physical page access handler structure. */
460typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
461
462
463/**
464 * Cache node for the physical addresses covered by a virtual handler.
465 */
466typedef struct PGMPHYS2VIRTHANDLER
467{
468 /** Core node for the tree based on physical ranges. */
469 AVLROGCPHYSNODECORE Core;
470 /** Offset from this struct to the PGMVIRTHANDLER structure. */
471 int32_t offVirtHandler;
472 /** Offset of the next alias relative to this one.
473 * Bit 0 is used for indicating whether we're in the tree.
474 * Bit 1 is used for indicating that we're the head node.
475 */
476 int32_t offNextAlias;
477} PGMPHYS2VIRTHANDLER;
478/** Pointer to a phys to virtual handler structure. */
479typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
480
481/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
482 * node is in the tree. */
483#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
484/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
485 * node is in the head of an alias chain.
486 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
487#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
488/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
489#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
490
491
492/**
493 * Virtual page access handler structure.
494 *
495 * This is used to keep track of virtual address ranges
496 * which are being monitored in some kind of way.
497 */
498typedef struct PGMVIRTHANDLER
499{
500 /** Core node for the tree based on virtual ranges. */
501 AVLROGCPTRNODECORE Core;
502 /** Size of the range (in bytes). */
503 RTGCPTR cb;
504 /** Number of cache pages. */
505 uint32_t cPages;
506 /** Access type. */
507 PGMVIRTHANDLERTYPE enmType;
508 /** Pointer to the RC callback function. */
509 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
510#if HC_ARCH_BITS == 64
511 RTRCPTR padding;
512#endif
513 /** Pointer to the R3 callback function for invalidation. */
514 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
515 /** Pointer to the R3 callback function. */
516 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
517 /** Description / Name. For easing debugging. */
518 R3PTRTYPE(const char *) pszDesc;
519#ifdef VBOX_WITH_STATISTICS
520 /** Profiling of this handler. */
521 STAMPROFILE Stat;
522#endif
523 /** Array of cached physical addresses for the monitored ranged. */
524 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
525} PGMVIRTHANDLER;
526/** Pointer to a virtual page access handler structure. */
527typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
528
529
530/**
531 * Page type.
532 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
533 * @todo convert to \#defines.
534 */
535typedef enum PGMPAGETYPE
536{
537 /** The usual invalid zero entry. */
538 PGMPAGETYPE_INVALID = 0,
539 /** RAM page. (RWX) */
540 PGMPAGETYPE_RAM,
541 /** MMIO2 page. (RWX) */
542 PGMPAGETYPE_MMIO2,
543 /** Shadowed ROM. (RWX) */
544 PGMPAGETYPE_ROM_SHADOW,
545 /** ROM page. (R-X) */
546 PGMPAGETYPE_ROM,
547 /** MMIO page. (---) */
548 PGMPAGETYPE_MMIO,
549 /** End of valid entries. */
550 PGMPAGETYPE_END
551} PGMPAGETYPE;
552AssertCompile(PGMPAGETYPE_END < 7);
553
554/** @name Page type predicates.
555 * @{ */
556#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
557#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
558#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
559#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
560#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
561/** @} */
562
563
564/**
565 * A Physical Guest Page tracking structure.
566 *
567 * The format of this structure is complicated because we have to fit a lot
568 * of information into as few bits as possible. The format is also subject
569 * to change (there is one comming up soon). Which means that for we'll be
570 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
571 * accessess to the structure.
572 */
573typedef struct PGMPAGE
574{
575 /** The physical address and a whole lot of other stuff. All bits are used! */
576 RTHCPHYS HCPhys;
577 /** The page state. */
578 uint32_t u2StateX : 2;
579 /** Flag indicating that a write monitored page was written to when set. */
580 uint32_t fWrittenToX : 1;
581 /** For later. */
582 uint32_t fSomethingElse : 1;
583 /** The Page ID.
584 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
585 * The HCPhys will be 100% static. */
586 uint32_t idPageX : 28;
587 /** The page type (PGMPAGETYPE). */
588 uint32_t u3Type : 3;
589 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
590 uint32_t u2HandlerPhysStateX : 2;
591 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
592 uint32_t u2HandlerVirtStateX : 2;
593 uint32_t u29B : 25;
594} PGMPAGE;
595AssertCompileSize(PGMPAGE, 16);
596/** Pointer to a physical guest page. */
597typedef PGMPAGE *PPGMPAGE;
598/** Pointer to a const physical guest page. */
599typedef const PGMPAGE *PCPGMPAGE;
600/** Pointer to a physical guest page pointer. */
601typedef PPGMPAGE *PPPGMPAGE;
602
603
604/**
605 * Clears the page structure.
606 * @param pPage Pointer to the physical guest page tracking structure.
607 */
608#define PGM_PAGE_CLEAR(pPage) \
609 do { \
610 (pPage)->HCPhys = 0; \
611 (pPage)->u2StateX = 0; \
612 (pPage)->fWrittenToX = 0; \
613 (pPage)->fSomethingElse = 0; \
614 (pPage)->idPageX = 0; \
615 (pPage)->u3Type = 0; \
616 (pPage)->u29B = 0; \
617 } while (0)
618
619/**
620 * Initializes the page structure.
621 * @param pPage Pointer to the physical guest page tracking structure.
622 */
623#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
624 do { \
625 (pPage)->HCPhys = (_HCPhys); \
626 (pPage)->u2StateX = (_uState); \
627 (pPage)->fWrittenToX = 0; \
628 (pPage)->fSomethingElse = 0; \
629 (pPage)->idPageX = (_idPage); \
630 /*(pPage)->u3Type = (_uType); - later */ \
631 PGM_PAGE_SET_TYPE(pPage, _uType); \
632 (pPage)->u29B = 0; \
633 } while (0)
634
635/**
636 * Initializes the page structure of a ZERO page.
637 * @param pPage Pointer to the physical guest page tracking structure.
638 */
639#ifdef VBOX_WITH_NEW_PHYS_CODE
640# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
641 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
642#else
643# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
644 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645#endif
646/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
647# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
648 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649
650
651/** @name The Page state, PGMPAGE::u2StateX.
652 * @{ */
653/** The zero page.
654 * This is a per-VM page that's never ever mapped writable. */
655#define PGM_PAGE_STATE_ZERO 0
656/** A allocated page.
657 * This is a per-VM page allocated from the page pool (or wherever
658 * we get MMIO2 pages from if the type is MMIO2).
659 */
660#define PGM_PAGE_STATE_ALLOCATED 1
661/** A allocated page that's being monitored for writes.
662 * The shadow page table mappings are read-only. When a write occurs, the
663 * fWrittenTo member is set, the page remapped as read-write and the state
664 * moved back to allocated. */
665#define PGM_PAGE_STATE_WRITE_MONITORED 2
666/** The page is shared, aka. copy-on-write.
667 * This is a page that's shared with other VMs. */
668#define PGM_PAGE_STATE_SHARED 3
669/** @} */
670
671
672/**
673 * Gets the page state.
674 * @returns page state (PGM_PAGE_STATE_*).
675 * @param pPage Pointer to the physical guest page tracking structure.
676 */
677#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
678
679/**
680 * Sets the page state.
681 * @param pPage Pointer to the physical guest page tracking structure.
682 * @param _uState The new page state.
683 */
684#define PGM_PAGE_SET_STATE(pPage, _uState) \
685 do { (pPage)->u2StateX = (_uState); } while (0)
686
687
688/**
689 * Gets the host physical address of the guest page.
690 * @returns host physical address (RTHCPHYS).
691 * @param pPage Pointer to the physical guest page tracking structure.
692 */
693#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
694
695/**
696 * Sets the host physical address of the guest page.
697 * @param pPage Pointer to the physical guest page tracking structure.
698 * @param _HCPhys The new host physical address.
699 */
700#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
701 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
702 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
703
704/**
705 * Get the Page ID.
706 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
707 * @param pPage Pointer to the physical guest page tracking structure.
708 */
709#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
710/* later:
711#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
712 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
713*/
714/**
715 * Sets the Page ID.
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
719/* later:
720#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
721 | ((_idPage) & 0xfff) \
722 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
723*/
724
725/**
726 * Get the Chunk ID.
727 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
728 * @param pPage Pointer to the physical guest page tracking structure.
729 */
730#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
731/* later:
732#if GMM_CHUNKID_SHIFT == 12
733# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
734#elif GMM_CHUNKID_SHIFT > 12
735# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
736#elif GMM_CHUNKID_SHIFT < 12
737# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
738 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
739#else
740# error "GMM_CHUNKID_SHIFT isn't defined or something."
741#endif
742*/
743
744/**
745 * Get the index of the page within the allocaiton chunk.
746 * @returns The page index.
747 * @param pPage Pointer to the physical guest page tracking structure.
748 */
749#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
750/* later:
751#if GMM_CHUNKID_SHIFT <= 12
752# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
753#else
754# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
755 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
756#endif
757*/
758
759
760/**
761 * Gets the page type.
762 * @returns The page type.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 */
765#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
766
767/**
768 * Sets the page type.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 * @param _enmType The new page type (PGMPAGETYPE).
771 */
772#ifdef VBOX_WITH_NEW_PHYS_CODE
773#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
774 do { (pPage)->u3Type = (_enmType); } while (0)
775#else
776#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
777 do { \
778 (pPage)->u3Type = (_enmType); \
779 if ((_enmType) == PGMPAGETYPE_ROM) \
780 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
781 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
782 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
783 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
784 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
785 } while (0)
786#endif
787
788
789/**
790 * Checks if the page is 'reserved'.
791 * @returns true/false.
792 * @param pPage Pointer to the physical guest page tracking structure.
793 */
794#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
795
796/**
797 * Checks if the page is marked for MMIO.
798 * @returns true/false.
799 * @param pPage Pointer to the physical guest page tracking structure.
800 */
801#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
802
803/**
804 * Checks if the page is backed by the ZERO page.
805 * @returns true/false.
806 * @param pPage Pointer to the physical guest page tracking structure.
807 */
808#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
809
810/**
811 * Checks if the page is backed by a SHARED page.
812 * @returns true/false.
813 * @param pPage Pointer to the physical guest page tracking structure.
814 */
815#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
816
817
818/**
819 * Marks the paget as written to (for GMM change monitoring).
820 * @param pPage Pointer to the physical guest page tracking structure.
821 */
822#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
823
824/**
825 * Clears the written-to indicator.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
829
830/**
831 * Checks if the page was marked as written-to.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
836
837
838/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
839 *
840 * @remarks The values are assigned in order of priority, so we can calculate
841 * the correct state for a page with different handlers installed.
842 * @{ */
843/** No handler installed. */
844#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
845/** Monitoring is temporarily disabled. */
846#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
847/** Write access is monitored. */
848#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
849/** All access is monitored. */
850#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
851/** @} */
852
853/**
854 * Gets the physical access handler state of a page.
855 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 */
858#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
859
860/**
861 * Sets the physical access handler state of a page.
862 * @param pPage Pointer to the physical guest page tracking structure.
863 * @param _uState The new state value.
864 */
865#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
866 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
867
868/**
869 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
870 * @returns true/false
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
874
875/**
876 * Checks if the page has any active physical access handlers.
877 * @returns true/false
878 * @param pPage Pointer to the physical guest page tracking structure.
879 */
880#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
881
882
883/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
884 *
885 * @remarks The values are assigned in order of priority, so we can calculate
886 * the correct state for a page with different handlers installed.
887 * @{ */
888/** No handler installed. */
889#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
890/* 1 is reserved so the lineup is identical with the physical ones. */
891/** Write access is monitored. */
892#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
893/** All access is monitored. */
894#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
895/** @} */
896
897/**
898 * Gets the virtual access handler state of a page.
899 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
903
904/**
905 * Sets the virtual access handler state of a page.
906 * @param pPage Pointer to the physical guest page tracking structure.
907 * @param _uState The new state value.
908 */
909#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
910 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
911
912/**
913 * Checks if the page has any virtual access handlers.
914 * @returns true/false
915 * @param pPage Pointer to the physical guest page tracking structure.
916 */
917#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
918
919/**
920 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
921 * virtual handlers.
922 * @returns true/false
923 * @param pPage Pointer to the physical guest page tracking structure.
924 */
925#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
926
927
928
929/**
930 * Checks if the page has any access handlers, including temporarily disabled ones.
931 * @returns true/false
932 * @param pPage Pointer to the physical guest page tracking structure.
933 */
934#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
935 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
936 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
937
938/**
939 * Checks if the page has any active access handlers.
940 * @returns true/false
941 * @param pPage Pointer to the physical guest page tracking structure.
942 */
943#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
944 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
945 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
946
947/**
948 * Checks if the page has any active access handlers catching all accesses.
949 * @returns true/false
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
953 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
954 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
955
956
957/**
958 * Ram range for GC Phys to HC Phys conversion.
959 *
960 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
961 * conversions too, but we'll let MM handle that for now.
962 *
963 * This structure is used by linked lists in both GC and HC.
964 */
965typedef struct PGMRAMRANGE
966{
967 /** Pointer to the next RAM range - for R3. */
968 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
969 /** Pointer to the next RAM range - for R0. */
970 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
971 /** Pointer to the next RAM range - for RC. */
972 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
973 /** Pointer alignment. */
974 RTRCPTR RCPtrAlignment;
975 /** Start of the range. Page aligned. */
976 RTGCPHYS GCPhys;
977 /** Last address in the range (inclusive). Page aligned (-1). */
978 RTGCPHYS GCPhysLast;
979 /** Size of the range. (Page aligned of course). */
980 RTGCPHYS cb;
981 /** MM_RAM_* flags */
982 uint32_t fFlags;
983 uint32_t u32Alignment; /**< alignment. */
984#ifndef VBOX_WITH_NEW_PHYS_CODE
985 /** R3 virtual lookup ranges for chunks.
986 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
987 * @remarks This is occationally accessed from ring-0!! (not darwin) */
988# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
989 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
990# else
991 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
992# endif
993#endif
994 /** Start of the HC mapping of the range. This is only used for MMIO2. */
995 R3PTRTYPE(void *) pvR3;
996 /** The range description. */
997 R3PTRTYPE(const char *) pszDesc;
998
999 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1000#ifdef VBOX_WITH_NEW_PHYS_CODE
1001 uint32_t au32Reserved[2];
1002#elif HC_ARCH_BITS == 32
1003 uint32_t au32Reserved[1];
1004#endif
1005
1006 /** Array of physical guest page tracking structures. */
1007 PGMPAGE aPages[1];
1008} PGMRAMRANGE;
1009/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1010typedef PGMRAMRANGE *PPGMRAMRANGE;
1011
1012/** Return hc ptr corresponding to the ram range and physical offset */
1013#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1014 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1015 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1016
1017/**
1018 * Per page tracking structure for ROM image.
1019 *
1020 * A ROM image may have a shadow page, in which case we may have
1021 * two pages backing it. This structure contains the PGMPAGE for
1022 * both while PGMRAMRANGE have a copy of the active one. It is
1023 * important that these aren't out of sync in any regard other
1024 * than page pool tracking data.
1025 */
1026typedef struct PGMROMPAGE
1027{
1028 /** The page structure for the virgin ROM page. */
1029 PGMPAGE Virgin;
1030 /** The page structure for the shadow RAM page. */
1031 PGMPAGE Shadow;
1032 /** The current protection setting. */
1033 PGMROMPROT enmProt;
1034 /** Pad the structure size to a multiple of 8. */
1035 uint32_t u32Padding;
1036} PGMROMPAGE;
1037/** Pointer to a ROM page tracking structure. */
1038typedef PGMROMPAGE *PPGMROMPAGE;
1039
1040
1041/**
1042 * A registered ROM image.
1043 *
1044 * This is needed to keep track of ROM image since they generally
1045 * intrude into a PGMRAMRANGE. It also keeps track of additional
1046 * info like the two page sets (read-only virgin and read-write shadow),
1047 * the current state of each page.
1048 *
1049 * Because access handlers cannot easily be executed in a different
1050 * context, the ROM ranges needs to be accessible and in all contexts.
1051 */
1052typedef struct PGMROMRANGE
1053{
1054 /** Pointer to the next range - R3. */
1055 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1056 /** Pointer to the next range - R0. */
1057 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1058 /** Pointer to the next range - RC. */
1059 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1060 /** Pointer alignment */
1061 RTRCPTR GCPtrAlignment;
1062 /** Address of the range. */
1063 RTGCPHYS GCPhys;
1064 /** Address of the last byte in the range. */
1065 RTGCPHYS GCPhysLast;
1066 /** Size of the range. */
1067 RTGCPHYS cb;
1068 /** The flags (PGMPHYS_ROM_FLAG_*). */
1069 uint32_t fFlags;
1070 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1071 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1072 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1073 * This is used for strictness checks. */
1074 R3PTRTYPE(const void *) pvOriginal;
1075 /** The ROM description. */
1076 R3PTRTYPE(const char *) pszDesc;
1077 /** The per page tracking structures. */
1078 PGMROMPAGE aPages[1];
1079} PGMROMRANGE;
1080/** Pointer to a ROM range. */
1081typedef PGMROMRANGE *PPGMROMRANGE;
1082
1083
1084/**
1085 * A registered MMIO2 (= Device RAM) range.
1086 *
1087 * There are a few reason why we need to keep track of these
1088 * registrations. One of them is the deregistration & cleanup
1089 * stuff, while another is that the PGMRAMRANGE associated with
1090 * such a region may have to be removed from the ram range list.
1091 *
1092 * Overlapping with a RAM range has to be 100% or none at all. The
1093 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1094 * meditation will be raised if a partial overlap or an overlap of
1095 * ROM pages is encountered. On an overlap we will free all the
1096 * existing RAM pages and put in the ram range pages instead.
1097 */
1098typedef struct PGMMMIO2RANGE
1099{
1100 /** The owner of the range. (a device) */
1101 PPDMDEVINSR3 pDevInsR3;
1102 /** Pointer to the ring-3 mapping of the allocation. */
1103 RTR3PTR pvR3;
1104 /** Pointer to the next range - R3. */
1105 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1106 /** Whether it's mapped or not. */
1107 bool fMapped;
1108 /** Whether it's overlapping or not. */
1109 bool fOverlapping;
1110 /** The PCI region number.
1111 * @remarks This ASSUMES that nobody will ever really need to have multiple
1112 * PCI devices with matching MMIO region numbers on a single device. */
1113 uint8_t iRegion;
1114 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1115 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1116 /** The associated RAM range. */
1117 PGMRAMRANGE RamRange;
1118} PGMMMIO2RANGE;
1119/** Pointer to a MMIO2 range. */
1120typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1121
1122
1123
1124
1125/**
1126 * PGMPhysRead/Write cache entry
1127 */
1128typedef struct PGMPHYSCACHEENTRY
1129{
1130 /** R3 pointer to physical page. */
1131 R3PTRTYPE(uint8_t *) pbR3;
1132 /** GC Physical address for cache entry */
1133 RTGCPHYS GCPhys;
1134#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1135 RTGCPHYS u32Padding0; /**< alignment padding. */
1136#endif
1137} PGMPHYSCACHEENTRY;
1138
1139/**
1140 * PGMPhysRead/Write cache to reduce REM memory access overhead
1141 */
1142typedef struct PGMPHYSCACHE
1143{
1144 /** Bitmap of valid cache entries */
1145 uint64_t aEntries;
1146 /** Cache entries */
1147 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1148} PGMPHYSCACHE;
1149
1150
1151/** Pointer to an allocation chunk ring-3 mapping. */
1152typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1153/** Pointer to an allocation chunk ring-3 mapping pointer. */
1154typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1155
1156/**
1157 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1158 *
1159 * The primary tree (Core) uses the chunk id as key.
1160 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1161 */
1162typedef struct PGMCHUNKR3MAP
1163{
1164 /** The key is the chunk id. */
1165 AVLU32NODECORE Core;
1166 /** The key is the ageing sequence number. */
1167 AVLLU32NODECORE AgeCore;
1168 /** The current age thingy. */
1169 uint32_t iAge;
1170 /** The current reference count. */
1171 uint32_t volatile cRefs;
1172 /** The current permanent reference count. */
1173 uint32_t volatile cPermRefs;
1174 /** The mapping address. */
1175 void *pv;
1176} PGMCHUNKR3MAP;
1177
1178/**
1179 * Allocation chunk ring-3 mapping TLB entry.
1180 */
1181typedef struct PGMCHUNKR3MAPTLBE
1182{
1183 /** The chunk id. */
1184 uint32_t volatile idChunk;
1185#if HC_ARCH_BITS == 64
1186 uint32_t u32Padding; /**< alignment padding. */
1187#endif
1188 /** The chunk map. */
1189#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1190 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1191#else
1192 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1193#endif
1194} PGMCHUNKR3MAPTLBE;
1195/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1196typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1197
1198/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1199 * @remark Must be a power of two value. */
1200#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1201
1202/**
1203 * Allocation chunk ring-3 mapping TLB.
1204 *
1205 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1206 * At first glance this might look kinda odd since AVL trees are
1207 * supposed to give the most optimial lookup times of all trees
1208 * due to their balancing. However, take a tree with 1023 nodes
1209 * in it, that's 10 levels, meaning that most searches has to go
1210 * down 9 levels before they find what they want. This isn't fast
1211 * compared to a TLB hit. There is the factor of cache misses,
1212 * and of course the problem with trees and branch prediction.
1213 * This is why we use TLBs in front of most of the trees.
1214 *
1215 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1216 * difficult when we switch to the new inlined AVL trees (from kStuff).
1217 */
1218typedef struct PGMCHUNKR3MAPTLB
1219{
1220 /** The TLB entries. */
1221 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1222} PGMCHUNKR3MAPTLB;
1223
1224/**
1225 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1226 * @returns Chunk TLB index.
1227 * @param idChunk The Chunk ID.
1228 */
1229#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1230
1231
1232/**
1233 * Ring-3 guest page mapping TLB entry.
1234 * @remarks used in ring-0 as well at the moment.
1235 */
1236typedef struct PGMPAGER3MAPTLBE
1237{
1238 /** Address of the page. */
1239 RTGCPHYS volatile GCPhys;
1240 /** The guest page. */
1241#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1242 R3PTRTYPE(PPGMPAGE) volatile pPage;
1243#else
1244 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1245#endif
1246 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1247#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1248 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1249#else
1250 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1251#endif
1252 /** The address */
1253#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1254 R3PTRTYPE(void *) volatile pv;
1255#else
1256 R3R0PTRTYPE(void *) volatile pv;
1257#endif
1258#if HC_ARCH_BITS == 32
1259 uint32_t u32Padding; /**< alignment padding. */
1260#endif
1261} PGMPAGER3MAPTLBE;
1262/** Pointer to an entry in the HC physical TLB. */
1263typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1264
1265
1266/** The number of entries in the ring-3 guest page mapping TLB.
1267 * @remarks The value must be a power of two. */
1268#define PGM_PAGER3MAPTLB_ENTRIES 64
1269
1270/**
1271 * Ring-3 guest page mapping TLB.
1272 * @remarks used in ring-0 as well at the moment.
1273 */
1274typedef struct PGMPAGER3MAPTLB
1275{
1276 /** The TLB entries. */
1277 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1278} PGMPAGER3MAPTLB;
1279/** Pointer to the ring-3 guest page mapping TLB. */
1280typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1281
1282/**
1283 * Calculates the index of the TLB entry for the specified guest page.
1284 * @returns Physical TLB index.
1285 * @param GCPhys The guest physical address.
1286 */
1287#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1288
1289
1290/**
1291 * Mapping cache usage set entry.
1292 *
1293 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1294 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1295 * cache. If it's extended to include ring-3, well, then something will
1296 * have be changed here...
1297 */
1298typedef struct PGMMAPSETENTRY
1299{
1300 /** The mapping cache index. */
1301 uint16_t iPage;
1302 /** The number of references.
1303 * The max is UINT16_MAX - 1. */
1304 uint16_t cRefs;
1305 /** Pointer to the page. */
1306 RTR0PTR pvPage;
1307 /** The physical address for this entry. */
1308 RTHCPHYS HCPhys;
1309} PGMMAPSETENTRY;
1310/** Pointer to a mapping cache usage set entry. */
1311typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1312
1313/**
1314 * Mapping cache usage set.
1315 *
1316 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1317 * done during exits / traps. The set is
1318 */
1319typedef struct PGMMAPSET
1320{
1321 /** The number of occupied entries.
1322 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1323 * dynamic mappings. */
1324 uint32_t cEntries;
1325 /** The start of the current subset.
1326 * This is UINT32_MAX if no subset is currently open. */
1327 uint32_t iSubset;
1328 /** The index of the current CPU, only valid if the set is open. */
1329 int32_t iCpu;
1330 /** The entries. */
1331 PGMMAPSETENTRY aEntries[64];
1332 /** HCPhys -> iEntry fast lookup table.
1333 * Use PGMMAPSET_HASH for hashing.
1334 * The entries may or may not be valid, check against cEntries. */
1335 uint8_t aiHashTable[128];
1336} PGMMAPSET;
1337/** Pointer to the mapping cache set. */
1338typedef PGMMAPSET *PPGMMAPSET;
1339
1340/** PGMMAPSET::cEntries value for a closed set. */
1341#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1342
1343/** Hash function for aiHashTable. */
1344#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1345
1346/** The max fill size (strict builds). */
1347#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1348
1349
1350/** @name Context neutrual page mapper TLB.
1351 *
1352 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1353 * code is writting in a kind of context neutrual way. Time will show whether
1354 * this actually makes sense or not...
1355 *
1356 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1357 * context ends up using a global mapping cache on some platforms
1358 * (darwin).
1359 *
1360 * @{ */
1361/** @typedef PPGMPAGEMAPTLB
1362 * The page mapper TLB pointer type for the current context. */
1363/** @typedef PPGMPAGEMAPTLB
1364 * The page mapper TLB entry pointer type for the current context. */
1365/** @typedef PPGMPAGEMAPTLB
1366 * The page mapper TLB entry pointer pointer type for the current context. */
1367/** @def PGM_PAGEMAPTLB_ENTRIES
1368 * The number of TLB entries in the page mapper TLB for the current context. */
1369/** @def PGM_PAGEMAPTLB_IDX
1370 * Calculate the TLB index for a guest physical address.
1371 * @returns The TLB index.
1372 * @param GCPhys The guest physical address. */
1373/** @typedef PPGMPAGEMAP
1374 * Pointer to a page mapper unit for current context. */
1375/** @typedef PPPGMPAGEMAP
1376 * Pointer to a page mapper unit pointer for current context. */
1377#ifdef IN_RC
1378// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1379// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1380// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1381# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1382# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1383 typedef void * PPGMPAGEMAP;
1384 typedef void ** PPPGMPAGEMAP;
1385//#elif IN_RING0
1386// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1387// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1388// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1389//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1390//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1391// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1392// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1393#else
1394 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1395 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1396 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1397# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1398# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1399 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1400 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1401#endif
1402/** @} */
1403
1404
1405/** @name PGM Pool Indexes.
1406 * Aka. the unique shadow page identifier.
1407 * @{ */
1408/** NIL page pool IDX. */
1409#define NIL_PGMPOOL_IDX 0
1410/** The first normal index. */
1411#define PGMPOOL_IDX_FIRST_SPECIAL 1
1412#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1413/** Page directory (32-bit root). */
1414#define PGMPOOL_IDX_PD 1
1415/** Page Directory Pointer Table (PAE root). */
1416#define PGMPOOL_IDX_PDPT 2
1417/** AMD64 CR3 level index.*/
1418#define PGMPOOL_IDX_AMD64_CR3 3
1419/** Nested paging root.*/
1420#define PGMPOOL_IDX_NESTED_ROOT 4
1421/** The first normal index. */
1422#define PGMPOOL_IDX_FIRST 5
1423#else
1424/** Page directory (32-bit root). */
1425#define PGMPOOL_IDX_PD 1
1426/** The extended PAE page directory (2048 entries, works as root currently). */
1427#define PGMPOOL_IDX_PAE_PD 2
1428/** PAE Page Directory Table 0. */
1429#define PGMPOOL_IDX_PAE_PD_0 3
1430/** PAE Page Directory Table 1. */
1431#define PGMPOOL_IDX_PAE_PD_1 4
1432/** PAE Page Directory Table 2. */
1433#define PGMPOOL_IDX_PAE_PD_2 5
1434/** PAE Page Directory Table 3. */
1435#define PGMPOOL_IDX_PAE_PD_3 6
1436/** Page Directory Pointer Table (PAE root, not currently used). */
1437#define PGMPOOL_IDX_PDPT 7
1438/** AMD64 CR3 level index.*/
1439#define PGMPOOL_IDX_AMD64_CR3 8
1440/** Nested paging root.*/
1441#define PGMPOOL_IDX_NESTED_ROOT 9
1442/** The first normal index. */
1443#define PGMPOOL_IDX_FIRST 10
1444#endif
1445/** The last valid index. (inclusive, 14 bits) */
1446#define PGMPOOL_IDX_LAST 0x3fff
1447/** @} */
1448
1449/** The NIL index for the parent chain. */
1450#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1451
1452/**
1453 * Node in the chain linking a shadowed page to it's parent (user).
1454 */
1455#pragma pack(1)
1456typedef struct PGMPOOLUSER
1457{
1458 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1459 uint16_t iNext;
1460 /** The user page index. */
1461 uint16_t iUser;
1462 /** Index into the user table. */
1463 uint32_t iUserTable;
1464} PGMPOOLUSER, *PPGMPOOLUSER;
1465typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1466#pragma pack()
1467
1468
1469/** The NIL index for the phys ext chain. */
1470#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1471
1472/**
1473 * Node in the chain of physical cross reference extents.
1474 */
1475#pragma pack(1)
1476typedef struct PGMPOOLPHYSEXT
1477{
1478 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1479 uint16_t iNext;
1480 /** The user page index. */
1481 uint16_t aidx[3];
1482} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1483typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1484#pragma pack()
1485
1486
1487/**
1488 * The kind of page that's being shadowed.
1489 */
1490typedef enum PGMPOOLKIND
1491{
1492 /** The virtual invalid 0 entry. */
1493 PGMPOOLKIND_INVALID = 0,
1494 /** The entry is free (=unused). */
1495 PGMPOOLKIND_FREE,
1496
1497 /** Shw: 32-bit page table; Gst: no paging */
1498 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1499 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1500 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1501 /** Shw: 32-bit page table; Gst: 4MB page. */
1502 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1503 /** Shw: PAE page table; Gst: no paging */
1504 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1505 /** Shw: PAE page table; Gst: 32-bit page table. */
1506 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1507 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1508 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1509 /** Shw: PAE page table; Gst: PAE page table. */
1510 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1511 /** Shw: PAE page table; Gst: 2MB page. */
1512 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1513
1514 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1515 PGMPOOLKIND_32BIT_PD,
1516 /** Shw: 32-bit page directory. Gst: no paging. */
1517 PGMPOOLKIND_32BIT_PD_PHYS,
1518 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1519 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1520 /** Shw: PAE page directory; Gst: PAE page directory. */
1521 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1522 /** Shw: PAE page directory; Gst: no paging. */
1523 PGMPOOLKIND_PAE_PD_PHYS,
1524
1525 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1526 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1527 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1528 PGMPOOLKIND_PAE_PDPT,
1529 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1530 PGMPOOLKIND_PAE_PDPT_PHYS,
1531
1532 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1533 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1534 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1535 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1536 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1537 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1538 /** Shw: 64-bit page directory table; Gst: no paging */
1539 PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1540
1541 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1542 PGMPOOLKIND_64BIT_PML4,
1543
1544 /** Shw: EPT page directory pointer table; Gst: no paging */
1545 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1546 /** Shw: EPT page directory table; Gst: no paging */
1547 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1548 /** Shw: EPT page table; Gst: no paging */
1549 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1550
1551#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1552 /** Shw: Root 32-bit page directory. */
1553 PGMPOOLKIND_ROOT_32BIT_PD,
1554 /** Shw: Root PAE page directory */
1555 PGMPOOLKIND_ROOT_PAE_PD,
1556 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1557 PGMPOOLKIND_ROOT_PDPT,
1558#endif
1559 /** Shw: Root Nested paging table. */
1560 PGMPOOLKIND_ROOT_NESTED,
1561
1562 /** The last valid entry. */
1563 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1564} PGMPOOLKIND;
1565
1566
1567/**
1568 * The tracking data for a page in the pool.
1569 */
1570typedef struct PGMPOOLPAGE
1571{
1572 /** AVL node code with the (R3) physical address of this page. */
1573 AVLOHCPHYSNODECORE Core;
1574 /** Pointer to the R3 mapping of the page. */
1575#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1576 R3PTRTYPE(void *) pvPageR3;
1577#else
1578 R3R0PTRTYPE(void *) pvPageR3;
1579#endif
1580 /** The guest physical address. */
1581#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1582 uint32_t Alignment0;
1583#endif
1584 RTGCPHYS GCPhys;
1585 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1586 uint8_t enmKind;
1587 uint8_t bPadding;
1588 /** The index of this page. */
1589 uint16_t idx;
1590 /** The next entry in the list this page currently resides in.
1591 * It's either in the free list or in the GCPhys hash. */
1592 uint16_t iNext;
1593#ifdef PGMPOOL_WITH_USER_TRACKING
1594 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1595 uint16_t iUserHead;
1596 /** The number of present entries. */
1597 uint16_t cPresent;
1598 /** The first entry in the table which is present. */
1599 uint16_t iFirstPresent;
1600#endif
1601#ifdef PGMPOOL_WITH_MONITORING
1602 /** The number of modifications to the monitored page. */
1603 uint16_t cModifications;
1604 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1605 uint16_t iModifiedNext;
1606 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1607 uint16_t iModifiedPrev;
1608 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1609 uint16_t iMonitoredNext;
1610 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1611 uint16_t iMonitoredPrev;
1612#endif
1613#ifdef PGMPOOL_WITH_CACHE
1614 /** The next page in the age list. */
1615 uint16_t iAgeNext;
1616 /** The previous page in the age list. */
1617 uint16_t iAgePrev;
1618#endif /* PGMPOOL_WITH_CACHE */
1619 /** Used to indicate that the page is zeroed. */
1620 bool fZeroed;
1621 /** Used to indicate that a PT has non-global entries. */
1622 bool fSeenNonGlobal;
1623 /** Used to indicate that we're monitoring writes to the guest page. */
1624 bool fMonitored;
1625 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1626 * (All pages are in the age list.) */
1627 bool fCached;
1628 /** This is used by the R3 access handlers when invoked by an async thread.
1629 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1630 bool volatile fReusedFlushPending;
1631 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1632 * In these cases the access handler acts differently and will check
1633 * for mapping conflicts like the normal CR3 handler.
1634 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1635 * replaced by a list of pages which share access handler.
1636 */
1637 bool fCR3Mix;
1638} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1639
1640
1641#ifdef PGMPOOL_WITH_CACHE
1642/** The hash table size. */
1643# define PGMPOOL_HASH_SIZE 0x40
1644/** The hash function. */
1645# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1646#endif
1647
1648
1649/**
1650 * The shadow page pool instance data.
1651 *
1652 * It's all one big allocation made at init time, except for the
1653 * pages that is. The user nodes follows immediatly after the
1654 * page structures.
1655 */
1656typedef struct PGMPOOL
1657{
1658 /** The VM handle - R3 Ptr. */
1659 PVMR3 pVMR3;
1660 /** The VM handle - R0 Ptr. */
1661 PVMR0 pVMR0;
1662 /** The VM handle - RC Ptr. */
1663 PVMRC pVMRC;
1664 /** The max pool size. This includes the special IDs. */
1665 uint16_t cMaxPages;
1666 /** The current pool size. */
1667 uint16_t cCurPages;
1668 /** The head of the free page list. */
1669 uint16_t iFreeHead;
1670 /* Padding. */
1671 uint16_t u16Padding;
1672#ifdef PGMPOOL_WITH_USER_TRACKING
1673 /** Head of the chain of free user nodes. */
1674 uint16_t iUserFreeHead;
1675 /** The number of user nodes we've allocated. */
1676 uint16_t cMaxUsers;
1677 /** The number of present page table entries in the entire pool. */
1678 uint32_t cPresent;
1679 /** Pointer to the array of user nodes - RC pointer. */
1680 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1681 /** Pointer to the array of user nodes - R3 pointer. */
1682 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1683 /** Pointer to the array of user nodes - R0 pointer. */
1684 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1685#endif /* PGMPOOL_WITH_USER_TRACKING */
1686#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1687 /** Head of the chain of free phys ext nodes. */
1688 uint16_t iPhysExtFreeHead;
1689 /** The number of user nodes we've allocated. */
1690 uint16_t cMaxPhysExts;
1691 /** Pointer to the array of physical xref extent - RC pointer. */
1692 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1693 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1694 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1695 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1696 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1697#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1698#ifdef PGMPOOL_WITH_CACHE
1699 /** Hash table for GCPhys addresses. */
1700 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1701 /** The head of the age list. */
1702 uint16_t iAgeHead;
1703 /** The tail of the age list. */
1704 uint16_t iAgeTail;
1705 /** Set if the cache is enabled. */
1706 bool fCacheEnabled;
1707#endif /* PGMPOOL_WITH_CACHE */
1708#ifdef PGMPOOL_WITH_MONITORING
1709 /** Head of the list of modified pages. */
1710 uint16_t iModifiedHead;
1711 /** The current number of modified pages. */
1712 uint16_t cModifiedPages;
1713 /** Access handler, RC. */
1714 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1715 /** Access handler, R0. */
1716 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1717 /** Access handler, R3. */
1718 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1719 /** The access handler description (HC ptr). */
1720 R3PTRTYPE(const char *) pszAccessHandler;
1721#endif /* PGMPOOL_WITH_MONITORING */
1722 /** The number of pages currently in use. */
1723 uint16_t cUsedPages;
1724#ifdef VBOX_WITH_STATISTICS
1725 /** The high wather mark for cUsedPages. */
1726 uint16_t cUsedPagesHigh;
1727 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1728 /** Profiling pgmPoolAlloc(). */
1729 STAMPROFILEADV StatAlloc;
1730 /** Profiling pgmPoolClearAll(). */
1731 STAMPROFILE StatClearAll;
1732 /** Profiling pgmPoolFlushAllInt(). */
1733 STAMPROFILE StatFlushAllInt;
1734 /** Profiling pgmPoolFlushPage(). */
1735 STAMPROFILE StatFlushPage;
1736 /** Profiling pgmPoolFree(). */
1737 STAMPROFILE StatFree;
1738 /** Profiling time spent zeroing pages. */
1739 STAMPROFILE StatZeroPage;
1740# ifdef PGMPOOL_WITH_USER_TRACKING
1741 /** Profiling of pgmPoolTrackDeref. */
1742 STAMPROFILE StatTrackDeref;
1743 /** Profiling pgmTrackFlushGCPhysPT. */
1744 STAMPROFILE StatTrackFlushGCPhysPT;
1745 /** Profiling pgmTrackFlushGCPhysPTs. */
1746 STAMPROFILE StatTrackFlushGCPhysPTs;
1747 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1748 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1749 /** Number of times we've been out of user records. */
1750 STAMCOUNTER StatTrackFreeUpOneUser;
1751# endif
1752# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1753 /** Profiling deref activity related tracking GC physical pages. */
1754 STAMPROFILE StatTrackDerefGCPhys;
1755 /** Number of linear searches for a HCPhys in the ram ranges. */
1756 STAMCOUNTER StatTrackLinearRamSearches;
1757 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1758 STAMCOUNTER StamTrackPhysExtAllocFailures;
1759# endif
1760# ifdef PGMPOOL_WITH_MONITORING
1761 /** Profiling the RC/R0 access handler. */
1762 STAMPROFILE StatMonitorRZ;
1763 /** Times we've failed interpreting the instruction. */
1764 STAMCOUNTER StatMonitorRZEmulateInstr;
1765 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1766 STAMPROFILE StatMonitorRZFlushPage;
1767 /** Times we've detected fork(). */
1768 STAMCOUNTER StatMonitorRZFork;
1769 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1770 STAMPROFILE StatMonitorRZHandled;
1771 /** Times we've failed interpreting a patch code instruction. */
1772 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1773 /** Times we've failed interpreting a patch code instruction during flushing. */
1774 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1775 /** The number of times we've seen rep prefixes we can't handle. */
1776 STAMCOUNTER StatMonitorRZRepPrefix;
1777 /** Profiling the REP STOSD cases we've handled. */
1778 STAMPROFILE StatMonitorRZRepStosd;
1779
1780 /** Profiling the R3 access handler. */
1781 STAMPROFILE StatMonitorR3;
1782 /** Times we've failed interpreting the instruction. */
1783 STAMCOUNTER StatMonitorR3EmulateInstr;
1784 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1785 STAMPROFILE StatMonitorR3FlushPage;
1786 /** Times we've detected fork(). */
1787 STAMCOUNTER StatMonitorR3Fork;
1788 /** Profiling the R3 access we've handled (except REP STOSD). */
1789 STAMPROFILE StatMonitorR3Handled;
1790 /** The number of times we've seen rep prefixes we can't handle. */
1791 STAMCOUNTER StatMonitorR3RepPrefix;
1792 /** Profiling the REP STOSD cases we've handled. */
1793 STAMPROFILE StatMonitorR3RepStosd;
1794 /** The number of times we're called in an async thread an need to flush. */
1795 STAMCOUNTER StatMonitorR3Async;
1796 /** The high wather mark for cModifiedPages. */
1797 uint16_t cModifiedPagesHigh;
1798 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1799# endif
1800# ifdef PGMPOOL_WITH_CACHE
1801 /** The number of cache hits. */
1802 STAMCOUNTER StatCacheHits;
1803 /** The number of cache misses. */
1804 STAMCOUNTER StatCacheMisses;
1805 /** The number of times we've got a conflict of 'kind' in the cache. */
1806 STAMCOUNTER StatCacheKindMismatches;
1807 /** Number of times we've been out of pages. */
1808 STAMCOUNTER StatCacheFreeUpOne;
1809 /** The number of cacheable allocations. */
1810 STAMCOUNTER StatCacheCacheable;
1811 /** The number of uncacheable allocations. */
1812 STAMCOUNTER StatCacheUncacheable;
1813# endif
1814#elif HC_ARCH_BITS == 64
1815 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1816#endif
1817 /** The AVL tree for looking up a page by its HC physical address. */
1818 AVLOHCPHYSTREE HCPhysTree;
1819 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1820 /** Array of pages. (cMaxPages in length)
1821 * The Id is the index into thist array.
1822 */
1823 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1824} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1825
1826
1827/** @def PGMPOOL_PAGE_2_PTR
1828 * Maps a pool page pool into the current context.
1829 *
1830 * @returns VBox status code.
1831 * @param pVM The VM handle.
1832 * @param pPage The pool page.
1833 *
1834 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1835 * small page window employeed by that function. Be careful.
1836 * @remark There is no need to assert on the result.
1837 */
1838#if defined(IN_RC)
1839# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1840#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1841# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1842#elif defined(VBOX_STRICT)
1843# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1844DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1845{
1846 Assert(pPage->pvPageR3);
1847 return pPage->pvPageR3;
1848}
1849#else
1850# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1851#endif
1852
1853/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1854 * Maps a pool page pool into the current context.
1855 *
1856 * @returns VBox status code.
1857 * @param pPGM Pointer to the PGM instance data.
1858 * @param pPage The pool page.
1859 *
1860 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1861 * small page window employeed by that function. Be careful.
1862 * @remark There is no need to assert on the result.
1863 */
1864#if defined(IN_RC)
1865# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1866#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1867# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1868#else
1869# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1870#endif
1871
1872
1873
1874/**
1875 * Trees are using self relative offsets as pointers.
1876 * So, all its data, including the root pointer, must be in the heap for HC and GC
1877 * to have the same layout.
1878 */
1879typedef struct PGMTREES
1880{
1881 /** Physical access handlers (AVL range+offsetptr tree). */
1882 AVLROGCPHYSTREE PhysHandlers;
1883 /** Virtual access handlers (AVL range + GC ptr tree). */
1884 AVLROGCPTRTREE VirtHandlers;
1885 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1886 AVLROGCPHYSTREE PhysToVirtHandlers;
1887 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1888 AVLROGCPTRTREE HyperVirtHandlers;
1889} PGMTREES;
1890/** Pointer to PGM trees. */
1891typedef PGMTREES *PPGMTREES;
1892
1893
1894/** @name Paging mode macros
1895 * @{ */
1896#ifdef IN_RC
1897# define PGM_CTX(a,b) a##RC##b
1898# define PGM_CTX_STR(a,b) a "GC" b
1899# define PGM_CTX_DECL(type) VMMRCDECL(type)
1900#else
1901# ifdef IN_RING3
1902# define PGM_CTX(a,b) a##R3##b
1903# define PGM_CTX_STR(a,b) a "R3" b
1904# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1905# else
1906# define PGM_CTX(a,b) a##R0##b
1907# define PGM_CTX_STR(a,b) a "R0" b
1908# define PGM_CTX_DECL(type) VMMDECL(type)
1909# endif
1910#endif
1911
1912#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1913#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1914#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1915#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1916#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1917#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1918#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1919#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1920#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1921#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1922#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1923#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1924#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1925#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1926#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1927#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1928#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1929
1930#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1931#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1932#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1933#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1934#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1935#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1936#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1937#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1938#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1939#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1940#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1941#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1942#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1943#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1944#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1945#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1946#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1947
1948/* Shw_Gst */
1949#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1950#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1951#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1952#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1953#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1954#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1955#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1956#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1957#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1958#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1959#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1960#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1961#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1962#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1963#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1964#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1965#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1966#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1967#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1968
1969#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1970#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1971#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1972#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1973#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1974#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1975#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1976#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1977#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1978#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1979#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1980#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1981#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1982#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1983#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1984#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1985#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1986#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1987#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1988#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1989#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1990#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1991#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1992#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1993#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1994#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1995#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1996#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1997#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1998#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1999#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2000#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2001#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2002#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2003#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2004#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2005#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2006
2007#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2008#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2009/** @} */
2010
2011/**
2012 * Data for each paging mode.
2013 */
2014typedef struct PGMMODEDATA
2015{
2016 /** The guest mode type. */
2017 uint32_t uGstType;
2018 /** The shadow mode type. */
2019 uint32_t uShwType;
2020
2021 /** @name Function pointers for Shadow paging.
2022 * @{
2023 */
2024 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2025 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2026 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2027 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2028
2029 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2030 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2031
2032 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2033 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2034 /** @} */
2035
2036 /** @name Function pointers for Guest paging.
2037 * @{
2038 */
2039 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2040 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2041 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2042 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2043 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2044#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2045 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2046 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2047#endif
2048#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2049 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2050 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2051 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2052 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2053#endif
2054 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2055 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2056 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2057#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2058 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2059 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2060#endif
2061#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2062 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2063 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2064#endif
2065 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2066 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2067 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2068#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2069 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2070 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2071#endif
2072#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2073 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2074 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2075#endif
2076 /** @} */
2077
2078 /** @name Function pointers for Both Shadow and Guest paging.
2079 * @{
2080 */
2081 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2082 /* no pfnR3BthTrap0eHandler */
2083 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2084 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2085 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2086 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2087 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2088#ifdef VBOX_STRICT
2089 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2090#endif
2091 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2092 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2093
2094 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2095 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2096 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2097 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2098 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2099 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2100#ifdef VBOX_STRICT
2101 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2102#endif
2103 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2104 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2105
2106 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2107 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2108 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2109 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2110 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2111 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2112#ifdef VBOX_STRICT
2113 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2114#endif
2115 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2116 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2117 /** @} */
2118} PGMMODEDATA, *PPGMMODEDATA;
2119
2120
2121
2122/**
2123 * Converts a PGM pointer into a VM pointer.
2124 * @returns Pointer to the VM structure the PGM is part of.
2125 * @param pPGM Pointer to PGM instance data.
2126 */
2127#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2128
2129/**
2130 * PGM Data (part of VM)
2131 */
2132typedef struct PGM
2133{
2134 /** Offset to the VM structure. */
2135 RTINT offVM;
2136 /** Offset of the PGMCPU structure relative to VMCPU. */
2137 int32_t offVCpu;
2138 /** Alignment padding. */
2139 int32_t i32Alignment;
2140
2141 /*
2142 * This will be redefined at least two more times before we're done, I'm sure.
2143 * The current code is only to get on with the coding.
2144 * - 2004-06-10: initial version, bird.
2145 * - 2004-07-02: 1st time, bird.
2146 * - 2004-10-18: 2nd time, bird.
2147 * - 2005-07-xx: 3rd time, bird.
2148 */
2149
2150 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2151 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2152 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2153 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2154
2155 /** The host paging mode. (This is what SUPLib reports.) */
2156 SUPPAGINGMODE enmHostMode;
2157 /** The shadow paging mode. */
2158 PGMMODE enmShadowMode;
2159 /** The guest paging mode. */
2160 PGMMODE enmGuestMode;
2161
2162 /** The current physical address representing in the guest CR3 register. */
2163 RTGCPHYS GCPhysCR3;
2164 /** Pointer to the 5 page CR3 content mapping.
2165 * The first page is always the CR3 (in some form) while the 4 other pages
2166 * are used of the PDs in PAE mode. */
2167 RTGCPTR GCPtrCR3Mapping;
2168#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2169 uint32_t u32Alignment;
2170#endif
2171 /** The physical address of the currently monitored guest CR3 page.
2172 * When this value is NIL_RTGCPHYS no page is being monitored. */
2173 RTGCPHYS GCPhysGstCR3Monitored;
2174
2175 /** @name 32-bit Guest Paging.
2176 * @{ */
2177 /** The guest's page directory, R3 pointer. */
2178 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2179#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2180 /** The guest's page directory, R0 pointer. */
2181 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2182#endif
2183 /** The guest's page directory, static RC mapping. */
2184 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2185 /** @} */
2186
2187 /** @name PAE Guest Paging.
2188 * @{ */
2189 /** The guest's page directory pointer table, static RC mapping. */
2190 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2191 /** The guest's page directory pointer table, R3 pointer. */
2192 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2193#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2194 /** The guest's page directory pointer table, R0 pointer. */
2195 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2196#endif
2197
2198 /** The guest's page directories, R3 pointers.
2199 * These are individual pointers and don't have to be adjecent.
2200 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2201 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2202 /** The guest's page directories, R0 pointers.
2203 * Same restrictions as apGstPaePDsR3. */
2204#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2205 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2206#endif
2207 /** The guest's page directories, static GC mapping.
2208 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2209 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2210 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2211 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2212 RTGCPHYS aGCPhysGstPaePDs[4];
2213 /** The physical addresses of the monitored guest page directories (PAE). */
2214 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2215 /** @} */
2216
2217 /** @name AMD64 Guest Paging.
2218 * @{ */
2219 /** The guest's page directory pointer table, R3 pointer. */
2220 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2221#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2222 /** The guest's page directory pointer table, R0 pointer. */
2223 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2224#endif
2225 /** @} */
2226
2227 /** @name Shadow paging
2228 * @{ */
2229 /** The root page table - R3 Ptr. */
2230 R3PTRTYPE(void *) pShwRootR3;
2231# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2232 /** The root page table - R0 Ptr. */
2233 R0PTRTYPE(void *) pShwRootR0;
2234# endif
2235 /** The root page table - RC Ptr. */
2236 RCPTRTYPE(void *) pShwRootRC;
2237# if HC_ARCH_BITS == 64
2238 uint32_t u32Padding1; /**< alignment padding. */
2239# endif
2240 /** The Physical Address (HC) of the current active shadow CR3. */
2241 RTHCPHYS HCPhysShwCR3;
2242 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2243 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2244 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2245 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2246 /** Pointer to the page of the current active CR3 - RC Ptr. */
2247 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2248 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2249 uint32_t iShwUser;
2250 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2251 uint32_t iShwUserTable;
2252# if HC_ARCH_BITS == 64
2253 RTRCPTR alignment6; /**< structure size alignment. */
2254# endif
2255 /** @} */
2256#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2257 /** @name 32-bit Shadow Paging
2258 * @{ */
2259 /** The 32-Bit PD - R3 Ptr. */
2260 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2261 /** The 32-Bit PD - R0 Ptr. */
2262 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2263 /** The 32-Bit PD - RC Ptr. */
2264 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2265# if HC_ARCH_BITS == 64
2266 uint32_t u32Padding10; /**< alignment padding. */
2267# endif
2268 /** The Physical Address (HC) of the 32-Bit PD. */
2269 RTHCPHYS HCPhysShw32BitPD;
2270 /** @} */
2271
2272 /** @name PAE Shadow Paging
2273 * @{ */
2274 /** The four PDs for the low 4GB - R3 Ptr.
2275 * Even though these are 4 pointers, what they point at is a single table.
2276 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2277 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2278# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2279 /** The four PDs for the low 4GB - R0 Ptr.
2280 * Same kind of mapping as apHCPaePDs. */
2281 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2282# endif
2283 /** The four PDs for the low 4GB - RC Ptr.
2284 * Same kind of mapping as apHCPaePDs. */
2285 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2286 /** The Physical Address (HC) of the four PDs for the low 4GB.
2287 * These are *NOT* 4 contiguous pages. */
2288 RTHCPHYS aHCPhysPaePDs[4];
2289 /** The Physical Address (HC) of the PAE PDPT. */
2290 RTHCPHYS HCPhysShwPaePdpt;
2291 /** The PAE PDPT - R3 Ptr. */
2292 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2293 /** The PAE PDPT - R0 Ptr. */
2294 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2295 /** The PAE PDPT - RC Ptr. */
2296 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2297 /** @} */
2298# if HC_ARCH_BITS == 64
2299 RTRCPTR alignment5; /**< structure size alignment. */
2300# endif
2301#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2302 /** @name Nested Shadow Paging
2303 * @{ */
2304 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2305 RTR3PTR pShwNestedRootR3;
2306# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2307 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2308 RTR0PTR pShwNestedRootR0;
2309# endif
2310 /** The Physical Address (HC) of the nested paging root. */
2311 RTHCPHYS HCPhysShwNestedRoot;
2312 /** @} */
2313
2314 /** @name Function pointers for Shadow paging.
2315 * @{
2316 */
2317 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2318 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2319 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2320 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2321
2322 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2323 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2324
2325 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2326 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2327
2328 /** @} */
2329
2330 /** @name Function pointers for Guest paging.
2331 * @{
2332 */
2333 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2334 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2335 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2336 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2337 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2338#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2339 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2340 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2341#endif
2342#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2343 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2344 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2345 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2346 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2347#endif
2348 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2349 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2350 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2351#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2352 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2353 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2354#endif
2355#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2356 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2357 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2358#endif
2359#if HC_ARCH_BITS == 64
2360 RTRCPTR alignment3; /**< structure size alignment. */
2361#endif
2362
2363 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2364 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2365 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2366#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2367 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2368 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2369#endif
2370#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2371 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2372 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2373#endif
2374 /** @} */
2375
2376 /** @name Function pointers for Both Shadow and Guest paging.
2377 * @{
2378 */
2379 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2380 /* no pfnR3BthTrap0eHandler */
2381 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2382 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2383 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2384 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2385 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2386 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2387 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2388 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2389
2390 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2391 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2392 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2393 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2394 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2395 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2396 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2397 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2398 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2399
2400 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2401 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2402 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2403 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2404 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2405 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2406 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2407 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2408 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2409#if HC_ARCH_BITS == 64
2410 RTRCPTR alignment2; /**< structure size alignment. */
2411#endif
2412 /** @} */
2413
2414 /** Pointer to SHW+GST mode data (function pointers).
2415 * The index into this table is made up from */
2416 R3PTRTYPE(PPGMMODEDATA) paModeData;
2417
2418 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2419 * This is sorted by physical address and contains no overlapping ranges. */
2420 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2421 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2422 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2423 /** RC pointer corresponding to PGM::pRamRangesR3. */
2424 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2425 /** The configured RAM size. */
2426 RTUINT cbRamSize;
2427
2428 /** Pointer to the list of ROM ranges - for R3.
2429 * This is sorted by physical address and contains no overlapping ranges. */
2430 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2431 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2432 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2433 /** RC pointer corresponding to PGM::pRomRangesR3. */
2434 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2435 /** Alignment padding. */
2436 RTRCPTR GCPtrPadding2;
2437
2438 /** Pointer to the list of MMIO2 ranges - for R3.
2439 * Registration order. */
2440 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2441
2442 /** PGM offset based trees - R3 Ptr. */
2443 R3PTRTYPE(PPGMTREES) pTreesR3;
2444 /** PGM offset based trees - R0 Ptr. */
2445 R0PTRTYPE(PPGMTREES) pTreesR0;
2446 /** PGM offset based trees - RC Ptr. */
2447 RCPTRTYPE(PPGMTREES) pTreesRC;
2448
2449 /** Linked list of GC mappings - for RC.
2450 * The list is sorted ascending on address.
2451 */
2452 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2453 /** Linked list of GC mappings - for HC.
2454 * The list is sorted ascending on address.
2455 */
2456 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2457 /** Linked list of GC mappings - for R0.
2458 * The list is sorted ascending on address.
2459 */
2460 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2461
2462 /** Indicates that PGMR3FinalizeMappings has been called and that further
2463 * PGMR3MapIntermediate calls will be rejected. */
2464 bool fFinalizedMappings;
2465 /** If set no conflict checks are required. (boolean) */
2466 bool fMappingsFixed;
2467 /** If set, then no mappings are put into the shadow page table. (boolean) */
2468 bool fDisableMappings;
2469 /** Size of fixed mapping */
2470 uint32_t cbMappingFixed;
2471 /** Base address (GC) of fixed mapping */
2472 RTGCPTR GCPtrMappingFixed;
2473#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2474 uint32_t u32Padding0; /**< alignment padding. */
2475#endif
2476
2477
2478 /** @name Intermediate Context
2479 * @{ */
2480 /** Pointer to the intermediate page directory - Normal. */
2481 R3PTRTYPE(PX86PD) pInterPD;
2482 /** Pointer to the intermedate page tables - Normal.
2483 * There are two page tables, one for the identity mapping and one for
2484 * the host context mapping (of the core code). */
2485 R3PTRTYPE(PX86PT) apInterPTs[2];
2486 /** Pointer to the intermedate page tables - PAE. */
2487 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2488 /** Pointer to the intermedate page directory - PAE. */
2489 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2490 /** Pointer to the intermedate page directory - PAE. */
2491 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2492 /** Pointer to the intermedate page-map level 4 - AMD64. */
2493 R3PTRTYPE(PX86PML4) pInterPaePML4;
2494 /** Pointer to the intermedate page directory - AMD64. */
2495 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2496 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2497 RTHCPHYS HCPhysInterPD;
2498 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2499 RTHCPHYS HCPhysInterPaePDPT;
2500 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2501 RTHCPHYS HCPhysInterPaePML4;
2502 /** @} */
2503
2504 /** Base address of the dynamic page mapping area.
2505 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2506 */
2507 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2508 /** The index of the last entry used in the dynamic page mapping area. */
2509 RTUINT iDynPageMapLast;
2510 /** Cache containing the last entries in the dynamic page mapping area.
2511 * The cache size is covering half of the mapping area. */
2512 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2513
2514 /** The address of the ring-0 mapping cache if we're making use of it. */
2515 RTR0PTR pvR0DynMapUsed;
2516#if HC_ARCH_BITS == 32
2517 RTR0PTR R0PtrPadding0; /**< Alignment. */
2518#endif
2519
2520
2521 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2522 RTGCPHYS GCPhys4MBPSEMask;
2523
2524 /** A20 gate mask.
2525 * Our current approach to A20 emulation is to let REM do it and don't bother
2526 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2527 * But whould need arrise, we'll subject physical addresses to this mask. */
2528 RTGCPHYS GCPhysA20Mask;
2529 /** A20 gate state - boolean! */
2530 RTUINT fA20Enabled;
2531
2532 /** What needs syncing (PGM_SYNC_*).
2533 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2534 * PGMFlushTLB, and PGMR3Load. */
2535 RTUINT fSyncFlags;
2536
2537 /** PGM critical section.
2538 * This protects the physical & virtual access handlers, ram ranges,
2539 * and the page flag updating (some of it anyway).
2540 */
2541 PDMCRITSECT CritSect;
2542
2543 /** Shadow Page Pool - R3 Ptr. */
2544 R3PTRTYPE(PPGMPOOL) pPoolR3;
2545 /** Shadow Page Pool - R0 Ptr. */
2546 R0PTRTYPE(PPGMPOOL) pPoolR0;
2547 /** Shadow Page Pool - RC Ptr. */
2548 RCPTRTYPE(PPGMPOOL) pPoolRC;
2549
2550 /** We're not in a state which permits writes to guest memory.
2551 * (Only used in strict builds.) */
2552 bool fNoMorePhysWrites;
2553
2554 /** Flush the cache on the next access. */
2555 bool fPhysCacheFlushPending;
2556/** @todo r=bird: Fix member names!*/
2557 /** PGMPhysRead cache */
2558 PGMPHYSCACHE pgmphysreadcache;
2559 /** PGMPhysWrite cache */
2560 PGMPHYSCACHE pgmphyswritecache;
2561
2562 /**
2563 * Data associated with managing the ring-3 mappings of the allocation chunks.
2564 */
2565 struct
2566 {
2567 /** The chunk tree, ordered by chunk id. */
2568#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2569 R3PTRTYPE(PAVLU32NODECORE) pTree;
2570#else
2571 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2572#endif
2573 /** The chunk mapping TLB. */
2574 PGMCHUNKR3MAPTLB Tlb;
2575 /** The number of mapped chunks. */
2576 uint32_t c;
2577 /** The maximum number of mapped chunks.
2578 * @cfgm PGM/MaxRing3Chunks */
2579 uint32_t cMax;
2580 /** The chunk age tree, ordered by ageing sequence number. */
2581 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2582 /** The current time. */
2583 uint32_t iNow;
2584 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2585 uint32_t AgeingCountdown;
2586 } ChunkR3Map;
2587
2588 /**
2589 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2590 */
2591 PGMPAGER3MAPTLB PhysTlbHC;
2592
2593 /** @name The zero page.
2594 * @{ */
2595 /** The host physical address of the zero page. */
2596 RTHCPHYS HCPhysZeroPg;
2597 /** The ring-3 mapping of the zero page. */
2598 RTR3PTR pvZeroPgR3;
2599 /** The ring-0 mapping of the zero page. */
2600 RTR0PTR pvZeroPgR0;
2601 /** The GC mapping of the zero page. */
2602 RTGCPTR pvZeroPgGC;
2603#if GC_ARCH_BITS != 32
2604 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2605#endif
2606 /** @}*/
2607
2608 /** The number of handy pages. */
2609 uint32_t cHandyPages;
2610 /**
2611 * Array of handy pages.
2612 *
2613 * This array is used in a two way communication between pgmPhysAllocPage
2614 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2615 * an intermediary.
2616 *
2617 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2618 * (The current size of 32 pages, means 128 KB of handy memory.)
2619 */
2620 GMMPAGEDESC aHandyPages[32];
2621
2622 /** @name Release Statistics
2623 * @{ */
2624 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2625 uint32_t cPrivatePages; /**< The number of private pages. */
2626 uint32_t cSharedPages; /**< The number of shared pages. */
2627 uint32_t cZeroPages; /**< The number of zero backed pages. */
2628 /** The number of times the guest has switched mode since last reset or statistics reset. */
2629 STAMCOUNTER cGuestModeChanges;
2630 /** The number of times we were forced to change the hypervisor region location. */
2631 STAMCOUNTER cRelocations;
2632 /** @} */
2633
2634#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2635 /** RC: Which statistic this \#PF should be attributed to. */
2636 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2637 RTRCPTR padding0;
2638 /** R0: Which statistic this \#PF should be attributed to. */
2639 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2640 RTR0PTR padding1;
2641
2642 /* Common */
2643# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2644 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2645 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2646 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2647 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2648 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2649 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2650# endif
2651 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2652 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2653
2654 /* R3 only: */
2655 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2656 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2657 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2658 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2659 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2660 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2661
2662 /* R0 only: */
2663 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2664 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2665 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2666 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2667 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2668 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2669 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2670 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2671 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2672 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2673 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2674 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2675 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2676 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2677 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2678 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2679 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2680 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2681 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2682 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2683 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2684 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2685 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2686 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2687 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2688 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2689
2690 /* RC only: */
2691 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2692 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2693 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2694 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2695
2696 /* RZ only: */
2697 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2698 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2699 STAMPROFILE StatRZTrap0eTimeSyncPT;
2700 STAMPROFILE StatRZTrap0eTimeMapping;
2701 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2702 STAMPROFILE StatRZTrap0eTimeHandlers;
2703 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2704 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2705 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2706 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2707 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2708 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2709 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2710 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2711 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2712 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2713 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2714 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2715 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2716 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2717 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2718 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2719 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2720 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2721 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2722 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2723 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2724 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2725 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2726 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2727 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2728 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2729 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2730 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2731 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2732 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2733 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2734 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2735 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2736 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2737 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2738 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2739 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2740 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2741 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2742 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2743 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2744 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2745 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2746
2747 /* HC - R3 and (maybe) R0: */
2748
2749 /* RZ & R3: */
2750 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2751 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2752 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2753 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2754 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2755 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2756 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2757 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2758 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2759 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2760 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2761 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2762 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2763 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2764 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2765 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2766 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2767 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2768 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2769 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2770 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2771 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2772 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2773 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2774 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2775 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2776 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2777 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2778 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2779 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2780 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2781 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2782 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2783 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2784 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2785 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2786 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2787 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2788 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2789 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2790 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2791 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2792 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2793 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2794 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2795 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2796 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2797/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2798 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2799 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2800 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2801 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2802 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2803 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2804
2805 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2806 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2807 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2808 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2809 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2810 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2811 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2812 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2813 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2814 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2815 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2816 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2817 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2818 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2819 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2820 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2821 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2822 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2823 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2824 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2825 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2826 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2827 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2828 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2829 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2830 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2831 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2832 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2833 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2834 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2835 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2836 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2837 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2838 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2839 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2840 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2841 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2842 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2843 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2844 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2845 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2846 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2847 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2848 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2849 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2850 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2851 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2852/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2853 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2854 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2855 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2856 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2857 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2858 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2859#endif /* VBOX_WITH_STATISTICS */
2860} PGM;
2861/** Pointer to the PGM instance data. */
2862typedef PGM *PPGM;
2863
2864
2865/**
2866 * PGMCPU Data (part of VMCPU).
2867 */
2868typedef struct PGMCPU
2869{
2870 /** Offset to the VMCPU structure. */
2871 RTINT offVMCPU;
2872 /** Automatically tracked physical memory mapping set.
2873 * Ring-0 and strict raw-mode builds. */
2874 PGMMAPSET AutoSet;
2875} PGMCPU;
2876/** Pointer to the per-cpu PGM data. */
2877typedef PGMCPU *PPGMCPU;
2878
2879
2880/** @name PGM::fSyncFlags Flags
2881 * @{
2882 */
2883/** Updates the virtual access handler state bit in PGMPAGE. */
2884#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2885/** Always sync CR3. */
2886#define PGM_SYNC_ALWAYS RT_BIT(1)
2887/** Check monitoring on next CR3 (re)load and invalidate page. */
2888#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2889/** Check guest mapping in SyncCR3. */
2890#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2891/** Clear the page pool (a light weight flush). */
2892#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2893/** @} */
2894
2895
2896__BEGIN_DECLS
2897
2898int pgmLock(PVM pVM);
2899void pgmUnlock(PVM pVM);
2900
2901VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2902VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2903
2904int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2905int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2906PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2907void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2908DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2909
2910void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2911bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2912int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2913DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2914#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2915void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2916#else
2917# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2918#endif
2919DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2920
2921
2922void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2923int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2924int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2925int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2926#ifdef IN_RING3
2927int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2928int pgmR3PhysRamReset(PVM pVM);
2929int pgmR3PhysRomReset(PVM pVM);
2930# ifndef VBOX_WITH_NEW_PHYS_CODE
2931int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2932# endif
2933
2934int pgmR3PoolInit(PVM pVM);
2935void pgmR3PoolRelocate(PVM pVM);
2936void pgmR3PoolReset(PVM pVM);
2937
2938#endif /* IN_RING3 */
2939#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2940int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2941#endif
2942#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2943void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2944#endif
2945int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2946PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2947void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2948void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2949int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2950void pgmPoolFlushAll(PVM pVM);
2951void pgmPoolClearAll(PVM pVM);
2952int pgmPoolSyncCR3(PVM pVM);
2953void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2954void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2955int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2956PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2957void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2958void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2959uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2960void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2961#ifdef PGMPOOL_WITH_MONITORING
2962# ifdef IN_RING3
2963void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2964# else
2965void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2966# endif
2967int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2968void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2969void pgmPoolMonitorModifiedClearAll(PVM pVM);
2970int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2971int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2972#endif
2973
2974#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2975void pgmMapClearShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iOldPDE);
2976void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2977#endif
2978
2979__END_DECLS
2980
2981
2982/**
2983 * Gets the PGMRAMRANGE structure for a guest page.
2984 *
2985 * @returns Pointer to the RAM range on success.
2986 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2987 *
2988 * @param pPGM PGM handle.
2989 * @param GCPhys The GC physical address.
2990 */
2991DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2992{
2993 /*
2994 * Optimize for the first range.
2995 */
2996 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2997 RTGCPHYS off = GCPhys - pRam->GCPhys;
2998 if (RT_UNLIKELY(off >= pRam->cb))
2999 {
3000 do
3001 {
3002 pRam = pRam->CTX_SUFF(pNext);
3003 if (RT_UNLIKELY(!pRam))
3004 break;
3005 off = GCPhys - pRam->GCPhys;
3006 } while (off >= pRam->cb);
3007 }
3008 return pRam;
3009}
3010
3011
3012/**
3013 * Gets the PGMPAGE structure for a guest page.
3014 *
3015 * @returns Pointer to the page on success.
3016 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3017 *
3018 * @param pPGM PGM handle.
3019 * @param GCPhys The GC physical address.
3020 */
3021DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3022{
3023 /*
3024 * Optimize for the first range.
3025 */
3026 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3027 RTGCPHYS off = GCPhys - pRam->GCPhys;
3028 if (RT_UNLIKELY(off >= pRam->cb))
3029 {
3030 do
3031 {
3032 pRam = pRam->CTX_SUFF(pNext);
3033 if (RT_UNLIKELY(!pRam))
3034 return NULL;
3035 off = GCPhys - pRam->GCPhys;
3036 } while (off >= pRam->cb);
3037 }
3038 return &pRam->aPages[off >> PAGE_SHIFT];
3039}
3040
3041
3042/**
3043 * Gets the PGMPAGE structure for a guest page.
3044 *
3045 * Old Phys code: Will make sure the page is present.
3046 *
3047 * @returns VBox status code.
3048 * @retval VINF_SUCCESS and a valid *ppPage on success.
3049 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3050 *
3051 * @param pPGM PGM handle.
3052 * @param GCPhys The GC physical address.
3053 * @param ppPage Where to store the page poitner on success.
3054 */
3055DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3056{
3057 /*
3058 * Optimize for the first range.
3059 */
3060 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3061 RTGCPHYS off = GCPhys - pRam->GCPhys;
3062 if (RT_UNLIKELY(off >= pRam->cb))
3063 {
3064 do
3065 {
3066 pRam = pRam->CTX_SUFF(pNext);
3067 if (RT_UNLIKELY(!pRam))
3068 {
3069 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3070 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3071 }
3072 off = GCPhys - pRam->GCPhys;
3073 } while (off >= pRam->cb);
3074 }
3075 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3076#ifndef VBOX_WITH_NEW_PHYS_CODE
3077
3078 /*
3079 * Make sure it's present.
3080 */
3081 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3082 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3083 {
3084#ifdef IN_RING3
3085 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3086#else
3087 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3088#endif
3089 if (RT_FAILURE(rc))
3090 {
3091 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3092 return rc;
3093 }
3094 Assert(rc == VINF_SUCCESS);
3095 }
3096#endif
3097 return VINF_SUCCESS;
3098}
3099
3100
3101
3102
3103/**
3104 * Gets the PGMPAGE structure for a guest page.
3105 *
3106 * Old Phys code: Will make sure the page is present.
3107 *
3108 * @returns VBox status code.
3109 * @retval VINF_SUCCESS and a valid *ppPage on success.
3110 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3111 *
3112 * @param pPGM PGM handle.
3113 * @param GCPhys The GC physical address.
3114 * @param ppPage Where to store the page poitner on success.
3115 * @param ppRamHint Where to read and store the ram list hint.
3116 * The caller initializes this to NULL before the call.
3117 */
3118DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3119{
3120 RTGCPHYS off;
3121 PPGMRAMRANGE pRam = *ppRamHint;
3122 if ( !pRam
3123 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3124 {
3125 pRam = pPGM->CTX_SUFF(pRamRanges);
3126 off = GCPhys - pRam->GCPhys;
3127 if (RT_UNLIKELY(off >= pRam->cb))
3128 {
3129 do
3130 {
3131 pRam = pRam->CTX_SUFF(pNext);
3132 if (RT_UNLIKELY(!pRam))
3133 {
3134 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3135 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3136 }
3137 off = GCPhys - pRam->GCPhys;
3138 } while (off >= pRam->cb);
3139 }
3140 *ppRamHint = pRam;
3141 }
3142 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3143#ifndef VBOX_WITH_NEW_PHYS_CODE
3144
3145 /*
3146 * Make sure it's present.
3147 */
3148 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3149 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3150 {
3151#ifdef IN_RING3
3152 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3153#else
3154 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3155#endif
3156 if (RT_FAILURE(rc))
3157 {
3158 *ppPage = NULL; /* Shut up annoying smart ass. */
3159 return rc;
3160 }
3161 Assert(rc == VINF_SUCCESS);
3162 }
3163#endif
3164 return VINF_SUCCESS;
3165}
3166
3167
3168/**
3169 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3170 *
3171 * @returns Pointer to the page on success.
3172 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3173 *
3174 * @param pPGM PGM handle.
3175 * @param GCPhys The GC physical address.
3176 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3177 */
3178DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3179{
3180 /*
3181 * Optimize for the first range.
3182 */
3183 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3184 RTGCPHYS off = GCPhys - pRam->GCPhys;
3185 if (RT_UNLIKELY(off >= pRam->cb))
3186 {
3187 do
3188 {
3189 pRam = pRam->CTX_SUFF(pNext);
3190 if (RT_UNLIKELY(!pRam))
3191 return NULL;
3192 off = GCPhys - pRam->GCPhys;
3193 } while (off >= pRam->cb);
3194 }
3195 *ppRam = pRam;
3196 return &pRam->aPages[off >> PAGE_SHIFT];
3197}
3198
3199
3200/**
3201 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3202 *
3203 * @returns Pointer to the page on success.
3204 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3205 *
3206 * @param pPGM PGM handle.
3207 * @param GCPhys The GC physical address.
3208 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3209 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3210 */
3211DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3212{
3213 /*
3214 * Optimize for the first range.
3215 */
3216 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3217 RTGCPHYS off = GCPhys - pRam->GCPhys;
3218 if (RT_UNLIKELY(off >= pRam->cb))
3219 {
3220 do
3221 {
3222 pRam = pRam->CTX_SUFF(pNext);
3223 if (RT_UNLIKELY(!pRam))
3224 {
3225 *ppRam = NULL; /* Shut up silly GCC warnings. */
3226 *ppPage = NULL; /* ditto */
3227 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3228 }
3229 off = GCPhys - pRam->GCPhys;
3230 } while (off >= pRam->cb);
3231 }
3232 *ppRam = pRam;
3233 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3234#ifndef VBOX_WITH_NEW_PHYS_CODE
3235
3236 /*
3237 * Make sure it's present.
3238 */
3239 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3240 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3241 {
3242#ifdef IN_RING3
3243 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3244#else
3245 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3246#endif
3247 if (RT_FAILURE(rc))
3248 {
3249 *ppPage = NULL; /* Shut up silly GCC warnings. */
3250 *ppPage = NULL; /* ditto */
3251 return rc;
3252 }
3253 Assert(rc == VINF_SUCCESS);
3254
3255 }
3256#endif
3257 return VINF_SUCCESS;
3258}
3259
3260
3261/**
3262 * Convert GC Phys to HC Phys.
3263 *
3264 * @returns VBox status.
3265 * @param pPGM PGM handle.
3266 * @param GCPhys The GC physical address.
3267 * @param pHCPhys Where to store the corresponding HC physical address.
3268 *
3269 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3270 * Avoid when writing new code!
3271 */
3272DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3273{
3274 PPGMPAGE pPage;
3275 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3276 if (RT_FAILURE(rc))
3277 return rc;
3278 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3279 return VINF_SUCCESS;
3280}
3281
3282#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3283
3284/**
3285 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3286 * optimizes access to pages already in the set.
3287 *
3288 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3289 * @param pPGM Pointer to the PVM instance data.
3290 * @param HCPhys The physical address of the page.
3291 * @param ppv Where to store the mapping address.
3292 */
3293DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3294{
3295 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3296 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3297 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3298 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3299
3300 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3301 unsigned iEntry = pSet->aiHashTable[iHash];
3302 if ( iEntry < pSet->cEntries
3303 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3304 {
3305 *ppv = pSet->aEntries[iEntry].pvPage;
3306 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3307 }
3308 else
3309 {
3310 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3311 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3312 }
3313
3314 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3315 return VINF_SUCCESS;
3316}
3317
3318
3319/**
3320 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3321 * access to pages already in the set.
3322 *
3323 * @returns See PGMDynMapGCPage.
3324 * @param pPGM Pointer to the PVM instance data.
3325 * @param HCPhys The physical address of the page.
3326 * @param ppv Where to store the mapping address.
3327 */
3328DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3329{
3330 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3331 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3332
3333 /*
3334 * Get the ram range.
3335 */
3336 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3337 RTGCPHYS off = GCPhys - pRam->GCPhys;
3338 if (RT_UNLIKELY(off >= pRam->cb
3339 /** @todo || page state stuff */))
3340 {
3341 /* This case is not counted into StatR0DynMapGCPageInl. */
3342 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3343 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3344 }
3345
3346 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3347 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3348
3349 /*
3350 * pgmR0DynMapHCPageInlined with out stats.
3351 */
3352 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3353 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3354 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3355
3356 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3357 unsigned iEntry = pSet->aiHashTable[iHash];
3358 if ( iEntry < pSet->cEntries
3359 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3360 {
3361 *ppv = pSet->aEntries[iEntry].pvPage;
3362 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3363 }
3364 else
3365 {
3366 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3367 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3368 }
3369
3370 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3371 return VINF_SUCCESS;
3372}
3373
3374#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3375
3376#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3377/**
3378 * Maps the page into current context (RC and maybe R0).
3379 *
3380 * @returns pointer to the mapping.
3381 * @param pVM Pointer to the PGM instance data.
3382 * @param pPage The page.
3383 */
3384DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3385{
3386 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3387 {
3388 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3389 void *pv;
3390# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3391 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3392# else
3393 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3394# endif
3395 return pv;
3396 }
3397 return pgmPoolMapPageFallback(pPGM, pPage);
3398}
3399
3400/**
3401 * Temporarily maps one host page specified by HC physical address, returning
3402 * pointer within the page.
3403 *
3404 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3405 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3406 *
3407 * @returns The address corresponding to HCPhys.
3408 * @param pPGM Pointer to the PVM instance data.
3409 * @param HCPhys HC Physical address of the page.
3410 */
3411DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3412{
3413 void *pv;
3414# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3415 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3416# else
3417 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3418# endif
3419 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3420 return pv;
3421}
3422#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3423
3424
3425#ifndef IN_RC
3426/**
3427 * Queries the Physical TLB entry for a physical guest page,
3428 * attemting to load the TLB entry if necessary.
3429 *
3430 * @returns VBox status code.
3431 * @retval VINF_SUCCESS on success
3432 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3433 * @param pPGM The PGM instance handle.
3434 * @param GCPhys The address of the guest page.
3435 * @param ppTlbe Where to store the pointer to the TLB entry.
3436 */
3437
3438DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3439{
3440 int rc;
3441 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3442 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3443 {
3444 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3445 rc = VINF_SUCCESS;
3446 }
3447 else
3448 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3449 *ppTlbe = pTlbe;
3450 return rc;
3451}
3452#endif /* !IN_RC */
3453
3454#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3455
3456# ifndef VBOX_WITH_NEW_PHYS_CODE
3457/**
3458 * Convert GC Phys to HC Virt.
3459 *
3460 * @returns VBox status.
3461 * @param pPGM PGM handle.
3462 * @param GCPhys The GC physical address.
3463 * @param pHCPtr Where to store the corresponding HC virtual address.
3464 *
3465 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3466 * pgmPoolMonitorGCPtr2CCPtr.
3467 */
3468DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3469{
3470 PPGMRAMRANGE pRam;
3471 PPGMPAGE pPage;
3472 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3473 if (RT_FAILURE(rc))
3474 {
3475 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3476 return rc;
3477 }
3478 RTGCPHYS off = GCPhys - pRam->GCPhys;
3479
3480 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3481 {
3482 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3483 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3484 return VINF_SUCCESS;
3485 }
3486 if (pRam->pvR3)
3487 {
3488 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3489 return VINF_SUCCESS;
3490 }
3491 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3492 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3493}
3494# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3495#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3496
3497/**
3498 * Convert GC Phys to HC Virt and HC Phys.
3499 *
3500 * @returns VBox status.
3501 * @param pPGM PGM handle.
3502 * @param GCPhys The GC physical address.
3503 * @param pHCPtr Where to store the corresponding HC virtual address.
3504 * @param pHCPhys Where to store the HC Physical address and its flags.
3505 *
3506 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3507 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3508 */
3509DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3510{
3511 PPGMRAMRANGE pRam;
3512 PPGMPAGE pPage;
3513 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3514 if (RT_FAILURE(rc))
3515 {
3516 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3517 *pHCPhys = 0; /* ditto */
3518 return rc;
3519 }
3520 RTGCPHYS off = GCPhys - pRam->GCPhys;
3521
3522 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3523 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3524 {
3525 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3526#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3527 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3528 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3529#else
3530 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3531#endif
3532 return VINF_SUCCESS;
3533 }
3534 if (pRam->pvR3)
3535 {
3536 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3537 return VINF_SUCCESS;
3538 }
3539 *pHCPtr = 0;
3540 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3541}
3542
3543
3544/**
3545 * Clears flags associated with a RAM address.
3546 *
3547 * @returns VBox status code.
3548 * @param pPGM PGM handle.
3549 * @param GCPhys Guest context physical address.
3550 * @param fFlags fFlags to clear. (Bits 0-11.)
3551 */
3552DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3553{
3554 PPGMPAGE pPage;
3555 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3556 if (RT_FAILURE(rc))
3557 return rc;
3558
3559 fFlags &= ~X86_PTE_PAE_PG_MASK;
3560 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3561 return VINF_SUCCESS;
3562}
3563
3564
3565/**
3566 * Clears flags associated with a RAM address.
3567 *
3568 * @returns VBox status code.
3569 * @param pPGM PGM handle.
3570 * @param GCPhys Guest context physical address.
3571 * @param fFlags fFlags to clear. (Bits 0-11.)
3572 * @param ppRamHint Where to read and store the ram list hint.
3573 * The caller initializes this to NULL before the call.
3574 */
3575DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3576{
3577 PPGMPAGE pPage;
3578 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3579 if (RT_FAILURE(rc))
3580 return rc;
3581
3582 fFlags &= ~X86_PTE_PAE_PG_MASK;
3583 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3584 return VINF_SUCCESS;
3585}
3586
3587
3588/**
3589 * Sets (bitwise OR) flags associated with a RAM address.
3590 *
3591 * @returns VBox status code.
3592 * @param pPGM PGM handle.
3593 * @param GCPhys Guest context physical address.
3594 * @param fFlags fFlags to set clear. (Bits 0-11.)
3595 */
3596DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3597{
3598 PPGMPAGE pPage;
3599 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3600 if (RT_FAILURE(rc))
3601 return rc;
3602
3603 fFlags &= ~X86_PTE_PAE_PG_MASK;
3604 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3605 return VINF_SUCCESS;
3606}
3607
3608
3609/**
3610 * Sets (bitwise OR) flags associated with a RAM address.
3611 *
3612 * @returns VBox status code.
3613 * @param pPGM PGM handle.
3614 * @param GCPhys Guest context physical address.
3615 * @param fFlags fFlags to set clear. (Bits 0-11.)
3616 * @param ppRamHint Where to read and store the ram list hint.
3617 * The caller initializes this to NULL before the call.
3618 */
3619DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3620{
3621 PPGMPAGE pPage;
3622 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3623 if (RT_FAILURE(rc))
3624 return rc;
3625
3626 fFlags &= ~X86_PTE_PAE_PG_MASK;
3627 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3628 return VINF_SUCCESS;
3629}
3630
3631
3632/**
3633 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3634 * Takes PSE-36 into account.
3635 *
3636 * @returns guest physical address
3637 * @param pPGM Pointer to the PGM instance data.
3638 * @param Pde Guest Pde
3639 */
3640DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3641{
3642 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3643 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3644
3645 return GCPhys & pPGM->GCPhys4MBPSEMask;
3646}
3647
3648
3649/**
3650 * Gets the page directory entry for the specified address (32-bit paging).
3651 *
3652 * @returns The page directory entry in question.
3653 * @param pPGM Pointer to the PGM instance data.
3654 * @param GCPtr The address.
3655 */
3656DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3657{
3658#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3659 PCX86PD pGuestPD = 0;
3660 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3661 if (RT_FAILURE(rc))
3662 {
3663 X86PDE ZeroPde = {0};
3664 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3665 }
3666 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3667#else
3668 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3669#endif
3670}
3671
3672
3673/**
3674 * Gets the address of a specific page directory entry (32-bit paging).
3675 *
3676 * @returns Pointer the page directory entry in question.
3677 * @param pPGM Pointer to the PGM instance data.
3678 * @param GCPtr The address.
3679 */
3680DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3681{
3682#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3683 PX86PD pGuestPD = 0;
3684 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3685 AssertRCReturn(rc, 0);
3686 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3687#else
3688 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3689#endif
3690}
3691
3692
3693/**
3694 * Gets the address the guest page directory (32-bit paging).
3695 *
3696 * @returns Pointer the page directory entry in question.
3697 * @param pPGM Pointer to the PGM instance data.
3698 */
3699DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3700{
3701#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3702 PX86PD pGuestPD = 0;
3703 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3704 AssertRCReturn(rc, 0);
3705 return pGuestPD;
3706#else
3707 return pPGM->CTX_SUFF(pGst32BitPd);
3708#endif
3709}
3710
3711
3712/**
3713 * Gets the guest page directory pointer table.
3714 *
3715 * @returns Pointer to the page directory in question.
3716 * @returns NULL if the page directory is not present or on an invalid page.
3717 * @param pPGM Pointer to the PGM instance data.
3718 */
3719DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3720{
3721#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3722 PX86PDPT pGuestPDPT = 0;
3723 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3724 AssertRCReturn(rc, 0);
3725 return pGuestPDPT;
3726#else
3727 return pPGM->CTX_SUFF(pGstPaePdpt);
3728#endif
3729}
3730
3731
3732/**
3733 * Gets the guest page directory pointer table entry for the specified address.
3734 *
3735 * @returns Pointer to the page directory in question.
3736 * @returns NULL if the page directory is not present or on an invalid page.
3737 * @param pPGM Pointer to the PGM instance data.
3738 * @param GCPtr The address.
3739 */
3740DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3741{
3742 AssertGCPtr32(GCPtr);
3743
3744#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3745 PX86PDPT pGuestPDPT = 0;
3746 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3747 AssertRCReturn(rc, 0);
3748 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3749#else
3750 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3751#endif
3752}
3753
3754
3755/**
3756 * Gets the page directory for the specified address.
3757 *
3758 * @returns Pointer to the page directory in question.
3759 * @returns NULL if the page directory is not present or on an invalid page.
3760 * @param pPGM Pointer to the PGM instance data.
3761 * @param GCPtr The address.
3762 */
3763DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3764{
3765 AssertGCPtr32(GCPtr);
3766
3767#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3768 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3769 AssertReturn(pGuestPDPT, 0);
3770#else
3771 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3772#endif
3773 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3774 if (pGuestPDPT->a[iPdPt].n.u1Present)
3775 {
3776#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3777 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3778 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3779#endif
3780
3781 /* cache is out-of-sync. */
3782 PX86PDPAE pPD;
3783 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3784 if (RT_SUCCESS(rc))
3785 return pPD;
3786 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3787 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3788 }
3789 return NULL;
3790}
3791
3792
3793/**
3794 * Gets the page directory entry for the specified address.
3795 *
3796 * @returns Pointer to the page directory entry in question.
3797 * @returns NULL if the page directory is not present or on an invalid page.
3798 * @param pPGM Pointer to the PGM instance data.
3799 * @param GCPtr The address.
3800 */
3801DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3802{
3803 AssertGCPtr32(GCPtr);
3804
3805#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3806 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3807 AssertReturn(pGuestPDPT, 0);
3808#else
3809 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3810#endif
3811 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3812 if (pGuestPDPT->a[iPdPt].n.u1Present)
3813 {
3814 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3815#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3816 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3817 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3818#endif
3819
3820 /* The cache is out-of-sync. */
3821 PX86PDPAE pPD;
3822 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3823 if (RT_SUCCESS(rc))
3824 return &pPD->a[iPD];
3825 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3826 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3827 }
3828 return NULL;
3829}
3830
3831
3832/**
3833 * Gets the page directory entry for the specified address.
3834 *
3835 * @returns The page directory entry in question.
3836 * @returns A non-present entry if the page directory is not present or on an invalid page.
3837 * @param pPGM Pointer to the PGM instance data.
3838 * @param GCPtr The address.
3839 */
3840DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3841{
3842 AssertGCPtr32(GCPtr);
3843
3844#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3845 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3846 if (RT_LIKELY(pGuestPDPT))
3847#else
3848 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3849#endif
3850 {
3851 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3852 if (pGuestPDPT->a[iPdPt].n.u1Present)
3853 {
3854 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3855#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3856 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3857 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3858#endif
3859
3860 /* cache is out-of-sync. */
3861 PX86PDPAE pPD;
3862 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3863 if (RT_SUCCESS(rc))
3864 return pPD->a[iPD];
3865 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3866 }
3867 }
3868 X86PDEPAE ZeroPde = {0};
3869 return ZeroPde;
3870}
3871
3872
3873/**
3874 * Gets the page directory pointer table entry for the specified address
3875 * and returns the index into the page directory
3876 *
3877 * @returns Pointer to the page directory in question.
3878 * @returns NULL if the page directory is not present or on an invalid page.
3879 * @param pPGM Pointer to the PGM instance data.
3880 * @param GCPtr The address.
3881 * @param piPD Receives the index into the returned page directory
3882 * @param pPdpe Receives the page directory pointer entry. Optional.
3883 */
3884DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3885{
3886 AssertGCPtr32(GCPtr);
3887
3888#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3889 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3890 AssertReturn(pGuestPDPT, 0);
3891#else
3892 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3893#endif
3894 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3895 if (pPdpe)
3896 *pPdpe = pGuestPDPT->a[iPdPt];
3897 if (pGuestPDPT->a[iPdPt].n.u1Present)
3898 {
3899 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3900#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3901 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3902 {
3903 *piPD = iPD;
3904 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3905 }
3906#endif
3907
3908 /* cache is out-of-sync. */
3909 PX86PDPAE pPD;
3910 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3911 if (RT_SUCCESS(rc))
3912 {
3913 *piPD = iPD;
3914 return pPD;
3915 }
3916 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3917 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3918 }
3919 return NULL;
3920}
3921
3922#ifndef IN_RC
3923
3924/**
3925 * Gets the page map level-4 pointer for the guest.
3926 *
3927 * @returns Pointer to the PML4 page.
3928 * @param pPGM Pointer to the PGM instance data.
3929 */
3930DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3931{
3932#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3933 PX86PML4 pGuestPml4;
3934 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3935 AssertRCReturn(rc, NULL);
3936 return pGuestPml4;
3937#else
3938 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3939 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3940#endif
3941}
3942
3943
3944/**
3945 * Gets the pointer to a page map level-4 entry.
3946 *
3947 * @returns Pointer to the PML4 entry.
3948 * @param pPGM Pointer to the PGM instance data.
3949 * @param iPml4 The index.
3950 */
3951DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3952{
3953#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3954 PX86PML4 pGuestPml4;
3955 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3956 AssertRCReturn(rc, NULL);
3957 return &pGuestPml4->a[iPml4];
3958#else
3959 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3960 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3961#endif
3962}
3963
3964
3965/**
3966 * Gets a page map level-4 entry.
3967 *
3968 * @returns The PML4 entry.
3969 * @param pPGM Pointer to the PGM instance data.
3970 * @param iPml4 The index.
3971 */
3972DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3973{
3974#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3975 PX86PML4 pGuestPml4;
3976 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3977 if (RT_FAILURE(rc))
3978 {
3979 X86PML4E ZeroPml4e = {0};
3980 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3981 }
3982 return pGuestPml4->a[iPml4];
3983#else
3984 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3985 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3986#endif
3987}
3988
3989
3990/**
3991 * Gets the page directory pointer entry for the specified address.
3992 *
3993 * @returns Pointer to the page directory pointer entry in question.
3994 * @returns NULL if the page directory is not present or on an invalid page.
3995 * @param pPGM Pointer to the PGM instance data.
3996 * @param GCPtr The address.
3997 * @param ppPml4e Page Map Level-4 Entry (out)
3998 */
3999DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4000{
4001 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4002 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4003 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4004 if (pPml4e->n.u1Present)
4005 {
4006 PX86PDPT pPdpt;
4007 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4008 AssertRCReturn(rc, NULL);
4009
4010 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4011 return &pPdpt->a[iPdPt];
4012 }
4013 return NULL;
4014}
4015
4016
4017/**
4018 * Gets the page directory entry for the specified address.
4019 *
4020 * @returns The page directory entry in question.
4021 * @returns A non-present entry if the page directory is not present or on an invalid page.
4022 * @param pPGM Pointer to the PGM instance data.
4023 * @param GCPtr The address.
4024 * @param ppPml4e Page Map Level-4 Entry (out)
4025 * @param pPdpe Page directory pointer table entry (out)
4026 */
4027DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4028{
4029 X86PDEPAE ZeroPde = {0};
4030 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4031 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4032 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4033 if (pPml4e->n.u1Present)
4034 {
4035 PCX86PDPT pPdptTemp;
4036 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4037 AssertRCReturn(rc, ZeroPde);
4038
4039 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4040 *pPdpe = pPdptTemp->a[iPdPt];
4041 if (pPdptTemp->a[iPdPt].n.u1Present)
4042 {
4043 PCX86PDPAE pPD;
4044 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4045 AssertRCReturn(rc, ZeroPde);
4046
4047 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4048 return pPD->a[iPD];
4049 }
4050 }
4051
4052 return ZeroPde;
4053}
4054
4055
4056/**
4057 * Gets the page directory entry for the specified address.
4058 *
4059 * @returns The page directory entry in question.
4060 * @returns A non-present entry if the page directory is not present or on an invalid page.
4061 * @param pPGM Pointer to the PGM instance data.
4062 * @param GCPtr The address.
4063 */
4064DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4065{
4066 X86PDEPAE ZeroPde = {0};
4067 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4068 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4069 if (pGuestPml4->a[iPml4].n.u1Present)
4070 {
4071 PCX86PDPT pPdptTemp;
4072 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4073 AssertRCReturn(rc, ZeroPde);
4074
4075 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4076 if (pPdptTemp->a[iPdPt].n.u1Present)
4077 {
4078 PCX86PDPAE pPD;
4079 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4080 AssertRCReturn(rc, ZeroPde);
4081
4082 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4083 return pPD->a[iPD];
4084 }
4085 }
4086 return ZeroPde;
4087}
4088
4089
4090/**
4091 * Gets the page directory entry for the specified address.
4092 *
4093 * @returns Pointer to the page directory entry in question.
4094 * @returns NULL if the page directory is not present or on an invalid page.
4095 * @param pPGM Pointer to the PGM instance data.
4096 * @param GCPtr The address.
4097 */
4098DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4099{
4100 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4101 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4102 if (pGuestPml4->a[iPml4].n.u1Present)
4103 {
4104 PCX86PDPT pPdptTemp;
4105 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4106 AssertRCReturn(rc, NULL);
4107
4108 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4109 if (pPdptTemp->a[iPdPt].n.u1Present)
4110 {
4111 PX86PDPAE pPD;
4112 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4113 AssertRCReturn(rc, NULL);
4114
4115 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4116 return &pPD->a[iPD];
4117 }
4118 }
4119 return NULL;
4120}
4121
4122
4123/**
4124 * Gets the GUEST page directory pointer for the specified address.
4125 *
4126 * @returns The page directory in question.
4127 * @returns NULL if the page directory is not present or on an invalid page.
4128 * @param pPGM Pointer to the PGM instance data.
4129 * @param GCPtr The address.
4130 * @param ppPml4e Page Map Level-4 Entry (out)
4131 * @param pPdpe Page directory pointer table entry (out)
4132 * @param piPD Receives the index into the returned page directory
4133 */
4134DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4135{
4136 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4137 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4138 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4139 if (pPml4e->n.u1Present)
4140 {
4141 PCX86PDPT pPdptTemp;
4142 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4143 AssertRCReturn(rc, NULL);
4144
4145 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4146 *pPdpe = pPdptTemp->a[iPdPt];
4147 if (pPdptTemp->a[iPdPt].n.u1Present)
4148 {
4149 PX86PDPAE pPD;
4150 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4151 AssertRCReturn(rc, NULL);
4152
4153 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4154 return pPD;
4155 }
4156 }
4157 return 0;
4158}
4159
4160#endif /* !IN_RC */
4161
4162
4163/**
4164 * Gets the shadow page directory, 32-bit.
4165 *
4166 * @returns Pointer to the shadow 32-bit PD.
4167 * @param pPGM Pointer to the PGM instance data.
4168 */
4169DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4170{
4171#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4172 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4173#else
4174# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4175 PX86PD pShwPd;
4176 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4177 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4178 AssertRCReturn(rc, NULL);
4179 return pShwPd;
4180# else
4181 return pPGM->CTX_SUFF(pShw32BitPd);
4182# endif
4183#endif
4184}
4185
4186
4187/**
4188 * Gets the shadow page directory entry for the specified address, 32-bit.
4189 *
4190 * @returns Shadow 32-bit PDE.
4191 * @param pPGM Pointer to the PGM instance data.
4192 * @param GCPtr The address.
4193 */
4194DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4195{
4196 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4197
4198 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4199 if (!pShwPde)
4200 {
4201 X86PDE ZeroPde = {0};
4202 return ZeroPde;
4203 }
4204 return pShwPde->a[iPd];
4205}
4206
4207
4208/**
4209 * Gets the pointer to the shadow page directory entry for the specified
4210 * address, 32-bit.
4211 *
4212 * @returns Pointer to the shadow 32-bit PDE.
4213 * @param pPGM Pointer to the PGM instance data.
4214 * @param GCPtr The address.
4215 */
4216DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4217{
4218 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4219
4220 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4221 AssertReturn(pPde, NULL);
4222 return &pPde->a[iPd];
4223}
4224
4225
4226/**
4227 * Gets the shadow page pointer table, PAE.
4228 *
4229 * @returns Pointer to the shadow PAE PDPT.
4230 * @param pPGM Pointer to the PGM instance data.
4231 */
4232DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4233{
4234#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4235 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4236#else
4237# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4238 PX86PDPT pShwPdpt;
4239 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4240 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4241 AssertRCReturn(rc, 0);
4242 return pShwPdpt;
4243# else
4244 return pPGM->CTX_SUFF(pShwPaePdpt);
4245# endif
4246#endif
4247}
4248
4249
4250/**
4251 * Gets the shadow page directory for the specified address, PAE.
4252 *
4253 * @returns Pointer to the shadow PD.
4254 * @param pPGM Pointer to the PGM instance data.
4255 * @param GCPtr The address.
4256 */
4257DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4258{
4259#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4260 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4261 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4262
4263 /* Fetch the pgm pool shadow descriptor. */
4264 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4265 AssertReturn(pShwPde, NULL);
4266
4267 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4268#else
4269 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4270# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4271 PX86PDPAE pPD;
4272 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4273 AssertRCReturn(rc, 0);
4274 return pPD;
4275# else
4276 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4277 Assert(pPD);
4278 return pPD;
4279# endif
4280#endif
4281}
4282
4283
4284/**
4285 * Gets the shadow page directory entry, PAE.
4286 *
4287 * @returns PDE.
4288 * @param pPGM Pointer to the PGM instance data.
4289 * @param GCPtr The address.
4290 */
4291DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4292{
4293 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4294
4295 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4296 if (!pShwPde)
4297 {
4298 X86PDEPAE ZeroPde = {0};
4299 return ZeroPde;
4300 }
4301 return pShwPde->a[iPd];
4302}
4303
4304
4305/**
4306 * Gets the pointer to the shadow page directory entry for an address, PAE.
4307 *
4308 * @returns Pointer to the PDE.
4309 * @param pPGM Pointer to the PGM instance data.
4310 * @param GCPtr The address.
4311 */
4312DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4313{
4314 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4315
4316 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4317 AssertReturn(pPde, NULL);
4318 return &pPde->a[iPd];
4319}
4320
4321#ifndef IN_RC
4322/**
4323 * Gets the shadow page map level-4 pointer.
4324 *
4325 * @returns Pointer to the shadow PML4.
4326 * @param pPGM Pointer to the PGM instance data.
4327 */
4328DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4329{
4330#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4331 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4332#else
4333# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4334 PX86PML4 pShwPml4;
4335 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4336 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4337 AssertRCReturn(rc, 0);
4338 return pShwPml4;
4339# else
4340 Assert(pPGM->CTX_SUFF(pShwRoot));
4341 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4342# endif
4343#endif
4344}
4345
4346
4347/**
4348 * Gets the shadow page map level-4 entry for the specified address.
4349 *
4350 * @returns The entry.
4351 * @param pPGM Pointer to the PGM instance data.
4352 * @param GCPtr The address.
4353 */
4354DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4355{
4356 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4357 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4358
4359 if (!pShwPml4)
4360 {
4361 X86PML4E ZeroPml4e = {0};
4362 return ZeroPml4e;
4363 }
4364 return pShwPml4->a[iPml4];
4365}
4366
4367
4368/**
4369 * Gets the pointer to the specified shadow page map level-4 entry.
4370 *
4371 * @returns The entry.
4372 * @param pPGM Pointer to the PGM instance data.
4373 * @param iPml4 The PML4 index.
4374 */
4375DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4376{
4377 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4378 if (!pShwPml4)
4379 return NULL;
4380 return &pShwPml4->a[iPml4];
4381}
4382
4383
4384/**
4385 * Gets the GUEST page directory pointer for the specified address.
4386 *
4387 * @returns The page directory in question.
4388 * @returns NULL if the page directory is not present or on an invalid page.
4389 * @param pPGM Pointer to the PGM instance data.
4390 * @param GCPtr The address.
4391 * @param piPD Receives the index into the returned page directory
4392 */
4393DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4394{
4395 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4396 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4397 if (pGuestPml4->a[iPml4].n.u1Present)
4398 {
4399 PCX86PDPT pPdptTemp;
4400 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4401 AssertRCReturn(rc, NULL);
4402
4403 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4404 if (pPdptTemp->a[iPdPt].n.u1Present)
4405 {
4406 PX86PDPAE pPD;
4407 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4408 AssertRCReturn(rc, NULL);
4409
4410 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4411 return pPD;
4412 }
4413 }
4414 return NULL;
4415}
4416
4417#endif /* !IN_RC */
4418
4419/**
4420 * Checks if any of the specified page flags are set for the given page.
4421 *
4422 * @returns true if any of the flags are set.
4423 * @returns false if all the flags are clear.
4424 * @param pPGM PGM handle.
4425 * @param GCPhys The GC physical address.
4426 * @param fFlags The flags to check for.
4427 */
4428DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4429{
4430 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4431 return pPage
4432 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4433}
4434
4435
4436/**
4437 * Gets the page state for a physical handler.
4438 *
4439 * @returns The physical handler page state.
4440 * @param pCur The physical handler in question.
4441 */
4442DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4443{
4444 switch (pCur->enmType)
4445 {
4446 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4447 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4448
4449 case PGMPHYSHANDLERTYPE_MMIO:
4450 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4451 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4452
4453 default:
4454 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4455 }
4456}
4457
4458
4459/**
4460 * Gets the page state for a virtual handler.
4461 *
4462 * @returns The virtual handler page state.
4463 * @param pCur The virtual handler in question.
4464 * @remarks This should never be used on a hypervisor access handler.
4465 */
4466DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4467{
4468 switch (pCur->enmType)
4469 {
4470 case PGMVIRTHANDLERTYPE_WRITE:
4471 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4472 case PGMVIRTHANDLERTYPE_ALL:
4473 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4474 default:
4475 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4476 }
4477}
4478
4479
4480/**
4481 * Clears one physical page of a virtual handler
4482 *
4483 * @param pPGM Pointer to the PGM instance.
4484 * @param pCur Virtual handler structure
4485 * @param iPage Physical page index
4486 *
4487 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4488 * need to care about other handlers in the same page.
4489 */
4490DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4491{
4492 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4493
4494 /*
4495 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4496 */
4497#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4498 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4499 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4500 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4501#endif
4502 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4503 {
4504 /* We're the head of the alias chain. */
4505 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4506#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4507 AssertReleaseMsg(pRemove != NULL,
4508 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4509 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4510 AssertReleaseMsg(pRemove == pPhys2Virt,
4511 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4512 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4513 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4514 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4515#endif
4516 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4517 {
4518 /* Insert the next list in the alias chain into the tree. */
4519 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4520#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4521 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4522 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4523 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4524#endif
4525 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4526 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4527 AssertRelease(fRc);
4528 }
4529 }
4530 else
4531 {
4532 /* Locate the previous node in the alias chain. */
4533 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4534#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4535 AssertReleaseMsg(pPrev != pPhys2Virt,
4536 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4537 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4538#endif
4539 for (;;)
4540 {
4541 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4542 if (pNext == pPhys2Virt)
4543 {
4544 /* unlink. */
4545 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4546 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4547 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4548 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4549 else
4550 {
4551 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4552 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4553 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4554 }
4555 break;
4556 }
4557
4558 /* next */
4559 if (pNext == pPrev)
4560 {
4561#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4562 AssertReleaseMsg(pNext != pPrev,
4563 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4564 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4565#endif
4566 break;
4567 }
4568 pPrev = pNext;
4569 }
4570 }
4571 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4572 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4573 pPhys2Virt->offNextAlias = 0;
4574 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4575
4576 /*
4577 * Clear the ram flags for this page.
4578 */
4579 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4580 AssertReturnVoid(pPage);
4581 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4582}
4583
4584
4585/**
4586 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4587 *
4588 * @returns Pointer to the shadow page structure.
4589 * @param pPool The pool.
4590 * @param HCPhys The HC physical address of the shadow page.
4591 */
4592DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4593{
4594 /*
4595 * Look up the page.
4596 */
4597 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4598 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4599 return pPage;
4600}
4601
4602
4603/**
4604 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4605 *
4606 * @returns Pointer to the shadow page structure.
4607 * @param pPool The pool.
4608 * @param idx The pool page index.
4609 */
4610DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4611{
4612 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4613 return &pPool->aPages[idx];
4614}
4615
4616
4617#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4618/**
4619 * Clear references to guest physical memory.
4620 *
4621 * @param pPool The pool.
4622 * @param pPoolPage The pool page.
4623 * @param pPhysPage The physical guest page tracking structure.
4624 */
4625DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4626{
4627 /*
4628 * Just deal with the simple case here.
4629 */
4630# ifdef LOG_ENABLED
4631 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4632# endif
4633 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4634 if (cRefs == 1)
4635 {
4636 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4637 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4638 }
4639 else
4640 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4641 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4642}
4643#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4644
4645
4646#ifdef PGMPOOL_WITH_CACHE
4647/**
4648 * Moves the page to the head of the age list.
4649 *
4650 * This is done when the cached page is used in one way or another.
4651 *
4652 * @param pPool The pool.
4653 * @param pPage The cached page.
4654 * @todo inline in PGMInternal.h!
4655 */
4656DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4657{
4658 /*
4659 * Move to the head of the age list.
4660 */
4661 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4662 {
4663 /* unlink */
4664 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4665 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4666 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4667 else
4668 pPool->iAgeTail = pPage->iAgePrev;
4669
4670 /* insert at head */
4671 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4672 pPage->iAgeNext = pPool->iAgeHead;
4673 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4674 pPool->iAgeHead = pPage->idx;
4675 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4676 }
4677}
4678#endif /* PGMPOOL_WITH_CACHE */
4679
4680/**
4681 * Tells if mappings are to be put into the shadow page table or not
4682 *
4683 * @returns boolean result
4684 * @param pVM VM handle.
4685 */
4686
4687DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4688{
4689#ifdef IN_RING0
4690 /* There are no mappings in VT-x and AMD-V mode. */
4691 Assert(pPGM->fDisableMappings);
4692 return false;
4693#else
4694 return !pPGM->fDisableMappings;
4695#endif
4696}
4697
4698/** @} */
4699
4700#endif
4701
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