VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 16941

Last change on this file since 16941 was 16941, checked in by vboxsync, 16 years ago

Cleaned up + PAE write fix for 2nd PTE
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File size: 193.3 KB
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1/* $Id: PGMInternal.h 16941 2009-02-19 10:14:40Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59//#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186/** @} */
187
188/** @name Defines used to indicate the shadow and guest paging in the templates.
189 * @{ */
190#define PGM_TYPE_REAL 1
191#define PGM_TYPE_PROT 2
192#define PGM_TYPE_32BIT 3
193#define PGM_TYPE_PAE 4
194#define PGM_TYPE_AMD64 5
195#define PGM_TYPE_NESTED 6
196#define PGM_TYPE_EPT 7
197#define PGM_TYPE_MAX PGM_TYPE_EPT
198/** @} */
199
200/** Macro for checking if the guest is using paging.
201 * @param uGstType PGM_TYPE_*
202 * @param uShwType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_PAGING(uGstType, uShwType) \
206 ( (uGstType) >= PGM_TYPE_32BIT \
207 && (uShwType) != PGM_TYPE_NESTED \
208 && (uShwType) != PGM_TYPE_EPT)
209
210/** Macro for checking if the guest supports the NX bit.
211 * @param uGstType PGM_TYPE_*
212 * @param uShwType PGM_TYPE_*
213 * @remark ASSUMES certain order of the PGM_TYPE_* values.
214 */
215#define PGM_WITH_NX(uGstType, uShwType) \
216 ( (uGstType) >= PGM_TYPE_PAE \
217 && (uShwType) != PGM_TYPE_NESTED \
218 && (uShwType) != PGM_TYPE_EPT)
219
220
221/** @def PGM_HCPHYS_2_PTR
222 * Maps a HC physical page pool address to a virtual address.
223 *
224 * @returns VBox status code.
225 * @param pVM The VM handle.
226 * @param HCPhys The HC physical address to map to a virtual one.
227 * @param ppv Where to store the virtual address. No need to cast this.
228 *
229 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
230 * small page window employeed by that function. Be careful.
231 * @remark There is no need to assert on the result.
232 */
233#ifdef IN_RC
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
236#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
237# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
239#else
240# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
241 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
242#endif
243
244/** @def PGM_HCPHYS_2_PTR_BY_PGM
245 * Maps a HC physical page pool address to a virtual address.
246 *
247 * @returns VBox status code.
248 * @param pPGM The PGM instance data.
249 * @param HCPhys The HC physical address to map to a virtual one.
250 * @param ppv Where to store the virtual address. No need to cast this.
251 *
252 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
253 * small page window employeed by that function. Be careful.
254 * @remark There is no need to assert on the result.
255 */
256#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
257# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
259#else
260# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
261 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
262#endif
263
264/** @def PGM_GCPHYS_2_PTR
265 * Maps a GC physical page address to a virtual address.
266 *
267 * @returns VBox status code.
268 * @param pVM The VM handle.
269 * @param GCPhys The GC physical address to map to a virtual one.
270 * @param ppv Where to store the virtual address. No need to cast this.
271 *
272 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
273 * small page window employeed by that function. Be careful.
274 * @remark There is no need to assert on the result.
275 */
276#ifdef IN_RC
277# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
279#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
280# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
282#else
283# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
284 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
285#endif
286
287/** @def PGM_GCPHYS_2_PTR_BY_PGM
288 * Maps a GC physical page address to a virtual address.
289 *
290 * @returns VBox status code.
291 * @param pPGM Pointer to the PGM instance data.
292 * @param GCPhys The GC physical address to map to a virtual one.
293 * @param ppv Where to store the virtual address. No need to cast this.
294 *
295 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
296 * small page window employeed by that function. Be careful.
297 * @remark There is no need to assert on the result.
298 */
299#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
300# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
301 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
302#else
303# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
304 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
305#endif
306
307/** @def PGM_GCPHYS_2_PTR_EX
308 * Maps a unaligned GC physical page address to a virtual address.
309 *
310 * @returns VBox status code.
311 * @param pVM The VM handle.
312 * @param GCPhys The GC physical address to map to a virtual one.
313 * @param ppv Where to store the virtual address. No need to cast this.
314 *
315 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
316 * small page window employeed by that function. Be careful.
317 * @remark There is no need to assert on the result.
318 */
319#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
320# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
322#else
323# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
324 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
325#endif
326
327/** @def PGM_INVL_PG
328 * Invalidates a page when in GC does nothing in HC.
329 *
330 * @param GCVirt The virtual address of the page to invalidate.
331 */
332#ifdef IN_RC
333# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
334#elif defined(IN_RING0)
335# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
336#else
337# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
338#endif
339
340/** @def PGM_INVL_BIG_PG
341 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
342 *
343 * @param GCVirt The virtual address within the page directory to invalidate.
344 */
345#ifdef IN_RC
346# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
347#elif defined(IN_RING0)
348# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
349#else
350# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
351#endif
352
353/** @def PGM_INVL_GUEST_TLBS()
354 * Invalidates all guest TLBs.
355 */
356#ifdef IN_RC
357# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
358#elif defined(IN_RING0)
359# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
360#else
361# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
362#endif
363
364
365/**
366 * Structure for tracking GC Mappings.
367 *
368 * This structure is used by linked list in both GC and HC.
369 */
370typedef struct PGMMAPPING
371{
372 /** Pointer to next entry. */
373 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
374 /** Pointer to next entry. */
375 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
376 /** Pointer to next entry. */
377 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
378 /** Indicate whether this entry is finalized. */
379 bool fFinalized;
380 /** Start Virtual address. */
381 RTGCPTR GCPtr;
382 /** Last Virtual address (inclusive). */
383 RTGCPTR GCPtrLast;
384 /** Range size (bytes). */
385 RTGCPTR cb;
386 /** Pointer to relocation callback function. */
387 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
388 /** User argument to the callback. */
389 R3PTRTYPE(void *) pvUser;
390 /** Mapping description / name. For easing debugging. */
391 R3PTRTYPE(const char *) pszDesc;
392 /** Number of page tables. */
393 uint32_t cPTs;
394#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
395 uint32_t uPadding1; /**< Alignment padding. */
396#endif
397 /** Array of page table mapping data. Each entry
398 * describes one page table. The array can be longer
399 * than the declared length.
400 */
401 struct
402 {
403 /** The HC physical address of the page table. */
404 RTHCPHYS HCPhysPT;
405 /** The HC physical address of the first PAE page table. */
406 RTHCPHYS HCPhysPaePT0;
407 /** The HC physical address of the second PAE page table. */
408 RTHCPHYS HCPhysPaePT1;
409 /** The HC virtual address of the 32-bit page table. */
410 R3PTRTYPE(PX86PT) pPTR3;
411 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
412 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
413 /** The GC virtual address of the 32-bit page table. */
414 RCPTRTYPE(PX86PT) pPTRC;
415 /** The GC virtual address of the two PAE page table. */
416 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
417 /** The GC virtual address of the 32-bit page table. */
418 R0PTRTYPE(PX86PT) pPTR0;
419 /** The GC virtual address of the two PAE page table. */
420 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
421 } aPTs[1];
422} PGMMAPPING;
423/** Pointer to structure for tracking GC Mappings. */
424typedef struct PGMMAPPING *PPGMMAPPING;
425
426
427/**
428 * Physical page access handler structure.
429 *
430 * This is used to keep track of physical address ranges
431 * which are being monitored in some kind of way.
432 */
433typedef struct PGMPHYSHANDLER
434{
435 AVLROGCPHYSNODECORE Core;
436 /** Access type. */
437 PGMPHYSHANDLERTYPE enmType;
438 /** Number of pages to update. */
439 uint32_t cPages;
440 /** Pointer to R3 callback function. */
441 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
442 /** User argument for R3 handlers. */
443 R3PTRTYPE(void *) pvUserR3;
444 /** Pointer to R0 callback function. */
445 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
446 /** User argument for R0 handlers. */
447 R0PTRTYPE(void *) pvUserR0;
448 /** Pointer to GC callback function. */
449 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
450 /** User argument for RC handlers. */
451 RCPTRTYPE(void *) pvUserRC;
452 /** Description / Name. For easing debugging. */
453 R3PTRTYPE(const char *) pszDesc;
454#ifdef VBOX_WITH_STATISTICS
455 /** Profiling of this handler. */
456 STAMPROFILE Stat;
457#endif
458} PGMPHYSHANDLER;
459/** Pointer to a physical page access handler structure. */
460typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
461
462
463/**
464 * Cache node for the physical addresses covered by a virtual handler.
465 */
466typedef struct PGMPHYS2VIRTHANDLER
467{
468 /** Core node for the tree based on physical ranges. */
469 AVLROGCPHYSNODECORE Core;
470 /** Offset from this struct to the PGMVIRTHANDLER structure. */
471 int32_t offVirtHandler;
472 /** Offset of the next alias relative to this one.
473 * Bit 0 is used for indicating whether we're in the tree.
474 * Bit 1 is used for indicating that we're the head node.
475 */
476 int32_t offNextAlias;
477} PGMPHYS2VIRTHANDLER;
478/** Pointer to a phys to virtual handler structure. */
479typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
480
481/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
482 * node is in the tree. */
483#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
484/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
485 * node is in the head of an alias chain.
486 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
487#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
488/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
489#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
490
491
492/**
493 * Virtual page access handler structure.
494 *
495 * This is used to keep track of virtual address ranges
496 * which are being monitored in some kind of way.
497 */
498typedef struct PGMVIRTHANDLER
499{
500 /** Core node for the tree based on virtual ranges. */
501 AVLROGCPTRNODECORE Core;
502 /** Size of the range (in bytes). */
503 RTGCPTR cb;
504 /** Number of cache pages. */
505 uint32_t cPages;
506 /** Access type. */
507 PGMVIRTHANDLERTYPE enmType;
508 /** Pointer to the RC callback function. */
509 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
510#if HC_ARCH_BITS == 64
511 RTRCPTR padding;
512#endif
513 /** Pointer to the R3 callback function for invalidation. */
514 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
515 /** Pointer to the R3 callback function. */
516 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
517 /** Description / Name. For easing debugging. */
518 R3PTRTYPE(const char *) pszDesc;
519#ifdef VBOX_WITH_STATISTICS
520 /** Profiling of this handler. */
521 STAMPROFILE Stat;
522#endif
523 /** Array of cached physical addresses for the monitored ranged. */
524 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
525} PGMVIRTHANDLER;
526/** Pointer to a virtual page access handler structure. */
527typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
528
529
530/**
531 * Page type.
532 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
533 * @todo convert to \#defines.
534 */
535typedef enum PGMPAGETYPE
536{
537 /** The usual invalid zero entry. */
538 PGMPAGETYPE_INVALID = 0,
539 /** RAM page. (RWX) */
540 PGMPAGETYPE_RAM,
541 /** MMIO2 page. (RWX) */
542 PGMPAGETYPE_MMIO2,
543 /** Shadowed ROM. (RWX) */
544 PGMPAGETYPE_ROM_SHADOW,
545 /** ROM page. (R-X) */
546 PGMPAGETYPE_ROM,
547 /** MMIO page. (---) */
548 PGMPAGETYPE_MMIO,
549 /** End of valid entries. */
550 PGMPAGETYPE_END
551} PGMPAGETYPE;
552AssertCompile(PGMPAGETYPE_END < 7);
553
554/** @name Page type predicates.
555 * @{ */
556#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
557#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
558#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
559#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
560#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
561/** @} */
562
563
564/**
565 * A Physical Guest Page tracking structure.
566 *
567 * The format of this structure is complicated because we have to fit a lot
568 * of information into as few bits as possible. The format is also subject
569 * to change (there is one comming up soon). Which means that for we'll be
570 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
571 * accessess to the structure.
572 */
573typedef struct PGMPAGE
574{
575 /** The physical address and a whole lot of other stuff. All bits are used! */
576 RTHCPHYS HCPhys;
577 /** The page state. */
578 uint32_t u2StateX : 2;
579 /** Flag indicating that a write monitored page was written to when set. */
580 uint32_t fWrittenToX : 1;
581 /** For later. */
582 uint32_t fSomethingElse : 1;
583 /** The Page ID.
584 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
585 * The HCPhys will be 100% static. */
586 uint32_t idPageX : 28;
587 /** The page type (PGMPAGETYPE). */
588 uint32_t u3Type : 3;
589 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
590 uint32_t u2HandlerPhysStateX : 2;
591 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
592 uint32_t u2HandlerVirtStateX : 2;
593 uint32_t u29B : 25;
594} PGMPAGE;
595AssertCompileSize(PGMPAGE, 16);
596/** Pointer to a physical guest page. */
597typedef PGMPAGE *PPGMPAGE;
598/** Pointer to a const physical guest page. */
599typedef const PGMPAGE *PCPGMPAGE;
600/** Pointer to a physical guest page pointer. */
601typedef PPGMPAGE *PPPGMPAGE;
602
603
604/**
605 * Clears the page structure.
606 * @param pPage Pointer to the physical guest page tracking structure.
607 */
608#define PGM_PAGE_CLEAR(pPage) \
609 do { \
610 (pPage)->HCPhys = 0; \
611 (pPage)->u2StateX = 0; \
612 (pPage)->fWrittenToX = 0; \
613 (pPage)->fSomethingElse = 0; \
614 (pPage)->idPageX = 0; \
615 (pPage)->u3Type = 0; \
616 (pPage)->u29B = 0; \
617 } while (0)
618
619/**
620 * Initializes the page structure.
621 * @param pPage Pointer to the physical guest page tracking structure.
622 */
623#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
624 do { \
625 (pPage)->HCPhys = (_HCPhys); \
626 (pPage)->u2StateX = (_uState); \
627 (pPage)->fWrittenToX = 0; \
628 (pPage)->fSomethingElse = 0; \
629 (pPage)->idPageX = (_idPage); \
630 /*(pPage)->u3Type = (_uType); - later */ \
631 PGM_PAGE_SET_TYPE(pPage, _uType); \
632 (pPage)->u29B = 0; \
633 } while (0)
634
635/**
636 * Initializes the page structure of a ZERO page.
637 * @param pPage Pointer to the physical guest page tracking structure.
638 */
639#ifdef VBOX_WITH_NEW_PHYS_CODE
640# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
641 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
642#else
643# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
644 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645#endif
646/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
647# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
648 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649
650
651/** @name The Page state, PGMPAGE::u2StateX.
652 * @{ */
653/** The zero page.
654 * This is a per-VM page that's never ever mapped writable. */
655#define PGM_PAGE_STATE_ZERO 0
656/** A allocated page.
657 * This is a per-VM page allocated from the page pool (or wherever
658 * we get MMIO2 pages from if the type is MMIO2).
659 */
660#define PGM_PAGE_STATE_ALLOCATED 1
661/** A allocated page that's being monitored for writes.
662 * The shadow page table mappings are read-only. When a write occurs, the
663 * fWrittenTo member is set, the page remapped as read-write and the state
664 * moved back to allocated. */
665#define PGM_PAGE_STATE_WRITE_MONITORED 2
666/** The page is shared, aka. copy-on-write.
667 * This is a page that's shared with other VMs. */
668#define PGM_PAGE_STATE_SHARED 3
669/** @} */
670
671
672/**
673 * Gets the page state.
674 * @returns page state (PGM_PAGE_STATE_*).
675 * @param pPage Pointer to the physical guest page tracking structure.
676 */
677#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
678
679/**
680 * Sets the page state.
681 * @param pPage Pointer to the physical guest page tracking structure.
682 * @param _uState The new page state.
683 */
684#define PGM_PAGE_SET_STATE(pPage, _uState) \
685 do { (pPage)->u2StateX = (_uState); } while (0)
686
687
688/**
689 * Gets the host physical address of the guest page.
690 * @returns host physical address (RTHCPHYS).
691 * @param pPage Pointer to the physical guest page tracking structure.
692 */
693#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
694
695/**
696 * Sets the host physical address of the guest page.
697 * @param pPage Pointer to the physical guest page tracking structure.
698 * @param _HCPhys The new host physical address.
699 */
700#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
701 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
702 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
703
704/**
705 * Get the Page ID.
706 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
707 * @param pPage Pointer to the physical guest page tracking structure.
708 */
709#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
710/* later:
711#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
712 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
713*/
714/**
715 * Sets the Page ID.
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
719/* later:
720#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
721 | ((_idPage) & 0xfff) \
722 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
723*/
724
725/**
726 * Get the Chunk ID.
727 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
728 * @param pPage Pointer to the physical guest page tracking structure.
729 */
730#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
731/* later:
732#if GMM_CHUNKID_SHIFT == 12
733# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
734#elif GMM_CHUNKID_SHIFT > 12
735# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
736#elif GMM_CHUNKID_SHIFT < 12
737# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
738 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
739#else
740# error "GMM_CHUNKID_SHIFT isn't defined or something."
741#endif
742*/
743
744/**
745 * Get the index of the page within the allocaiton chunk.
746 * @returns The page index.
747 * @param pPage Pointer to the physical guest page tracking structure.
748 */
749#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
750/* later:
751#if GMM_CHUNKID_SHIFT <= 12
752# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
753#else
754# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
755 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
756#endif
757*/
758
759
760/**
761 * Gets the page type.
762 * @returns The page type.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 */
765#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
766
767/**
768 * Sets the page type.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 * @param _enmType The new page type (PGMPAGETYPE).
771 */
772#ifdef VBOX_WITH_NEW_PHYS_CODE
773#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
774 do { (pPage)->u3Type = (_enmType); } while (0)
775#else
776#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
777 do { \
778 (pPage)->u3Type = (_enmType); \
779 if ((_enmType) == PGMPAGETYPE_ROM) \
780 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
781 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
782 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
783 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
784 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
785 } while (0)
786#endif
787
788
789/**
790 * Checks if the page is 'reserved'.
791 * @returns true/false.
792 * @param pPage Pointer to the physical guest page tracking structure.
793 */
794#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
795
796/**
797 * Checks if the page is marked for MMIO.
798 * @returns true/false.
799 * @param pPage Pointer to the physical guest page tracking structure.
800 */
801#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
802
803/**
804 * Checks if the page is backed by the ZERO page.
805 * @returns true/false.
806 * @param pPage Pointer to the physical guest page tracking structure.
807 */
808#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
809
810/**
811 * Checks if the page is backed by a SHARED page.
812 * @returns true/false.
813 * @param pPage Pointer to the physical guest page tracking structure.
814 */
815#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
816
817
818/**
819 * Marks the paget as written to (for GMM change monitoring).
820 * @param pPage Pointer to the physical guest page tracking structure.
821 */
822#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
823
824/**
825 * Clears the written-to indicator.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
829
830/**
831 * Checks if the page was marked as written-to.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
836
837
838/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
839 *
840 * @remarks The values are assigned in order of priority, so we can calculate
841 * the correct state for a page with different handlers installed.
842 * @{ */
843/** No handler installed. */
844#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
845/** Monitoring is temporarily disabled. */
846#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
847/** Write access is monitored. */
848#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
849/** All access is monitored. */
850#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
851/** @} */
852
853/**
854 * Gets the physical access handler state of a page.
855 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 */
858#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
859
860/**
861 * Sets the physical access handler state of a page.
862 * @param pPage Pointer to the physical guest page tracking structure.
863 * @param _uState The new state value.
864 */
865#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
866 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
867
868/**
869 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
870 * @returns true/false
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
874
875/**
876 * Checks if the page has any active physical access handlers.
877 * @returns true/false
878 * @param pPage Pointer to the physical guest page tracking structure.
879 */
880#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
881
882
883/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
884 *
885 * @remarks The values are assigned in order of priority, so we can calculate
886 * the correct state for a page with different handlers installed.
887 * @{ */
888/** No handler installed. */
889#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
890/* 1 is reserved so the lineup is identical with the physical ones. */
891/** Write access is monitored. */
892#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
893/** All access is monitored. */
894#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
895/** @} */
896
897/**
898 * Gets the virtual access handler state of a page.
899 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
903
904/**
905 * Sets the virtual access handler state of a page.
906 * @param pPage Pointer to the physical guest page tracking structure.
907 * @param _uState The new state value.
908 */
909#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
910 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
911
912/**
913 * Checks if the page has any virtual access handlers.
914 * @returns true/false
915 * @param pPage Pointer to the physical guest page tracking structure.
916 */
917#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
918
919/**
920 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
921 * virtual handlers.
922 * @returns true/false
923 * @param pPage Pointer to the physical guest page tracking structure.
924 */
925#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
926
927
928
929/**
930 * Checks if the page has any access handlers, including temporarily disabled ones.
931 * @returns true/false
932 * @param pPage Pointer to the physical guest page tracking structure.
933 */
934#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
935 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
936 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
937
938/**
939 * Checks if the page has any active access handlers.
940 * @returns true/false
941 * @param pPage Pointer to the physical guest page tracking structure.
942 */
943#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
944 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
945 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
946
947/**
948 * Checks if the page has any active access handlers catching all accesses.
949 * @returns true/false
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
953 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
954 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
955
956
957/**
958 * Ram range for GC Phys to HC Phys conversion.
959 *
960 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
961 * conversions too, but we'll let MM handle that for now.
962 *
963 * This structure is used by linked lists in both GC and HC.
964 */
965typedef struct PGMRAMRANGE
966{
967 /** Pointer to the next RAM range - for R3. */
968 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
969 /** Pointer to the next RAM range - for R0. */
970 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
971 /** Pointer to the next RAM range - for RC. */
972 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
973 /** Pointer alignment. */
974 RTRCPTR RCPtrAlignment;
975 /** Start of the range. Page aligned. */
976 RTGCPHYS GCPhys;
977 /** Last address in the range (inclusive). Page aligned (-1). */
978 RTGCPHYS GCPhysLast;
979 /** Size of the range. (Page aligned of course). */
980 RTGCPHYS cb;
981 /** MM_RAM_* flags */
982 uint32_t fFlags;
983 uint32_t u32Alignment; /**< alignment. */
984#ifndef VBOX_WITH_NEW_PHYS_CODE
985 /** R3 virtual lookup ranges for chunks.
986 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
987 * @remarks This is occationally accessed from ring-0!! (not darwin) */
988# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
989 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
990# else
991 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
992# endif
993#endif
994 /** Start of the HC mapping of the range. This is only used for MMIO2. */
995 R3PTRTYPE(void *) pvR3;
996 /** The range description. */
997 R3PTRTYPE(const char *) pszDesc;
998
999 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1000#ifdef VBOX_WITH_NEW_PHYS_CODE
1001 uint32_t au32Reserved[2];
1002#elif HC_ARCH_BITS == 32
1003 uint32_t au32Reserved[1];
1004#endif
1005
1006 /** Array of physical guest page tracking structures. */
1007 PGMPAGE aPages[1];
1008} PGMRAMRANGE;
1009/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1010typedef PGMRAMRANGE *PPGMRAMRANGE;
1011
1012/** Return hc ptr corresponding to the ram range and physical offset */
1013#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1014 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1015 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1016
1017/**
1018 * Per page tracking structure for ROM image.
1019 *
1020 * A ROM image may have a shadow page, in which case we may have
1021 * two pages backing it. This structure contains the PGMPAGE for
1022 * both while PGMRAMRANGE have a copy of the active one. It is
1023 * important that these aren't out of sync in any regard other
1024 * than page pool tracking data.
1025 */
1026typedef struct PGMROMPAGE
1027{
1028 /** The page structure for the virgin ROM page. */
1029 PGMPAGE Virgin;
1030 /** The page structure for the shadow RAM page. */
1031 PGMPAGE Shadow;
1032 /** The current protection setting. */
1033 PGMROMPROT enmProt;
1034 /** Pad the structure size to a multiple of 8. */
1035 uint32_t u32Padding;
1036} PGMROMPAGE;
1037/** Pointer to a ROM page tracking structure. */
1038typedef PGMROMPAGE *PPGMROMPAGE;
1039
1040
1041/**
1042 * A registered ROM image.
1043 *
1044 * This is needed to keep track of ROM image since they generally
1045 * intrude into a PGMRAMRANGE. It also keeps track of additional
1046 * info like the two page sets (read-only virgin and read-write shadow),
1047 * the current state of each page.
1048 *
1049 * Because access handlers cannot easily be executed in a different
1050 * context, the ROM ranges needs to be accessible and in all contexts.
1051 */
1052typedef struct PGMROMRANGE
1053{
1054 /** Pointer to the next range - R3. */
1055 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1056 /** Pointer to the next range - R0. */
1057 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1058 /** Pointer to the next range - RC. */
1059 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1060 /** Pointer alignment */
1061 RTRCPTR GCPtrAlignment;
1062 /** Address of the range. */
1063 RTGCPHYS GCPhys;
1064 /** Address of the last byte in the range. */
1065 RTGCPHYS GCPhysLast;
1066 /** Size of the range. */
1067 RTGCPHYS cb;
1068 /** The flags (PGMPHYS_ROM_FLAG_*). */
1069 uint32_t fFlags;
1070 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1071 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1072 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1073 * This is used for strictness checks. */
1074 R3PTRTYPE(const void *) pvOriginal;
1075 /** The ROM description. */
1076 R3PTRTYPE(const char *) pszDesc;
1077 /** The per page tracking structures. */
1078 PGMROMPAGE aPages[1];
1079} PGMROMRANGE;
1080/** Pointer to a ROM range. */
1081typedef PGMROMRANGE *PPGMROMRANGE;
1082
1083
1084/**
1085 * A registered MMIO2 (= Device RAM) range.
1086 *
1087 * There are a few reason why we need to keep track of these
1088 * registrations. One of them is the deregistration & cleanup
1089 * stuff, while another is that the PGMRAMRANGE associated with
1090 * such a region may have to be removed from the ram range list.
1091 *
1092 * Overlapping with a RAM range has to be 100% or none at all. The
1093 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1094 * meditation will be raised if a partial overlap or an overlap of
1095 * ROM pages is encountered. On an overlap we will free all the
1096 * existing RAM pages and put in the ram range pages instead.
1097 */
1098typedef struct PGMMMIO2RANGE
1099{
1100 /** The owner of the range. (a device) */
1101 PPDMDEVINSR3 pDevInsR3;
1102 /** Pointer to the ring-3 mapping of the allocation. */
1103 RTR3PTR pvR3;
1104 /** Pointer to the next range - R3. */
1105 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1106 /** Whether it's mapped or not. */
1107 bool fMapped;
1108 /** Whether it's overlapping or not. */
1109 bool fOverlapping;
1110 /** The PCI region number.
1111 * @remarks This ASSUMES that nobody will ever really need to have multiple
1112 * PCI devices with matching MMIO region numbers on a single device. */
1113 uint8_t iRegion;
1114 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1115 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1116 /** The associated RAM range. */
1117 PGMRAMRANGE RamRange;
1118} PGMMMIO2RANGE;
1119/** Pointer to a MMIO2 range. */
1120typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1121
1122
1123
1124
1125/**
1126 * PGMPhysRead/Write cache entry
1127 */
1128typedef struct PGMPHYSCACHEENTRY
1129{
1130 /** R3 pointer to physical page. */
1131 R3PTRTYPE(uint8_t *) pbR3;
1132 /** GC Physical address for cache entry */
1133 RTGCPHYS GCPhys;
1134#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1135 RTGCPHYS u32Padding0; /**< alignment padding. */
1136#endif
1137} PGMPHYSCACHEENTRY;
1138
1139/**
1140 * PGMPhysRead/Write cache to reduce REM memory access overhead
1141 */
1142typedef struct PGMPHYSCACHE
1143{
1144 /** Bitmap of valid cache entries */
1145 uint64_t aEntries;
1146 /** Cache entries */
1147 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1148} PGMPHYSCACHE;
1149
1150
1151/** Pointer to an allocation chunk ring-3 mapping. */
1152typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1153/** Pointer to an allocation chunk ring-3 mapping pointer. */
1154typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1155
1156/**
1157 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1158 *
1159 * The primary tree (Core) uses the chunk id as key.
1160 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1161 */
1162typedef struct PGMCHUNKR3MAP
1163{
1164 /** The key is the chunk id. */
1165 AVLU32NODECORE Core;
1166 /** The key is the ageing sequence number. */
1167 AVLLU32NODECORE AgeCore;
1168 /** The current age thingy. */
1169 uint32_t iAge;
1170 /** The current reference count. */
1171 uint32_t volatile cRefs;
1172 /** The current permanent reference count. */
1173 uint32_t volatile cPermRefs;
1174 /** The mapping address. */
1175 void *pv;
1176} PGMCHUNKR3MAP;
1177
1178/**
1179 * Allocation chunk ring-3 mapping TLB entry.
1180 */
1181typedef struct PGMCHUNKR3MAPTLBE
1182{
1183 /** The chunk id. */
1184 uint32_t volatile idChunk;
1185#if HC_ARCH_BITS == 64
1186 uint32_t u32Padding; /**< alignment padding. */
1187#endif
1188 /** The chunk map. */
1189#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1190 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1191#else
1192 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1193#endif
1194} PGMCHUNKR3MAPTLBE;
1195/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1196typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1197
1198/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1199 * @remark Must be a power of two value. */
1200#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1201
1202/**
1203 * Allocation chunk ring-3 mapping TLB.
1204 *
1205 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1206 * At first glance this might look kinda odd since AVL trees are
1207 * supposed to give the most optimial lookup times of all trees
1208 * due to their balancing. However, take a tree with 1023 nodes
1209 * in it, that's 10 levels, meaning that most searches has to go
1210 * down 9 levels before they find what they want. This isn't fast
1211 * compared to a TLB hit. There is the factor of cache misses,
1212 * and of course the problem with trees and branch prediction.
1213 * This is why we use TLBs in front of most of the trees.
1214 *
1215 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1216 * difficult when we switch to the new inlined AVL trees (from kStuff).
1217 */
1218typedef struct PGMCHUNKR3MAPTLB
1219{
1220 /** The TLB entries. */
1221 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1222} PGMCHUNKR3MAPTLB;
1223
1224/**
1225 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1226 * @returns Chunk TLB index.
1227 * @param idChunk The Chunk ID.
1228 */
1229#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1230
1231
1232/**
1233 * Ring-3 guest page mapping TLB entry.
1234 * @remarks used in ring-0 as well at the moment.
1235 */
1236typedef struct PGMPAGER3MAPTLBE
1237{
1238 /** Address of the page. */
1239 RTGCPHYS volatile GCPhys;
1240 /** The guest page. */
1241#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1242 R3PTRTYPE(PPGMPAGE) volatile pPage;
1243#else
1244 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1245#endif
1246 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1247#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1248 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1249#else
1250 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1251#endif
1252 /** The address */
1253#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1254 R3PTRTYPE(void *) volatile pv;
1255#else
1256 R3R0PTRTYPE(void *) volatile pv;
1257#endif
1258#if HC_ARCH_BITS == 32
1259 uint32_t u32Padding; /**< alignment padding. */
1260#endif
1261} PGMPAGER3MAPTLBE;
1262/** Pointer to an entry in the HC physical TLB. */
1263typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1264
1265
1266/** The number of entries in the ring-3 guest page mapping TLB.
1267 * @remarks The value must be a power of two. */
1268#define PGM_PAGER3MAPTLB_ENTRIES 64
1269
1270/**
1271 * Ring-3 guest page mapping TLB.
1272 * @remarks used in ring-0 as well at the moment.
1273 */
1274typedef struct PGMPAGER3MAPTLB
1275{
1276 /** The TLB entries. */
1277 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1278} PGMPAGER3MAPTLB;
1279/** Pointer to the ring-3 guest page mapping TLB. */
1280typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1281
1282/**
1283 * Calculates the index of the TLB entry for the specified guest page.
1284 * @returns Physical TLB index.
1285 * @param GCPhys The guest physical address.
1286 */
1287#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1288
1289
1290/**
1291 * Mapping cache usage set entry.
1292 *
1293 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1294 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1295 * cache. If it's extended to include ring-3, well, then something will
1296 * have be changed here...
1297 */
1298typedef struct PGMMAPSETENTRY
1299{
1300 /** The mapping cache index. */
1301 uint16_t iPage;
1302 /** The number of references.
1303 * The max is UINT16_MAX - 1. */
1304 uint16_t cRefs;
1305 /** Pointer to the page. */
1306 RTR0PTR pvPage;
1307 /** The physical address for this entry. */
1308 RTHCPHYS HCPhys;
1309} PGMMAPSETENTRY;
1310/** Pointer to a mapping cache usage set entry. */
1311typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1312
1313/**
1314 * Mapping cache usage set.
1315 *
1316 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1317 * done during exits / traps. The set is
1318 */
1319typedef struct PGMMAPSET
1320{
1321 /** The number of occupied entries.
1322 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1323 * dynamic mappings. */
1324 uint32_t cEntries;
1325 /** The start of the current subset.
1326 * This is UINT32_MAX if no subset is currently open. */
1327 uint32_t iSubset;
1328 /** The index of the current CPU, only valid if the set is open. */
1329 int32_t iCpu;
1330 /** The entries. */
1331 PGMMAPSETENTRY aEntries[64];
1332 /** HCPhys -> iEntry fast lookup table.
1333 * Use PGMMAPSET_HASH for hashing.
1334 * The entries may or may not be valid, check against cEntries. */
1335 uint8_t aiHashTable[128];
1336} PGMMAPSET;
1337/** Pointer to the mapping cache set. */
1338typedef PGMMAPSET *PPGMMAPSET;
1339
1340/** PGMMAPSET::cEntries value for a closed set. */
1341#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1342
1343/** Hash function for aiHashTable. */
1344#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1345
1346/** The max fill size (strict builds). */
1347#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1348
1349
1350/** @name Context neutrual page mapper TLB.
1351 *
1352 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1353 * code is writting in a kind of context neutrual way. Time will show whether
1354 * this actually makes sense or not...
1355 *
1356 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1357 * context ends up using a global mapping cache on some platforms
1358 * (darwin).
1359 *
1360 * @{ */
1361/** @typedef PPGMPAGEMAPTLB
1362 * The page mapper TLB pointer type for the current context. */
1363/** @typedef PPGMPAGEMAPTLB
1364 * The page mapper TLB entry pointer type for the current context. */
1365/** @typedef PPGMPAGEMAPTLB
1366 * The page mapper TLB entry pointer pointer type for the current context. */
1367/** @def PGM_PAGEMAPTLB_ENTRIES
1368 * The number of TLB entries in the page mapper TLB for the current context. */
1369/** @def PGM_PAGEMAPTLB_IDX
1370 * Calculate the TLB index for a guest physical address.
1371 * @returns The TLB index.
1372 * @param GCPhys The guest physical address. */
1373/** @typedef PPGMPAGEMAP
1374 * Pointer to a page mapper unit for current context. */
1375/** @typedef PPPGMPAGEMAP
1376 * Pointer to a page mapper unit pointer for current context. */
1377#ifdef IN_RC
1378// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1379// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1380// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1381# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1382# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1383 typedef void * PPGMPAGEMAP;
1384 typedef void ** PPPGMPAGEMAP;
1385//#elif IN_RING0
1386// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1387// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1388// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1389//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1390//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1391// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1392// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1393#else
1394 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1395 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1396 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1397# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1398# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1399 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1400 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1401#endif
1402/** @} */
1403
1404
1405/** @name PGM Pool Indexes.
1406 * Aka. the unique shadow page identifier.
1407 * @{ */
1408/** NIL page pool IDX. */
1409#define NIL_PGMPOOL_IDX 0
1410/** The first normal index. */
1411#define PGMPOOL_IDX_FIRST_SPECIAL 1
1412#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1413/** Page directory (32-bit root). */
1414#define PGMPOOL_IDX_PD 1
1415/** Page Directory Pointer Table (PAE root). */
1416#define PGMPOOL_IDX_PDPT 2
1417/** AMD64 CR3 level index.*/
1418#define PGMPOOL_IDX_AMD64_CR3 3
1419/** Nested paging root.*/
1420#define PGMPOOL_IDX_NESTED_ROOT 4
1421/** The first normal index. */
1422#define PGMPOOL_IDX_FIRST 5
1423#else
1424/** Page directory (32-bit root). */
1425#define PGMPOOL_IDX_PD 1
1426/** The extended PAE page directory (2048 entries, works as root currently). */
1427#define PGMPOOL_IDX_PAE_PD 2
1428/** PAE Page Directory Table 0. */
1429#define PGMPOOL_IDX_PAE_PD_0 3
1430/** PAE Page Directory Table 1. */
1431#define PGMPOOL_IDX_PAE_PD_1 4
1432/** PAE Page Directory Table 2. */
1433#define PGMPOOL_IDX_PAE_PD_2 5
1434/** PAE Page Directory Table 3. */
1435#define PGMPOOL_IDX_PAE_PD_3 6
1436/** Page Directory Pointer Table (PAE root, not currently used). */
1437#define PGMPOOL_IDX_PDPT 7
1438/** AMD64 CR3 level index.*/
1439#define PGMPOOL_IDX_AMD64_CR3 8
1440/** Nested paging root.*/
1441#define PGMPOOL_IDX_NESTED_ROOT 9
1442/** The first normal index. */
1443#define PGMPOOL_IDX_FIRST 10
1444#endif
1445/** The last valid index. (inclusive, 14 bits) */
1446#define PGMPOOL_IDX_LAST 0x3fff
1447/** @} */
1448
1449/** The NIL index for the parent chain. */
1450#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1451
1452/**
1453 * Node in the chain linking a shadowed page to it's parent (user).
1454 */
1455#pragma pack(1)
1456typedef struct PGMPOOLUSER
1457{
1458 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1459 uint16_t iNext;
1460 /** The user page index. */
1461 uint16_t iUser;
1462 /** Index into the user table. */
1463 uint32_t iUserTable;
1464} PGMPOOLUSER, *PPGMPOOLUSER;
1465typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1466#pragma pack()
1467
1468
1469/** The NIL index for the phys ext chain. */
1470#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1471
1472/**
1473 * Node in the chain of physical cross reference extents.
1474 */
1475#pragma pack(1)
1476typedef struct PGMPOOLPHYSEXT
1477{
1478 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1479 uint16_t iNext;
1480 /** The user page index. */
1481 uint16_t aidx[3];
1482} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1483typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1484#pragma pack()
1485
1486
1487/**
1488 * The kind of page that's being shadowed.
1489 */
1490typedef enum PGMPOOLKIND
1491{
1492 /** The virtual invalid 0 entry. */
1493 PGMPOOLKIND_INVALID = 0,
1494 /** The entry is free (=unused). */
1495 PGMPOOLKIND_FREE,
1496
1497 /** Shw: 32-bit page table; Gst: no paging */
1498 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1499 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1500 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1501 /** Shw: 32-bit page table; Gst: 4MB page. */
1502 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1503 /** Shw: PAE page table; Gst: no paging */
1504 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1505 /** Shw: PAE page table; Gst: 32-bit page table. */
1506 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1507 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1508 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1509 /** Shw: PAE page table; Gst: PAE page table. */
1510 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1511 /** Shw: PAE page table; Gst: 2MB page. */
1512 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1513
1514 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1515 PGMPOOLKIND_32BIT_PD,
1516 /** Shw: 32-bit page directory. Gst: no paging. */
1517 PGMPOOLKIND_32BIT_PD_PHYS,
1518 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1519 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1520 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1521 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1522 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1523 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1524 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1525 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1526 /** Shw: PAE page directory; Gst: PAE page directory. */
1527 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1528 /** Shw: PAE page directory; Gst: no paging. */
1529 PGMPOOLKIND_PAE_PD_PHYS,
1530
1531 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1532 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1533 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1534 PGMPOOLKIND_PAE_PDPT,
1535 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1536 PGMPOOLKIND_PAE_PDPT_PHYS,
1537
1538 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1539 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1540 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1541 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1542 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1543 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1544 /** Shw: 64-bit page directory table; Gst: no paging */
1545 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1546
1547 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1548 PGMPOOLKIND_64BIT_PML4,
1549
1550 /** Shw: EPT page directory pointer table; Gst: no paging */
1551 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1552 /** Shw: EPT page directory table; Gst: no paging */
1553 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1554 /** Shw: EPT page table; Gst: no paging */
1555 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1556
1557#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1558 /** Shw: Root 32-bit page directory. */
1559 PGMPOOLKIND_ROOT_32BIT_PD,
1560 /** Shw: Root PAE page directory */
1561 PGMPOOLKIND_ROOT_PAE_PD,
1562 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1563 PGMPOOLKIND_ROOT_PDPT,
1564#endif
1565 /** Shw: Root Nested paging table. */
1566 PGMPOOLKIND_ROOT_NESTED,
1567
1568 /** The last valid entry. */
1569 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1570} PGMPOOLKIND;
1571
1572
1573/**
1574 * The tracking data for a page in the pool.
1575 */
1576typedef struct PGMPOOLPAGE
1577{
1578 /** AVL node code with the (R3) physical address of this page. */
1579 AVLOHCPHYSNODECORE Core;
1580 /** Pointer to the R3 mapping of the page. */
1581#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1582 R3PTRTYPE(void *) pvPageR3;
1583#else
1584 R3R0PTRTYPE(void *) pvPageR3;
1585#endif
1586 /** The guest physical address. */
1587#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1588 uint32_t Alignment0;
1589#endif
1590 RTGCPHYS GCPhys;
1591 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1592 uint8_t enmKind;
1593 uint8_t bPadding;
1594 /** The index of this page. */
1595 uint16_t idx;
1596 /** The next entry in the list this page currently resides in.
1597 * It's either in the free list or in the GCPhys hash. */
1598 uint16_t iNext;
1599#ifdef PGMPOOL_WITH_USER_TRACKING
1600 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1601 uint16_t iUserHead;
1602 /** The number of present entries. */
1603 uint16_t cPresent;
1604 /** The first entry in the table which is present. */
1605 uint16_t iFirstPresent;
1606#endif
1607#ifdef PGMPOOL_WITH_MONITORING
1608 /** The number of modifications to the monitored page. */
1609 uint16_t cModifications;
1610 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1611 uint16_t iModifiedNext;
1612 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1613 uint16_t iModifiedPrev;
1614 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1615 uint16_t iMonitoredNext;
1616 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1617 uint16_t iMonitoredPrev;
1618#endif
1619#ifdef PGMPOOL_WITH_CACHE
1620 /** The next page in the age list. */
1621 uint16_t iAgeNext;
1622 /** The previous page in the age list. */
1623 uint16_t iAgePrev;
1624#endif /* PGMPOOL_WITH_CACHE */
1625 /** Used to indicate that the page is zeroed. */
1626 bool fZeroed;
1627 /** Used to indicate that a PT has non-global entries. */
1628 bool fSeenNonGlobal;
1629 /** Used to indicate that we're monitoring writes to the guest page. */
1630 bool fMonitored;
1631 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1632 * (All pages are in the age list.) */
1633 bool fCached;
1634 /** This is used by the R3 access handlers when invoked by an async thread.
1635 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1636 bool volatile fReusedFlushPending;
1637#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1638 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1639 * In these cases the access handler acts differently and will check
1640 * for mapping conflicts like the normal CR3 handler.
1641 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1642 * replaced by a list of pages which share access handler.
1643 */
1644 bool fCR3Mix;
1645#endif
1646} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1647
1648
1649#ifdef PGMPOOL_WITH_CACHE
1650/** The hash table size. */
1651# define PGMPOOL_HASH_SIZE 0x40
1652/** The hash function. */
1653# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1654#endif
1655
1656
1657/**
1658 * The shadow page pool instance data.
1659 *
1660 * It's all one big allocation made at init time, except for the
1661 * pages that is. The user nodes follows immediatly after the
1662 * page structures.
1663 */
1664typedef struct PGMPOOL
1665{
1666 /** The VM handle - R3 Ptr. */
1667 PVMR3 pVMR3;
1668 /** The VM handle - R0 Ptr. */
1669 PVMR0 pVMR0;
1670 /** The VM handle - RC Ptr. */
1671 PVMRC pVMRC;
1672 /** The max pool size. This includes the special IDs. */
1673 uint16_t cMaxPages;
1674 /** The current pool size. */
1675 uint16_t cCurPages;
1676 /** The head of the free page list. */
1677 uint16_t iFreeHead;
1678 /* Padding. */
1679 uint16_t u16Padding;
1680#ifdef PGMPOOL_WITH_USER_TRACKING
1681 /** Head of the chain of free user nodes. */
1682 uint16_t iUserFreeHead;
1683 /** The number of user nodes we've allocated. */
1684 uint16_t cMaxUsers;
1685 /** The number of present page table entries in the entire pool. */
1686 uint32_t cPresent;
1687 /** Pointer to the array of user nodes - RC pointer. */
1688 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1689 /** Pointer to the array of user nodes - R3 pointer. */
1690 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1691 /** Pointer to the array of user nodes - R0 pointer. */
1692 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1693#endif /* PGMPOOL_WITH_USER_TRACKING */
1694#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1695 /** Head of the chain of free phys ext nodes. */
1696 uint16_t iPhysExtFreeHead;
1697 /** The number of user nodes we've allocated. */
1698 uint16_t cMaxPhysExts;
1699 /** Pointer to the array of physical xref extent - RC pointer. */
1700 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1701 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1702 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1703 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1704 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1705#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1706#ifdef PGMPOOL_WITH_CACHE
1707 /** Hash table for GCPhys addresses. */
1708 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1709 /** The head of the age list. */
1710 uint16_t iAgeHead;
1711 /** The tail of the age list. */
1712 uint16_t iAgeTail;
1713 /** Set if the cache is enabled. */
1714 bool fCacheEnabled;
1715#endif /* PGMPOOL_WITH_CACHE */
1716#ifdef PGMPOOL_WITH_MONITORING
1717 /** Head of the list of modified pages. */
1718 uint16_t iModifiedHead;
1719 /** The current number of modified pages. */
1720 uint16_t cModifiedPages;
1721 /** Access handler, RC. */
1722 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1723 /** Access handler, R0. */
1724 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1725 /** Access handler, R3. */
1726 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1727 /** The access handler description (HC ptr). */
1728 R3PTRTYPE(const char *) pszAccessHandler;
1729#endif /* PGMPOOL_WITH_MONITORING */
1730 /** The number of pages currently in use. */
1731 uint16_t cUsedPages;
1732#ifdef VBOX_WITH_STATISTICS
1733 /** The high wather mark for cUsedPages. */
1734 uint16_t cUsedPagesHigh;
1735 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1736 /** Profiling pgmPoolAlloc(). */
1737 STAMPROFILEADV StatAlloc;
1738 /** Profiling pgmPoolClearAll(). */
1739 STAMPROFILE StatClearAll;
1740 /** Profiling pgmPoolFlushAllInt(). */
1741 STAMPROFILE StatFlushAllInt;
1742 /** Profiling pgmPoolFlushPage(). */
1743 STAMPROFILE StatFlushPage;
1744 /** Profiling pgmPoolFree(). */
1745 STAMPROFILE StatFree;
1746 /** Profiling time spent zeroing pages. */
1747 STAMPROFILE StatZeroPage;
1748# ifdef PGMPOOL_WITH_USER_TRACKING
1749 /** Profiling of pgmPoolTrackDeref. */
1750 STAMPROFILE StatTrackDeref;
1751 /** Profiling pgmTrackFlushGCPhysPT. */
1752 STAMPROFILE StatTrackFlushGCPhysPT;
1753 /** Profiling pgmTrackFlushGCPhysPTs. */
1754 STAMPROFILE StatTrackFlushGCPhysPTs;
1755 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1756 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1757 /** Number of times we've been out of user records. */
1758 STAMCOUNTER StatTrackFreeUpOneUser;
1759# endif
1760# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1761 /** Profiling deref activity related tracking GC physical pages. */
1762 STAMPROFILE StatTrackDerefGCPhys;
1763 /** Number of linear searches for a HCPhys in the ram ranges. */
1764 STAMCOUNTER StatTrackLinearRamSearches;
1765 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1766 STAMCOUNTER StamTrackPhysExtAllocFailures;
1767# endif
1768# ifdef PGMPOOL_WITH_MONITORING
1769 /** Profiling the RC/R0 access handler. */
1770 STAMPROFILE StatMonitorRZ;
1771 /** Times we've failed interpreting the instruction. */
1772 STAMCOUNTER StatMonitorRZEmulateInstr;
1773 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1774 STAMPROFILE StatMonitorRZFlushPage;
1775 /** Times we've detected fork(). */
1776 STAMCOUNTER StatMonitorRZFork;
1777 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1778 STAMPROFILE StatMonitorRZHandled;
1779 /** Times we've failed interpreting a patch code instruction. */
1780 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1781 /** Times we've failed interpreting a patch code instruction during flushing. */
1782 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1783 /** The number of times we've seen rep prefixes we can't handle. */
1784 STAMCOUNTER StatMonitorRZRepPrefix;
1785 /** Profiling the REP STOSD cases we've handled. */
1786 STAMPROFILE StatMonitorRZRepStosd;
1787
1788 /** Profiling the R3 access handler. */
1789 STAMPROFILE StatMonitorR3;
1790 /** Times we've failed interpreting the instruction. */
1791 STAMCOUNTER StatMonitorR3EmulateInstr;
1792 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1793 STAMPROFILE StatMonitorR3FlushPage;
1794 /** Times we've detected fork(). */
1795 STAMCOUNTER StatMonitorR3Fork;
1796 /** Profiling the R3 access we've handled (except REP STOSD). */
1797 STAMPROFILE StatMonitorR3Handled;
1798 /** The number of times we've seen rep prefixes we can't handle. */
1799 STAMCOUNTER StatMonitorR3RepPrefix;
1800 /** Profiling the REP STOSD cases we've handled. */
1801 STAMPROFILE StatMonitorR3RepStosd;
1802 /** The number of times we're called in an async thread an need to flush. */
1803 STAMCOUNTER StatMonitorR3Async;
1804 /** The high wather mark for cModifiedPages. */
1805 uint16_t cModifiedPagesHigh;
1806 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1807# endif
1808# ifdef PGMPOOL_WITH_CACHE
1809 /** The number of cache hits. */
1810 STAMCOUNTER StatCacheHits;
1811 /** The number of cache misses. */
1812 STAMCOUNTER StatCacheMisses;
1813 /** The number of times we've got a conflict of 'kind' in the cache. */
1814 STAMCOUNTER StatCacheKindMismatches;
1815 /** Number of times we've been out of pages. */
1816 STAMCOUNTER StatCacheFreeUpOne;
1817 /** The number of cacheable allocations. */
1818 STAMCOUNTER StatCacheCacheable;
1819 /** The number of uncacheable allocations. */
1820 STAMCOUNTER StatCacheUncacheable;
1821# endif
1822#elif HC_ARCH_BITS == 64
1823 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1824#endif
1825 /** The AVL tree for looking up a page by its HC physical address. */
1826 AVLOHCPHYSTREE HCPhysTree;
1827 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1828 /** Array of pages. (cMaxPages in length)
1829 * The Id is the index into thist array.
1830 */
1831 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1832} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1833
1834
1835/** @def PGMPOOL_PAGE_2_PTR
1836 * Maps a pool page pool into the current context.
1837 *
1838 * @returns VBox status code.
1839 * @param pVM The VM handle.
1840 * @param pPage The pool page.
1841 *
1842 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1843 * small page window employeed by that function. Be careful.
1844 * @remark There is no need to assert on the result.
1845 */
1846#if defined(IN_RC)
1847# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1848#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1849# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1850#elif defined(VBOX_STRICT)
1851# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1852DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1853{
1854 Assert(pPage->pvPageR3);
1855 return pPage->pvPageR3;
1856}
1857#else
1858# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1859#endif
1860
1861/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1862 * Maps a pool page pool into the current context.
1863 *
1864 * @returns VBox status code.
1865 * @param pPGM Pointer to the PGM instance data.
1866 * @param pPage The pool page.
1867 *
1868 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1869 * small page window employeed by that function. Be careful.
1870 * @remark There is no need to assert on the result.
1871 */
1872#if defined(IN_RC)
1873# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1874#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1875# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1876#else
1877# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1878#endif
1879
1880
1881
1882/**
1883 * Trees are using self relative offsets as pointers.
1884 * So, all its data, including the root pointer, must be in the heap for HC and GC
1885 * to have the same layout.
1886 */
1887typedef struct PGMTREES
1888{
1889 /** Physical access handlers (AVL range+offsetptr tree). */
1890 AVLROGCPHYSTREE PhysHandlers;
1891 /** Virtual access handlers (AVL range + GC ptr tree). */
1892 AVLROGCPTRTREE VirtHandlers;
1893 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1894 AVLROGCPHYSTREE PhysToVirtHandlers;
1895 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1896 AVLROGCPTRTREE HyperVirtHandlers;
1897} PGMTREES;
1898/** Pointer to PGM trees. */
1899typedef PGMTREES *PPGMTREES;
1900
1901
1902/** @name Paging mode macros
1903 * @{ */
1904#ifdef IN_RC
1905# define PGM_CTX(a,b) a##RC##b
1906# define PGM_CTX_STR(a,b) a "GC" b
1907# define PGM_CTX_DECL(type) VMMRCDECL(type)
1908#else
1909# ifdef IN_RING3
1910# define PGM_CTX(a,b) a##R3##b
1911# define PGM_CTX_STR(a,b) a "R3" b
1912# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1913# else
1914# define PGM_CTX(a,b) a##R0##b
1915# define PGM_CTX_STR(a,b) a "R0" b
1916# define PGM_CTX_DECL(type) VMMDECL(type)
1917# endif
1918#endif
1919
1920#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1921#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1922#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1923#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1924#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1925#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1926#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1927#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1928#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1929#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1930#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1931#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1932#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1933#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1934#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1935#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1936#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1937
1938#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1939#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1940#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1941#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1942#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1943#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1944#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1945#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1946#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1947#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1948#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1949#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1950#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1951#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1952#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1953#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1954#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1955
1956/* Shw_Gst */
1957#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1958#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1959#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1960#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1961#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1962#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1963#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1964#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1965#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1966#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1967#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1968#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1969#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1970#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1971#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1972#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1973#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1974#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1975#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1976
1977#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1978#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1979#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1980#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1981#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1982#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1983#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1984#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1985#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1986#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1987#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1988#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1989#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1990#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1991#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1992#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1993#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1994#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1995#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1996#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1997#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1998#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1999#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2000#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2001#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2002#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2003#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2004#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2005#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2006#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2007#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2008#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2009#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2010#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2011#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2012#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2013#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2014
2015#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2016#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2017/** @} */
2018
2019/**
2020 * Data for each paging mode.
2021 */
2022typedef struct PGMMODEDATA
2023{
2024 /** The guest mode type. */
2025 uint32_t uGstType;
2026 /** The shadow mode type. */
2027 uint32_t uShwType;
2028
2029 /** @name Function pointers for Shadow paging.
2030 * @{
2031 */
2032 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2033 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2034 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2035 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2036
2037 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2038 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2039
2040 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2041 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2042 /** @} */
2043
2044 /** @name Function pointers for Guest paging.
2045 * @{
2046 */
2047 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2048 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2049 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2050 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2051 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2052#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2053 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2054 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2055#endif
2056#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2057 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2058 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2059 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2060 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2061#endif
2062 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2063 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2064 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2065#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2066 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2067 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2068#endif
2069#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2070 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2071 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2072#endif
2073 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2074 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2075 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2076#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2077 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2078 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2079#endif
2080#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2081 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2082 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2083#endif
2084 /** @} */
2085
2086 /** @name Function pointers for Both Shadow and Guest paging.
2087 * @{
2088 */
2089 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2090 /* no pfnR3BthTrap0eHandler */
2091 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2092 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2093 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2094 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2095 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2096#ifdef VBOX_STRICT
2097 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2098#endif
2099 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2100 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2101
2102 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2103 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2104 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2105 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2106 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2107 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2108#ifdef VBOX_STRICT
2109 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2110#endif
2111 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2112 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2113
2114 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2115 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2116 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2117 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2118 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2119 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2120#ifdef VBOX_STRICT
2121 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2122#endif
2123 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2124 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2125 /** @} */
2126} PGMMODEDATA, *PPGMMODEDATA;
2127
2128
2129
2130/**
2131 * Converts a PGM pointer into a VM pointer.
2132 * @returns Pointer to the VM structure the PGM is part of.
2133 * @param pPGM Pointer to PGM instance data.
2134 */
2135#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2136
2137/**
2138 * PGM Data (part of VM)
2139 */
2140typedef struct PGM
2141{
2142 /** Offset to the VM structure. */
2143 RTINT offVM;
2144 /** Offset of the PGMCPU structure relative to VMCPU. */
2145 int32_t offVCpu;
2146 /** Alignment padding. */
2147 int32_t i32Alignment;
2148
2149 /*
2150 * This will be redefined at least two more times before we're done, I'm sure.
2151 * The current code is only to get on with the coding.
2152 * - 2004-06-10: initial version, bird.
2153 * - 2004-07-02: 1st time, bird.
2154 * - 2004-10-18: 2nd time, bird.
2155 * - 2005-07-xx: 3rd time, bird.
2156 */
2157
2158 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2159 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2160 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2161 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2162
2163 /** The host paging mode. (This is what SUPLib reports.) */
2164 SUPPAGINGMODE enmHostMode;
2165 /** The shadow paging mode. */
2166 PGMMODE enmShadowMode;
2167 /** The guest paging mode. */
2168 PGMMODE enmGuestMode;
2169
2170 /** The current physical address representing in the guest CR3 register. */
2171 RTGCPHYS GCPhysCR3;
2172 /** Pointer to the 5 page CR3 content mapping.
2173 * The first page is always the CR3 (in some form) while the 4 other pages
2174 * are used of the PDs in PAE mode. */
2175 RTGCPTR GCPtrCR3Mapping;
2176#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2177 uint32_t u32Alignment;
2178#endif
2179#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2180 /** The physical address of the currently monitored guest CR3 page.
2181 * When this value is NIL_RTGCPHYS no page is being monitored. */
2182 RTGCPHYS GCPhysGstCR3Monitored;
2183#endif
2184 /** @name 32-bit Guest Paging.
2185 * @{ */
2186 /** The guest's page directory, R3 pointer. */
2187 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2188#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2189 /** The guest's page directory, R0 pointer. */
2190 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2191#endif
2192 /** The guest's page directory, static RC mapping. */
2193 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2194 /** @} */
2195
2196 /** @name PAE Guest Paging.
2197 * @{ */
2198 /** The guest's page directory pointer table, static RC mapping. */
2199 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2200 /** The guest's page directory pointer table, R3 pointer. */
2201 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2202#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2203 /** The guest's page directory pointer table, R0 pointer. */
2204 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2205#endif
2206
2207 /** The guest's page directories, R3 pointers.
2208 * These are individual pointers and don't have to be adjecent.
2209 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2210 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2211 /** The guest's page directories, R0 pointers.
2212 * Same restrictions as apGstPaePDsR3. */
2213#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2214 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2215#endif
2216 /** The guest's page directories, static GC mapping.
2217 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2218 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2219 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2220 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2221 RTGCPHYS aGCPhysGstPaePDs[4];
2222 /** The physical addresses of the monitored guest page directories (PAE). */
2223 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2224 /** @} */
2225
2226 /** @name AMD64 Guest Paging.
2227 * @{ */
2228 /** The guest's page directory pointer table, R3 pointer. */
2229 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2230#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2231 /** The guest's page directory pointer table, R0 pointer. */
2232 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2233#endif
2234 /** @} */
2235
2236 /** @name Shadow paging
2237 * @{ */
2238 /** The root page table - R3 Ptr. */
2239 R3PTRTYPE(void *) pShwRootR3;
2240# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2241 /** The root page table - R0 Ptr. */
2242 R0PTRTYPE(void *) pShwRootR0;
2243# endif
2244 /** The root page table - RC Ptr. */
2245 RCPTRTYPE(void *) pShwRootRC;
2246# if HC_ARCH_BITS == 64
2247 uint32_t u32Padding1; /**< alignment padding. */
2248# endif
2249 /** The Physical Address (HC) of the current active shadow CR3. */
2250 RTHCPHYS HCPhysShwCR3;
2251 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2252 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2253 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2254 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2255 /** Pointer to the page of the current active CR3 - RC Ptr. */
2256 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2257 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2258 uint32_t iShwUser;
2259 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2260 uint32_t iShwUserTable;
2261# if HC_ARCH_BITS == 64
2262 RTRCPTR alignment6; /**< structure size alignment. */
2263# endif
2264 /** @} */
2265#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2266 /** @name 32-bit Shadow Paging
2267 * @{ */
2268 /** The 32-Bit PD - R3 Ptr. */
2269 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2270 /** The 32-Bit PD - R0 Ptr. */
2271 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2272 /** The 32-Bit PD - RC Ptr. */
2273 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2274# if HC_ARCH_BITS == 64
2275 uint32_t u32Padding10; /**< alignment padding. */
2276# endif
2277 /** The Physical Address (HC) of the 32-Bit PD. */
2278 RTHCPHYS HCPhysShw32BitPD;
2279 /** @} */
2280
2281 /** @name PAE Shadow Paging
2282 * @{ */
2283 /** The four PDs for the low 4GB - R3 Ptr.
2284 * Even though these are 4 pointers, what they point at is a single table.
2285 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2286 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2287# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2288 /** The four PDs for the low 4GB - R0 Ptr.
2289 * Same kind of mapping as apHCPaePDs. */
2290 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2291# endif
2292 /** The four PDs for the low 4GB - RC Ptr.
2293 * Same kind of mapping as apHCPaePDs. */
2294 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2295 /** The Physical Address (HC) of the four PDs for the low 4GB.
2296 * These are *NOT* 4 contiguous pages. */
2297 RTHCPHYS aHCPhysPaePDs[4];
2298 /** The Physical Address (HC) of the PAE PDPT. */
2299 RTHCPHYS HCPhysShwPaePdpt;
2300 /** The PAE PDPT - R3 Ptr. */
2301 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2302 /** The PAE PDPT - R0 Ptr. */
2303 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2304 /** The PAE PDPT - RC Ptr. */
2305 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2306 /** @} */
2307# if HC_ARCH_BITS == 64
2308 RTRCPTR alignment5; /**< structure size alignment. */
2309# endif
2310#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2311 /** @name Nested Shadow Paging
2312 * @{ */
2313 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2314 RTR3PTR pShwNestedRootR3;
2315# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2316 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2317 RTR0PTR pShwNestedRootR0;
2318# endif
2319 /** The Physical Address (HC) of the nested paging root. */
2320 RTHCPHYS HCPhysShwNestedRoot;
2321 /** @} */
2322
2323 /** @name Function pointers for Shadow paging.
2324 * @{
2325 */
2326 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2327 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2328 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2329 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2330
2331 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2332 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2333
2334 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2335 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2336
2337 /** @} */
2338
2339 /** @name Function pointers for Guest paging.
2340 * @{
2341 */
2342 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2343 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2344 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2345 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2346 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2347#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2348 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2349 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2350#endif
2351#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2352 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2353 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2354 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2355 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2356#endif
2357 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2358 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2359 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2360#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2361 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2362 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2363#endif
2364#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2365 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2366 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2367#endif
2368#if HC_ARCH_BITS == 64
2369 RTRCPTR alignment3; /**< structure size alignment. */
2370#endif
2371
2372 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2373 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2374 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2375#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2376 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2377 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2378#endif
2379#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2380 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2381 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2382#endif
2383 /** @} */
2384
2385 /** @name Function pointers for Both Shadow and Guest paging.
2386 * @{
2387 */
2388 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2389 /* no pfnR3BthTrap0eHandler */
2390 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2391 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2392 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2393 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2394 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2395 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2396 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2397 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2398
2399 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2400 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2401 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2402 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2403 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2404 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2405 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2406 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2407 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2408
2409 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2410 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2411 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2412 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2413 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2414 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2415 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2416 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2417 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2418#if HC_ARCH_BITS == 64
2419 RTRCPTR alignment2; /**< structure size alignment. */
2420#endif
2421 /** @} */
2422
2423 /** Pointer to SHW+GST mode data (function pointers).
2424 * The index into this table is made up from */
2425 R3PTRTYPE(PPGMMODEDATA) paModeData;
2426
2427 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2428 * This is sorted by physical address and contains no overlapping ranges. */
2429 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2430 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2431 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2432 /** RC pointer corresponding to PGM::pRamRangesR3. */
2433 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2434 /** The configured RAM size. */
2435 RTUINT cbRamSize;
2436
2437 /** Pointer to the list of ROM ranges - for R3.
2438 * This is sorted by physical address and contains no overlapping ranges. */
2439 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2440 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2441 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2442 /** RC pointer corresponding to PGM::pRomRangesR3. */
2443 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2444 /** Alignment padding. */
2445 RTRCPTR GCPtrPadding2;
2446
2447 /** Pointer to the list of MMIO2 ranges - for R3.
2448 * Registration order. */
2449 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2450
2451 /** PGM offset based trees - R3 Ptr. */
2452 R3PTRTYPE(PPGMTREES) pTreesR3;
2453 /** PGM offset based trees - R0 Ptr. */
2454 R0PTRTYPE(PPGMTREES) pTreesR0;
2455 /** PGM offset based trees - RC Ptr. */
2456 RCPTRTYPE(PPGMTREES) pTreesRC;
2457
2458 /** Linked list of GC mappings - for RC.
2459 * The list is sorted ascending on address.
2460 */
2461 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2462 /** Linked list of GC mappings - for HC.
2463 * The list is sorted ascending on address.
2464 */
2465 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2466 /** Linked list of GC mappings - for R0.
2467 * The list is sorted ascending on address.
2468 */
2469 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2470
2471 /** Indicates that PGMR3FinalizeMappings has been called and that further
2472 * PGMR3MapIntermediate calls will be rejected. */
2473 bool fFinalizedMappings;
2474 /** If set no conflict checks are required. (boolean) */
2475 bool fMappingsFixed;
2476 /** If set, then no mappings are put into the shadow page table. (boolean) */
2477 bool fDisableMappings;
2478 /** Size of fixed mapping */
2479 uint32_t cbMappingFixed;
2480 /** Base address (GC) of fixed mapping */
2481 RTGCPTR GCPtrMappingFixed;
2482#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2483 uint32_t u32Padding0; /**< alignment padding. */
2484#endif
2485
2486
2487 /** @name Intermediate Context
2488 * @{ */
2489 /** Pointer to the intermediate page directory - Normal. */
2490 R3PTRTYPE(PX86PD) pInterPD;
2491 /** Pointer to the intermedate page tables - Normal.
2492 * There are two page tables, one for the identity mapping and one for
2493 * the host context mapping (of the core code). */
2494 R3PTRTYPE(PX86PT) apInterPTs[2];
2495 /** Pointer to the intermedate page tables - PAE. */
2496 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2497 /** Pointer to the intermedate page directory - PAE. */
2498 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2499 /** Pointer to the intermedate page directory - PAE. */
2500 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2501 /** Pointer to the intermedate page-map level 4 - AMD64. */
2502 R3PTRTYPE(PX86PML4) pInterPaePML4;
2503 /** Pointer to the intermedate page directory - AMD64. */
2504 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2505 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2506 RTHCPHYS HCPhysInterPD;
2507 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2508 RTHCPHYS HCPhysInterPaePDPT;
2509 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2510 RTHCPHYS HCPhysInterPaePML4;
2511 /** @} */
2512
2513 /** Base address of the dynamic page mapping area.
2514 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2515 */
2516 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2517 /** The index of the last entry used in the dynamic page mapping area. */
2518 RTUINT iDynPageMapLast;
2519 /** Cache containing the last entries in the dynamic page mapping area.
2520 * The cache size is covering half of the mapping area. */
2521 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2522
2523 /** The address of the ring-0 mapping cache if we're making use of it. */
2524 RTR0PTR pvR0DynMapUsed;
2525#if HC_ARCH_BITS == 32
2526 RTR0PTR R0PtrPadding0; /**< Alignment. */
2527#endif
2528
2529
2530 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2531 RTGCPHYS GCPhys4MBPSEMask;
2532
2533 /** A20 gate mask.
2534 * Our current approach to A20 emulation is to let REM do it and don't bother
2535 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2536 * But whould need arrise, we'll subject physical addresses to this mask. */
2537 RTGCPHYS GCPhysA20Mask;
2538 /** A20 gate state - boolean! */
2539 RTUINT fA20Enabled;
2540
2541 /** What needs syncing (PGM_SYNC_*).
2542 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2543 * PGMFlushTLB, and PGMR3Load. */
2544 RTUINT fSyncFlags;
2545
2546 /** PGM critical section.
2547 * This protects the physical & virtual access handlers, ram ranges,
2548 * and the page flag updating (some of it anyway).
2549 */
2550 PDMCRITSECT CritSect;
2551
2552 /** Shadow Page Pool - R3 Ptr. */
2553 R3PTRTYPE(PPGMPOOL) pPoolR3;
2554 /** Shadow Page Pool - R0 Ptr. */
2555 R0PTRTYPE(PPGMPOOL) pPoolR0;
2556 /** Shadow Page Pool - RC Ptr. */
2557 RCPTRTYPE(PPGMPOOL) pPoolRC;
2558
2559 /** We're not in a state which permits writes to guest memory.
2560 * (Only used in strict builds.) */
2561 bool fNoMorePhysWrites;
2562
2563 /** Flush the cache on the next access. */
2564 bool fPhysCacheFlushPending;
2565/** @todo r=bird: Fix member names!*/
2566 /** PGMPhysRead cache */
2567 PGMPHYSCACHE pgmphysreadcache;
2568 /** PGMPhysWrite cache */
2569 PGMPHYSCACHE pgmphyswritecache;
2570
2571 /**
2572 * Data associated with managing the ring-3 mappings of the allocation chunks.
2573 */
2574 struct
2575 {
2576 /** The chunk tree, ordered by chunk id. */
2577#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2578 R3PTRTYPE(PAVLU32NODECORE) pTree;
2579#else
2580 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2581#endif
2582 /** The chunk mapping TLB. */
2583 PGMCHUNKR3MAPTLB Tlb;
2584 /** The number of mapped chunks. */
2585 uint32_t c;
2586 /** The maximum number of mapped chunks.
2587 * @cfgm PGM/MaxRing3Chunks */
2588 uint32_t cMax;
2589 /** The chunk age tree, ordered by ageing sequence number. */
2590 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2591 /** The current time. */
2592 uint32_t iNow;
2593 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2594 uint32_t AgeingCountdown;
2595 } ChunkR3Map;
2596
2597 /**
2598 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2599 */
2600 PGMPAGER3MAPTLB PhysTlbHC;
2601
2602 /** @name The zero page.
2603 * @{ */
2604 /** The host physical address of the zero page. */
2605 RTHCPHYS HCPhysZeroPg;
2606 /** The ring-3 mapping of the zero page. */
2607 RTR3PTR pvZeroPgR3;
2608 /** The ring-0 mapping of the zero page. */
2609 RTR0PTR pvZeroPgR0;
2610 /** The GC mapping of the zero page. */
2611 RTGCPTR pvZeroPgGC;
2612#if GC_ARCH_BITS != 32
2613 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2614#endif
2615 /** @}*/
2616
2617 /** The number of handy pages. */
2618 uint32_t cHandyPages;
2619 /**
2620 * Array of handy pages.
2621 *
2622 * This array is used in a two way communication between pgmPhysAllocPage
2623 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2624 * an intermediary.
2625 *
2626 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2627 * (The current size of 32 pages, means 128 KB of handy memory.)
2628 */
2629 GMMPAGEDESC aHandyPages[32];
2630
2631 /** @name Release Statistics
2632 * @{ */
2633 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2634 uint32_t cPrivatePages; /**< The number of private pages. */
2635 uint32_t cSharedPages; /**< The number of shared pages. */
2636 uint32_t cZeroPages; /**< The number of zero backed pages. */
2637 /** The number of times the guest has switched mode since last reset or statistics reset. */
2638 STAMCOUNTER cGuestModeChanges;
2639 /** The number of times we were forced to change the hypervisor region location. */
2640 STAMCOUNTER cRelocations;
2641 /** @} */
2642
2643#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2644 /** RC: Which statistic this \#PF should be attributed to. */
2645 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2646 RTRCPTR padding0;
2647 /** R0: Which statistic this \#PF should be attributed to. */
2648 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2649 RTR0PTR padding1;
2650
2651 /* Common */
2652# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2653 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2654 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2655 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2656 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2657 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2658 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2659# endif
2660 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2661 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2662
2663 /* R3 only: */
2664 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2665 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2666 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2667 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2668 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2669 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2670
2671 /* R0 only: */
2672 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2673 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2674 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2675 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2676 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2677 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2678 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2679 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2680 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2681 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2682 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2683 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2684 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2685 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2686 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2687 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2688 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2689 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2690 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2691 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2692 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2693 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2694 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2695 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2696 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2697 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2698
2699 /* RC only: */
2700 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2701 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2702 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2703 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2704
2705 /* RZ only: */
2706 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2707 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2708 STAMPROFILE StatRZTrap0eTimeSyncPT;
2709 STAMPROFILE StatRZTrap0eTimeMapping;
2710 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2711 STAMPROFILE StatRZTrap0eTimeHandlers;
2712 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2713 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2714 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2715 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2716 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2717 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2718 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2719 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2720 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2721 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2722 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2723 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2724 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2725 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2726 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2727 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2728 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2729 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2730 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2731 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2732 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2733 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2734 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2735 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2736 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2737 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2738 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2739 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2740 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2741 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2742 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2743 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2744 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2745 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2746 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2747 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2748 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2749 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2750 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2751 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2752 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2753 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2754 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2755
2756 /* HC - R3 and (maybe) R0: */
2757
2758 /* RZ & R3: */
2759 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2760 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2761 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2762 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2763 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2764 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2765 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2766 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2767 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2768 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2769 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2770 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2771 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2772 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2773 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2774 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2775 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2776 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2777 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2778 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2779 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2780 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2781 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2782 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2783 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2784 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2785 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2786 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2787 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2788 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2789 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2790 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2791 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2792 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2793 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2794 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2795 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2796 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2797 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2798 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2799 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2800 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2801 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2802 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2803 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2804 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2805 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2806/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2807 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2808 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2809 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2810 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2811 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2812 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2813
2814 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2815 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2816 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2817 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2818 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2819 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2820 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2821 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2822 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2823 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2824 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2825 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2826 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2827 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2828 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2829 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2830 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2831 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2832 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2833 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2834 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2835 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2836 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2837 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2838 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2839 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2840 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2841 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2842 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2843 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2844 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2845 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2846 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2847 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2848 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2849 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2850 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2851 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2852 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2853 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2854 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2855 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2856 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2857 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2858 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2859 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2860 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2861/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2862 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2863 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2864 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2865 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2866 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2867 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2868#endif /* VBOX_WITH_STATISTICS */
2869} PGM;
2870/** Pointer to the PGM instance data. */
2871typedef PGM *PPGM;
2872
2873
2874/**
2875 * PGMCPU Data (part of VMCPU).
2876 */
2877typedef struct PGMCPU
2878{
2879 /** Offset to the VMCPU structure. */
2880 RTINT offVMCPU;
2881 /** Automatically tracked physical memory mapping set.
2882 * Ring-0 and strict raw-mode builds. */
2883 PGMMAPSET AutoSet;
2884} PGMCPU;
2885/** Pointer to the per-cpu PGM data. */
2886typedef PGMCPU *PPGMCPU;
2887
2888
2889/** @name PGM::fSyncFlags Flags
2890 * @{
2891 */
2892/** Updates the virtual access handler state bit in PGMPAGE. */
2893#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2894/** Always sync CR3. */
2895#define PGM_SYNC_ALWAYS RT_BIT(1)
2896/** Check monitoring on next CR3 (re)load and invalidate page. */
2897#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2898/** Check guest mapping in SyncCR3. */
2899#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2900/** Clear the page pool (a light weight flush). */
2901#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2902/** @} */
2903
2904
2905__BEGIN_DECLS
2906
2907int pgmLock(PVM pVM);
2908void pgmUnlock(PVM pVM);
2909
2910VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2911VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2912
2913int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2914int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2915PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2916void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2917DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2918
2919void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2920bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2921int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2922DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2923#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2924void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2925#else
2926# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2927#endif
2928DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2929
2930
2931void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2932int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2933int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2934int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2935#ifdef IN_RING3
2936int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2937int pgmR3PhysRamReset(PVM pVM);
2938int pgmR3PhysRomReset(PVM pVM);
2939# ifndef VBOX_WITH_NEW_PHYS_CODE
2940int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2941# endif
2942
2943int pgmR3PoolInit(PVM pVM);
2944void pgmR3PoolRelocate(PVM pVM);
2945void pgmR3PoolReset(PVM pVM);
2946
2947#endif /* IN_RING3 */
2948#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2949int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2950#endif
2951#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2952void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2953#endif
2954int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2955PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2956void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2957void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2958int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2959void pgmPoolFlushAll(PVM pVM);
2960void pgmPoolClearAll(PVM pVM);
2961int pgmPoolSyncCR3(PVM pVM);
2962void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2963void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2964int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2965PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2966void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2967void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2968uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2969void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2970#ifdef PGMPOOL_WITH_MONITORING
2971void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2972int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2973void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2974void pgmPoolMonitorModifiedClearAll(PVM pVM);
2975int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2976int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2977#endif
2978
2979#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2980bool pgmPoolIsActiveRootPage(PVM pVM, PPGMPOOLPAGE pPage);
2981
2982void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
2983void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2984int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2985int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2986#endif
2987#ifndef IN_RC
2988int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2989#endif
2990int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
2991
2992__END_DECLS
2993
2994
2995/**
2996 * Gets the PGMRAMRANGE structure for a guest page.
2997 *
2998 * @returns Pointer to the RAM range on success.
2999 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3000 *
3001 * @param pPGM PGM handle.
3002 * @param GCPhys The GC physical address.
3003 */
3004DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3005{
3006 /*
3007 * Optimize for the first range.
3008 */
3009 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3010 RTGCPHYS off = GCPhys - pRam->GCPhys;
3011 if (RT_UNLIKELY(off >= pRam->cb))
3012 {
3013 do
3014 {
3015 pRam = pRam->CTX_SUFF(pNext);
3016 if (RT_UNLIKELY(!pRam))
3017 break;
3018 off = GCPhys - pRam->GCPhys;
3019 } while (off >= pRam->cb);
3020 }
3021 return pRam;
3022}
3023
3024
3025/**
3026 * Gets the PGMPAGE structure for a guest page.
3027 *
3028 * @returns Pointer to the page on success.
3029 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3030 *
3031 * @param pPGM PGM handle.
3032 * @param GCPhys The GC physical address.
3033 */
3034DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3035{
3036 /*
3037 * Optimize for the first range.
3038 */
3039 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3040 RTGCPHYS off = GCPhys - pRam->GCPhys;
3041 if (RT_UNLIKELY(off >= pRam->cb))
3042 {
3043 do
3044 {
3045 pRam = pRam->CTX_SUFF(pNext);
3046 if (RT_UNLIKELY(!pRam))
3047 return NULL;
3048 off = GCPhys - pRam->GCPhys;
3049 } while (off >= pRam->cb);
3050 }
3051 return &pRam->aPages[off >> PAGE_SHIFT];
3052}
3053
3054
3055/**
3056 * Gets the PGMPAGE structure for a guest page.
3057 *
3058 * Old Phys code: Will make sure the page is present.
3059 *
3060 * @returns VBox status code.
3061 * @retval VINF_SUCCESS and a valid *ppPage on success.
3062 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3063 *
3064 * @param pPGM PGM handle.
3065 * @param GCPhys The GC physical address.
3066 * @param ppPage Where to store the page poitner on success.
3067 */
3068DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3069{
3070 /*
3071 * Optimize for the first range.
3072 */
3073 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3074 RTGCPHYS off = GCPhys - pRam->GCPhys;
3075 if (RT_UNLIKELY(off >= pRam->cb))
3076 {
3077 do
3078 {
3079 pRam = pRam->CTX_SUFF(pNext);
3080 if (RT_UNLIKELY(!pRam))
3081 {
3082 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3083 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3084 }
3085 off = GCPhys - pRam->GCPhys;
3086 } while (off >= pRam->cb);
3087 }
3088 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3089#ifndef VBOX_WITH_NEW_PHYS_CODE
3090
3091 /*
3092 * Make sure it's present.
3093 */
3094 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3095 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3096 {
3097#ifdef IN_RING3
3098 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3099#else
3100 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3101#endif
3102 if (RT_FAILURE(rc))
3103 {
3104 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3105 return rc;
3106 }
3107 Assert(rc == VINF_SUCCESS);
3108 }
3109#endif
3110 return VINF_SUCCESS;
3111}
3112
3113
3114
3115
3116/**
3117 * Gets the PGMPAGE structure for a guest page.
3118 *
3119 * Old Phys code: Will make sure the page is present.
3120 *
3121 * @returns VBox status code.
3122 * @retval VINF_SUCCESS and a valid *ppPage on success.
3123 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3124 *
3125 * @param pPGM PGM handle.
3126 * @param GCPhys The GC physical address.
3127 * @param ppPage Where to store the page poitner on success.
3128 * @param ppRamHint Where to read and store the ram list hint.
3129 * The caller initializes this to NULL before the call.
3130 */
3131DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3132{
3133 RTGCPHYS off;
3134 PPGMRAMRANGE pRam = *ppRamHint;
3135 if ( !pRam
3136 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3137 {
3138 pRam = pPGM->CTX_SUFF(pRamRanges);
3139 off = GCPhys - pRam->GCPhys;
3140 if (RT_UNLIKELY(off >= pRam->cb))
3141 {
3142 do
3143 {
3144 pRam = pRam->CTX_SUFF(pNext);
3145 if (RT_UNLIKELY(!pRam))
3146 {
3147 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3148 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3149 }
3150 off = GCPhys - pRam->GCPhys;
3151 } while (off >= pRam->cb);
3152 }
3153 *ppRamHint = pRam;
3154 }
3155 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3156#ifndef VBOX_WITH_NEW_PHYS_CODE
3157
3158 /*
3159 * Make sure it's present.
3160 */
3161 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3162 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3163 {
3164#ifdef IN_RING3
3165 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3166#else
3167 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3168#endif
3169 if (RT_FAILURE(rc))
3170 {
3171 *ppPage = NULL; /* Shut up annoying smart ass. */
3172 return rc;
3173 }
3174 Assert(rc == VINF_SUCCESS);
3175 }
3176#endif
3177 return VINF_SUCCESS;
3178}
3179
3180
3181/**
3182 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3183 *
3184 * @returns Pointer to the page on success.
3185 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3186 *
3187 * @param pPGM PGM handle.
3188 * @param GCPhys The GC physical address.
3189 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3190 */
3191DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3192{
3193 /*
3194 * Optimize for the first range.
3195 */
3196 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3197 RTGCPHYS off = GCPhys - pRam->GCPhys;
3198 if (RT_UNLIKELY(off >= pRam->cb))
3199 {
3200 do
3201 {
3202 pRam = pRam->CTX_SUFF(pNext);
3203 if (RT_UNLIKELY(!pRam))
3204 return NULL;
3205 off = GCPhys - pRam->GCPhys;
3206 } while (off >= pRam->cb);
3207 }
3208 *ppRam = pRam;
3209 return &pRam->aPages[off >> PAGE_SHIFT];
3210}
3211
3212
3213/**
3214 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3215 *
3216 * @returns Pointer to the page on success.
3217 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3218 *
3219 * @param pPGM PGM handle.
3220 * @param GCPhys The GC physical address.
3221 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3222 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3223 */
3224DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3225{
3226 /*
3227 * Optimize for the first range.
3228 */
3229 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3230 RTGCPHYS off = GCPhys - pRam->GCPhys;
3231 if (RT_UNLIKELY(off >= pRam->cb))
3232 {
3233 do
3234 {
3235 pRam = pRam->CTX_SUFF(pNext);
3236 if (RT_UNLIKELY(!pRam))
3237 {
3238 *ppRam = NULL; /* Shut up silly GCC warnings. */
3239 *ppPage = NULL; /* ditto */
3240 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3241 }
3242 off = GCPhys - pRam->GCPhys;
3243 } while (off >= pRam->cb);
3244 }
3245 *ppRam = pRam;
3246 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3247#ifndef VBOX_WITH_NEW_PHYS_CODE
3248
3249 /*
3250 * Make sure it's present.
3251 */
3252 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3253 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3254 {
3255#ifdef IN_RING3
3256 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3257#else
3258 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3259#endif
3260 if (RT_FAILURE(rc))
3261 {
3262 *ppPage = NULL; /* Shut up silly GCC warnings. */
3263 *ppPage = NULL; /* ditto */
3264 return rc;
3265 }
3266 Assert(rc == VINF_SUCCESS);
3267
3268 }
3269#endif
3270 return VINF_SUCCESS;
3271}
3272
3273
3274/**
3275 * Convert GC Phys to HC Phys.
3276 *
3277 * @returns VBox status.
3278 * @param pPGM PGM handle.
3279 * @param GCPhys The GC physical address.
3280 * @param pHCPhys Where to store the corresponding HC physical address.
3281 *
3282 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3283 * Avoid when writing new code!
3284 */
3285DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3286{
3287 PPGMPAGE pPage;
3288 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3289 if (RT_FAILURE(rc))
3290 return rc;
3291 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3292 return VINF_SUCCESS;
3293}
3294
3295#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3296
3297/**
3298 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3299 * optimizes access to pages already in the set.
3300 *
3301 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3302 * @param pPGM Pointer to the PVM instance data.
3303 * @param HCPhys The physical address of the page.
3304 * @param ppv Where to store the mapping address.
3305 */
3306DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3307{
3308 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3309 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3310 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3311 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3312
3313 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3314 unsigned iEntry = pSet->aiHashTable[iHash];
3315 if ( iEntry < pSet->cEntries
3316 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3317 {
3318 *ppv = pSet->aEntries[iEntry].pvPage;
3319 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3320 }
3321 else
3322 {
3323 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3324 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3325 }
3326
3327 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3328 return VINF_SUCCESS;
3329}
3330
3331
3332/**
3333 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3334 * access to pages already in the set.
3335 *
3336 * @returns See PGMDynMapGCPage.
3337 * @param pPGM Pointer to the PVM instance data.
3338 * @param HCPhys The physical address of the page.
3339 * @param ppv Where to store the mapping address.
3340 */
3341DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3342{
3343 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3344 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3345
3346 /*
3347 * Get the ram range.
3348 */
3349 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3350 RTGCPHYS off = GCPhys - pRam->GCPhys;
3351 if (RT_UNLIKELY(off >= pRam->cb
3352 /** @todo || page state stuff */))
3353 {
3354 /* This case is not counted into StatR0DynMapGCPageInl. */
3355 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3356 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3357 }
3358
3359 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3360 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3361
3362 /*
3363 * pgmR0DynMapHCPageInlined with out stats.
3364 */
3365 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3366 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3367 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3368
3369 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3370 unsigned iEntry = pSet->aiHashTable[iHash];
3371 if ( iEntry < pSet->cEntries
3372 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3373 {
3374 *ppv = pSet->aEntries[iEntry].pvPage;
3375 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3376 }
3377 else
3378 {
3379 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3380 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3381 }
3382
3383 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3384 return VINF_SUCCESS;
3385}
3386
3387#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3388
3389#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3390/**
3391 * Maps the page into current context (RC and maybe R0).
3392 *
3393 * @returns pointer to the mapping.
3394 * @param pVM Pointer to the PGM instance data.
3395 * @param pPage The page.
3396 */
3397DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3398{
3399 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3400 {
3401 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3402 void *pv;
3403# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3404 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3405# else
3406 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3407# endif
3408 return pv;
3409 }
3410 return pgmPoolMapPageFallback(pPGM, pPage);
3411}
3412
3413/**
3414 * Temporarily maps one host page specified by HC physical address, returning
3415 * pointer within the page.
3416 *
3417 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3418 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3419 *
3420 * @returns The address corresponding to HCPhys.
3421 * @param pPGM Pointer to the PVM instance data.
3422 * @param HCPhys HC Physical address of the page.
3423 */
3424DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3425{
3426 void *pv;
3427# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3428 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3429# else
3430 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3431# endif
3432 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3433 return pv;
3434}
3435#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3436
3437
3438#ifndef IN_RC
3439/**
3440 * Queries the Physical TLB entry for a physical guest page,
3441 * attemting to load the TLB entry if necessary.
3442 *
3443 * @returns VBox status code.
3444 * @retval VINF_SUCCESS on success
3445 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3446 * @param pPGM The PGM instance handle.
3447 * @param GCPhys The address of the guest page.
3448 * @param ppTlbe Where to store the pointer to the TLB entry.
3449 */
3450
3451DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3452{
3453 int rc;
3454 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3455 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3456 {
3457 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3458 rc = VINF_SUCCESS;
3459 }
3460 else
3461 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3462 *ppTlbe = pTlbe;
3463 return rc;
3464}
3465#endif /* !IN_RC */
3466
3467#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3468
3469# ifndef VBOX_WITH_NEW_PHYS_CODE
3470/**
3471 * Convert GC Phys to HC Virt.
3472 *
3473 * @returns VBox status.
3474 * @param pPGM PGM handle.
3475 * @param GCPhys The GC physical address.
3476 * @param pHCPtr Where to store the corresponding HC virtual address.
3477 *
3478 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3479 * pgmPoolMonitorGCPtr2CCPtr.
3480 */
3481DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3482{
3483 PPGMRAMRANGE pRam;
3484 PPGMPAGE pPage;
3485 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3486 if (RT_FAILURE(rc))
3487 {
3488 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3489 return rc;
3490 }
3491 RTGCPHYS off = GCPhys - pRam->GCPhys;
3492
3493 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3494 {
3495 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3496 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3497 return VINF_SUCCESS;
3498 }
3499 if (pRam->pvR3)
3500 {
3501 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3502 return VINF_SUCCESS;
3503 }
3504 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3505 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3506}
3507# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3508#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3509
3510/**
3511 * Convert GC Phys to HC Virt and HC Phys.
3512 *
3513 * @returns VBox status.
3514 * @param pPGM PGM handle.
3515 * @param GCPhys The GC physical address.
3516 * @param pHCPtr Where to store the corresponding HC virtual address.
3517 * @param pHCPhys Where to store the HC Physical address and its flags.
3518 *
3519 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3520 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3521 */
3522DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3523{
3524 PPGMRAMRANGE pRam;
3525 PPGMPAGE pPage;
3526 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3527 if (RT_FAILURE(rc))
3528 {
3529 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3530 *pHCPhys = 0; /* ditto */
3531 return rc;
3532 }
3533 RTGCPHYS off = GCPhys - pRam->GCPhys;
3534
3535 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3536 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3537 {
3538 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3539#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3540 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3541 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3542#else
3543 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3544#endif
3545 return VINF_SUCCESS;
3546 }
3547 if (pRam->pvR3)
3548 {
3549 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3550 return VINF_SUCCESS;
3551 }
3552 *pHCPtr = 0;
3553 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3554}
3555
3556
3557/**
3558 * Clears flags associated with a RAM address.
3559 *
3560 * @returns VBox status code.
3561 * @param pPGM PGM handle.
3562 * @param GCPhys Guest context physical address.
3563 * @param fFlags fFlags to clear. (Bits 0-11.)
3564 */
3565DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3566{
3567 PPGMPAGE pPage;
3568 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3569 if (RT_FAILURE(rc))
3570 return rc;
3571
3572 fFlags &= ~X86_PTE_PAE_PG_MASK;
3573 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3574 return VINF_SUCCESS;
3575}
3576
3577
3578/**
3579 * Clears flags associated with a RAM address.
3580 *
3581 * @returns VBox status code.
3582 * @param pPGM PGM handle.
3583 * @param GCPhys Guest context physical address.
3584 * @param fFlags fFlags to clear. (Bits 0-11.)
3585 * @param ppRamHint Where to read and store the ram list hint.
3586 * The caller initializes this to NULL before the call.
3587 */
3588DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3589{
3590 PPGMPAGE pPage;
3591 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3592 if (RT_FAILURE(rc))
3593 return rc;
3594
3595 fFlags &= ~X86_PTE_PAE_PG_MASK;
3596 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3597 return VINF_SUCCESS;
3598}
3599
3600
3601/**
3602 * Sets (bitwise OR) flags associated with a RAM address.
3603 *
3604 * @returns VBox status code.
3605 * @param pPGM PGM handle.
3606 * @param GCPhys Guest context physical address.
3607 * @param fFlags fFlags to set clear. (Bits 0-11.)
3608 */
3609DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3610{
3611 PPGMPAGE pPage;
3612 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3613 if (RT_FAILURE(rc))
3614 return rc;
3615
3616 fFlags &= ~X86_PTE_PAE_PG_MASK;
3617 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3618 return VINF_SUCCESS;
3619}
3620
3621
3622/**
3623 * Sets (bitwise OR) flags associated with a RAM address.
3624 *
3625 * @returns VBox status code.
3626 * @param pPGM PGM handle.
3627 * @param GCPhys Guest context physical address.
3628 * @param fFlags fFlags to set clear. (Bits 0-11.)
3629 * @param ppRamHint Where to read and store the ram list hint.
3630 * The caller initializes this to NULL before the call.
3631 */
3632DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3633{
3634 PPGMPAGE pPage;
3635 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3636 if (RT_FAILURE(rc))
3637 return rc;
3638
3639 fFlags &= ~X86_PTE_PAE_PG_MASK;
3640 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3641 return VINF_SUCCESS;
3642}
3643
3644
3645/**
3646 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3647 * Takes PSE-36 into account.
3648 *
3649 * @returns guest physical address
3650 * @param pPGM Pointer to the PGM instance data.
3651 * @param Pde Guest Pde
3652 */
3653DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3654{
3655 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3656 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3657
3658 return GCPhys & pPGM->GCPhys4MBPSEMask;
3659}
3660
3661
3662/**
3663 * Gets the page directory entry for the specified address (32-bit paging).
3664 *
3665 * @returns The page directory entry in question.
3666 * @param pPGM Pointer to the PGM instance data.
3667 * @param GCPtr The address.
3668 */
3669DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3670{
3671#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3672 PCX86PD pGuestPD = 0;
3673 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3674 if (RT_FAILURE(rc))
3675 {
3676 X86PDE ZeroPde = {0};
3677 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3678 }
3679 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3680#else
3681 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3682#endif
3683}
3684
3685
3686/**
3687 * Gets the address of a specific page directory entry (32-bit paging).
3688 *
3689 * @returns Pointer the page directory entry in question.
3690 * @param pPGM Pointer to the PGM instance data.
3691 * @param GCPtr The address.
3692 */
3693DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3694{
3695#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3696 PX86PD pGuestPD = 0;
3697 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3698 AssertRCReturn(rc, 0);
3699 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3700#else
3701 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3702#endif
3703}
3704
3705
3706/**
3707 * Gets the address the guest page directory (32-bit paging).
3708 *
3709 * @returns Pointer the page directory entry in question.
3710 * @param pPGM Pointer to the PGM instance data.
3711 */
3712DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3713{
3714#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3715 PX86PD pGuestPD = 0;
3716 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3717 AssertRCReturn(rc, 0);
3718 return pGuestPD;
3719#else
3720 return pPGM->CTX_SUFF(pGst32BitPd);
3721#endif
3722}
3723
3724
3725/**
3726 * Gets the guest page directory pointer table.
3727 *
3728 * @returns Pointer to the page directory in question.
3729 * @returns NULL if the page directory is not present or on an invalid page.
3730 * @param pPGM Pointer to the PGM instance data.
3731 */
3732DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3733{
3734#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3735 PX86PDPT pGuestPDPT = 0;
3736 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3737 AssertRCReturn(rc, 0);
3738 return pGuestPDPT;
3739#else
3740 return pPGM->CTX_SUFF(pGstPaePdpt);
3741#endif
3742}
3743
3744
3745/**
3746 * Gets the guest page directory pointer table entry for the specified address.
3747 *
3748 * @returns Pointer to the page directory in question.
3749 * @returns NULL if the page directory is not present or on an invalid page.
3750 * @param pPGM Pointer to the PGM instance data.
3751 * @param GCPtr The address.
3752 */
3753DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3754{
3755 AssertGCPtr32(GCPtr);
3756
3757#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3758 PX86PDPT pGuestPDPT = 0;
3759 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3760 AssertRCReturn(rc, 0);
3761 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3762#else
3763 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3764#endif
3765}
3766
3767
3768/**
3769 * Gets the page directory for the specified address.
3770 *
3771 * @returns Pointer to the page directory in question.
3772 * @returns NULL if the page directory is not present or on an invalid page.
3773 * @param pPGM Pointer to the PGM instance data.
3774 * @param GCPtr The address.
3775 */
3776DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3777{
3778 AssertGCPtr32(GCPtr);
3779
3780#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3781 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3782 AssertReturn(pGuestPDPT, 0);
3783#else
3784 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3785#endif
3786 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3787 if (pGuestPDPT->a[iPdPt].n.u1Present)
3788 {
3789#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3790 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3791 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3792#endif
3793
3794 /* cache is out-of-sync. */
3795 PX86PDPAE pPD;
3796 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3797 if (RT_SUCCESS(rc))
3798 return pPD;
3799 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3800 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3801 }
3802 return NULL;
3803}
3804
3805
3806/**
3807 * Gets the page directory entry for the specified address.
3808 *
3809 * @returns Pointer to the page directory entry in question.
3810 * @returns NULL if the page directory is not present or on an invalid page.
3811 * @param pPGM Pointer to the PGM instance data.
3812 * @param GCPtr The address.
3813 */
3814DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3815{
3816 AssertGCPtr32(GCPtr);
3817
3818#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3819 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3820 AssertReturn(pGuestPDPT, 0);
3821#else
3822 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3823#endif
3824 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3825 if (pGuestPDPT->a[iPdPt].n.u1Present)
3826 {
3827 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3828#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3829 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3830 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3831#endif
3832
3833 /* The cache is out-of-sync. */
3834 PX86PDPAE pPD;
3835 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3836 if (RT_SUCCESS(rc))
3837 return &pPD->a[iPD];
3838 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3839 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3840 }
3841 return NULL;
3842}
3843
3844
3845/**
3846 * Gets the page directory entry for the specified address.
3847 *
3848 * @returns The page directory entry in question.
3849 * @returns A non-present entry if the page directory is not present or on an invalid page.
3850 * @param pPGM Pointer to the PGM instance data.
3851 * @param GCPtr The address.
3852 */
3853DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3854{
3855 AssertGCPtr32(GCPtr);
3856
3857#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3858 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3859 if (RT_LIKELY(pGuestPDPT))
3860#else
3861 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3862#endif
3863 {
3864 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3865 if (pGuestPDPT->a[iPdPt].n.u1Present)
3866 {
3867 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3868#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3869 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3870 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3871#endif
3872
3873 /* cache is out-of-sync. */
3874 PX86PDPAE pPD;
3875 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3876 if (RT_SUCCESS(rc))
3877 return pPD->a[iPD];
3878 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3879 }
3880 }
3881 X86PDEPAE ZeroPde = {0};
3882 return ZeroPde;
3883}
3884
3885
3886/**
3887 * Gets the page directory pointer table entry for the specified address
3888 * and returns the index into the page directory
3889 *
3890 * @returns Pointer to the page directory in question.
3891 * @returns NULL if the page directory is not present or on an invalid page.
3892 * @param pPGM Pointer to the PGM instance data.
3893 * @param GCPtr The address.
3894 * @param piPD Receives the index into the returned page directory
3895 * @param pPdpe Receives the page directory pointer entry. Optional.
3896 */
3897DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3898{
3899 AssertGCPtr32(GCPtr);
3900
3901#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3902 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3903 AssertReturn(pGuestPDPT, 0);
3904#else
3905 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3906#endif
3907 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3908 if (pPdpe)
3909 *pPdpe = pGuestPDPT->a[iPdPt];
3910 if (pGuestPDPT->a[iPdPt].n.u1Present)
3911 {
3912 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3913#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3914 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3915 {
3916 *piPD = iPD;
3917 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3918 }
3919#endif
3920
3921 /* cache is out-of-sync. */
3922 PX86PDPAE pPD;
3923 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3924 if (RT_SUCCESS(rc))
3925 {
3926 *piPD = iPD;
3927 return pPD;
3928 }
3929 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3930 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3931 }
3932 return NULL;
3933}
3934
3935#ifndef IN_RC
3936
3937/**
3938 * Gets the page map level-4 pointer for the guest.
3939 *
3940 * @returns Pointer to the PML4 page.
3941 * @param pPGM Pointer to the PGM instance data.
3942 */
3943DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3944{
3945#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3946 PX86PML4 pGuestPml4;
3947 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3948 AssertRCReturn(rc, NULL);
3949 return pGuestPml4;
3950#else
3951 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3952 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3953#endif
3954}
3955
3956
3957/**
3958 * Gets the pointer to a page map level-4 entry.
3959 *
3960 * @returns Pointer to the PML4 entry.
3961 * @param pPGM Pointer to the PGM instance data.
3962 * @param iPml4 The index.
3963 */
3964DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3965{
3966#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3967 PX86PML4 pGuestPml4;
3968 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3969 AssertRCReturn(rc, NULL);
3970 return &pGuestPml4->a[iPml4];
3971#else
3972 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3973 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3974#endif
3975}
3976
3977
3978/**
3979 * Gets a page map level-4 entry.
3980 *
3981 * @returns The PML4 entry.
3982 * @param pPGM Pointer to the PGM instance data.
3983 * @param iPml4 The index.
3984 */
3985DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3986{
3987#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3988 PX86PML4 pGuestPml4;
3989 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3990 if (RT_FAILURE(rc))
3991 {
3992 X86PML4E ZeroPml4e = {0};
3993 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3994 }
3995 return pGuestPml4->a[iPml4];
3996#else
3997 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3998 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3999#endif
4000}
4001
4002
4003/**
4004 * Gets the page directory pointer entry for the specified address.
4005 *
4006 * @returns Pointer to the page directory pointer entry in question.
4007 * @returns NULL if the page directory is not present or on an invalid page.
4008 * @param pPGM Pointer to the PGM instance data.
4009 * @param GCPtr The address.
4010 * @param ppPml4e Page Map Level-4 Entry (out)
4011 */
4012DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4013{
4014 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4015 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4016 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4017 if (pPml4e->n.u1Present)
4018 {
4019 PX86PDPT pPdpt;
4020 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4021 AssertRCReturn(rc, NULL);
4022
4023 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4024 return &pPdpt->a[iPdPt];
4025 }
4026 return NULL;
4027}
4028
4029
4030/**
4031 * Gets the page directory entry for the specified address.
4032 *
4033 * @returns The page directory entry in question.
4034 * @returns A non-present entry if the page directory is not present or on an invalid page.
4035 * @param pPGM Pointer to the PGM instance data.
4036 * @param GCPtr The address.
4037 * @param ppPml4e Page Map Level-4 Entry (out)
4038 * @param pPdpe Page directory pointer table entry (out)
4039 */
4040DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4041{
4042 X86PDEPAE ZeroPde = {0};
4043 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4044 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4045 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4046 if (pPml4e->n.u1Present)
4047 {
4048 PCX86PDPT pPdptTemp;
4049 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4050 AssertRCReturn(rc, ZeroPde);
4051
4052 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4053 *pPdpe = pPdptTemp->a[iPdPt];
4054 if (pPdptTemp->a[iPdPt].n.u1Present)
4055 {
4056 PCX86PDPAE pPD;
4057 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4058 AssertRCReturn(rc, ZeroPde);
4059
4060 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4061 return pPD->a[iPD];
4062 }
4063 }
4064
4065 return ZeroPde;
4066}
4067
4068
4069/**
4070 * Gets the page directory entry for the specified address.
4071 *
4072 * @returns The page directory entry in question.
4073 * @returns A non-present entry if the page directory is not present or on an invalid page.
4074 * @param pPGM Pointer to the PGM instance data.
4075 * @param GCPtr The address.
4076 */
4077DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4078{
4079 X86PDEPAE ZeroPde = {0};
4080 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4081 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4082 if (pGuestPml4->a[iPml4].n.u1Present)
4083 {
4084 PCX86PDPT pPdptTemp;
4085 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4086 AssertRCReturn(rc, ZeroPde);
4087
4088 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4089 if (pPdptTemp->a[iPdPt].n.u1Present)
4090 {
4091 PCX86PDPAE pPD;
4092 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4093 AssertRCReturn(rc, ZeroPde);
4094
4095 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4096 return pPD->a[iPD];
4097 }
4098 }
4099 return ZeroPde;
4100}
4101
4102
4103/**
4104 * Gets the page directory entry for the specified address.
4105 *
4106 * @returns Pointer to the page directory entry in question.
4107 * @returns NULL if the page directory is not present or on an invalid page.
4108 * @param pPGM Pointer to the PGM instance data.
4109 * @param GCPtr The address.
4110 */
4111DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4112{
4113 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4114 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4115 if (pGuestPml4->a[iPml4].n.u1Present)
4116 {
4117 PCX86PDPT pPdptTemp;
4118 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4119 AssertRCReturn(rc, NULL);
4120
4121 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4122 if (pPdptTemp->a[iPdPt].n.u1Present)
4123 {
4124 PX86PDPAE pPD;
4125 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4126 AssertRCReturn(rc, NULL);
4127
4128 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4129 return &pPD->a[iPD];
4130 }
4131 }
4132 return NULL;
4133}
4134
4135
4136/**
4137 * Gets the GUEST page directory pointer for the specified address.
4138 *
4139 * @returns The page directory in question.
4140 * @returns NULL if the page directory is not present or on an invalid page.
4141 * @param pPGM Pointer to the PGM instance data.
4142 * @param GCPtr The address.
4143 * @param ppPml4e Page Map Level-4 Entry (out)
4144 * @param pPdpe Page directory pointer table entry (out)
4145 * @param piPD Receives the index into the returned page directory
4146 */
4147DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4148{
4149 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4150 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4151 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4152 if (pPml4e->n.u1Present)
4153 {
4154 PCX86PDPT pPdptTemp;
4155 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4156 AssertRCReturn(rc, NULL);
4157
4158 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4159 *pPdpe = pPdptTemp->a[iPdPt];
4160 if (pPdptTemp->a[iPdPt].n.u1Present)
4161 {
4162 PX86PDPAE pPD;
4163 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4164 AssertRCReturn(rc, NULL);
4165
4166 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4167 return pPD;
4168 }
4169 }
4170 return 0;
4171}
4172
4173#endif /* !IN_RC */
4174
4175
4176/**
4177 * Gets the shadow page directory, 32-bit.
4178 *
4179 * @returns Pointer to the shadow 32-bit PD.
4180 * @param pPGM Pointer to the PGM instance data.
4181 */
4182DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4183{
4184#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4185 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4186#else
4187# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4188 PX86PD pShwPd;
4189 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4190 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4191 AssertRCReturn(rc, NULL);
4192 return pShwPd;
4193# else
4194 return pPGM->CTX_SUFF(pShw32BitPd);
4195# endif
4196#endif
4197}
4198
4199
4200/**
4201 * Gets the shadow page directory entry for the specified address, 32-bit.
4202 *
4203 * @returns Shadow 32-bit PDE.
4204 * @param pPGM Pointer to the PGM instance data.
4205 * @param GCPtr The address.
4206 */
4207DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4208{
4209 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4210
4211 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4212 if (!pShwPde)
4213 {
4214 X86PDE ZeroPde = {0};
4215 return ZeroPde;
4216 }
4217 return pShwPde->a[iPd];
4218}
4219
4220
4221/**
4222 * Gets the pointer to the shadow page directory entry for the specified
4223 * address, 32-bit.
4224 *
4225 * @returns Pointer to the shadow 32-bit PDE.
4226 * @param pPGM Pointer to the PGM instance data.
4227 * @param GCPtr The address.
4228 */
4229DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4230{
4231 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4232
4233 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4234 AssertReturn(pPde, NULL);
4235 return &pPde->a[iPd];
4236}
4237
4238
4239/**
4240 * Gets the shadow page pointer table, PAE.
4241 *
4242 * @returns Pointer to the shadow PAE PDPT.
4243 * @param pPGM Pointer to the PGM instance data.
4244 */
4245DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4246{
4247#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4248 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4249#else
4250# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4251 PX86PDPT pShwPdpt;
4252 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4253 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4254 AssertRCReturn(rc, 0);
4255 return pShwPdpt;
4256# else
4257 return pPGM->CTX_SUFF(pShwPaePdpt);
4258# endif
4259#endif
4260}
4261
4262
4263/**
4264 * Gets the shadow page directory for the specified address, PAE.
4265 *
4266 * @returns Pointer to the shadow PD.
4267 * @param pPGM Pointer to the PGM instance data.
4268 * @param GCPtr The address.
4269 */
4270DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4271{
4272#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4273 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4274 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4275
4276 if (!pPdpt->a[iPdpt].n.u1Present)
4277 return NULL;
4278
4279 /* Fetch the pgm pool shadow descriptor. */
4280 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4281 AssertReturn(pShwPde, NULL);
4282
4283 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4284#else
4285 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4286# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4287 PX86PDPAE pPD;
4288 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4289 AssertRCReturn(rc, 0);
4290 return pPD;
4291# else
4292 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4293 Assert(pPD);
4294 return pPD;
4295# endif
4296#endif
4297}
4298
4299/**
4300 * Gets the shadow page directory for the specified address, PAE.
4301 *
4302 * @returns Pointer to the shadow PD.
4303 * @param pPGM Pointer to the PGM instance data.
4304 * @param GCPtr The address.
4305 */
4306DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4307{
4308#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4309 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4310
4311 if (!pPdpt->a[iPdpt].n.u1Present)
4312 return NULL;
4313
4314 /* Fetch the pgm pool shadow descriptor. */
4315 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4316 AssertReturn(pShwPde, NULL);
4317
4318 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4319#else
4320 AssertFailed();
4321 return NULL;
4322#endif
4323}
4324
4325/**
4326 * Gets the shadow page directory entry, PAE.
4327 *
4328 * @returns PDE.
4329 * @param pPGM Pointer to the PGM instance data.
4330 * @param GCPtr The address.
4331 */
4332DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4333{
4334 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4335
4336 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4337 if (!pShwPde)
4338 {
4339 X86PDEPAE ZeroPde = {0};
4340 return ZeroPde;
4341 }
4342 return pShwPde->a[iPd];
4343}
4344
4345
4346/**
4347 * Gets the pointer to the shadow page directory entry for an address, PAE.
4348 *
4349 * @returns Pointer to the PDE.
4350 * @param pPGM Pointer to the PGM instance data.
4351 * @param GCPtr The address.
4352 */
4353DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4354{
4355 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4356
4357 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4358 AssertReturn(pPde, NULL);
4359 return &pPde->a[iPd];
4360}
4361
4362#ifndef IN_RC
4363/**
4364 * Gets the shadow page map level-4 pointer.
4365 *
4366 * @returns Pointer to the shadow PML4.
4367 * @param pPGM Pointer to the PGM instance data.
4368 */
4369DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4370{
4371#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4372 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4373#else
4374# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4375 PX86PML4 pShwPml4;
4376 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4377 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4378 AssertRCReturn(rc, 0);
4379 return pShwPml4;
4380# else
4381 Assert(pPGM->CTX_SUFF(pShwRoot));
4382 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4383# endif
4384#endif
4385}
4386
4387
4388/**
4389 * Gets the shadow page map level-4 entry for the specified address.
4390 *
4391 * @returns The entry.
4392 * @param pPGM Pointer to the PGM instance data.
4393 * @param GCPtr The address.
4394 */
4395DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4396{
4397 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4398 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4399
4400 if (!pShwPml4)
4401 {
4402 X86PML4E ZeroPml4e = {0};
4403 return ZeroPml4e;
4404 }
4405 return pShwPml4->a[iPml4];
4406}
4407
4408
4409/**
4410 * Gets the pointer to the specified shadow page map level-4 entry.
4411 *
4412 * @returns The entry.
4413 * @param pPGM Pointer to the PGM instance data.
4414 * @param iPml4 The PML4 index.
4415 */
4416DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4417{
4418 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4419 if (!pShwPml4)
4420 return NULL;
4421 return &pShwPml4->a[iPml4];
4422}
4423
4424
4425/**
4426 * Gets the GUEST page directory pointer for the specified address.
4427 *
4428 * @returns The page directory in question.
4429 * @returns NULL if the page directory is not present or on an invalid page.
4430 * @param pPGM Pointer to the PGM instance data.
4431 * @param GCPtr The address.
4432 * @param piPD Receives the index into the returned page directory
4433 */
4434DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4435{
4436 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4437 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4438 if (pGuestPml4->a[iPml4].n.u1Present)
4439 {
4440 PCX86PDPT pPdptTemp;
4441 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4442 AssertRCReturn(rc, NULL);
4443
4444 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4445 if (pPdptTemp->a[iPdPt].n.u1Present)
4446 {
4447 PX86PDPAE pPD;
4448 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4449 AssertRCReturn(rc, NULL);
4450
4451 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4452 return pPD;
4453 }
4454 }
4455 return NULL;
4456}
4457
4458#endif /* !IN_RC */
4459
4460/**
4461 * Checks if any of the specified page flags are set for the given page.
4462 *
4463 * @returns true if any of the flags are set.
4464 * @returns false if all the flags are clear.
4465 * @param pPGM PGM handle.
4466 * @param GCPhys The GC physical address.
4467 * @param fFlags The flags to check for.
4468 */
4469DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4470{
4471 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4472 return pPage
4473 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4474}
4475
4476
4477/**
4478 * Gets the page state for a physical handler.
4479 *
4480 * @returns The physical handler page state.
4481 * @param pCur The physical handler in question.
4482 */
4483DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4484{
4485 switch (pCur->enmType)
4486 {
4487 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4488 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4489
4490 case PGMPHYSHANDLERTYPE_MMIO:
4491 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4492 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4493
4494 default:
4495 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4496 }
4497}
4498
4499
4500/**
4501 * Gets the page state for a virtual handler.
4502 *
4503 * @returns The virtual handler page state.
4504 * @param pCur The virtual handler in question.
4505 * @remarks This should never be used on a hypervisor access handler.
4506 */
4507DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4508{
4509 switch (pCur->enmType)
4510 {
4511 case PGMVIRTHANDLERTYPE_WRITE:
4512 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4513 case PGMVIRTHANDLERTYPE_ALL:
4514 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4515 default:
4516 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4517 }
4518}
4519
4520
4521/**
4522 * Clears one physical page of a virtual handler
4523 *
4524 * @param pPGM Pointer to the PGM instance.
4525 * @param pCur Virtual handler structure
4526 * @param iPage Physical page index
4527 *
4528 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4529 * need to care about other handlers in the same page.
4530 */
4531DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4532{
4533 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4534
4535 /*
4536 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4537 */
4538#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4539 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4540 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4541 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4542#endif
4543 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4544 {
4545 /* We're the head of the alias chain. */
4546 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4547#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4548 AssertReleaseMsg(pRemove != NULL,
4549 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4550 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4551 AssertReleaseMsg(pRemove == pPhys2Virt,
4552 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4553 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4554 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4555 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4556#endif
4557 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4558 {
4559 /* Insert the next list in the alias chain into the tree. */
4560 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4561#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4562 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4563 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4564 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4565#endif
4566 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4567 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4568 AssertRelease(fRc);
4569 }
4570 }
4571 else
4572 {
4573 /* Locate the previous node in the alias chain. */
4574 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4575#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4576 AssertReleaseMsg(pPrev != pPhys2Virt,
4577 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4578 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4579#endif
4580 for (;;)
4581 {
4582 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4583 if (pNext == pPhys2Virt)
4584 {
4585 /* unlink. */
4586 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4587 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4588 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4589 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4590 else
4591 {
4592 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4593 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4594 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4595 }
4596 break;
4597 }
4598
4599 /* next */
4600 if (pNext == pPrev)
4601 {
4602#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4603 AssertReleaseMsg(pNext != pPrev,
4604 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4605 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4606#endif
4607 break;
4608 }
4609 pPrev = pNext;
4610 }
4611 }
4612 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4613 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4614 pPhys2Virt->offNextAlias = 0;
4615 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4616
4617 /*
4618 * Clear the ram flags for this page.
4619 */
4620 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4621 AssertReturnVoid(pPage);
4622 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4623}
4624
4625
4626/**
4627 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4628 *
4629 * @returns Pointer to the shadow page structure.
4630 * @param pPool The pool.
4631 * @param HCPhys The HC physical address of the shadow page.
4632 */
4633DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4634{
4635 /*
4636 * Look up the page.
4637 */
4638 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4639 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4640 return pPage;
4641}
4642
4643
4644/**
4645 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4646 *
4647 * @returns Pointer to the shadow page structure.
4648 * @param pPool The pool.
4649 * @param idx The pool page index.
4650 */
4651DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4652{
4653 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4654 return &pPool->aPages[idx];
4655}
4656
4657
4658#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4659/**
4660 * Clear references to guest physical memory.
4661 *
4662 * @param pPool The pool.
4663 * @param pPoolPage The pool page.
4664 * @param pPhysPage The physical guest page tracking structure.
4665 */
4666DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4667{
4668 /*
4669 * Just deal with the simple case here.
4670 */
4671# ifdef LOG_ENABLED
4672 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4673# endif
4674 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4675 if (cRefs == 1)
4676 {
4677 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4678 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4679 }
4680 else
4681 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4682 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4683}
4684#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4685
4686
4687#ifdef PGMPOOL_WITH_CACHE
4688/**
4689 * Moves the page to the head of the age list.
4690 *
4691 * This is done when the cached page is used in one way or another.
4692 *
4693 * @param pPool The pool.
4694 * @param pPage The cached page.
4695 * @todo inline in PGMInternal.h!
4696 */
4697DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4698{
4699 /*
4700 * Move to the head of the age list.
4701 */
4702 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4703 {
4704 /* unlink */
4705 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4706 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4707 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4708 else
4709 pPool->iAgeTail = pPage->iAgePrev;
4710
4711 /* insert at head */
4712 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4713 pPage->iAgeNext = pPool->iAgeHead;
4714 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4715 pPool->iAgeHead = pPage->idx;
4716 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4717 }
4718}
4719#endif /* PGMPOOL_WITH_CACHE */
4720
4721/**
4722 * Tells if mappings are to be put into the shadow page table or not
4723 *
4724 * @returns boolean result
4725 * @param pVM VM handle.
4726 */
4727
4728DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4729{
4730#ifdef IN_RING0
4731 /* There are no mappings in VT-x and AMD-V mode. */
4732 Assert(pPGM->fDisableMappings);
4733 return false;
4734#else
4735 return !pPGM->fDisableMappings;
4736#endif
4737}
4738
4739/** @} */
4740
4741#endif
4742
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