VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17130

Last change on this file since 17130 was 17057, checked in by vboxsync, 16 years ago

Experiment with temporarily locking dynamic pages
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1/* $Id: PGMInternal.h 17057 2009-02-24 12:14:19Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59//#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** Mark a dynamic map entry (PGMDynMapHCPage) as locked. */
188#define PGM_PTFLAGS_DYN_LOCKED RT_BIT(9)
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGM
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page when in GC does nothing in HC.
333 *
334 * @param GCVirt The virtual address of the page to invalidate.
335 */
336#ifdef IN_RC
337# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
338#elif defined(IN_RING0)
339# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340#else
341# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
342#endif
343
344/** @def PGM_INVL_BIG_PG
345 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
346 *
347 * @param GCVirt The virtual address within the page directory to invalidate.
348 */
349#ifdef IN_RC
350# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
351#elif defined(IN_RING0)
352# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353#else
354# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
355#endif
356
357/** @def PGM_INVL_GUEST_TLBS()
358 * Invalidates all guest TLBs.
359 */
360#ifdef IN_RC
361# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
362#elif defined(IN_RING0)
363# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364#else
365# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
366#endif
367
368
369/**
370 * Structure for tracking GC Mappings.
371 *
372 * This structure is used by linked list in both GC and HC.
373 */
374typedef struct PGMMAPPING
375{
376 /** Pointer to next entry. */
377 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378 /** Pointer to next entry. */
379 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380 /** Pointer to next entry. */
381 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382 /** Indicate whether this entry is finalized. */
383 bool fFinalized;
384 /** Start Virtual address. */
385 RTGCPTR GCPtr;
386 /** Last Virtual address (inclusive). */
387 RTGCPTR GCPtrLast;
388 /** Range size (bytes). */
389 RTGCPTR cb;
390 /** Pointer to relocation callback function. */
391 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392 /** User argument to the callback. */
393 R3PTRTYPE(void *) pvUser;
394 /** Mapping description / name. For easing debugging. */
395 R3PTRTYPE(const char *) pszDesc;
396 /** Number of page tables. */
397 uint32_t cPTs;
398#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
399 uint32_t uPadding1; /**< Alignment padding. */
400#endif
401 /** Array of page table mapping data. Each entry
402 * describes one page table. The array can be longer
403 * than the declared length.
404 */
405 struct
406 {
407 /** The HC physical address of the page table. */
408 RTHCPHYS HCPhysPT;
409 /** The HC physical address of the first PAE page table. */
410 RTHCPHYS HCPhysPaePT0;
411 /** The HC physical address of the second PAE page table. */
412 RTHCPHYS HCPhysPaePT1;
413 /** The HC virtual address of the 32-bit page table. */
414 R3PTRTYPE(PX86PT) pPTR3;
415 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
416 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
417 /** The GC virtual address of the 32-bit page table. */
418 RCPTRTYPE(PX86PT) pPTRC;
419 /** The GC virtual address of the two PAE page table. */
420 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
421 /** The GC virtual address of the 32-bit page table. */
422 R0PTRTYPE(PX86PT) pPTR0;
423 /** The GC virtual address of the two PAE page table. */
424 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
425 } aPTs[1];
426} PGMMAPPING;
427/** Pointer to structure for tracking GC Mappings. */
428typedef struct PGMMAPPING *PPGMMAPPING;
429
430
431/**
432 * Physical page access handler structure.
433 *
434 * This is used to keep track of physical address ranges
435 * which are being monitored in some kind of way.
436 */
437typedef struct PGMPHYSHANDLER
438{
439 AVLROGCPHYSNODECORE Core;
440 /** Access type. */
441 PGMPHYSHANDLERTYPE enmType;
442 /** Number of pages to update. */
443 uint32_t cPages;
444 /** Pointer to R3 callback function. */
445 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
446 /** User argument for R3 handlers. */
447 R3PTRTYPE(void *) pvUserR3;
448 /** Pointer to R0 callback function. */
449 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
450 /** User argument for R0 handlers. */
451 R0PTRTYPE(void *) pvUserR0;
452 /** Pointer to GC callback function. */
453 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
454 /** User argument for RC handlers. */
455 RCPTRTYPE(void *) pvUserRC;
456 /** Description / Name. For easing debugging. */
457 R3PTRTYPE(const char *) pszDesc;
458#ifdef VBOX_WITH_STATISTICS
459 /** Profiling of this handler. */
460 STAMPROFILE Stat;
461#endif
462} PGMPHYSHANDLER;
463/** Pointer to a physical page access handler structure. */
464typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
465
466
467/**
468 * Cache node for the physical addresses covered by a virtual handler.
469 */
470typedef struct PGMPHYS2VIRTHANDLER
471{
472 /** Core node for the tree based on physical ranges. */
473 AVLROGCPHYSNODECORE Core;
474 /** Offset from this struct to the PGMVIRTHANDLER structure. */
475 int32_t offVirtHandler;
476 /** Offset of the next alias relative to this one.
477 * Bit 0 is used for indicating whether we're in the tree.
478 * Bit 1 is used for indicating that we're the head node.
479 */
480 int32_t offNextAlias;
481} PGMPHYS2VIRTHANDLER;
482/** Pointer to a phys to virtual handler structure. */
483typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
484
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the tree. */
487#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
488/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489 * node is in the head of an alias chain.
490 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
491#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
492/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
493#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
494
495
496/**
497 * Virtual page access handler structure.
498 *
499 * This is used to keep track of virtual address ranges
500 * which are being monitored in some kind of way.
501 */
502typedef struct PGMVIRTHANDLER
503{
504 /** Core node for the tree based on virtual ranges. */
505 AVLROGCPTRNODECORE Core;
506 /** Size of the range (in bytes). */
507 RTGCPTR cb;
508 /** Number of cache pages. */
509 uint32_t cPages;
510 /** Access type. */
511 PGMVIRTHANDLERTYPE enmType;
512 /** Pointer to the RC callback function. */
513 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
514#if HC_ARCH_BITS == 64
515 RTRCPTR padding;
516#endif
517 /** Pointer to the R3 callback function for invalidation. */
518 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
519 /** Pointer to the R3 callback function. */
520 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
521 /** Description / Name. For easing debugging. */
522 R3PTRTYPE(const char *) pszDesc;
523#ifdef VBOX_WITH_STATISTICS
524 /** Profiling of this handler. */
525 STAMPROFILE Stat;
526#endif
527 /** Array of cached physical addresses for the monitored ranged. */
528 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
529} PGMVIRTHANDLER;
530/** Pointer to a virtual page access handler structure. */
531typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
532
533
534/**
535 * Page type.
536 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
537 * @todo convert to \#defines.
538 */
539typedef enum PGMPAGETYPE
540{
541 /** The usual invalid zero entry. */
542 PGMPAGETYPE_INVALID = 0,
543 /** RAM page. (RWX) */
544 PGMPAGETYPE_RAM,
545 /** MMIO2 page. (RWX) */
546 PGMPAGETYPE_MMIO2,
547 /** Shadowed ROM. (RWX) */
548 PGMPAGETYPE_ROM_SHADOW,
549 /** ROM page. (R-X) */
550 PGMPAGETYPE_ROM,
551 /** MMIO page. (---) */
552 PGMPAGETYPE_MMIO,
553 /** End of valid entries. */
554 PGMPAGETYPE_END
555} PGMPAGETYPE;
556AssertCompile(PGMPAGETYPE_END < 7);
557
558/** @name Page type predicates.
559 * @{ */
560#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
561#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
562#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
563#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
565/** @} */
566
567
568/**
569 * A Physical Guest Page tracking structure.
570 *
571 * The format of this structure is complicated because we have to fit a lot
572 * of information into as few bits as possible. The format is also subject
573 * to change (there is one comming up soon). Which means that for we'll be
574 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
575 * accessess to the structure.
576 */
577typedef struct PGMPAGE
578{
579 /** The physical address and a whole lot of other stuff. All bits are used! */
580 RTHCPHYS HCPhys;
581 /** The page state. */
582 uint32_t u2StateX : 2;
583 /** Flag indicating that a write monitored page was written to when set. */
584 uint32_t fWrittenToX : 1;
585 /** For later. */
586 uint32_t fSomethingElse : 1;
587 /** The Page ID.
588 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
589 * The HCPhys will be 100% static. */
590 uint32_t idPageX : 28;
591 /** The page type (PGMPAGETYPE). */
592 uint32_t u3Type : 3;
593 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
594 uint32_t u2HandlerPhysStateX : 2;
595 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
596 uint32_t u2HandlerVirtStateX : 2;
597 uint32_t u29B : 25;
598} PGMPAGE;
599AssertCompileSize(PGMPAGE, 16);
600/** Pointer to a physical guest page. */
601typedef PGMPAGE *PPGMPAGE;
602/** Pointer to a const physical guest page. */
603typedef const PGMPAGE *PCPGMPAGE;
604/** Pointer to a physical guest page pointer. */
605typedef PPGMPAGE *PPPGMPAGE;
606
607
608/**
609 * Clears the page structure.
610 * @param pPage Pointer to the physical guest page tracking structure.
611 */
612#define PGM_PAGE_CLEAR(pPage) \
613 do { \
614 (pPage)->HCPhys = 0; \
615 (pPage)->u2StateX = 0; \
616 (pPage)->fWrittenToX = 0; \
617 (pPage)->fSomethingElse = 0; \
618 (pPage)->idPageX = 0; \
619 (pPage)->u3Type = 0; \
620 (pPage)->u29B = 0; \
621 } while (0)
622
623/**
624 * Initializes the page structure.
625 * @param pPage Pointer to the physical guest page tracking structure.
626 */
627#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
628 do { \
629 (pPage)->HCPhys = (_HCPhys); \
630 (pPage)->u2StateX = (_uState); \
631 (pPage)->fWrittenToX = 0; \
632 (pPage)->fSomethingElse = 0; \
633 (pPage)->idPageX = (_idPage); \
634 /*(pPage)->u3Type = (_uType); - later */ \
635 PGM_PAGE_SET_TYPE(pPage, _uType); \
636 (pPage)->u29B = 0; \
637 } while (0)
638
639/**
640 * Initializes the page structure of a ZERO page.
641 * @param pPage Pointer to the physical guest page tracking structure.
642 */
643#ifdef VBOX_WITH_NEW_PHYS_CODE
644# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
645 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
646#else
647# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
648 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649#endif
650/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
651# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
652 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
653
654
655/** @name The Page state, PGMPAGE::u2StateX.
656 * @{ */
657/** The zero page.
658 * This is a per-VM page that's never ever mapped writable. */
659#define PGM_PAGE_STATE_ZERO 0
660/** A allocated page.
661 * This is a per-VM page allocated from the page pool (or wherever
662 * we get MMIO2 pages from if the type is MMIO2).
663 */
664#define PGM_PAGE_STATE_ALLOCATED 1
665/** A allocated page that's being monitored for writes.
666 * The shadow page table mappings are read-only. When a write occurs, the
667 * fWrittenTo member is set, the page remapped as read-write and the state
668 * moved back to allocated. */
669#define PGM_PAGE_STATE_WRITE_MONITORED 2
670/** The page is shared, aka. copy-on-write.
671 * This is a page that's shared with other VMs. */
672#define PGM_PAGE_STATE_SHARED 3
673/** @} */
674
675
676/**
677 * Gets the page state.
678 * @returns page state (PGM_PAGE_STATE_*).
679 * @param pPage Pointer to the physical guest page tracking structure.
680 */
681#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
682
683/**
684 * Sets the page state.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 * @param _uState The new page state.
687 */
688#define PGM_PAGE_SET_STATE(pPage, _uState) \
689 do { (pPage)->u2StateX = (_uState); } while (0)
690
691
692/**
693 * Gets the host physical address of the guest page.
694 * @returns host physical address (RTHCPHYS).
695 * @param pPage Pointer to the physical guest page tracking structure.
696 */
697#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
698
699/**
700 * Sets the host physical address of the guest page.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 * @param _HCPhys The new host physical address.
703 */
704#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
705 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
706 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
707
708/**
709 * Get the Page ID.
710 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
711 * @param pPage Pointer to the physical guest page tracking structure.
712 */
713#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
714/* later:
715#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
716 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
717*/
718/**
719 * Sets the Page ID.
720 * @param pPage Pointer to the physical guest page tracking structure.
721 */
722#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
723/* later:
724#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
725 | ((_idPage) & 0xfff) \
726 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
727*/
728
729/**
730 * Get the Chunk ID.
731 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
732 * @param pPage Pointer to the physical guest page tracking structure.
733 */
734#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
735/* later:
736#if GMM_CHUNKID_SHIFT == 12
737# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
738#elif GMM_CHUNKID_SHIFT > 12
739# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
740#elif GMM_CHUNKID_SHIFT < 12
741# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
742 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
743#else
744# error "GMM_CHUNKID_SHIFT isn't defined or something."
745#endif
746*/
747
748/**
749 * Get the index of the page within the allocaiton chunk.
750 * @returns The page index.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
754/* later:
755#if GMM_CHUNKID_SHIFT <= 12
756# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
757#else
758# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
759 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
760#endif
761*/
762
763
764/**
765 * Gets the page type.
766 * @returns The page type.
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
770
771/**
772 * Sets the page type.
773 * @param pPage Pointer to the physical guest page tracking structure.
774 * @param _enmType The new page type (PGMPAGETYPE).
775 */
776#ifdef VBOX_WITH_NEW_PHYS_CODE
777#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
778 do { (pPage)->u3Type = (_enmType); } while (0)
779#else
780#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
781 do { \
782 (pPage)->u3Type = (_enmType); \
783 if ((_enmType) == PGMPAGETYPE_ROM) \
784 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
785 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
786 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
787 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
788 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
789 } while (0)
790#endif
791
792
793/**
794 * Checks if the page is 'reserved'.
795 * @returns true/false.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
799
800/**
801 * Checks if the page is marked for MMIO.
802 * @returns true/false.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
806
807/**
808 * Checks if the page is backed by the ZERO page.
809 * @returns true/false.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
813
814/**
815 * Checks if the page is backed by a SHARED page.
816 * @returns true/false.
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
820
821
822/**
823 * Marks the paget as written to (for GMM change monitoring).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
827
828/**
829 * Clears the written-to indicator.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 */
832#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
833
834/**
835 * Checks if the page was marked as written-to.
836 * @returns true/false.
837 * @param pPage Pointer to the physical guest page tracking structure.
838 */
839#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
840
841
842/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
843 *
844 * @remarks The values are assigned in order of priority, so we can calculate
845 * the correct state for a page with different handlers installed.
846 * @{ */
847/** No handler installed. */
848#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
849/** Monitoring is temporarily disabled. */
850#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
851/** Write access is monitored. */
852#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
853/** All access is monitored. */
854#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
855/** @} */
856
857/**
858 * Gets the physical access handler state of a page.
859 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
860 * @param pPage Pointer to the physical guest page tracking structure.
861 */
862#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
863
864/**
865 * Sets the physical access handler state of a page.
866 * @param pPage Pointer to the physical guest page tracking structure.
867 * @param _uState The new state value.
868 */
869#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
870 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
871
872/**
873 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
874 * @returns true/false
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
878
879/**
880 * Checks if the page has any active physical access handlers.
881 * @returns true/false
882 * @param pPage Pointer to the physical guest page tracking structure.
883 */
884#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
885
886
887/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
888 *
889 * @remarks The values are assigned in order of priority, so we can calculate
890 * the correct state for a page with different handlers installed.
891 * @{ */
892/** No handler installed. */
893#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
894/* 1 is reserved so the lineup is identical with the physical ones. */
895/** Write access is monitored. */
896#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
897/** All access is monitored. */
898#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
899/** @} */
900
901/**
902 * Gets the virtual access handler state of a page.
903 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
904 * @param pPage Pointer to the physical guest page tracking structure.
905 */
906#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
907
908/**
909 * Sets the virtual access handler state of a page.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 * @param _uState The new state value.
912 */
913#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
914 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
915
916/**
917 * Checks if the page has any virtual access handlers.
918 * @returns true/false
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
922
923/**
924 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
925 * virtual handlers.
926 * @returns true/false
927 * @param pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
930
931
932
933/**
934 * Checks if the page has any access handlers, including temporarily disabled ones.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
939 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
940 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
941
942/**
943 * Checks if the page has any active access handlers.
944 * @returns true/false
945 * @param pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
948 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
949 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
950
951/**
952 * Checks if the page has any active access handlers catching all accesses.
953 * @returns true/false
954 * @param pPage Pointer to the physical guest page tracking structure.
955 */
956#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
957 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
958 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
959
960
961/**
962 * Ram range for GC Phys to HC Phys conversion.
963 *
964 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
965 * conversions too, but we'll let MM handle that for now.
966 *
967 * This structure is used by linked lists in both GC and HC.
968 */
969typedef struct PGMRAMRANGE
970{
971 /** Pointer to the next RAM range - for R3. */
972 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
973 /** Pointer to the next RAM range - for R0. */
974 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
975 /** Pointer to the next RAM range - for RC. */
976 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
977 /** Pointer alignment. */
978 RTRCPTR RCPtrAlignment;
979 /** Start of the range. Page aligned. */
980 RTGCPHYS GCPhys;
981 /** Last address in the range (inclusive). Page aligned (-1). */
982 RTGCPHYS GCPhysLast;
983 /** Size of the range. (Page aligned of course). */
984 RTGCPHYS cb;
985 /** MM_RAM_* flags */
986 uint32_t fFlags;
987 uint32_t u32Alignment; /**< alignment. */
988#ifndef VBOX_WITH_NEW_PHYS_CODE
989 /** R3 virtual lookup ranges for chunks.
990 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
991 * @remarks This is occationally accessed from ring-0!! (not darwin) */
992# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
993 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
994# else
995 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
996# endif
997#endif
998 /** Start of the HC mapping of the range. This is only used for MMIO2. */
999 R3PTRTYPE(void *) pvR3;
1000 /** The range description. */
1001 R3PTRTYPE(const char *) pszDesc;
1002
1003 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1004#ifdef VBOX_WITH_NEW_PHYS_CODE
1005 uint32_t au32Reserved[2];
1006#elif HC_ARCH_BITS == 32
1007 uint32_t au32Reserved[1];
1008#endif
1009
1010 /** Array of physical guest page tracking structures. */
1011 PGMPAGE aPages[1];
1012} PGMRAMRANGE;
1013/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1014typedef PGMRAMRANGE *PPGMRAMRANGE;
1015
1016/** Return hc ptr corresponding to the ram range and physical offset */
1017#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1018 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1019 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1020
1021/**
1022 * Per page tracking structure for ROM image.
1023 *
1024 * A ROM image may have a shadow page, in which case we may have
1025 * two pages backing it. This structure contains the PGMPAGE for
1026 * both while PGMRAMRANGE have a copy of the active one. It is
1027 * important that these aren't out of sync in any regard other
1028 * than page pool tracking data.
1029 */
1030typedef struct PGMROMPAGE
1031{
1032 /** The page structure for the virgin ROM page. */
1033 PGMPAGE Virgin;
1034 /** The page structure for the shadow RAM page. */
1035 PGMPAGE Shadow;
1036 /** The current protection setting. */
1037 PGMROMPROT enmProt;
1038 /** Pad the structure size to a multiple of 8. */
1039 uint32_t u32Padding;
1040} PGMROMPAGE;
1041/** Pointer to a ROM page tracking structure. */
1042typedef PGMROMPAGE *PPGMROMPAGE;
1043
1044
1045/**
1046 * A registered ROM image.
1047 *
1048 * This is needed to keep track of ROM image since they generally
1049 * intrude into a PGMRAMRANGE. It also keeps track of additional
1050 * info like the two page sets (read-only virgin and read-write shadow),
1051 * the current state of each page.
1052 *
1053 * Because access handlers cannot easily be executed in a different
1054 * context, the ROM ranges needs to be accessible and in all contexts.
1055 */
1056typedef struct PGMROMRANGE
1057{
1058 /** Pointer to the next range - R3. */
1059 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1060 /** Pointer to the next range - R0. */
1061 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1062 /** Pointer to the next range - RC. */
1063 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1064 /** Pointer alignment */
1065 RTRCPTR GCPtrAlignment;
1066 /** Address of the range. */
1067 RTGCPHYS GCPhys;
1068 /** Address of the last byte in the range. */
1069 RTGCPHYS GCPhysLast;
1070 /** Size of the range. */
1071 RTGCPHYS cb;
1072 /** The flags (PGMPHYS_ROM_FLAG_*). */
1073 uint32_t fFlags;
1074 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1075 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1076 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1077 * This is used for strictness checks. */
1078 R3PTRTYPE(const void *) pvOriginal;
1079 /** The ROM description. */
1080 R3PTRTYPE(const char *) pszDesc;
1081 /** The per page tracking structures. */
1082 PGMROMPAGE aPages[1];
1083} PGMROMRANGE;
1084/** Pointer to a ROM range. */
1085typedef PGMROMRANGE *PPGMROMRANGE;
1086
1087
1088/**
1089 * A registered MMIO2 (= Device RAM) range.
1090 *
1091 * There are a few reason why we need to keep track of these
1092 * registrations. One of them is the deregistration & cleanup
1093 * stuff, while another is that the PGMRAMRANGE associated with
1094 * such a region may have to be removed from the ram range list.
1095 *
1096 * Overlapping with a RAM range has to be 100% or none at all. The
1097 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1098 * meditation will be raised if a partial overlap or an overlap of
1099 * ROM pages is encountered. On an overlap we will free all the
1100 * existing RAM pages and put in the ram range pages instead.
1101 */
1102typedef struct PGMMMIO2RANGE
1103{
1104 /** The owner of the range. (a device) */
1105 PPDMDEVINSR3 pDevInsR3;
1106 /** Pointer to the ring-3 mapping of the allocation. */
1107 RTR3PTR pvR3;
1108 /** Pointer to the next range - R3. */
1109 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1110 /** Whether it's mapped or not. */
1111 bool fMapped;
1112 /** Whether it's overlapping or not. */
1113 bool fOverlapping;
1114 /** The PCI region number.
1115 * @remarks This ASSUMES that nobody will ever really need to have multiple
1116 * PCI devices with matching MMIO region numbers on a single device. */
1117 uint8_t iRegion;
1118 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1119 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1120 /** The associated RAM range. */
1121 PGMRAMRANGE RamRange;
1122} PGMMMIO2RANGE;
1123/** Pointer to a MMIO2 range. */
1124typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1125
1126
1127
1128
1129/**
1130 * PGMPhysRead/Write cache entry
1131 */
1132typedef struct PGMPHYSCACHEENTRY
1133{
1134 /** R3 pointer to physical page. */
1135 R3PTRTYPE(uint8_t *) pbR3;
1136 /** GC Physical address for cache entry */
1137 RTGCPHYS GCPhys;
1138#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1139 RTGCPHYS u32Padding0; /**< alignment padding. */
1140#endif
1141} PGMPHYSCACHEENTRY;
1142
1143/**
1144 * PGMPhysRead/Write cache to reduce REM memory access overhead
1145 */
1146typedef struct PGMPHYSCACHE
1147{
1148 /** Bitmap of valid cache entries */
1149 uint64_t aEntries;
1150 /** Cache entries */
1151 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1152} PGMPHYSCACHE;
1153
1154
1155/** Pointer to an allocation chunk ring-3 mapping. */
1156typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1157/** Pointer to an allocation chunk ring-3 mapping pointer. */
1158typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1159
1160/**
1161 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1162 *
1163 * The primary tree (Core) uses the chunk id as key.
1164 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1165 */
1166typedef struct PGMCHUNKR3MAP
1167{
1168 /** The key is the chunk id. */
1169 AVLU32NODECORE Core;
1170 /** The key is the ageing sequence number. */
1171 AVLLU32NODECORE AgeCore;
1172 /** The current age thingy. */
1173 uint32_t iAge;
1174 /** The current reference count. */
1175 uint32_t volatile cRefs;
1176 /** The current permanent reference count. */
1177 uint32_t volatile cPermRefs;
1178 /** The mapping address. */
1179 void *pv;
1180} PGMCHUNKR3MAP;
1181
1182/**
1183 * Allocation chunk ring-3 mapping TLB entry.
1184 */
1185typedef struct PGMCHUNKR3MAPTLBE
1186{
1187 /** The chunk id. */
1188 uint32_t volatile idChunk;
1189#if HC_ARCH_BITS == 64
1190 uint32_t u32Padding; /**< alignment padding. */
1191#endif
1192 /** The chunk map. */
1193#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1194 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1195#else
1196 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1197#endif
1198} PGMCHUNKR3MAPTLBE;
1199/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1200typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1201
1202/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1203 * @remark Must be a power of two value. */
1204#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1205
1206/**
1207 * Allocation chunk ring-3 mapping TLB.
1208 *
1209 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1210 * At first glance this might look kinda odd since AVL trees are
1211 * supposed to give the most optimial lookup times of all trees
1212 * due to their balancing. However, take a tree with 1023 nodes
1213 * in it, that's 10 levels, meaning that most searches has to go
1214 * down 9 levels before they find what they want. This isn't fast
1215 * compared to a TLB hit. There is the factor of cache misses,
1216 * and of course the problem with trees and branch prediction.
1217 * This is why we use TLBs in front of most of the trees.
1218 *
1219 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1220 * difficult when we switch to the new inlined AVL trees (from kStuff).
1221 */
1222typedef struct PGMCHUNKR3MAPTLB
1223{
1224 /** The TLB entries. */
1225 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1226} PGMCHUNKR3MAPTLB;
1227
1228/**
1229 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1230 * @returns Chunk TLB index.
1231 * @param idChunk The Chunk ID.
1232 */
1233#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1234
1235
1236/**
1237 * Ring-3 guest page mapping TLB entry.
1238 * @remarks used in ring-0 as well at the moment.
1239 */
1240typedef struct PGMPAGER3MAPTLBE
1241{
1242 /** Address of the page. */
1243 RTGCPHYS volatile GCPhys;
1244 /** The guest page. */
1245#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1246 R3PTRTYPE(PPGMPAGE) volatile pPage;
1247#else
1248 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1249#endif
1250 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1251#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1252 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1253#else
1254 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1255#endif
1256 /** The address */
1257#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1258 R3PTRTYPE(void *) volatile pv;
1259#else
1260 R3R0PTRTYPE(void *) volatile pv;
1261#endif
1262#if HC_ARCH_BITS == 32
1263 uint32_t u32Padding; /**< alignment padding. */
1264#endif
1265} PGMPAGER3MAPTLBE;
1266/** Pointer to an entry in the HC physical TLB. */
1267typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1268
1269
1270/** The number of entries in the ring-3 guest page mapping TLB.
1271 * @remarks The value must be a power of two. */
1272#define PGM_PAGER3MAPTLB_ENTRIES 64
1273
1274/**
1275 * Ring-3 guest page mapping TLB.
1276 * @remarks used in ring-0 as well at the moment.
1277 */
1278typedef struct PGMPAGER3MAPTLB
1279{
1280 /** The TLB entries. */
1281 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1282} PGMPAGER3MAPTLB;
1283/** Pointer to the ring-3 guest page mapping TLB. */
1284typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1285
1286/**
1287 * Calculates the index of the TLB entry for the specified guest page.
1288 * @returns Physical TLB index.
1289 * @param GCPhys The guest physical address.
1290 */
1291#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1292
1293
1294/**
1295 * Mapping cache usage set entry.
1296 *
1297 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1298 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1299 * cache. If it's extended to include ring-3, well, then something will
1300 * have be changed here...
1301 */
1302typedef struct PGMMAPSETENTRY
1303{
1304 /** The mapping cache index. */
1305 uint16_t iPage;
1306 /** The number of references.
1307 * The max is UINT16_MAX - 1. */
1308 uint16_t cRefs;
1309 /** Pointer to the page. */
1310 RTR0PTR pvPage;
1311 /** The physical address for this entry. */
1312 RTHCPHYS HCPhys;
1313} PGMMAPSETENTRY;
1314/** Pointer to a mapping cache usage set entry. */
1315typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1316
1317/**
1318 * Mapping cache usage set.
1319 *
1320 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1321 * done during exits / traps. The set is
1322 */
1323typedef struct PGMMAPSET
1324{
1325 /** The number of occupied entries.
1326 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1327 * dynamic mappings. */
1328 uint32_t cEntries;
1329 /** The start of the current subset.
1330 * This is UINT32_MAX if no subset is currently open. */
1331 uint32_t iSubset;
1332 /** The index of the current CPU, only valid if the set is open. */
1333 int32_t iCpu;
1334 /** The entries. */
1335 PGMMAPSETENTRY aEntries[64];
1336 /** HCPhys -> iEntry fast lookup table.
1337 * Use PGMMAPSET_HASH for hashing.
1338 * The entries may or may not be valid, check against cEntries. */
1339 uint8_t aiHashTable[128];
1340} PGMMAPSET;
1341/** Pointer to the mapping cache set. */
1342typedef PGMMAPSET *PPGMMAPSET;
1343
1344/** PGMMAPSET::cEntries value for a closed set. */
1345#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1346
1347/** Hash function for aiHashTable. */
1348#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1349
1350/** The max fill size (strict builds). */
1351#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1352
1353
1354/** @name Context neutrual page mapper TLB.
1355 *
1356 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1357 * code is writting in a kind of context neutrual way. Time will show whether
1358 * this actually makes sense or not...
1359 *
1360 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1361 * context ends up using a global mapping cache on some platforms
1362 * (darwin).
1363 *
1364 * @{ */
1365/** @typedef PPGMPAGEMAPTLB
1366 * The page mapper TLB pointer type for the current context. */
1367/** @typedef PPGMPAGEMAPTLB
1368 * The page mapper TLB entry pointer type for the current context. */
1369/** @typedef PPGMPAGEMAPTLB
1370 * The page mapper TLB entry pointer pointer type for the current context. */
1371/** @def PGM_PAGEMAPTLB_ENTRIES
1372 * The number of TLB entries in the page mapper TLB for the current context. */
1373/** @def PGM_PAGEMAPTLB_IDX
1374 * Calculate the TLB index for a guest physical address.
1375 * @returns The TLB index.
1376 * @param GCPhys The guest physical address. */
1377/** @typedef PPGMPAGEMAP
1378 * Pointer to a page mapper unit for current context. */
1379/** @typedef PPPGMPAGEMAP
1380 * Pointer to a page mapper unit pointer for current context. */
1381#ifdef IN_RC
1382// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1383// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1384// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1385# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1386# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1387 typedef void * PPGMPAGEMAP;
1388 typedef void ** PPPGMPAGEMAP;
1389//#elif IN_RING0
1390// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1391// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1392// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1393//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1394//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1395// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1396// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1397#else
1398 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1399 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1400 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1401# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1402# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1403 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1404 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1405#endif
1406/** @} */
1407
1408
1409/** @name PGM Pool Indexes.
1410 * Aka. the unique shadow page identifier.
1411 * @{ */
1412/** NIL page pool IDX. */
1413#define NIL_PGMPOOL_IDX 0
1414/** The first normal index. */
1415#define PGMPOOL_IDX_FIRST_SPECIAL 1
1416#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1417/** Page directory (32-bit root). */
1418#define PGMPOOL_IDX_PD 1
1419/** Page Directory Pointer Table (PAE root). */
1420#define PGMPOOL_IDX_PDPT 2
1421/** AMD64 CR3 level index.*/
1422#define PGMPOOL_IDX_AMD64_CR3 3
1423/** Nested paging root.*/
1424#define PGMPOOL_IDX_NESTED_ROOT 4
1425/** The first normal index. */
1426#define PGMPOOL_IDX_FIRST 5
1427#else
1428/** Page directory (32-bit root). */
1429#define PGMPOOL_IDX_PD 1
1430/** The extended PAE page directory (2048 entries, works as root currently). */
1431#define PGMPOOL_IDX_PAE_PD 2
1432/** PAE Page Directory Table 0. */
1433#define PGMPOOL_IDX_PAE_PD_0 3
1434/** PAE Page Directory Table 1. */
1435#define PGMPOOL_IDX_PAE_PD_1 4
1436/** PAE Page Directory Table 2. */
1437#define PGMPOOL_IDX_PAE_PD_2 5
1438/** PAE Page Directory Table 3. */
1439#define PGMPOOL_IDX_PAE_PD_3 6
1440/** Page Directory Pointer Table (PAE root, not currently used). */
1441#define PGMPOOL_IDX_PDPT 7
1442/** AMD64 CR3 level index.*/
1443#define PGMPOOL_IDX_AMD64_CR3 8
1444/** Nested paging root.*/
1445#define PGMPOOL_IDX_NESTED_ROOT 9
1446/** The first normal index. */
1447#define PGMPOOL_IDX_FIRST 10
1448#endif
1449/** The last valid index. (inclusive, 14 bits) */
1450#define PGMPOOL_IDX_LAST 0x3fff
1451/** @} */
1452
1453/** The NIL index for the parent chain. */
1454#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1455
1456/**
1457 * Node in the chain linking a shadowed page to it's parent (user).
1458 */
1459#pragma pack(1)
1460typedef struct PGMPOOLUSER
1461{
1462 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1463 uint16_t iNext;
1464 /** The user page index. */
1465 uint16_t iUser;
1466 /** Index into the user table. */
1467 uint32_t iUserTable;
1468} PGMPOOLUSER, *PPGMPOOLUSER;
1469typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1470#pragma pack()
1471
1472
1473/** The NIL index for the phys ext chain. */
1474#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1475
1476/**
1477 * Node in the chain of physical cross reference extents.
1478 */
1479#pragma pack(1)
1480typedef struct PGMPOOLPHYSEXT
1481{
1482 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1483 uint16_t iNext;
1484 /** The user page index. */
1485 uint16_t aidx[3];
1486} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1487typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1488#pragma pack()
1489
1490
1491/**
1492 * The kind of page that's being shadowed.
1493 */
1494typedef enum PGMPOOLKIND
1495{
1496 /** The virtual invalid 0 entry. */
1497 PGMPOOLKIND_INVALID = 0,
1498 /** The entry is free (=unused). */
1499 PGMPOOLKIND_FREE,
1500
1501 /** Shw: 32-bit page table; Gst: no paging */
1502 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1503 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1504 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1505 /** Shw: 32-bit page table; Gst: 4MB page. */
1506 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1507 /** Shw: PAE page table; Gst: no paging */
1508 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1509 /** Shw: PAE page table; Gst: 32-bit page table. */
1510 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1511 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1512 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1513 /** Shw: PAE page table; Gst: PAE page table. */
1514 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1515 /** Shw: PAE page table; Gst: 2MB page. */
1516 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1517
1518 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1519 PGMPOOLKIND_32BIT_PD,
1520 /** Shw: 32-bit page directory. Gst: no paging. */
1521 PGMPOOLKIND_32BIT_PD_PHYS,
1522 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1523 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1524 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1525 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1526 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1527 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1528 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1529 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1530 /** Shw: PAE page directory; Gst: PAE page directory. */
1531 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1532 /** Shw: PAE page directory; Gst: no paging. */
1533 PGMPOOLKIND_PAE_PD_PHYS,
1534
1535 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1536 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1537 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1538 PGMPOOLKIND_PAE_PDPT,
1539 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1540 PGMPOOLKIND_PAE_PDPT_PHYS,
1541
1542 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1543 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1544 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1545 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1546 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1547 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1548 /** Shw: 64-bit page directory table; Gst: no paging */
1549 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1550
1551 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1552 PGMPOOLKIND_64BIT_PML4,
1553
1554 /** Shw: EPT page directory pointer table; Gst: no paging */
1555 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1556 /** Shw: EPT page directory table; Gst: no paging */
1557 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1558 /** Shw: EPT page table; Gst: no paging */
1559 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1560
1561#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1562 /** Shw: Root 32-bit page directory. */
1563 PGMPOOLKIND_ROOT_32BIT_PD,
1564 /** Shw: Root PAE page directory */
1565 PGMPOOLKIND_ROOT_PAE_PD,
1566 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1567 PGMPOOLKIND_ROOT_PDPT,
1568#endif
1569 /** Shw: Root Nested paging table. */
1570 PGMPOOLKIND_ROOT_NESTED,
1571
1572 /** The last valid entry. */
1573 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1574} PGMPOOLKIND;
1575
1576
1577/**
1578 * The tracking data for a page in the pool.
1579 */
1580typedef struct PGMPOOLPAGE
1581{
1582 /** AVL node code with the (R3) physical address of this page. */
1583 AVLOHCPHYSNODECORE Core;
1584 /** Pointer to the R3 mapping of the page. */
1585#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1586 R3PTRTYPE(void *) pvPageR3;
1587#else
1588 R3R0PTRTYPE(void *) pvPageR3;
1589#endif
1590 /** The guest physical address. */
1591#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1592 uint32_t Alignment0;
1593#endif
1594 RTGCPHYS GCPhys;
1595 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1596 uint8_t enmKind;
1597 uint8_t bPadding;
1598 /** The index of this page. */
1599 uint16_t idx;
1600 /** The next entry in the list this page currently resides in.
1601 * It's either in the free list or in the GCPhys hash. */
1602 uint16_t iNext;
1603#ifdef PGMPOOL_WITH_USER_TRACKING
1604 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1605 uint16_t iUserHead;
1606 /** The number of present entries. */
1607 uint16_t cPresent;
1608 /** The first entry in the table which is present. */
1609 uint16_t iFirstPresent;
1610#endif
1611#ifdef PGMPOOL_WITH_MONITORING
1612 /** The number of modifications to the monitored page. */
1613 uint16_t cModifications;
1614 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1615 uint16_t iModifiedNext;
1616 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1617 uint16_t iModifiedPrev;
1618 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1619 uint16_t iMonitoredNext;
1620 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1621 uint16_t iMonitoredPrev;
1622#endif
1623#ifdef PGMPOOL_WITH_CACHE
1624 /** The next page in the age list. */
1625 uint16_t iAgeNext;
1626 /** The previous page in the age list. */
1627 uint16_t iAgePrev;
1628#endif /* PGMPOOL_WITH_CACHE */
1629 /** Used to indicate that the page is zeroed. */
1630 bool fZeroed;
1631 /** Used to indicate that a PT has non-global entries. */
1632 bool fSeenNonGlobal;
1633 /** Used to indicate that we're monitoring writes to the guest page. */
1634 bool fMonitored;
1635 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1636 * (All pages are in the age list.) */
1637 bool fCached;
1638 /** This is used by the R3 access handlers when invoked by an async thread.
1639 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1640 bool volatile fReusedFlushPending;
1641#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1642 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1643 * In these cases the access handler acts differently and will check
1644 * for mapping conflicts like the normal CR3 handler.
1645 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1646 * replaced by a list of pages which share access handler.
1647 */
1648 bool fCR3Mix;
1649#endif
1650} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1651
1652
1653#ifdef PGMPOOL_WITH_CACHE
1654/** The hash table size. */
1655# define PGMPOOL_HASH_SIZE 0x40
1656/** The hash function. */
1657# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1658#endif
1659
1660
1661/**
1662 * The shadow page pool instance data.
1663 *
1664 * It's all one big allocation made at init time, except for the
1665 * pages that is. The user nodes follows immediatly after the
1666 * page structures.
1667 */
1668typedef struct PGMPOOL
1669{
1670 /** The VM handle - R3 Ptr. */
1671 PVMR3 pVMR3;
1672 /** The VM handle - R0 Ptr. */
1673 PVMR0 pVMR0;
1674 /** The VM handle - RC Ptr. */
1675 PVMRC pVMRC;
1676 /** The max pool size. This includes the special IDs. */
1677 uint16_t cMaxPages;
1678 /** The current pool size. */
1679 uint16_t cCurPages;
1680 /** The head of the free page list. */
1681 uint16_t iFreeHead;
1682 /* Padding. */
1683 uint16_t u16Padding;
1684#ifdef PGMPOOL_WITH_USER_TRACKING
1685 /** Head of the chain of free user nodes. */
1686 uint16_t iUserFreeHead;
1687 /** The number of user nodes we've allocated. */
1688 uint16_t cMaxUsers;
1689 /** The number of present page table entries in the entire pool. */
1690 uint32_t cPresent;
1691 /** Pointer to the array of user nodes - RC pointer. */
1692 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1693 /** Pointer to the array of user nodes - R3 pointer. */
1694 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1695 /** Pointer to the array of user nodes - R0 pointer. */
1696 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1697#endif /* PGMPOOL_WITH_USER_TRACKING */
1698#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1699 /** Head of the chain of free phys ext nodes. */
1700 uint16_t iPhysExtFreeHead;
1701 /** The number of user nodes we've allocated. */
1702 uint16_t cMaxPhysExts;
1703 /** Pointer to the array of physical xref extent - RC pointer. */
1704 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1705 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1706 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1707 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1708 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1709#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1710#ifdef PGMPOOL_WITH_CACHE
1711 /** Hash table for GCPhys addresses. */
1712 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1713 /** The head of the age list. */
1714 uint16_t iAgeHead;
1715 /** The tail of the age list. */
1716 uint16_t iAgeTail;
1717 /** Set if the cache is enabled. */
1718 bool fCacheEnabled;
1719#endif /* PGMPOOL_WITH_CACHE */
1720#ifdef PGMPOOL_WITH_MONITORING
1721 /** Head of the list of modified pages. */
1722 uint16_t iModifiedHead;
1723 /** The current number of modified pages. */
1724 uint16_t cModifiedPages;
1725 /** Access handler, RC. */
1726 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1727 /** Access handler, R0. */
1728 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1729 /** Access handler, R3. */
1730 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1731 /** The access handler description (HC ptr). */
1732 R3PTRTYPE(const char *) pszAccessHandler;
1733#endif /* PGMPOOL_WITH_MONITORING */
1734 /** The number of pages currently in use. */
1735 uint16_t cUsedPages;
1736#ifdef VBOX_WITH_STATISTICS
1737 /** The high wather mark for cUsedPages. */
1738 uint16_t cUsedPagesHigh;
1739 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1740 /** Profiling pgmPoolAlloc(). */
1741 STAMPROFILEADV StatAlloc;
1742 /** Profiling pgmPoolClearAll(). */
1743 STAMPROFILE StatClearAll;
1744 /** Profiling pgmPoolFlushAllInt(). */
1745 STAMPROFILE StatFlushAllInt;
1746 /** Profiling pgmPoolFlushPage(). */
1747 STAMPROFILE StatFlushPage;
1748 /** Profiling pgmPoolFree(). */
1749 STAMPROFILE StatFree;
1750 /** Profiling time spent zeroing pages. */
1751 STAMPROFILE StatZeroPage;
1752# ifdef PGMPOOL_WITH_USER_TRACKING
1753 /** Profiling of pgmPoolTrackDeref. */
1754 STAMPROFILE StatTrackDeref;
1755 /** Profiling pgmTrackFlushGCPhysPT. */
1756 STAMPROFILE StatTrackFlushGCPhysPT;
1757 /** Profiling pgmTrackFlushGCPhysPTs. */
1758 STAMPROFILE StatTrackFlushGCPhysPTs;
1759 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1760 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1761 /** Number of times we've been out of user records. */
1762 STAMCOUNTER StatTrackFreeUpOneUser;
1763# endif
1764# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1765 /** Profiling deref activity related tracking GC physical pages. */
1766 STAMPROFILE StatTrackDerefGCPhys;
1767 /** Number of linear searches for a HCPhys in the ram ranges. */
1768 STAMCOUNTER StatTrackLinearRamSearches;
1769 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1770 STAMCOUNTER StamTrackPhysExtAllocFailures;
1771# endif
1772# ifdef PGMPOOL_WITH_MONITORING
1773 /** Profiling the RC/R0 access handler. */
1774 STAMPROFILE StatMonitorRZ;
1775 /** Times we've failed interpreting the instruction. */
1776 STAMCOUNTER StatMonitorRZEmulateInstr;
1777 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1778 STAMPROFILE StatMonitorRZFlushPage;
1779 /** Times we've detected fork(). */
1780 STAMCOUNTER StatMonitorRZFork;
1781 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1782 STAMPROFILE StatMonitorRZHandled;
1783 /** Times we've failed interpreting a patch code instruction. */
1784 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1785 /** Times we've failed interpreting a patch code instruction during flushing. */
1786 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1787 /** The number of times we've seen rep prefixes we can't handle. */
1788 STAMCOUNTER StatMonitorRZRepPrefix;
1789 /** Profiling the REP STOSD cases we've handled. */
1790 STAMPROFILE StatMonitorRZRepStosd;
1791
1792 /** Profiling the R3 access handler. */
1793 STAMPROFILE StatMonitorR3;
1794 /** Times we've failed interpreting the instruction. */
1795 STAMCOUNTER StatMonitorR3EmulateInstr;
1796 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1797 STAMPROFILE StatMonitorR3FlushPage;
1798 /** Times we've detected fork(). */
1799 STAMCOUNTER StatMonitorR3Fork;
1800 /** Profiling the R3 access we've handled (except REP STOSD). */
1801 STAMPROFILE StatMonitorR3Handled;
1802 /** The number of times we've seen rep prefixes we can't handle. */
1803 STAMCOUNTER StatMonitorR3RepPrefix;
1804 /** Profiling the REP STOSD cases we've handled. */
1805 STAMPROFILE StatMonitorR3RepStosd;
1806 /** The number of times we're called in an async thread an need to flush. */
1807 STAMCOUNTER StatMonitorR3Async;
1808 /** The high wather mark for cModifiedPages. */
1809 uint16_t cModifiedPagesHigh;
1810 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1811# endif
1812# ifdef PGMPOOL_WITH_CACHE
1813 /** The number of cache hits. */
1814 STAMCOUNTER StatCacheHits;
1815 /** The number of cache misses. */
1816 STAMCOUNTER StatCacheMisses;
1817 /** The number of times we've got a conflict of 'kind' in the cache. */
1818 STAMCOUNTER StatCacheKindMismatches;
1819 /** Number of times we've been out of pages. */
1820 STAMCOUNTER StatCacheFreeUpOne;
1821 /** The number of cacheable allocations. */
1822 STAMCOUNTER StatCacheCacheable;
1823 /** The number of uncacheable allocations. */
1824 STAMCOUNTER StatCacheUncacheable;
1825# endif
1826#elif HC_ARCH_BITS == 64
1827 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1828#endif
1829 /** The AVL tree for looking up a page by its HC physical address. */
1830 AVLOHCPHYSTREE HCPhysTree;
1831 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1832 /** Array of pages. (cMaxPages in length)
1833 * The Id is the index into thist array.
1834 */
1835 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1836} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1837
1838
1839/** @def PGMPOOL_PAGE_2_PTR
1840 * Maps a pool page pool into the current context.
1841 *
1842 * @returns VBox status code.
1843 * @param pVM The VM handle.
1844 * @param pPage The pool page.
1845 *
1846 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1847 * small page window employeed by that function. Be careful.
1848 * @remark There is no need to assert on the result.
1849 */
1850#if defined(IN_RC)
1851# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1852#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1853# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1854#elif defined(VBOX_STRICT)
1855# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1856DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1857{
1858 Assert(pPage->pvPageR3);
1859 return pPage->pvPageR3;
1860}
1861#else
1862# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1863#endif
1864
1865/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1866 * Maps a pool page pool into the current context.
1867 *
1868 * @returns VBox status code.
1869 * @param pPGM Pointer to the PGM instance data.
1870 * @param pPage The pool page.
1871 *
1872 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1873 * small page window employeed by that function. Be careful.
1874 * @remark There is no need to assert on the result.
1875 */
1876#if defined(IN_RC)
1877# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1878#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1879# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1880#else
1881# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1882#endif
1883
1884
1885
1886/**
1887 * Trees are using self relative offsets as pointers.
1888 * So, all its data, including the root pointer, must be in the heap for HC and GC
1889 * to have the same layout.
1890 */
1891typedef struct PGMTREES
1892{
1893 /** Physical access handlers (AVL range+offsetptr tree). */
1894 AVLROGCPHYSTREE PhysHandlers;
1895 /** Virtual access handlers (AVL range + GC ptr tree). */
1896 AVLROGCPTRTREE VirtHandlers;
1897 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1898 AVLROGCPHYSTREE PhysToVirtHandlers;
1899 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1900 AVLROGCPTRTREE HyperVirtHandlers;
1901} PGMTREES;
1902/** Pointer to PGM trees. */
1903typedef PGMTREES *PPGMTREES;
1904
1905
1906/** @name Paging mode macros
1907 * @{ */
1908#ifdef IN_RC
1909# define PGM_CTX(a,b) a##RC##b
1910# define PGM_CTX_STR(a,b) a "GC" b
1911# define PGM_CTX_DECL(type) VMMRCDECL(type)
1912#else
1913# ifdef IN_RING3
1914# define PGM_CTX(a,b) a##R3##b
1915# define PGM_CTX_STR(a,b) a "R3" b
1916# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1917# else
1918# define PGM_CTX(a,b) a##R0##b
1919# define PGM_CTX_STR(a,b) a "R0" b
1920# define PGM_CTX_DECL(type) VMMDECL(type)
1921# endif
1922#endif
1923
1924#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1925#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1926#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1927#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1928#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1929#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1930#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1931#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1932#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1933#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1934#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1935#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1936#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1937#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1938#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1939#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1940#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1941
1942#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1943#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1944#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1945#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1946#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1947#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1948#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1949#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1950#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1951#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1952#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1953#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1954#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1955#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1956#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1957#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1958#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1959
1960/* Shw_Gst */
1961#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1962#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1963#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1964#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1965#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1966#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1967#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1968#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1969#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1970#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1971#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1972#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1973#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1974#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1975#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1976#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1977#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1978#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1979#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1980
1981#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1982#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1983#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1984#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1985#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1986#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1987#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1988#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1989#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1990#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1991#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1992#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1993#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1994#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1995#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1996#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1997#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1998#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1999#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2000#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2001#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2002#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2003#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2004#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2005#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2006#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2007#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2008#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2009#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2010#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2011#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2012#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2013#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2014#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2015#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2016#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2017#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2018
2019#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2020#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2021/** @} */
2022
2023/**
2024 * Data for each paging mode.
2025 */
2026typedef struct PGMMODEDATA
2027{
2028 /** The guest mode type. */
2029 uint32_t uGstType;
2030 /** The shadow mode type. */
2031 uint32_t uShwType;
2032
2033 /** @name Function pointers for Shadow paging.
2034 * @{
2035 */
2036 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2037 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2038 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2039 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2040
2041 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2042 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2043
2044 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2045 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2046 /** @} */
2047
2048 /** @name Function pointers for Guest paging.
2049 * @{
2050 */
2051 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2052 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2053 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2054 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2055 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2056#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2057 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2058 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2059#endif
2060#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2061 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2062 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2063 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2064 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2065#endif
2066 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2067 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2068 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2069#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2070 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2071 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2072#endif
2073#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2074 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2075 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2076#endif
2077 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2078 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2079 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2080#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2081 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2082 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2083#endif
2084#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2085 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2086 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2087#endif
2088 /** @} */
2089
2090 /** @name Function pointers for Both Shadow and Guest paging.
2091 * @{
2092 */
2093 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2094 /* no pfnR3BthTrap0eHandler */
2095 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2096 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2097 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2098 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2099 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2100#ifdef VBOX_STRICT
2101 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2102#endif
2103 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2104 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2105
2106 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2107 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2108 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2109 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2110 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2111 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2112#ifdef VBOX_STRICT
2113 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2114#endif
2115 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2116 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2117
2118 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2119 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2120 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2121 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2122 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2123 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2124#ifdef VBOX_STRICT
2125 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2126#endif
2127 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2128 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2129 /** @} */
2130} PGMMODEDATA, *PPGMMODEDATA;
2131
2132
2133
2134/**
2135 * Converts a PGM pointer into a VM pointer.
2136 * @returns Pointer to the VM structure the PGM is part of.
2137 * @param pPGM Pointer to PGM instance data.
2138 */
2139#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2140
2141/**
2142 * PGM Data (part of VM)
2143 */
2144typedef struct PGM
2145{
2146 /** Offset to the VM structure. */
2147 RTINT offVM;
2148 /** Offset of the PGMCPU structure relative to VMCPU. */
2149 int32_t offVCpu;
2150 /** Alignment padding. */
2151 int32_t i32Alignment;
2152
2153 /*
2154 * This will be redefined at least two more times before we're done, I'm sure.
2155 * The current code is only to get on with the coding.
2156 * - 2004-06-10: initial version, bird.
2157 * - 2004-07-02: 1st time, bird.
2158 * - 2004-10-18: 2nd time, bird.
2159 * - 2005-07-xx: 3rd time, bird.
2160 */
2161
2162 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2163 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2164 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2165 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2166
2167 /** The host paging mode. (This is what SUPLib reports.) */
2168 SUPPAGINGMODE enmHostMode;
2169 /** The shadow paging mode. */
2170 PGMMODE enmShadowMode;
2171 /** The guest paging mode. */
2172 PGMMODE enmGuestMode;
2173
2174 /** The current physical address representing in the guest CR3 register. */
2175 RTGCPHYS GCPhysCR3;
2176 /** Pointer to the 5 page CR3 content mapping.
2177 * The first page is always the CR3 (in some form) while the 4 other pages
2178 * are used of the PDs in PAE mode. */
2179 RTGCPTR GCPtrCR3Mapping;
2180#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2181 uint32_t u32Alignment;
2182#endif
2183#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2184 /** The physical address of the currently monitored guest CR3 page.
2185 * When this value is NIL_RTGCPHYS no page is being monitored. */
2186 RTGCPHYS GCPhysGstCR3Monitored;
2187#endif
2188 /** @name 32-bit Guest Paging.
2189 * @{ */
2190 /** The guest's page directory, R3 pointer. */
2191 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2192#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2193 /** The guest's page directory, R0 pointer. */
2194 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2195#endif
2196 /** The guest's page directory, static RC mapping. */
2197 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2198 /** @} */
2199
2200 /** @name PAE Guest Paging.
2201 * @{ */
2202 /** The guest's page directory pointer table, static RC mapping. */
2203 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2204 /** The guest's page directory pointer table, R3 pointer. */
2205 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2206#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2207 /** The guest's page directory pointer table, R0 pointer. */
2208 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2209#endif
2210
2211 /** The guest's page directories, R3 pointers.
2212 * These are individual pointers and don't have to be adjecent.
2213 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2214 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2215 /** The guest's page directories, R0 pointers.
2216 * Same restrictions as apGstPaePDsR3. */
2217#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2218 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2219#endif
2220 /** The guest's page directories, static GC mapping.
2221 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2222 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2223 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2224 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2225 RTGCPHYS aGCPhysGstPaePDs[4];
2226 /** The physical addresses of the monitored guest page directories (PAE). */
2227 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2228 /** @} */
2229
2230 /** @name AMD64 Guest Paging.
2231 * @{ */
2232 /** The guest's page directory pointer table, R3 pointer. */
2233 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2234#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2235 /** The guest's page directory pointer table, R0 pointer. */
2236 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2237#endif
2238 /** @} */
2239
2240 /** @name Shadow paging
2241 * @{ */
2242 /** The root page table - R3 Ptr. */
2243 R3PTRTYPE(void *) pShwRootR3;
2244# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2245 /** The root page table - R0 Ptr. */
2246 R0PTRTYPE(void *) pShwRootR0;
2247# endif
2248 /** The root page table - RC Ptr. */
2249 RCPTRTYPE(void *) pShwRootRC;
2250# if HC_ARCH_BITS == 64
2251 uint32_t u32Padding1; /**< alignment padding. */
2252# endif
2253 /** The Physical Address (HC) of the current active shadow CR3. */
2254 RTHCPHYS HCPhysShwCR3;
2255 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2256 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2257 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2258 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2259 /** Pointer to the page of the current active CR3 - RC Ptr. */
2260 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2261 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2262 uint32_t iShwUser;
2263 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2264 uint32_t iShwUserTable;
2265# if HC_ARCH_BITS == 64
2266 RTRCPTR alignment6; /**< structure size alignment. */
2267# endif
2268 /** @} */
2269#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2270 /** @name 32-bit Shadow Paging
2271 * @{ */
2272 /** The 32-Bit PD - R3 Ptr. */
2273 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2274 /** The 32-Bit PD - R0 Ptr. */
2275 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2276 /** The 32-Bit PD - RC Ptr. */
2277 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2278# if HC_ARCH_BITS == 64
2279 uint32_t u32Padding10; /**< alignment padding. */
2280# endif
2281 /** The Physical Address (HC) of the 32-Bit PD. */
2282 RTHCPHYS HCPhysShw32BitPD;
2283 /** @} */
2284
2285 /** @name PAE Shadow Paging
2286 * @{ */
2287 /** The four PDs for the low 4GB - R3 Ptr.
2288 * Even though these are 4 pointers, what they point at is a single table.
2289 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2290 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2291# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2292 /** The four PDs for the low 4GB - R0 Ptr.
2293 * Same kind of mapping as apHCPaePDs. */
2294 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2295# endif
2296 /** The four PDs for the low 4GB - RC Ptr.
2297 * Same kind of mapping as apHCPaePDs. */
2298 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2299 /** The Physical Address (HC) of the four PDs for the low 4GB.
2300 * These are *NOT* 4 contiguous pages. */
2301 RTHCPHYS aHCPhysPaePDs[4];
2302 /** The Physical Address (HC) of the PAE PDPT. */
2303 RTHCPHYS HCPhysShwPaePdpt;
2304 /** The PAE PDPT - R3 Ptr. */
2305 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2306 /** The PAE PDPT - R0 Ptr. */
2307 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2308 /** The PAE PDPT - RC Ptr. */
2309 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2310 /** @} */
2311# if HC_ARCH_BITS == 64
2312 RTRCPTR alignment5; /**< structure size alignment. */
2313# endif
2314#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2315 /** @name Nested Shadow Paging
2316 * @{ */
2317 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2318 RTR3PTR pShwNestedRootR3;
2319# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2320 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2321 RTR0PTR pShwNestedRootR0;
2322# endif
2323 /** The Physical Address (HC) of the nested paging root. */
2324 RTHCPHYS HCPhysShwNestedRoot;
2325 /** @} */
2326
2327 /** @name Function pointers for Shadow paging.
2328 * @{
2329 */
2330 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2331 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2332 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2333 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2334
2335 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2336 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2337
2338 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2339 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2340
2341 /** @} */
2342
2343 /** @name Function pointers for Guest paging.
2344 * @{
2345 */
2346 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2347 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2348 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2349 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2350 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2351#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2352 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2353 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2354#endif
2355#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2356 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2357 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2358 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2359 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2360#endif
2361 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2362 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2363 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2364#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2365 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2366 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2367#endif
2368#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2369 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2370 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2371#endif
2372#if HC_ARCH_BITS == 64
2373 RTRCPTR alignment3; /**< structure size alignment. */
2374#endif
2375
2376 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2377 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2378 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2379#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2380 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2381 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2382#endif
2383#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2384 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2385 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2386#endif
2387 /** @} */
2388
2389 /** @name Function pointers for Both Shadow and Guest paging.
2390 * @{
2391 */
2392 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2393 /* no pfnR3BthTrap0eHandler */
2394 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2395 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2396 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2397 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2398 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2399 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2400 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2401 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2402
2403 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2404 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2405 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2406 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2407 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2408 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2409 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2410 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2411 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2412
2413 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2414 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2415 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2416 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2417 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2418 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2419 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2420 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2421 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2422#if HC_ARCH_BITS == 64
2423 RTRCPTR alignment2; /**< structure size alignment. */
2424#endif
2425 /** @} */
2426
2427 /** Pointer to SHW+GST mode data (function pointers).
2428 * The index into this table is made up from */
2429 R3PTRTYPE(PPGMMODEDATA) paModeData;
2430
2431 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2432 * This is sorted by physical address and contains no overlapping ranges. */
2433 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2434 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2435 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2436 /** RC pointer corresponding to PGM::pRamRangesR3. */
2437 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2438 /** The configured RAM size. */
2439 RTUINT cbRamSize;
2440
2441 /** Pointer to the list of ROM ranges - for R3.
2442 * This is sorted by physical address and contains no overlapping ranges. */
2443 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2444 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2445 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2446 /** RC pointer corresponding to PGM::pRomRangesR3. */
2447 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2448 /** Alignment padding. */
2449 RTRCPTR GCPtrPadding2;
2450
2451 /** Pointer to the list of MMIO2 ranges - for R3.
2452 * Registration order. */
2453 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2454
2455 /** PGM offset based trees - R3 Ptr. */
2456 R3PTRTYPE(PPGMTREES) pTreesR3;
2457 /** PGM offset based trees - R0 Ptr. */
2458 R0PTRTYPE(PPGMTREES) pTreesR0;
2459 /** PGM offset based trees - RC Ptr. */
2460 RCPTRTYPE(PPGMTREES) pTreesRC;
2461
2462 /** Linked list of GC mappings - for RC.
2463 * The list is sorted ascending on address.
2464 */
2465 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2466 /** Linked list of GC mappings - for HC.
2467 * The list is sorted ascending on address.
2468 */
2469 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2470 /** Linked list of GC mappings - for R0.
2471 * The list is sorted ascending on address.
2472 */
2473 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2474
2475 /** Indicates that PGMR3FinalizeMappings has been called and that further
2476 * PGMR3MapIntermediate calls will be rejected. */
2477 bool fFinalizedMappings;
2478 /** If set no conflict checks are required. (boolean) */
2479 bool fMappingsFixed;
2480 /** If set, then no mappings are put into the shadow page table. (boolean) */
2481 bool fDisableMappings;
2482 /** Size of fixed mapping */
2483 uint32_t cbMappingFixed;
2484 /** Base address (GC) of fixed mapping */
2485 RTGCPTR GCPtrMappingFixed;
2486#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2487 uint32_t u32Padding0; /**< alignment padding. */
2488#endif
2489
2490
2491 /** @name Intermediate Context
2492 * @{ */
2493 /** Pointer to the intermediate page directory - Normal. */
2494 R3PTRTYPE(PX86PD) pInterPD;
2495 /** Pointer to the intermedate page tables - Normal.
2496 * There are two page tables, one for the identity mapping and one for
2497 * the host context mapping (of the core code). */
2498 R3PTRTYPE(PX86PT) apInterPTs[2];
2499 /** Pointer to the intermedate page tables - PAE. */
2500 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2501 /** Pointer to the intermedate page directory - PAE. */
2502 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2503 /** Pointer to the intermedate page directory - PAE. */
2504 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2505 /** Pointer to the intermedate page-map level 4 - AMD64. */
2506 R3PTRTYPE(PX86PML4) pInterPaePML4;
2507 /** Pointer to the intermedate page directory - AMD64. */
2508 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2509 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2510 RTHCPHYS HCPhysInterPD;
2511 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2512 RTHCPHYS HCPhysInterPaePDPT;
2513 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2514 RTHCPHYS HCPhysInterPaePML4;
2515 /** @} */
2516
2517 /** Base address of the dynamic page mapping area.
2518 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2519 */
2520 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2521 /** The index of the last entry used in the dynamic page mapping area. */
2522 RTUINT iDynPageMapLast;
2523 /** Cache containing the last entries in the dynamic page mapping area.
2524 * The cache size is covering half of the mapping area. */
2525 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2526
2527 /** The address of the ring-0 mapping cache if we're making use of it. */
2528 RTR0PTR pvR0DynMapUsed;
2529#if HC_ARCH_BITS == 32
2530 RTR0PTR R0PtrPadding0; /**< Alignment. */
2531#endif
2532
2533
2534 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2535 RTGCPHYS GCPhys4MBPSEMask;
2536
2537 /** A20 gate mask.
2538 * Our current approach to A20 emulation is to let REM do it and don't bother
2539 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2540 * But whould need arrise, we'll subject physical addresses to this mask. */
2541 RTGCPHYS GCPhysA20Mask;
2542 /** A20 gate state - boolean! */
2543 RTUINT fA20Enabled;
2544
2545 /** What needs syncing (PGM_SYNC_*).
2546 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2547 * PGMFlushTLB, and PGMR3Load. */
2548 RTUINT fSyncFlags;
2549
2550 /** PGM critical section.
2551 * This protects the physical & virtual access handlers, ram ranges,
2552 * and the page flag updating (some of it anyway).
2553 */
2554 PDMCRITSECT CritSect;
2555
2556 /** Shadow Page Pool - R3 Ptr. */
2557 R3PTRTYPE(PPGMPOOL) pPoolR3;
2558 /** Shadow Page Pool - R0 Ptr. */
2559 R0PTRTYPE(PPGMPOOL) pPoolR0;
2560 /** Shadow Page Pool - RC Ptr. */
2561 RCPTRTYPE(PPGMPOOL) pPoolRC;
2562
2563 /** We're not in a state which permits writes to guest memory.
2564 * (Only used in strict builds.) */
2565 bool fNoMorePhysWrites;
2566
2567 /** Flush the cache on the next access. */
2568 bool fPhysCacheFlushPending;
2569/** @todo r=bird: Fix member names!*/
2570 /** PGMPhysRead cache */
2571 PGMPHYSCACHE pgmphysreadcache;
2572 /** PGMPhysWrite cache */
2573 PGMPHYSCACHE pgmphyswritecache;
2574
2575 /**
2576 * Data associated with managing the ring-3 mappings of the allocation chunks.
2577 */
2578 struct
2579 {
2580 /** The chunk tree, ordered by chunk id. */
2581#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2582 R3PTRTYPE(PAVLU32NODECORE) pTree;
2583#else
2584 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2585#endif
2586 /** The chunk mapping TLB. */
2587 PGMCHUNKR3MAPTLB Tlb;
2588 /** The number of mapped chunks. */
2589 uint32_t c;
2590 /** The maximum number of mapped chunks.
2591 * @cfgm PGM/MaxRing3Chunks */
2592 uint32_t cMax;
2593 /** The chunk age tree, ordered by ageing sequence number. */
2594 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2595 /** The current time. */
2596 uint32_t iNow;
2597 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2598 uint32_t AgeingCountdown;
2599 } ChunkR3Map;
2600
2601 /**
2602 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2603 */
2604 PGMPAGER3MAPTLB PhysTlbHC;
2605
2606 /** @name The zero page.
2607 * @{ */
2608 /** The host physical address of the zero page. */
2609 RTHCPHYS HCPhysZeroPg;
2610 /** The ring-3 mapping of the zero page. */
2611 RTR3PTR pvZeroPgR3;
2612 /** The ring-0 mapping of the zero page. */
2613 RTR0PTR pvZeroPgR0;
2614 /** The GC mapping of the zero page. */
2615 RTGCPTR pvZeroPgGC;
2616#if GC_ARCH_BITS != 32
2617 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2618#endif
2619 /** @}*/
2620
2621 /** The number of handy pages. */
2622 uint32_t cHandyPages;
2623 /**
2624 * Array of handy pages.
2625 *
2626 * This array is used in a two way communication between pgmPhysAllocPage
2627 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2628 * an intermediary.
2629 *
2630 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2631 * (The current size of 32 pages, means 128 KB of handy memory.)
2632 */
2633 GMMPAGEDESC aHandyPages[32];
2634
2635 /** @name Release Statistics
2636 * @{ */
2637 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2638 uint32_t cPrivatePages; /**< The number of private pages. */
2639 uint32_t cSharedPages; /**< The number of shared pages. */
2640 uint32_t cZeroPages; /**< The number of zero backed pages. */
2641 /** The number of times the guest has switched mode since last reset or statistics reset. */
2642 STAMCOUNTER cGuestModeChanges;
2643 /** The number of times we were forced to change the hypervisor region location. */
2644 STAMCOUNTER cRelocations;
2645 /** @} */
2646
2647#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2648 /** RC: Which statistic this \#PF should be attributed to. */
2649 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2650 RTRCPTR padding0;
2651 /** R0: Which statistic this \#PF should be attributed to. */
2652 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2653 RTR0PTR padding1;
2654
2655 /* Common */
2656# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2657 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2658 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2659 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2660 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2661 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2662 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2663# endif
2664 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2665 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2666
2667 /* R3 only: */
2668 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2669 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2670 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2671 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2672 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2673 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2674
2675 /* R0 only: */
2676 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2677 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2678 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2679 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2680 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2681 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2682 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2683 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2684 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2685 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2686 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2687 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2688 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2689 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2690 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2691 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2692 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2693 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2694 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2695 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2696 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2697 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2698 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2699 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2700 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2701 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2702
2703 /* RC only: */
2704 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2705 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2706 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2707 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2708
2709 /* RZ only: */
2710 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2711 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2712 STAMPROFILE StatRZTrap0eTimeSyncPT;
2713 STAMPROFILE StatRZTrap0eTimeMapping;
2714 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2715 STAMPROFILE StatRZTrap0eTimeHandlers;
2716 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2717 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2718 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2719 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2720 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2721 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2722 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2723 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2724 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2725 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2726 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2727 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2728 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2729 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2730 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2731 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2732 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2733 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2734 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2735 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2736 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2737 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2738 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2739 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2740 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2741 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2742 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2743 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2744 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2745 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2746 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2747 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2748 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2749 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2750 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2751 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2752 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2753 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2754 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2755 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2756 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2757 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2758 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2759
2760 /* HC - R3 and (maybe) R0: */
2761
2762 /* RZ & R3: */
2763 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2764 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2765 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2766 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2767 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2768 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2769 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2770 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2771 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2772 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2773 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2774 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2775 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2776 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2777 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2778 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2779 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2780 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2781 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2782 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2783 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2784 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2785 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2786 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2787 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2788 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2789 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2790 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2791 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2792 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2793 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2794 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2795 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2796 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2797 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2798 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2799 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2800 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2801 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2802 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2803 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2804 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2805 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2806 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2807 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2808 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2809 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2810/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2811 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2812 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2813 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2814 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2815 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2816 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2817
2818 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2819 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2820 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2821 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2822 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2823 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2824 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2825 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2826 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2827 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2828 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2829 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2830 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2831 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2832 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2833 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2834 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2835 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2836 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2837 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2838 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2839 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2840 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2841 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2842 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2843 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2844 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2845 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2846 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2847 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2848 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2849 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2850 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2851 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2852 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2853 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2854 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2855 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2856 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2857 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2858 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2859 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2860 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2861 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2862 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2863 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2864 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2865/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2866 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2867 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2868 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2869 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2870 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2871 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2872#endif /* VBOX_WITH_STATISTICS */
2873} PGM;
2874/** Pointer to the PGM instance data. */
2875typedef PGM *PPGM;
2876
2877
2878/**
2879 * PGMCPU Data (part of VMCPU).
2880 */
2881typedef struct PGMCPU
2882{
2883 /** Offset to the VMCPU structure. */
2884 RTINT offVMCPU;
2885 /** Automatically tracked physical memory mapping set.
2886 * Ring-0 and strict raw-mode builds. */
2887 PGMMAPSET AutoSet;
2888} PGMCPU;
2889/** Pointer to the per-cpu PGM data. */
2890typedef PGMCPU *PPGMCPU;
2891
2892
2893/** @name PGM::fSyncFlags Flags
2894 * @{
2895 */
2896/** Updates the virtual access handler state bit in PGMPAGE. */
2897#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2898/** Always sync CR3. */
2899#define PGM_SYNC_ALWAYS RT_BIT(1)
2900/** Check monitoring on next CR3 (re)load and invalidate page. */
2901#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2902/** Check guest mapping in SyncCR3. */
2903#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2904/** Clear the page pool (a light weight flush). */
2905#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2906/** @} */
2907
2908
2909__BEGIN_DECLS
2910
2911int pgmLock(PVM pVM);
2912void pgmUnlock(PVM pVM);
2913
2914VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2915VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2916
2917int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2918int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2919PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2920void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2921DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2922
2923void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2924bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2925int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2926DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2927#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2928void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2929#else
2930# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2931#endif
2932DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2933
2934
2935void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2936int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2937int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2938int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2939#ifdef IN_RING3
2940int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2941int pgmR3PhysRamReset(PVM pVM);
2942int pgmR3PhysRomReset(PVM pVM);
2943# ifndef VBOX_WITH_NEW_PHYS_CODE
2944int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2945# endif
2946
2947int pgmR3PoolInit(PVM pVM);
2948void pgmR3PoolRelocate(PVM pVM);
2949void pgmR3PoolReset(PVM pVM);
2950
2951#endif /* IN_RING3 */
2952#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2953int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2954#endif
2955#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2956void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2957#endif
2958int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2959PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2960void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2961void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2962int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2963void pgmPoolFlushAll(PVM pVM);
2964void pgmPoolClearAll(PVM pVM);
2965int pgmPoolSyncCR3(PVM pVM);
2966void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2967void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2968int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2969PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2970void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2971void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2972uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2973void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2974#ifdef PGMPOOL_WITH_MONITORING
2975void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2976int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2977void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2978void pgmPoolMonitorModifiedClearAll(PVM pVM);
2979int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2980int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2981#endif
2982
2983#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2984bool pgmPoolIsActiveRootPage(PVM pVM, PPGMPOOLPAGE pPage);
2985
2986void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
2987void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2988int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2989int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2990#endif
2991#ifndef IN_RC
2992int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2993#endif
2994int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
2995
2996__END_DECLS
2997
2998
2999/**
3000 * Gets the PGMRAMRANGE structure for a guest page.
3001 *
3002 * @returns Pointer to the RAM range on success.
3003 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3004 *
3005 * @param pPGM PGM handle.
3006 * @param GCPhys The GC physical address.
3007 */
3008DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3009{
3010 /*
3011 * Optimize for the first range.
3012 */
3013 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3014 RTGCPHYS off = GCPhys - pRam->GCPhys;
3015 if (RT_UNLIKELY(off >= pRam->cb))
3016 {
3017 do
3018 {
3019 pRam = pRam->CTX_SUFF(pNext);
3020 if (RT_UNLIKELY(!pRam))
3021 break;
3022 off = GCPhys - pRam->GCPhys;
3023 } while (off >= pRam->cb);
3024 }
3025 return pRam;
3026}
3027
3028
3029/**
3030 * Gets the PGMPAGE structure for a guest page.
3031 *
3032 * @returns Pointer to the page on success.
3033 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3034 *
3035 * @param pPGM PGM handle.
3036 * @param GCPhys The GC physical address.
3037 */
3038DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3039{
3040 /*
3041 * Optimize for the first range.
3042 */
3043 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3044 RTGCPHYS off = GCPhys - pRam->GCPhys;
3045 if (RT_UNLIKELY(off >= pRam->cb))
3046 {
3047 do
3048 {
3049 pRam = pRam->CTX_SUFF(pNext);
3050 if (RT_UNLIKELY(!pRam))
3051 return NULL;
3052 off = GCPhys - pRam->GCPhys;
3053 } while (off >= pRam->cb);
3054 }
3055 return &pRam->aPages[off >> PAGE_SHIFT];
3056}
3057
3058
3059/**
3060 * Gets the PGMPAGE structure for a guest page.
3061 *
3062 * Old Phys code: Will make sure the page is present.
3063 *
3064 * @returns VBox status code.
3065 * @retval VINF_SUCCESS and a valid *ppPage on success.
3066 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3067 *
3068 * @param pPGM PGM handle.
3069 * @param GCPhys The GC physical address.
3070 * @param ppPage Where to store the page poitner on success.
3071 */
3072DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3073{
3074 /*
3075 * Optimize for the first range.
3076 */
3077 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3078 RTGCPHYS off = GCPhys - pRam->GCPhys;
3079 if (RT_UNLIKELY(off >= pRam->cb))
3080 {
3081 do
3082 {
3083 pRam = pRam->CTX_SUFF(pNext);
3084 if (RT_UNLIKELY(!pRam))
3085 {
3086 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3087 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3088 }
3089 off = GCPhys - pRam->GCPhys;
3090 } while (off >= pRam->cb);
3091 }
3092 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3093#ifndef VBOX_WITH_NEW_PHYS_CODE
3094
3095 /*
3096 * Make sure it's present.
3097 */
3098 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3099 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3100 {
3101#ifdef IN_RING3
3102 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3103#else
3104 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3105#endif
3106 if (RT_FAILURE(rc))
3107 {
3108 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3109 return rc;
3110 }
3111 Assert(rc == VINF_SUCCESS);
3112 }
3113#endif
3114 return VINF_SUCCESS;
3115}
3116
3117
3118
3119
3120/**
3121 * Gets the PGMPAGE structure for a guest page.
3122 *
3123 * Old Phys code: Will make sure the page is present.
3124 *
3125 * @returns VBox status code.
3126 * @retval VINF_SUCCESS and a valid *ppPage on success.
3127 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3128 *
3129 * @param pPGM PGM handle.
3130 * @param GCPhys The GC physical address.
3131 * @param ppPage Where to store the page poitner on success.
3132 * @param ppRamHint Where to read and store the ram list hint.
3133 * The caller initializes this to NULL before the call.
3134 */
3135DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3136{
3137 RTGCPHYS off;
3138 PPGMRAMRANGE pRam = *ppRamHint;
3139 if ( !pRam
3140 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3141 {
3142 pRam = pPGM->CTX_SUFF(pRamRanges);
3143 off = GCPhys - pRam->GCPhys;
3144 if (RT_UNLIKELY(off >= pRam->cb))
3145 {
3146 do
3147 {
3148 pRam = pRam->CTX_SUFF(pNext);
3149 if (RT_UNLIKELY(!pRam))
3150 {
3151 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3152 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3153 }
3154 off = GCPhys - pRam->GCPhys;
3155 } while (off >= pRam->cb);
3156 }
3157 *ppRamHint = pRam;
3158 }
3159 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3160#ifndef VBOX_WITH_NEW_PHYS_CODE
3161
3162 /*
3163 * Make sure it's present.
3164 */
3165 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3166 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3167 {
3168#ifdef IN_RING3
3169 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3170#else
3171 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3172#endif
3173 if (RT_FAILURE(rc))
3174 {
3175 *ppPage = NULL; /* Shut up annoying smart ass. */
3176 return rc;
3177 }
3178 Assert(rc == VINF_SUCCESS);
3179 }
3180#endif
3181 return VINF_SUCCESS;
3182}
3183
3184
3185/**
3186 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3187 *
3188 * @returns Pointer to the page on success.
3189 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3190 *
3191 * @param pPGM PGM handle.
3192 * @param GCPhys The GC physical address.
3193 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3194 */
3195DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3196{
3197 /*
3198 * Optimize for the first range.
3199 */
3200 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3201 RTGCPHYS off = GCPhys - pRam->GCPhys;
3202 if (RT_UNLIKELY(off >= pRam->cb))
3203 {
3204 do
3205 {
3206 pRam = pRam->CTX_SUFF(pNext);
3207 if (RT_UNLIKELY(!pRam))
3208 return NULL;
3209 off = GCPhys - pRam->GCPhys;
3210 } while (off >= pRam->cb);
3211 }
3212 *ppRam = pRam;
3213 return &pRam->aPages[off >> PAGE_SHIFT];
3214}
3215
3216
3217/**
3218 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3219 *
3220 * @returns Pointer to the page on success.
3221 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3222 *
3223 * @param pPGM PGM handle.
3224 * @param GCPhys The GC physical address.
3225 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3226 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3227 */
3228DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3229{
3230 /*
3231 * Optimize for the first range.
3232 */
3233 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3234 RTGCPHYS off = GCPhys - pRam->GCPhys;
3235 if (RT_UNLIKELY(off >= pRam->cb))
3236 {
3237 do
3238 {
3239 pRam = pRam->CTX_SUFF(pNext);
3240 if (RT_UNLIKELY(!pRam))
3241 {
3242 *ppRam = NULL; /* Shut up silly GCC warnings. */
3243 *ppPage = NULL; /* ditto */
3244 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3245 }
3246 off = GCPhys - pRam->GCPhys;
3247 } while (off >= pRam->cb);
3248 }
3249 *ppRam = pRam;
3250 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3251#ifndef VBOX_WITH_NEW_PHYS_CODE
3252
3253 /*
3254 * Make sure it's present.
3255 */
3256 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3257 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3258 {
3259#ifdef IN_RING3
3260 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3261#else
3262 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3263#endif
3264 if (RT_FAILURE(rc))
3265 {
3266 *ppPage = NULL; /* Shut up silly GCC warnings. */
3267 *ppPage = NULL; /* ditto */
3268 return rc;
3269 }
3270 Assert(rc == VINF_SUCCESS);
3271
3272 }
3273#endif
3274 return VINF_SUCCESS;
3275}
3276
3277
3278/**
3279 * Convert GC Phys to HC Phys.
3280 *
3281 * @returns VBox status.
3282 * @param pPGM PGM handle.
3283 * @param GCPhys The GC physical address.
3284 * @param pHCPhys Where to store the corresponding HC physical address.
3285 *
3286 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3287 * Avoid when writing new code!
3288 */
3289DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3290{
3291 PPGMPAGE pPage;
3292 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3293 if (RT_FAILURE(rc))
3294 return rc;
3295 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3296 return VINF_SUCCESS;
3297}
3298
3299#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3300
3301/**
3302 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3303 * optimizes access to pages already in the set.
3304 *
3305 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3306 * @param pPGM Pointer to the PVM instance data.
3307 * @param HCPhys The physical address of the page.
3308 * @param ppv Where to store the mapping address.
3309 */
3310DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3311{
3312 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3313 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3314 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3315 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3316
3317 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3318 unsigned iEntry = pSet->aiHashTable[iHash];
3319 if ( iEntry < pSet->cEntries
3320 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3321 {
3322 *ppv = pSet->aEntries[iEntry].pvPage;
3323 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3324 }
3325 else
3326 {
3327 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3328 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3329 }
3330
3331 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3332 return VINF_SUCCESS;
3333}
3334
3335
3336/**
3337 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3338 * access to pages already in the set.
3339 *
3340 * @returns See PGMDynMapGCPage.
3341 * @param pPGM Pointer to the PVM instance data.
3342 * @param HCPhys The physical address of the page.
3343 * @param ppv Where to store the mapping address.
3344 */
3345DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3346{
3347 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3348 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3349
3350 /*
3351 * Get the ram range.
3352 */
3353 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3354 RTGCPHYS off = GCPhys - pRam->GCPhys;
3355 if (RT_UNLIKELY(off >= pRam->cb
3356 /** @todo || page state stuff */))
3357 {
3358 /* This case is not counted into StatR0DynMapGCPageInl. */
3359 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3360 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3361 }
3362
3363 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3364 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3365
3366 /*
3367 * pgmR0DynMapHCPageInlined with out stats.
3368 */
3369 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3370 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3371 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3372
3373 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3374 unsigned iEntry = pSet->aiHashTable[iHash];
3375 if ( iEntry < pSet->cEntries
3376 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3377 {
3378 *ppv = pSet->aEntries[iEntry].pvPage;
3379 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3380 }
3381 else
3382 {
3383 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3384 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3385 }
3386
3387 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3388 return VINF_SUCCESS;
3389}
3390
3391#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3392
3393#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3394/**
3395 * Maps the page into current context (RC and maybe R0).
3396 *
3397 * @returns pointer to the mapping.
3398 * @param pVM Pointer to the PGM instance data.
3399 * @param pPage The page.
3400 */
3401DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3402{
3403 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3404 {
3405 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3406 void *pv;
3407# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3408 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3409# else
3410 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3411# endif
3412 return pv;
3413 }
3414 return pgmPoolMapPageFallback(pPGM, pPage);
3415}
3416
3417/**
3418 * Temporarily maps one host page specified by HC physical address, returning
3419 * pointer within the page.
3420 *
3421 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3422 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3423 *
3424 * @returns The address corresponding to HCPhys.
3425 * @param pPGM Pointer to the PVM instance data.
3426 * @param HCPhys HC Physical address of the page.
3427 */
3428DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3429{
3430 void *pv;
3431# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3432 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3433# else
3434 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3435# endif
3436 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3437 return pv;
3438}
3439#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3440
3441
3442#ifndef IN_RC
3443/**
3444 * Queries the Physical TLB entry for a physical guest page,
3445 * attemting to load the TLB entry if necessary.
3446 *
3447 * @returns VBox status code.
3448 * @retval VINF_SUCCESS on success
3449 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3450 * @param pPGM The PGM instance handle.
3451 * @param GCPhys The address of the guest page.
3452 * @param ppTlbe Where to store the pointer to the TLB entry.
3453 */
3454
3455DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3456{
3457 int rc;
3458 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3459 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3460 {
3461 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3462 rc = VINF_SUCCESS;
3463 }
3464 else
3465 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3466 *ppTlbe = pTlbe;
3467 return rc;
3468}
3469#endif /* !IN_RC */
3470
3471#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3472
3473# ifndef VBOX_WITH_NEW_PHYS_CODE
3474/**
3475 * Convert GC Phys to HC Virt.
3476 *
3477 * @returns VBox status.
3478 * @param pPGM PGM handle.
3479 * @param GCPhys The GC physical address.
3480 * @param pHCPtr Where to store the corresponding HC virtual address.
3481 *
3482 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3483 * pgmPoolMonitorGCPtr2CCPtr.
3484 */
3485DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3486{
3487 PPGMRAMRANGE pRam;
3488 PPGMPAGE pPage;
3489 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3490 if (RT_FAILURE(rc))
3491 {
3492 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3493 return rc;
3494 }
3495 RTGCPHYS off = GCPhys - pRam->GCPhys;
3496
3497 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3498 {
3499 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3500 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3501 return VINF_SUCCESS;
3502 }
3503 if (pRam->pvR3)
3504 {
3505 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3506 return VINF_SUCCESS;
3507 }
3508 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3509 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3510}
3511# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3512#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3513
3514/**
3515 * Convert GC Phys to HC Virt and HC Phys.
3516 *
3517 * @returns VBox status.
3518 * @param pPGM PGM handle.
3519 * @param GCPhys The GC physical address.
3520 * @param pHCPtr Where to store the corresponding HC virtual address.
3521 * @param pHCPhys Where to store the HC Physical address and its flags.
3522 *
3523 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3524 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3525 */
3526DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3527{
3528 PPGMRAMRANGE pRam;
3529 PPGMPAGE pPage;
3530 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3531 if (RT_FAILURE(rc))
3532 {
3533 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3534 *pHCPhys = 0; /* ditto */
3535 return rc;
3536 }
3537 RTGCPHYS off = GCPhys - pRam->GCPhys;
3538
3539 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3540 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3541 {
3542 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3543#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3544 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3545 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3546#else
3547 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3548#endif
3549 return VINF_SUCCESS;
3550 }
3551 if (pRam->pvR3)
3552 {
3553 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3554 return VINF_SUCCESS;
3555 }
3556 *pHCPtr = 0;
3557 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3558}
3559
3560
3561/**
3562 * Clears flags associated with a RAM address.
3563 *
3564 * @returns VBox status code.
3565 * @param pPGM PGM handle.
3566 * @param GCPhys Guest context physical address.
3567 * @param fFlags fFlags to clear. (Bits 0-11.)
3568 */
3569DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3570{
3571 PPGMPAGE pPage;
3572 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3573 if (RT_FAILURE(rc))
3574 return rc;
3575
3576 fFlags &= ~X86_PTE_PAE_PG_MASK;
3577 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3578 return VINF_SUCCESS;
3579}
3580
3581
3582/**
3583 * Clears flags associated with a RAM address.
3584 *
3585 * @returns VBox status code.
3586 * @param pPGM PGM handle.
3587 * @param GCPhys Guest context physical address.
3588 * @param fFlags fFlags to clear. (Bits 0-11.)
3589 * @param ppRamHint Where to read and store the ram list hint.
3590 * The caller initializes this to NULL before the call.
3591 */
3592DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3593{
3594 PPGMPAGE pPage;
3595 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3596 if (RT_FAILURE(rc))
3597 return rc;
3598
3599 fFlags &= ~X86_PTE_PAE_PG_MASK;
3600 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3601 return VINF_SUCCESS;
3602}
3603
3604
3605/**
3606 * Sets (bitwise OR) flags associated with a RAM address.
3607 *
3608 * @returns VBox status code.
3609 * @param pPGM PGM handle.
3610 * @param GCPhys Guest context physical address.
3611 * @param fFlags fFlags to set clear. (Bits 0-11.)
3612 */
3613DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3614{
3615 PPGMPAGE pPage;
3616 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3617 if (RT_FAILURE(rc))
3618 return rc;
3619
3620 fFlags &= ~X86_PTE_PAE_PG_MASK;
3621 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3622 return VINF_SUCCESS;
3623}
3624
3625
3626/**
3627 * Sets (bitwise OR) flags associated with a RAM address.
3628 *
3629 * @returns VBox status code.
3630 * @param pPGM PGM handle.
3631 * @param GCPhys Guest context physical address.
3632 * @param fFlags fFlags to set clear. (Bits 0-11.)
3633 * @param ppRamHint Where to read and store the ram list hint.
3634 * The caller initializes this to NULL before the call.
3635 */
3636DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3637{
3638 PPGMPAGE pPage;
3639 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3640 if (RT_FAILURE(rc))
3641 return rc;
3642
3643 fFlags &= ~X86_PTE_PAE_PG_MASK;
3644 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3645 return VINF_SUCCESS;
3646}
3647
3648
3649/**
3650 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3651 * Takes PSE-36 into account.
3652 *
3653 * @returns guest physical address
3654 * @param pPGM Pointer to the PGM instance data.
3655 * @param Pde Guest Pde
3656 */
3657DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3658{
3659 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3660 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3661
3662 return GCPhys & pPGM->GCPhys4MBPSEMask;
3663}
3664
3665
3666/**
3667 * Gets the page directory entry for the specified address (32-bit paging).
3668 *
3669 * @returns The page directory entry in question.
3670 * @param pPGM Pointer to the PGM instance data.
3671 * @param GCPtr The address.
3672 */
3673DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3674{
3675#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3676 PCX86PD pGuestPD = 0;
3677 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3678 if (RT_FAILURE(rc))
3679 {
3680 X86PDE ZeroPde = {0};
3681 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3682 }
3683 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3684#else
3685 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3686#endif
3687}
3688
3689
3690/**
3691 * Gets the address of a specific page directory entry (32-bit paging).
3692 *
3693 * @returns Pointer the page directory entry in question.
3694 * @param pPGM Pointer to the PGM instance data.
3695 * @param GCPtr The address.
3696 */
3697DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3698{
3699#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3700 PX86PD pGuestPD = 0;
3701 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3702 AssertRCReturn(rc, 0);
3703 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3704#else
3705 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3706#endif
3707}
3708
3709
3710/**
3711 * Gets the address the guest page directory (32-bit paging).
3712 *
3713 * @returns Pointer the page directory entry in question.
3714 * @param pPGM Pointer to the PGM instance data.
3715 */
3716DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3717{
3718#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3719 PX86PD pGuestPD = 0;
3720 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3721 AssertRCReturn(rc, 0);
3722 return pGuestPD;
3723#else
3724 return pPGM->CTX_SUFF(pGst32BitPd);
3725#endif
3726}
3727
3728
3729/**
3730 * Gets the guest page directory pointer table.
3731 *
3732 * @returns Pointer to the page directory in question.
3733 * @returns NULL if the page directory is not present or on an invalid page.
3734 * @param pPGM Pointer to the PGM instance data.
3735 */
3736DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3737{
3738#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3739 PX86PDPT pGuestPDPT = 0;
3740 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3741 AssertRCReturn(rc, 0);
3742 return pGuestPDPT;
3743#else
3744 return pPGM->CTX_SUFF(pGstPaePdpt);
3745#endif
3746}
3747
3748
3749/**
3750 * Gets the guest page directory pointer table entry for the specified address.
3751 *
3752 * @returns Pointer to the page directory in question.
3753 * @returns NULL if the page directory is not present or on an invalid page.
3754 * @param pPGM Pointer to the PGM instance data.
3755 * @param GCPtr The address.
3756 */
3757DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3758{
3759 AssertGCPtr32(GCPtr);
3760
3761#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3762 PX86PDPT pGuestPDPT = 0;
3763 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3764 AssertRCReturn(rc, 0);
3765 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3766#else
3767 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3768#endif
3769}
3770
3771
3772/**
3773 * Gets the page directory for the specified address.
3774 *
3775 * @returns Pointer to the page directory in question.
3776 * @returns NULL if the page directory is not present or on an invalid page.
3777 * @param pPGM Pointer to the PGM instance data.
3778 * @param GCPtr The address.
3779 */
3780DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3781{
3782 AssertGCPtr32(GCPtr);
3783
3784#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3785 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3786 AssertReturn(pGuestPDPT, 0);
3787#else
3788 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3789#endif
3790 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3791 if (pGuestPDPT->a[iPdPt].n.u1Present)
3792 {
3793#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3794 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3795 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3796#endif
3797
3798 /* cache is out-of-sync. */
3799 PX86PDPAE pPD;
3800 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3801 if (RT_SUCCESS(rc))
3802 return pPD;
3803 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3804 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3805 }
3806 return NULL;
3807}
3808
3809
3810/**
3811 * Gets the page directory entry for the specified address.
3812 *
3813 * @returns Pointer to the page directory entry in question.
3814 * @returns NULL if the page directory is not present or on an invalid page.
3815 * @param pPGM Pointer to the PGM instance data.
3816 * @param GCPtr The address.
3817 */
3818DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3819{
3820 AssertGCPtr32(GCPtr);
3821
3822#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3823 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3824 AssertReturn(pGuestPDPT, 0);
3825#else
3826 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3827#endif
3828 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3829 if (pGuestPDPT->a[iPdPt].n.u1Present)
3830 {
3831 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3832#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3833 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3834 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3835#endif
3836
3837 /* The cache is out-of-sync. */
3838 PX86PDPAE pPD;
3839 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3840 if (RT_SUCCESS(rc))
3841 return &pPD->a[iPD];
3842 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3843 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3844 }
3845 return NULL;
3846}
3847
3848
3849/**
3850 * Gets the page directory entry for the specified address.
3851 *
3852 * @returns The page directory entry in question.
3853 * @returns A non-present entry if the page directory is not present or on an invalid page.
3854 * @param pPGM Pointer to the PGM instance data.
3855 * @param GCPtr The address.
3856 */
3857DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3858{
3859 AssertGCPtr32(GCPtr);
3860
3861#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3862 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3863 if (RT_LIKELY(pGuestPDPT))
3864#else
3865 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3866#endif
3867 {
3868 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3869 if (pGuestPDPT->a[iPdPt].n.u1Present)
3870 {
3871 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3872#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3873 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3874 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3875#endif
3876
3877 /* cache is out-of-sync. */
3878 PX86PDPAE pPD;
3879 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3880 if (RT_SUCCESS(rc))
3881 return pPD->a[iPD];
3882 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3883 }
3884 }
3885 X86PDEPAE ZeroPde = {0};
3886 return ZeroPde;
3887}
3888
3889
3890/**
3891 * Gets the page directory pointer table entry for the specified address
3892 * and returns the index into the page directory
3893 *
3894 * @returns Pointer to the page directory in question.
3895 * @returns NULL if the page directory is not present or on an invalid page.
3896 * @param pPGM Pointer to the PGM instance data.
3897 * @param GCPtr The address.
3898 * @param piPD Receives the index into the returned page directory
3899 * @param pPdpe Receives the page directory pointer entry. Optional.
3900 */
3901DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3902{
3903 AssertGCPtr32(GCPtr);
3904
3905#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3906 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3907 AssertReturn(pGuestPDPT, 0);
3908#else
3909 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3910#endif
3911 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3912 if (pPdpe)
3913 *pPdpe = pGuestPDPT->a[iPdPt];
3914 if (pGuestPDPT->a[iPdPt].n.u1Present)
3915 {
3916 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3917#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3918 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3919 {
3920 *piPD = iPD;
3921 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3922 }
3923#endif
3924
3925 /* cache is out-of-sync. */
3926 PX86PDPAE pPD;
3927 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3928 if (RT_SUCCESS(rc))
3929 {
3930 *piPD = iPD;
3931 return pPD;
3932 }
3933 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3934 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3935 }
3936 return NULL;
3937}
3938
3939#ifndef IN_RC
3940
3941/**
3942 * Gets the page map level-4 pointer for the guest.
3943 *
3944 * @returns Pointer to the PML4 page.
3945 * @param pPGM Pointer to the PGM instance data.
3946 */
3947DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3948{
3949#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3950 PX86PML4 pGuestPml4;
3951 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3952 AssertRCReturn(rc, NULL);
3953 return pGuestPml4;
3954#else
3955 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3956 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3957#endif
3958}
3959
3960
3961/**
3962 * Gets the pointer to a page map level-4 entry.
3963 *
3964 * @returns Pointer to the PML4 entry.
3965 * @param pPGM Pointer to the PGM instance data.
3966 * @param iPml4 The index.
3967 */
3968DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3969{
3970#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3971 PX86PML4 pGuestPml4;
3972 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3973 AssertRCReturn(rc, NULL);
3974 return &pGuestPml4->a[iPml4];
3975#else
3976 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3977 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3978#endif
3979}
3980
3981
3982/**
3983 * Gets a page map level-4 entry.
3984 *
3985 * @returns The PML4 entry.
3986 * @param pPGM Pointer to the PGM instance data.
3987 * @param iPml4 The index.
3988 */
3989DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3990{
3991#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3992 PX86PML4 pGuestPml4;
3993 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3994 if (RT_FAILURE(rc))
3995 {
3996 X86PML4E ZeroPml4e = {0};
3997 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3998 }
3999 return pGuestPml4->a[iPml4];
4000#else
4001 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4002 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4003#endif
4004}
4005
4006
4007/**
4008 * Gets the page directory pointer entry for the specified address.
4009 *
4010 * @returns Pointer to the page directory pointer entry in question.
4011 * @returns NULL if the page directory is not present or on an invalid page.
4012 * @param pPGM Pointer to the PGM instance data.
4013 * @param GCPtr The address.
4014 * @param ppPml4e Page Map Level-4 Entry (out)
4015 */
4016DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4017{
4018 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4019 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4020 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4021 if (pPml4e->n.u1Present)
4022 {
4023 PX86PDPT pPdpt;
4024 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4025 AssertRCReturn(rc, NULL);
4026
4027 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4028 return &pPdpt->a[iPdPt];
4029 }
4030 return NULL;
4031}
4032
4033
4034/**
4035 * Gets the page directory entry for the specified address.
4036 *
4037 * @returns The page directory entry in question.
4038 * @returns A non-present entry if the page directory is not present or on an invalid page.
4039 * @param pPGM Pointer to the PGM instance data.
4040 * @param GCPtr The address.
4041 * @param ppPml4e Page Map Level-4 Entry (out)
4042 * @param pPdpe Page directory pointer table entry (out)
4043 */
4044DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4045{
4046 X86PDEPAE ZeroPde = {0};
4047 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4048 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4049 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4050 if (pPml4e->n.u1Present)
4051 {
4052 PCX86PDPT pPdptTemp;
4053 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4054 AssertRCReturn(rc, ZeroPde);
4055
4056 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4057 *pPdpe = pPdptTemp->a[iPdPt];
4058 if (pPdptTemp->a[iPdPt].n.u1Present)
4059 {
4060 PCX86PDPAE pPD;
4061 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4062 AssertRCReturn(rc, ZeroPde);
4063
4064 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4065 return pPD->a[iPD];
4066 }
4067 }
4068
4069 return ZeroPde;
4070}
4071
4072
4073/**
4074 * Gets the page directory entry for the specified address.
4075 *
4076 * @returns The page directory entry in question.
4077 * @returns A non-present entry if the page directory is not present or on an invalid page.
4078 * @param pPGM Pointer to the PGM instance data.
4079 * @param GCPtr The address.
4080 */
4081DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4082{
4083 X86PDEPAE ZeroPde = {0};
4084 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4085 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4086 if (pGuestPml4->a[iPml4].n.u1Present)
4087 {
4088 PCX86PDPT pPdptTemp;
4089 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4090 AssertRCReturn(rc, ZeroPde);
4091
4092 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4093 if (pPdptTemp->a[iPdPt].n.u1Present)
4094 {
4095 PCX86PDPAE pPD;
4096 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4097 AssertRCReturn(rc, ZeroPde);
4098
4099 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4100 return pPD->a[iPD];
4101 }
4102 }
4103 return ZeroPde;
4104}
4105
4106
4107/**
4108 * Gets the page directory entry for the specified address.
4109 *
4110 * @returns Pointer to the page directory entry in question.
4111 * @returns NULL if the page directory is not present or on an invalid page.
4112 * @param pPGM Pointer to the PGM instance data.
4113 * @param GCPtr The address.
4114 */
4115DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4116{
4117 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4118 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4119 if (pGuestPml4->a[iPml4].n.u1Present)
4120 {
4121 PCX86PDPT pPdptTemp;
4122 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4123 AssertRCReturn(rc, NULL);
4124
4125 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4126 if (pPdptTemp->a[iPdPt].n.u1Present)
4127 {
4128 PX86PDPAE pPD;
4129 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4130 AssertRCReturn(rc, NULL);
4131
4132 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4133 return &pPD->a[iPD];
4134 }
4135 }
4136 return NULL;
4137}
4138
4139
4140/**
4141 * Gets the GUEST page directory pointer for the specified address.
4142 *
4143 * @returns The page directory in question.
4144 * @returns NULL if the page directory is not present or on an invalid page.
4145 * @param pPGM Pointer to the PGM instance data.
4146 * @param GCPtr The address.
4147 * @param ppPml4e Page Map Level-4 Entry (out)
4148 * @param pPdpe Page directory pointer table entry (out)
4149 * @param piPD Receives the index into the returned page directory
4150 */
4151DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4152{
4153 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4154 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4155 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4156 if (pPml4e->n.u1Present)
4157 {
4158 PCX86PDPT pPdptTemp;
4159 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4160 AssertRCReturn(rc, NULL);
4161
4162 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4163 *pPdpe = pPdptTemp->a[iPdPt];
4164 if (pPdptTemp->a[iPdPt].n.u1Present)
4165 {
4166 PX86PDPAE pPD;
4167 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4168 AssertRCReturn(rc, NULL);
4169
4170 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4171 return pPD;
4172 }
4173 }
4174 return 0;
4175}
4176
4177#endif /* !IN_RC */
4178
4179
4180/**
4181 * Gets the shadow page directory, 32-bit.
4182 *
4183 * @returns Pointer to the shadow 32-bit PD.
4184 * @param pPGM Pointer to the PGM instance data.
4185 */
4186DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4187{
4188#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4189 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4190#else
4191# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4192 PX86PD pShwPd;
4193 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4194 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4195 AssertRCReturn(rc, NULL);
4196 return pShwPd;
4197# else
4198 return pPGM->CTX_SUFF(pShw32BitPd);
4199# endif
4200#endif
4201}
4202
4203
4204/**
4205 * Gets the shadow page directory entry for the specified address, 32-bit.
4206 *
4207 * @returns Shadow 32-bit PDE.
4208 * @param pPGM Pointer to the PGM instance data.
4209 * @param GCPtr The address.
4210 */
4211DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4212{
4213 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4214
4215 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4216 if (!pShwPde)
4217 {
4218 X86PDE ZeroPde = {0};
4219 return ZeroPde;
4220 }
4221 return pShwPde->a[iPd];
4222}
4223
4224
4225/**
4226 * Gets the pointer to the shadow page directory entry for the specified
4227 * address, 32-bit.
4228 *
4229 * @returns Pointer to the shadow 32-bit PDE.
4230 * @param pPGM Pointer to the PGM instance data.
4231 * @param GCPtr The address.
4232 */
4233DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4234{
4235 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4236
4237 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4238 AssertReturn(pPde, NULL);
4239 return &pPde->a[iPd];
4240}
4241
4242
4243/**
4244 * Gets the shadow page pointer table, PAE.
4245 *
4246 * @returns Pointer to the shadow PAE PDPT.
4247 * @param pPGM Pointer to the PGM instance data.
4248 */
4249DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4250{
4251#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4252 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4253#else
4254# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4255 PX86PDPT pShwPdpt;
4256 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4257 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4258 AssertRCReturn(rc, 0);
4259 return pShwPdpt;
4260# else
4261 return pPGM->CTX_SUFF(pShwPaePdpt);
4262# endif
4263#endif
4264}
4265
4266
4267/**
4268 * Gets the shadow page directory for the specified address, PAE.
4269 *
4270 * @returns Pointer to the shadow PD.
4271 * @param pPGM Pointer to the PGM instance data.
4272 * @param GCPtr The address.
4273 */
4274DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4275{
4276#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4277 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4278 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4279
4280 if (!pPdpt->a[iPdpt].n.u1Present)
4281 return NULL;
4282
4283 /* Fetch the pgm pool shadow descriptor. */
4284 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4285 AssertReturn(pShwPde, NULL);
4286
4287 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4288#else
4289 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4290# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4291 PX86PDPAE pPD;
4292 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4293 AssertRCReturn(rc, 0);
4294 return pPD;
4295# else
4296 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4297 Assert(pPD);
4298 return pPD;
4299# endif
4300#endif
4301}
4302
4303/**
4304 * Gets the shadow page directory for the specified address, PAE.
4305 *
4306 * @returns Pointer to the shadow PD.
4307 * @param pPGM Pointer to the PGM instance data.
4308 * @param GCPtr The address.
4309 */
4310DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4311{
4312#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4313 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4314
4315 if (!pPdpt->a[iPdpt].n.u1Present)
4316 return NULL;
4317
4318 /* Fetch the pgm pool shadow descriptor. */
4319 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4320 AssertReturn(pShwPde, NULL);
4321
4322 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4323#else
4324 AssertFailed();
4325 return NULL;
4326#endif
4327}
4328
4329/**
4330 * Gets the shadow page directory entry, PAE.
4331 *
4332 * @returns PDE.
4333 * @param pPGM Pointer to the PGM instance data.
4334 * @param GCPtr The address.
4335 */
4336DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4337{
4338 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4339
4340 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4341 if (!pShwPde)
4342 {
4343 X86PDEPAE ZeroPde = {0};
4344 return ZeroPde;
4345 }
4346 return pShwPde->a[iPd];
4347}
4348
4349
4350/**
4351 * Gets the pointer to the shadow page directory entry for an address, PAE.
4352 *
4353 * @returns Pointer to the PDE.
4354 * @param pPGM Pointer to the PGM instance data.
4355 * @param GCPtr The address.
4356 */
4357DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4358{
4359 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4360
4361 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4362 AssertReturn(pPde, NULL);
4363 return &pPde->a[iPd];
4364}
4365
4366#ifndef IN_RC
4367/**
4368 * Gets the shadow page map level-4 pointer.
4369 *
4370 * @returns Pointer to the shadow PML4.
4371 * @param pPGM Pointer to the PGM instance data.
4372 */
4373DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4374{
4375#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4376 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4377#else
4378# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4379 PX86PML4 pShwPml4;
4380 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4381 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4382 AssertRCReturn(rc, 0);
4383 return pShwPml4;
4384# else
4385 Assert(pPGM->CTX_SUFF(pShwRoot));
4386 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4387# endif
4388#endif
4389}
4390
4391
4392/**
4393 * Gets the shadow page map level-4 entry for the specified address.
4394 *
4395 * @returns The entry.
4396 * @param pPGM Pointer to the PGM instance data.
4397 * @param GCPtr The address.
4398 */
4399DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4400{
4401 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4402 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4403
4404 if (!pShwPml4)
4405 {
4406 X86PML4E ZeroPml4e = {0};
4407 return ZeroPml4e;
4408 }
4409 return pShwPml4->a[iPml4];
4410}
4411
4412
4413/**
4414 * Gets the pointer to the specified shadow page map level-4 entry.
4415 *
4416 * @returns The entry.
4417 * @param pPGM Pointer to the PGM instance data.
4418 * @param iPml4 The PML4 index.
4419 */
4420DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4421{
4422 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4423 if (!pShwPml4)
4424 return NULL;
4425 return &pShwPml4->a[iPml4];
4426}
4427
4428
4429/**
4430 * Gets the GUEST page directory pointer for the specified address.
4431 *
4432 * @returns The page directory in question.
4433 * @returns NULL if the page directory is not present or on an invalid page.
4434 * @param pPGM Pointer to the PGM instance data.
4435 * @param GCPtr The address.
4436 * @param piPD Receives the index into the returned page directory
4437 */
4438DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4439{
4440 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4441 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4442 if (pGuestPml4->a[iPml4].n.u1Present)
4443 {
4444 PCX86PDPT pPdptTemp;
4445 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4446 AssertRCReturn(rc, NULL);
4447
4448 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4449 if (pPdptTemp->a[iPdPt].n.u1Present)
4450 {
4451 PX86PDPAE pPD;
4452 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4453 AssertRCReturn(rc, NULL);
4454
4455 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4456 return pPD;
4457 }
4458 }
4459 return NULL;
4460}
4461
4462#endif /* !IN_RC */
4463
4464/**
4465 * Checks if any of the specified page flags are set for the given page.
4466 *
4467 * @returns true if any of the flags are set.
4468 * @returns false if all the flags are clear.
4469 * @param pPGM PGM handle.
4470 * @param GCPhys The GC physical address.
4471 * @param fFlags The flags to check for.
4472 */
4473DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4474{
4475 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4476 return pPage
4477 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4478}
4479
4480
4481/**
4482 * Gets the page state for a physical handler.
4483 *
4484 * @returns The physical handler page state.
4485 * @param pCur The physical handler in question.
4486 */
4487DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4488{
4489 switch (pCur->enmType)
4490 {
4491 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4492 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4493
4494 case PGMPHYSHANDLERTYPE_MMIO:
4495 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4496 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4497
4498 default:
4499 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4500 }
4501}
4502
4503
4504/**
4505 * Gets the page state for a virtual handler.
4506 *
4507 * @returns The virtual handler page state.
4508 * @param pCur The virtual handler in question.
4509 * @remarks This should never be used on a hypervisor access handler.
4510 */
4511DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4512{
4513 switch (pCur->enmType)
4514 {
4515 case PGMVIRTHANDLERTYPE_WRITE:
4516 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4517 case PGMVIRTHANDLERTYPE_ALL:
4518 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4519 default:
4520 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4521 }
4522}
4523
4524
4525/**
4526 * Clears one physical page of a virtual handler
4527 *
4528 * @param pPGM Pointer to the PGM instance.
4529 * @param pCur Virtual handler structure
4530 * @param iPage Physical page index
4531 *
4532 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4533 * need to care about other handlers in the same page.
4534 */
4535DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4536{
4537 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4538
4539 /*
4540 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4541 */
4542#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4543 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4544 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4545 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4546#endif
4547 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4548 {
4549 /* We're the head of the alias chain. */
4550 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4551#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4552 AssertReleaseMsg(pRemove != NULL,
4553 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4554 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4555 AssertReleaseMsg(pRemove == pPhys2Virt,
4556 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4557 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4558 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4559 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4560#endif
4561 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4562 {
4563 /* Insert the next list in the alias chain into the tree. */
4564 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4565#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4566 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4567 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4568 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4569#endif
4570 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4571 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4572 AssertRelease(fRc);
4573 }
4574 }
4575 else
4576 {
4577 /* Locate the previous node in the alias chain. */
4578 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4579#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4580 AssertReleaseMsg(pPrev != pPhys2Virt,
4581 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4582 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4583#endif
4584 for (;;)
4585 {
4586 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4587 if (pNext == pPhys2Virt)
4588 {
4589 /* unlink. */
4590 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4591 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4592 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4593 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4594 else
4595 {
4596 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4597 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4598 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4599 }
4600 break;
4601 }
4602
4603 /* next */
4604 if (pNext == pPrev)
4605 {
4606#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4607 AssertReleaseMsg(pNext != pPrev,
4608 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4609 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4610#endif
4611 break;
4612 }
4613 pPrev = pNext;
4614 }
4615 }
4616 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4617 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4618 pPhys2Virt->offNextAlias = 0;
4619 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4620
4621 /*
4622 * Clear the ram flags for this page.
4623 */
4624 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4625 AssertReturnVoid(pPage);
4626 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4627}
4628
4629
4630/**
4631 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4632 *
4633 * @returns Pointer to the shadow page structure.
4634 * @param pPool The pool.
4635 * @param HCPhys The HC physical address of the shadow page.
4636 */
4637DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4638{
4639 /*
4640 * Look up the page.
4641 */
4642 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4643 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4644 return pPage;
4645}
4646
4647
4648/**
4649 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4650 *
4651 * @returns Pointer to the shadow page structure.
4652 * @param pPool The pool.
4653 * @param idx The pool page index.
4654 */
4655DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4656{
4657 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4658 return &pPool->aPages[idx];
4659}
4660
4661
4662#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4663/**
4664 * Clear references to guest physical memory.
4665 *
4666 * @param pPool The pool.
4667 * @param pPoolPage The pool page.
4668 * @param pPhysPage The physical guest page tracking structure.
4669 */
4670DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4671{
4672 /*
4673 * Just deal with the simple case here.
4674 */
4675# ifdef LOG_ENABLED
4676 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4677# endif
4678 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4679 if (cRefs == 1)
4680 {
4681 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4682 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4683 }
4684 else
4685 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4686 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4687}
4688#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4689
4690
4691#ifdef PGMPOOL_WITH_CACHE
4692/**
4693 * Moves the page to the head of the age list.
4694 *
4695 * This is done when the cached page is used in one way or another.
4696 *
4697 * @param pPool The pool.
4698 * @param pPage The cached page.
4699 * @todo inline in PGMInternal.h!
4700 */
4701DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4702{
4703 /*
4704 * Move to the head of the age list.
4705 */
4706 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4707 {
4708 /* unlink */
4709 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4710 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4711 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4712 else
4713 pPool->iAgeTail = pPage->iAgePrev;
4714
4715 /* insert at head */
4716 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4717 pPage->iAgeNext = pPool->iAgeHead;
4718 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4719 pPool->iAgeHead = pPage->idx;
4720 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4721 }
4722}
4723#endif /* PGMPOOL_WITH_CACHE */
4724
4725/**
4726 * Tells if mappings are to be put into the shadow page table or not
4727 *
4728 * @returns boolean result
4729 * @param pVM VM handle.
4730 */
4731
4732DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4733{
4734#ifdef IN_RING0
4735 /* There are no mappings in VT-x and AMD-V mode. */
4736 Assert(pPGM->fDisableMappings);
4737 return false;
4738#else
4739 return !pPGM->fDisableMappings;
4740#endif
4741}
4742
4743/** @} */
4744
4745#endif
4746
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