PGMInternal.h@ 17290

Last change on this file since 17290 was 17290, checked in by vboxsync, 16 years ago
PGM: -MM_RAM_FLAGS_IDX_SHIFT, -MM_RAM_FLAGS_IDX_MASK
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 198.3 KB

Line
1	/* $Id: PGMInternal.h 17290 2009-03-03 15:05:31Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/*
57	* Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58	*/
59	#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61	/**
62	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63	* Comment it if it will break something.
64	*/
65	#define PGM_OUT_OF_SYNC_IN_GC
66
67	/**
68	* Check and skip global PDEs for non-global flushes
69	*/
70	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72	/**
73	* Sync N pages instead of a whole page table
74	*/
75	#define PGM_SYNC_N_PAGES
76
77	/**
78	* Number of pages to sync during a page fault
79	*
80	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82	*/
83	#define PGM_SYNC_NR_PAGES 8
84
85	/**
86	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87	*/
88	#define PGM_MAX_PHYSCACHE_ENTRIES 64
89	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91	/**
92	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93	*/
94	#define PGM_PHYSMEMACCESS_CACHING
95
96	/** @def PGMPOOL_WITH_CACHE
97	* Enable agressive caching using the page pool.
98	*
99	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100	*/
101	#define PGMPOOL_WITH_CACHE
102
103	/** @def PGMPOOL_WITH_MIXED_PT_CR3
104	* When defined, we'll deal with 'uncachable' pages.
105	*/
106	#ifdef PGMPOOL_WITH_CACHE
107	# define PGMPOOL_WITH_MIXED_PT_CR3
108	#endif
109
110	/** @def PGMPOOL_WITH_MONITORING
111	* Monitor the guest pages which are shadowed.
112	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113	* be enabled as well.
114	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115	*/
116	#ifdef PGMPOOL_WITH_CACHE
117	# define PGMPOOL_WITH_MONITORING
118	#endif
119
120	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121	* Tracking the of shadow pages mapping guest physical pages.
122	*
123	* This is very expensive, the current cache prototype is trying to figure out
124	* whether it will be acceptable with an agressive caching policy.
125	*/
126	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
127	# define PGMPOOL_WITH_GCPHYS_TRACKING
128	#endif
129
130	/** @def PGMPOOL_WITH_USER_TRACKING
131	* Tracking users of shadow pages. This is required for the linking of shadow page
132	* tables and physical guest addresses.
133	*/
134	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
135	# define PGMPOOL_WITH_USER_TRACKING
136	#endif
137
138	/** @def PGMPOOL_CFG_MAX_GROW
139	* The maximum number of pages to add to the pool in one go.
140	*/
141	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
145	*/
146	#ifdef VBOX_STRICT
147	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148	#endif
149	/** @} */
150
151
152	/** @name PDPT and PML4 flags.
153	* These are placed in the three bits available for system programs in
154	* the PDPT and PML4 entries.
155	* @{ */
156	/** The entry is a permanent one and it's must always be present.
157	* Never free such an entry. */
158	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159	/** Mapping (hypervisor allocated pagetable). */
160	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161	/** @} */
162
163	/** @name Page directory flags.
164	* These are placed in the three bits available for system programs in
165	* the page directory entries.
166	* @{ */
167	/** Mapping (hypervisor allocated pagetable). */
168	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169	/** Made read-only to facilitate dirty bit tracking. */
170	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171	/** @} */
172
173	/** @name Page flags.
174	* These are placed in the three bits available for system programs in
175	* the page entries.
176	* @{ */
177	/** Made read-only to facilitate dirty bit tracking. */
178	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181	/** Scanned and approved by CSAM (tm).
182	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
183	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185	#endif
186
187	/** Mark a dynamic map entry (PGMDynMapHCPage) as locked. */
188	#define PGM_PTFLAGS_DYN_LOCKED RT_BIT(9)
189
190	/** @} */
191
192	/** @name Defines used to indicate the shadow and guest paging in the templates.
193	* @{ */
194	#define PGM_TYPE_REAL 1
195	#define PGM_TYPE_PROT 2
196	#define PGM_TYPE_32BIT 3
197	#define PGM_TYPE_PAE 4
198	#define PGM_TYPE_AMD64 5
199	#define PGM_TYPE_NESTED 6
200	#define PGM_TYPE_EPT 7
201	#define PGM_TYPE_MAX PGM_TYPE_EPT
202	/** @} */
203
204	/** Macro for checking if the guest is using paging.
205	* @param uGstType PGM_TYPE_*
206	* @param uShwType PGM_TYPE_*
207	* @remark ASSUMES certain order of the PGM_TYPE_* values.
208	*/
209	#define PGM_WITH_PAGING(uGstType, uShwType) \
210	( (uGstType) >= PGM_TYPE_32BIT \
211	&& (uShwType) != PGM_TYPE_NESTED \
212	&& (uShwType) != PGM_TYPE_EPT)
213
214	/** Macro for checking if the guest supports the NX bit.
215	* @param uGstType PGM_TYPE_*
216	* @param uShwType PGM_TYPE_*
217	* @remark ASSUMES certain order of the PGM_TYPE_* values.
218	*/
219	#define PGM_WITH_NX(uGstType, uShwType) \
220	( (uGstType) >= PGM_TYPE_PAE \
221	&& (uShwType) != PGM_TYPE_NESTED \
222	&& (uShwType) != PGM_TYPE_EPT)
223
224
225	/** @def PGM_HCPHYS_2_PTR
226	* Maps a HC physical page pool address to a virtual address.
227	*
228	* @returns VBox status code.
229	* @param pVM The VM handle.
230	* @param HCPhys The HC physical address to map to a virtual one.
231	* @param ppv Where to store the virtual address. No need to cast this.
232	*
233	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234	* small page window employeed by that function. Be careful.
235	* @remark There is no need to assert on the result.
236	*/
237	#ifdef IN_RC
238	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243	#else
244	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246	#endif
247
248	/** @def PGM_HCPHYS_2_PTR_BY_PGM
249	* Maps a HC physical page pool address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pPGM The PGM instance data.
253	* @param HCPhys The HC physical address to map to a virtual one.
254	* @param ppv Where to store the virtual address. No need to cast this.
255	*
256	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257	* small page window employeed by that function. Be careful.
258	* @remark There is no need to assert on the result.
259	*/
260	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263	#else
264	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266	#endif
267
268	/** @def PGM_GCPHYS_2_PTR
269	* Maps a GC physical page address to a virtual address.
270	*
271	* @returns VBox status code.
272	* @param pVM The VM handle.
273	* @param GCPhys The GC physical address to map to a virtual one.
274	* @param ppv Where to store the virtual address. No need to cast this.
275	*
276	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277	* small page window employeed by that function. Be careful.
278	* @remark There is no need to assert on the result.
279	*/
280	#ifdef IN_RC
281	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286	#else
287	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289	#endif
290
291	/** @def PGM_GCPHYS_2_PTR_BY_PGM
292	* Maps a GC physical page address to a virtual address.
293	*
294	* @returns VBox status code.
295	* @param pPGM Pointer to the PGM instance data.
296	* @param GCPhys The GC physical address to map to a virtual one.
297	* @param ppv Where to store the virtual address. No need to cast this.
298	*
299	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300	* small page window employeed by that function. Be careful.
301	* @remark There is no need to assert on the result.
302	*/
303	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
306	#else
307	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
309	#endif
310
311	/** @def PGM_GCPHYS_2_PTR_EX
312	* Maps a unaligned GC physical page address to a virtual address.
313	*
314	* @returns VBox status code.
315	* @param pVM The VM handle.
316	* @param GCPhys The GC physical address to map to a virtual one.
317	* @param ppv Where to store the virtual address. No need to cast this.
318	*
319	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320	* small page window employeed by that function. Be careful.
321	* @remark There is no need to assert on the result.
322	*/
323	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326	#else
327	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329	#endif
330
331	/** @def PGM_INVL_PG
332	* Invalidates a page when in GC does nothing in HC.
333	*
334	* @param GCVirt The virtual address of the page to invalidate.
335	*/
336	#ifdef IN_RC
337	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
338	#elif defined(IN_RING0)
339	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340	#else
341	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
342	#endif
343
344	/** @def PGM_INVL_BIG_PG
345	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
346	*
347	* @param GCVirt The virtual address within the page directory to invalidate.
348	*/
349	#ifdef IN_RC
350	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
351	#elif defined(IN_RING0)
352	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353	#else
354	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
355	#endif
356
357	/** @def PGM_INVL_GUEST_TLBS()
358	* Invalidates all guest TLBs.
359	*/
360	#ifdef IN_RC
361	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
362	#elif defined(IN_RING0)
363	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364	#else
365	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
366	#endif
367
368
369	/**
370	* Structure for tracking GC Mappings.
371	*
372	* This structure is used by linked list in both GC and HC.
373	*/
374	typedef struct PGMMAPPING
375	{
376	/** Pointer to next entry. */
377	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378	/** Pointer to next entry. */
379	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380	/** Pointer to next entry. */
381	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382	/** Indicate whether this entry is finalized. */
383	bool fFinalized;
384	/** Start Virtual address. */
385	RTGCPTR GCPtr;
386	/** Last Virtual address (inclusive). */
387	RTGCPTR GCPtrLast;
388	/** Range size (bytes). */
389	RTGCPTR cb;
390	/** Pointer to relocation callback function. */
391	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392	/** User argument to the callback. */
393	R3PTRTYPE(void *) pvUser;
394	/** Mapping description / name. For easing debugging. */
395	R3PTRTYPE(const char *) pszDesc;
396	/** Number of page tables. */
397	uint32_t cPTs;
398	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
399	uint32_t uPadding1; /*< Alignment padding. /
400	#endif
401	/** Array of page table mapping data. Each entry
402	* describes one page table. The array can be longer
403	* than the declared length.
404	*/
405	struct
406	{
407	/** The HC physical address of the page table. */
408	RTHCPHYS HCPhysPT;
409	/** The HC physical address of the first PAE page table. */
410	RTHCPHYS HCPhysPaePT0;
411	/** The HC physical address of the second PAE page table. */
412	RTHCPHYS HCPhysPaePT1;
413	/** The HC virtual address of the 32-bit page table. */
414	R3PTRTYPE(PX86PT) pPTR3;
415	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
416	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
417	/** The GC virtual address of the 32-bit page table. */
418	RCPTRTYPE(PX86PT) pPTRC;
419	/** The GC virtual address of the two PAE page table. */
420	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
421	/** The GC virtual address of the 32-bit page table. */
422	R0PTRTYPE(PX86PT) pPTR0;
423	/** The GC virtual address of the two PAE page table. */
424	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
425	} aPTs[1];
426	} PGMMAPPING;
427	/** Pointer to structure for tracking GC Mappings. */
428	typedef struct PGMMAPPING *PPGMMAPPING;
429
430
431	/**
432	* Physical page access handler structure.
433	*
434	* This is used to keep track of physical address ranges
435	* which are being monitored in some kind of way.
436	*/
437	typedef struct PGMPHYSHANDLER
438	{
439	AVLROGCPHYSNODECORE Core;
440	/** Access type. */
441	PGMPHYSHANDLERTYPE enmType;
442	/** Number of pages to update. */
443	uint32_t cPages;
444	/** Pointer to R3 callback function. */
445	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
446	/** User argument for R3 handlers. */
447	R3PTRTYPE(void *) pvUserR3;
448	/** Pointer to R0 callback function. */
449	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
450	/** User argument for R0 handlers. */
451	R0PTRTYPE(void *) pvUserR0;
452	/** Pointer to GC callback function. */
453	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
454	/** User argument for RC handlers. */
455	RCPTRTYPE(void *) pvUserRC;
456	/** Description / Name. For easing debugging. */
457	R3PTRTYPE(const char *) pszDesc;
458	#ifdef VBOX_WITH_STATISTICS
459	/** Profiling of this handler. */
460	STAMPROFILE Stat;
461	#endif
462	} PGMPHYSHANDLER;
463	/** Pointer to a physical page access handler structure. */
464	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
465
466
467	/**
468	* Cache node for the physical addresses covered by a virtual handler.
469	*/
470	typedef struct PGMPHYS2VIRTHANDLER
471	{
472	/** Core node for the tree based on physical ranges. */
473	AVLROGCPHYSNODECORE Core;
474	/** Offset from this struct to the PGMVIRTHANDLER structure. */
475	int32_t offVirtHandler;
476	/** Offset of the next alias relative to this one.
477	* Bit 0 is used for indicating whether we're in the tree.
478	* Bit 1 is used for indicating that we're the head node.
479	*/
480	int32_t offNextAlias;
481	} PGMPHYS2VIRTHANDLER;
482	/** Pointer to a phys to virtual handler structure. */
483	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
484
485	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486	* node is in the tree. */
487	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
488	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489	* node is in the head of an alias chain.
490	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
491	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
492	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
493	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
494
495
496	/**
497	* Virtual page access handler structure.
498	*
499	* This is used to keep track of virtual address ranges
500	* which are being monitored in some kind of way.
501	*/
502	typedef struct PGMVIRTHANDLER
503	{
504	/** Core node for the tree based on virtual ranges. */
505	AVLROGCPTRNODECORE Core;
506	/** Size of the range (in bytes). */
507	RTGCPTR cb;
508	/** Number of cache pages. */
509	uint32_t cPages;
510	/** Access type. */
511	PGMVIRTHANDLERTYPE enmType;
512	/** Pointer to the RC callback function. */
513	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
514	#if HC_ARCH_BITS == 64
515	RTRCPTR padding;
516	#endif
517	/** Pointer to the R3 callback function for invalidation. */
518	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
519	/** Pointer to the R3 callback function. */
520	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
521	/** Description / Name. For easing debugging. */
522	R3PTRTYPE(const char *) pszDesc;
523	#ifdef VBOX_WITH_STATISTICS
524	/** Profiling of this handler. */
525	STAMPROFILE Stat;
526	#endif
527	/** Array of cached physical addresses for the monitored ranged. */
528	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
529	} PGMVIRTHANDLER;
530	/** Pointer to a virtual page access handler structure. */
531	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
532
533
534	/**
535	* Page type.
536	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
537	* @todo convert to \#defines.
538	*/
539	typedef enum PGMPAGETYPE
540	{
541	/** The usual invalid zero entry. */
542	PGMPAGETYPE_INVALID = 0,
543	/** RAM page. (RWX) */
544	PGMPAGETYPE_RAM,
545	/** MMIO2 page. (RWX) */
546	PGMPAGETYPE_MMIO2,
547	/** Shadowed ROM. (RWX) */
548	PGMPAGETYPE_ROM_SHADOW,
549	/** ROM page. (R-X) */
550	PGMPAGETYPE_ROM,
551	/** MMIO page. (---) */
552	PGMPAGETYPE_MMIO,
553	/** End of valid entries. */
554	PGMPAGETYPE_END
555	} PGMPAGETYPE;
556	AssertCompile(PGMPAGETYPE_END < 7);
557
558	/** @name Page type predicates.
559	* @{ */
560	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
561	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
562	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
563	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
564	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
565	/** @} */
566
567
568	/**
569	* A Physical Guest Page tracking structure.
570	*
571	* The format of this structure is complicated because we have to fit a lot
572	* of information into as few bits as possible. The format is also subject
573	* to change (there is one comming up soon). Which means that for we'll be
574	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
575	* accessess to the structure.
576	*/
577	typedef struct PGMPAGE
578	{
579	/** The physical address and a whole lot of other stuff. All bits are used! */
580	RTHCPHYS HCPhys;
581	/** The page state. */
582	uint32_t u2StateX : 2;
583	/** Flag indicating that a write monitored page was written to when set. */
584	uint32_t fWrittenToX : 1;
585	/** For later. */
586	uint32_t fSomethingElse : 1;
587	/** The Page ID.
588	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
589	* The HCPhys will be 100% static. */
590	uint32_t idPageX : 28;
591	/** The page type (PGMPAGETYPE). */
592	uint32_t u3Type : 3;
593	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
594	uint32_t u2HandlerPhysStateX : 2;
595	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
596	uint32_t u2HandlerVirtStateX : 2;
597	uint32_t u29B : 25;
598	} PGMPAGE;
599	AssertCompileSize(PGMPAGE, 16);
600	/** Pointer to a physical guest page. */
601	typedef PGMPAGE *PPGMPAGE;
602	/** Pointer to a const physical guest page. */
603	typedef const PGMPAGE *PCPGMPAGE;
604	/** Pointer to a physical guest page pointer. */
605	typedef PPGMPAGE *PPPGMPAGE;
606
607
608	/**
609	* Clears the page structure.
610	* @param pPage Pointer to the physical guest page tracking structure.
611	*/
612	#define PGM_PAGE_CLEAR(pPage) \
613	do { \
614	(pPage)->HCPhys = 0; \
615	(pPage)->u2StateX = 0; \
616	(pPage)->fWrittenToX = 0; \
617	(pPage)->fSomethingElse = 0; \
618	(pPage)->idPageX = 0; \
619	(pPage)->u3Type = 0; \
620	(pPage)->u29B = 0; \
621	} while (0)
622
623	/**
624	* Initializes the page structure.
625	* @param pPage Pointer to the physical guest page tracking structure.
626	*/
627	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
628	do { \
629	(pPage)->HCPhys = (_HCPhys); \
630	(pPage)->u2StateX = (_uState); \
631	(pPage)->fWrittenToX = 0; \
632	(pPage)->fSomethingElse = 0; \
633	(pPage)->idPageX = (_idPage); \
634	/(pPage)->u3Type = (_uType); - later / \
635	PGM_PAGE_SET_TYPE(pPage, _uType); \
636	(pPage)->u29B = 0; \
637	} while (0)
638
639	/**
640	* Initializes the page structure of a ZERO page.
641	* @param pPage Pointer to the physical guest page tracking structure.
642	*/
643	#ifdef VBOX_WITH_NEW_PHYS_CODE
644	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
645	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
646	#else
647	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
648	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
649	#endif
650	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
651	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
652	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
653
654
655	/** @name The Page state, PGMPAGE::u2StateX.
656	* @{ */
657	/** The zero page.
658	* This is a per-VM page that's never ever mapped writable. */
659	#define PGM_PAGE_STATE_ZERO 0
660	/** A allocated page.
661	* This is a per-VM page allocated from the page pool (or wherever
662	* we get MMIO2 pages from if the type is MMIO2).
663	*/
664	#define PGM_PAGE_STATE_ALLOCATED 1
665	/** A allocated page that's being monitored for writes.
666	* The shadow page table mappings are read-only. When a write occurs, the
667	* fWrittenTo member is set, the page remapped as read-write and the state
668	* moved back to allocated. */
669	#define PGM_PAGE_STATE_WRITE_MONITORED 2
670	/** The page is shared, aka. copy-on-write.
671	* This is a page that's shared with other VMs. */
672	#define PGM_PAGE_STATE_SHARED 3
673	/** @} */
674
675
676	/**
677	* Gets the page state.
678	* @returns page state (PGM_PAGE_STATE_*).
679	* @param pPage Pointer to the physical guest page tracking structure.
680	*/
681	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
682
683	/**
684	* Sets the page state.
685	* @param pPage Pointer to the physical guest page tracking structure.
686	* @param _uState The new page state.
687	*/
688	#define PGM_PAGE_SET_STATE(pPage, _uState) \
689	do { (pPage)->u2StateX = (_uState); } while (0)
690
691
692	/**
693	* Gets the host physical address of the guest page.
694	* @returns host physical address (RTHCPHYS).
695	* @param pPage Pointer to the physical guest page tracking structure.
696	*/
697	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
698
699	/**
700	* Sets the host physical address of the guest page.
701	* @param pPage Pointer to the physical guest page tracking structure.
702	* @param _HCPhys The new host physical address.
703	*/
704	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
705	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
706	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
707
708	/**
709	* Get the Page ID.
710	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
711	* @param pPage Pointer to the physical guest page tracking structure.
712	*/
713	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
714	/* later:
715	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
716	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
717	*/
718	/**
719	* Sets the Page ID.
720	* @param pPage Pointer to the physical guest page tracking structure.
721	*/
722	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
723	/* later:
724	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
725	\| ((_idPage) & 0xfff) \
726	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
727	*/
728
729	/**
730	* Get the Chunk ID.
731	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
732	* @param pPage Pointer to the physical guest page tracking structure.
733	*/
734	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
735	/* later:
736	#if GMM_CHUNKID_SHIFT == 12
737	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
738	#elif GMM_CHUNKID_SHIFT > 12
739	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
740	#elif GMM_CHUNKID_SHIFT < 12
741	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
742	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
743	#else
744	# error "GMM_CHUNKID_SHIFT isn't defined or something."
745	#endif
746	*/
747
748	/**
749	* Get the index of the page within the allocaiton chunk.
750	* @returns The page index.
751	* @param pPage Pointer to the physical guest page tracking structure.
752	*/
753	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
754	/* later:
755	#if GMM_CHUNKID_SHIFT <= 12
756	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
757	#else
758	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
759	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
760	#endif
761	*/
762
763
764	/**
765	* Gets the page type.
766	* @returns The page type.
767	* @param pPage Pointer to the physical guest page tracking structure.
768	*/
769	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
770
771	/**
772	* Sets the page type.
773	* @param pPage Pointer to the physical guest page tracking structure.
774	* @param _enmType The new page type (PGMPAGETYPE).
775	*/
776	#ifdef VBOX_WITH_NEW_PHYS_CODE
777	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
778	do { (pPage)->u3Type = (_enmType); } while (0)
779	#else
780	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
781	do { \
782	(pPage)->u3Type = (_enmType); \
783	if ((_enmType) == PGMPAGETYPE_ROM) \
784	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
785	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
786	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
787	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
788	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
789	} while (0)
790	#endif
791
792
793	/**
794	* Checks if the page is 'reserved'.
795	* @returns true/false.
796	* @param pPage Pointer to the physical guest page tracking structure.
797	*/
798	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
799
800	/**
801	* Checks if the page is marked for MMIO.
802	* @returns true/false.
803	* @param pPage Pointer to the physical guest page tracking structure.
804	*/
805	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
806
807	/**
808	* Checks if the page is backed by the ZERO page.
809	* @returns true/false.
810	* @param pPage Pointer to the physical guest page tracking structure.
811	*/
812	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
813
814	/**
815	* Checks if the page is backed by a SHARED page.
816	* @returns true/false.
817	* @param pPage Pointer to the physical guest page tracking structure.
818	*/
819	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
820
821
822	/**
823	* Marks the paget as written to (for GMM change monitoring).
824	* @param pPage Pointer to the physical guest page tracking structure.
825	*/
826	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
827
828	/**
829	* Clears the written-to indicator.
830	* @param pPage Pointer to the physical guest page tracking structure.
831	*/
832	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
833
834	/**
835	* Checks if the page was marked as written-to.
836	* @returns true/false.
837	* @param pPage Pointer to the physical guest page tracking structure.
838	*/
839	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
840
841
842	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
843	*
844	* @remarks The values are assigned in order of priority, so we can calculate
845	* the correct state for a page with different handlers installed.
846	* @{ */
847	/** No handler installed. */
848	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
849	/** Monitoring is temporarily disabled. */
850	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
851	/** Write access is monitored. */
852	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
853	/** All access is monitored. */
854	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
855	/** @} */
856
857	/**
858	* Gets the physical access handler state of a page.
859	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
860	* @param pPage Pointer to the physical guest page tracking structure.
861	*/
862	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
863
864	/**
865	* Sets the physical access handler state of a page.
866	* @param pPage Pointer to the physical guest page tracking structure.
867	* @param _uState The new state value.
868	*/
869	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
870	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
871
872	/**
873	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
874	* @returns true/false
875	* @param pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
878
879	/**
880	* Checks if the page has any active physical access handlers.
881	* @returns true/false
882	* @param pPage Pointer to the physical guest page tracking structure.
883	*/
884	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
885
886
887	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
888	*
889	* @remarks The values are assigned in order of priority, so we can calculate
890	* the correct state for a page with different handlers installed.
891	* @{ */
892	/** No handler installed. */
893	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
894	/* 1 is reserved so the lineup is identical with the physical ones. */
895	/** Write access is monitored. */
896	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
897	/** All access is monitored. */
898	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
899	/** @} */
900
901	/**
902	* Gets the virtual access handler state of a page.
903	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
904	* @param pPage Pointer to the physical guest page tracking structure.
905	*/
906	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
907
908	/**
909	* Sets the virtual access handler state of a page.
910	* @param pPage Pointer to the physical guest page tracking structure.
911	* @param _uState The new state value.
912	*/
913	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
914	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
915
916	/**
917	* Checks if the page has any virtual access handlers.
918	* @returns true/false
919	* @param pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
922
923	/**
924	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
925	* virtual handlers.
926	* @returns true/false
927	* @param pPage Pointer to the physical guest page tracking structure.
928	*/
929	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
930
931
932
933	/**
934	* Checks if the page has any access handlers, including temporarily disabled ones.
935	* @returns true/false
936	* @param pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
939	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
940	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
941
942	/**
943	* Checks if the page has any active access handlers.
944	* @returns true/false
945	* @param pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
948	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
949	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
950
951	/**
952	* Checks if the page has any active access handlers catching all accesses.
953	* @returns true/false
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
957	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
958	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
959
960
961
962
963	/** @def PGM_PAGE_GET_TRACKING
964	* Gets the packed shadow page pool tracking data associated with a guest page.
965	* @returns uint16_t containing the data.
966	* @param pPage Pointer to the physical guest page tracking structure.
967	*/
968	#define PGM_PAGE_GET_TRACKING(pPage) \
969	( ((uint16_t )&(pPage)->HCPhys + 3) )
970
971	/** @def PGM_PAGE_SET_TRACKING
972	* Sets the packed shadow page pool tracking data associated with a guest page.
973	* @param pPage Pointer to the physical guest page tracking structure.
974	* @param u16TrackingData The tracking data to store.
975	*/
976	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
977	do { ((uint16_t )&(pPage)->HCPhys + 3) = (u16TrackingData); } while (0)
978
979	/** @def PGM_PAGE_GET_TD_CREFS
980	* Gets the @a cRefs tracking data member.
981	* @returns cRefs.
982	* @param pPage Pointer to the physical guest page tracking structure.
983	*/
984	#define PGM_PAGE_GET_TD_CREFS(pPage) \
985	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
986
987	#define PGM_PAGE_GET_TD_IDX(pPage) \
988	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
989
990	/**
991	* Ram range for GC Phys to HC Phys conversion.
992	*
993	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
994	* conversions too, but we'll let MM handle that for now.
995	*
996	* This structure is used by linked lists in both GC and HC.
997	*/
998	typedef struct PGMRAMRANGE
999	{
1000	/** Pointer to the next RAM range - for R3. */
1001	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1002	/** Pointer to the next RAM range - for R0. */
1003	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1004	/** Pointer to the next RAM range - for RC. */
1005	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1006	/** Pointer alignment. */
1007	RTRCPTR RCPtrAlignment;
1008	/** Start of the range. Page aligned. */
1009	RTGCPHYS GCPhys;
1010	/** Last address in the range (inclusive). Page aligned (-1). */
1011	RTGCPHYS GCPhysLast;
1012	/** Size of the range. (Page aligned of course). */
1013	RTGCPHYS cb;
1014	/** MM_RAM_* flags */
1015	uint32_t fFlags;
1016	uint32_t u32Alignment; /*< alignment. /
1017	#ifndef VBOX_WITH_NEW_PHYS_CODE
1018	/** R3 virtual lookup ranges for chunks.
1019	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1020	* @remarks This is occationally accessed from ring-0!! (not darwin) */
1021	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1022	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1023	# else
1024	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1025	# endif
1026	#endif
1027	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1028	R3PTRTYPE(void *) pvR3;
1029	/** The range description. */
1030	R3PTRTYPE(const char *) pszDesc;
1031
1032	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1033	#ifdef VBOX_WITH_NEW_PHYS_CODE
1034	uint32_t au32Reserved[2];
1035	#elif HC_ARCH_BITS == 32
1036	uint32_t au32Reserved[1];
1037	#endif
1038
1039	/** Array of physical guest page tracking structures. */
1040	PGMPAGE aPages[1];
1041	} PGMRAMRANGE;
1042	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1043	typedef PGMRAMRANGE *PPGMRAMRANGE;
1044
1045	/** Return hc ptr corresponding to the ram range and physical offset */
1046	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1047	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1048	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1049
1050	/**
1051	* Per page tracking structure for ROM image.
1052	*
1053	* A ROM image may have a shadow page, in which case we may have
1054	* two pages backing it. This structure contains the PGMPAGE for
1055	* both while PGMRAMRANGE have a copy of the active one. It is
1056	* important that these aren't out of sync in any regard other
1057	* than page pool tracking data.
1058	*/
1059	typedef struct PGMROMPAGE
1060	{
1061	/** The page structure for the virgin ROM page. */
1062	PGMPAGE Virgin;
1063	/** The page structure for the shadow RAM page. */
1064	PGMPAGE Shadow;
1065	/** The current protection setting. */
1066	PGMROMPROT enmProt;
1067	/** Pad the structure size to a multiple of 8. */
1068	uint32_t u32Padding;
1069	} PGMROMPAGE;
1070	/** Pointer to a ROM page tracking structure. */
1071	typedef PGMROMPAGE *PPGMROMPAGE;
1072
1073
1074	/**
1075	* A registered ROM image.
1076	*
1077	* This is needed to keep track of ROM image since they generally
1078	* intrude into a PGMRAMRANGE. It also keeps track of additional
1079	* info like the two page sets (read-only virgin and read-write shadow),
1080	* the current state of each page.
1081	*
1082	* Because access handlers cannot easily be executed in a different
1083	* context, the ROM ranges needs to be accessible and in all contexts.
1084	*/
1085	typedef struct PGMROMRANGE
1086	{
1087	/** Pointer to the next range - R3. */
1088	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1089	/** Pointer to the next range - R0. */
1090	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1091	/** Pointer to the next range - RC. */
1092	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1093	/** Pointer alignment */
1094	RTRCPTR GCPtrAlignment;
1095	/** Address of the range. */
1096	RTGCPHYS GCPhys;
1097	/** Address of the last byte in the range. */
1098	RTGCPHYS GCPhysLast;
1099	/** Size of the range. */
1100	RTGCPHYS cb;
1101	/** The flags (PGMPHYS_ROM_FLAG_). /
1102	uint32_t fFlags;
1103	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1104	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1105	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1106	* This is used for strictness checks. */
1107	R3PTRTYPE(const void *) pvOriginal;
1108	/** The ROM description. */
1109	R3PTRTYPE(const char *) pszDesc;
1110	/** The per page tracking structures. */
1111	PGMROMPAGE aPages[1];
1112	} PGMROMRANGE;
1113	/** Pointer to a ROM range. */
1114	typedef PGMROMRANGE *PPGMROMRANGE;
1115
1116
1117	/**
1118	* A registered MMIO2 (= Device RAM) range.
1119	*
1120	* There are a few reason why we need to keep track of these
1121	* registrations. One of them is the deregistration & cleanup
1122	* stuff, while another is that the PGMRAMRANGE associated with
1123	* such a region may have to be removed from the ram range list.
1124	*
1125	* Overlapping with a RAM range has to be 100% or none at all. The
1126	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1127	* meditation will be raised if a partial overlap or an overlap of
1128	* ROM pages is encountered. On an overlap we will free all the
1129	* existing RAM pages and put in the ram range pages instead.
1130	*/
1131	typedef struct PGMMMIO2RANGE
1132	{
1133	/** The owner of the range. (a device) */
1134	PPDMDEVINSR3 pDevInsR3;
1135	/** Pointer to the ring-3 mapping of the allocation. */
1136	RTR3PTR pvR3;
1137	/** Pointer to the next range - R3. */
1138	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1139	/** Whether it's mapped or not. */
1140	bool fMapped;
1141	/** Whether it's overlapping or not. */
1142	bool fOverlapping;
1143	/** The PCI region number.
1144	* @remarks This ASSUMES that nobody will ever really need to have multiple
1145	* PCI devices with matching MMIO region numbers on a single device. */
1146	uint8_t iRegion;
1147	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1148	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1149	/** The associated RAM range. */
1150	PGMRAMRANGE RamRange;
1151	} PGMMMIO2RANGE;
1152	/** Pointer to a MMIO2 range. */
1153	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1154
1155
1156
1157
1158	/**
1159	* PGMPhysRead/Write cache entry
1160	*/
1161	typedef struct PGMPHYSCACHEENTRY
1162	{
1163	/** R3 pointer to physical page. */
1164	R3PTRTYPE(uint8_t *) pbR3;
1165	/** GC Physical address for cache entry */
1166	RTGCPHYS GCPhys;
1167	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1168	RTGCPHYS u32Padding0; /*< alignment padding. /
1169	#endif
1170	} PGMPHYSCACHEENTRY;
1171
1172	/**
1173	* PGMPhysRead/Write cache to reduce REM memory access overhead
1174	*/
1175	typedef struct PGMPHYSCACHE
1176	{
1177	/** Bitmap of valid cache entries */
1178	uint64_t aEntries;
1179	/** Cache entries */
1180	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1181	} PGMPHYSCACHE;
1182
1183
1184	/** Pointer to an allocation chunk ring-3 mapping. */
1185	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1186	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1187	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1188
1189	/**
1190	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1191	*
1192	* The primary tree (Core) uses the chunk id as key.
1193	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1194	*/
1195	typedef struct PGMCHUNKR3MAP
1196	{
1197	/** The key is the chunk id. */
1198	AVLU32NODECORE Core;
1199	/** The key is the ageing sequence number. */
1200	AVLLU32NODECORE AgeCore;
1201	/** The current age thingy. */
1202	uint32_t iAge;
1203	/** The current reference count. */
1204	uint32_t volatile cRefs;
1205	/** The current permanent reference count. */
1206	uint32_t volatile cPermRefs;
1207	/** The mapping address. */
1208	void *pv;
1209	} PGMCHUNKR3MAP;
1210
1211	/**
1212	* Allocation chunk ring-3 mapping TLB entry.
1213	*/
1214	typedef struct PGMCHUNKR3MAPTLBE
1215	{
1216	/** The chunk id. */
1217	uint32_t volatile idChunk;
1218	#if HC_ARCH_BITS == 64
1219	uint32_t u32Padding; /*< alignment padding. /
1220	#endif
1221	/** The chunk map. */
1222	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1223	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1224	#else
1225	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1226	#endif
1227	} PGMCHUNKR3MAPTLBE;
1228	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1229	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1230
1231	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1232	* @remark Must be a power of two value. */
1233	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1234
1235	/**
1236	* Allocation chunk ring-3 mapping TLB.
1237	*
1238	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1239	* At first glance this might look kinda odd since AVL trees are
1240	* supposed to give the most optimial lookup times of all trees
1241	* due to their balancing. However, take a tree with 1023 nodes
1242	* in it, that's 10 levels, meaning that most searches has to go
1243	* down 9 levels before they find what they want. This isn't fast
1244	* compared to a TLB hit. There is the factor of cache misses,
1245	* and of course the problem with trees and branch prediction.
1246	* This is why we use TLBs in front of most of the trees.
1247	*
1248	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1249	* difficult when we switch to the new inlined AVL trees (from kStuff).
1250	*/
1251	typedef struct PGMCHUNKR3MAPTLB
1252	{
1253	/** The TLB entries. */
1254	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1255	} PGMCHUNKR3MAPTLB;
1256
1257	/**
1258	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1259	* @returns Chunk TLB index.
1260	* @param idChunk The Chunk ID.
1261	*/
1262	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1263
1264
1265	/**
1266	* Ring-3 guest page mapping TLB entry.
1267	* @remarks used in ring-0 as well at the moment.
1268	*/
1269	typedef struct PGMPAGER3MAPTLBE
1270	{
1271	/** Address of the page. */
1272	RTGCPHYS volatile GCPhys;
1273	/** The guest page. */
1274	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1275	R3PTRTYPE(PPGMPAGE) volatile pPage;
1276	#else
1277	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1278	#endif
1279	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1280	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1281	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1282	#else
1283	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1284	#endif
1285	/** The address */
1286	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1287	R3PTRTYPE(void *) volatile pv;
1288	#else
1289	R3R0PTRTYPE(void *) volatile pv;
1290	#endif
1291	#if HC_ARCH_BITS == 32
1292	uint32_t u32Padding; /*< alignment padding. /
1293	#endif
1294	} PGMPAGER3MAPTLBE;
1295	/** Pointer to an entry in the HC physical TLB. */
1296	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1297
1298
1299	/** The number of entries in the ring-3 guest page mapping TLB.
1300	* @remarks The value must be a power of two. */
1301	#define PGM_PAGER3MAPTLB_ENTRIES 64
1302
1303	/**
1304	* Ring-3 guest page mapping TLB.
1305	* @remarks used in ring-0 as well at the moment.
1306	*/
1307	typedef struct PGMPAGER3MAPTLB
1308	{
1309	/** The TLB entries. */
1310	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1311	} PGMPAGER3MAPTLB;
1312	/** Pointer to the ring-3 guest page mapping TLB. */
1313	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1314
1315	/**
1316	* Calculates the index of the TLB entry for the specified guest page.
1317	* @returns Physical TLB index.
1318	* @param GCPhys The guest physical address.
1319	*/
1320	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1321
1322
1323	/**
1324	* Mapping cache usage set entry.
1325	*
1326	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1327	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1328	* cache. If it's extended to include ring-3, well, then something will
1329	* have be changed here...
1330	*/
1331	typedef struct PGMMAPSETENTRY
1332	{
1333	/** The mapping cache index. */
1334	uint16_t iPage;
1335	/** The number of references.
1336	* The max is UINT16_MAX - 1. */
1337	uint16_t cRefs;
1338	/** Pointer to the page. */
1339	RTR0PTR pvPage;
1340	/** The physical address for this entry. */
1341	RTHCPHYS HCPhys;
1342	} PGMMAPSETENTRY;
1343	/** Pointer to a mapping cache usage set entry. */
1344	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1345
1346	/**
1347	* Mapping cache usage set.
1348	*
1349	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1350	* done during exits / traps. The set is
1351	*/
1352	typedef struct PGMMAPSET
1353	{
1354	/** The number of occupied entries.
1355	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1356	* dynamic mappings. */
1357	uint32_t cEntries;
1358	/** The start of the current subset.
1359	* This is UINT32_MAX if no subset is currently open. */
1360	uint32_t iSubset;
1361	/** The index of the current CPU, only valid if the set is open. */
1362	int32_t iCpu;
1363	/** The entries. */
1364	PGMMAPSETENTRY aEntries[64];
1365	/** HCPhys -> iEntry fast lookup table.
1366	* Use PGMMAPSET_HASH for hashing.
1367	* The entries may or may not be valid, check against cEntries. */
1368	uint8_t aiHashTable[128];
1369	} PGMMAPSET;
1370	/** Pointer to the mapping cache set. */
1371	typedef PGMMAPSET *PPGMMAPSET;
1372
1373	/** PGMMAPSET::cEntries value for a closed set. */
1374	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1375
1376	/** Hash function for aiHashTable. */
1377	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1378
1379	/** The max fill size (strict builds). */
1380	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1381
1382
1383	/** @name Context neutrual page mapper TLB.
1384	*
1385	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1386	* code is writting in a kind of context neutrual way. Time will show whether
1387	* this actually makes sense or not...
1388	*
1389	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1390	* context ends up using a global mapping cache on some platforms
1391	* (darwin).
1392	*
1393	* @{ */
1394	/** @typedef PPGMPAGEMAPTLB
1395	* The page mapper TLB pointer type for the current context. */
1396	/** @typedef PPGMPAGEMAPTLB
1397	* The page mapper TLB entry pointer type for the current context. */
1398	/** @typedef PPGMPAGEMAPTLB
1399	* The page mapper TLB entry pointer pointer type for the current context. */
1400	/** @def PGM_PAGEMAPTLB_ENTRIES
1401	* The number of TLB entries in the page mapper TLB for the current context. */
1402	/** @def PGM_PAGEMAPTLB_IDX
1403	* Calculate the TLB index for a guest physical address.
1404	* @returns The TLB index.
1405	* @param GCPhys The guest physical address. */
1406	/** @typedef PPGMPAGEMAP
1407	* Pointer to a page mapper unit for current context. */
1408	/** @typedef PPPGMPAGEMAP
1409	* Pointer to a page mapper unit pointer for current context. */
1410	#ifdef IN_RC
1411	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1412	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1413	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1414	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1415	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1416	typedef void * PPGMPAGEMAP;
1417	typedef void ** PPPGMPAGEMAP;
1418	//#elif IN_RING0
1419	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1420	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1421	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1422	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1423	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1424	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1425	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1426	#else
1427	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1428	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1429	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1430	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1431	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1432	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1433	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1434	#endif
1435	/** @} */
1436
1437
1438	/** @name PGM Pool Indexes.
1439	* Aka. the unique shadow page identifier.
1440	* @{ */
1441	/** NIL page pool IDX. */
1442	#define NIL_PGMPOOL_IDX 0
1443	/** The first normal index. */
1444	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1445	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1446	/** Page directory (32-bit root). */
1447	#define PGMPOOL_IDX_PD 1
1448	/** Page Directory Pointer Table (PAE root). */
1449	#define PGMPOOL_IDX_PDPT 2
1450	/** AMD64 CR3 level index.*/
1451	#define PGMPOOL_IDX_AMD64_CR3 3
1452	/** Nested paging root.*/
1453	#define PGMPOOL_IDX_NESTED_ROOT 4
1454	/** The first normal index. */
1455	#define PGMPOOL_IDX_FIRST 5
1456	#else
1457	/** Page directory (32-bit root). */
1458	#define PGMPOOL_IDX_PD 1
1459	/** The extended PAE page directory (2048 entries, works as root currently). */
1460	#define PGMPOOL_IDX_PAE_PD 2
1461	/** PAE Page Directory Table 0. */
1462	#define PGMPOOL_IDX_PAE_PD_0 3
1463	/** PAE Page Directory Table 1. */
1464	#define PGMPOOL_IDX_PAE_PD_1 4
1465	/** PAE Page Directory Table 2. */
1466	#define PGMPOOL_IDX_PAE_PD_2 5
1467	/** PAE Page Directory Table 3. */
1468	#define PGMPOOL_IDX_PAE_PD_3 6
1469	/** Page Directory Pointer Table (PAE root, not currently used). */
1470	#define PGMPOOL_IDX_PDPT 7
1471	/** AMD64 CR3 level index.*/
1472	#define PGMPOOL_IDX_AMD64_CR3 8
1473	/** Nested paging root.*/
1474	#define PGMPOOL_IDX_NESTED_ROOT 9
1475	/** The first normal index. */
1476	#define PGMPOOL_IDX_FIRST 10
1477	#endif
1478	/** The last valid index. (inclusive, 14 bits) */
1479	#define PGMPOOL_IDX_LAST 0x3fff
1480	/** @} */
1481
1482	/** The NIL index for the parent chain. */
1483	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1484
1485	/**
1486	* Node in the chain linking a shadowed page to it's parent (user).
1487	*/
1488	#pragma pack(1)
1489	typedef struct PGMPOOLUSER
1490	{
1491	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1492	uint16_t iNext;
1493	/** The user page index. */
1494	uint16_t iUser;
1495	/** Index into the user table. */
1496	uint32_t iUserTable;
1497	} PGMPOOLUSER, *PPGMPOOLUSER;
1498	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1499	#pragma pack()
1500
1501
1502	/** The NIL index for the phys ext chain. */
1503	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1504
1505	/**
1506	* Node in the chain of physical cross reference extents.
1507	* @todo Calling this an 'extent' is not quite right, find a better name.
1508	*/
1509	#pragma pack(1)
1510	typedef struct PGMPOOLPHYSEXT
1511	{
1512	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1513	uint16_t iNext;
1514	/** The user page index. */
1515	uint16_t aidx[3];
1516	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1517	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1518	#pragma pack()
1519
1520
1521	/**
1522	* The kind of page that's being shadowed.
1523	*/
1524	typedef enum PGMPOOLKIND
1525	{
1526	/** The virtual invalid 0 entry. */
1527	PGMPOOLKIND_INVALID = 0,
1528	/** The entry is free (=unused). */
1529	PGMPOOLKIND_FREE,
1530
1531	/** Shw: 32-bit page table; Gst: no paging */
1532	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1533	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1534	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1535	/** Shw: 32-bit page table; Gst: 4MB page. */
1536	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1537	/** Shw: PAE page table; Gst: no paging */
1538	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1539	/** Shw: PAE page table; Gst: 32-bit page table. */
1540	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1541	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1542	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1543	/** Shw: PAE page table; Gst: PAE page table. */
1544	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1545	/** Shw: PAE page table; Gst: 2MB page. */
1546	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1547
1548	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1549	PGMPOOLKIND_32BIT_PD,
1550	/** Shw: 32-bit page directory. Gst: no paging. */
1551	PGMPOOLKIND_32BIT_PD_PHYS,
1552	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1553	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1554	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1555	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1556	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1557	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1558	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1559	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1560	/** Shw: PAE page directory; Gst: PAE page directory. */
1561	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1562	/** Shw: PAE page directory; Gst: no paging. */
1563	PGMPOOLKIND_PAE_PD_PHYS,
1564
1565	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1566	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1567	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1568	PGMPOOLKIND_PAE_PDPT,
1569	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1570	PGMPOOLKIND_PAE_PDPT_PHYS,
1571
1572	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1573	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1574	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1575	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1576	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1577	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1578	/** Shw: 64-bit page directory table; Gst: no paging */
1579	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1580
1581	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1582	PGMPOOLKIND_64BIT_PML4,
1583
1584	/** Shw: EPT page directory pointer table; Gst: no paging */
1585	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1586	/** Shw: EPT page directory table; Gst: no paging */
1587	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1588	/** Shw: EPT page table; Gst: no paging */
1589	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1590
1591	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1592	/** Shw: Root 32-bit page directory. */
1593	PGMPOOLKIND_ROOT_32BIT_PD,
1594	/** Shw: Root PAE page directory */
1595	PGMPOOLKIND_ROOT_PAE_PD,
1596	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1597	PGMPOOLKIND_ROOT_PDPT,
1598	#endif
1599	/** Shw: Root Nested paging table. */
1600	PGMPOOLKIND_ROOT_NESTED,
1601
1602	/** The last valid entry. */
1603	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1604	} PGMPOOLKIND;
1605
1606
1607	/**
1608	* The tracking data for a page in the pool.
1609	*/
1610	typedef struct PGMPOOLPAGE
1611	{
1612	/** AVL node code with the (R3) physical address of this page. */
1613	AVLOHCPHYSNODECORE Core;
1614	/** Pointer to the R3 mapping of the page. */
1615	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1616	R3PTRTYPE(void *) pvPageR3;
1617	#else
1618	R3R0PTRTYPE(void *) pvPageR3;
1619	#endif
1620	/** The guest physical address. */
1621	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1622	uint32_t Alignment0;
1623	#endif
1624	RTGCPHYS GCPhys;
1625	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1626	uint8_t enmKind;
1627	uint8_t bPadding;
1628	/** The index of this page. */
1629	uint16_t idx;
1630	/** The next entry in the list this page currently resides in.
1631	* It's either in the free list or in the GCPhys hash. */
1632	uint16_t iNext;
1633	#ifdef PGMPOOL_WITH_USER_TRACKING
1634	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1635	uint16_t iUserHead;
1636	/** The number of present entries. */
1637	uint16_t cPresent;
1638	/** The first entry in the table which is present. */
1639	uint16_t iFirstPresent;
1640	#endif
1641	#ifdef PGMPOOL_WITH_MONITORING
1642	/** The number of modifications to the monitored page. */
1643	uint16_t cModifications;
1644	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1645	uint16_t iModifiedNext;
1646	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1647	uint16_t iModifiedPrev;
1648	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1649	uint16_t iMonitoredNext;
1650	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1651	uint16_t iMonitoredPrev;
1652	#endif
1653	#ifdef PGMPOOL_WITH_CACHE
1654	/** The next page in the age list. */
1655	uint16_t iAgeNext;
1656	/** The previous page in the age list. */
1657	uint16_t iAgePrev;
1658	#endif /* PGMPOOL_WITH_CACHE */
1659	/** Used to indicate that the page is zeroed. */
1660	bool fZeroed;
1661	/** Used to indicate that a PT has non-global entries. */
1662	bool fSeenNonGlobal;
1663	/** Used to indicate that we're monitoring writes to the guest page. */
1664	bool fMonitored;
1665	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1666	* (All pages are in the age list.) */
1667	bool fCached;
1668	/** This is used by the R3 access handlers when invoked by an async thread.
1669	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1670	bool volatile fReusedFlushPending;
1671	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1672	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1673	bool fLocked;
1674	#else
1675	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1676	* In these cases the access handler acts differently and will check
1677	* for mapping conflicts like the normal CR3 handler.
1678	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1679	* replaced by a list of pages which share access handler.
1680	*/
1681	bool fCR3Mix;
1682	#endif
1683	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1684
1685
1686	#ifdef PGMPOOL_WITH_CACHE
1687	/** The hash table size. */
1688	# define PGMPOOL_HASH_SIZE 0x40
1689	/** The hash function. */
1690	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1691	#endif
1692
1693
1694	/**
1695	* The shadow page pool instance data.
1696	*
1697	* It's all one big allocation made at init time, except for the
1698	* pages that is. The user nodes follows immediatly after the
1699	* page structures.
1700	*/
1701	typedef struct PGMPOOL
1702	{
1703	/** The VM handle - R3 Ptr. */
1704	PVMR3 pVMR3;
1705	/** The VM handle - R0 Ptr. */
1706	PVMR0 pVMR0;
1707	/** The VM handle - RC Ptr. */
1708	PVMRC pVMRC;
1709	/** The max pool size. This includes the special IDs. */
1710	uint16_t cMaxPages;
1711	/** The current pool size. */
1712	uint16_t cCurPages;
1713	/** The head of the free page list. */
1714	uint16_t iFreeHead;
1715	/* Padding. */
1716	uint16_t u16Padding;
1717	#ifdef PGMPOOL_WITH_USER_TRACKING
1718	/** Head of the chain of free user nodes. */
1719	uint16_t iUserFreeHead;
1720	/** The number of user nodes we've allocated. */
1721	uint16_t cMaxUsers;
1722	/** The number of present page table entries in the entire pool. */
1723	uint32_t cPresent;
1724	/** Pointer to the array of user nodes - RC pointer. */
1725	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1726	/** Pointer to the array of user nodes - R3 pointer. */
1727	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1728	/** Pointer to the array of user nodes - R0 pointer. */
1729	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1730	#endif /* PGMPOOL_WITH_USER_TRACKING */
1731	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1732	/** Head of the chain of free phys ext nodes. */
1733	uint16_t iPhysExtFreeHead;
1734	/** The number of user nodes we've allocated. */
1735	uint16_t cMaxPhysExts;
1736	/** Pointer to the array of physical xref extent - RC pointer. */
1737	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1738	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1739	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1740	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1741	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1742	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1743	#ifdef PGMPOOL_WITH_CACHE
1744	/** Hash table for GCPhys addresses. */
1745	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1746	/** The head of the age list. */
1747	uint16_t iAgeHead;
1748	/** The tail of the age list. */
1749	uint16_t iAgeTail;
1750	/** Set if the cache is enabled. */
1751	bool fCacheEnabled;
1752	#endif /* PGMPOOL_WITH_CACHE */
1753	#ifdef PGMPOOL_WITH_MONITORING
1754	/** Head of the list of modified pages. */
1755	uint16_t iModifiedHead;
1756	/** The current number of modified pages. */
1757	uint16_t cModifiedPages;
1758	/** Access handler, RC. */
1759	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1760	/** Access handler, R0. */
1761	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1762	/** Access handler, R3. */
1763	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1764	/** The access handler description (HC ptr). */
1765	R3PTRTYPE(const char *) pszAccessHandler;
1766	#endif /* PGMPOOL_WITH_MONITORING */
1767	/** The number of pages currently in use. */
1768	uint16_t cUsedPages;
1769	#ifdef VBOX_WITH_STATISTICS
1770	/** The high wather mark for cUsedPages. */
1771	uint16_t cUsedPagesHigh;
1772	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1773	/** Profiling pgmPoolAlloc(). */
1774	STAMPROFILEADV StatAlloc;
1775	/** Profiling pgmPoolClearAll(). */
1776	STAMPROFILE StatClearAll;
1777	/** Profiling pgmPoolFlushAllInt(). */
1778	STAMPROFILE StatFlushAllInt;
1779	/** Profiling pgmPoolFlushPage(). */
1780	STAMPROFILE StatFlushPage;
1781	/** Profiling pgmPoolFree(). */
1782	STAMPROFILE StatFree;
1783	/** Profiling time spent zeroing pages. */
1784	STAMPROFILE StatZeroPage;
1785	# ifdef PGMPOOL_WITH_USER_TRACKING
1786	/** Profiling of pgmPoolTrackDeref. */
1787	STAMPROFILE StatTrackDeref;
1788	/** Profiling pgmTrackFlushGCPhysPT. */
1789	STAMPROFILE StatTrackFlushGCPhysPT;
1790	/** Profiling pgmTrackFlushGCPhysPTs. */
1791	STAMPROFILE StatTrackFlushGCPhysPTs;
1792	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1793	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1794	/** Number of times we've been out of user records. */
1795	STAMCOUNTER StatTrackFreeUpOneUser;
1796	# endif
1797	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1798	/** Profiling deref activity related tracking GC physical pages. */
1799	STAMPROFILE StatTrackDerefGCPhys;
1800	/** Number of linear searches for a HCPhys in the ram ranges. */
1801	STAMCOUNTER StatTrackLinearRamSearches;
1802	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1803	STAMCOUNTER StamTrackPhysExtAllocFailures;
1804	# endif
1805	# ifdef PGMPOOL_WITH_MONITORING
1806	/** Profiling the RC/R0 access handler. */
1807	STAMPROFILE StatMonitorRZ;
1808	/** Times we've failed interpreting the instruction. */
1809	STAMCOUNTER StatMonitorRZEmulateInstr;
1810	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1811	STAMPROFILE StatMonitorRZFlushPage;
1812	/** Times we've detected fork(). */
1813	STAMCOUNTER StatMonitorRZFork;
1814	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1815	STAMPROFILE StatMonitorRZHandled;
1816	/** Times we've failed interpreting a patch code instruction. */
1817	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1818	/** Times we've failed interpreting a patch code instruction during flushing. */
1819	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1820	/** The number of times we've seen rep prefixes we can't handle. */
1821	STAMCOUNTER StatMonitorRZRepPrefix;
1822	/** Profiling the REP STOSD cases we've handled. */
1823	STAMPROFILE StatMonitorRZRepStosd;
1824
1825	/** Profiling the R3 access handler. */
1826	STAMPROFILE StatMonitorR3;
1827	/** Times we've failed interpreting the instruction. */
1828	STAMCOUNTER StatMonitorR3EmulateInstr;
1829	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1830	STAMPROFILE StatMonitorR3FlushPage;
1831	/** Times we've detected fork(). */
1832	STAMCOUNTER StatMonitorR3Fork;
1833	/** Profiling the R3 access we've handled (except REP STOSD). */
1834	STAMPROFILE StatMonitorR3Handled;
1835	/** The number of times we've seen rep prefixes we can't handle. */
1836	STAMCOUNTER StatMonitorR3RepPrefix;
1837	/** Profiling the REP STOSD cases we've handled. */
1838	STAMPROFILE StatMonitorR3RepStosd;
1839	/** The number of times we're called in an async thread an need to flush. */
1840	STAMCOUNTER StatMonitorR3Async;
1841	/** The high wather mark for cModifiedPages. */
1842	uint16_t cModifiedPagesHigh;
1843	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1844	# endif
1845	# ifdef PGMPOOL_WITH_CACHE
1846	/** The number of cache hits. */
1847	STAMCOUNTER StatCacheHits;
1848	/** The number of cache misses. */
1849	STAMCOUNTER StatCacheMisses;
1850	/** The number of times we've got a conflict of 'kind' in the cache. */
1851	STAMCOUNTER StatCacheKindMismatches;
1852	/** Number of times we've been out of pages. */
1853	STAMCOUNTER StatCacheFreeUpOne;
1854	/** The number of cacheable allocations. */
1855	STAMCOUNTER StatCacheCacheable;
1856	/** The number of uncacheable allocations. */
1857	STAMCOUNTER StatCacheUncacheable;
1858	# endif
1859	#elif HC_ARCH_BITS == 64
1860	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1861	#endif
1862	/** The AVL tree for looking up a page by its HC physical address. */
1863	AVLOHCPHYSTREE HCPhysTree;
1864	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1865	/** Array of pages. (cMaxPages in length)
1866	* The Id is the index into thist array.
1867	*/
1868	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1869	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1870
1871
1872	/** @def PGMPOOL_PAGE_2_PTR
1873	* Maps a pool page pool into the current context.
1874	*
1875	* @returns VBox status code.
1876	* @param pVM The VM handle.
1877	* @param pPage The pool page.
1878	*
1879	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1880	* small page window employeed by that function. Be careful.
1881	* @remark There is no need to assert on the result.
1882	*/
1883	#if defined(IN_RC)
1884	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1885	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1886	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1887	#elif defined(VBOX_STRICT)
1888	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1889	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1890	{
1891	Assert(pPage->pvPageR3);
1892	return pPage->pvPageR3;
1893	}
1894	#else
1895	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1896	#endif
1897
1898	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1899	* Maps a pool page pool into the current context.
1900	*
1901	* @returns VBox status code.
1902	* @param pPGM Pointer to the PGM instance data.
1903	* @param pPage The pool page.
1904	*
1905	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1906	* small page window employeed by that function. Be careful.
1907	* @remark There is no need to assert on the result.
1908	*/
1909	#if defined(IN_RC)
1910	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1911	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1912	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1913	#else
1914	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1915	#endif
1916
1917
1918	/** @name Per guest page tracking data.
1919	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1920	* is to use more bits for it and split it up later on. But for now we'll play
1921	* safe and change as little as possible.
1922	*
1923	* The 16-bit word has two parts:
1924	*
1925	* The first 14-bit forms the @a idx field. It is either the index of a page in
1926	* the shadow page pool, or and index into the extent list.
1927	*
1928	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
1929	* shadow page pool references to the page. If cRefs equals
1930	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1931	* (misnomer) table and not the shadow page pool.
1932	*
1933	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1934	* the 16-bit word.
1935	*
1936	* @{ */
1937	/** The shift count for getting to the cRefs part. */
1938	#define PGMPOOL_TD_CREFS_SHIFT 14
1939	/** The mask applied after shifting the tracking data down by
1940	* PGMPOOL_TD_CREFS_SHIFT. */
1941	#define PGMPOOL_TD_CREFS_MASK 0x3
1942	/** The cRef value used to indiciate that the idx is the head of a
1943	* physical cross reference list. */
1944	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1945	/** The shift used to get idx. */
1946	#define PGMPOOL_TD_IDX_SHIFT 0
1947	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1948	#define PGMPOOL_TD_IDX_MASK 0x3fff
1949	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1950	* simply too many mappings of this page. */
1951	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1952
1953	/** @def PGMPOOL_TD_MAKE
1954	* Makes a 16-bit tracking data word.
1955	*
1956	* @returns tracking data.
1957	* @param cRefs The @a cRefs field. Must be within bounds!
1958	* @param idx The @a idx field. Must also be within bounds! */
1959	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
1960
1961	/** @def PGMPOOL_TD_GET_CREFS
1962	* Get the @a cRefs field from a tracking data word.
1963	*
1964	* @returns The @a cRefs field
1965	* @param u16 The tracking data word. */
1966	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1967
1968	/** @def PGMPOOL_TD_GET_IDX
1969	* Get the @a idx field from a tracking data word.
1970	*
1971	* @returns The @a idx field
1972	* @param u16 The tracking data word. */
1973	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1974	/** @} */
1975
1976
1977	/**
1978	* Trees are using self relative offsets as pointers.
1979	* So, all its data, including the root pointer, must be in the heap for HC and GC
1980	* to have the same layout.
1981	*/
1982	typedef struct PGMTREES
1983	{
1984	/** Physical access handlers (AVL range+offsetptr tree). */
1985	AVLROGCPHYSTREE PhysHandlers;
1986	/** Virtual access handlers (AVL range + GC ptr tree). */
1987	AVLROGCPTRTREE VirtHandlers;
1988	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1989	AVLROGCPHYSTREE PhysToVirtHandlers;
1990	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1991	AVLROGCPTRTREE HyperVirtHandlers;
1992	} PGMTREES;
1993	/** Pointer to PGM trees. */
1994	typedef PGMTREES *PPGMTREES;
1995
1996
1997	/** @name Paging mode macros
1998	* @{ */
1999	#ifdef IN_RC
2000	# define PGM_CTX(a,b) a##RC##b
2001	# define PGM_CTX_STR(a,b) a "GC" b
2002	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2003	#else
2004	# ifdef IN_RING3
2005	# define PGM_CTX(a,b) a##R3##b
2006	# define PGM_CTX_STR(a,b) a "R3" b
2007	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2008	# else
2009	# define PGM_CTX(a,b) a##R0##b
2010	# define PGM_CTX_STR(a,b) a "R0" b
2011	# define PGM_CTX_DECL(type) VMMDECL(type)
2012	# endif
2013	#endif
2014
2015	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2016	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2017	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2018	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2019	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2020	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2021	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2022	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2023	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2024	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2025	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2026	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2027	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2028	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2029	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2030	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2031	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2032
2033	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2034	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2035	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2036	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2037	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2038	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2039	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2040	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2041	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2042	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2043	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2044	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2045	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2046	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2047	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2048	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2049	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2050
2051	/* Shw_Gst */
2052	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2053	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2054	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2055	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2056	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2057	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2058	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2059	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2060	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2061	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2062	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2063	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2064	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2065	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2066	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2067	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2068	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2069	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2070	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2071
2072	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2073	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2074	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2075	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2076	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2077	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2078	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2079	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2080	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2081	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2082	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2083	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2084	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2085	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2086	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2087	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2088	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2089	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2090	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2091	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2092	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2093	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2094	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2095	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2096	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2097	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2098	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2099	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2100	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2101	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2102	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2103	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2104	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2105	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2106	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2107	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2108	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2109
2110	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2111	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2112	/** @} */
2113
2114	/**
2115	* Data for each paging mode.
2116	*/
2117	typedef struct PGMMODEDATA
2118	{
2119	/** The guest mode type. */
2120	uint32_t uGstType;
2121	/** The shadow mode type. */
2122	uint32_t uShwType;
2123
2124	/** @name Function pointers for Shadow paging.
2125	* @{
2126	*/
2127	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2128	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2129	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2130	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2131
2132	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2133	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2134
2135	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2136	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2137	/** @} */
2138
2139	/** @name Function pointers for Guest paging.
2140	* @{
2141	*/
2142	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2143	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2144	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2145	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2146	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2147	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2148	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2149	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2150	#endif
2151	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2152	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2153	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2154	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2155	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2156	#endif
2157	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2158	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2159	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2160	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2161	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2162	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2163	#endif
2164	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2165	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2166	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2167	#endif
2168	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2169	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2170	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2171	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2172	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2173	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2174	#endif
2175	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2176	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2177	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2178	#endif
2179	/** @} */
2180
2181	/** @name Function pointers for Both Shadow and Guest paging.
2182	* @{
2183	*/
2184	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2185	/* no pfnR3BthTrap0eHandler */
2186	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2187	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2188	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2189	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2190	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2191	#ifdef VBOX_STRICT
2192	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2193	#endif
2194	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2195	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2196
2197	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2198	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2199	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2200	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2201	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2202	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2203	#ifdef VBOX_STRICT
2204	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2205	#endif
2206	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2207	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2208
2209	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2210	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2211	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2212	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2213	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2214	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2215	#ifdef VBOX_STRICT
2216	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2217	#endif
2218	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2219	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2220	/** @} */
2221	} PGMMODEDATA, *PPGMMODEDATA;
2222
2223
2224
2225	/**
2226	* Converts a PGM pointer into a VM pointer.
2227	* @returns Pointer to the VM structure the PGM is part of.
2228	* @param pPGM Pointer to PGM instance data.
2229	*/
2230	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2231
2232	/**
2233	* PGM Data (part of VM)
2234	*/
2235	typedef struct PGM
2236	{
2237	/** Offset to the VM structure. */
2238	RTINT offVM;
2239	/** Offset of the PGMCPU structure relative to VMCPU. */
2240	int32_t offVCpu;
2241	/** Alignment padding. */
2242	int32_t i32Alignment;
2243
2244	/*
2245	* This will be redefined at least two more times before we're done, I'm sure.
2246	* The current code is only to get on with the coding.
2247	* - 2004-06-10: initial version, bird.
2248	* - 2004-07-02: 1st time, bird.
2249	* - 2004-10-18: 2nd time, bird.
2250	* - 2005-07-xx: 3rd time, bird.
2251	*/
2252
2253	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2254	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2255	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2256	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2257
2258	/** The host paging mode. (This is what SUPLib reports.) */
2259	SUPPAGINGMODE enmHostMode;
2260	/** The shadow paging mode. */
2261	PGMMODE enmShadowMode;
2262	/** The guest paging mode. */
2263	PGMMODE enmGuestMode;
2264
2265	/** The current physical address representing in the guest CR3 register. */
2266	RTGCPHYS GCPhysCR3;
2267	/** Pointer to the 5 page CR3 content mapping.
2268	* The first page is always the CR3 (in some form) while the 4 other pages
2269	* are used of the PDs in PAE mode. */
2270	RTGCPTR GCPtrCR3Mapping;
2271	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2272	uint32_t u32Alignment;
2273	#endif
2274	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2275	/** The physical address of the currently monitored guest CR3 page.
2276	* When this value is NIL_RTGCPHYS no page is being monitored. */
2277	RTGCPHYS GCPhysGstCR3Monitored;
2278	#endif
2279	/** @name 32-bit Guest Paging.
2280	* @{ */
2281	/** The guest's page directory, R3 pointer. */
2282	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2283	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2284	/** The guest's page directory, R0 pointer. */
2285	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2286	#endif
2287	/** The guest's page directory, static RC mapping. */
2288	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2289	/** @} */
2290
2291	/** @name PAE Guest Paging.
2292	* @{ */
2293	/** The guest's page directory pointer table, static RC mapping. */
2294	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2295	/** The guest's page directory pointer table, R3 pointer. */
2296	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2297	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2298	/** The guest's page directory pointer table, R0 pointer. */
2299	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2300	#endif
2301
2302	/** The guest's page directories, R3 pointers.
2303	* These are individual pointers and don't have to be adjecent.
2304	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2305	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2306	/** The guest's page directories, R0 pointers.
2307	* Same restrictions as apGstPaePDsR3. */
2308	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2309	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2310	#endif
2311	/** The guest's page directories, static GC mapping.
2312	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2313	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2314	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2315	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2316	RTGCPHYS aGCPhysGstPaePDs[4];
2317	/** The physical addresses of the monitored guest page directories (PAE). */
2318	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2319	/** @} */
2320
2321	/** @name AMD64 Guest Paging.
2322	* @{ */
2323	/** The guest's page directory pointer table, R3 pointer. */
2324	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2325	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2326	/** The guest's page directory pointer table, R0 pointer. */
2327	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2328	#endif
2329	/** @} */
2330
2331	/** @name Shadow paging
2332	* @{ */
2333	/** The root page table - R3 Ptr. */
2334	R3PTRTYPE(void *) pShwRootR3;
2335	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2336	/** The root page table - R0 Ptr. */
2337	R0PTRTYPE(void *) pShwRootR0;
2338	# endif
2339	/** The root page table - RC Ptr. */
2340	RCPTRTYPE(void *) pShwRootRC;
2341	# if HC_ARCH_BITS == 64
2342	uint32_t u32Padding1; /*< alignment padding. /
2343	# endif
2344	/** The Physical Address (HC) of the current active shadow CR3. */
2345	RTHCPHYS HCPhysShwCR3;
2346	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2347	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2348	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2349	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2350	/** Pointer to the page of the current active CR3 - RC Ptr. */
2351	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2352	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2353	uint32_t iShwUser;
2354	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2355	uint32_t iShwUserTable;
2356	# if HC_ARCH_BITS == 64
2357	RTRCPTR alignment6; /*< structure size alignment. /
2358	# endif
2359	/** @} */
2360	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2361	/** @name 32-bit Shadow Paging
2362	* @{ */
2363	/** The 32-Bit PD - R3 Ptr. */
2364	R3PTRTYPE(PX86PD) pShw32BitPdR3;
2365	/** The 32-Bit PD - R0 Ptr. */
2366	R0PTRTYPE(PX86PD) pShw32BitPdR0;
2367	/** The 32-Bit PD - RC Ptr. */
2368	RCPTRTYPE(PX86PD) pShw32BitPdRC;
2369	# if HC_ARCH_BITS == 64
2370	uint32_t u32Padding10; /*< alignment padding. /
2371	# endif
2372	/** The Physical Address (HC) of the 32-Bit PD. */
2373	RTHCPHYS HCPhysShw32BitPD;
2374	/** @} */
2375
2376	/** @name PAE Shadow Paging
2377	* @{ */
2378	/** The four PDs for the low 4GB - R3 Ptr.
2379	* Even though these are 4 pointers, what they point at is a single table.
2380	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2381	R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2382	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2383	/** The four PDs for the low 4GB - R0 Ptr.
2384	* Same kind of mapping as apHCPaePDs. */
2385	R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2386	# endif
2387	/** The four PDs for the low 4GB - RC Ptr.
2388	* Same kind of mapping as apHCPaePDs. */
2389	RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2390	/** The Physical Address (HC) of the four PDs for the low 4GB.
2391	* These are NOT 4 contiguous pages. */
2392	RTHCPHYS aHCPhysPaePDs[4];
2393	/** The Physical Address (HC) of the PAE PDPT. */
2394	RTHCPHYS HCPhysShwPaePdpt;
2395	/** The PAE PDPT - R3 Ptr. */
2396	R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2397	/** The PAE PDPT - R0 Ptr. */
2398	R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2399	/** The PAE PDPT - RC Ptr. */
2400	RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2401	/** @} */
2402	# if HC_ARCH_BITS == 64
2403	RTRCPTR alignment5; /*< structure size alignment. /
2404	# endif
2405	#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2406	/** @name Nested Shadow Paging
2407	* @{ */
2408	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2409	RTR3PTR pShwNestedRootR3;
2410	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2411	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2412	RTR0PTR pShwNestedRootR0;
2413	# endif
2414	/** The Physical Address (HC) of the nested paging root. */
2415	RTHCPHYS HCPhysShwNestedRoot;
2416	/** @} */
2417
2418	/** @name Function pointers for Shadow paging.
2419	* @{
2420	*/
2421	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2422	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2423	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2424	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2425
2426	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2427	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2428
2429	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2430	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2431
2432	/** @} */
2433
2434	/** @name Function pointers for Guest paging.
2435	* @{
2436	*/
2437	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2438	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2439	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2440	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2441	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2442	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2443	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2444	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2445	#endif
2446	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2447	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2448	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2449	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2450	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2451	#endif
2452	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2453	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2454	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2455	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2456	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2457	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2458	#endif
2459	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2460	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2461	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2462	#endif
2463	#if HC_ARCH_BITS == 64
2464	RTRCPTR alignment3; /*< structure size alignment. /
2465	#endif
2466
2467	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2468	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2469	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2470	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2471	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2472	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2473	#endif
2474	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2475	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2476	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2477	#endif
2478	/** @} */
2479
2480	/** @name Function pointers for Both Shadow and Guest paging.
2481	* @{
2482	*/
2483	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2484	/* no pfnR3BthTrap0eHandler */
2485	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2486	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2487	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2488	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2489	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2490	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2491	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2492	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2493
2494	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2495	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2496	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2497	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2498	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2499	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2500	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2501	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2502	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2503
2504	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2505	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2506	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2507	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2508	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2509	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2510	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2511	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2512	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2513	#if HC_ARCH_BITS == 64
2514	RTRCPTR alignment2; /*< structure size alignment. /
2515	#endif
2516	/** @} */
2517
2518	/** Pointer to SHW+GST mode data (function pointers).
2519	* The index into this table is made up from */
2520	R3PTRTYPE(PPGMMODEDATA) paModeData;
2521
2522	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2523	* This is sorted by physical address and contains no overlapping ranges. */
2524	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2525	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2526	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2527	/** RC pointer corresponding to PGM::pRamRangesR3. */
2528	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2529	/** The configured RAM size. */
2530	RTUINT cbRamSize;
2531
2532	/** Pointer to the list of ROM ranges - for R3.
2533	* This is sorted by physical address and contains no overlapping ranges. */
2534	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2535	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2536	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2537	/** RC pointer corresponding to PGM::pRomRangesR3. */
2538	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2539	/** Alignment padding. */
2540	RTRCPTR GCPtrPadding2;
2541
2542	/** Pointer to the list of MMIO2 ranges - for R3.
2543	* Registration order. */
2544	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2545
2546	/** PGM offset based trees - R3 Ptr. */
2547	R3PTRTYPE(PPGMTREES) pTreesR3;
2548	/** PGM offset based trees - R0 Ptr. */
2549	R0PTRTYPE(PPGMTREES) pTreesR0;
2550	/** PGM offset based trees - RC Ptr. */
2551	RCPTRTYPE(PPGMTREES) pTreesRC;
2552
2553	/** Linked list of GC mappings - for RC.
2554	* The list is sorted ascending on address.
2555	*/
2556	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2557	/** Linked list of GC mappings - for HC.
2558	* The list is sorted ascending on address.
2559	*/
2560	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2561	/** Linked list of GC mappings - for R0.
2562	* The list is sorted ascending on address.
2563	*/
2564	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2565
2566	/** Indicates that PGMR3FinalizeMappings has been called and that further
2567	* PGMR3MapIntermediate calls will be rejected. */
2568	bool fFinalizedMappings;
2569	/** If set no conflict checks are required. (boolean) */
2570	bool fMappingsFixed;
2571	/** If set, then no mappings are put into the shadow page table. (boolean) */
2572	bool fDisableMappings;
2573	/** Size of fixed mapping */
2574	uint32_t cbMappingFixed;
2575	/** Base address (GC) of fixed mapping */
2576	RTGCPTR GCPtrMappingFixed;
2577	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2578	uint32_t u32Padding0; /*< alignment padding. /
2579	#endif
2580
2581
2582	/** @name Intermediate Context
2583	* @{ */
2584	/** Pointer to the intermediate page directory - Normal. */
2585	R3PTRTYPE(PX86PD) pInterPD;
2586	/** Pointer to the intermedate page tables - Normal.
2587	* There are two page tables, one for the identity mapping and one for
2588	* the host context mapping (of the core code). */
2589	R3PTRTYPE(PX86PT) apInterPTs[2];
2590	/** Pointer to the intermedate page tables - PAE. */
2591	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2592	/** Pointer to the intermedate page directory - PAE. */
2593	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2594	/** Pointer to the intermedate page directory - PAE. */
2595	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2596	/** Pointer to the intermedate page-map level 4 - AMD64. */
2597	R3PTRTYPE(PX86PML4) pInterPaePML4;
2598	/** Pointer to the intermedate page directory - AMD64. */
2599	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2600	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2601	RTHCPHYS HCPhysInterPD;
2602	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2603	RTHCPHYS HCPhysInterPaePDPT;
2604	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2605	RTHCPHYS HCPhysInterPaePML4;
2606	/** @} */
2607
2608	/** Base address of the dynamic page mapping area.
2609	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2610	*/
2611	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2612	/** The index of the last entry used in the dynamic page mapping area. */
2613	RTUINT iDynPageMapLast;
2614	/** Cache containing the last entries in the dynamic page mapping area.
2615	* The cache size is covering half of the mapping area. */
2616	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2617
2618	/** The address of the ring-0 mapping cache if we're making use of it. */
2619	RTR0PTR pvR0DynMapUsed;
2620	#if HC_ARCH_BITS == 32
2621	RTR0PTR R0PtrPadding0; /*< Alignment. /
2622	#endif
2623
2624
2625	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2626	RTGCPHYS GCPhys4MBPSEMask;
2627
2628	/** A20 gate mask.
2629	* Our current approach to A20 emulation is to let REM do it and don't bother
2630	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2631	* But whould need arrise, we'll subject physical addresses to this mask. */
2632	RTGCPHYS GCPhysA20Mask;
2633	/** A20 gate state - boolean! */
2634	RTUINT fA20Enabled;
2635
2636	/** What needs syncing (PGM_SYNC_*).
2637	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2638	* PGMFlushTLB, and PGMR3Load. */
2639	RTUINT fSyncFlags;
2640
2641	/** PGM critical section.
2642	* This protects the physical & virtual access handlers, ram ranges,
2643	* and the page flag updating (some of it anyway).
2644	*/
2645	PDMCRITSECT CritSect;
2646
2647	/** Shadow Page Pool - R3 Ptr. */
2648	R3PTRTYPE(PPGMPOOL) pPoolR3;
2649	/** Shadow Page Pool - R0 Ptr. */
2650	R0PTRTYPE(PPGMPOOL) pPoolR0;
2651	/** Shadow Page Pool - RC Ptr. */
2652	RCPTRTYPE(PPGMPOOL) pPoolRC;
2653
2654	/** We're not in a state which permits writes to guest memory.
2655	* (Only used in strict builds.) */
2656	bool fNoMorePhysWrites;
2657
2658	/** Flush the cache on the next access. */
2659	bool fPhysCacheFlushPending;
2660	/** @todo r=bird: Fix member names!*/
2661	/** PGMPhysRead cache */
2662	PGMPHYSCACHE pgmphysreadcache;
2663	/** PGMPhysWrite cache */
2664	PGMPHYSCACHE pgmphyswritecache;
2665
2666	/**
2667	* Data associated with managing the ring-3 mappings of the allocation chunks.
2668	*/
2669	struct
2670	{
2671	/** The chunk tree, ordered by chunk id. */
2672	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2673	R3PTRTYPE(PAVLU32NODECORE) pTree;
2674	#else
2675	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2676	#endif
2677	/** The chunk mapping TLB. */
2678	PGMCHUNKR3MAPTLB Tlb;
2679	/** The number of mapped chunks. */
2680	uint32_t c;
2681	/** The maximum number of mapped chunks.
2682	* @cfgm PGM/MaxRing3Chunks */
2683	uint32_t cMax;
2684	/** The chunk age tree, ordered by ageing sequence number. */
2685	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2686	/** The current time. */
2687	uint32_t iNow;
2688	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2689	uint32_t AgeingCountdown;
2690	} ChunkR3Map;
2691
2692	/**
2693	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2694	*/
2695	PGMPAGER3MAPTLB PhysTlbHC;
2696
2697	/** @name The zero page.
2698	* @{ */
2699	/** The host physical address of the zero page. */
2700	RTHCPHYS HCPhysZeroPg;
2701	/** The ring-3 mapping of the zero page. */
2702	RTR3PTR pvZeroPgR3;
2703	/** The ring-0 mapping of the zero page. */
2704	RTR0PTR pvZeroPgR0;
2705	/** The GC mapping of the zero page. */
2706	RTGCPTR pvZeroPgGC;
2707	#if GC_ARCH_BITS != 32
2708	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2709	#endif
2710	/** @}*/
2711
2712	/** The number of handy pages. */
2713	uint32_t cHandyPages;
2714	/**
2715	* Array of handy pages.
2716	*
2717	* This array is used in a two way communication between pgmPhysAllocPage
2718	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2719	* an intermediary.
2720	*
2721	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2722	* (The current size of 32 pages, means 128 KB of handy memory.)
2723	*/
2724	GMMPAGEDESC aHandyPages[32];
2725
2726	/** @name Release Statistics
2727	* @{ */
2728	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2729	uint32_t cPrivatePages; /*< The number of private pages. /
2730	uint32_t cSharedPages; /*< The number of shared pages. /
2731	uint32_t cZeroPages; /*< The number of zero backed pages. /
2732	/** The number of times the guest has switched mode since last reset or statistics reset. */
2733	STAMCOUNTER cGuestModeChanges;
2734	/** The number of times we were forced to change the hypervisor region location. */
2735	STAMCOUNTER cRelocations;
2736	/** @} */
2737
2738	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2739	/** RC: Which statistic this \#PF should be attributed to. */
2740	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2741	RTRCPTR padding0;
2742	/** R0: Which statistic this \#PF should be attributed to. */
2743	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2744	RTR0PTR padding1;
2745
2746	/* Common */
2747	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2748	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2749	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2750	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2751	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2752	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2753	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2754	# endif
2755	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2756	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2757
2758	/* R3 only: */
2759	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2760	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2761	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2762	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2763	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2764	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2765
2766	/* R0 only: */
2767	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2768	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2769	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2770	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2771	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2772	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2773	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2774	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2775	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2776	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2777	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2778	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2779	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2780	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2781	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2782	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2783	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2784	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2785	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2786	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2787	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2788	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2789	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2790	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2791	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2792	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2793
2794	/* RC only: */
2795	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2796	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2797	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2798	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2799
2800	/* RZ only: */
2801	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2802	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2803	STAMPROFILE StatRZTrap0eTimeSyncPT;
2804	STAMPROFILE StatRZTrap0eTimeMapping;
2805	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2806	STAMPROFILE StatRZTrap0eTimeHandlers;
2807	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2808	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2809	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2810	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2811	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2812	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2813	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2814	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2815	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2816	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2817	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2818	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2819	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2820	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2821	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2822	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2823	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2824	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2825	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2826	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2827	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2828	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2829	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2830	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2831	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2832	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2833	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2834	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2835	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2836	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2837	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2838	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2839	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2840	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2841	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2842	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2843	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2844	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2845	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2846	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2847	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2848	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2849	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2850
2851	/* HC - R3 and (maybe) R0: */
2852
2853	/* RZ & R3: */
2854	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2855	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2856	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2857	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2858	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2859	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2860	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2861	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2862	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2863	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2864	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2865	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2866	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2867	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2868	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2869	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2870	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2871	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2872	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2873	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2874	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2875	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2876	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2877	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2878	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2879	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2880	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2881	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2882	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2883	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2884	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2885	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2886	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2887	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2888	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2889	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2890	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2891	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2892	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2893	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2894	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2895	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2896	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2897	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2898	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2899	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2900	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2901	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2902	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2903	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2904	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2905	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2906	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2907	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2908
2909	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2910	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2911	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2912	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2913	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2914	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2915	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2916	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2917	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2918	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2919	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2920	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2921	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2922	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2923	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2924	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2925	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2926	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2927	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2928	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2929	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2930	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2931	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2932	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2933	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2934	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2935	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2936	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2937	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2938	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2939	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2940	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2941	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2942	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2943	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2944	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2945	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2946	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2947	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2948	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2949	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2950	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2951	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2952	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2953	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2954	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2955	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2956	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2957	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2958	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2959	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2960	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2961	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2962	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2963	#endif /* VBOX_WITH_STATISTICS */
2964	} PGM;
2965	/** Pointer to the PGM instance data. */
2966	typedef PGM *PPGM;
2967
2968
2969	/**
2970	* PGMCPU Data (part of VMCPU).
2971	*/
2972	typedef struct PGMCPU
2973	{
2974	/** Offset to the VMCPU structure. */
2975	RTINT offVMCPU;
2976	/** Automatically tracked physical memory mapping set.
2977	* Ring-0 and strict raw-mode builds. */
2978	PGMMAPSET AutoSet;
2979	} PGMCPU;
2980	/** Pointer to the per-cpu PGM data. */
2981	typedef PGMCPU *PPGMCPU;
2982
2983
2984	/** @name PGM::fSyncFlags Flags
2985	* @{
2986	*/
2987	/** Updates the virtual access handler state bit in PGMPAGE. */
2988	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2989	/** Always sync CR3. */
2990	#define PGM_SYNC_ALWAYS RT_BIT(1)
2991	/** Check monitoring on next CR3 (re)load and invalidate page. */
2992	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2993	/** Check guest mapping in SyncCR3. */
2994	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2995	/** Clear the page pool (a light weight flush). */
2996	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2997	/** @} */
2998
2999
3000	__BEGIN_DECLS
3001
3002	int pgmLock(PVM pVM);
3003	void pgmUnlock(PVM pVM);
3004
3005	VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
3006	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
3007
3008	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3009	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3010	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3011	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3012	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3013
3014	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3015	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3016	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3017	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3018	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3019	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3020	#else
3021	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3022	#endif
3023	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3024
3025
3026	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3027	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3028	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3029	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3030	#ifdef IN_RING3
3031	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3032	int pgmR3PhysRamReset(PVM pVM);
3033	int pgmR3PhysRomReset(PVM pVM);
3034	# ifndef VBOX_WITH_NEW_PHYS_CODE
3035	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3036	# endif
3037
3038	int pgmR3PoolInit(PVM pVM);
3039	void pgmR3PoolRelocate(PVM pVM);
3040	void pgmR3PoolReset(PVM pVM);
3041
3042	#endif /* IN_RING3 */
3043	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3044	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3045	#endif
3046	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3047	void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3048	#endif
3049	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3050	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3051	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3052	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3053	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3054	void pgmPoolFlushAll(PVM pVM);
3055	void pgmPoolClearAll(PVM pVM);
3056	int pgmPoolSyncCR3(PVM pVM);
3057	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3058	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3059	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3060	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3061	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3062	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3063	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3064	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3065	#ifdef PGMPOOL_WITH_MONITORING
3066	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3067	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3068	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3069	void pgmPoolMonitorModifiedClearAll(PVM pVM);
3070	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3071	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3072	#endif
3073
3074	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3075	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3076	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3077	int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3078	#endif
3079	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3080	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3081
3082	#ifndef IN_RC
3083	int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3084	#endif
3085	int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3086
3087	__END_DECLS
3088
3089
3090	/**
3091	* Gets the PGMRAMRANGE structure for a guest page.
3092	*
3093	* @returns Pointer to the RAM range on success.
3094	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3095	*
3096	* @param pPGM PGM handle.
3097	* @param GCPhys The GC physical address.
3098	*/
3099	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3100	{
3101	/*
3102	* Optimize for the first range.
3103	*/
3104	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3105	RTGCPHYS off = GCPhys - pRam->GCPhys;
3106	if (RT_UNLIKELY(off >= pRam->cb))
3107	{
3108	do
3109	{
3110	pRam = pRam->CTX_SUFF(pNext);
3111	if (RT_UNLIKELY(!pRam))
3112	break;
3113	off = GCPhys - pRam->GCPhys;
3114	} while (off >= pRam->cb);
3115	}
3116	return pRam;
3117	}
3118
3119
3120	/**
3121	* Gets the PGMPAGE structure for a guest page.
3122	*
3123	* @returns Pointer to the page on success.
3124	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3125	*
3126	* @param pPGM PGM handle.
3127	* @param GCPhys The GC physical address.
3128	*/
3129	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3130	{
3131	/*
3132	* Optimize for the first range.
3133	*/
3134	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3135	RTGCPHYS off = GCPhys - pRam->GCPhys;
3136	if (RT_UNLIKELY(off >= pRam->cb))
3137	{
3138	do
3139	{
3140	pRam = pRam->CTX_SUFF(pNext);
3141	if (RT_UNLIKELY(!pRam))
3142	return NULL;
3143	off = GCPhys - pRam->GCPhys;
3144	} while (off >= pRam->cb);
3145	}
3146	return &pRam->aPages[off >> PAGE_SHIFT];
3147	}
3148
3149
3150	/**
3151	* Gets the PGMPAGE structure for a guest page.
3152	*
3153	* Old Phys code: Will make sure the page is present.
3154	*
3155	* @returns VBox status code.
3156	* @retval VINF_SUCCESS and a valid *ppPage on success.
3157	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3158	*
3159	* @param pPGM PGM handle.
3160	* @param GCPhys The GC physical address.
3161	* @param ppPage Where to store the page poitner on success.
3162	*/
3163	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3164	{
3165	/*
3166	* Optimize for the first range.
3167	*/
3168	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3169	RTGCPHYS off = GCPhys - pRam->GCPhys;
3170	if (RT_UNLIKELY(off >= pRam->cb))
3171	{
3172	do
3173	{
3174	pRam = pRam->CTX_SUFF(pNext);
3175	if (RT_UNLIKELY(!pRam))
3176	{
3177	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3178	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3179	}
3180	off = GCPhys - pRam->GCPhys;
3181	} while (off >= pRam->cb);
3182	}
3183	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3184	#ifndef VBOX_WITH_NEW_PHYS_CODE
3185
3186	/*
3187	* Make sure it's present.
3188	*/
3189	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3190	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3191	{
3192	#ifdef IN_RING3
3193	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3194	#else
3195	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3196	#endif
3197	if (RT_FAILURE(rc))
3198	{
3199	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3200	return rc;
3201	}
3202	Assert(rc == VINF_SUCCESS);
3203	}
3204	#endif
3205	return VINF_SUCCESS;
3206	}
3207
3208
3209
3210
3211	/**
3212	* Gets the PGMPAGE structure for a guest page.
3213	*
3214	* Old Phys code: Will make sure the page is present.
3215	*
3216	* @returns VBox status code.
3217	* @retval VINF_SUCCESS and a valid *ppPage on success.
3218	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3219	*
3220	* @param pPGM PGM handle.
3221	* @param GCPhys The GC physical address.
3222	* @param ppPage Where to store the page poitner on success.
3223	* @param ppRamHint Where to read and store the ram list hint.
3224	* The caller initializes this to NULL before the call.
3225	*/
3226	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3227	{
3228	RTGCPHYS off;
3229	PPGMRAMRANGE pRam = *ppRamHint;
3230	if ( !pRam
3231	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3232	{
3233	pRam = pPGM->CTX_SUFF(pRamRanges);
3234	off = GCPhys - pRam->GCPhys;
3235	if (RT_UNLIKELY(off >= pRam->cb))
3236	{
3237	do
3238	{
3239	pRam = pRam->CTX_SUFF(pNext);
3240	if (RT_UNLIKELY(!pRam))
3241	{
3242	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3243	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3244	}
3245	off = GCPhys - pRam->GCPhys;
3246	} while (off >= pRam->cb);
3247	}
3248	*ppRamHint = pRam;
3249	}
3250	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3251	#ifndef VBOX_WITH_NEW_PHYS_CODE
3252
3253	/*
3254	* Make sure it's present.
3255	*/
3256	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3257	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3258	{
3259	#ifdef IN_RING3
3260	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3261	#else
3262	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3263	#endif
3264	if (RT_FAILURE(rc))
3265	{
3266	ppPage = NULL; / Shut up annoying smart ass. */
3267	return rc;
3268	}
3269	Assert(rc == VINF_SUCCESS);
3270	}
3271	#endif
3272	return VINF_SUCCESS;
3273	}
3274
3275
3276	/**
3277	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3278	*
3279	* @returns Pointer to the page on success.
3280	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3281	*
3282	* @param pPGM PGM handle.
3283	* @param GCPhys The GC physical address.
3284	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3285	*/
3286	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3287	{
3288	/*
3289	* Optimize for the first range.
3290	*/
3291	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3292	RTGCPHYS off = GCPhys - pRam->GCPhys;
3293	if (RT_UNLIKELY(off >= pRam->cb))
3294	{
3295	do
3296	{
3297	pRam = pRam->CTX_SUFF(pNext);
3298	if (RT_UNLIKELY(!pRam))
3299	return NULL;
3300	off = GCPhys - pRam->GCPhys;
3301	} while (off >= pRam->cb);
3302	}
3303	*ppRam = pRam;
3304	return &pRam->aPages[off >> PAGE_SHIFT];
3305	}
3306
3307
3308	/**
3309	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3310	*
3311	* @returns Pointer to the page on success.
3312	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3313	*
3314	* @param pPGM PGM handle.
3315	* @param GCPhys The GC physical address.
3316	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3317	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3318	*/
3319	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3320	{
3321	/*
3322	* Optimize for the first range.
3323	*/
3324	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3325	RTGCPHYS off = GCPhys - pRam->GCPhys;
3326	if (RT_UNLIKELY(off >= pRam->cb))
3327	{
3328	do
3329	{
3330	pRam = pRam->CTX_SUFF(pNext);
3331	if (RT_UNLIKELY(!pRam))
3332	{
3333	ppRam = NULL; / Shut up silly GCC warnings. */
3334	ppPage = NULL; / ditto */
3335	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3336	}
3337	off = GCPhys - pRam->GCPhys;
3338	} while (off >= pRam->cb);
3339	}
3340	*ppRam = pRam;
3341	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3342	#ifndef VBOX_WITH_NEW_PHYS_CODE
3343
3344	/*
3345	* Make sure it's present.
3346	*/
3347	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3348	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3349	{
3350	#ifdef IN_RING3
3351	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3352	#else
3353	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3354	#endif
3355	if (RT_FAILURE(rc))
3356	{
3357	ppPage = NULL; / Shut up silly GCC warnings. */
3358	ppPage = NULL; / ditto */
3359	return rc;
3360	}
3361	Assert(rc == VINF_SUCCESS);
3362
3363	}
3364	#endif
3365	return VINF_SUCCESS;
3366	}
3367
3368
3369	/**
3370	* Convert GC Phys to HC Phys.
3371	*
3372	* @returns VBox status.
3373	* @param pPGM PGM handle.
3374	* @param GCPhys The GC physical address.
3375	* @param pHCPhys Where to store the corresponding HC physical address.
3376	*
3377	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3378	* Avoid when writing new code!
3379	*/
3380	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3381	{
3382	PPGMPAGE pPage;
3383	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3384	if (RT_FAILURE(rc))
3385	return rc;
3386	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3387	return VINF_SUCCESS;
3388	}
3389
3390	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3391
3392	/**
3393	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3394	* optimizes access to pages already in the set.
3395	*
3396	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3397	* @param pPGM Pointer to the PVM instance data.
3398	* @param HCPhys The physical address of the page.
3399	* @param ppv Where to store the mapping address.
3400	*/
3401	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3402	{
3403	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3404	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3405	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3406	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3407
3408	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3409	unsigned iEntry = pSet->aiHashTable[iHash];
3410	if ( iEntry < pSet->cEntries
3411	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3412	{
3413	*ppv = pSet->aEntries[iEntry].pvPage;
3414	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3415	}
3416	else
3417	{
3418	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3419	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3420	}
3421
3422	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3423	return VINF_SUCCESS;
3424	}
3425
3426
3427	/**
3428	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3429	* access to pages already in the set.
3430	*
3431	* @returns See PGMDynMapGCPage.
3432	* @param pPGM Pointer to the PVM instance data.
3433	* @param HCPhys The physical address of the page.
3434	* @param ppv Where to store the mapping address.
3435	*/
3436	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3437	{
3438	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3439	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3440
3441	/*
3442	* Get the ram range.
3443	*/
3444	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3445	RTGCPHYS off = GCPhys - pRam->GCPhys;
3446	if (RT_UNLIKELY(off >= pRam->cb
3447	/** @todo \|\| page state stuff */))
3448	{
3449	/* This case is not counted into StatR0DynMapGCPageInl. */
3450	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3451	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3452	}
3453
3454	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3455	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3456
3457	/*
3458	* pgmR0DynMapHCPageInlined with out stats.
3459	*/
3460	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3461	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3462	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3463
3464	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3465	unsigned iEntry = pSet->aiHashTable[iHash];
3466	if ( iEntry < pSet->cEntries
3467	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3468	{
3469	*ppv = pSet->aEntries[iEntry].pvPage;
3470	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3471	}
3472	else
3473	{
3474	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3475	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3476	}
3477
3478	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3479	return VINF_SUCCESS;
3480	}
3481
3482	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3483
3484	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3485	/**
3486	* Maps the page into current context (RC and maybe R0).
3487	*
3488	* @returns pointer to the mapping.
3489	* @param pVM Pointer to the PGM instance data.
3490	* @param pPage The page.
3491	*/
3492	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3493	{
3494	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3495	{
3496	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3497	void *pv;
3498	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3499	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3500	# else
3501	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3502	# endif
3503	return pv;
3504	}
3505	return pgmPoolMapPageFallback(pPGM, pPage);
3506	}
3507
3508	/**
3509	* Temporarily maps one host page specified by HC physical address, returning
3510	* pointer within the page.
3511	*
3512	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3513	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3514	*
3515	* @returns The address corresponding to HCPhys.
3516	* @param pPGM Pointer to the PVM instance data.
3517	* @param HCPhys HC Physical address of the page.
3518	*/
3519	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3520	{
3521	void *pv;
3522	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3523	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3524	# else
3525	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3526	# endif
3527	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3528	return pv;
3529	}
3530	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3531
3532
3533	#ifndef IN_RC
3534	/**
3535	* Queries the Physical TLB entry for a physical guest page,
3536	* attemting to load the TLB entry if necessary.
3537	*
3538	* @returns VBox status code.
3539	* @retval VINF_SUCCESS on success
3540	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3541	* @param pPGM The PGM instance handle.
3542	* @param GCPhys The address of the guest page.
3543	* @param ppTlbe Where to store the pointer to the TLB entry.
3544	*/
3545
3546	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3547	{
3548	int rc;
3549	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3550	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3551	{
3552	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3553	rc = VINF_SUCCESS;
3554	}
3555	else
3556	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3557	*ppTlbe = pTlbe;
3558	return rc;
3559	}
3560	#endif /* !IN_RC */
3561
3562	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3563
3564	# ifndef VBOX_WITH_NEW_PHYS_CODE
3565	/**
3566	* Convert GC Phys to HC Virt.
3567	*
3568	* @returns VBox status.
3569	* @param pPGM PGM handle.
3570	* @param GCPhys The GC physical address.
3571	* @param pHCPtr Where to store the corresponding HC virtual address.
3572	*
3573	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3574	* pgmPoolMonitorGCPtr2CCPtr.
3575	*/
3576	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3577	{
3578	PPGMRAMRANGE pRam;
3579	PPGMPAGE pPage;
3580	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3581	if (RT_FAILURE(rc))
3582	{
3583	pHCPtr = 0; / Shut up silly GCC warnings. */
3584	return rc;
3585	}
3586	RTGCPHYS off = GCPhys - pRam->GCPhys;
3587
3588	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3589	{
3590	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3591	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3592	return VINF_SUCCESS;
3593	}
3594	if (pRam->pvR3)
3595	{
3596	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3597	return VINF_SUCCESS;
3598	}
3599	pHCPtr = 0; / Shut up silly GCC warnings. */
3600	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3601	}
3602	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3603	#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3604
3605	/**
3606	* Convert GC Phys to HC Virt and HC Phys.
3607	*
3608	* @returns VBox status.
3609	* @param pPGM PGM handle.
3610	* @param GCPhys The GC physical address.
3611	* @param pHCPtr Where to store the corresponding HC virtual address.
3612	* @param pHCPhys Where to store the HC Physical address and its flags.
3613	*
3614	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3615	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3616	*/
3617	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3618	{
3619	PPGMRAMRANGE pRam;
3620	PPGMPAGE pPage;
3621	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3622	if (RT_FAILURE(rc))
3623	{
3624	pHCPtr = 0; / Shut up crappy GCC warnings */
3625	pHCPhys = 0; / ditto */
3626	return rc;
3627	}
3628	RTGCPHYS off = GCPhys - pRam->GCPhys;
3629
3630	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3631	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3632	{
3633	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3634	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3635	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3636	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3637	#else
3638	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3639	#endif
3640	return VINF_SUCCESS;
3641	}
3642	if (pRam->pvR3)
3643	{
3644	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3645	return VINF_SUCCESS;
3646	}
3647	*pHCPtr = 0;
3648	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3649	}
3650
3651
3652	/**
3653	* Clears flags associated with a RAM address.
3654	*
3655	* @returns VBox status code.
3656	* @param pPGM PGM handle.
3657	* @param GCPhys Guest context physical address.
3658	* @param fFlags fFlags to clear. (Bits 0-11.)
3659	*/
3660	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3661	{
3662	PPGMPAGE pPage;
3663	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3664	if (RT_FAILURE(rc))
3665	return rc;
3666
3667	fFlags &= ~X86_PTE_PAE_PG_MASK;
3668	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3669	return VINF_SUCCESS;
3670	}
3671
3672
3673	/**
3674	* Clears flags associated with a RAM address.
3675	*
3676	* @returns VBox status code.
3677	* @param pPGM PGM handle.
3678	* @param GCPhys Guest context physical address.
3679	* @param fFlags fFlags to clear. (Bits 0-11.)
3680	* @param ppRamHint Where to read and store the ram list hint.
3681	* The caller initializes this to NULL before the call.
3682	*/
3683	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3684	{
3685	PPGMPAGE pPage;
3686	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3687	if (RT_FAILURE(rc))
3688	return rc;
3689
3690	fFlags &= ~X86_PTE_PAE_PG_MASK;
3691	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3692	return VINF_SUCCESS;
3693	}
3694
3695
3696	/**
3697	* Sets (bitwise OR) flags associated with a RAM address.
3698	*
3699	* @returns VBox status code.
3700	* @param pPGM PGM handle.
3701	* @param GCPhys Guest context physical address.
3702	* @param fFlags fFlags to set clear. (Bits 0-11.)
3703	*/
3704	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3705	{
3706	PPGMPAGE pPage;
3707	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3708	if (RT_FAILURE(rc))
3709	return rc;
3710
3711	fFlags &= ~X86_PTE_PAE_PG_MASK;
3712	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3713	return VINF_SUCCESS;
3714	}
3715
3716
3717	/**
3718	* Sets (bitwise OR) flags associated with a RAM address.
3719	*
3720	* @returns VBox status code.
3721	* @param pPGM PGM handle.
3722	* @param GCPhys Guest context physical address.
3723	* @param fFlags fFlags to set clear. (Bits 0-11.)
3724	* @param ppRamHint Where to read and store the ram list hint.
3725	* The caller initializes this to NULL before the call.
3726	*/
3727	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3728	{
3729	PPGMPAGE pPage;
3730	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3731	if (RT_FAILURE(rc))
3732	return rc;
3733
3734	fFlags &= ~X86_PTE_PAE_PG_MASK;
3735	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3736	return VINF_SUCCESS;
3737	}
3738
3739
3740	/**
3741	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3742	* Takes PSE-36 into account.
3743	*
3744	* @returns guest physical address
3745	* @param pPGM Pointer to the PGM instance data.
3746	* @param Pde Guest Pde
3747	*/
3748	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3749	{
3750	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3751	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3752
3753	return GCPhys & pPGM->GCPhys4MBPSEMask;
3754	}
3755
3756
3757	/**
3758	* Gets the page directory entry for the specified address (32-bit paging).
3759	*
3760	* @returns The page directory entry in question.
3761	* @param pPGM Pointer to the PGM instance data.
3762	* @param GCPtr The address.
3763	*/
3764	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3765	{
3766	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3767	PCX86PD pGuestPD = 0;
3768	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3769	if (RT_FAILURE(rc))
3770	{
3771	X86PDE ZeroPde = {0};
3772	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3773	}
3774	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3775	#else
3776	return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3777	#endif
3778	}
3779
3780
3781	/**
3782	* Gets the address of a specific page directory entry (32-bit paging).
3783	*
3784	* @returns Pointer the page directory entry in question.
3785	* @param pPGM Pointer to the PGM instance data.
3786	* @param GCPtr The address.
3787	*/
3788	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3789	{
3790	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3791	PX86PD pGuestPD = 0;
3792	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3793	AssertRCReturn(rc, 0);
3794	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3795	#else
3796	return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3797	#endif
3798	}
3799
3800
3801	/**
3802	* Gets the address the guest page directory (32-bit paging).
3803	*
3804	* @returns Pointer the page directory entry in question.
3805	* @param pPGM Pointer to the PGM instance data.
3806	*/
3807	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3808	{
3809	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3810	PX86PD pGuestPD = 0;
3811	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3812	AssertRCReturn(rc, 0);
3813	return pGuestPD;
3814	#else
3815	return pPGM->CTX_SUFF(pGst32BitPd);
3816	#endif
3817	}
3818
3819
3820	/**
3821	* Gets the guest page directory pointer table.
3822	*
3823	* @returns Pointer to the page directory in question.
3824	* @returns NULL if the page directory is not present or on an invalid page.
3825	* @param pPGM Pointer to the PGM instance data.
3826	*/
3827	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3828	{
3829	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3830	PX86PDPT pGuestPDPT = 0;
3831	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3832	AssertRCReturn(rc, 0);
3833	return pGuestPDPT;
3834	#else
3835	return pPGM->CTX_SUFF(pGstPaePdpt);
3836	#endif
3837	}
3838
3839
3840	/**
3841	* Gets the guest page directory pointer table entry for the specified address.
3842	*
3843	* @returns Pointer to the page directory in question.
3844	* @returns NULL if the page directory is not present or on an invalid page.
3845	* @param pPGM Pointer to the PGM instance data.
3846	* @param GCPtr The address.
3847	*/
3848	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3849	{
3850	AssertGCPtr32(GCPtr);
3851
3852	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3853	PX86PDPT pGuestPDPT = 0;
3854	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3855	AssertRCReturn(rc, 0);
3856	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3857	#else
3858	return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3859	#endif
3860	}
3861
3862
3863	/**
3864	* Gets the page directory for the specified address.
3865	*
3866	* @returns Pointer to the page directory in question.
3867	* @returns NULL if the page directory is not present or on an invalid page.
3868	* @param pPGM Pointer to the PGM instance data.
3869	* @param GCPtr The address.
3870	*/
3871	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3872	{
3873	AssertGCPtr32(GCPtr);
3874
3875	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3876	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3877	AssertReturn(pGuestPDPT, 0);
3878	#else
3879	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3880	#endif
3881	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3882	if (pGuestPDPT->a[iPdPt].n.u1Present)
3883	{
3884	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3885	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3886	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3887	#endif
3888
3889	/* cache is out-of-sync. */
3890	PX86PDPAE pPD;
3891	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3892	if (RT_SUCCESS(rc))
3893	return pPD;
3894	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3895	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3896	}
3897	return NULL;
3898	}
3899
3900
3901	/**
3902	* Gets the page directory entry for the specified address.
3903	*
3904	* @returns Pointer to the page directory entry in question.
3905	* @returns NULL if the page directory is not present or on an invalid page.
3906	* @param pPGM Pointer to the PGM instance data.
3907	* @param GCPtr The address.
3908	*/
3909	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3910	{
3911	AssertGCPtr32(GCPtr);
3912
3913	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3914	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3915	AssertReturn(pGuestPDPT, 0);
3916	#else
3917	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3918	#endif
3919	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3920	if (pGuestPDPT->a[iPdPt].n.u1Present)
3921	{
3922	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3923	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3924	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3925	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3926	#endif
3927
3928	/* The cache is out-of-sync. */
3929	PX86PDPAE pPD;
3930	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3931	if (RT_SUCCESS(rc))
3932	return &pPD->a[iPD];
3933	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3934	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3935	}
3936	return NULL;
3937	}
3938
3939
3940	/**
3941	* Gets the page directory entry for the specified address.
3942	*
3943	* @returns The page directory entry in question.
3944	* @returns A non-present entry if the page directory is not present or on an invalid page.
3945	* @param pPGM Pointer to the PGM instance data.
3946	* @param GCPtr The address.
3947	*/
3948	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3949	{
3950	AssertGCPtr32(GCPtr);
3951
3952	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3953	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3954	if (RT_LIKELY(pGuestPDPT))
3955	#else
3956	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3957	#endif
3958	{
3959	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3960	if (pGuestPDPT->a[iPdPt].n.u1Present)
3961	{
3962	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3963	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3964	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3965	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3966	#endif
3967
3968	/* cache is out-of-sync. */
3969	PX86PDPAE pPD;
3970	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3971	if (RT_SUCCESS(rc))
3972	return pPD->a[iPD];
3973	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3974	}
3975	}
3976	X86PDEPAE ZeroPde = {0};
3977	return ZeroPde;
3978	}
3979
3980
3981	/**
3982	* Gets the page directory pointer table entry for the specified address
3983	* and returns the index into the page directory
3984	*
3985	* @returns Pointer to the page directory in question.
3986	* @returns NULL if the page directory is not present or on an invalid page.
3987	* @param pPGM Pointer to the PGM instance data.
3988	* @param GCPtr The address.
3989	* @param piPD Receives the index into the returned page directory
3990	* @param pPdpe Receives the page directory pointer entry. Optional.
3991	*/
3992	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3993	{
3994	AssertGCPtr32(GCPtr);
3995
3996	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3997	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3998	AssertReturn(pGuestPDPT, 0);
3999	#else
4000	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
4001	#endif
4002	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4003	if (pPdpe)
4004	*pPdpe = pGuestPDPT->a[iPdPt];
4005	if (pGuestPDPT->a[iPdPt].n.u1Present)
4006	{
4007	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4008	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4009	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
4010	{
4011	*piPD = iPD;
4012	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
4013	}
4014	#endif
4015
4016	/* cache is out-of-sync. */
4017	PX86PDPAE pPD;
4018	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4019	if (RT_SUCCESS(rc))
4020	{
4021	*piPD = iPD;
4022	return pPD;
4023	}
4024	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
4025	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4026	}
4027	return NULL;
4028	}
4029
4030	#ifndef IN_RC
4031
4032	/**
4033	* Gets the page map level-4 pointer for the guest.
4034	*
4035	* @returns Pointer to the PML4 page.
4036	* @param pPGM Pointer to the PGM instance data.
4037	*/
4038	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
4039	{
4040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4041	PX86PML4 pGuestPml4;
4042	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4043	AssertRCReturn(rc, NULL);
4044	return pGuestPml4;
4045	#else
4046	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4047	return pPGM->CTX_SUFF(pGstAmd64Pml4);
4048	#endif
4049	}
4050
4051
4052	/**
4053	* Gets the pointer to a page map level-4 entry.
4054	*
4055	* @returns Pointer to the PML4 entry.
4056	* @param pPGM Pointer to the PGM instance data.
4057	* @param iPml4 The index.
4058	*/
4059	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4060	{
4061	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4062	PX86PML4 pGuestPml4;
4063	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4064	AssertRCReturn(rc, NULL);
4065	return &pGuestPml4->a[iPml4];
4066	#else
4067	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4068	return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4069	#endif
4070	}
4071
4072
4073	/**
4074	* Gets a page map level-4 entry.
4075	*
4076	* @returns The PML4 entry.
4077	* @param pPGM Pointer to the PGM instance data.
4078	* @param iPml4 The index.
4079	*/
4080	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
4081	{
4082	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4083	PX86PML4 pGuestPml4;
4084	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4085	if (RT_FAILURE(rc))
4086	{
4087	X86PML4E ZeroPml4e = {0};
4088	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4089	}
4090	return pGuestPml4->a[iPml4];
4091	#else
4092	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4093	return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4094	#endif
4095	}
4096
4097
4098	/**
4099	* Gets the page directory pointer entry for the specified address.
4100	*
4101	* @returns Pointer to the page directory pointer entry in question.
4102	* @returns NULL if the page directory is not present or on an invalid page.
4103	* @param pPGM Pointer to the PGM instance data.
4104	* @param GCPtr The address.
4105	* @param ppPml4e Page Map Level-4 Entry (out)
4106	*/
4107	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4108	{
4109	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4110	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4111	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4112	if (pPml4e->n.u1Present)
4113	{
4114	PX86PDPT pPdpt;
4115	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4116	AssertRCReturn(rc, NULL);
4117
4118	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4119	return &pPdpt->a[iPdPt];
4120	}
4121	return NULL;
4122	}
4123
4124
4125	/**
4126	* Gets the page directory entry for the specified address.
4127	*
4128	* @returns The page directory entry in question.
4129	* @returns A non-present entry if the page directory is not present or on an invalid page.
4130	* @param pPGM Pointer to the PGM instance data.
4131	* @param GCPtr The address.
4132	* @param ppPml4e Page Map Level-4 Entry (out)
4133	* @param pPdpe Page directory pointer table entry (out)
4134	*/
4135	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4136	{
4137	X86PDEPAE ZeroPde = {0};
4138	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4139	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4140	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4141	if (pPml4e->n.u1Present)
4142	{
4143	PCX86PDPT pPdptTemp;
4144	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4145	AssertRCReturn(rc, ZeroPde);
4146
4147	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4148	*pPdpe = pPdptTemp->a[iPdPt];
4149	if (pPdptTemp->a[iPdPt].n.u1Present)
4150	{
4151	PCX86PDPAE pPD;
4152	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4153	AssertRCReturn(rc, ZeroPde);
4154
4155	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4156	return pPD->a[iPD];
4157	}
4158	}
4159
4160	return ZeroPde;
4161	}
4162
4163
4164	/**
4165	* Gets the page directory entry for the specified address.
4166	*
4167	* @returns The page directory entry in question.
4168	* @returns A non-present entry if the page directory is not present or on an invalid page.
4169	* @param pPGM Pointer to the PGM instance data.
4170	* @param GCPtr The address.
4171	*/
4172	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4173	{
4174	X86PDEPAE ZeroPde = {0};
4175	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4176	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4177	if (pGuestPml4->a[iPml4].n.u1Present)
4178	{
4179	PCX86PDPT pPdptTemp;
4180	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4181	AssertRCReturn(rc, ZeroPde);
4182
4183	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4184	if (pPdptTemp->a[iPdPt].n.u1Present)
4185	{
4186	PCX86PDPAE pPD;
4187	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4188	AssertRCReturn(rc, ZeroPde);
4189
4190	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4191	return pPD->a[iPD];
4192	}
4193	}
4194	return ZeroPde;
4195	}
4196
4197
4198	/**
4199	* Gets the page directory entry for the specified address.
4200	*
4201	* @returns Pointer to the page directory entry in question.
4202	* @returns NULL if the page directory is not present or on an invalid page.
4203	* @param pPGM Pointer to the PGM instance data.
4204	* @param GCPtr The address.
4205	*/
4206	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4207	{
4208	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4209	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4210	if (pGuestPml4->a[iPml4].n.u1Present)
4211	{
4212	PCX86PDPT pPdptTemp;
4213	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4214	AssertRCReturn(rc, NULL);
4215
4216	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4217	if (pPdptTemp->a[iPdPt].n.u1Present)
4218	{
4219	PX86PDPAE pPD;
4220	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4221	AssertRCReturn(rc, NULL);
4222
4223	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4224	return &pPD->a[iPD];
4225	}
4226	}
4227	return NULL;
4228	}
4229
4230
4231	/**
4232	* Gets the GUEST page directory pointer for the specified address.
4233	*
4234	* @returns The page directory in question.
4235	* @returns NULL if the page directory is not present or on an invalid page.
4236	* @param pPGM Pointer to the PGM instance data.
4237	* @param GCPtr The address.
4238	* @param ppPml4e Page Map Level-4 Entry (out)
4239	* @param pPdpe Page directory pointer table entry (out)
4240	* @param piPD Receives the index into the returned page directory
4241	*/
4242	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4243	{
4244	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4245	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4246	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4247	if (pPml4e->n.u1Present)
4248	{
4249	PCX86PDPT pPdptTemp;
4250	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4251	AssertRCReturn(rc, NULL);
4252
4253	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4254	*pPdpe = pPdptTemp->a[iPdPt];
4255	if (pPdptTemp->a[iPdPt].n.u1Present)
4256	{
4257	PX86PDPAE pPD;
4258	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4259	AssertRCReturn(rc, NULL);
4260
4261	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4262	return pPD;
4263	}
4264	}
4265	return 0;
4266	}
4267
4268	#endif /* !IN_RC */
4269
4270
4271	/**
4272	* Gets the shadow page directory, 32-bit.
4273	*
4274	* @returns Pointer to the shadow 32-bit PD.
4275	* @param pPGM Pointer to the PGM instance data.
4276	*/
4277	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4278	{
4279	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4280	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4281	#else
4282	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4283	PX86PD pShwPd;
4284	Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4285	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4286	AssertRCReturn(rc, NULL);
4287	return pShwPd;
4288	# else
4289	return pPGM->CTX_SUFF(pShw32BitPd);
4290	# endif
4291	#endif
4292	}
4293
4294
4295	/**
4296	* Gets the shadow page directory entry for the specified address, 32-bit.
4297	*
4298	* @returns Shadow 32-bit PDE.
4299	* @param pPGM Pointer to the PGM instance data.
4300	* @param GCPtr The address.
4301	*/
4302	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4303	{
4304	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4305
4306	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4307	if (!pShwPde)
4308	{
4309	X86PDE ZeroPde = {0};
4310	return ZeroPde;
4311	}
4312	return pShwPde->a[iPd];
4313	}
4314
4315
4316	/**
4317	* Gets the pointer to the shadow page directory entry for the specified
4318	* address, 32-bit.
4319	*
4320	* @returns Pointer to the shadow 32-bit PDE.
4321	* @param pPGM Pointer to the PGM instance data.
4322	* @param GCPtr The address.
4323	*/
4324	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4325	{
4326	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4327
4328	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4329	AssertReturn(pPde, NULL);
4330	return &pPde->a[iPd];
4331	}
4332
4333
4334	/**
4335	* Gets the shadow page pointer table, PAE.
4336	*
4337	* @returns Pointer to the shadow PAE PDPT.
4338	* @param pPGM Pointer to the PGM instance data.
4339	*/
4340	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4341	{
4342	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4343	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4344	#else
4345	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4346	PX86PDPT pShwPdpt;
4347	Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4348	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4349	AssertRCReturn(rc, 0);
4350	return pShwPdpt;
4351	# else
4352	return pPGM->CTX_SUFF(pShwPaePdpt);
4353	# endif
4354	#endif
4355	}
4356
4357
4358	/**
4359	* Gets the shadow page directory for the specified address, PAE.
4360	*
4361	* @returns Pointer to the shadow PD.
4362	* @param pPGM Pointer to the PGM instance data.
4363	* @param GCPtr The address.
4364	*/
4365	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4366	{
4367	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4368	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4369	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4370
4371	if (!pPdpt->a[iPdpt].n.u1Present)
4372	return NULL;
4373
4374	/* Fetch the pgm pool shadow descriptor. */
4375	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4376	AssertReturn(pShwPde, NULL);
4377
4378	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4379	#else
4380	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4381	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4382	PX86PDPAE pPD;
4383	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4384	AssertRCReturn(rc, 0);
4385	return pPD;
4386	# else
4387	PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4388	Assert(pPD);
4389	return pPD;
4390	# endif
4391	#endif
4392	}
4393
4394	/**
4395	* Gets the shadow page directory for the specified address, PAE.
4396	*
4397	* @returns Pointer to the shadow PD.
4398	* @param pPGM Pointer to the PGM instance data.
4399	* @param GCPtr The address.
4400	*/
4401	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4402	{
4403	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4404	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4405
4406	if (!pPdpt->a[iPdpt].n.u1Present)
4407	return NULL;
4408
4409	/* Fetch the pgm pool shadow descriptor. */
4410	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4411	AssertReturn(pShwPde, NULL);
4412
4413	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4414	#else
4415	AssertFailed();
4416	return NULL;
4417	#endif
4418	}
4419
4420	/**
4421	* Gets the shadow page directory entry, PAE.
4422	*
4423	* @returns PDE.
4424	* @param pPGM Pointer to the PGM instance data.
4425	* @param GCPtr The address.
4426	*/
4427	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4428	{
4429	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4430
4431	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4432	if (!pShwPde)
4433	{
4434	X86PDEPAE ZeroPde = {0};
4435	return ZeroPde;
4436	}
4437	return pShwPde->a[iPd];
4438	}
4439
4440
4441	/**
4442	* Gets the pointer to the shadow page directory entry for an address, PAE.
4443	*
4444	* @returns Pointer to the PDE.
4445	* @param pPGM Pointer to the PGM instance data.
4446	* @param GCPtr The address.
4447	*/
4448	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4449	{
4450	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4451
4452	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4453	AssertReturn(pPde, NULL);
4454	return &pPde->a[iPd];
4455	}
4456
4457	#ifndef IN_RC
4458	/**
4459	* Gets the shadow page map level-4 pointer.
4460	*
4461	* @returns Pointer to the shadow PML4.
4462	* @param pPGM Pointer to the PGM instance data.
4463	*/
4464	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4465	{
4466	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4467	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4468	#else
4469	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4470	PX86PML4 pShwPml4;
4471	Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4472	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4473	AssertRCReturn(rc, 0);
4474	return pShwPml4;
4475	# else
4476	Assert(pPGM->CTX_SUFF(pShwRoot));
4477	return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4478	# endif
4479	#endif
4480	}
4481
4482
4483	/**
4484	* Gets the shadow page map level-4 entry for the specified address.
4485	*
4486	* @returns The entry.
4487	* @param pPGM Pointer to the PGM instance data.
4488	* @param GCPtr The address.
4489	*/
4490	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4491	{
4492	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4493	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4494
4495	if (!pShwPml4)
4496	{
4497	X86PML4E ZeroPml4e = {0};
4498	return ZeroPml4e;
4499	}
4500	return pShwPml4->a[iPml4];
4501	}
4502
4503
4504	/**
4505	* Gets the pointer to the specified shadow page map level-4 entry.
4506	*
4507	* @returns The entry.
4508	* @param pPGM Pointer to the PGM instance data.
4509	* @param iPml4 The PML4 index.
4510	*/
4511	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4512	{
4513	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4514	if (!pShwPml4)
4515	return NULL;
4516	return &pShwPml4->a[iPml4];
4517	}
4518
4519
4520	/**
4521	* Gets the GUEST page directory pointer for the specified address.
4522	*
4523	* @returns The page directory in question.
4524	* @returns NULL if the page directory is not present or on an invalid page.
4525	* @param pPGM Pointer to the PGM instance data.
4526	* @param GCPtr The address.
4527	* @param piPD Receives the index into the returned page directory
4528	*/
4529	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4530	{
4531	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4532	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4533	if (pGuestPml4->a[iPml4].n.u1Present)
4534	{
4535	PCX86PDPT pPdptTemp;
4536	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4537	AssertRCReturn(rc, NULL);
4538
4539	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4540	if (pPdptTemp->a[iPdPt].n.u1Present)
4541	{
4542	PX86PDPAE pPD;
4543	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4544	AssertRCReturn(rc, NULL);
4545
4546	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4547	return pPD;
4548	}
4549	}
4550	return NULL;
4551	}
4552
4553	#endif /* !IN_RC */
4554
4555	/**
4556	* Checks if any of the specified page flags are set for the given page.
4557	*
4558	* @returns true if any of the flags are set.
4559	* @returns false if all the flags are clear.
4560	* @param pPGM PGM handle.
4561	* @param GCPhys The GC physical address.
4562	* @param fFlags The flags to check for.
4563	*/
4564	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4565	{
4566	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4567	return pPage
4568	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4569	}
4570
4571
4572	/**
4573	* Gets the page state for a physical handler.
4574	*
4575	* @returns The physical handler page state.
4576	* @param pCur The physical handler in question.
4577	*/
4578	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4579	{
4580	switch (pCur->enmType)
4581	{
4582	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4583	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4584
4585	case PGMPHYSHANDLERTYPE_MMIO:
4586	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4587	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4588
4589	default:
4590	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4591	}
4592	}
4593
4594
4595	/**
4596	* Gets the page state for a virtual handler.
4597	*
4598	* @returns The virtual handler page state.
4599	* @param pCur The virtual handler in question.
4600	* @remarks This should never be used on a hypervisor access handler.
4601	*/
4602	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4603	{
4604	switch (pCur->enmType)
4605	{
4606	case PGMVIRTHANDLERTYPE_WRITE:
4607	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4608	case PGMVIRTHANDLERTYPE_ALL:
4609	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4610	default:
4611	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4612	}
4613	}
4614
4615
4616	/**
4617	* Clears one physical page of a virtual handler
4618	*
4619	* @param pPGM Pointer to the PGM instance.
4620	* @param pCur Virtual handler structure
4621	* @param iPage Physical page index
4622	*
4623	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4624	* need to care about other handlers in the same page.
4625	*/
4626	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4627	{
4628	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4629
4630	/*
4631	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4632	*/
4633	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4634	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4635	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4636	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4637	#endif
4638	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4639	{
4640	/* We're the head of the alias chain. */
4641	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4642	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4643	AssertReleaseMsg(pRemove != NULL,
4644	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4645	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4646	AssertReleaseMsg(pRemove == pPhys2Virt,
4647	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4648	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4649	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4650	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4651	#endif
4652	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4653	{
4654	/* Insert the next list in the alias chain into the tree. */
4655	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4656	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4657	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4658	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4659	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4660	#endif
4661	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4662	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4663	AssertRelease(fRc);
4664	}
4665	}
4666	else
4667	{
4668	/* Locate the previous node in the alias chain. */
4669	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4670	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4671	AssertReleaseMsg(pPrev != pPhys2Virt,
4672	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4673	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4674	#endif
4675	for (;;)
4676	{
4677	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4678	if (pNext == pPhys2Virt)
4679	{
4680	/* unlink. */
4681	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4682	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4683	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4684	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4685	else
4686	{
4687	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4688	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4689	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4690	}
4691	break;
4692	}
4693
4694	/* next */
4695	if (pNext == pPrev)
4696	{
4697	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4698	AssertReleaseMsg(pNext != pPrev,
4699	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4700	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4701	#endif
4702	break;
4703	}
4704	pPrev = pNext;
4705	}
4706	}
4707	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4708	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4709	pPhys2Virt->offNextAlias = 0;
4710	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4711
4712	/*
4713	* Clear the ram flags for this page.
4714	*/
4715	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4716	AssertReturnVoid(pPage);
4717	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4718	}
4719
4720
4721	/**
4722	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4723	*
4724	* @returns Pointer to the shadow page structure.
4725	* @param pPool The pool.
4726	* @param HCPhys The HC physical address of the shadow page.
4727	*/
4728	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4729	{
4730	/*
4731	* Look up the page.
4732	*/
4733	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4734	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4735	return pPage;
4736	}
4737
4738
4739	/**
4740	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4741	*
4742	* @returns Pointer to the shadow page structure.
4743	* @param pPool The pool.
4744	* @param idx The pool page index.
4745	*/
4746	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4747	{
4748	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4749	return &pPool->aPages[idx];
4750	}
4751
4752
4753	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4754	/**
4755	* Clear references to guest physical memory.
4756	*
4757	* @param pPool The pool.
4758	* @param pPoolPage The pool page.
4759	* @param pPhysPage The physical guest page tracking structure.
4760	*/
4761	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4762	{
4763	/*
4764	* Just deal with the simple case here.
4765	*/
4766	# ifdef LOG_ENABLED
4767	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4768	# endif
4769	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4770	if (cRefs == 1)
4771	{
4772	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4773	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4774	}
4775	else
4776	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4777	Log2(("pgmTrackDerefGCPhys: %x -> %x HCPhys=%RGp\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), PGM_PAGE_GET_HCPHYS(pPhysPage) ));
4778	}
4779	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4780
4781
4782	#ifdef PGMPOOL_WITH_CACHE
4783	/**
4784	* Moves the page to the head of the age list.
4785	*
4786	* This is done when the cached page is used in one way or another.
4787	*
4788	* @param pPool The pool.
4789	* @param pPage The cached page.
4790	* @todo inline in PGMInternal.h!
4791	*/
4792	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4793	{
4794	/*
4795	* Move to the head of the age list.
4796	*/
4797	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4798	{
4799	/* unlink */
4800	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4801	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4802	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4803	else
4804	pPool->iAgeTail = pPage->iAgePrev;
4805
4806	/* insert at head */
4807	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4808	pPage->iAgeNext = pPool->iAgeHead;
4809	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4810	pPool->iAgeHead = pPage->idx;
4811	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4812	}
4813	}
4814	#endif /* PGMPOOL_WITH_CACHE */
4815
4816	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4817	/**
4818	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4819	*
4820	* @returns VBox status code.
4821	* @param pVM VM Handle.
4822	* @param pPage PGM pool page
4823	*/
4824	DECLINLINE(int) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4825	{
4826	Assert(!pPage->fLocked);
4827	pPage->fLocked = true;
4828	return VINF_SUCCESS;
4829	}
4830
4831	/**
4832	* Unlocks a page to allow flushing again
4833	*
4834	* @returns VBox status code.
4835	* @param pVM VM Handle.
4836	* @param pPage PGM pool page
4837	*/
4838	DECLINLINE(int) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4839	{
4840	Assert(pPage->fLocked);
4841	pPage->fLocked = false;
4842	return VINF_SUCCESS;
4843	}
4844
4845	/**
4846	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4847	*
4848	* @returns VBox status code.
4849	* @param pPage PGM pool page
4850	*/
4851	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4852	{
4853	if (pPage->fLocked)
4854	{
4855	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4856	if (pPage->cModifications)
4857	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4858	return true;
4859	}
4860	return false;
4861	}
4862	#endif
4863
4864	/**
4865	* Tells if mappings are to be put into the shadow page table or not
4866	*
4867	* @returns boolean result
4868	* @param pVM VM handle.
4869	*/
4870
4871	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4872	{
4873	#ifdef IN_RING0
4874	/* There are no mappings in VT-x and AMD-V mode. */
4875	Assert(pPGM->fDisableMappings);
4876	return false;
4877	#else
4878	return !pPGM->fDisableMappings;
4879	#endif
4880	}
4881
4882	/** @} */
4883
4884	#endif
4885

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17290

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