VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17469

Last change on this file since 17469 was 17462, checked in by vboxsync, 16 years ago

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1/* $Id: PGMInternal.h 17462 2009-03-06 13:00:54Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** @} */
188
189/** @name Defines used to indicate the shadow and guest paging in the templates.
190 * @{ */
191#define PGM_TYPE_REAL 1
192#define PGM_TYPE_PROT 2
193#define PGM_TYPE_32BIT 3
194#define PGM_TYPE_PAE 4
195#define PGM_TYPE_AMD64 5
196#define PGM_TYPE_NESTED 6
197#define PGM_TYPE_EPT 7
198#define PGM_TYPE_MAX PGM_TYPE_EPT
199/** @} */
200
201/** Macro for checking if the guest is using paging.
202 * @param uGstType PGM_TYPE_*
203 * @param uShwType PGM_TYPE_*
204 * @remark ASSUMES certain order of the PGM_TYPE_* values.
205 */
206#define PGM_WITH_PAGING(uGstType, uShwType) \
207 ( (uGstType) >= PGM_TYPE_32BIT \
208 && (uShwType) != PGM_TYPE_NESTED \
209 && (uShwType) != PGM_TYPE_EPT)
210
211/** Macro for checking if the guest supports the NX bit.
212 * @param uGstType PGM_TYPE_*
213 * @param uShwType PGM_TYPE_*
214 * @remark ASSUMES certain order of the PGM_TYPE_* values.
215 */
216#define PGM_WITH_NX(uGstType, uShwType) \
217 ( (uGstType) >= PGM_TYPE_PAE \
218 && (uShwType) != PGM_TYPE_NESTED \
219 && (uShwType) != PGM_TYPE_EPT)
220
221
222/** @def PGM_HCPHYS_2_PTR
223 * Maps a HC physical page pool address to a virtual address.
224 *
225 * @returns VBox status code.
226 * @param pVM The VM handle.
227 * @param HCPhys The HC physical address to map to a virtual one.
228 * @param ppv Where to store the virtual address. No need to cast this.
229 *
230 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
231 * small page window employeed by that function. Be careful.
232 * @remark There is no need to assert on the result.
233 */
234#ifdef IN_RC
235# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
237#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
240#else
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
243#endif
244
245/** @def PGM_HCPHYS_2_PTR_BY_PGM
246 * Maps a HC physical page pool address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pPGM The PGM instance data.
250 * @param HCPhys The HC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
258# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
259 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
260#else
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
263#endif
264
265/** @def PGM_GCPHYS_2_PTR
266 * Maps a GC physical page address to a virtual address.
267 *
268 * @returns VBox status code.
269 * @param pVM The VM handle.
270 * @param GCPhys The GC physical address to map to a virtual one.
271 * @param ppv Where to store the virtual address. No need to cast this.
272 *
273 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
274 * small page window employeed by that function. Be careful.
275 * @remark There is no need to assert on the result.
276 */
277#ifdef IN_RC
278# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
280#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
283#else
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
286#endif
287
288/** @def PGM_GCPHYS_2_PTR_BY_PGM
289 * Maps a GC physical page address to a virtual address.
290 *
291 * @returns VBox status code.
292 * @param pPGM Pointer to the PGM instance data.
293 * @param GCPhys The GC physical address to map to a virtual one.
294 * @param ppv Where to store the virtual address. No need to cast this.
295 *
296 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
297 * small page window employeed by that function. Be careful.
298 * @remark There is no need to assert on the result.
299 */
300#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
301# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
302 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
303#else
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
306#endif
307
308/** @def PGM_GCPHYS_2_PTR_EX
309 * Maps a unaligned GC physical page address to a virtual address.
310 *
311 * @returns VBox status code.
312 * @param pVM The VM handle.
313 * @param GCPhys The GC physical address to map to a virtual one.
314 * @param ppv Where to store the virtual address. No need to cast this.
315 *
316 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
317 * small page window employeed by that function. Be careful.
318 * @remark There is no need to assert on the result.
319 */
320#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
321# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
322 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
323#else
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
326#endif
327
328/** @def PGM_INVL_PG
329 * Invalidates a page when in GC does nothing in HC.
330 *
331 * @param GCVirt The virtual address of the page to invalidate.
332 */
333#ifdef IN_RC
334# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
335#elif defined(IN_RING0)
336# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
337#else
338# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
339#endif
340
341/** @def PGM_INVL_BIG_PG
342 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
343 *
344 * @param GCVirt The virtual address within the page directory to invalidate.
345 */
346#ifdef IN_RC
347# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
348#elif defined(IN_RING0)
349# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
350#else
351# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
352#endif
353
354/** @def PGM_INVL_GUEST_TLBS()
355 * Invalidates all guest TLBs.
356 */
357#ifdef IN_RC
358# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
359#elif defined(IN_RING0)
360# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
361#else
362# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
363#endif
364
365
366/**
367 * Structure for tracking GC Mappings.
368 *
369 * This structure is used by linked list in both GC and HC.
370 */
371typedef struct PGMMAPPING
372{
373 /** Pointer to next entry. */
374 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
375 /** Pointer to next entry. */
376 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
377 /** Pointer to next entry. */
378 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
379 /** Indicate whether this entry is finalized. */
380 bool fFinalized;
381 /** Start Virtual address. */
382 RTGCPTR GCPtr;
383 /** Last Virtual address (inclusive). */
384 RTGCPTR GCPtrLast;
385 /** Range size (bytes). */
386 RTGCPTR cb;
387 /** Pointer to relocation callback function. */
388 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
389 /** User argument to the callback. */
390 R3PTRTYPE(void *) pvUser;
391 /** Mapping description / name. For easing debugging. */
392 R3PTRTYPE(const char *) pszDesc;
393 /** Number of page tables. */
394 uint32_t cPTs;
395#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
396 uint32_t uPadding1; /**< Alignment padding. */
397#endif
398 /** Array of page table mapping data. Each entry
399 * describes one page table. The array can be longer
400 * than the declared length.
401 */
402 struct
403 {
404 /** The HC physical address of the page table. */
405 RTHCPHYS HCPhysPT;
406 /** The HC physical address of the first PAE page table. */
407 RTHCPHYS HCPhysPaePT0;
408 /** The HC physical address of the second PAE page table. */
409 RTHCPHYS HCPhysPaePT1;
410 /** The HC virtual address of the 32-bit page table. */
411 R3PTRTYPE(PX86PT) pPTR3;
412 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
413 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
414 /** The GC virtual address of the 32-bit page table. */
415 RCPTRTYPE(PX86PT) pPTRC;
416 /** The GC virtual address of the two PAE page table. */
417 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
418 /** The GC virtual address of the 32-bit page table. */
419 R0PTRTYPE(PX86PT) pPTR0;
420 /** The GC virtual address of the two PAE page table. */
421 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
422 } aPTs[1];
423} PGMMAPPING;
424/** Pointer to structure for tracking GC Mappings. */
425typedef struct PGMMAPPING *PPGMMAPPING;
426
427
428/**
429 * Physical page access handler structure.
430 *
431 * This is used to keep track of physical address ranges
432 * which are being monitored in some kind of way.
433 */
434typedef struct PGMPHYSHANDLER
435{
436 AVLROGCPHYSNODECORE Core;
437 /** Access type. */
438 PGMPHYSHANDLERTYPE enmType;
439 /** Number of pages to update. */
440 uint32_t cPages;
441 /** Pointer to R3 callback function. */
442 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
443 /** User argument for R3 handlers. */
444 R3PTRTYPE(void *) pvUserR3;
445 /** Pointer to R0 callback function. */
446 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
447 /** User argument for R0 handlers. */
448 R0PTRTYPE(void *) pvUserR0;
449 /** Pointer to GC callback function. */
450 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
451 /** User argument for RC handlers. */
452 RCPTRTYPE(void *) pvUserRC;
453 /** Description / Name. For easing debugging. */
454 R3PTRTYPE(const char *) pszDesc;
455#ifdef VBOX_WITH_STATISTICS
456 /** Profiling of this handler. */
457 STAMPROFILE Stat;
458#endif
459} PGMPHYSHANDLER;
460/** Pointer to a physical page access handler structure. */
461typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
462
463
464/**
465 * Cache node for the physical addresses covered by a virtual handler.
466 */
467typedef struct PGMPHYS2VIRTHANDLER
468{
469 /** Core node for the tree based on physical ranges. */
470 AVLROGCPHYSNODECORE Core;
471 /** Offset from this struct to the PGMVIRTHANDLER structure. */
472 int32_t offVirtHandler;
473 /** Offset of the next alias relative to this one.
474 * Bit 0 is used for indicating whether we're in the tree.
475 * Bit 1 is used for indicating that we're the head node.
476 */
477 int32_t offNextAlias;
478} PGMPHYS2VIRTHANDLER;
479/** Pointer to a phys to virtual handler structure. */
480typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
481
482/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
483 * node is in the tree. */
484#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the head of an alias chain.
487 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
488#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
489/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
490#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
491
492
493/**
494 * Virtual page access handler structure.
495 *
496 * This is used to keep track of virtual address ranges
497 * which are being monitored in some kind of way.
498 */
499typedef struct PGMVIRTHANDLER
500{
501 /** Core node for the tree based on virtual ranges. */
502 AVLROGCPTRNODECORE Core;
503 /** Size of the range (in bytes). */
504 RTGCPTR cb;
505 /** Number of cache pages. */
506 uint32_t cPages;
507 /** Access type. */
508 PGMVIRTHANDLERTYPE enmType;
509 /** Pointer to the RC callback function. */
510 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
511#if HC_ARCH_BITS == 64
512 RTRCPTR padding;
513#endif
514 /** Pointer to the R3 callback function for invalidation. */
515 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
516 /** Pointer to the R3 callback function. */
517 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
518 /** Description / Name. For easing debugging. */
519 R3PTRTYPE(const char *) pszDesc;
520#ifdef VBOX_WITH_STATISTICS
521 /** Profiling of this handler. */
522 STAMPROFILE Stat;
523#endif
524 /** Array of cached physical addresses for the monitored ranged. */
525 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
526} PGMVIRTHANDLER;
527/** Pointer to a virtual page access handler structure. */
528typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
529
530
531/**
532 * Page type.
533 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
534 * @todo convert to \#defines.
535 */
536typedef enum PGMPAGETYPE
537{
538 /** The usual invalid zero entry. */
539 PGMPAGETYPE_INVALID = 0,
540 /** RAM page. (RWX) */
541 PGMPAGETYPE_RAM,
542 /** MMIO2 page. (RWX) */
543 PGMPAGETYPE_MMIO2,
544 /** MMIO2 page aliased over an MMIO page. (RWX)
545 * See PGMHandlerPhysicalPageAlias(). */
546 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
547 /** Shadowed ROM. (RWX) */
548 PGMPAGETYPE_ROM_SHADOW,
549 /** ROM page. (R-X) */
550 PGMPAGETYPE_ROM,
551 /** MMIO page. (---) */
552 PGMPAGETYPE_MMIO,
553 /** End of valid entries. */
554 PGMPAGETYPE_END
555} PGMPAGETYPE;
556AssertCompile(PGMPAGETYPE_END <= 7);
557
558/** @name Page type predicates.
559 * @{ */
560#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
561#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
562#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
563#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
565/** @} */
566
567
568/**
569 * A Physical Guest Page tracking structure.
570 *
571 * The format of this structure is complicated because we have to fit a lot
572 * of information into as few bits as possible. The format is also subject
573 * to change (there is one comming up soon). Which means that for we'll be
574 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
575 * accessess to the structure.
576 */
577typedef struct PGMPAGE
578{
579 /** The physical address and a whole lot of other stuff. All bits are used! */
580#ifdef VBOX_WITH_NEW_PHYS_CODE
581 RTHCPHYS HCPhysX;
582#else
583 RTHCPHYS HCPhys;
584#define HCPhysX HCPhys /**< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. */
585#endif
586 /** The page state. */
587 uint32_t u2StateX : 2;
588 /** Flag indicating that a write monitored page was written to when set. */
589 uint32_t fWrittenToX : 1;
590 /** For later. */
591 uint32_t fSomethingElse : 1;
592 /** The Page ID.
593 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
594 * The HCPhysX will then be 100% static. */
595 uint32_t idPageX : 28;
596 /** The page type (PGMPAGETYPE). */
597 uint32_t u3Type : 3;
598 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
599 uint32_t u2HandlerPhysStateX : 2;
600 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
601 uint32_t u2HandlerVirtStateX : 2;
602 uint32_t u29B : 25;
603} PGMPAGE;
604AssertCompileSize(PGMPAGE, 16);
605/** Pointer to a physical guest page. */
606typedef PGMPAGE *PPGMPAGE;
607/** Pointer to a const physical guest page. */
608typedef const PGMPAGE *PCPGMPAGE;
609/** Pointer to a physical guest page pointer. */
610typedef PPGMPAGE *PPPGMPAGE;
611
612
613/**
614 * Clears the page structure.
615 * @param pPage Pointer to the physical guest page tracking structure.
616 */
617#define PGM_PAGE_CLEAR(pPage) \
618 do { \
619 (pPage)->HCPhysX = 0; \
620 (pPage)->u2StateX = 0; \
621 (pPage)->fWrittenToX = 0; \
622 (pPage)->fSomethingElse = 0; \
623 (pPage)->idPageX = 0; \
624 (pPage)->u3Type = 0; \
625 (pPage)->u29B = 0; \
626 } while (0)
627
628/**
629 * Initializes the page structure.
630 * @param pPage Pointer to the physical guest page tracking structure.
631 */
632#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
633 do { \
634 (pPage)->HCPhysX = (_HCPhys); \
635 (pPage)->u2StateX = (_uState); \
636 (pPage)->fWrittenToX = 0; \
637 (pPage)->fSomethingElse = 0; \
638 (pPage)->idPageX = (_idPage); \
639 /*(pPage)->u3Type = (_uType); - later */ \
640 PGM_PAGE_SET_TYPE(pPage, _uType); \
641 (pPage)->u29B = 0; \
642 } while (0)
643
644/**
645 * Initializes the page structure of a ZERO page.
646 * @param pPage Pointer to the physical guest page tracking structure.
647 */
648#ifdef VBOX_WITH_NEW_PHYS_CODE
649# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
650 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
651#else
652# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
653 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
654#endif
655/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
656# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
657 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
658
659
660/** @name The Page state, PGMPAGE::u2StateX.
661 * @{ */
662/** The zero page.
663 * This is a per-VM page that's never ever mapped writable. */
664#define PGM_PAGE_STATE_ZERO 0
665/** A allocated page.
666 * This is a per-VM page allocated from the page pool (or wherever
667 * we get MMIO2 pages from if the type is MMIO2).
668 */
669#define PGM_PAGE_STATE_ALLOCATED 1
670/** A allocated page that's being monitored for writes.
671 * The shadow page table mappings are read-only. When a write occurs, the
672 * fWrittenTo member is set, the page remapped as read-write and the state
673 * moved back to allocated. */
674#define PGM_PAGE_STATE_WRITE_MONITORED 2
675/** The page is shared, aka. copy-on-write.
676 * This is a page that's shared with other VMs. */
677#define PGM_PAGE_STATE_SHARED 3
678/** @} */
679
680
681/**
682 * Gets the page state.
683 * @returns page state (PGM_PAGE_STATE_*).
684 * @param pPage Pointer to the physical guest page tracking structure.
685 */
686#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
687
688/**
689 * Sets the page state.
690 * @param pPage Pointer to the physical guest page tracking structure.
691 * @param _uState The new page state.
692 */
693#define PGM_PAGE_SET_STATE(pPage, _uState) \
694 do { (pPage)->u2StateX = (_uState); } while (0)
695
696
697/**
698 * Gets the host physical address of the guest page.
699 * @returns host physical address (RTHCPHYS).
700 * @param pPage Pointer to the physical guest page tracking structure.
701 */
702#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
703
704/**
705 * Sets the host physical address of the guest page.
706 * @param pPage Pointer to the physical guest page tracking structure.
707 * @param _HCPhys The new host physical address.
708 */
709#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
710 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
711 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
712
713/**
714 * Get the Page ID.
715 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
719/* later:
720#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
721 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
722*/
723/**
724 * Sets the Page ID.
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
728/* later:
729#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
730 | ((_idPage) & 0xfff) \
731 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
732*/
733
734/**
735 * Get the Chunk ID.
736 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
740/* later:
741#if GMM_CHUNKID_SHIFT == 12
742# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
743#elif GMM_CHUNKID_SHIFT > 12
744# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
745#elif GMM_CHUNKID_SHIFT < 12
746# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
747 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
748#else
749# error "GMM_CHUNKID_SHIFT isn't defined or something."
750#endif
751*/
752
753/**
754 * Get the index of the page within the allocaiton chunk.
755 * @returns The page index.
756 * @param pPage Pointer to the physical guest page tracking structure.
757 */
758#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
759/* later:
760#if GMM_CHUNKID_SHIFT <= 12
761# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
762#else
763# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
764 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
765#endif
766*/
767
768
769/**
770 * Gets the page type.
771 * @returns The page type.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
775
776/**
777 * Sets the page type.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 * @param _enmType The new page type (PGMPAGETYPE).
780 */
781#ifdef VBOX_WITH_NEW_PHYS_CODE
782#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
783 do { (pPage)->u3Type = (_enmType); } while (0)
784#else
785#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
786 do { \
787 (pPage)->u3Type = (_enmType); \
788 if ((_enmType) == PGMPAGETYPE_ROM) \
789 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM; \
790 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
791 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
792 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
793 (pPage)->HCPhysX |= MM_RAM_FLAGS_MMIO2; \
794 } while (0)
795#endif
796
797
798/**
799 * Checks if the page is 'reserved'.
800 * @returns true/false.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
804
805/**
806 * Checks if the page is marked for MMIO.
807 * @returns true/false.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#ifdef VBOX_WITH_NEW_PHYS_CODE
811# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
812#else
813# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
814#endif
815
816/**
817 * Checks if the page is backed by the ZERO page.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
822
823/**
824 * Checks if the page is backed by a SHARED page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
829
830
831/**
832 * Marks the paget as written to (for GMM change monitoring).
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
836
837/**
838 * Clears the written-to indicator.
839 * @param pPage Pointer to the physical guest page tracking structure.
840 */
841#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
842
843/**
844 * Checks if the page was marked as written-to.
845 * @returns true/false.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
849
850
851/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
852 *
853 * @remarks The values are assigned in order of priority, so we can calculate
854 * the correct state for a page with different handlers installed.
855 * @{ */
856/** No handler installed. */
857#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
858/** Monitoring is temporarily disabled. */
859#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
860/** Write access is monitored. */
861#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
862/** All access is monitored. */
863#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
864/** @} */
865
866/**
867 * Gets the physical access handler state of a page.
868 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
869 * @param pPage Pointer to the physical guest page tracking structure.
870 */
871#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
872
873/**
874 * Sets the physical access handler state of a page.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 * @param _uState The new state value.
877 */
878#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
879 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
880
881/**
882 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
883 * @returns true/false
884 * @param pPage Pointer to the physical guest page tracking structure.
885 */
886#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
887
888/**
889 * Checks if the page has any active physical access handlers.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
894
895
896/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
897 *
898 * @remarks The values are assigned in order of priority, so we can calculate
899 * the correct state for a page with different handlers installed.
900 * @{ */
901/** No handler installed. */
902#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
903/* 1 is reserved so the lineup is identical with the physical ones. */
904/** Write access is monitored. */
905#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
906/** All access is monitored. */
907#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
908/** @} */
909
910/**
911 * Gets the virtual access handler state of a page.
912 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
913 * @param pPage Pointer to the physical guest page tracking structure.
914 */
915#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
916
917/**
918 * Sets the virtual access handler state of a page.
919 * @param pPage Pointer to the physical guest page tracking structure.
920 * @param _uState The new state value.
921 */
922#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
923 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
924
925/**
926 * Checks if the page has any virtual access handlers.
927 * @returns true/false
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
931
932/**
933 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
934 * virtual handlers.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
939
940
941
942/**
943 * Checks if the page has any access handlers, including temporarily disabled ones.
944 * @returns true/false
945 * @param pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
948 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
949 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951/**
952 * Checks if the page has any active access handlers.
953 * @returns true/false
954 * @param pPage Pointer to the physical guest page tracking structure.
955 */
956#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
957 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
958 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
959
960/**
961 * Checks if the page has any active access handlers catching all accesses.
962 * @returns true/false
963 * @param pPage Pointer to the physical guest page tracking structure.
964 */
965#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
967 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
968
969
970
971
972/** @def PGM_PAGE_GET_TRACKING
973 * Gets the packed shadow page pool tracking data associated with a guest page.
974 * @returns uint16_t containing the data.
975 * @param pPage Pointer to the physical guest page tracking structure.
976 */
977#define PGM_PAGE_GET_TRACKING(pPage) \
978 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
979
980/** @def PGM_PAGE_SET_TRACKING
981 * Sets the packed shadow page pool tracking data associated with a guest page.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 * @param u16TrackingData The tracking data to store.
984 */
985#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
986 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
987
988/** @def PGM_PAGE_GET_TD_CREFS
989 * Gets the @a cRefs tracking data member.
990 * @returns cRefs.
991 * @param pPage Pointer to the physical guest page tracking structure.
992 */
993#define PGM_PAGE_GET_TD_CREFS(pPage) \
994 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
995
996#define PGM_PAGE_GET_TD_IDX(pPage) \
997 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
998
999/**
1000 * Ram range for GC Phys to HC Phys conversion.
1001 *
1002 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1003 * conversions too, but we'll let MM handle that for now.
1004 *
1005 * This structure is used by linked lists in both GC and HC.
1006 */
1007typedef struct PGMRAMRANGE
1008{
1009 /** Pointer to the next RAM range - for R3. */
1010 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1011 /** Pointer to the next RAM range - for R0. */
1012 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1013 /** Pointer to the next RAM range - for RC. */
1014 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1015 /** Pointer alignment. */
1016 RTRCPTR RCPtrAlignment;
1017 /** Start of the range. Page aligned. */
1018 RTGCPHYS GCPhys;
1019 /** Last address in the range (inclusive). Page aligned (-1). */
1020 RTGCPHYS GCPhysLast;
1021 /** Size of the range. (Page aligned of course). */
1022 RTGCPHYS cb;
1023 /** MM_RAM_* flags */
1024 uint32_t fFlags;
1025 uint32_t u32Alignment; /**< alignment. */
1026#ifndef VBOX_WITH_NEW_PHYS_CODE
1027 /** R3 virtual lookup ranges for chunks.
1028 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1029 * @remarks This is occationally accessed from ring-0!! (not darwin) */
1030# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1031 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1032# else
1033 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1034# endif
1035#endif
1036 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1037 R3PTRTYPE(void *) pvR3;
1038 /** The range description. */
1039 R3PTRTYPE(const char *) pszDesc;
1040
1041 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1042#ifdef VBOX_WITH_NEW_PHYS_CODE
1043 uint32_t au32Reserved[2];
1044#elif HC_ARCH_BITS == 32
1045 uint32_t au32Reserved[1];
1046#endif
1047
1048 /** Array of physical guest page tracking structures. */
1049 PGMPAGE aPages[1];
1050} PGMRAMRANGE;
1051/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1052typedef PGMRAMRANGE *PPGMRAMRANGE;
1053
1054#ifndef VBOX_WITH_NEW_PHYS_CODE
1055/** Return hc ptr corresponding to the ram range and physical offset */
1056#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1057 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1058 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1059#endif
1060
1061/**
1062 * Per page tracking structure for ROM image.
1063 *
1064 * A ROM image may have a shadow page, in which case we may have
1065 * two pages backing it. This structure contains the PGMPAGE for
1066 * both while PGMRAMRANGE have a copy of the active one. It is
1067 * important that these aren't out of sync in any regard other
1068 * than page pool tracking data.
1069 */
1070typedef struct PGMROMPAGE
1071{
1072 /** The page structure for the virgin ROM page. */
1073 PGMPAGE Virgin;
1074 /** The page structure for the shadow RAM page. */
1075 PGMPAGE Shadow;
1076 /** The current protection setting. */
1077 PGMROMPROT enmProt;
1078 /** Pad the structure size to a multiple of 8. */
1079 uint32_t u32Padding;
1080} PGMROMPAGE;
1081/** Pointer to a ROM page tracking structure. */
1082typedef PGMROMPAGE *PPGMROMPAGE;
1083
1084
1085/**
1086 * A registered ROM image.
1087 *
1088 * This is needed to keep track of ROM image since they generally
1089 * intrude into a PGMRAMRANGE. It also keeps track of additional
1090 * info like the two page sets (read-only virgin and read-write shadow),
1091 * the current state of each page.
1092 *
1093 * Because access handlers cannot easily be executed in a different
1094 * context, the ROM ranges needs to be accessible and in all contexts.
1095 */
1096typedef struct PGMROMRANGE
1097{
1098 /** Pointer to the next range - R3. */
1099 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1100 /** Pointer to the next range - R0. */
1101 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1102 /** Pointer to the next range - RC. */
1103 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1104 /** Pointer alignment */
1105 RTRCPTR GCPtrAlignment;
1106 /** Address of the range. */
1107 RTGCPHYS GCPhys;
1108 /** Address of the last byte in the range. */
1109 RTGCPHYS GCPhysLast;
1110 /** Size of the range. */
1111 RTGCPHYS cb;
1112 /** The flags (PGMPHYS_ROM_FLAG_*). */
1113 uint32_t fFlags;
1114 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1115 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1116 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1117 * This is used for strictness checks. */
1118 R3PTRTYPE(const void *) pvOriginal;
1119 /** The ROM description. */
1120 R3PTRTYPE(const char *) pszDesc;
1121 /** The per page tracking structures. */
1122 PGMROMPAGE aPages[1];
1123} PGMROMRANGE;
1124/** Pointer to a ROM range. */
1125typedef PGMROMRANGE *PPGMROMRANGE;
1126
1127
1128/**
1129 * A registered MMIO2 (= Device RAM) range.
1130 *
1131 * There are a few reason why we need to keep track of these
1132 * registrations. One of them is the deregistration & cleanup
1133 * stuff, while another is that the PGMRAMRANGE associated with
1134 * such a region may have to be removed from the ram range list.
1135 *
1136 * Overlapping with a RAM range has to be 100% or none at all. The
1137 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1138 * meditation will be raised if a partial overlap or an overlap of
1139 * ROM pages is encountered. On an overlap we will free all the
1140 * existing RAM pages and put in the ram range pages instead.
1141 */
1142typedef struct PGMMMIO2RANGE
1143{
1144 /** The owner of the range. (a device) */
1145 PPDMDEVINSR3 pDevInsR3;
1146 /** Pointer to the ring-3 mapping of the allocation. */
1147 RTR3PTR pvR3;
1148 /** Pointer to the next range - R3. */
1149 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1150 /** Whether it's mapped or not. */
1151 bool fMapped;
1152 /** Whether it's overlapping or not. */
1153 bool fOverlapping;
1154 /** The PCI region number.
1155 * @remarks This ASSUMES that nobody will ever really need to have multiple
1156 * PCI devices with matching MMIO region numbers on a single device. */
1157 uint8_t iRegion;
1158 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1159 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1160 /** The associated RAM range. */
1161 PGMRAMRANGE RamRange;
1162} PGMMMIO2RANGE;
1163/** Pointer to a MMIO2 range. */
1164typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1165
1166
1167
1168
1169/**
1170 * PGMPhysRead/Write cache entry
1171 */
1172typedef struct PGMPHYSCACHEENTRY
1173{
1174 /** R3 pointer to physical page. */
1175 R3PTRTYPE(uint8_t *) pbR3;
1176 /** GC Physical address for cache entry */
1177 RTGCPHYS GCPhys;
1178#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1179 RTGCPHYS u32Padding0; /**< alignment padding. */
1180#endif
1181} PGMPHYSCACHEENTRY;
1182
1183/**
1184 * PGMPhysRead/Write cache to reduce REM memory access overhead
1185 */
1186typedef struct PGMPHYSCACHE
1187{
1188 /** Bitmap of valid cache entries */
1189 uint64_t aEntries;
1190 /** Cache entries */
1191 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1192} PGMPHYSCACHE;
1193
1194
1195/** Pointer to an allocation chunk ring-3 mapping. */
1196typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1197/** Pointer to an allocation chunk ring-3 mapping pointer. */
1198typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1199
1200/**
1201 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1202 *
1203 * The primary tree (Core) uses the chunk id as key.
1204 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1205 */
1206typedef struct PGMCHUNKR3MAP
1207{
1208 /** The key is the chunk id. */
1209 AVLU32NODECORE Core;
1210 /** The key is the ageing sequence number. */
1211 AVLLU32NODECORE AgeCore;
1212 /** The current age thingy. */
1213 uint32_t iAge;
1214 /** The current reference count. */
1215 uint32_t volatile cRefs;
1216 /** The current permanent reference count. */
1217 uint32_t volatile cPermRefs;
1218 /** The mapping address. */
1219 void *pv;
1220} PGMCHUNKR3MAP;
1221
1222/**
1223 * Allocation chunk ring-3 mapping TLB entry.
1224 */
1225typedef struct PGMCHUNKR3MAPTLBE
1226{
1227 /** The chunk id. */
1228 uint32_t volatile idChunk;
1229#if HC_ARCH_BITS == 64
1230 uint32_t u32Padding; /**< alignment padding. */
1231#endif
1232 /** The chunk map. */
1233#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1234 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1235#else
1236 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1237#endif
1238} PGMCHUNKR3MAPTLBE;
1239/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1240typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1241
1242/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1243 * @remark Must be a power of two value. */
1244#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1245
1246/**
1247 * Allocation chunk ring-3 mapping TLB.
1248 *
1249 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1250 * At first glance this might look kinda odd since AVL trees are
1251 * supposed to give the most optimial lookup times of all trees
1252 * due to their balancing. However, take a tree with 1023 nodes
1253 * in it, that's 10 levels, meaning that most searches has to go
1254 * down 9 levels before they find what they want. This isn't fast
1255 * compared to a TLB hit. There is the factor of cache misses,
1256 * and of course the problem with trees and branch prediction.
1257 * This is why we use TLBs in front of most of the trees.
1258 *
1259 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1260 * difficult when we switch to the new inlined AVL trees (from kStuff).
1261 */
1262typedef struct PGMCHUNKR3MAPTLB
1263{
1264 /** The TLB entries. */
1265 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1266} PGMCHUNKR3MAPTLB;
1267
1268/**
1269 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1270 * @returns Chunk TLB index.
1271 * @param idChunk The Chunk ID.
1272 */
1273#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1274
1275
1276/**
1277 * Ring-3 guest page mapping TLB entry.
1278 * @remarks used in ring-0 as well at the moment.
1279 */
1280typedef struct PGMPAGER3MAPTLBE
1281{
1282 /** Address of the page. */
1283 RTGCPHYS volatile GCPhys;
1284 /** The guest page. */
1285#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1286 R3PTRTYPE(PPGMPAGE) volatile pPage;
1287#else
1288 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1289#endif
1290 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1291#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1292 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1293#else
1294 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1295#endif
1296 /** The address */
1297#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1298 R3PTRTYPE(void *) volatile pv;
1299#else
1300 R3R0PTRTYPE(void *) volatile pv;
1301#endif
1302#if HC_ARCH_BITS == 32
1303 uint32_t u32Padding; /**< alignment padding. */
1304#endif
1305} PGMPAGER3MAPTLBE;
1306/** Pointer to an entry in the HC physical TLB. */
1307typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1308
1309
1310/** The number of entries in the ring-3 guest page mapping TLB.
1311 * @remarks The value must be a power of two. */
1312#define PGM_PAGER3MAPTLB_ENTRIES 64
1313
1314/**
1315 * Ring-3 guest page mapping TLB.
1316 * @remarks used in ring-0 as well at the moment.
1317 */
1318typedef struct PGMPAGER3MAPTLB
1319{
1320 /** The TLB entries. */
1321 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1322} PGMPAGER3MAPTLB;
1323/** Pointer to the ring-3 guest page mapping TLB. */
1324typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1325
1326/**
1327 * Calculates the index of the TLB entry for the specified guest page.
1328 * @returns Physical TLB index.
1329 * @param GCPhys The guest physical address.
1330 */
1331#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1332
1333
1334/**
1335 * Mapping cache usage set entry.
1336 *
1337 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1338 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1339 * cache. If it's extended to include ring-3, well, then something will
1340 * have be changed here...
1341 */
1342typedef struct PGMMAPSETENTRY
1343{
1344 /** The mapping cache index. */
1345 uint16_t iPage;
1346 /** The number of references.
1347 * The max is UINT16_MAX - 1. */
1348 uint16_t cRefs;
1349 /** Pointer to the page. */
1350 RTR0PTR pvPage;
1351 /** The physical address for this entry. */
1352 RTHCPHYS HCPhys;
1353} PGMMAPSETENTRY;
1354/** Pointer to a mapping cache usage set entry. */
1355typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1356
1357/**
1358 * Mapping cache usage set.
1359 *
1360 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1361 * done during exits / traps. The set is
1362 */
1363typedef struct PGMMAPSET
1364{
1365 /** The number of occupied entries.
1366 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1367 * dynamic mappings. */
1368 uint32_t cEntries;
1369 /** The start of the current subset.
1370 * This is UINT32_MAX if no subset is currently open. */
1371 uint32_t iSubset;
1372 /** The index of the current CPU, only valid if the set is open. */
1373 int32_t iCpu;
1374 /** The entries. */
1375 PGMMAPSETENTRY aEntries[64];
1376 /** HCPhys -> iEntry fast lookup table.
1377 * Use PGMMAPSET_HASH for hashing.
1378 * The entries may or may not be valid, check against cEntries. */
1379 uint8_t aiHashTable[128];
1380} PGMMAPSET;
1381/** Pointer to the mapping cache set. */
1382typedef PGMMAPSET *PPGMMAPSET;
1383
1384/** PGMMAPSET::cEntries value for a closed set. */
1385#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1386
1387/** Hash function for aiHashTable. */
1388#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1389
1390/** The max fill size (strict builds). */
1391#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1392
1393
1394/** @name Context neutrual page mapper TLB.
1395 *
1396 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1397 * code is writting in a kind of context neutrual way. Time will show whether
1398 * this actually makes sense or not...
1399 *
1400 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1401 * context ends up using a global mapping cache on some platforms
1402 * (darwin).
1403 *
1404 * @{ */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB pointer type for the current context. */
1407/** @typedef PPGMPAGEMAPTLB
1408 * The page mapper TLB entry pointer type for the current context. */
1409/** @typedef PPGMPAGEMAPTLB
1410 * The page mapper TLB entry pointer pointer type for the current context. */
1411/** @def PGM_PAGEMAPTLB_ENTRIES
1412 * The number of TLB entries in the page mapper TLB for the current context. */
1413/** @def PGM_PAGEMAPTLB_IDX
1414 * Calculate the TLB index for a guest physical address.
1415 * @returns The TLB index.
1416 * @param GCPhys The guest physical address. */
1417/** @typedef PPGMPAGEMAP
1418 * Pointer to a page mapper unit for current context. */
1419/** @typedef PPPGMPAGEMAP
1420 * Pointer to a page mapper unit pointer for current context. */
1421#ifdef IN_RC
1422// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1423// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1424// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1425# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1426# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1427 typedef void * PPGMPAGEMAP;
1428 typedef void ** PPPGMPAGEMAP;
1429//#elif IN_RING0
1430// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1431// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1432// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1433//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1434//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1435// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1436// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1437#else
1438 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1439 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1440 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1441# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1442# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1443 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1444 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1445#endif
1446/** @} */
1447
1448
1449/** @name PGM Pool Indexes.
1450 * Aka. the unique shadow page identifier.
1451 * @{ */
1452/** NIL page pool IDX. */
1453#define NIL_PGMPOOL_IDX 0
1454/** The first normal index. */
1455#define PGMPOOL_IDX_FIRST_SPECIAL 1
1456#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1457/** Page directory (32-bit root). */
1458#define PGMPOOL_IDX_PD 1
1459/** Page Directory Pointer Table (PAE root). */
1460#define PGMPOOL_IDX_PDPT 2
1461/** AMD64 CR3 level index.*/
1462#define PGMPOOL_IDX_AMD64_CR3 3
1463/** Nested paging root.*/
1464#define PGMPOOL_IDX_NESTED_ROOT 4
1465/** The first normal index. */
1466#define PGMPOOL_IDX_FIRST 5
1467#else
1468/** Page directory (32-bit root). */
1469#define PGMPOOL_IDX_PD 1
1470/** The extended PAE page directory (2048 entries, works as root currently). */
1471#define PGMPOOL_IDX_PAE_PD 2
1472/** PAE Page Directory Table 0. */
1473#define PGMPOOL_IDX_PAE_PD_0 3
1474/** PAE Page Directory Table 1. */
1475#define PGMPOOL_IDX_PAE_PD_1 4
1476/** PAE Page Directory Table 2. */
1477#define PGMPOOL_IDX_PAE_PD_2 5
1478/** PAE Page Directory Table 3. */
1479#define PGMPOOL_IDX_PAE_PD_3 6
1480/** Page Directory Pointer Table (PAE root, not currently used). */
1481#define PGMPOOL_IDX_PDPT 7
1482/** AMD64 CR3 level index.*/
1483#define PGMPOOL_IDX_AMD64_CR3 8
1484/** Nested paging root.*/
1485#define PGMPOOL_IDX_NESTED_ROOT 9
1486/** The first normal index. */
1487#define PGMPOOL_IDX_FIRST 10
1488#endif
1489/** The last valid index. (inclusive, 14 bits) */
1490#define PGMPOOL_IDX_LAST 0x3fff
1491/** @} */
1492
1493/** The NIL index for the parent chain. */
1494#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1495
1496/**
1497 * Node in the chain linking a shadowed page to it's parent (user).
1498 */
1499#pragma pack(1)
1500typedef struct PGMPOOLUSER
1501{
1502 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1503 uint16_t iNext;
1504 /** The user page index. */
1505 uint16_t iUser;
1506 /** Index into the user table. */
1507 uint32_t iUserTable;
1508} PGMPOOLUSER, *PPGMPOOLUSER;
1509typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1510#pragma pack()
1511
1512
1513/** The NIL index for the phys ext chain. */
1514#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1515
1516/**
1517 * Node in the chain of physical cross reference extents.
1518 * @todo Calling this an 'extent' is not quite right, find a better name.
1519 */
1520#pragma pack(1)
1521typedef struct PGMPOOLPHYSEXT
1522{
1523 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1524 uint16_t iNext;
1525 /** The user page index. */
1526 uint16_t aidx[3];
1527} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1528typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1529#pragma pack()
1530
1531
1532/**
1533 * The kind of page that's being shadowed.
1534 */
1535typedef enum PGMPOOLKIND
1536{
1537 /** The virtual invalid 0 entry. */
1538 PGMPOOLKIND_INVALID = 0,
1539 /** The entry is free (=unused). */
1540 PGMPOOLKIND_FREE,
1541
1542 /** Shw: 32-bit page table; Gst: no paging */
1543 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1544 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1545 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1546 /** Shw: 32-bit page table; Gst: 4MB page. */
1547 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1548 /** Shw: PAE page table; Gst: no paging */
1549 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1550 /** Shw: PAE page table; Gst: 32-bit page table. */
1551 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1552 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1553 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1554 /** Shw: PAE page table; Gst: PAE page table. */
1555 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1556 /** Shw: PAE page table; Gst: 2MB page. */
1557 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1558
1559 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1560 PGMPOOLKIND_32BIT_PD,
1561 /** Shw: 32-bit page directory. Gst: no paging. */
1562 PGMPOOLKIND_32BIT_PD_PHYS,
1563 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1564 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1565 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1566 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1567 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1568 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1569 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1570 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1571 /** Shw: PAE page directory; Gst: PAE page directory. */
1572 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1573 /** Shw: PAE page directory; Gst: no paging. */
1574 PGMPOOLKIND_PAE_PD_PHYS,
1575
1576 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1577 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1578 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1579 PGMPOOLKIND_PAE_PDPT,
1580 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1581 PGMPOOLKIND_PAE_PDPT_PHYS,
1582
1583 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1584 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1585 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1586 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1587 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1588 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1589 /** Shw: 64-bit page directory table; Gst: no paging */
1590 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1591
1592 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1593 PGMPOOLKIND_64BIT_PML4,
1594
1595 /** Shw: EPT page directory pointer table; Gst: no paging */
1596 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1597 /** Shw: EPT page directory table; Gst: no paging */
1598 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1599 /** Shw: EPT page table; Gst: no paging */
1600 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1601
1602#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1603 /** Shw: Root 32-bit page directory. */
1604 PGMPOOLKIND_ROOT_32BIT_PD,
1605 /** Shw: Root PAE page directory */
1606 PGMPOOLKIND_ROOT_PAE_PD,
1607 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1608 PGMPOOLKIND_ROOT_PDPT,
1609#endif
1610 /** Shw: Root Nested paging table. */
1611 PGMPOOLKIND_ROOT_NESTED,
1612
1613 /** The last valid entry. */
1614 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1615} PGMPOOLKIND;
1616
1617
1618/**
1619 * The tracking data for a page in the pool.
1620 */
1621typedef struct PGMPOOLPAGE
1622{
1623 /** AVL node code with the (R3) physical address of this page. */
1624 AVLOHCPHYSNODECORE Core;
1625 /** Pointer to the R3 mapping of the page. */
1626#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1627 R3PTRTYPE(void *) pvPageR3;
1628#else
1629 R3R0PTRTYPE(void *) pvPageR3;
1630#endif
1631 /** The guest physical address. */
1632#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1633 uint32_t Alignment0;
1634#endif
1635 RTGCPHYS GCPhys;
1636 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1637 uint8_t enmKind;
1638 uint8_t bPadding;
1639 /** The index of this page. */
1640 uint16_t idx;
1641 /** The next entry in the list this page currently resides in.
1642 * It's either in the free list or in the GCPhys hash. */
1643 uint16_t iNext;
1644#ifdef PGMPOOL_WITH_USER_TRACKING
1645 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1646 uint16_t iUserHead;
1647 /** The number of present entries. */
1648 uint16_t cPresent;
1649 /** The first entry in the table which is present. */
1650 uint16_t iFirstPresent;
1651#endif
1652#ifdef PGMPOOL_WITH_MONITORING
1653 /** The number of modifications to the monitored page. */
1654 uint16_t cModifications;
1655 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1656 uint16_t iModifiedNext;
1657 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1658 uint16_t iModifiedPrev;
1659 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1660 uint16_t iMonitoredNext;
1661 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1662 uint16_t iMonitoredPrev;
1663#endif
1664#ifdef PGMPOOL_WITH_CACHE
1665 /** The next page in the age list. */
1666 uint16_t iAgeNext;
1667 /** The previous page in the age list. */
1668 uint16_t iAgePrev;
1669#endif /* PGMPOOL_WITH_CACHE */
1670 /** Used to indicate that the page is zeroed. */
1671 bool fZeroed;
1672 /** Used to indicate that a PT has non-global entries. */
1673 bool fSeenNonGlobal;
1674 /** Used to indicate that we're monitoring writes to the guest page. */
1675 bool fMonitored;
1676 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1677 * (All pages are in the age list.) */
1678 bool fCached;
1679 /** This is used by the R3 access handlers when invoked by an async thread.
1680 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1681 bool volatile fReusedFlushPending;
1682#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1683 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1684 bool fLocked;
1685#else
1686 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1687 * In these cases the access handler acts differently and will check
1688 * for mapping conflicts like the normal CR3 handler.
1689 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1690 * replaced by a list of pages which share access handler.
1691 */
1692 bool fCR3Mix;
1693#endif
1694} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1695
1696
1697#ifdef PGMPOOL_WITH_CACHE
1698/** The hash table size. */
1699# define PGMPOOL_HASH_SIZE 0x40
1700/** The hash function. */
1701# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1702#endif
1703
1704
1705/**
1706 * The shadow page pool instance data.
1707 *
1708 * It's all one big allocation made at init time, except for the
1709 * pages that is. The user nodes follows immediatly after the
1710 * page structures.
1711 */
1712typedef struct PGMPOOL
1713{
1714 /** The VM handle - R3 Ptr. */
1715 PVMR3 pVMR3;
1716 /** The VM handle - R0 Ptr. */
1717 PVMR0 pVMR0;
1718 /** The VM handle - RC Ptr. */
1719 PVMRC pVMRC;
1720 /** The max pool size. This includes the special IDs. */
1721 uint16_t cMaxPages;
1722 /** The current pool size. */
1723 uint16_t cCurPages;
1724 /** The head of the free page list. */
1725 uint16_t iFreeHead;
1726 /* Padding. */
1727 uint16_t u16Padding;
1728#ifdef PGMPOOL_WITH_USER_TRACKING
1729 /** Head of the chain of free user nodes. */
1730 uint16_t iUserFreeHead;
1731 /** The number of user nodes we've allocated. */
1732 uint16_t cMaxUsers;
1733 /** The number of present page table entries in the entire pool. */
1734 uint32_t cPresent;
1735 /** Pointer to the array of user nodes - RC pointer. */
1736 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1737 /** Pointer to the array of user nodes - R3 pointer. */
1738 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1739 /** Pointer to the array of user nodes - R0 pointer. */
1740 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1741#endif /* PGMPOOL_WITH_USER_TRACKING */
1742#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1743 /** Head of the chain of free phys ext nodes. */
1744 uint16_t iPhysExtFreeHead;
1745 /** The number of user nodes we've allocated. */
1746 uint16_t cMaxPhysExts;
1747 /** Pointer to the array of physical xref extent - RC pointer. */
1748 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1749 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1750 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1751 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1752 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1753#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1754#ifdef PGMPOOL_WITH_CACHE
1755 /** Hash table for GCPhys addresses. */
1756 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1757 /** The head of the age list. */
1758 uint16_t iAgeHead;
1759 /** The tail of the age list. */
1760 uint16_t iAgeTail;
1761 /** Set if the cache is enabled. */
1762 bool fCacheEnabled;
1763#endif /* PGMPOOL_WITH_CACHE */
1764#ifdef PGMPOOL_WITH_MONITORING
1765 /** Head of the list of modified pages. */
1766 uint16_t iModifiedHead;
1767 /** The current number of modified pages. */
1768 uint16_t cModifiedPages;
1769 /** Access handler, RC. */
1770 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1771 /** Access handler, R0. */
1772 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1773 /** Access handler, R3. */
1774 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1775 /** The access handler description (HC ptr). */
1776 R3PTRTYPE(const char *) pszAccessHandler;
1777#endif /* PGMPOOL_WITH_MONITORING */
1778 /** The number of pages currently in use. */
1779 uint16_t cUsedPages;
1780#ifdef VBOX_WITH_STATISTICS
1781 /** The high wather mark for cUsedPages. */
1782 uint16_t cUsedPagesHigh;
1783 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1784 /** Profiling pgmPoolAlloc(). */
1785 STAMPROFILEADV StatAlloc;
1786 /** Profiling pgmPoolClearAll(). */
1787 STAMPROFILE StatClearAll;
1788 /** Profiling pgmPoolFlushAllInt(). */
1789 STAMPROFILE StatFlushAllInt;
1790 /** Profiling pgmPoolFlushPage(). */
1791 STAMPROFILE StatFlushPage;
1792 /** Profiling pgmPoolFree(). */
1793 STAMPROFILE StatFree;
1794 /** Profiling time spent zeroing pages. */
1795 STAMPROFILE StatZeroPage;
1796# ifdef PGMPOOL_WITH_USER_TRACKING
1797 /** Profiling of pgmPoolTrackDeref. */
1798 STAMPROFILE StatTrackDeref;
1799 /** Profiling pgmTrackFlushGCPhysPT. */
1800 STAMPROFILE StatTrackFlushGCPhysPT;
1801 /** Profiling pgmTrackFlushGCPhysPTs. */
1802 STAMPROFILE StatTrackFlushGCPhysPTs;
1803 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1804 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1805 /** Number of times we've been out of user records. */
1806 STAMCOUNTER StatTrackFreeUpOneUser;
1807# endif
1808# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1809 /** Profiling deref activity related tracking GC physical pages. */
1810 STAMPROFILE StatTrackDerefGCPhys;
1811 /** Number of linear searches for a HCPhys in the ram ranges. */
1812 STAMCOUNTER StatTrackLinearRamSearches;
1813 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1814 STAMCOUNTER StamTrackPhysExtAllocFailures;
1815# endif
1816# ifdef PGMPOOL_WITH_MONITORING
1817 /** Profiling the RC/R0 access handler. */
1818 STAMPROFILE StatMonitorRZ;
1819 /** Times we've failed interpreting the instruction. */
1820 STAMCOUNTER StatMonitorRZEmulateInstr;
1821 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1822 STAMPROFILE StatMonitorRZFlushPage;
1823 /** Times we've detected fork(). */
1824 STAMCOUNTER StatMonitorRZFork;
1825 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1826 STAMPROFILE StatMonitorRZHandled;
1827 /** Times we've failed interpreting a patch code instruction. */
1828 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1829 /** Times we've failed interpreting a patch code instruction during flushing. */
1830 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1831 /** The number of times we've seen rep prefixes we can't handle. */
1832 STAMCOUNTER StatMonitorRZRepPrefix;
1833 /** Profiling the REP STOSD cases we've handled. */
1834 STAMPROFILE StatMonitorRZRepStosd;
1835
1836 /** Profiling the R3 access handler. */
1837 STAMPROFILE StatMonitorR3;
1838 /** Times we've failed interpreting the instruction. */
1839 STAMCOUNTER StatMonitorR3EmulateInstr;
1840 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1841 STAMPROFILE StatMonitorR3FlushPage;
1842 /** Times we've detected fork(). */
1843 STAMCOUNTER StatMonitorR3Fork;
1844 /** Profiling the R3 access we've handled (except REP STOSD). */
1845 STAMPROFILE StatMonitorR3Handled;
1846 /** The number of times we've seen rep prefixes we can't handle. */
1847 STAMCOUNTER StatMonitorR3RepPrefix;
1848 /** Profiling the REP STOSD cases we've handled. */
1849 STAMPROFILE StatMonitorR3RepStosd;
1850 /** The number of times we're called in an async thread an need to flush. */
1851 STAMCOUNTER StatMonitorR3Async;
1852 /** The high wather mark for cModifiedPages. */
1853 uint16_t cModifiedPagesHigh;
1854 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1855# endif
1856# ifdef PGMPOOL_WITH_CACHE
1857 /** The number of cache hits. */
1858 STAMCOUNTER StatCacheHits;
1859 /** The number of cache misses. */
1860 STAMCOUNTER StatCacheMisses;
1861 /** The number of times we've got a conflict of 'kind' in the cache. */
1862 STAMCOUNTER StatCacheKindMismatches;
1863 /** Number of times we've been out of pages. */
1864 STAMCOUNTER StatCacheFreeUpOne;
1865 /** The number of cacheable allocations. */
1866 STAMCOUNTER StatCacheCacheable;
1867 /** The number of uncacheable allocations. */
1868 STAMCOUNTER StatCacheUncacheable;
1869# endif
1870#elif HC_ARCH_BITS == 64
1871 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1872#endif
1873 /** The AVL tree for looking up a page by its HC physical address. */
1874 AVLOHCPHYSTREE HCPhysTree;
1875 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1876 /** Array of pages. (cMaxPages in length)
1877 * The Id is the index into thist array.
1878 */
1879 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1880} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1881
1882
1883/** @def PGMPOOL_PAGE_2_PTR
1884 * Maps a pool page pool into the current context.
1885 *
1886 * @returns VBox status code.
1887 * @param pVM The VM handle.
1888 * @param pPage The pool page.
1889 *
1890 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1891 * small page window employeed by that function. Be careful.
1892 * @remark There is no need to assert on the result.
1893 */
1894#if defined(IN_RC)
1895# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1896#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1897# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1898#elif defined(VBOX_STRICT)
1899# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1900DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1901{
1902 Assert(pPage->pvPageR3);
1903 return pPage->pvPageR3;
1904}
1905#else
1906# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1907#endif
1908
1909/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1910 * Maps a pool page pool into the current context.
1911 *
1912 * @returns VBox status code.
1913 * @param pPGM Pointer to the PGM instance data.
1914 * @param pPage The pool page.
1915 *
1916 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1917 * small page window employeed by that function. Be careful.
1918 * @remark There is no need to assert on the result.
1919 */
1920#if defined(IN_RC)
1921# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1922#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1923# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1924#else
1925# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1926#endif
1927
1928
1929/** @name Per guest page tracking data.
1930 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1931 * is to use more bits for it and split it up later on. But for now we'll play
1932 * safe and change as little as possible.
1933 *
1934 * The 16-bit word has two parts:
1935 *
1936 * The first 14-bit forms the @a idx field. It is either the index of a page in
1937 * the shadow page pool, or and index into the extent list.
1938 *
1939 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1940 * shadow page pool references to the page. If cRefs equals
1941 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1942 * (misnomer) table and not the shadow page pool.
1943 *
1944 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1945 * the 16-bit word.
1946 *
1947 * @{ */
1948/** The shift count for getting to the cRefs part. */
1949#define PGMPOOL_TD_CREFS_SHIFT 14
1950/** The mask applied after shifting the tracking data down by
1951 * PGMPOOL_TD_CREFS_SHIFT. */
1952#define PGMPOOL_TD_CREFS_MASK 0x3
1953/** The cRef value used to indiciate that the idx is the head of a
1954 * physical cross reference list. */
1955#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1956/** The shift used to get idx. */
1957#define PGMPOOL_TD_IDX_SHIFT 0
1958/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1959#define PGMPOOL_TD_IDX_MASK 0x3fff
1960/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1961 * simply too many mappings of this page. */
1962#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1963
1964/** @def PGMPOOL_TD_MAKE
1965 * Makes a 16-bit tracking data word.
1966 *
1967 * @returns tracking data.
1968 * @param cRefs The @a cRefs field. Must be within bounds!
1969 * @param idx The @a idx field. Must also be within bounds! */
1970#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1971
1972/** @def PGMPOOL_TD_GET_CREFS
1973 * Get the @a cRefs field from a tracking data word.
1974 *
1975 * @returns The @a cRefs field
1976 * @param u16 The tracking data word. */
1977#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1978
1979/** @def PGMPOOL_TD_GET_IDX
1980 * Get the @a idx field from a tracking data word.
1981 *
1982 * @returns The @a idx field
1983 * @param u16 The tracking data word. */
1984#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1985/** @} */
1986
1987
1988/**
1989 * Trees are using self relative offsets as pointers.
1990 * So, all its data, including the root pointer, must be in the heap for HC and GC
1991 * to have the same layout.
1992 */
1993typedef struct PGMTREES
1994{
1995 /** Physical access handlers (AVL range+offsetptr tree). */
1996 AVLROGCPHYSTREE PhysHandlers;
1997 /** Virtual access handlers (AVL range + GC ptr tree). */
1998 AVLROGCPTRTREE VirtHandlers;
1999 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2000 AVLROGCPHYSTREE PhysToVirtHandlers;
2001 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2002 AVLROGCPTRTREE HyperVirtHandlers;
2003} PGMTREES;
2004/** Pointer to PGM trees. */
2005typedef PGMTREES *PPGMTREES;
2006
2007
2008/** @name Paging mode macros
2009 * @{ */
2010#ifdef IN_RC
2011# define PGM_CTX(a,b) a##RC##b
2012# define PGM_CTX_STR(a,b) a "GC" b
2013# define PGM_CTX_DECL(type) VMMRCDECL(type)
2014#else
2015# ifdef IN_RING3
2016# define PGM_CTX(a,b) a##R3##b
2017# define PGM_CTX_STR(a,b) a "R3" b
2018# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2019# else
2020# define PGM_CTX(a,b) a##R0##b
2021# define PGM_CTX_STR(a,b) a "R0" b
2022# define PGM_CTX_DECL(type) VMMDECL(type)
2023# endif
2024#endif
2025
2026#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2027#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2028#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2029#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2030#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2031#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2032#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2033#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2034#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2035#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2036#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2037#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2038#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2039#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2040#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2041#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2042#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2043
2044#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2045#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2046#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2047#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2048#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2049#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2050#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2051#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2052#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2053#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2054#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2055#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2056#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2057#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2058#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2059#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2060#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2061
2062/* Shw_Gst */
2063#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2064#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2065#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2066#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2067#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2068#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2069#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2070#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2071#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2072#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2073#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2074#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2075#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2076#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2077#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2078#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2079#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2080#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2081#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2082
2083#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2084#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2085#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2086#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2087#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2088#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2089#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2090#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2091#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2092#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2093#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2094#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2095#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2096#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2097#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2098#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2099#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2100#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2101#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2102#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2103#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2104#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2105#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2106#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2107#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2108#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2109#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2110#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2111#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2112#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2113#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2114#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2115#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2116#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2117#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2118#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2119#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2120
2121#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2122#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2123/** @} */
2124
2125/**
2126 * Data for each paging mode.
2127 */
2128typedef struct PGMMODEDATA
2129{
2130 /** The guest mode type. */
2131 uint32_t uGstType;
2132 /** The shadow mode type. */
2133 uint32_t uShwType;
2134
2135 /** @name Function pointers for Shadow paging.
2136 * @{
2137 */
2138 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2139 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2140 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2141 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2142
2143 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2144 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2145
2146 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2147 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2148 /** @} */
2149
2150 /** @name Function pointers for Guest paging.
2151 * @{
2152 */
2153 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2154 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2155 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2156 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2157 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2158#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2159 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2160 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2161#endif
2162#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2163 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2164 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2165 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2166 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2167#endif
2168 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2169 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2170 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2171#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2172 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2173 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2174#endif
2175#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2176 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2177 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2178#endif
2179 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2180 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2181 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2182#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2183 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2184 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2185#endif
2186#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2187 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2188 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2189#endif
2190 /** @} */
2191
2192 /** @name Function pointers for Both Shadow and Guest paging.
2193 * @{
2194 */
2195 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2196 /* no pfnR3BthTrap0eHandler */
2197 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2198 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2199 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2200 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2202#ifdef VBOX_STRICT
2203 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2204#endif
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2207
2208 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2209 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2210 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2211 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2212 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2213 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2214#ifdef VBOX_STRICT
2215 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2216#endif
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2219
2220 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2221 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2222 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2223 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2224 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2225 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2226#ifdef VBOX_STRICT
2227 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2228#endif
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2231 /** @} */
2232} PGMMODEDATA, *PPGMMODEDATA;
2233
2234
2235
2236/**
2237 * Converts a PGM pointer into a VM pointer.
2238 * @returns Pointer to the VM structure the PGM is part of.
2239 * @param pPGM Pointer to PGM instance data.
2240 */
2241#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2242
2243/**
2244 * PGM Data (part of VM)
2245 */
2246typedef struct PGM
2247{
2248 /** Offset to the VM structure. */
2249 RTINT offVM;
2250 /** Offset of the PGMCPU structure relative to VMCPU. */
2251 int32_t offVCpu;
2252 /** @cfgm{PGM/RamPreAlloc, bool, false}
2253 * Whether to preallocate all the guest RAM or not. */
2254 bool fRamPreAlloc;
2255 /** Alignment padding. */
2256 bool afAlignment0[3];
2257
2258
2259 /*
2260 * This will be redefined at least two more times before we're done, I'm sure.
2261 * The current code is only to get on with the coding.
2262 * - 2004-06-10: initial version, bird.
2263 * - 2004-07-02: 1st time, bird.
2264 * - 2004-10-18: 2nd time, bird.
2265 * - 2005-07-xx: 3rd time, bird.
2266 */
2267
2268 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2269 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2270 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2271 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2272
2273 /** The host paging mode. (This is what SUPLib reports.) */
2274 SUPPAGINGMODE enmHostMode;
2275 /** The shadow paging mode. */
2276 PGMMODE enmShadowMode;
2277 /** The guest paging mode. */
2278 PGMMODE enmGuestMode;
2279
2280 /** The current physical address representing in the guest CR3 register. */
2281 RTGCPHYS GCPhysCR3;
2282 /** Pointer to the 5 page CR3 content mapping.
2283 * The first page is always the CR3 (in some form) while the 4 other pages
2284 * are used of the PDs in PAE mode. */
2285 RTGCPTR GCPtrCR3Mapping;
2286#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2287 uint32_t u32Alignment;
2288#endif
2289#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2290 /** The physical address of the currently monitored guest CR3 page.
2291 * When this value is NIL_RTGCPHYS no page is being monitored. */
2292 RTGCPHYS GCPhysGstCR3Monitored;
2293#endif
2294 /** @name 32-bit Guest Paging.
2295 * @{ */
2296 /** The guest's page directory, R3 pointer. */
2297 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2298#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2299 /** The guest's page directory, R0 pointer. */
2300 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2301#endif
2302 /** The guest's page directory, static RC mapping. */
2303 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2304 /** @} */
2305
2306 /** @name PAE Guest Paging.
2307 * @{ */
2308 /** The guest's page directory pointer table, static RC mapping. */
2309 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2310 /** The guest's page directory pointer table, R3 pointer. */
2311 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2312#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2313 /** The guest's page directory pointer table, R0 pointer. */
2314 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2315#endif
2316
2317 /** The guest's page directories, R3 pointers.
2318 * These are individual pointers and don't have to be adjecent.
2319 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2320 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2321 /** The guest's page directories, R0 pointers.
2322 * Same restrictions as apGstPaePDsR3. */
2323#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2324 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2325#endif
2326 /** The guest's page directories, static GC mapping.
2327 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2328 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2329 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2330 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2331 RTGCPHYS aGCPhysGstPaePDs[4];
2332 /** The physical addresses of the monitored guest page directories (PAE). */
2333 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2334 /** @} */
2335
2336 /** @name AMD64 Guest Paging.
2337 * @{ */
2338 /** The guest's page directory pointer table, R3 pointer. */
2339 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2340#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2341 /** The guest's page directory pointer table, R0 pointer. */
2342 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2343#endif
2344 /** @} */
2345
2346 /** @name Shadow paging
2347 * @{ */
2348 /** The root page table - R3 Ptr. */
2349 R3PTRTYPE(void *) pShwRootR3;
2350# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2351 /** The root page table - R0 Ptr. */
2352 R0PTRTYPE(void *) pShwRootR0;
2353# endif
2354 /** The root page table - RC Ptr. */
2355 RCPTRTYPE(void *) pShwRootRC;
2356# if HC_ARCH_BITS == 64
2357 uint32_t u32Padding1; /**< alignment padding. */
2358# endif
2359 /** The Physical Address (HC) of the current active shadow CR3. */
2360 RTHCPHYS HCPhysShwCR3;
2361 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2362 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2363 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2364 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2365 /** Pointer to the page of the current active CR3 - RC Ptr. */
2366 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2367 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2368 uint32_t iShwUser;
2369 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2370 uint32_t iShwUserTable;
2371# if HC_ARCH_BITS == 64
2372 RTRCPTR alignment6; /**< structure size alignment. */
2373# endif
2374 /** @} */
2375#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2376 /** @name 32-bit Shadow Paging
2377 * @{ */
2378 /** The 32-Bit PD - R3 Ptr. */
2379 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2380 /** The 32-Bit PD - R0 Ptr. */
2381 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2382 /** The 32-Bit PD - RC Ptr. */
2383 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2384# if HC_ARCH_BITS == 64
2385 uint32_t u32Padding10; /**< alignment padding. */
2386# endif
2387 /** The Physical Address (HC) of the 32-Bit PD. */
2388 RTHCPHYS HCPhysShw32BitPD;
2389 /** @} */
2390
2391 /** @name PAE Shadow Paging
2392 * @{ */
2393 /** The four PDs for the low 4GB - R3 Ptr.
2394 * Even though these are 4 pointers, what they point at is a single table.
2395 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2396 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2397# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2398 /** The four PDs for the low 4GB - R0 Ptr.
2399 * Same kind of mapping as apHCPaePDs. */
2400 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2401# endif
2402 /** The four PDs for the low 4GB - RC Ptr.
2403 * Same kind of mapping as apHCPaePDs. */
2404 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2405 /** The Physical Address (HC) of the four PDs for the low 4GB.
2406 * These are *NOT* 4 contiguous pages. */
2407 RTHCPHYS aHCPhysPaePDs[4];
2408 /** The Physical Address (HC) of the PAE PDPT. */
2409 RTHCPHYS HCPhysShwPaePdpt;
2410 /** The PAE PDPT - R3 Ptr. */
2411 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2412 /** The PAE PDPT - R0 Ptr. */
2413 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2414 /** The PAE PDPT - RC Ptr. */
2415 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2416 /** @} */
2417# if HC_ARCH_BITS == 64
2418 RTRCPTR alignment5; /**< structure size alignment. */
2419# endif
2420#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2421 /** @name Nested Shadow Paging
2422 * @{ */
2423 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2424 RTR3PTR pShwNestedRootR3;
2425# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2426 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2427 RTR0PTR pShwNestedRootR0;
2428# endif
2429 /** The Physical Address (HC) of the nested paging root. */
2430 RTHCPHYS HCPhysShwNestedRoot;
2431 /** @} */
2432
2433 /** @name Function pointers for Shadow paging.
2434 * @{
2435 */
2436 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2437 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2438 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2439 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2440
2441 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2442 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2443
2444 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2445 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2446
2447 /** @} */
2448
2449 /** @name Function pointers for Guest paging.
2450 * @{
2451 */
2452 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2453 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2454 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2455 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2456 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2457#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2458 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2459 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2460#endif
2461#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2462 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2463 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2464 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2465 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2466#endif
2467 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2468 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2469 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2470#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2471 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2472 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2473#endif
2474#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2475 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2476 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2477#endif
2478#if HC_ARCH_BITS == 64
2479 RTRCPTR alignment3; /**< structure size alignment. */
2480#endif
2481
2482 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2483 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2484 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2485#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2486 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2487 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2488#endif
2489#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2490 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2491 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2492#endif
2493 /** @} */
2494
2495 /** @name Function pointers for Both Shadow and Guest paging.
2496 * @{
2497 */
2498 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2499 /* no pfnR3BthTrap0eHandler */
2500 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2501 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2502 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2503 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2504 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2505 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2506 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2507 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2508
2509 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2510 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2511 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2512 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2513 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2514 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2515 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2516 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2517 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2518
2519 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2520 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2521 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2522 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2523 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2524 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2525 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2526 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2527 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2528#if HC_ARCH_BITS == 64
2529 RTRCPTR alignment2; /**< structure size alignment. */
2530#endif
2531 /** @} */
2532
2533 /** Pointer to SHW+GST mode data (function pointers).
2534 * The index into this table is made up from */
2535 R3PTRTYPE(PPGMMODEDATA) paModeData;
2536
2537 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2538 * This is sorted by physical address and contains no overlapping ranges. */
2539 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2540 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2541 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2542 /** RC pointer corresponding to PGM::pRamRangesR3. */
2543 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2544 /** The configured RAM size. */
2545 RTUINT cbRamSize;
2546
2547 /** Pointer to the list of ROM ranges - for R3.
2548 * This is sorted by physical address and contains no overlapping ranges. */
2549 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2550 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2551 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2552 /** RC pointer corresponding to PGM::pRomRangesR3. */
2553 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2554 /** Alignment padding. */
2555 RTRCPTR GCPtrPadding2;
2556
2557 /** Pointer to the list of MMIO2 ranges - for R3.
2558 * Registration order. */
2559 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2560
2561 /** PGM offset based trees - R3 Ptr. */
2562 R3PTRTYPE(PPGMTREES) pTreesR3;
2563 /** PGM offset based trees - R0 Ptr. */
2564 R0PTRTYPE(PPGMTREES) pTreesR0;
2565 /** PGM offset based trees - RC Ptr. */
2566 RCPTRTYPE(PPGMTREES) pTreesRC;
2567
2568 /** Linked list of GC mappings - for RC.
2569 * The list is sorted ascending on address.
2570 */
2571 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2572 /** Linked list of GC mappings - for HC.
2573 * The list is sorted ascending on address.
2574 */
2575 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2576 /** Linked list of GC mappings - for R0.
2577 * The list is sorted ascending on address.
2578 */
2579 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2580
2581 /** Indicates that PGMR3FinalizeMappings has been called and that further
2582 * PGMR3MapIntermediate calls will be rejected. */
2583 bool fFinalizedMappings;
2584 /** If set no conflict checks are required. (boolean) */
2585 bool fMappingsFixed;
2586 /** If set, then no mappings are put into the shadow page table. (boolean) */
2587 bool fDisableMappings;
2588 /** Size of fixed mapping */
2589 uint32_t cbMappingFixed;
2590 /** Base address (GC) of fixed mapping */
2591 RTGCPTR GCPtrMappingFixed;
2592#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2593 uint32_t u32Padding0; /**< alignment padding. */
2594#endif
2595
2596
2597 /** @name Intermediate Context
2598 * @{ */
2599 /** Pointer to the intermediate page directory - Normal. */
2600 R3PTRTYPE(PX86PD) pInterPD;
2601 /** Pointer to the intermedate page tables - Normal.
2602 * There are two page tables, one for the identity mapping and one for
2603 * the host context mapping (of the core code). */
2604 R3PTRTYPE(PX86PT) apInterPTs[2];
2605 /** Pointer to the intermedate page tables - PAE. */
2606 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2607 /** Pointer to the intermedate page directory - PAE. */
2608 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2609 /** Pointer to the intermedate page directory - PAE. */
2610 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2611 /** Pointer to the intermedate page-map level 4 - AMD64. */
2612 R3PTRTYPE(PX86PML4) pInterPaePML4;
2613 /** Pointer to the intermedate page directory - AMD64. */
2614 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2615 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2616 RTHCPHYS HCPhysInterPD;
2617 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2618 RTHCPHYS HCPhysInterPaePDPT;
2619 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2620 RTHCPHYS HCPhysInterPaePML4;
2621 /** @} */
2622
2623 /** Base address of the dynamic page mapping area.
2624 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2625 */
2626 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2627 /** The index of the last entry used in the dynamic page mapping area. */
2628 RTUINT iDynPageMapLast;
2629 /** Cache containing the last entries in the dynamic page mapping area.
2630 * The cache size is covering half of the mapping area. */
2631 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2632 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2633
2634 /** The address of the ring-0 mapping cache if we're making use of it. */
2635 RTR0PTR pvR0DynMapUsed;
2636#if HC_ARCH_BITS == 32
2637 RTR0PTR R0PtrPadding0; /**< Alignment. */
2638#endif
2639
2640
2641 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2642 RTGCPHYS GCPhys4MBPSEMask;
2643
2644 /** A20 gate mask.
2645 * Our current approach to A20 emulation is to let REM do it and don't bother
2646 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2647 * But whould need arrise, we'll subject physical addresses to this mask. */
2648 RTGCPHYS GCPhysA20Mask;
2649 /** A20 gate state - boolean! */
2650 RTUINT fA20Enabled;
2651
2652 /** What needs syncing (PGM_SYNC_*).
2653 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2654 * PGMFlushTLB, and PGMR3Load. */
2655 RTUINT fSyncFlags;
2656
2657 /** PGM critical section.
2658 * This protects the physical & virtual access handlers, ram ranges,
2659 * and the page flag updating (some of it anyway).
2660 */
2661 PDMCRITSECT CritSect;
2662
2663 /** Shadow Page Pool - R3 Ptr. */
2664 R3PTRTYPE(PPGMPOOL) pPoolR3;
2665 /** Shadow Page Pool - R0 Ptr. */
2666 R0PTRTYPE(PPGMPOOL) pPoolR0;
2667 /** Shadow Page Pool - RC Ptr. */
2668 RCPTRTYPE(PPGMPOOL) pPoolRC;
2669
2670 /** We're not in a state which permits writes to guest memory.
2671 * (Only used in strict builds.) */
2672 bool fNoMorePhysWrites;
2673
2674 /** Flush the cache on the next access. */
2675 bool fPhysCacheFlushPending;
2676/** @todo r=bird: Fix member names!*/
2677 /** PGMPhysRead cache */
2678 PGMPHYSCACHE pgmphysreadcache;
2679 /** PGMPhysWrite cache */
2680 PGMPHYSCACHE pgmphyswritecache;
2681
2682 /**
2683 * Data associated with managing the ring-3 mappings of the allocation chunks.
2684 */
2685 struct
2686 {
2687 /** The chunk tree, ordered by chunk id. */
2688#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2689 R3PTRTYPE(PAVLU32NODECORE) pTree;
2690#else
2691 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2692#endif
2693 /** The chunk mapping TLB. */
2694 PGMCHUNKR3MAPTLB Tlb;
2695 /** The number of mapped chunks. */
2696 uint32_t c;
2697 /** The maximum number of mapped chunks.
2698 * @cfgm PGM/MaxRing3Chunks */
2699 uint32_t cMax;
2700 /** The chunk age tree, ordered by ageing sequence number. */
2701 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2702 /** The current time. */
2703 uint32_t iNow;
2704 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2705 uint32_t AgeingCountdown;
2706 } ChunkR3Map;
2707
2708 /**
2709 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2710 */
2711 PGMPAGER3MAPTLB PhysTlbHC;
2712
2713 /** @name The zero page.
2714 * @{ */
2715 /** The host physical address of the zero page. */
2716 RTHCPHYS HCPhysZeroPg;
2717 /** The ring-3 mapping of the zero page. */
2718 RTR3PTR pvZeroPgR3;
2719 /** The ring-0 mapping of the zero page. */
2720 RTR0PTR pvZeroPgR0;
2721 /** The GC mapping of the zero page. */
2722 RTGCPTR pvZeroPgGC;
2723#if GC_ARCH_BITS != 32
2724 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2725#endif
2726 /** @}*/
2727
2728 /** The number of handy pages. */
2729 uint32_t cHandyPages;
2730 /**
2731 * Array of handy pages.
2732 *
2733 * This array is used in a two way communication between pgmPhysAllocPage
2734 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2735 * an intermediary.
2736 *
2737 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2738 * (The current size of 32 pages, means 128 KB of handy memory.)
2739 */
2740 GMMPAGEDESC aHandyPages[32];
2741
2742 /** @name Release Statistics
2743 * @{ */
2744 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2745 uint32_t cPrivatePages; /**< The number of private pages. */
2746 uint32_t cSharedPages; /**< The number of shared pages. */
2747 uint32_t cZeroPages; /**< The number of zero backed pages. */
2748 /** The number of times the guest has switched mode since last reset or statistics reset. */
2749 STAMCOUNTER cGuestModeChanges;
2750 /** The number of times we were forced to change the hypervisor region location. */
2751 STAMCOUNTER cRelocations;
2752 /** @} */
2753
2754#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2755 /** RC: Which statistic this \#PF should be attributed to. */
2756 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2757 RTRCPTR padding0;
2758 /** R0: Which statistic this \#PF should be attributed to. */
2759 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2760 RTR0PTR padding1;
2761
2762 /* Common */
2763# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2764 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2765 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2766 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2767 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2768 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2769 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2770# endif
2771 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2772 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2773
2774 /* R3 only: */
2775 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2776 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2777 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2778 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2779 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2780 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2781
2782 /* R0 only: */
2783 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2784 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2785 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2786 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2787 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2788 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2789 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2790 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2791 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2792 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2793 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2794 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2795 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2796 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2797 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2798 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2799 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2800 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2801 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2802 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2803 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2804 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2805 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2806 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2807 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2808 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2809
2810 /* RC only: */
2811 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2812 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2813 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2814 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2815
2816 /* RZ only: */
2817 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2818 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2819 STAMPROFILE StatRZTrap0eTimeSyncPT;
2820 STAMPROFILE StatRZTrap0eTimeMapping;
2821 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2822 STAMPROFILE StatRZTrap0eTimeHandlers;
2823 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2824 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2825 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2826 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2827 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2828 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2829 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2830 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2831 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2832 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2833 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2834 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2835 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2836 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2837 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2838 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2839 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2840 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2841 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2842 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2843 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2844 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2845 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2846 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2847 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2848 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2849 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2850 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2851 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2852 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2853 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2854 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2856 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2857 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2858 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2859 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2860 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2861 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2862 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2863 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2864 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2865 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2866
2867 /* HC - R3 and (maybe) R0: */
2868
2869 /* RZ & R3: */
2870 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2871 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2872 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2873 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2874 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2875 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2876 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2877 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2878 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2879 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2880 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2881 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2882 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2883 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2884 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2885 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2886 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2887 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2888 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2889 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2890 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2891 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2892 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2893 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2894 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2895 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2896 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2897 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2898 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2899 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2900 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2901 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2902 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2903 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2904 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2905 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2906 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2907 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2908 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2909 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2910 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2911 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2912 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2913 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2914 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2915 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2916 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2917/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2918 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2919 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2920 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2921 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2922 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2923 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2924
2925 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2926 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2927 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2928 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2929 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2930 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2931 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2932 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2933 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2934 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2935 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2936 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2937 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2938 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2939 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2940 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2941 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2942 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2943 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2944 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2945 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2946 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2947 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2948 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2949 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2950 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2951 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2952 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2953 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2954 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2955 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2956 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2957 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2958 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2959 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2960 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2961 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2962 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2963 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2964 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2965 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2966 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2967 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2968 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2969 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2970 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2971 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2972/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2973 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2974 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2975 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2976 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2977 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2978 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2979#endif /* VBOX_WITH_STATISTICS */
2980} PGM;
2981/** Pointer to the PGM instance data. */
2982typedef PGM *PPGM;
2983
2984
2985/**
2986 * PGMCPU Data (part of VMCPU).
2987 */
2988typedef struct PGMCPU
2989{
2990 /** Offset to the VMCPU structure. */
2991 RTINT offVMCPU;
2992 /** Automatically tracked physical memory mapping set.
2993 * Ring-0 and strict raw-mode builds. */
2994 PGMMAPSET AutoSet;
2995} PGMCPU;
2996/** Pointer to the per-cpu PGM data. */
2997typedef PGMCPU *PPGMCPU;
2998
2999
3000/** @name PGM::fSyncFlags Flags
3001 * @{
3002 */
3003/** Updates the virtual access handler state bit in PGMPAGE. */
3004#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3005/** Always sync CR3. */
3006#define PGM_SYNC_ALWAYS RT_BIT(1)
3007/** Check monitoring on next CR3 (re)load and invalidate page. */
3008#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3009/** Check guest mapping in SyncCR3. */
3010#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3011/** Clear the page pool (a light weight flush). */
3012#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
3013/** @} */
3014
3015
3016__BEGIN_DECLS
3017
3018int pgmLock(PVM pVM);
3019void pgmUnlock(PVM pVM);
3020
3021VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3022VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3023
3024int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3025int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3026PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3027void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3028DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3029
3030void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3031bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3032int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3033DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3034#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3035void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3036#else
3037# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3038#endif
3039DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3040
3041
3042int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3043int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3044int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3045int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3046int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3047int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3048int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3049int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3050#ifdef IN_RING3
3051int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3052int pgmR3PhysRamReset(PVM pVM);
3053int pgmR3PhysRomReset(PVM pVM);
3054# ifndef VBOX_WITH_NEW_PHYS_CODE
3055int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3056# endif
3057
3058int pgmR3PoolInit(PVM pVM);
3059void pgmR3PoolRelocate(PVM pVM);
3060void pgmR3PoolReset(PVM pVM);
3061
3062#endif /* IN_RING3 */
3063#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3064int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3065#endif
3066#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3067void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3068#endif
3069int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3070PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3071void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3072void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3073int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3074void pgmPoolFlushAll(PVM pVM);
3075void pgmPoolClearAll(PVM pVM);
3076int pgmPoolSyncCR3(PVM pVM);
3077void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3078void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3079int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3080PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3081void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3082void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3083uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3084void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3085#ifdef PGMPOOL_WITH_MONITORING
3086void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3087int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3088void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3089void pgmPoolMonitorModifiedClearAll(PVM pVM);
3090int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3091int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3092#endif
3093
3094#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3095void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3096void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3097int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3098#endif
3099int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3100int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3101
3102#ifndef IN_RC
3103int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3104#endif
3105int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3106
3107__END_DECLS
3108
3109
3110/**
3111 * Gets the PGMRAMRANGE structure for a guest page.
3112 *
3113 * @returns Pointer to the RAM range on success.
3114 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3115 *
3116 * @param pPGM PGM handle.
3117 * @param GCPhys The GC physical address.
3118 */
3119DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3120{
3121 /*
3122 * Optimize for the first range.
3123 */
3124 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3125 RTGCPHYS off = GCPhys - pRam->GCPhys;
3126 if (RT_UNLIKELY(off >= pRam->cb))
3127 {
3128 do
3129 {
3130 pRam = pRam->CTX_SUFF(pNext);
3131 if (RT_UNLIKELY(!pRam))
3132 break;
3133 off = GCPhys - pRam->GCPhys;
3134 } while (off >= pRam->cb);
3135 }
3136 return pRam;
3137}
3138
3139
3140/**
3141 * Gets the PGMPAGE structure for a guest page.
3142 *
3143 * @returns Pointer to the page on success.
3144 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3145 *
3146 * @param pPGM PGM handle.
3147 * @param GCPhys The GC physical address.
3148 */
3149DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3150{
3151 /*
3152 * Optimize for the first range.
3153 */
3154 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3155 RTGCPHYS off = GCPhys - pRam->GCPhys;
3156 if (RT_UNLIKELY(off >= pRam->cb))
3157 {
3158 do
3159 {
3160 pRam = pRam->CTX_SUFF(pNext);
3161 if (RT_UNLIKELY(!pRam))
3162 return NULL;
3163 off = GCPhys - pRam->GCPhys;
3164 } while (off >= pRam->cb);
3165 }
3166 return &pRam->aPages[off >> PAGE_SHIFT];
3167}
3168
3169
3170/**
3171 * Gets the PGMPAGE structure for a guest page.
3172 *
3173 * Old Phys code: Will make sure the page is present.
3174 *
3175 * @returns VBox status code.
3176 * @retval VINF_SUCCESS and a valid *ppPage on success.
3177 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3178 *
3179 * @param pPGM PGM handle.
3180 * @param GCPhys The GC physical address.
3181 * @param ppPage Where to store the page poitner on success.
3182 */
3183DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3184{
3185 /*
3186 * Optimize for the first range.
3187 */
3188 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3189 RTGCPHYS off = GCPhys - pRam->GCPhys;
3190 if (RT_UNLIKELY(off >= pRam->cb))
3191 {
3192 do
3193 {
3194 pRam = pRam->CTX_SUFF(pNext);
3195 if (RT_UNLIKELY(!pRam))
3196 {
3197 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3198 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3199 }
3200 off = GCPhys - pRam->GCPhys;
3201 } while (off >= pRam->cb);
3202 }
3203 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3204#ifndef VBOX_WITH_NEW_PHYS_CODE
3205
3206 /*
3207 * Make sure it's present.
3208 */
3209 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3210 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3211 {
3212#ifdef IN_RING3
3213 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3214#else
3215 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3216#endif
3217 if (RT_FAILURE(rc))
3218 {
3219 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3220 return rc;
3221 }
3222 Assert(rc == VINF_SUCCESS);
3223 }
3224#endif
3225 return VINF_SUCCESS;
3226}
3227
3228
3229
3230
3231/**
3232 * Gets the PGMPAGE structure for a guest page.
3233 *
3234 * Old Phys code: Will make sure the page is present.
3235 *
3236 * @returns VBox status code.
3237 * @retval VINF_SUCCESS and a valid *ppPage on success.
3238 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3239 *
3240 * @param pPGM PGM handle.
3241 * @param GCPhys The GC physical address.
3242 * @param ppPage Where to store the page poitner on success.
3243 * @param ppRamHint Where to read and store the ram list hint.
3244 * The caller initializes this to NULL before the call.
3245 */
3246DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3247{
3248 RTGCPHYS off;
3249 PPGMRAMRANGE pRam = *ppRamHint;
3250 if ( !pRam
3251 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3252 {
3253 pRam = pPGM->CTX_SUFF(pRamRanges);
3254 off = GCPhys - pRam->GCPhys;
3255 if (RT_UNLIKELY(off >= pRam->cb))
3256 {
3257 do
3258 {
3259 pRam = pRam->CTX_SUFF(pNext);
3260 if (RT_UNLIKELY(!pRam))
3261 {
3262 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3263 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3264 }
3265 off = GCPhys - pRam->GCPhys;
3266 } while (off >= pRam->cb);
3267 }
3268 *ppRamHint = pRam;
3269 }
3270 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3271#ifndef VBOX_WITH_NEW_PHYS_CODE
3272
3273 /*
3274 * Make sure it's present.
3275 */
3276 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3277 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3278 {
3279#ifdef IN_RING3
3280 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3281#else
3282 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3283#endif
3284 if (RT_FAILURE(rc))
3285 {
3286 *ppPage = NULL; /* Shut up annoying smart ass. */
3287 return rc;
3288 }
3289 Assert(rc == VINF_SUCCESS);
3290 }
3291#endif
3292 return VINF_SUCCESS;
3293}
3294
3295
3296/**
3297 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3298 *
3299 * @returns Pointer to the page on success.
3300 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3301 *
3302 * @param pPGM PGM handle.
3303 * @param GCPhys The GC physical address.
3304 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3305 */
3306DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3307{
3308 /*
3309 * Optimize for the first range.
3310 */
3311 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3312 RTGCPHYS off = GCPhys - pRam->GCPhys;
3313 if (RT_UNLIKELY(off >= pRam->cb))
3314 {
3315 do
3316 {
3317 pRam = pRam->CTX_SUFF(pNext);
3318 if (RT_UNLIKELY(!pRam))
3319 return NULL;
3320 off = GCPhys - pRam->GCPhys;
3321 } while (off >= pRam->cb);
3322 }
3323 *ppRam = pRam;
3324 return &pRam->aPages[off >> PAGE_SHIFT];
3325}
3326
3327
3328/**
3329 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3330 *
3331 * @returns Pointer to the page on success.
3332 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3333 *
3334 * @param pPGM PGM handle.
3335 * @param GCPhys The GC physical address.
3336 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3337 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3338 */
3339DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3340{
3341 /*
3342 * Optimize for the first range.
3343 */
3344 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3345 RTGCPHYS off = GCPhys - pRam->GCPhys;
3346 if (RT_UNLIKELY(off >= pRam->cb))
3347 {
3348 do
3349 {
3350 pRam = pRam->CTX_SUFF(pNext);
3351 if (RT_UNLIKELY(!pRam))
3352 {
3353 *ppRam = NULL; /* Shut up silly GCC warnings. */
3354 *ppPage = NULL; /* ditto */
3355 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3356 }
3357 off = GCPhys - pRam->GCPhys;
3358 } while (off >= pRam->cb);
3359 }
3360 *ppRam = pRam;
3361 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3362#ifndef VBOX_WITH_NEW_PHYS_CODE
3363
3364 /*
3365 * Make sure it's present.
3366 */
3367 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3368 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3369 {
3370#ifdef IN_RING3
3371 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3372#else
3373 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3374#endif
3375 if (RT_FAILURE(rc))
3376 {
3377 *ppPage = NULL; /* Shut up silly GCC warnings. */
3378 *ppPage = NULL; /* ditto */
3379 return rc;
3380 }
3381 Assert(rc == VINF_SUCCESS);
3382
3383 }
3384#endif
3385 return VINF_SUCCESS;
3386}
3387
3388
3389/**
3390 * Convert GC Phys to HC Phys.
3391 *
3392 * @returns VBox status.
3393 * @param pPGM PGM handle.
3394 * @param GCPhys The GC physical address.
3395 * @param pHCPhys Where to store the corresponding HC physical address.
3396 *
3397 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3398 * Avoid when writing new code!
3399 */
3400DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3401{
3402 PPGMPAGE pPage;
3403 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3404 if (RT_FAILURE(rc))
3405 return rc;
3406 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3407 return VINF_SUCCESS;
3408}
3409
3410#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3411
3412/**
3413 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3414 * optimizes access to pages already in the set.
3415 *
3416 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3417 * @param pPGM Pointer to the PVM instance data.
3418 * @param HCPhys The physical address of the page.
3419 * @param ppv Where to store the mapping address.
3420 */
3421DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3422{
3423 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3424 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3425 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3426 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3427
3428 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3429 unsigned iEntry = pSet->aiHashTable[iHash];
3430 if ( iEntry < pSet->cEntries
3431 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3432 {
3433 *ppv = pSet->aEntries[iEntry].pvPage;
3434 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3435 }
3436 else
3437 {
3438 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3439 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3440 }
3441
3442 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3443 return VINF_SUCCESS;
3444}
3445
3446
3447/**
3448 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3449 * access to pages already in the set.
3450 *
3451 * @returns See PGMDynMapGCPage.
3452 * @param pPGM Pointer to the PVM instance data.
3453 * @param HCPhys The physical address of the page.
3454 * @param ppv Where to store the mapping address.
3455 */
3456DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3457{
3458 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3459 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3460
3461 /*
3462 * Get the ram range.
3463 */
3464 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3465 RTGCPHYS off = GCPhys - pRam->GCPhys;
3466 if (RT_UNLIKELY(off >= pRam->cb
3467 /** @todo || page state stuff */))
3468 {
3469 /* This case is not counted into StatR0DynMapGCPageInl. */
3470 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3471 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3472 }
3473
3474 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3475 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3476
3477 /*
3478 * pgmR0DynMapHCPageInlined with out stats.
3479 */
3480 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3481 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3482 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3483
3484 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3485 unsigned iEntry = pSet->aiHashTable[iHash];
3486 if ( iEntry < pSet->cEntries
3487 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3488 {
3489 *ppv = pSet->aEntries[iEntry].pvPage;
3490 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3491 }
3492 else
3493 {
3494 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3495 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3496 }
3497
3498 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3499 return VINF_SUCCESS;
3500}
3501
3502#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3503#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3504
3505/**
3506 * Maps the page into current context (RC and maybe R0).
3507 *
3508 * @returns pointer to the mapping.
3509 * @param pVM Pointer to the PGM instance data.
3510 * @param pPage The page.
3511 */
3512DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3513{
3514 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3515 {
3516 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3517 void *pv;
3518# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3519 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3520# else
3521 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3522# endif
3523 return pv;
3524 }
3525 return pgmPoolMapPageFallback(pPGM, pPage);
3526}
3527
3528/**
3529 * Temporarily maps one host page specified by HC physical address, returning
3530 * pointer within the page.
3531 *
3532 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3533 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3534 *
3535 * @returns The address corresponding to HCPhys.
3536 * @param pPGM Pointer to the PVM instance data.
3537 * @param HCPhys HC Physical address of the page.
3538 */
3539DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3540{
3541 void *pv;
3542# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3543 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3544# else
3545 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3546# endif
3547 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3548 return pv;
3549}
3550
3551#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3552
3553#ifndef IN_RC
3554/**
3555 * Queries the Physical TLB entry for a physical guest page,
3556 * attemting to load the TLB entry if necessary.
3557 *
3558 * @returns VBox status code.
3559 * @retval VINF_SUCCESS on success
3560 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3561 *
3562 * @param pPGM The PGM instance handle.
3563 * @param GCPhys The address of the guest page.
3564 * @param ppTlbe Where to store the pointer to the TLB entry.
3565 */
3566DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3567{
3568 int rc;
3569 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3570 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3571 {
3572 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3573 rc = VINF_SUCCESS;
3574 }
3575 else
3576 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3577 *ppTlbe = pTlbe;
3578 return rc;
3579}
3580
3581
3582/**
3583 * Queries the Physical TLB entry for a physical guest page,
3584 * attemting to load the TLB entry if necessary.
3585 *
3586 * @returns VBox status code.
3587 * @retval VINF_SUCCESS on success
3588 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3589 *
3590 * @param pPGM The PGM instance handle.
3591 * @param pPage Pointer to the PGMPAGE structure corresponding to
3592 * GCPhys.
3593 * @param GCPhys The address of the guest page.
3594 * @param ppTlbe Where to store the pointer to the TLB entry.
3595 */
3596DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3597{
3598 int rc;
3599 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3600 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3601 {
3602 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3603 rc = VINF_SUCCESS;
3604 }
3605 else
3606 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3607 *ppTlbe = pTlbe;
3608 return rc;
3609}
3610#endif /* !IN_RC */
3611
3612
3613#ifndef VBOX_WITH_NEW_PHYS_CODE
3614/**
3615 * Convert GC Phys to HC Virt and HC Phys.
3616 *
3617 * @returns VBox status.
3618 * @param pPGM PGM handle.
3619 * @param GCPhys The GC physical address.
3620 * @param pHCPtr Where to store the corresponding HC virtual address.
3621 * @param pHCPhys Where to store the HC Physical address and its flags.
3622 *
3623 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3624 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3625 * Either way, we have to make sure the page is writable in MapCR3.
3626 */
3627DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3628{
3629 PPGMRAMRANGE pRam;
3630 PPGMPAGE pPage;
3631 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3632 if (RT_FAILURE(rc))
3633 {
3634 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3635 *pHCPhys = 0; /* ditto */
3636 return rc;
3637 }
3638 RTGCPHYS off = GCPhys - pRam->GCPhys;
3639
3640 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3641 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3642 {
3643 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3644#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3645 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3646 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3647#else
3648 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3649#endif
3650 return VINF_SUCCESS;
3651 }
3652 if (pRam->pvR3)
3653 {
3654 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3655 return VINF_SUCCESS;
3656 }
3657 *pHCPtr = 0;
3658 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3659}
3660#endif /* VBOX_WITH_NEW_PHYS_CODE */
3661
3662
3663/**
3664 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3665 * Takes PSE-36 into account.
3666 *
3667 * @returns guest physical address
3668 * @param pPGM Pointer to the PGM instance data.
3669 * @param Pde Guest Pde
3670 */
3671DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3672{
3673 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3674 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3675
3676 return GCPhys & pPGM->GCPhys4MBPSEMask;
3677}
3678
3679
3680/**
3681 * Gets the page directory entry for the specified address (32-bit paging).
3682 *
3683 * @returns The page directory entry in question.
3684 * @param pPGM Pointer to the PGM instance data.
3685 * @param GCPtr The address.
3686 */
3687DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3688{
3689#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3690 PCX86PD pGuestPD = 0;
3691 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3692 if (RT_FAILURE(rc))
3693 {
3694 X86PDE ZeroPde = {0};
3695 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3696 }
3697 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3698#else
3699 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3700#endif
3701}
3702
3703
3704/**
3705 * Gets the address of a specific page directory entry (32-bit paging).
3706 *
3707 * @returns Pointer the page directory entry in question.
3708 * @param pPGM Pointer to the PGM instance data.
3709 * @param GCPtr The address.
3710 */
3711DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3712{
3713#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3714 PX86PD pGuestPD = 0;
3715 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3716 AssertRCReturn(rc, 0);
3717 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3718#else
3719 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3720#endif
3721}
3722
3723
3724/**
3725 * Gets the address the guest page directory (32-bit paging).
3726 *
3727 * @returns Pointer the page directory entry in question.
3728 * @param pPGM Pointer to the PGM instance data.
3729 */
3730DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3731{
3732#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3733 PX86PD pGuestPD = 0;
3734 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3735 AssertRCReturn(rc, 0);
3736 return pGuestPD;
3737#else
3738 return pPGM->CTX_SUFF(pGst32BitPd);
3739#endif
3740}
3741
3742
3743/**
3744 * Gets the guest page directory pointer table.
3745 *
3746 * @returns Pointer to the page directory in question.
3747 * @returns NULL if the page directory is not present or on an invalid page.
3748 * @param pPGM Pointer to the PGM instance data.
3749 */
3750DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3751{
3752#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3753 PX86PDPT pGuestPDPT = 0;
3754 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3755 AssertRCReturn(rc, 0);
3756 return pGuestPDPT;
3757#else
3758 return pPGM->CTX_SUFF(pGstPaePdpt);
3759#endif
3760}
3761
3762
3763/**
3764 * Gets the guest page directory pointer table entry for the specified address.
3765 *
3766 * @returns Pointer to the page directory in question.
3767 * @returns NULL if the page directory is not present or on an invalid page.
3768 * @param pPGM Pointer to the PGM instance data.
3769 * @param GCPtr The address.
3770 */
3771DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3772{
3773 AssertGCPtr32(GCPtr);
3774
3775#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3776 PX86PDPT pGuestPDPT = 0;
3777 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3778 AssertRCReturn(rc, 0);
3779 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3780#else
3781 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3782#endif
3783}
3784
3785
3786/**
3787 * Gets the page directory for the specified address.
3788 *
3789 * @returns Pointer to the page directory in question.
3790 * @returns NULL if the page directory is not present or on an invalid page.
3791 * @param pPGM Pointer to the PGM instance data.
3792 * @param GCPtr The address.
3793 */
3794DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3795{
3796 AssertGCPtr32(GCPtr);
3797
3798#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3799 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3800 AssertReturn(pGuestPDPT, 0);
3801#else
3802 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3803#endif
3804 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3805 if (pGuestPDPT->a[iPdPt].n.u1Present)
3806 {
3807#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3808 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3809 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3810#endif
3811
3812 /* cache is out-of-sync. */
3813 PX86PDPAE pPD;
3814 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3815 if (RT_SUCCESS(rc))
3816 return pPD;
3817 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3818 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3819 }
3820 return NULL;
3821}
3822
3823
3824/**
3825 * Gets the page directory entry for the specified address.
3826 *
3827 * @returns Pointer to the page directory entry in question.
3828 * @returns NULL if the page directory is not present or on an invalid page.
3829 * @param pPGM Pointer to the PGM instance data.
3830 * @param GCPtr The address.
3831 */
3832DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3833{
3834 AssertGCPtr32(GCPtr);
3835
3836#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3837 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3838 AssertReturn(pGuestPDPT, 0);
3839#else
3840 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3841#endif
3842 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3843 if (pGuestPDPT->a[iPdPt].n.u1Present)
3844 {
3845 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3846#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3847 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3848 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3849#endif
3850
3851 /* The cache is out-of-sync. */
3852 PX86PDPAE pPD;
3853 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3854 if (RT_SUCCESS(rc))
3855 return &pPD->a[iPD];
3856 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3857 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3858 }
3859 return NULL;
3860}
3861
3862
3863/**
3864 * Gets the page directory entry for the specified address.
3865 *
3866 * @returns The page directory entry in question.
3867 * @returns A non-present entry if the page directory is not present or on an invalid page.
3868 * @param pPGM Pointer to the PGM instance data.
3869 * @param GCPtr The address.
3870 */
3871DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3872{
3873 AssertGCPtr32(GCPtr);
3874
3875#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3876 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3877 if (RT_LIKELY(pGuestPDPT))
3878#else
3879 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3880#endif
3881 {
3882 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3883 if (pGuestPDPT->a[iPdPt].n.u1Present)
3884 {
3885 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3886#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3887 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3888 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3889#endif
3890
3891 /* cache is out-of-sync. */
3892 PX86PDPAE pPD;
3893 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3894 if (RT_SUCCESS(rc))
3895 return pPD->a[iPD];
3896 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3897 }
3898 }
3899 X86PDEPAE ZeroPde = {0};
3900 return ZeroPde;
3901}
3902
3903
3904/**
3905 * Gets the page directory pointer table entry for the specified address
3906 * and returns the index into the page directory
3907 *
3908 * @returns Pointer to the page directory in question.
3909 * @returns NULL if the page directory is not present or on an invalid page.
3910 * @param pPGM Pointer to the PGM instance data.
3911 * @param GCPtr The address.
3912 * @param piPD Receives the index into the returned page directory
3913 * @param pPdpe Receives the page directory pointer entry. Optional.
3914 */
3915DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3916{
3917 AssertGCPtr32(GCPtr);
3918
3919#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3920 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3921 AssertReturn(pGuestPDPT, 0);
3922#else
3923 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3924#endif
3925 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3926 if (pPdpe)
3927 *pPdpe = pGuestPDPT->a[iPdPt];
3928 if (pGuestPDPT->a[iPdPt].n.u1Present)
3929 {
3930 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3931#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3932 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3933 {
3934 *piPD = iPD;
3935 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3936 }
3937#endif
3938
3939 /* cache is out-of-sync. */
3940 PX86PDPAE pPD;
3941 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3942 if (RT_SUCCESS(rc))
3943 {
3944 *piPD = iPD;
3945 return pPD;
3946 }
3947 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3948 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3949 }
3950 return NULL;
3951}
3952
3953#ifndef IN_RC
3954
3955/**
3956 * Gets the page map level-4 pointer for the guest.
3957 *
3958 * @returns Pointer to the PML4 page.
3959 * @param pPGM Pointer to the PGM instance data.
3960 */
3961DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3962{
3963#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3964 PX86PML4 pGuestPml4;
3965 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3966 AssertRCReturn(rc, NULL);
3967 return pGuestPml4;
3968#else
3969 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3970 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3971#endif
3972}
3973
3974
3975/**
3976 * Gets the pointer to a page map level-4 entry.
3977 *
3978 * @returns Pointer to the PML4 entry.
3979 * @param pPGM Pointer to the PGM instance data.
3980 * @param iPml4 The index.
3981 */
3982DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3983{
3984#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3985 PX86PML4 pGuestPml4;
3986 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3987 AssertRCReturn(rc, NULL);
3988 return &pGuestPml4->a[iPml4];
3989#else
3990 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3991 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3992#endif
3993}
3994
3995
3996/**
3997 * Gets a page map level-4 entry.
3998 *
3999 * @returns The PML4 entry.
4000 * @param pPGM Pointer to the PGM instance data.
4001 * @param iPml4 The index.
4002 */
4003DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
4004{
4005#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4006 PX86PML4 pGuestPml4;
4007 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4008 if (RT_FAILURE(rc))
4009 {
4010 X86PML4E ZeroPml4e = {0};
4011 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4012 }
4013 return pGuestPml4->a[iPml4];
4014#else
4015 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4016 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4017#endif
4018}
4019
4020
4021/**
4022 * Gets the page directory pointer entry for the specified address.
4023 *
4024 * @returns Pointer to the page directory pointer entry in question.
4025 * @returns NULL if the page directory is not present or on an invalid page.
4026 * @param pPGM Pointer to the PGM instance data.
4027 * @param GCPtr The address.
4028 * @param ppPml4e Page Map Level-4 Entry (out)
4029 */
4030DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4031{
4032 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4033 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4034 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4035 if (pPml4e->n.u1Present)
4036 {
4037 PX86PDPT pPdpt;
4038 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4039 AssertRCReturn(rc, NULL);
4040
4041 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4042 return &pPdpt->a[iPdPt];
4043 }
4044 return NULL;
4045}
4046
4047
4048/**
4049 * Gets the page directory entry for the specified address.
4050 *
4051 * @returns The page directory entry in question.
4052 * @returns A non-present entry if the page directory is not present or on an invalid page.
4053 * @param pPGM Pointer to the PGM instance data.
4054 * @param GCPtr The address.
4055 * @param ppPml4e Page Map Level-4 Entry (out)
4056 * @param pPdpe Page directory pointer table entry (out)
4057 */
4058DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4059{
4060 X86PDEPAE ZeroPde = {0};
4061 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4062 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4063 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4064 if (pPml4e->n.u1Present)
4065 {
4066 PCX86PDPT pPdptTemp;
4067 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4068 AssertRCReturn(rc, ZeroPde);
4069
4070 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4071 *pPdpe = pPdptTemp->a[iPdPt];
4072 if (pPdptTemp->a[iPdPt].n.u1Present)
4073 {
4074 PCX86PDPAE pPD;
4075 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4076 AssertRCReturn(rc, ZeroPde);
4077
4078 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4079 return pPD->a[iPD];
4080 }
4081 }
4082
4083 return ZeroPde;
4084}
4085
4086
4087/**
4088 * Gets the page directory entry for the specified address.
4089 *
4090 * @returns The page directory entry in question.
4091 * @returns A non-present entry if the page directory is not present or on an invalid page.
4092 * @param pPGM Pointer to the PGM instance data.
4093 * @param GCPtr The address.
4094 */
4095DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4096{
4097 X86PDEPAE ZeroPde = {0};
4098 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4099 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4100 if (pGuestPml4->a[iPml4].n.u1Present)
4101 {
4102 PCX86PDPT pPdptTemp;
4103 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4104 AssertRCReturn(rc, ZeroPde);
4105
4106 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4107 if (pPdptTemp->a[iPdPt].n.u1Present)
4108 {
4109 PCX86PDPAE pPD;
4110 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4111 AssertRCReturn(rc, ZeroPde);
4112
4113 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4114 return pPD->a[iPD];
4115 }
4116 }
4117 return ZeroPde;
4118}
4119
4120
4121/**
4122 * Gets the page directory entry for the specified address.
4123 *
4124 * @returns Pointer to the page directory entry in question.
4125 * @returns NULL if the page directory is not present or on an invalid page.
4126 * @param pPGM Pointer to the PGM instance data.
4127 * @param GCPtr The address.
4128 */
4129DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4130{
4131 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4132 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4133 if (pGuestPml4->a[iPml4].n.u1Present)
4134 {
4135 PCX86PDPT pPdptTemp;
4136 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4137 AssertRCReturn(rc, NULL);
4138
4139 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4140 if (pPdptTemp->a[iPdPt].n.u1Present)
4141 {
4142 PX86PDPAE pPD;
4143 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4144 AssertRCReturn(rc, NULL);
4145
4146 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4147 return &pPD->a[iPD];
4148 }
4149 }
4150 return NULL;
4151}
4152
4153
4154/**
4155 * Gets the GUEST page directory pointer for the specified address.
4156 *
4157 * @returns The page directory in question.
4158 * @returns NULL if the page directory is not present or on an invalid page.
4159 * @param pPGM Pointer to the PGM instance data.
4160 * @param GCPtr The address.
4161 * @param ppPml4e Page Map Level-4 Entry (out)
4162 * @param pPdpe Page directory pointer table entry (out)
4163 * @param piPD Receives the index into the returned page directory
4164 */
4165DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4166{
4167 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4168 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4169 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4170 if (pPml4e->n.u1Present)
4171 {
4172 PCX86PDPT pPdptTemp;
4173 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4174 AssertRCReturn(rc, NULL);
4175
4176 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4177 *pPdpe = pPdptTemp->a[iPdPt];
4178 if (pPdptTemp->a[iPdPt].n.u1Present)
4179 {
4180 PX86PDPAE pPD;
4181 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4182 AssertRCReturn(rc, NULL);
4183
4184 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4185 return pPD;
4186 }
4187 }
4188 return 0;
4189}
4190
4191#endif /* !IN_RC */
4192
4193/**
4194 * Gets the shadow page directory, 32-bit.
4195 *
4196 * @returns Pointer to the shadow 32-bit PD.
4197 * @param pPGM Pointer to the PGM instance data.
4198 */
4199DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4200{
4201#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4202 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4203#else
4204# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4205 PX86PD pShwPd;
4206 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4207 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4208 AssertRCReturn(rc, NULL);
4209 return pShwPd;
4210# else
4211 return pPGM->CTX_SUFF(pShw32BitPd);
4212# endif
4213#endif
4214}
4215
4216
4217/**
4218 * Gets the shadow page directory entry for the specified address, 32-bit.
4219 *
4220 * @returns Shadow 32-bit PDE.
4221 * @param pPGM Pointer to the PGM instance data.
4222 * @param GCPtr The address.
4223 */
4224DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4225{
4226 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4227
4228 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4229 if (!pShwPde)
4230 {
4231 X86PDE ZeroPde = {0};
4232 return ZeroPde;
4233 }
4234 return pShwPde->a[iPd];
4235}
4236
4237
4238/**
4239 * Gets the pointer to the shadow page directory entry for the specified
4240 * address, 32-bit.
4241 *
4242 * @returns Pointer to the shadow 32-bit PDE.
4243 * @param pPGM Pointer to the PGM instance data.
4244 * @param GCPtr The address.
4245 */
4246DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4247{
4248 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4249
4250 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4251 AssertReturn(pPde, NULL);
4252 return &pPde->a[iPd];
4253}
4254
4255
4256/**
4257 * Gets the shadow page pointer table, PAE.
4258 *
4259 * @returns Pointer to the shadow PAE PDPT.
4260 * @param pPGM Pointer to the PGM instance data.
4261 */
4262DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4263{
4264#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4265 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4266#else
4267# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4268 PX86PDPT pShwPdpt;
4269 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4270 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4271 AssertRCReturn(rc, 0);
4272 return pShwPdpt;
4273# else
4274 return pPGM->CTX_SUFF(pShwPaePdpt);
4275# endif
4276#endif
4277}
4278
4279
4280/**
4281 * Gets the shadow page directory for the specified address, PAE.
4282 *
4283 * @returns Pointer to the shadow PD.
4284 * @param pPGM Pointer to the PGM instance data.
4285 * @param GCPtr The address.
4286 */
4287DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4288{
4289#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4290 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4291 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4292
4293 if (!pPdpt->a[iPdpt].n.u1Present)
4294 return NULL;
4295
4296 /* Fetch the pgm pool shadow descriptor. */
4297 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4298 AssertReturn(pShwPde, NULL);
4299
4300 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4301#else
4302 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4303# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4304 PX86PDPAE pPD;
4305 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4306 AssertRCReturn(rc, 0);
4307 return pPD;
4308# else
4309 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4310 Assert(pPD);
4311 return pPD;
4312# endif
4313#endif
4314}
4315
4316
4317/**
4318 * Gets the shadow page directory for the specified address, PAE.
4319 *
4320 * @returns Pointer to the shadow PD.
4321 * @param pPGM Pointer to the PGM instance data.
4322 * @param GCPtr The address.
4323 */
4324DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4325{
4326#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4327 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4328
4329 if (!pPdpt->a[iPdpt].n.u1Present)
4330 return NULL;
4331
4332 /* Fetch the pgm pool shadow descriptor. */
4333 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4334 AssertReturn(pShwPde, NULL);
4335
4336 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4337#else
4338 AssertFailed();
4339 return NULL;
4340#endif
4341}
4342
4343
4344/**
4345 * Gets the shadow page directory entry, PAE.
4346 *
4347 * @returns PDE.
4348 * @param pPGM Pointer to the PGM instance data.
4349 * @param GCPtr The address.
4350 */
4351DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4352{
4353 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4354
4355 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4356 if (!pShwPde)
4357 {
4358 X86PDEPAE ZeroPde = {0};
4359 return ZeroPde;
4360 }
4361 return pShwPde->a[iPd];
4362}
4363
4364
4365/**
4366 * Gets the pointer to the shadow page directory entry for an address, PAE.
4367 *
4368 * @returns Pointer to the PDE.
4369 * @param pPGM Pointer to the PGM instance data.
4370 * @param GCPtr The address.
4371 */
4372DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4373{
4374 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4375
4376 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4377 AssertReturn(pPde, NULL);
4378 return &pPde->a[iPd];
4379}
4380
4381#ifndef IN_RC
4382
4383/**
4384 * Gets the shadow page map level-4 pointer.
4385 *
4386 * @returns Pointer to the shadow PML4.
4387 * @param pPGM Pointer to the PGM instance data.
4388 */
4389DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4390{
4391#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4392 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4393#else
4394# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4395 PX86PML4 pShwPml4;
4396 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4397 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4398 AssertRCReturn(rc, 0);
4399 return pShwPml4;
4400# else
4401 Assert(pPGM->CTX_SUFF(pShwRoot));
4402 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4403# endif
4404#endif
4405}
4406
4407
4408/**
4409 * Gets the shadow page map level-4 entry for the specified address.
4410 *
4411 * @returns The entry.
4412 * @param pPGM Pointer to the PGM instance data.
4413 * @param GCPtr The address.
4414 */
4415DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4416{
4417 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4418 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4419
4420 if (!pShwPml4)
4421 {
4422 X86PML4E ZeroPml4e = {0};
4423 return ZeroPml4e;
4424 }
4425 return pShwPml4->a[iPml4];
4426}
4427
4428
4429/**
4430 * Gets the pointer to the specified shadow page map level-4 entry.
4431 *
4432 * @returns The entry.
4433 * @param pPGM Pointer to the PGM instance data.
4434 * @param iPml4 The PML4 index.
4435 */
4436DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4437{
4438 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4439 if (!pShwPml4)
4440 return NULL;
4441 return &pShwPml4->a[iPml4];
4442}
4443
4444
4445/**
4446 * Gets the GUEST page directory pointer for the specified address.
4447 *
4448 * @returns The page directory in question.
4449 * @returns NULL if the page directory is not present or on an invalid page.
4450 * @param pPGM Pointer to the PGM instance data.
4451 * @param GCPtr The address.
4452 * @param piPD Receives the index into the returned page directory
4453 */
4454DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4455{
4456 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4457 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4458 if (pGuestPml4->a[iPml4].n.u1Present)
4459 {
4460 PCX86PDPT pPdptTemp;
4461 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4462 AssertRCReturn(rc, NULL);
4463
4464 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4465 if (pPdptTemp->a[iPdPt].n.u1Present)
4466 {
4467 PX86PDPAE pPD;
4468 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4469 AssertRCReturn(rc, NULL);
4470
4471 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4472 return pPD;
4473 }
4474 }
4475 return NULL;
4476}
4477
4478#endif /* !IN_RC */
4479
4480/**
4481 * Gets the page state for a physical handler.
4482 *
4483 * @returns The physical handler page state.
4484 * @param pCur The physical handler in question.
4485 */
4486DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4487{
4488 switch (pCur->enmType)
4489 {
4490 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4491 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4492
4493 case PGMPHYSHANDLERTYPE_MMIO:
4494 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4495 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4496
4497 default:
4498 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4499 }
4500}
4501
4502
4503/**
4504 * Gets the page state for a virtual handler.
4505 *
4506 * @returns The virtual handler page state.
4507 * @param pCur The virtual handler in question.
4508 * @remarks This should never be used on a hypervisor access handler.
4509 */
4510DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4511{
4512 switch (pCur->enmType)
4513 {
4514 case PGMVIRTHANDLERTYPE_WRITE:
4515 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4516 case PGMVIRTHANDLERTYPE_ALL:
4517 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4518 default:
4519 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4520 }
4521}
4522
4523
4524/**
4525 * Clears one physical page of a virtual handler
4526 *
4527 * @param pPGM Pointer to the PGM instance.
4528 * @param pCur Virtual handler structure
4529 * @param iPage Physical page index
4530 *
4531 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4532 * need to care about other handlers in the same page.
4533 */
4534DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4535{
4536 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4537
4538 /*
4539 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4540 */
4541#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4542 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4543 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4544 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4545#endif
4546 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4547 {
4548 /* We're the head of the alias chain. */
4549 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4550#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4551 AssertReleaseMsg(pRemove != NULL,
4552 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4553 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4554 AssertReleaseMsg(pRemove == pPhys2Virt,
4555 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4556 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4557 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4558 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4559#endif
4560 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4561 {
4562 /* Insert the next list in the alias chain into the tree. */
4563 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4564#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4565 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4566 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4567 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4568#endif
4569 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4570 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4571 AssertRelease(fRc);
4572 }
4573 }
4574 else
4575 {
4576 /* Locate the previous node in the alias chain. */
4577 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4578#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4579 AssertReleaseMsg(pPrev != pPhys2Virt,
4580 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4581 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4582#endif
4583 for (;;)
4584 {
4585 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4586 if (pNext == pPhys2Virt)
4587 {
4588 /* unlink. */
4589 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4590 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4591 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4592 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4593 else
4594 {
4595 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4596 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4597 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4598 }
4599 break;
4600 }
4601
4602 /* next */
4603 if (pNext == pPrev)
4604 {
4605#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4606 AssertReleaseMsg(pNext != pPrev,
4607 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4608 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4609#endif
4610 break;
4611 }
4612 pPrev = pNext;
4613 }
4614 }
4615 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4616 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4617 pPhys2Virt->offNextAlias = 0;
4618 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4619
4620 /*
4621 * Clear the ram flags for this page.
4622 */
4623 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4624 AssertReturnVoid(pPage);
4625 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4626}
4627
4628
4629/**
4630 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4631 *
4632 * @returns Pointer to the shadow page structure.
4633 * @param pPool The pool.
4634 * @param HCPhys The HC physical address of the shadow page.
4635 */
4636DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4637{
4638 /*
4639 * Look up the page.
4640 */
4641 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4642 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4643 return pPage;
4644}
4645
4646
4647/**
4648 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4649 *
4650 * @returns Pointer to the shadow page structure.
4651 * @param pPool The pool.
4652 * @param idx The pool page index.
4653 */
4654DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4655{
4656 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4657 return &pPool->aPages[idx];
4658}
4659
4660
4661#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4662/**
4663 * Clear references to guest physical memory.
4664 *
4665 * @param pPool The pool.
4666 * @param pPoolPage The pool page.
4667 * @param pPhysPage The physical guest page tracking structure.
4668 */
4669DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4670{
4671 /*
4672 * Just deal with the simple case here.
4673 */
4674# ifdef LOG_ENABLED
4675 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4676# endif
4677 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4678 if (cRefs == 1)
4679 {
4680 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4681 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4682 }
4683 else
4684 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4685 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4686}
4687#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4688
4689
4690#ifdef PGMPOOL_WITH_CACHE
4691/**
4692 * Moves the page to the head of the age list.
4693 *
4694 * This is done when the cached page is used in one way or another.
4695 *
4696 * @param pPool The pool.
4697 * @param pPage The cached page.
4698 * @todo inline in PGMInternal.h!
4699 */
4700DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4701{
4702 /*
4703 * Move to the head of the age list.
4704 */
4705 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4706 {
4707 /* unlink */
4708 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4709 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4710 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4711 else
4712 pPool->iAgeTail = pPage->iAgePrev;
4713
4714 /* insert at head */
4715 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4716 pPage->iAgeNext = pPool->iAgeHead;
4717 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4718 pPool->iAgeHead = pPage->idx;
4719 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4720 }
4721}
4722#endif /* PGMPOOL_WITH_CACHE */
4723
4724#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4725
4726/**
4727 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4728 *
4729 * @param pVM VM Handle.
4730 * @param pPage PGM pool page
4731 */
4732DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4733{
4734 Assert(!pPage->fLocked);
4735 pPage->fLocked = true;
4736}
4737
4738
4739/**
4740 * Unlocks a page to allow flushing again
4741 *
4742 * @param pVM VM Handle.
4743 * @param pPage PGM pool page
4744 */
4745DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4746{
4747 Assert(pPage->fLocked);
4748 pPage->fLocked = false;
4749}
4750
4751
4752/**
4753 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4754 *
4755 * @returns VBox status code.
4756 * @param pPage PGM pool page
4757 */
4758DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4759{
4760 if (pPage->fLocked)
4761 {
4762 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4763 if (pPage->cModifications)
4764 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4765 return true;
4766 }
4767 return false;
4768}
4769
4770#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4771
4772/**
4773 * Tells if mappings are to be put into the shadow page table or not
4774 *
4775 * @returns boolean result
4776 * @param pVM VM handle.
4777 */
4778DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4779{
4780#ifdef IN_RING0
4781 /* There are no mappings in VT-x and AMD-V mode. */
4782 Assert(pPGM->fDisableMappings);
4783 return false;
4784#else
4785 return !pPGM->fDisableMappings;
4786#endif
4787}
4788
4789/** @} */
4790
4791#endif
4792
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