VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17483

Last change on this file since 17483 was 17483, checked in by vboxsync, 16 years ago

Cleaned up nested paging init and removed obsolete structure members.
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File size: 196.2 KB
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1/* $Id: PGMInternal.h 17483 2009-03-06 15:59:52Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** @} */
188
189/** @name Defines used to indicate the shadow and guest paging in the templates.
190 * @{ */
191#define PGM_TYPE_REAL 1
192#define PGM_TYPE_PROT 2
193#define PGM_TYPE_32BIT 3
194#define PGM_TYPE_PAE 4
195#define PGM_TYPE_AMD64 5
196#define PGM_TYPE_NESTED 6
197#define PGM_TYPE_EPT 7
198#define PGM_TYPE_MAX PGM_TYPE_EPT
199/** @} */
200
201/** Macro for checking if the guest is using paging.
202 * @param uGstType PGM_TYPE_*
203 * @param uShwType PGM_TYPE_*
204 * @remark ASSUMES certain order of the PGM_TYPE_* values.
205 */
206#define PGM_WITH_PAGING(uGstType, uShwType) \
207 ( (uGstType) >= PGM_TYPE_32BIT \
208 && (uShwType) != PGM_TYPE_NESTED \
209 && (uShwType) != PGM_TYPE_EPT)
210
211/** Macro for checking if the guest supports the NX bit.
212 * @param uGstType PGM_TYPE_*
213 * @param uShwType PGM_TYPE_*
214 * @remark ASSUMES certain order of the PGM_TYPE_* values.
215 */
216#define PGM_WITH_NX(uGstType, uShwType) \
217 ( (uGstType) >= PGM_TYPE_PAE \
218 && (uShwType) != PGM_TYPE_NESTED \
219 && (uShwType) != PGM_TYPE_EPT)
220
221
222/** @def PGM_HCPHYS_2_PTR
223 * Maps a HC physical page pool address to a virtual address.
224 *
225 * @returns VBox status code.
226 * @param pVM The VM handle.
227 * @param HCPhys The HC physical address to map to a virtual one.
228 * @param ppv Where to store the virtual address. No need to cast this.
229 *
230 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
231 * small page window employeed by that function. Be careful.
232 * @remark There is no need to assert on the result.
233 */
234#ifdef IN_RC
235# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
237#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
240#else
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
243#endif
244
245/** @def PGM_HCPHYS_2_PTR_BY_PGM
246 * Maps a HC physical page pool address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pPGM The PGM instance data.
250 * @param HCPhys The HC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
258# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
259 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
260#else
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
263#endif
264
265/** @def PGM_GCPHYS_2_PTR
266 * Maps a GC physical page address to a virtual address.
267 *
268 * @returns VBox status code.
269 * @param pVM The VM handle.
270 * @param GCPhys The GC physical address to map to a virtual one.
271 * @param ppv Where to store the virtual address. No need to cast this.
272 *
273 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
274 * small page window employeed by that function. Be careful.
275 * @remark There is no need to assert on the result.
276 */
277#ifdef IN_RC
278# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
280#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
283#else
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
286#endif
287
288/** @def PGM_GCPHYS_2_PTR_BY_PGM
289 * Maps a GC physical page address to a virtual address.
290 *
291 * @returns VBox status code.
292 * @param pPGM Pointer to the PGM instance data.
293 * @param GCPhys The GC physical address to map to a virtual one.
294 * @param ppv Where to store the virtual address. No need to cast this.
295 *
296 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
297 * small page window employeed by that function. Be careful.
298 * @remark There is no need to assert on the result.
299 */
300#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
301# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
302 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
303#else
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
306#endif
307
308/** @def PGM_GCPHYS_2_PTR_EX
309 * Maps a unaligned GC physical page address to a virtual address.
310 *
311 * @returns VBox status code.
312 * @param pVM The VM handle.
313 * @param GCPhys The GC physical address to map to a virtual one.
314 * @param ppv Where to store the virtual address. No need to cast this.
315 *
316 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
317 * small page window employeed by that function. Be careful.
318 * @remark There is no need to assert on the result.
319 */
320#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
321# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
322 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
323#else
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
326#endif
327
328/** @def PGM_INVL_PG
329 * Invalidates a page when in GC does nothing in HC.
330 *
331 * @param GCVirt The virtual address of the page to invalidate.
332 */
333#ifdef IN_RC
334# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
335#elif defined(IN_RING0)
336# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
337#else
338# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
339#endif
340
341/** @def PGM_INVL_BIG_PG
342 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
343 *
344 * @param GCVirt The virtual address within the page directory to invalidate.
345 */
346#ifdef IN_RC
347# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
348#elif defined(IN_RING0)
349# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
350#else
351# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
352#endif
353
354/** @def PGM_INVL_GUEST_TLBS()
355 * Invalidates all guest TLBs.
356 */
357#ifdef IN_RC
358# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
359#elif defined(IN_RING0)
360# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
361#else
362# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
363#endif
364
365
366/**
367 * Structure for tracking GC Mappings.
368 *
369 * This structure is used by linked list in both GC and HC.
370 */
371typedef struct PGMMAPPING
372{
373 /** Pointer to next entry. */
374 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
375 /** Pointer to next entry. */
376 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
377 /** Pointer to next entry. */
378 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
379 /** Indicate whether this entry is finalized. */
380 bool fFinalized;
381 /** Start Virtual address. */
382 RTGCPTR GCPtr;
383 /** Last Virtual address (inclusive). */
384 RTGCPTR GCPtrLast;
385 /** Range size (bytes). */
386 RTGCPTR cb;
387 /** Pointer to relocation callback function. */
388 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
389 /** User argument to the callback. */
390 R3PTRTYPE(void *) pvUser;
391 /** Mapping description / name. For easing debugging. */
392 R3PTRTYPE(const char *) pszDesc;
393 /** Number of page tables. */
394 uint32_t cPTs;
395#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
396 uint32_t uPadding1; /**< Alignment padding. */
397#endif
398 /** Array of page table mapping data. Each entry
399 * describes one page table. The array can be longer
400 * than the declared length.
401 */
402 struct
403 {
404 /** The HC physical address of the page table. */
405 RTHCPHYS HCPhysPT;
406 /** The HC physical address of the first PAE page table. */
407 RTHCPHYS HCPhysPaePT0;
408 /** The HC physical address of the second PAE page table. */
409 RTHCPHYS HCPhysPaePT1;
410 /** The HC virtual address of the 32-bit page table. */
411 R3PTRTYPE(PX86PT) pPTR3;
412 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
413 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
414 /** The GC virtual address of the 32-bit page table. */
415 RCPTRTYPE(PX86PT) pPTRC;
416 /** The GC virtual address of the two PAE page table. */
417 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
418 /** The GC virtual address of the 32-bit page table. */
419 R0PTRTYPE(PX86PT) pPTR0;
420 /** The GC virtual address of the two PAE page table. */
421 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
422 } aPTs[1];
423} PGMMAPPING;
424/** Pointer to structure for tracking GC Mappings. */
425typedef struct PGMMAPPING *PPGMMAPPING;
426
427
428/**
429 * Physical page access handler structure.
430 *
431 * This is used to keep track of physical address ranges
432 * which are being monitored in some kind of way.
433 */
434typedef struct PGMPHYSHANDLER
435{
436 AVLROGCPHYSNODECORE Core;
437 /** Access type. */
438 PGMPHYSHANDLERTYPE enmType;
439 /** Number of pages to update. */
440 uint32_t cPages;
441 /** Pointer to R3 callback function. */
442 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
443 /** User argument for R3 handlers. */
444 R3PTRTYPE(void *) pvUserR3;
445 /** Pointer to R0 callback function. */
446 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
447 /** User argument for R0 handlers. */
448 R0PTRTYPE(void *) pvUserR0;
449 /** Pointer to GC callback function. */
450 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
451 /** User argument for RC handlers. */
452 RCPTRTYPE(void *) pvUserRC;
453 /** Description / Name. For easing debugging. */
454 R3PTRTYPE(const char *) pszDesc;
455#ifdef VBOX_WITH_STATISTICS
456 /** Profiling of this handler. */
457 STAMPROFILE Stat;
458#endif
459} PGMPHYSHANDLER;
460/** Pointer to a physical page access handler structure. */
461typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
462
463
464/**
465 * Cache node for the physical addresses covered by a virtual handler.
466 */
467typedef struct PGMPHYS2VIRTHANDLER
468{
469 /** Core node for the tree based on physical ranges. */
470 AVLROGCPHYSNODECORE Core;
471 /** Offset from this struct to the PGMVIRTHANDLER structure. */
472 int32_t offVirtHandler;
473 /** Offset of the next alias relative to this one.
474 * Bit 0 is used for indicating whether we're in the tree.
475 * Bit 1 is used for indicating that we're the head node.
476 */
477 int32_t offNextAlias;
478} PGMPHYS2VIRTHANDLER;
479/** Pointer to a phys to virtual handler structure. */
480typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
481
482/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
483 * node is in the tree. */
484#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the head of an alias chain.
487 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
488#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
489/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
490#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
491
492
493/**
494 * Virtual page access handler structure.
495 *
496 * This is used to keep track of virtual address ranges
497 * which are being monitored in some kind of way.
498 */
499typedef struct PGMVIRTHANDLER
500{
501 /** Core node for the tree based on virtual ranges. */
502 AVLROGCPTRNODECORE Core;
503 /** Size of the range (in bytes). */
504 RTGCPTR cb;
505 /** Number of cache pages. */
506 uint32_t cPages;
507 /** Access type. */
508 PGMVIRTHANDLERTYPE enmType;
509 /** Pointer to the RC callback function. */
510 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
511#if HC_ARCH_BITS == 64
512 RTRCPTR padding;
513#endif
514 /** Pointer to the R3 callback function for invalidation. */
515 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
516 /** Pointer to the R3 callback function. */
517 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
518 /** Description / Name. For easing debugging. */
519 R3PTRTYPE(const char *) pszDesc;
520#ifdef VBOX_WITH_STATISTICS
521 /** Profiling of this handler. */
522 STAMPROFILE Stat;
523#endif
524 /** Array of cached physical addresses for the monitored ranged. */
525 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
526} PGMVIRTHANDLER;
527/** Pointer to a virtual page access handler structure. */
528typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
529
530
531/**
532 * Page type.
533 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
534 * @todo convert to \#defines.
535 */
536typedef enum PGMPAGETYPE
537{
538 /** The usual invalid zero entry. */
539 PGMPAGETYPE_INVALID = 0,
540 /** RAM page. (RWX) */
541 PGMPAGETYPE_RAM,
542 /** MMIO2 page. (RWX) */
543 PGMPAGETYPE_MMIO2,
544 /** MMIO2 page aliased over an MMIO page. (RWX)
545 * See PGMHandlerPhysicalPageAlias(). */
546 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
547 /** Shadowed ROM. (RWX) */
548 PGMPAGETYPE_ROM_SHADOW,
549 /** ROM page. (R-X) */
550 PGMPAGETYPE_ROM,
551 /** MMIO page. (---) */
552 PGMPAGETYPE_MMIO,
553 /** End of valid entries. */
554 PGMPAGETYPE_END
555} PGMPAGETYPE;
556AssertCompile(PGMPAGETYPE_END <= 7);
557
558/** @name Page type predicates.
559 * @{ */
560#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
561#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
562#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
563#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
565/** @} */
566
567
568/**
569 * A Physical Guest Page tracking structure.
570 *
571 * The format of this structure is complicated because we have to fit a lot
572 * of information into as few bits as possible. The format is also subject
573 * to change (there is one comming up soon). Which means that for we'll be
574 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
575 * accessess to the structure.
576 */
577typedef struct PGMPAGE
578{
579 /** The physical address and a whole lot of other stuff. All bits are used! */
580#ifdef VBOX_WITH_NEW_PHYS_CODE
581 RTHCPHYS HCPhysX;
582#else
583 RTHCPHYS HCPhys;
584#define HCPhysX HCPhys /**< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. */
585#endif
586 /** The page state. */
587 uint32_t u2StateX : 2;
588 /** Flag indicating that a write monitored page was written to when set. */
589 uint32_t fWrittenToX : 1;
590 /** For later. */
591 uint32_t fSomethingElse : 1;
592 /** The Page ID.
593 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
594 * The HCPhysX will then be 100% static. */
595 uint32_t idPageX : 28;
596 /** The page type (PGMPAGETYPE). */
597 uint32_t u3Type : 3;
598 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
599 uint32_t u2HandlerPhysStateX : 2;
600 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
601 uint32_t u2HandlerVirtStateX : 2;
602 uint32_t u29B : 25;
603} PGMPAGE;
604AssertCompileSize(PGMPAGE, 16);
605/** Pointer to a physical guest page. */
606typedef PGMPAGE *PPGMPAGE;
607/** Pointer to a const physical guest page. */
608typedef const PGMPAGE *PCPGMPAGE;
609/** Pointer to a physical guest page pointer. */
610typedef PPGMPAGE *PPPGMPAGE;
611
612
613/**
614 * Clears the page structure.
615 * @param pPage Pointer to the physical guest page tracking structure.
616 */
617#define PGM_PAGE_CLEAR(pPage) \
618 do { \
619 (pPage)->HCPhysX = 0; \
620 (pPage)->u2StateX = 0; \
621 (pPage)->fWrittenToX = 0; \
622 (pPage)->fSomethingElse = 0; \
623 (pPage)->idPageX = 0; \
624 (pPage)->u3Type = 0; \
625 (pPage)->u29B = 0; \
626 } while (0)
627
628/**
629 * Initializes the page structure.
630 * @param pPage Pointer to the physical guest page tracking structure.
631 */
632#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
633 do { \
634 (pPage)->HCPhysX = (_HCPhys); \
635 (pPage)->u2StateX = (_uState); \
636 (pPage)->fWrittenToX = 0; \
637 (pPage)->fSomethingElse = 0; \
638 (pPage)->idPageX = (_idPage); \
639 /*(pPage)->u3Type = (_uType); - later */ \
640 PGM_PAGE_SET_TYPE(pPage, _uType); \
641 (pPage)->u29B = 0; \
642 } while (0)
643
644/**
645 * Initializes the page structure of a ZERO page.
646 * @param pPage Pointer to the physical guest page tracking structure.
647 */
648#ifdef VBOX_WITH_NEW_PHYS_CODE
649# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
650 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
651#else
652# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
653 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
654#endif
655/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
656# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
657 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
658
659
660/** @name The Page state, PGMPAGE::u2StateX.
661 * @{ */
662/** The zero page.
663 * This is a per-VM page that's never ever mapped writable. */
664#define PGM_PAGE_STATE_ZERO 0
665/** A allocated page.
666 * This is a per-VM page allocated from the page pool (or wherever
667 * we get MMIO2 pages from if the type is MMIO2).
668 */
669#define PGM_PAGE_STATE_ALLOCATED 1
670/** A allocated page that's being monitored for writes.
671 * The shadow page table mappings are read-only. When a write occurs, the
672 * fWrittenTo member is set, the page remapped as read-write and the state
673 * moved back to allocated. */
674#define PGM_PAGE_STATE_WRITE_MONITORED 2
675/** The page is shared, aka. copy-on-write.
676 * This is a page that's shared with other VMs. */
677#define PGM_PAGE_STATE_SHARED 3
678/** @} */
679
680
681/**
682 * Gets the page state.
683 * @returns page state (PGM_PAGE_STATE_*).
684 * @param pPage Pointer to the physical guest page tracking structure.
685 */
686#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
687
688/**
689 * Sets the page state.
690 * @param pPage Pointer to the physical guest page tracking structure.
691 * @param _uState The new page state.
692 */
693#define PGM_PAGE_SET_STATE(pPage, _uState) \
694 do { (pPage)->u2StateX = (_uState); } while (0)
695
696
697/**
698 * Gets the host physical address of the guest page.
699 * @returns host physical address (RTHCPHYS).
700 * @param pPage Pointer to the physical guest page tracking structure.
701 */
702#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
703
704/**
705 * Sets the host physical address of the guest page.
706 * @param pPage Pointer to the physical guest page tracking structure.
707 * @param _HCPhys The new host physical address.
708 */
709#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
710 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
711 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
712
713/**
714 * Get the Page ID.
715 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
719/* later:
720#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
721 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
722*/
723/**
724 * Sets the Page ID.
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
728/* later:
729#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
730 | ((_idPage) & 0xfff) \
731 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
732*/
733
734/**
735 * Get the Chunk ID.
736 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
740/* later:
741#if GMM_CHUNKID_SHIFT == 12
742# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
743#elif GMM_CHUNKID_SHIFT > 12
744# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
745#elif GMM_CHUNKID_SHIFT < 12
746# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
747 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
748#else
749# error "GMM_CHUNKID_SHIFT isn't defined or something."
750#endif
751*/
752
753/**
754 * Get the index of the page within the allocaiton chunk.
755 * @returns The page index.
756 * @param pPage Pointer to the physical guest page tracking structure.
757 */
758#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
759/* later:
760#if GMM_CHUNKID_SHIFT <= 12
761# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
762#else
763# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
764 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
765#endif
766*/
767
768
769/**
770 * Gets the page type.
771 * @returns The page type.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
775
776/**
777 * Sets the page type.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 * @param _enmType The new page type (PGMPAGETYPE).
780 */
781#ifdef VBOX_WITH_NEW_PHYS_CODE
782#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
783 do { (pPage)->u3Type = (_enmType); } while (0)
784#else
785#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
786 do { \
787 (pPage)->u3Type = (_enmType); \
788 if ((_enmType) == PGMPAGETYPE_ROM) \
789 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM; \
790 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
791 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
792 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
793 (pPage)->HCPhysX |= MM_RAM_FLAGS_MMIO2; \
794 } while (0)
795#endif
796
797
798/**
799 * Checks if the page is 'reserved'.
800 * @returns true/false.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
804
805/**
806 * Checks if the page is marked for MMIO.
807 * @returns true/false.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#ifdef VBOX_WITH_NEW_PHYS_CODE
811# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
812#else
813# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
814#endif
815
816/**
817 * Checks if the page is backed by the ZERO page.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
822
823/**
824 * Checks if the page is backed by a SHARED page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
829
830
831/**
832 * Marks the paget as written to (for GMM change monitoring).
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
836
837/**
838 * Clears the written-to indicator.
839 * @param pPage Pointer to the physical guest page tracking structure.
840 */
841#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
842
843/**
844 * Checks if the page was marked as written-to.
845 * @returns true/false.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
849
850
851/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
852 *
853 * @remarks The values are assigned in order of priority, so we can calculate
854 * the correct state for a page with different handlers installed.
855 * @{ */
856/** No handler installed. */
857#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
858/** Monitoring is temporarily disabled. */
859#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
860/** Write access is monitored. */
861#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
862/** All access is monitored. */
863#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
864/** @} */
865
866/**
867 * Gets the physical access handler state of a page.
868 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
869 * @param pPage Pointer to the physical guest page tracking structure.
870 */
871#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
872
873/**
874 * Sets the physical access handler state of a page.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 * @param _uState The new state value.
877 */
878#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
879 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
880
881/**
882 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
883 * @returns true/false
884 * @param pPage Pointer to the physical guest page tracking structure.
885 */
886#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
887
888/**
889 * Checks if the page has any active physical access handlers.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
894
895
896/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
897 *
898 * @remarks The values are assigned in order of priority, so we can calculate
899 * the correct state for a page with different handlers installed.
900 * @{ */
901/** No handler installed. */
902#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
903/* 1 is reserved so the lineup is identical with the physical ones. */
904/** Write access is monitored. */
905#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
906/** All access is monitored. */
907#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
908/** @} */
909
910/**
911 * Gets the virtual access handler state of a page.
912 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
913 * @param pPage Pointer to the physical guest page tracking structure.
914 */
915#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
916
917/**
918 * Sets the virtual access handler state of a page.
919 * @param pPage Pointer to the physical guest page tracking structure.
920 * @param _uState The new state value.
921 */
922#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
923 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
924
925/**
926 * Checks if the page has any virtual access handlers.
927 * @returns true/false
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
931
932/**
933 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
934 * virtual handlers.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
939
940
941
942/**
943 * Checks if the page has any access handlers, including temporarily disabled ones.
944 * @returns true/false
945 * @param pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
948 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
949 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951/**
952 * Checks if the page has any active access handlers.
953 * @returns true/false
954 * @param pPage Pointer to the physical guest page tracking structure.
955 */
956#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
957 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
958 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
959
960/**
961 * Checks if the page has any active access handlers catching all accesses.
962 * @returns true/false
963 * @param pPage Pointer to the physical guest page tracking structure.
964 */
965#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
967 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
968
969
970
971
972/** @def PGM_PAGE_GET_TRACKING
973 * Gets the packed shadow page pool tracking data associated with a guest page.
974 * @returns uint16_t containing the data.
975 * @param pPage Pointer to the physical guest page tracking structure.
976 */
977#define PGM_PAGE_GET_TRACKING(pPage) \
978 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
979
980/** @def PGM_PAGE_SET_TRACKING
981 * Sets the packed shadow page pool tracking data associated with a guest page.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 * @param u16TrackingData The tracking data to store.
984 */
985#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
986 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
987
988/** @def PGM_PAGE_GET_TD_CREFS
989 * Gets the @a cRefs tracking data member.
990 * @returns cRefs.
991 * @param pPage Pointer to the physical guest page tracking structure.
992 */
993#define PGM_PAGE_GET_TD_CREFS(pPage) \
994 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
995
996#define PGM_PAGE_GET_TD_IDX(pPage) \
997 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
998
999/**
1000 * Ram range for GC Phys to HC Phys conversion.
1001 *
1002 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1003 * conversions too, but we'll let MM handle that for now.
1004 *
1005 * This structure is used by linked lists in both GC and HC.
1006 */
1007typedef struct PGMRAMRANGE
1008{
1009 /** Pointer to the next RAM range - for R3. */
1010 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1011 /** Pointer to the next RAM range - for R0. */
1012 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1013 /** Pointer to the next RAM range - for RC. */
1014 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1015 /** Pointer alignment. */
1016 RTRCPTR RCPtrAlignment;
1017 /** Start of the range. Page aligned. */
1018 RTGCPHYS GCPhys;
1019 /** Last address in the range (inclusive). Page aligned (-1). */
1020 RTGCPHYS GCPhysLast;
1021 /** Size of the range. (Page aligned of course). */
1022 RTGCPHYS cb;
1023 /** MM_RAM_* flags */
1024 uint32_t fFlags;
1025 uint32_t u32Alignment; /**< alignment. */
1026#ifndef VBOX_WITH_NEW_PHYS_CODE
1027 /** R3 virtual lookup ranges for chunks.
1028 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1029 * @remarks This is occationally accessed from ring-0!! (not darwin) */
1030# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1031 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1032# else
1033 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1034# endif
1035#endif
1036 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1037 R3PTRTYPE(void *) pvR3;
1038 /** The range description. */
1039 R3PTRTYPE(const char *) pszDesc;
1040
1041 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1042#ifdef VBOX_WITH_NEW_PHYS_CODE
1043 uint32_t au32Reserved[2];
1044#elif HC_ARCH_BITS == 32
1045 uint32_t au32Reserved[1];
1046#endif
1047
1048 /** Array of physical guest page tracking structures. */
1049 PGMPAGE aPages[1];
1050} PGMRAMRANGE;
1051/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1052typedef PGMRAMRANGE *PPGMRAMRANGE;
1053
1054#ifndef VBOX_WITH_NEW_PHYS_CODE
1055/** Return hc ptr corresponding to the ram range and physical offset */
1056#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1057 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1058 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1059#endif
1060
1061/**
1062 * Per page tracking structure for ROM image.
1063 *
1064 * A ROM image may have a shadow page, in which case we may have
1065 * two pages backing it. This structure contains the PGMPAGE for
1066 * both while PGMRAMRANGE have a copy of the active one. It is
1067 * important that these aren't out of sync in any regard other
1068 * than page pool tracking data.
1069 */
1070typedef struct PGMROMPAGE
1071{
1072 /** The page structure for the virgin ROM page. */
1073 PGMPAGE Virgin;
1074 /** The page structure for the shadow RAM page. */
1075 PGMPAGE Shadow;
1076 /** The current protection setting. */
1077 PGMROMPROT enmProt;
1078 /** Pad the structure size to a multiple of 8. */
1079 uint32_t u32Padding;
1080} PGMROMPAGE;
1081/** Pointer to a ROM page tracking structure. */
1082typedef PGMROMPAGE *PPGMROMPAGE;
1083
1084
1085/**
1086 * A registered ROM image.
1087 *
1088 * This is needed to keep track of ROM image since they generally
1089 * intrude into a PGMRAMRANGE. It also keeps track of additional
1090 * info like the two page sets (read-only virgin and read-write shadow),
1091 * the current state of each page.
1092 *
1093 * Because access handlers cannot easily be executed in a different
1094 * context, the ROM ranges needs to be accessible and in all contexts.
1095 */
1096typedef struct PGMROMRANGE
1097{
1098 /** Pointer to the next range - R3. */
1099 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1100 /** Pointer to the next range - R0. */
1101 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1102 /** Pointer to the next range - RC. */
1103 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1104 /** Pointer alignment */
1105 RTRCPTR GCPtrAlignment;
1106 /** Address of the range. */
1107 RTGCPHYS GCPhys;
1108 /** Address of the last byte in the range. */
1109 RTGCPHYS GCPhysLast;
1110 /** Size of the range. */
1111 RTGCPHYS cb;
1112 /** The flags (PGMPHYS_ROM_FLAG_*). */
1113 uint32_t fFlags;
1114 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1115 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1116 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1117 * This is used for strictness checks. */
1118 R3PTRTYPE(const void *) pvOriginal;
1119 /** The ROM description. */
1120 R3PTRTYPE(const char *) pszDesc;
1121 /** The per page tracking structures. */
1122 PGMROMPAGE aPages[1];
1123} PGMROMRANGE;
1124/** Pointer to a ROM range. */
1125typedef PGMROMRANGE *PPGMROMRANGE;
1126
1127
1128/**
1129 * A registered MMIO2 (= Device RAM) range.
1130 *
1131 * There are a few reason why we need to keep track of these
1132 * registrations. One of them is the deregistration & cleanup
1133 * stuff, while another is that the PGMRAMRANGE associated with
1134 * such a region may have to be removed from the ram range list.
1135 *
1136 * Overlapping with a RAM range has to be 100% or none at all. The
1137 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1138 * meditation will be raised if a partial overlap or an overlap of
1139 * ROM pages is encountered. On an overlap we will free all the
1140 * existing RAM pages and put in the ram range pages instead.
1141 */
1142typedef struct PGMMMIO2RANGE
1143{
1144 /** The owner of the range. (a device) */
1145 PPDMDEVINSR3 pDevInsR3;
1146 /** Pointer to the ring-3 mapping of the allocation. */
1147 RTR3PTR pvR3;
1148 /** Pointer to the next range - R3. */
1149 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1150 /** Whether it's mapped or not. */
1151 bool fMapped;
1152 /** Whether it's overlapping or not. */
1153 bool fOverlapping;
1154 /** The PCI region number.
1155 * @remarks This ASSUMES that nobody will ever really need to have multiple
1156 * PCI devices with matching MMIO region numbers on a single device. */
1157 uint8_t iRegion;
1158 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1159 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1160 /** The associated RAM range. */
1161 PGMRAMRANGE RamRange;
1162} PGMMMIO2RANGE;
1163/** Pointer to a MMIO2 range. */
1164typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1165
1166
1167
1168
1169/**
1170 * PGMPhysRead/Write cache entry
1171 */
1172typedef struct PGMPHYSCACHEENTRY
1173{
1174 /** R3 pointer to physical page. */
1175 R3PTRTYPE(uint8_t *) pbR3;
1176 /** GC Physical address for cache entry */
1177 RTGCPHYS GCPhys;
1178#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1179 RTGCPHYS u32Padding0; /**< alignment padding. */
1180#endif
1181} PGMPHYSCACHEENTRY;
1182
1183/**
1184 * PGMPhysRead/Write cache to reduce REM memory access overhead
1185 */
1186typedef struct PGMPHYSCACHE
1187{
1188 /** Bitmap of valid cache entries */
1189 uint64_t aEntries;
1190 /** Cache entries */
1191 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1192} PGMPHYSCACHE;
1193
1194
1195/** Pointer to an allocation chunk ring-3 mapping. */
1196typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1197/** Pointer to an allocation chunk ring-3 mapping pointer. */
1198typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1199
1200/**
1201 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1202 *
1203 * The primary tree (Core) uses the chunk id as key.
1204 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1205 */
1206typedef struct PGMCHUNKR3MAP
1207{
1208 /** The key is the chunk id. */
1209 AVLU32NODECORE Core;
1210 /** The key is the ageing sequence number. */
1211 AVLLU32NODECORE AgeCore;
1212 /** The current age thingy. */
1213 uint32_t iAge;
1214 /** The current reference count. */
1215 uint32_t volatile cRefs;
1216 /** The current permanent reference count. */
1217 uint32_t volatile cPermRefs;
1218 /** The mapping address. */
1219 void *pv;
1220} PGMCHUNKR3MAP;
1221
1222/**
1223 * Allocation chunk ring-3 mapping TLB entry.
1224 */
1225typedef struct PGMCHUNKR3MAPTLBE
1226{
1227 /** The chunk id. */
1228 uint32_t volatile idChunk;
1229#if HC_ARCH_BITS == 64
1230 uint32_t u32Padding; /**< alignment padding. */
1231#endif
1232 /** The chunk map. */
1233#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1234 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1235#else
1236 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1237#endif
1238} PGMCHUNKR3MAPTLBE;
1239/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1240typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1241
1242/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1243 * @remark Must be a power of two value. */
1244#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1245
1246/**
1247 * Allocation chunk ring-3 mapping TLB.
1248 *
1249 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1250 * At first glance this might look kinda odd since AVL trees are
1251 * supposed to give the most optimial lookup times of all trees
1252 * due to their balancing. However, take a tree with 1023 nodes
1253 * in it, that's 10 levels, meaning that most searches has to go
1254 * down 9 levels before they find what they want. This isn't fast
1255 * compared to a TLB hit. There is the factor of cache misses,
1256 * and of course the problem with trees and branch prediction.
1257 * This is why we use TLBs in front of most of the trees.
1258 *
1259 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1260 * difficult when we switch to the new inlined AVL trees (from kStuff).
1261 */
1262typedef struct PGMCHUNKR3MAPTLB
1263{
1264 /** The TLB entries. */
1265 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1266} PGMCHUNKR3MAPTLB;
1267
1268/**
1269 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1270 * @returns Chunk TLB index.
1271 * @param idChunk The Chunk ID.
1272 */
1273#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1274
1275
1276/**
1277 * Ring-3 guest page mapping TLB entry.
1278 * @remarks used in ring-0 as well at the moment.
1279 */
1280typedef struct PGMPAGER3MAPTLBE
1281{
1282 /** Address of the page. */
1283 RTGCPHYS volatile GCPhys;
1284 /** The guest page. */
1285#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1286 R3PTRTYPE(PPGMPAGE) volatile pPage;
1287#else
1288 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1289#endif
1290 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1291#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1292 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1293#else
1294 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1295#endif
1296 /** The address */
1297#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1298 R3PTRTYPE(void *) volatile pv;
1299#else
1300 R3R0PTRTYPE(void *) volatile pv;
1301#endif
1302#if HC_ARCH_BITS == 32
1303 uint32_t u32Padding; /**< alignment padding. */
1304#endif
1305} PGMPAGER3MAPTLBE;
1306/** Pointer to an entry in the HC physical TLB. */
1307typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1308
1309
1310/** The number of entries in the ring-3 guest page mapping TLB.
1311 * @remarks The value must be a power of two. */
1312#define PGM_PAGER3MAPTLB_ENTRIES 64
1313
1314/**
1315 * Ring-3 guest page mapping TLB.
1316 * @remarks used in ring-0 as well at the moment.
1317 */
1318typedef struct PGMPAGER3MAPTLB
1319{
1320 /** The TLB entries. */
1321 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1322} PGMPAGER3MAPTLB;
1323/** Pointer to the ring-3 guest page mapping TLB. */
1324typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1325
1326/**
1327 * Calculates the index of the TLB entry for the specified guest page.
1328 * @returns Physical TLB index.
1329 * @param GCPhys The guest physical address.
1330 */
1331#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1332
1333
1334/**
1335 * Mapping cache usage set entry.
1336 *
1337 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1338 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1339 * cache. If it's extended to include ring-3, well, then something will
1340 * have be changed here...
1341 */
1342typedef struct PGMMAPSETENTRY
1343{
1344 /** The mapping cache index. */
1345 uint16_t iPage;
1346 /** The number of references.
1347 * The max is UINT16_MAX - 1. */
1348 uint16_t cRefs;
1349 /** Pointer to the page. */
1350 RTR0PTR pvPage;
1351 /** The physical address for this entry. */
1352 RTHCPHYS HCPhys;
1353} PGMMAPSETENTRY;
1354/** Pointer to a mapping cache usage set entry. */
1355typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1356
1357/**
1358 * Mapping cache usage set.
1359 *
1360 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1361 * done during exits / traps. The set is
1362 */
1363typedef struct PGMMAPSET
1364{
1365 /** The number of occupied entries.
1366 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1367 * dynamic mappings. */
1368 uint32_t cEntries;
1369 /** The start of the current subset.
1370 * This is UINT32_MAX if no subset is currently open. */
1371 uint32_t iSubset;
1372 /** The index of the current CPU, only valid if the set is open. */
1373 int32_t iCpu;
1374 /** The entries. */
1375 PGMMAPSETENTRY aEntries[64];
1376 /** HCPhys -> iEntry fast lookup table.
1377 * Use PGMMAPSET_HASH for hashing.
1378 * The entries may or may not be valid, check against cEntries. */
1379 uint8_t aiHashTable[128];
1380} PGMMAPSET;
1381/** Pointer to the mapping cache set. */
1382typedef PGMMAPSET *PPGMMAPSET;
1383
1384/** PGMMAPSET::cEntries value for a closed set. */
1385#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1386
1387/** Hash function for aiHashTable. */
1388#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1389
1390/** The max fill size (strict builds). */
1391#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1392
1393
1394/** @name Context neutrual page mapper TLB.
1395 *
1396 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1397 * code is writting in a kind of context neutrual way. Time will show whether
1398 * this actually makes sense or not...
1399 *
1400 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1401 * context ends up using a global mapping cache on some platforms
1402 * (darwin).
1403 *
1404 * @{ */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB pointer type for the current context. */
1407/** @typedef PPGMPAGEMAPTLB
1408 * The page mapper TLB entry pointer type for the current context. */
1409/** @typedef PPGMPAGEMAPTLB
1410 * The page mapper TLB entry pointer pointer type for the current context. */
1411/** @def PGM_PAGEMAPTLB_ENTRIES
1412 * The number of TLB entries in the page mapper TLB for the current context. */
1413/** @def PGM_PAGEMAPTLB_IDX
1414 * Calculate the TLB index for a guest physical address.
1415 * @returns The TLB index.
1416 * @param GCPhys The guest physical address. */
1417/** @typedef PPGMPAGEMAP
1418 * Pointer to a page mapper unit for current context. */
1419/** @typedef PPPGMPAGEMAP
1420 * Pointer to a page mapper unit pointer for current context. */
1421#ifdef IN_RC
1422// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1423// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1424// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1425# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1426# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1427 typedef void * PPGMPAGEMAP;
1428 typedef void ** PPPGMPAGEMAP;
1429//#elif IN_RING0
1430// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1431// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1432// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1433//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1434//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1435// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1436// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1437#else
1438 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1439 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1440 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1441# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1442# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1443 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1444 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1445#endif
1446/** @} */
1447
1448
1449/** @name PGM Pool Indexes.
1450 * Aka. the unique shadow page identifier.
1451 * @{ */
1452/** NIL page pool IDX. */
1453#define NIL_PGMPOOL_IDX 0
1454/** The first normal index. */
1455#define PGMPOOL_IDX_FIRST_SPECIAL 1
1456#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1457/** Page directory (32-bit root). */
1458#define PGMPOOL_IDX_PD 1
1459/** Page Directory Pointer Table (PAE root). */
1460#define PGMPOOL_IDX_PDPT 2
1461/** AMD64 CR3 level index.*/
1462#define PGMPOOL_IDX_AMD64_CR3 3
1463/** Nested paging root.*/
1464#define PGMPOOL_IDX_NESTED_ROOT 4
1465/** The first normal index. */
1466#define PGMPOOL_IDX_FIRST 5
1467#else
1468/** Page directory (32-bit root). */
1469#define PGMPOOL_IDX_PD 1
1470/** The extended PAE page directory (2048 entries, works as root currently). */
1471#define PGMPOOL_IDX_PAE_PD 2
1472/** PAE Page Directory Table 0. */
1473#define PGMPOOL_IDX_PAE_PD_0 3
1474/** PAE Page Directory Table 1. */
1475#define PGMPOOL_IDX_PAE_PD_1 4
1476/** PAE Page Directory Table 2. */
1477#define PGMPOOL_IDX_PAE_PD_2 5
1478/** PAE Page Directory Table 3. */
1479#define PGMPOOL_IDX_PAE_PD_3 6
1480/** Page Directory Pointer Table (PAE root, not currently used). */
1481#define PGMPOOL_IDX_PDPT 7
1482/** AMD64 CR3 level index.*/
1483#define PGMPOOL_IDX_AMD64_CR3 8
1484/** Nested paging root.*/
1485#define PGMPOOL_IDX_NESTED_ROOT 9
1486/** The first normal index. */
1487#define PGMPOOL_IDX_FIRST 10
1488#endif
1489/** The last valid index. (inclusive, 14 bits) */
1490#define PGMPOOL_IDX_LAST 0x3fff
1491/** @} */
1492
1493/** The NIL index for the parent chain. */
1494#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1495
1496/**
1497 * Node in the chain linking a shadowed page to it's parent (user).
1498 */
1499#pragma pack(1)
1500typedef struct PGMPOOLUSER
1501{
1502 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1503 uint16_t iNext;
1504 /** The user page index. */
1505 uint16_t iUser;
1506 /** Index into the user table. */
1507 uint32_t iUserTable;
1508} PGMPOOLUSER, *PPGMPOOLUSER;
1509typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1510#pragma pack()
1511
1512
1513/** The NIL index for the phys ext chain. */
1514#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1515
1516/**
1517 * Node in the chain of physical cross reference extents.
1518 * @todo Calling this an 'extent' is not quite right, find a better name.
1519 */
1520#pragma pack(1)
1521typedef struct PGMPOOLPHYSEXT
1522{
1523 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1524 uint16_t iNext;
1525 /** The user page index. */
1526 uint16_t aidx[3];
1527} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1528typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1529#pragma pack()
1530
1531
1532/**
1533 * The kind of page that's being shadowed.
1534 */
1535typedef enum PGMPOOLKIND
1536{
1537 /** The virtual invalid 0 entry. */
1538 PGMPOOLKIND_INVALID = 0,
1539 /** The entry is free (=unused). */
1540 PGMPOOLKIND_FREE,
1541
1542 /** Shw: 32-bit page table; Gst: no paging */
1543 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1544 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1545 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1546 /** Shw: 32-bit page table; Gst: 4MB page. */
1547 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1548 /** Shw: PAE page table; Gst: no paging */
1549 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1550 /** Shw: PAE page table; Gst: 32-bit page table. */
1551 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1552 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1553 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1554 /** Shw: PAE page table; Gst: PAE page table. */
1555 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1556 /** Shw: PAE page table; Gst: 2MB page. */
1557 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1558
1559 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1560 PGMPOOLKIND_32BIT_PD,
1561 /** Shw: 32-bit page directory. Gst: no paging. */
1562 PGMPOOLKIND_32BIT_PD_PHYS,
1563 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1564 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1565 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1566 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1567 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1568 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1569 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1570 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1571 /** Shw: PAE page directory; Gst: PAE page directory. */
1572 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1573 /** Shw: PAE page directory; Gst: no paging. */
1574 PGMPOOLKIND_PAE_PD_PHYS,
1575
1576 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1577 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1578 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1579 PGMPOOLKIND_PAE_PDPT,
1580 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1581 PGMPOOLKIND_PAE_PDPT_PHYS,
1582
1583 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1584 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1585 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1586 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1587 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1588 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1589 /** Shw: 64-bit page directory table; Gst: no paging */
1590 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1591
1592 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1593 PGMPOOLKIND_64BIT_PML4,
1594
1595 /** Shw: EPT page directory pointer table; Gst: no paging */
1596 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1597 /** Shw: EPT page directory table; Gst: no paging */
1598 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1599 /** Shw: EPT page table; Gst: no paging */
1600 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1601
1602#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1603 /** Shw: Root 32-bit page directory. */
1604 PGMPOOLKIND_ROOT_32BIT_PD,
1605 /** Shw: Root PAE page directory */
1606 PGMPOOLKIND_ROOT_PAE_PD,
1607 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1608 PGMPOOLKIND_ROOT_PDPT,
1609#endif
1610 /** Shw: Root Nested paging table. */
1611 PGMPOOLKIND_ROOT_NESTED,
1612
1613 /** The last valid entry. */
1614 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1615} PGMPOOLKIND;
1616
1617
1618/**
1619 * The tracking data for a page in the pool.
1620 */
1621typedef struct PGMPOOLPAGE
1622{
1623 /** AVL node code with the (R3) physical address of this page. */
1624 AVLOHCPHYSNODECORE Core;
1625 /** Pointer to the R3 mapping of the page. */
1626#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1627 R3PTRTYPE(void *) pvPageR3;
1628#else
1629 R3R0PTRTYPE(void *) pvPageR3;
1630#endif
1631 /** The guest physical address. */
1632#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1633 uint32_t Alignment0;
1634#endif
1635 RTGCPHYS GCPhys;
1636 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1637 uint8_t enmKind;
1638 uint8_t bPadding;
1639 /** The index of this page. */
1640 uint16_t idx;
1641 /** The next entry in the list this page currently resides in.
1642 * It's either in the free list or in the GCPhys hash. */
1643 uint16_t iNext;
1644#ifdef PGMPOOL_WITH_USER_TRACKING
1645 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1646 uint16_t iUserHead;
1647 /** The number of present entries. */
1648 uint16_t cPresent;
1649 /** The first entry in the table which is present. */
1650 uint16_t iFirstPresent;
1651#endif
1652#ifdef PGMPOOL_WITH_MONITORING
1653 /** The number of modifications to the monitored page. */
1654 uint16_t cModifications;
1655 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1656 uint16_t iModifiedNext;
1657 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1658 uint16_t iModifiedPrev;
1659 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1660 uint16_t iMonitoredNext;
1661 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1662 uint16_t iMonitoredPrev;
1663#endif
1664#ifdef PGMPOOL_WITH_CACHE
1665 /** The next page in the age list. */
1666 uint16_t iAgeNext;
1667 /** The previous page in the age list. */
1668 uint16_t iAgePrev;
1669#endif /* PGMPOOL_WITH_CACHE */
1670 /** Used to indicate that the page is zeroed. */
1671 bool fZeroed;
1672 /** Used to indicate that a PT has non-global entries. */
1673 bool fSeenNonGlobal;
1674 /** Used to indicate that we're monitoring writes to the guest page. */
1675 bool fMonitored;
1676 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1677 * (All pages are in the age list.) */
1678 bool fCached;
1679 /** This is used by the R3 access handlers when invoked by an async thread.
1680 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1681 bool volatile fReusedFlushPending;
1682#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1683 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1684 bool fLocked;
1685#else
1686 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1687 * In these cases the access handler acts differently and will check
1688 * for mapping conflicts like the normal CR3 handler.
1689 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1690 * replaced by a list of pages which share access handler.
1691 */
1692 bool fCR3Mix;
1693#endif
1694} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1695
1696
1697#ifdef PGMPOOL_WITH_CACHE
1698/** The hash table size. */
1699# define PGMPOOL_HASH_SIZE 0x40
1700/** The hash function. */
1701# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1702#endif
1703
1704
1705/**
1706 * The shadow page pool instance data.
1707 *
1708 * It's all one big allocation made at init time, except for the
1709 * pages that is. The user nodes follows immediatly after the
1710 * page structures.
1711 */
1712typedef struct PGMPOOL
1713{
1714 /** The VM handle - R3 Ptr. */
1715 PVMR3 pVMR3;
1716 /** The VM handle - R0 Ptr. */
1717 PVMR0 pVMR0;
1718 /** The VM handle - RC Ptr. */
1719 PVMRC pVMRC;
1720 /** The max pool size. This includes the special IDs. */
1721 uint16_t cMaxPages;
1722 /** The current pool size. */
1723 uint16_t cCurPages;
1724 /** The head of the free page list. */
1725 uint16_t iFreeHead;
1726 /* Padding. */
1727 uint16_t u16Padding;
1728#ifdef PGMPOOL_WITH_USER_TRACKING
1729 /** Head of the chain of free user nodes. */
1730 uint16_t iUserFreeHead;
1731 /** The number of user nodes we've allocated. */
1732 uint16_t cMaxUsers;
1733 /** The number of present page table entries in the entire pool. */
1734 uint32_t cPresent;
1735 /** Pointer to the array of user nodes - RC pointer. */
1736 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1737 /** Pointer to the array of user nodes - R3 pointer. */
1738 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1739 /** Pointer to the array of user nodes - R0 pointer. */
1740 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1741#endif /* PGMPOOL_WITH_USER_TRACKING */
1742#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1743 /** Head of the chain of free phys ext nodes. */
1744 uint16_t iPhysExtFreeHead;
1745 /** The number of user nodes we've allocated. */
1746 uint16_t cMaxPhysExts;
1747 /** Pointer to the array of physical xref extent - RC pointer. */
1748 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1749 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1750 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1751 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1752 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1753#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1754#ifdef PGMPOOL_WITH_CACHE
1755 /** Hash table for GCPhys addresses. */
1756 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1757 /** The head of the age list. */
1758 uint16_t iAgeHead;
1759 /** The tail of the age list. */
1760 uint16_t iAgeTail;
1761 /** Set if the cache is enabled. */
1762 bool fCacheEnabled;
1763#endif /* PGMPOOL_WITH_CACHE */
1764#ifdef PGMPOOL_WITH_MONITORING
1765 /** Head of the list of modified pages. */
1766 uint16_t iModifiedHead;
1767 /** The current number of modified pages. */
1768 uint16_t cModifiedPages;
1769 /** Access handler, RC. */
1770 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1771 /** Access handler, R0. */
1772 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1773 /** Access handler, R3. */
1774 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1775 /** The access handler description (HC ptr). */
1776 R3PTRTYPE(const char *) pszAccessHandler;
1777#endif /* PGMPOOL_WITH_MONITORING */
1778 /** The number of pages currently in use. */
1779 uint16_t cUsedPages;
1780#ifdef VBOX_WITH_STATISTICS
1781 /** The high wather mark for cUsedPages. */
1782 uint16_t cUsedPagesHigh;
1783 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1784 /** Profiling pgmPoolAlloc(). */
1785 STAMPROFILEADV StatAlloc;
1786 /** Profiling pgmPoolClearAll(). */
1787 STAMPROFILE StatClearAll;
1788 /** Profiling pgmPoolFlushAllInt(). */
1789 STAMPROFILE StatFlushAllInt;
1790 /** Profiling pgmPoolFlushPage(). */
1791 STAMPROFILE StatFlushPage;
1792 /** Profiling pgmPoolFree(). */
1793 STAMPROFILE StatFree;
1794 /** Profiling time spent zeroing pages. */
1795 STAMPROFILE StatZeroPage;
1796# ifdef PGMPOOL_WITH_USER_TRACKING
1797 /** Profiling of pgmPoolTrackDeref. */
1798 STAMPROFILE StatTrackDeref;
1799 /** Profiling pgmTrackFlushGCPhysPT. */
1800 STAMPROFILE StatTrackFlushGCPhysPT;
1801 /** Profiling pgmTrackFlushGCPhysPTs. */
1802 STAMPROFILE StatTrackFlushGCPhysPTs;
1803 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1804 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1805 /** Number of times we've been out of user records. */
1806 STAMCOUNTER StatTrackFreeUpOneUser;
1807# endif
1808# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1809 /** Profiling deref activity related tracking GC physical pages. */
1810 STAMPROFILE StatTrackDerefGCPhys;
1811 /** Number of linear searches for a HCPhys in the ram ranges. */
1812 STAMCOUNTER StatTrackLinearRamSearches;
1813 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1814 STAMCOUNTER StamTrackPhysExtAllocFailures;
1815# endif
1816# ifdef PGMPOOL_WITH_MONITORING
1817 /** Profiling the RC/R0 access handler. */
1818 STAMPROFILE StatMonitorRZ;
1819 /** Times we've failed interpreting the instruction. */
1820 STAMCOUNTER StatMonitorRZEmulateInstr;
1821 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1822 STAMPROFILE StatMonitorRZFlushPage;
1823 /** Times we've detected fork(). */
1824 STAMCOUNTER StatMonitorRZFork;
1825 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1826 STAMPROFILE StatMonitorRZHandled;
1827 /** Times we've failed interpreting a patch code instruction. */
1828 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1829 /** Times we've failed interpreting a patch code instruction during flushing. */
1830 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1831 /** The number of times we've seen rep prefixes we can't handle. */
1832 STAMCOUNTER StatMonitorRZRepPrefix;
1833 /** Profiling the REP STOSD cases we've handled. */
1834 STAMPROFILE StatMonitorRZRepStosd;
1835
1836 /** Profiling the R3 access handler. */
1837 STAMPROFILE StatMonitorR3;
1838 /** Times we've failed interpreting the instruction. */
1839 STAMCOUNTER StatMonitorR3EmulateInstr;
1840 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1841 STAMPROFILE StatMonitorR3FlushPage;
1842 /** Times we've detected fork(). */
1843 STAMCOUNTER StatMonitorR3Fork;
1844 /** Profiling the R3 access we've handled (except REP STOSD). */
1845 STAMPROFILE StatMonitorR3Handled;
1846 /** The number of times we've seen rep prefixes we can't handle. */
1847 STAMCOUNTER StatMonitorR3RepPrefix;
1848 /** Profiling the REP STOSD cases we've handled. */
1849 STAMPROFILE StatMonitorR3RepStosd;
1850 /** The number of times we're called in an async thread an need to flush. */
1851 STAMCOUNTER StatMonitorR3Async;
1852 /** The high wather mark for cModifiedPages. */
1853 uint16_t cModifiedPagesHigh;
1854 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1855# endif
1856# ifdef PGMPOOL_WITH_CACHE
1857 /** The number of cache hits. */
1858 STAMCOUNTER StatCacheHits;
1859 /** The number of cache misses. */
1860 STAMCOUNTER StatCacheMisses;
1861 /** The number of times we've got a conflict of 'kind' in the cache. */
1862 STAMCOUNTER StatCacheKindMismatches;
1863 /** Number of times we've been out of pages. */
1864 STAMCOUNTER StatCacheFreeUpOne;
1865 /** The number of cacheable allocations. */
1866 STAMCOUNTER StatCacheCacheable;
1867 /** The number of uncacheable allocations. */
1868 STAMCOUNTER StatCacheUncacheable;
1869# endif
1870#elif HC_ARCH_BITS == 64
1871 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1872#endif
1873 /** The AVL tree for looking up a page by its HC physical address. */
1874 AVLOHCPHYSTREE HCPhysTree;
1875 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1876 /** Array of pages. (cMaxPages in length)
1877 * The Id is the index into thist array.
1878 */
1879 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1880} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1881
1882
1883/** @def PGMPOOL_PAGE_2_PTR
1884 * Maps a pool page pool into the current context.
1885 *
1886 * @returns VBox status code.
1887 * @param pVM The VM handle.
1888 * @param pPage The pool page.
1889 *
1890 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1891 * small page window employeed by that function. Be careful.
1892 * @remark There is no need to assert on the result.
1893 */
1894#if defined(IN_RC)
1895# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1896#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1897# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1898#elif defined(VBOX_STRICT)
1899# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1900DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1901{
1902 Assert(pPage && pPage->pvPageR3);
1903 return pPage->pvPageR3;
1904}
1905#else
1906# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1907#endif
1908
1909/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1910 * Maps a pool page pool into the current context.
1911 *
1912 * @returns VBox status code.
1913 * @param pPGM Pointer to the PGM instance data.
1914 * @param pPage The pool page.
1915 *
1916 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1917 * small page window employeed by that function. Be careful.
1918 * @remark There is no need to assert on the result.
1919 */
1920#if defined(IN_RC)
1921# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1922#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1923# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1924#else
1925# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1926#endif
1927
1928
1929/** @name Per guest page tracking data.
1930 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1931 * is to use more bits for it and split it up later on. But for now we'll play
1932 * safe and change as little as possible.
1933 *
1934 * The 16-bit word has two parts:
1935 *
1936 * The first 14-bit forms the @a idx field. It is either the index of a page in
1937 * the shadow page pool, or and index into the extent list.
1938 *
1939 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1940 * shadow page pool references to the page. If cRefs equals
1941 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1942 * (misnomer) table and not the shadow page pool.
1943 *
1944 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1945 * the 16-bit word.
1946 *
1947 * @{ */
1948/** The shift count for getting to the cRefs part. */
1949#define PGMPOOL_TD_CREFS_SHIFT 14
1950/** The mask applied after shifting the tracking data down by
1951 * PGMPOOL_TD_CREFS_SHIFT. */
1952#define PGMPOOL_TD_CREFS_MASK 0x3
1953/** The cRef value used to indiciate that the idx is the head of a
1954 * physical cross reference list. */
1955#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1956/** The shift used to get idx. */
1957#define PGMPOOL_TD_IDX_SHIFT 0
1958/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1959#define PGMPOOL_TD_IDX_MASK 0x3fff
1960/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1961 * simply too many mappings of this page. */
1962#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1963
1964/** @def PGMPOOL_TD_MAKE
1965 * Makes a 16-bit tracking data word.
1966 *
1967 * @returns tracking data.
1968 * @param cRefs The @a cRefs field. Must be within bounds!
1969 * @param idx The @a idx field. Must also be within bounds! */
1970#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1971
1972/** @def PGMPOOL_TD_GET_CREFS
1973 * Get the @a cRefs field from a tracking data word.
1974 *
1975 * @returns The @a cRefs field
1976 * @param u16 The tracking data word. */
1977#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1978
1979/** @def PGMPOOL_TD_GET_IDX
1980 * Get the @a idx field from a tracking data word.
1981 *
1982 * @returns The @a idx field
1983 * @param u16 The tracking data word. */
1984#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1985/** @} */
1986
1987
1988/**
1989 * Trees are using self relative offsets as pointers.
1990 * So, all its data, including the root pointer, must be in the heap for HC and GC
1991 * to have the same layout.
1992 */
1993typedef struct PGMTREES
1994{
1995 /** Physical access handlers (AVL range+offsetptr tree). */
1996 AVLROGCPHYSTREE PhysHandlers;
1997 /** Virtual access handlers (AVL range + GC ptr tree). */
1998 AVLROGCPTRTREE VirtHandlers;
1999 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2000 AVLROGCPHYSTREE PhysToVirtHandlers;
2001 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2002 AVLROGCPTRTREE HyperVirtHandlers;
2003} PGMTREES;
2004/** Pointer to PGM trees. */
2005typedef PGMTREES *PPGMTREES;
2006
2007
2008/** @name Paging mode macros
2009 * @{ */
2010#ifdef IN_RC
2011# define PGM_CTX(a,b) a##RC##b
2012# define PGM_CTX_STR(a,b) a "GC" b
2013# define PGM_CTX_DECL(type) VMMRCDECL(type)
2014#else
2015# ifdef IN_RING3
2016# define PGM_CTX(a,b) a##R3##b
2017# define PGM_CTX_STR(a,b) a "R3" b
2018# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2019# else
2020# define PGM_CTX(a,b) a##R0##b
2021# define PGM_CTX_STR(a,b) a "R0" b
2022# define PGM_CTX_DECL(type) VMMDECL(type)
2023# endif
2024#endif
2025
2026#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2027#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2028#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2029#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2030#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2031#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2032#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2033#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2034#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2035#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2036#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2037#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2038#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2039#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2040#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2041#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2042#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2043
2044#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2045#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2046#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2047#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2048#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2049#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2050#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2051#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2052#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2053#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2054#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2055#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2056#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2057#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2058#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2059#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2060#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2061
2062/* Shw_Gst */
2063#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2064#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2065#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2066#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2067#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2068#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2069#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2070#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2071#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2072#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2073#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2074#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2075#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2076#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2077#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2078#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2079#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2080#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2081#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2082
2083#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2084#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2085#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2086#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2087#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2088#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2089#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2090#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2091#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2092#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2093#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2094#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2095#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2096#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2097#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2098#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2099#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2100#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2101#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2102#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2103#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2104#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2105#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2106#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2107#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2108#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2109#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2110#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2111#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2112#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2113#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2114#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2115#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2116#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2117#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2118#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2119#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2120
2121#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2122#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2123/** @} */
2124
2125/**
2126 * Data for each paging mode.
2127 */
2128typedef struct PGMMODEDATA
2129{
2130 /** The guest mode type. */
2131 uint32_t uGstType;
2132 /** The shadow mode type. */
2133 uint32_t uShwType;
2134
2135 /** @name Function pointers for Shadow paging.
2136 * @{
2137 */
2138 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2139 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2140 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2141 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2142
2143 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2144 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2145
2146 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2147 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2148 /** @} */
2149
2150 /** @name Function pointers for Guest paging.
2151 * @{
2152 */
2153 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2154 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2155 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2156 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2157 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2158#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2159 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2160 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2161#endif
2162#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2163 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2164 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2165 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2166 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2167#endif
2168 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2169 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2170 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2171#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2172 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2173 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2174#endif
2175#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2176 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2177 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2178#endif
2179 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2180 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2181 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2182#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2183 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2184 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2185#endif
2186#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2187 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2188 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2189#endif
2190 /** @} */
2191
2192 /** @name Function pointers for Both Shadow and Guest paging.
2193 * @{
2194 */
2195 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2196 /* no pfnR3BthTrap0eHandler */
2197 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2198 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2199 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2200 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2202#ifdef VBOX_STRICT
2203 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2204#endif
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2207
2208 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2209 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2210 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2211 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2212 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2213 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2214#ifdef VBOX_STRICT
2215 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2216#endif
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2219
2220 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2221 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2222 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2223 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2224 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2225 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2226#ifdef VBOX_STRICT
2227 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2228#endif
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2231 /** @} */
2232} PGMMODEDATA, *PPGMMODEDATA;
2233
2234
2235
2236/**
2237 * Converts a PGM pointer into a VM pointer.
2238 * @returns Pointer to the VM structure the PGM is part of.
2239 * @param pPGM Pointer to PGM instance data.
2240 */
2241#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2242
2243/**
2244 * PGM Data (part of VM)
2245 */
2246typedef struct PGM
2247{
2248 /** Offset to the VM structure. */
2249 RTINT offVM;
2250 /** Offset of the PGMCPU structure relative to VMCPU. */
2251 int32_t offVCpu;
2252 /** @cfgm{PGM/RamPreAlloc, bool, false}
2253 * Whether to preallocate all the guest RAM or not. */
2254 bool fRamPreAlloc;
2255 /** Alignment padding. */
2256 bool afAlignment0[3];
2257
2258
2259 /*
2260 * This will be redefined at least two more times before we're done, I'm sure.
2261 * The current code is only to get on with the coding.
2262 * - 2004-06-10: initial version, bird.
2263 * - 2004-07-02: 1st time, bird.
2264 * - 2004-10-18: 2nd time, bird.
2265 * - 2005-07-xx: 3rd time, bird.
2266 */
2267
2268 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2269 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2270 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2271 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2272
2273 /** The host paging mode. (This is what SUPLib reports.) */
2274 SUPPAGINGMODE enmHostMode;
2275 /** The shadow paging mode. */
2276 PGMMODE enmShadowMode;
2277 /** The guest paging mode. */
2278 PGMMODE enmGuestMode;
2279
2280 /** The current physical address representing in the guest CR3 register. */
2281 RTGCPHYS GCPhysCR3;
2282 /** Pointer to the 5 page CR3 content mapping.
2283 * The first page is always the CR3 (in some form) while the 4 other pages
2284 * are used of the PDs in PAE mode. */
2285 RTGCPTR GCPtrCR3Mapping;
2286#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2287 uint32_t u32Alignment;
2288#endif
2289#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2290 /** The physical address of the currently monitored guest CR3 page.
2291 * When this value is NIL_RTGCPHYS no page is being monitored. */
2292 RTGCPHYS GCPhysGstCR3Monitored;
2293#endif
2294 /** @name 32-bit Guest Paging.
2295 * @{ */
2296 /** The guest's page directory, R3 pointer. */
2297 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2298#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2299 /** The guest's page directory, R0 pointer. */
2300 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2301#endif
2302 /** The guest's page directory, static RC mapping. */
2303 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2304 /** @} */
2305
2306 /** @name PAE Guest Paging.
2307 * @{ */
2308 /** The guest's page directory pointer table, static RC mapping. */
2309 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2310 /** The guest's page directory pointer table, R3 pointer. */
2311 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2312#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2313 /** The guest's page directory pointer table, R0 pointer. */
2314 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2315#endif
2316
2317 /** The guest's page directories, R3 pointers.
2318 * These are individual pointers and don't have to be adjecent.
2319 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2320 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2321 /** The guest's page directories, R0 pointers.
2322 * Same restrictions as apGstPaePDsR3. */
2323#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2324 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2325#endif
2326 /** The guest's page directories, static GC mapping.
2327 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2328 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2329 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2330 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2331 RTGCPHYS aGCPhysGstPaePDs[4];
2332 /** The physical addresses of the monitored guest page directories (PAE). */
2333 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2334 /** @} */
2335
2336 /** @name AMD64 Guest Paging.
2337 * @{ */
2338 /** The guest's page directory pointer table, R3 pointer. */
2339 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2340#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2341 /** The guest's page directory pointer table, R0 pointer. */
2342 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2343#endif
2344 /** @} */
2345
2346# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2347 /** @name Shadow paging
2348 * @{ */
2349 /** The root page table - R3 Ptr. */
2350 R3PTRTYPE(void *) pShwRootR3;
2351# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2352 /** The root page table - R0 Ptr. */
2353 R0PTRTYPE(void *) pShwRootR0;
2354# endif
2355 /** The root page table - RC Ptr. */
2356 RCPTRTYPE(void *) pShwRootRC;
2357# if HC_ARCH_BITS == 64
2358 uint32_t u32Padding1; /**< alignment padding. */
2359# endif
2360 /** The Physical Address (HC) of the current active shadow CR3. */
2361 RTHCPHYS HCPhysShwCR3;
2362# endif
2363 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2364 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2365 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2366 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2367 /** Pointer to the page of the current active CR3 - RC Ptr. */
2368 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2369 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2370 uint32_t iShwUser;
2371 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2372 uint32_t iShwUserTable;
2373# if HC_ARCH_BITS == 64
2374 RTRCPTR alignment6; /**< structure size alignment. */
2375# endif
2376 /** @} */
2377#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2378 /** @name 32-bit Shadow Paging
2379 * @{ */
2380 /** The 32-Bit PD - R3 Ptr. */
2381 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2382 /** The 32-Bit PD - R0 Ptr. */
2383 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2384 /** The 32-Bit PD - RC Ptr. */
2385 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2386# if HC_ARCH_BITS == 64
2387 uint32_t u32Padding10; /**< alignment padding. */
2388# endif
2389 /** The Physical Address (HC) of the 32-Bit PD. */
2390 RTHCPHYS HCPhysShw32BitPD;
2391 /** @} */
2392
2393 /** @name PAE Shadow Paging
2394 * @{ */
2395 /** The four PDs for the low 4GB - R3 Ptr.
2396 * Even though these are 4 pointers, what they point at is a single table.
2397 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2398 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2399# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2400 /** The four PDs for the low 4GB - R0 Ptr.
2401 * Same kind of mapping as apHCPaePDs. */
2402 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2403# endif
2404 /** The four PDs for the low 4GB - RC Ptr.
2405 * Same kind of mapping as apHCPaePDs. */
2406 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2407 /** The Physical Address (HC) of the four PDs for the low 4GB.
2408 * These are *NOT* 4 contiguous pages. */
2409 RTHCPHYS aHCPhysPaePDs[4];
2410 /** The Physical Address (HC) of the PAE PDPT. */
2411 RTHCPHYS HCPhysShwPaePdpt;
2412 /** The PAE PDPT - R3 Ptr. */
2413 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2414 /** The PAE PDPT - R0 Ptr. */
2415 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2416 /** The PAE PDPT - RC Ptr. */
2417 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2418 /** @} */
2419# if HC_ARCH_BITS == 64
2420 RTRCPTR alignment5; /**< structure size alignment. */
2421# endif
2422#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2423 /** @name Nested Shadow Paging
2424 * @{ */
2425 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2426 RTR3PTR pShwNestedRootR3;
2427# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2428 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2429 RTR0PTR pShwNestedRootR0;
2430# endif
2431 /** The Physical Address (HC) of the nested paging root. */
2432 RTHCPHYS HCPhysShwNestedRoot;
2433 /** @} */
2434
2435 /** @name Function pointers for Shadow paging.
2436 * @{
2437 */
2438 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2439 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2440 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2441 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2442
2443 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2444 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2445
2446 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2447 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2448
2449 /** @} */
2450
2451 /** @name Function pointers for Guest paging.
2452 * @{
2453 */
2454 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2455 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2456 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2457 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2458 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2459#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2460 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2461 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2462#endif
2463#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2464 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2465 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2466 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2467 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2468#endif
2469 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2470 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2471 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2472#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2473 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2474 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2475#endif
2476#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2477 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2478 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2479#endif
2480#if HC_ARCH_BITS == 64
2481 RTRCPTR alignment3; /**< structure size alignment. */
2482#endif
2483
2484 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2485 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2486 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2487#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2488 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2489 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2490#endif
2491#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2492 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2493 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2494#endif
2495 /** @} */
2496
2497 /** @name Function pointers for Both Shadow and Guest paging.
2498 * @{
2499 */
2500 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2501 /* no pfnR3BthTrap0eHandler */
2502 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2503 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2504 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2505 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2506 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2507 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2508 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2509 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2510
2511 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2512 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2513 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2514 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2515 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2516 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2517 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2518 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2519 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2520
2521 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2522 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2523 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2524 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2525 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2526 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2527 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2528 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2529 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2530#if HC_ARCH_BITS == 64
2531 RTRCPTR alignment2; /**< structure size alignment. */
2532#endif
2533 /** @} */
2534
2535 /** Pointer to SHW+GST mode data (function pointers).
2536 * The index into this table is made up from */
2537 R3PTRTYPE(PPGMMODEDATA) paModeData;
2538
2539 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2540 * This is sorted by physical address and contains no overlapping ranges. */
2541 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2542 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2543 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2544 /** RC pointer corresponding to PGM::pRamRangesR3. */
2545 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2546 /** The configured RAM size. */
2547 RTUINT cbRamSize;
2548
2549 /** Pointer to the list of ROM ranges - for R3.
2550 * This is sorted by physical address and contains no overlapping ranges. */
2551 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2552 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2553 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2554 /** RC pointer corresponding to PGM::pRomRangesR3. */
2555 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2556 /** Alignment padding. */
2557 RTRCPTR GCPtrPadding2;
2558
2559 /** Pointer to the list of MMIO2 ranges - for R3.
2560 * Registration order. */
2561 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2562
2563 /** PGM offset based trees - R3 Ptr. */
2564 R3PTRTYPE(PPGMTREES) pTreesR3;
2565 /** PGM offset based trees - R0 Ptr. */
2566 R0PTRTYPE(PPGMTREES) pTreesR0;
2567 /** PGM offset based trees - RC Ptr. */
2568 RCPTRTYPE(PPGMTREES) pTreesRC;
2569
2570 /** Linked list of GC mappings - for RC.
2571 * The list is sorted ascending on address.
2572 */
2573 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2574 /** Linked list of GC mappings - for HC.
2575 * The list is sorted ascending on address.
2576 */
2577 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2578 /** Linked list of GC mappings - for R0.
2579 * The list is sorted ascending on address.
2580 */
2581 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2582
2583 /** Indicates that PGMR3FinalizeMappings has been called and that further
2584 * PGMR3MapIntermediate calls will be rejected. */
2585 bool fFinalizedMappings;
2586 /** If set no conflict checks are required. (boolean) */
2587 bool fMappingsFixed;
2588 /** If set, then no mappings are put into the shadow page table. (boolean) */
2589 bool fDisableMappings;
2590 /** Size of fixed mapping */
2591 uint32_t cbMappingFixed;
2592 /** Base address (GC) of fixed mapping */
2593 RTGCPTR GCPtrMappingFixed;
2594#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2595 uint32_t u32Padding0; /**< alignment padding. */
2596#endif
2597
2598
2599 /** @name Intermediate Context
2600 * @{ */
2601 /** Pointer to the intermediate page directory - Normal. */
2602 R3PTRTYPE(PX86PD) pInterPD;
2603 /** Pointer to the intermedate page tables - Normal.
2604 * There are two page tables, one for the identity mapping and one for
2605 * the host context mapping (of the core code). */
2606 R3PTRTYPE(PX86PT) apInterPTs[2];
2607 /** Pointer to the intermedate page tables - PAE. */
2608 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2609 /** Pointer to the intermedate page directory - PAE. */
2610 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2611 /** Pointer to the intermedate page directory - PAE. */
2612 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2613 /** Pointer to the intermedate page-map level 4 - AMD64. */
2614 R3PTRTYPE(PX86PML4) pInterPaePML4;
2615 /** Pointer to the intermedate page directory - AMD64. */
2616 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2617 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2618 RTHCPHYS HCPhysInterPD;
2619 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2620 RTHCPHYS HCPhysInterPaePDPT;
2621 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2622 RTHCPHYS HCPhysInterPaePML4;
2623 /** @} */
2624
2625 /** Base address of the dynamic page mapping area.
2626 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2627 */
2628 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2629 /** The index of the last entry used in the dynamic page mapping area. */
2630 RTUINT iDynPageMapLast;
2631 /** Cache containing the last entries in the dynamic page mapping area.
2632 * The cache size is covering half of the mapping area. */
2633 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2634 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2635
2636 /** The address of the ring-0 mapping cache if we're making use of it. */
2637 RTR0PTR pvR0DynMapUsed;
2638#if HC_ARCH_BITS == 32
2639 RTR0PTR R0PtrPadding0; /**< Alignment. */
2640#endif
2641
2642
2643 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2644 RTGCPHYS GCPhys4MBPSEMask;
2645
2646 /** A20 gate mask.
2647 * Our current approach to A20 emulation is to let REM do it and don't bother
2648 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2649 * But whould need arrise, we'll subject physical addresses to this mask. */
2650 RTGCPHYS GCPhysA20Mask;
2651 /** A20 gate state - boolean! */
2652 RTUINT fA20Enabled;
2653
2654 /** What needs syncing (PGM_SYNC_*).
2655 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2656 * PGMFlushTLB, and PGMR3Load. */
2657 RTUINT fSyncFlags;
2658
2659 /** PGM critical section.
2660 * This protects the physical & virtual access handlers, ram ranges,
2661 * and the page flag updating (some of it anyway).
2662 */
2663 PDMCRITSECT CritSect;
2664
2665 /** Shadow Page Pool - R3 Ptr. */
2666 R3PTRTYPE(PPGMPOOL) pPoolR3;
2667 /** Shadow Page Pool - R0 Ptr. */
2668 R0PTRTYPE(PPGMPOOL) pPoolR0;
2669 /** Shadow Page Pool - RC Ptr. */
2670 RCPTRTYPE(PPGMPOOL) pPoolRC;
2671
2672 /** We're not in a state which permits writes to guest memory.
2673 * (Only used in strict builds.) */
2674 bool fNoMorePhysWrites;
2675
2676 /** Flush the cache on the next access. */
2677 bool fPhysCacheFlushPending;
2678/** @todo r=bird: Fix member names!*/
2679 /** PGMPhysRead cache */
2680 PGMPHYSCACHE pgmphysreadcache;
2681 /** PGMPhysWrite cache */
2682 PGMPHYSCACHE pgmphyswritecache;
2683
2684 /**
2685 * Data associated with managing the ring-3 mappings of the allocation chunks.
2686 */
2687 struct
2688 {
2689 /** The chunk tree, ordered by chunk id. */
2690#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2691 R3PTRTYPE(PAVLU32NODECORE) pTree;
2692#else
2693 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2694#endif
2695 /** The chunk mapping TLB. */
2696 PGMCHUNKR3MAPTLB Tlb;
2697 /** The number of mapped chunks. */
2698 uint32_t c;
2699 /** The maximum number of mapped chunks.
2700 * @cfgm PGM/MaxRing3Chunks */
2701 uint32_t cMax;
2702 /** The chunk age tree, ordered by ageing sequence number. */
2703 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2704 /** The current time. */
2705 uint32_t iNow;
2706 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2707 uint32_t AgeingCountdown;
2708 } ChunkR3Map;
2709
2710 /**
2711 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2712 */
2713 PGMPAGER3MAPTLB PhysTlbHC;
2714
2715 /** @name The zero page.
2716 * @{ */
2717 /** The host physical address of the zero page. */
2718 RTHCPHYS HCPhysZeroPg;
2719 /** The ring-3 mapping of the zero page. */
2720 RTR3PTR pvZeroPgR3;
2721 /** The ring-0 mapping of the zero page. */
2722 RTR0PTR pvZeroPgR0;
2723 /** The GC mapping of the zero page. */
2724 RTGCPTR pvZeroPgGC;
2725#if GC_ARCH_BITS != 32
2726 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2727#endif
2728 /** @}*/
2729
2730 /** The number of handy pages. */
2731 uint32_t cHandyPages;
2732 /**
2733 * Array of handy pages.
2734 *
2735 * This array is used in a two way communication between pgmPhysAllocPage
2736 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2737 * an intermediary.
2738 *
2739 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2740 * (The current size of 32 pages, means 128 KB of handy memory.)
2741 */
2742 GMMPAGEDESC aHandyPages[32];
2743
2744 /** @name Release Statistics
2745 * @{ */
2746 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2747 uint32_t cPrivatePages; /**< The number of private pages. */
2748 uint32_t cSharedPages; /**< The number of shared pages. */
2749 uint32_t cZeroPages; /**< The number of zero backed pages. */
2750 /** The number of times the guest has switched mode since last reset or statistics reset. */
2751 STAMCOUNTER cGuestModeChanges;
2752 /** The number of times we were forced to change the hypervisor region location. */
2753 STAMCOUNTER cRelocations;
2754 /** @} */
2755
2756#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2757 /** RC: Which statistic this \#PF should be attributed to. */
2758 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2759 RTRCPTR padding0;
2760 /** R0: Which statistic this \#PF should be attributed to. */
2761 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2762 RTR0PTR padding1;
2763
2764 /* Common */
2765# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2766 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2767 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2768 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2769 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2770 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2771 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2772# endif
2773 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2774 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2775
2776 /* R3 only: */
2777 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2778 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2779 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2780 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2781 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2782 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2783
2784 /* R0 only: */
2785 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2786 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2787 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2788 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2789 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2790 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2791 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2792 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2793 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2794 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2795 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2796 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2797 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2798 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2799 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2800 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2801 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2802 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2803 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2804 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2805 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2806 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2807 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2808 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2809 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2810 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2811
2812 /* RC only: */
2813 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2814 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2815 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2816 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2817
2818 /* RZ only: */
2819 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2820 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2821 STAMPROFILE StatRZTrap0eTimeSyncPT;
2822 STAMPROFILE StatRZTrap0eTimeMapping;
2823 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2824 STAMPROFILE StatRZTrap0eTimeHandlers;
2825 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2826 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2827 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2828 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2829 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2830 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2831 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2832 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2833 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2834 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2835 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2836 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2837 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2838 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2839 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2840 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2841 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2842 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2843 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2844 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2845 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2846 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2847 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2848 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2849 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2850 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2851 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2852 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2853 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2854 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2856 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2857 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2858 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2859 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2860 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2861 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2862 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2863 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2864 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2865 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2866 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2867 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2868
2869 /* HC - R3 and (maybe) R0: */
2870
2871 /* RZ & R3: */
2872 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2873 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2874 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2875 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2876 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2877 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2878 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2879 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2880 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2881 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2882 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2883 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2884 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2885 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2886 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2887 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2888 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2889 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2890 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2891 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2892 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2893 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2894 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2895 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2896 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2897 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2898 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2899 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2900 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2901 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2902 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2903 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2904 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2905 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2906 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2907 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2908 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2909 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2910 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2911 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2912 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2913 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2914 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2915 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2916 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2917 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2918 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2919/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2920 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2921 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2922 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2923 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2924 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2925 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2926
2927 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2928 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2929 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2930 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2931 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2932 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2933 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2934 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2935 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2936 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2937 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2938 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2939 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2940 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2941 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2942 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2943 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2944 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2945 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2946 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2947 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2948 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2949 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2950 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2951 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2952 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2953 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2954 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2955 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2956 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2957 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2958 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2959 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2960 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2961 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2962 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2963 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2964 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2965 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2966 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2967 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2968 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2969 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2970 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2971 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2972 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2973 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2974/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2975 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2976 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2977 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2978 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2979 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2980 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2981#endif /* VBOX_WITH_STATISTICS */
2982} PGM;
2983/** Pointer to the PGM instance data. */
2984typedef PGM *PPGM;
2985
2986
2987/**
2988 * PGMCPU Data (part of VMCPU).
2989 */
2990typedef struct PGMCPU
2991{
2992 /** Offset to the VMCPU structure. */
2993 RTINT offVMCPU;
2994 /** Automatically tracked physical memory mapping set.
2995 * Ring-0 and strict raw-mode builds. */
2996 PGMMAPSET AutoSet;
2997} PGMCPU;
2998/** Pointer to the per-cpu PGM data. */
2999typedef PGMCPU *PPGMCPU;
3000
3001
3002/** @name PGM::fSyncFlags Flags
3003 * @{
3004 */
3005/** Updates the virtual access handler state bit in PGMPAGE. */
3006#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3007/** Always sync CR3. */
3008#define PGM_SYNC_ALWAYS RT_BIT(1)
3009/** Check monitoring on next CR3 (re)load and invalidate page. */
3010#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3011/** Check guest mapping in SyncCR3. */
3012#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3013/** Clear the page pool (a light weight flush). */
3014#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
3015/** @} */
3016
3017
3018__BEGIN_DECLS
3019
3020int pgmLock(PVM pVM);
3021void pgmUnlock(PVM pVM);
3022
3023VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3024VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3025
3026int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3027int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3028PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3029void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3030DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3031
3032void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3033bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3034int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3035DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3036#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3037void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3038#else
3039# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3040#endif
3041DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3042
3043
3044int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3045int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3046int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3047int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3048int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3049int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3050int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3051int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3052#ifdef IN_RING3
3053int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3054int pgmR3PhysRamReset(PVM pVM);
3055int pgmR3PhysRomReset(PVM pVM);
3056# ifndef VBOX_WITH_NEW_PHYS_CODE
3057int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3058# endif
3059
3060int pgmR3PoolInit(PVM pVM);
3061void pgmR3PoolRelocate(PVM pVM);
3062void pgmR3PoolReset(PVM pVM);
3063
3064#endif /* IN_RING3 */
3065#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3066int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3067#endif
3068#if !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && (defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0))
3069void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3070#endif
3071int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3072PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3073void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3074void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3075int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3076void pgmPoolFlushAll(PVM pVM);
3077void pgmPoolClearAll(PVM pVM);
3078int pgmPoolSyncCR3(PVM pVM);
3079void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3080void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3081int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3082PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3083void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3084void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3085uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3086void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3087#ifdef PGMPOOL_WITH_MONITORING
3088void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3089int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3090void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3091void pgmPoolMonitorModifiedClearAll(PVM pVM);
3092int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3093int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3094#endif
3095
3096#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3097void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3098void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3099int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3100#endif
3101int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3102int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3103
3104#ifndef IN_RC
3105int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3106#endif
3107int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3108
3109__END_DECLS
3110
3111
3112/**
3113 * Gets the PGMRAMRANGE structure for a guest page.
3114 *
3115 * @returns Pointer to the RAM range on success.
3116 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3117 *
3118 * @param pPGM PGM handle.
3119 * @param GCPhys The GC physical address.
3120 */
3121DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3122{
3123 /*
3124 * Optimize for the first range.
3125 */
3126 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3127 RTGCPHYS off = GCPhys - pRam->GCPhys;
3128 if (RT_UNLIKELY(off >= pRam->cb))
3129 {
3130 do
3131 {
3132 pRam = pRam->CTX_SUFF(pNext);
3133 if (RT_UNLIKELY(!pRam))
3134 break;
3135 off = GCPhys - pRam->GCPhys;
3136 } while (off >= pRam->cb);
3137 }
3138 return pRam;
3139}
3140
3141
3142/**
3143 * Gets the PGMPAGE structure for a guest page.
3144 *
3145 * @returns Pointer to the page on success.
3146 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3147 *
3148 * @param pPGM PGM handle.
3149 * @param GCPhys The GC physical address.
3150 */
3151DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3152{
3153 /*
3154 * Optimize for the first range.
3155 */
3156 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3157 RTGCPHYS off = GCPhys - pRam->GCPhys;
3158 if (RT_UNLIKELY(off >= pRam->cb))
3159 {
3160 do
3161 {
3162 pRam = pRam->CTX_SUFF(pNext);
3163 if (RT_UNLIKELY(!pRam))
3164 return NULL;
3165 off = GCPhys - pRam->GCPhys;
3166 } while (off >= pRam->cb);
3167 }
3168 return &pRam->aPages[off >> PAGE_SHIFT];
3169}
3170
3171
3172/**
3173 * Gets the PGMPAGE structure for a guest page.
3174 *
3175 * Old Phys code: Will make sure the page is present.
3176 *
3177 * @returns VBox status code.
3178 * @retval VINF_SUCCESS and a valid *ppPage on success.
3179 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3180 *
3181 * @param pPGM PGM handle.
3182 * @param GCPhys The GC physical address.
3183 * @param ppPage Where to store the page poitner on success.
3184 */
3185DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3186{
3187 /*
3188 * Optimize for the first range.
3189 */
3190 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3191 RTGCPHYS off = GCPhys - pRam->GCPhys;
3192 if (RT_UNLIKELY(off >= pRam->cb))
3193 {
3194 do
3195 {
3196 pRam = pRam->CTX_SUFF(pNext);
3197 if (RT_UNLIKELY(!pRam))
3198 {
3199 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3200 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3201 }
3202 off = GCPhys - pRam->GCPhys;
3203 } while (off >= pRam->cb);
3204 }
3205 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3206#ifndef VBOX_WITH_NEW_PHYS_CODE
3207
3208 /*
3209 * Make sure it's present.
3210 */
3211 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3212 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3213 {
3214#ifdef IN_RING3
3215 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3216#else
3217 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3218#endif
3219 if (RT_FAILURE(rc))
3220 {
3221 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3222 return rc;
3223 }
3224 Assert(rc == VINF_SUCCESS);
3225 }
3226#endif
3227 return VINF_SUCCESS;
3228}
3229
3230
3231
3232
3233/**
3234 * Gets the PGMPAGE structure for a guest page.
3235 *
3236 * Old Phys code: Will make sure the page is present.
3237 *
3238 * @returns VBox status code.
3239 * @retval VINF_SUCCESS and a valid *ppPage on success.
3240 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3241 *
3242 * @param pPGM PGM handle.
3243 * @param GCPhys The GC physical address.
3244 * @param ppPage Where to store the page poitner on success.
3245 * @param ppRamHint Where to read and store the ram list hint.
3246 * The caller initializes this to NULL before the call.
3247 */
3248DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3249{
3250 RTGCPHYS off;
3251 PPGMRAMRANGE pRam = *ppRamHint;
3252 if ( !pRam
3253 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3254 {
3255 pRam = pPGM->CTX_SUFF(pRamRanges);
3256 off = GCPhys - pRam->GCPhys;
3257 if (RT_UNLIKELY(off >= pRam->cb))
3258 {
3259 do
3260 {
3261 pRam = pRam->CTX_SUFF(pNext);
3262 if (RT_UNLIKELY(!pRam))
3263 {
3264 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3265 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3266 }
3267 off = GCPhys - pRam->GCPhys;
3268 } while (off >= pRam->cb);
3269 }
3270 *ppRamHint = pRam;
3271 }
3272 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3273#ifndef VBOX_WITH_NEW_PHYS_CODE
3274
3275 /*
3276 * Make sure it's present.
3277 */
3278 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3279 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3280 {
3281#ifdef IN_RING3
3282 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3283#else
3284 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3285#endif
3286 if (RT_FAILURE(rc))
3287 {
3288 *ppPage = NULL; /* Shut up annoying smart ass. */
3289 return rc;
3290 }
3291 Assert(rc == VINF_SUCCESS);
3292 }
3293#endif
3294 return VINF_SUCCESS;
3295}
3296
3297
3298/**
3299 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3300 *
3301 * @returns Pointer to the page on success.
3302 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3303 *
3304 * @param pPGM PGM handle.
3305 * @param GCPhys The GC physical address.
3306 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3307 */
3308DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3309{
3310 /*
3311 * Optimize for the first range.
3312 */
3313 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3314 RTGCPHYS off = GCPhys - pRam->GCPhys;
3315 if (RT_UNLIKELY(off >= pRam->cb))
3316 {
3317 do
3318 {
3319 pRam = pRam->CTX_SUFF(pNext);
3320 if (RT_UNLIKELY(!pRam))
3321 return NULL;
3322 off = GCPhys - pRam->GCPhys;
3323 } while (off >= pRam->cb);
3324 }
3325 *ppRam = pRam;
3326 return &pRam->aPages[off >> PAGE_SHIFT];
3327}
3328
3329
3330/**
3331 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3332 *
3333 * @returns Pointer to the page on success.
3334 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3335 *
3336 * @param pPGM PGM handle.
3337 * @param GCPhys The GC physical address.
3338 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3339 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3340 */
3341DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3342{
3343 /*
3344 * Optimize for the first range.
3345 */
3346 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3347 RTGCPHYS off = GCPhys - pRam->GCPhys;
3348 if (RT_UNLIKELY(off >= pRam->cb))
3349 {
3350 do
3351 {
3352 pRam = pRam->CTX_SUFF(pNext);
3353 if (RT_UNLIKELY(!pRam))
3354 {
3355 *ppRam = NULL; /* Shut up silly GCC warnings. */
3356 *ppPage = NULL; /* ditto */
3357 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3358 }
3359 off = GCPhys - pRam->GCPhys;
3360 } while (off >= pRam->cb);
3361 }
3362 *ppRam = pRam;
3363 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3364#ifndef VBOX_WITH_NEW_PHYS_CODE
3365
3366 /*
3367 * Make sure it's present.
3368 */
3369 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3370 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3371 {
3372#ifdef IN_RING3
3373 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3374#else
3375 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3376#endif
3377 if (RT_FAILURE(rc))
3378 {
3379 *ppPage = NULL; /* Shut up silly GCC warnings. */
3380 *ppPage = NULL; /* ditto */
3381 return rc;
3382 }
3383 Assert(rc == VINF_SUCCESS);
3384
3385 }
3386#endif
3387 return VINF_SUCCESS;
3388}
3389
3390
3391/**
3392 * Convert GC Phys to HC Phys.
3393 *
3394 * @returns VBox status.
3395 * @param pPGM PGM handle.
3396 * @param GCPhys The GC physical address.
3397 * @param pHCPhys Where to store the corresponding HC physical address.
3398 *
3399 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3400 * Avoid when writing new code!
3401 */
3402DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3403{
3404 PPGMPAGE pPage;
3405 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3406 if (RT_FAILURE(rc))
3407 return rc;
3408 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3409 return VINF_SUCCESS;
3410}
3411
3412#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3413
3414/**
3415 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3416 * optimizes access to pages already in the set.
3417 *
3418 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3419 * @param pPGM Pointer to the PVM instance data.
3420 * @param HCPhys The physical address of the page.
3421 * @param ppv Where to store the mapping address.
3422 */
3423DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3424{
3425 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3426 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3427 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3428 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3429
3430 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3431 unsigned iEntry = pSet->aiHashTable[iHash];
3432 if ( iEntry < pSet->cEntries
3433 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3434 {
3435 *ppv = pSet->aEntries[iEntry].pvPage;
3436 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3437 }
3438 else
3439 {
3440 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3441 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3442 }
3443
3444 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3445 return VINF_SUCCESS;
3446}
3447
3448
3449/**
3450 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3451 * access to pages already in the set.
3452 *
3453 * @returns See PGMDynMapGCPage.
3454 * @param pPGM Pointer to the PVM instance data.
3455 * @param HCPhys The physical address of the page.
3456 * @param ppv Where to store the mapping address.
3457 */
3458DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3459{
3460 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3461 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3462
3463 /*
3464 * Get the ram range.
3465 */
3466 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3467 RTGCPHYS off = GCPhys - pRam->GCPhys;
3468 if (RT_UNLIKELY(off >= pRam->cb
3469 /** @todo || page state stuff */))
3470 {
3471 /* This case is not counted into StatR0DynMapGCPageInl. */
3472 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3473 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3474 }
3475
3476 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3477 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3478
3479 /*
3480 * pgmR0DynMapHCPageInlined with out stats.
3481 */
3482 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3483 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3484 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3485
3486 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3487 unsigned iEntry = pSet->aiHashTable[iHash];
3488 if ( iEntry < pSet->cEntries
3489 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3490 {
3491 *ppv = pSet->aEntries[iEntry].pvPage;
3492 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3493 }
3494 else
3495 {
3496 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3497 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3498 }
3499
3500 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3501 return VINF_SUCCESS;
3502}
3503
3504#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3505#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3506
3507/**
3508 * Maps the page into current context (RC and maybe R0).
3509 *
3510 * @returns pointer to the mapping.
3511 * @param pVM Pointer to the PGM instance data.
3512 * @param pPage The page.
3513 */
3514DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3515{
3516 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3517 {
3518 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3519 void *pv;
3520# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3521 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3522# else
3523 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3524# endif
3525 return pv;
3526 }
3527#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3528 AssertFatalMsg(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3529#else
3530 return pgmPoolMapPageFallback(pPGM, pPage);
3531#endif
3532}
3533
3534/**
3535 * Temporarily maps one host page specified by HC physical address, returning
3536 * pointer within the page.
3537 *
3538 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3539 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3540 *
3541 * @returns The address corresponding to HCPhys.
3542 * @param pPGM Pointer to the PVM instance data.
3543 * @param HCPhys HC Physical address of the page.
3544 */
3545DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3546{
3547 void *pv;
3548# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3549 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3550# else
3551 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3552# endif
3553 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3554 return pv;
3555}
3556
3557#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3558
3559#ifndef IN_RC
3560/**
3561 * Queries the Physical TLB entry for a physical guest page,
3562 * attemting to load the TLB entry if necessary.
3563 *
3564 * @returns VBox status code.
3565 * @retval VINF_SUCCESS on success
3566 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3567 *
3568 * @param pPGM The PGM instance handle.
3569 * @param GCPhys The address of the guest page.
3570 * @param ppTlbe Where to store the pointer to the TLB entry.
3571 */
3572DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3573{
3574 int rc;
3575 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3576 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3577 {
3578 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3579 rc = VINF_SUCCESS;
3580 }
3581 else
3582 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3583 *ppTlbe = pTlbe;
3584 return rc;
3585}
3586
3587
3588/**
3589 * Queries the Physical TLB entry for a physical guest page,
3590 * attemting to load the TLB entry if necessary.
3591 *
3592 * @returns VBox status code.
3593 * @retval VINF_SUCCESS on success
3594 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3595 *
3596 * @param pPGM The PGM instance handle.
3597 * @param pPage Pointer to the PGMPAGE structure corresponding to
3598 * GCPhys.
3599 * @param GCPhys The address of the guest page.
3600 * @param ppTlbe Where to store the pointer to the TLB entry.
3601 */
3602DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3603{
3604 int rc;
3605 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3606 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3607 {
3608 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3609 rc = VINF_SUCCESS;
3610 }
3611 else
3612 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3613 *ppTlbe = pTlbe;
3614 return rc;
3615}
3616#endif /* !IN_RC */
3617
3618
3619#ifndef VBOX_WITH_NEW_PHYS_CODE
3620/**
3621 * Convert GC Phys to HC Virt and HC Phys.
3622 *
3623 * @returns VBox status.
3624 * @param pPGM PGM handle.
3625 * @param GCPhys The GC physical address.
3626 * @param pHCPtr Where to store the corresponding HC virtual address.
3627 * @param pHCPhys Where to store the HC Physical address and its flags.
3628 *
3629 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3630 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3631 * Either way, we have to make sure the page is writable in MapCR3.
3632 */
3633DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3634{
3635 PPGMRAMRANGE pRam;
3636 PPGMPAGE pPage;
3637 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3638 if (RT_FAILURE(rc))
3639 {
3640 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3641 *pHCPhys = 0; /* ditto */
3642 return rc;
3643 }
3644 RTGCPHYS off = GCPhys - pRam->GCPhys;
3645
3646 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3647 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3648 {
3649 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3650#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3651 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3652 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3653#else
3654 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3655#endif
3656 return VINF_SUCCESS;
3657 }
3658 if (pRam->pvR3)
3659 {
3660 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3661 return VINF_SUCCESS;
3662 }
3663 *pHCPtr = 0;
3664 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3665}
3666#endif /* VBOX_WITH_NEW_PHYS_CODE */
3667
3668
3669/**
3670 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3671 * Takes PSE-36 into account.
3672 *
3673 * @returns guest physical address
3674 * @param pPGM Pointer to the PGM instance data.
3675 * @param Pde Guest Pde
3676 */
3677DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3678{
3679 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3680 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3681
3682 return GCPhys & pPGM->GCPhys4MBPSEMask;
3683}
3684
3685
3686/**
3687 * Gets the page directory entry for the specified address (32-bit paging).
3688 *
3689 * @returns The page directory entry in question.
3690 * @param pPGM Pointer to the PGM instance data.
3691 * @param GCPtr The address.
3692 */
3693DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3694{
3695#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3696 PCX86PD pGuestPD = 0;
3697 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3698 if (RT_FAILURE(rc))
3699 {
3700 X86PDE ZeroPde = {0};
3701 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3702 }
3703 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3704#else
3705 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3706#endif
3707}
3708
3709
3710/**
3711 * Gets the address of a specific page directory entry (32-bit paging).
3712 *
3713 * @returns Pointer the page directory entry in question.
3714 * @param pPGM Pointer to the PGM instance data.
3715 * @param GCPtr The address.
3716 */
3717DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3718{
3719#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3720 PX86PD pGuestPD = 0;
3721 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3722 AssertRCReturn(rc, 0);
3723 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3724#else
3725 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3726#endif
3727}
3728
3729
3730/**
3731 * Gets the address the guest page directory (32-bit paging).
3732 *
3733 * @returns Pointer the page directory entry in question.
3734 * @param pPGM Pointer to the PGM instance data.
3735 */
3736DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3737{
3738#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3739 PX86PD pGuestPD = 0;
3740 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3741 AssertRCReturn(rc, 0);
3742 return pGuestPD;
3743#else
3744 return pPGM->CTX_SUFF(pGst32BitPd);
3745#endif
3746}
3747
3748
3749/**
3750 * Gets the guest page directory pointer table.
3751 *
3752 * @returns Pointer to the page directory in question.
3753 * @returns NULL if the page directory is not present or on an invalid page.
3754 * @param pPGM Pointer to the PGM instance data.
3755 */
3756DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3757{
3758#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3759 PX86PDPT pGuestPDPT = 0;
3760 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3761 AssertRCReturn(rc, 0);
3762 return pGuestPDPT;
3763#else
3764 return pPGM->CTX_SUFF(pGstPaePdpt);
3765#endif
3766}
3767
3768
3769/**
3770 * Gets the guest page directory pointer table entry for the specified address.
3771 *
3772 * @returns Pointer to the page directory in question.
3773 * @returns NULL if the page directory is not present or on an invalid page.
3774 * @param pPGM Pointer to the PGM instance data.
3775 * @param GCPtr The address.
3776 */
3777DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3778{
3779 AssertGCPtr32(GCPtr);
3780
3781#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3782 PX86PDPT pGuestPDPT = 0;
3783 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3784 AssertRCReturn(rc, 0);
3785 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3786#else
3787 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3788#endif
3789}
3790
3791
3792/**
3793 * Gets the page directory for the specified address.
3794 *
3795 * @returns Pointer to the page directory in question.
3796 * @returns NULL if the page directory is not present or on an invalid page.
3797 * @param pPGM Pointer to the PGM instance data.
3798 * @param GCPtr The address.
3799 */
3800DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3801{
3802 AssertGCPtr32(GCPtr);
3803
3804#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3805 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3806 AssertReturn(pGuestPDPT, 0);
3807#else
3808 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3809#endif
3810 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3811 if (pGuestPDPT->a[iPdPt].n.u1Present)
3812 {
3813#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3814 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3815 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3816#endif
3817
3818 /* cache is out-of-sync. */
3819 PX86PDPAE pPD;
3820 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3821 if (RT_SUCCESS(rc))
3822 return pPD;
3823 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3824 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3825 }
3826 return NULL;
3827}
3828
3829
3830/**
3831 * Gets the page directory entry for the specified address.
3832 *
3833 * @returns Pointer to the page directory entry in question.
3834 * @returns NULL if the page directory is not present or on an invalid page.
3835 * @param pPGM Pointer to the PGM instance data.
3836 * @param GCPtr The address.
3837 */
3838DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3839{
3840 AssertGCPtr32(GCPtr);
3841
3842#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3843 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3844 AssertReturn(pGuestPDPT, 0);
3845#else
3846 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3847#endif
3848 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3849 if (pGuestPDPT->a[iPdPt].n.u1Present)
3850 {
3851 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3852#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3853 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3854 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3855#endif
3856
3857 /* The cache is out-of-sync. */
3858 PX86PDPAE pPD;
3859 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3860 if (RT_SUCCESS(rc))
3861 return &pPD->a[iPD];
3862 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3863 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3864 }
3865 return NULL;
3866}
3867
3868
3869/**
3870 * Gets the page directory entry for the specified address.
3871 *
3872 * @returns The page directory entry in question.
3873 * @returns A non-present entry if the page directory is not present or on an invalid page.
3874 * @param pPGM Pointer to the PGM instance data.
3875 * @param GCPtr The address.
3876 */
3877DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3878{
3879 AssertGCPtr32(GCPtr);
3880
3881#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3882 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3883 if (RT_LIKELY(pGuestPDPT))
3884#else
3885 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3886#endif
3887 {
3888 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3889 if (pGuestPDPT->a[iPdPt].n.u1Present)
3890 {
3891 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3892#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3893 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3894 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3895#endif
3896
3897 /* cache is out-of-sync. */
3898 PX86PDPAE pPD;
3899 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3900 if (RT_SUCCESS(rc))
3901 return pPD->a[iPD];
3902 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3903 }
3904 }
3905 X86PDEPAE ZeroPde = {0};
3906 return ZeroPde;
3907}
3908
3909
3910/**
3911 * Gets the page directory pointer table entry for the specified address
3912 * and returns the index into the page directory
3913 *
3914 * @returns Pointer to the page directory in question.
3915 * @returns NULL if the page directory is not present or on an invalid page.
3916 * @param pPGM Pointer to the PGM instance data.
3917 * @param GCPtr The address.
3918 * @param piPD Receives the index into the returned page directory
3919 * @param pPdpe Receives the page directory pointer entry. Optional.
3920 */
3921DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3922{
3923 AssertGCPtr32(GCPtr);
3924
3925#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3926 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3927 AssertReturn(pGuestPDPT, 0);
3928#else
3929 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3930#endif
3931 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3932 if (pPdpe)
3933 *pPdpe = pGuestPDPT->a[iPdPt];
3934 if (pGuestPDPT->a[iPdPt].n.u1Present)
3935 {
3936 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3937#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3938 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3939 {
3940 *piPD = iPD;
3941 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3942 }
3943#endif
3944
3945 /* cache is out-of-sync. */
3946 PX86PDPAE pPD;
3947 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3948 if (RT_SUCCESS(rc))
3949 {
3950 *piPD = iPD;
3951 return pPD;
3952 }
3953 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3954 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3955 }
3956 return NULL;
3957}
3958
3959#ifndef IN_RC
3960
3961/**
3962 * Gets the page map level-4 pointer for the guest.
3963 *
3964 * @returns Pointer to the PML4 page.
3965 * @param pPGM Pointer to the PGM instance data.
3966 */
3967DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3968{
3969#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3970 PX86PML4 pGuestPml4;
3971 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3972 AssertRCReturn(rc, NULL);
3973 return pGuestPml4;
3974#else
3975 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3976 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3977#endif
3978}
3979
3980
3981/**
3982 * Gets the pointer to a page map level-4 entry.
3983 *
3984 * @returns Pointer to the PML4 entry.
3985 * @param pPGM Pointer to the PGM instance data.
3986 * @param iPml4 The index.
3987 */
3988DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3989{
3990#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3991 PX86PML4 pGuestPml4;
3992 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3993 AssertRCReturn(rc, NULL);
3994 return &pGuestPml4->a[iPml4];
3995#else
3996 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3997 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3998#endif
3999}
4000
4001
4002/**
4003 * Gets a page map level-4 entry.
4004 *
4005 * @returns The PML4 entry.
4006 * @param pPGM Pointer to the PGM instance data.
4007 * @param iPml4 The index.
4008 */
4009DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
4010{
4011#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4012 PX86PML4 pGuestPml4;
4013 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4014 if (RT_FAILURE(rc))
4015 {
4016 X86PML4E ZeroPml4e = {0};
4017 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4018 }
4019 return pGuestPml4->a[iPml4];
4020#else
4021 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4022 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4023#endif
4024}
4025
4026
4027/**
4028 * Gets the page directory pointer entry for the specified address.
4029 *
4030 * @returns Pointer to the page directory pointer entry in question.
4031 * @returns NULL if the page directory is not present or on an invalid page.
4032 * @param pPGM Pointer to the PGM instance data.
4033 * @param GCPtr The address.
4034 * @param ppPml4e Page Map Level-4 Entry (out)
4035 */
4036DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4037{
4038 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4039 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4040 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4041 if (pPml4e->n.u1Present)
4042 {
4043 PX86PDPT pPdpt;
4044 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4045 AssertRCReturn(rc, NULL);
4046
4047 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4048 return &pPdpt->a[iPdPt];
4049 }
4050 return NULL;
4051}
4052
4053
4054/**
4055 * Gets the page directory entry for the specified address.
4056 *
4057 * @returns The page directory entry in question.
4058 * @returns A non-present entry if the page directory is not present or on an invalid page.
4059 * @param pPGM Pointer to the PGM instance data.
4060 * @param GCPtr The address.
4061 * @param ppPml4e Page Map Level-4 Entry (out)
4062 * @param pPdpe Page directory pointer table entry (out)
4063 */
4064DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4065{
4066 X86PDEPAE ZeroPde = {0};
4067 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4068 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4069 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4070 if (pPml4e->n.u1Present)
4071 {
4072 PCX86PDPT pPdptTemp;
4073 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4074 AssertRCReturn(rc, ZeroPde);
4075
4076 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4077 *pPdpe = pPdptTemp->a[iPdPt];
4078 if (pPdptTemp->a[iPdPt].n.u1Present)
4079 {
4080 PCX86PDPAE pPD;
4081 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4082 AssertRCReturn(rc, ZeroPde);
4083
4084 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4085 return pPD->a[iPD];
4086 }
4087 }
4088
4089 return ZeroPde;
4090}
4091
4092
4093/**
4094 * Gets the page directory entry for the specified address.
4095 *
4096 * @returns The page directory entry in question.
4097 * @returns A non-present entry if the page directory is not present or on an invalid page.
4098 * @param pPGM Pointer to the PGM instance data.
4099 * @param GCPtr The address.
4100 */
4101DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4102{
4103 X86PDEPAE ZeroPde = {0};
4104 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4105 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4106 if (pGuestPml4->a[iPml4].n.u1Present)
4107 {
4108 PCX86PDPT pPdptTemp;
4109 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4110 AssertRCReturn(rc, ZeroPde);
4111
4112 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4113 if (pPdptTemp->a[iPdPt].n.u1Present)
4114 {
4115 PCX86PDPAE pPD;
4116 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4117 AssertRCReturn(rc, ZeroPde);
4118
4119 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4120 return pPD->a[iPD];
4121 }
4122 }
4123 return ZeroPde;
4124}
4125
4126
4127/**
4128 * Gets the page directory entry for the specified address.
4129 *
4130 * @returns Pointer to the page directory entry in question.
4131 * @returns NULL if the page directory is not present or on an invalid page.
4132 * @param pPGM Pointer to the PGM instance data.
4133 * @param GCPtr The address.
4134 */
4135DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4136{
4137 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4138 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4139 if (pGuestPml4->a[iPml4].n.u1Present)
4140 {
4141 PCX86PDPT pPdptTemp;
4142 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4143 AssertRCReturn(rc, NULL);
4144
4145 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4146 if (pPdptTemp->a[iPdPt].n.u1Present)
4147 {
4148 PX86PDPAE pPD;
4149 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4150 AssertRCReturn(rc, NULL);
4151
4152 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4153 return &pPD->a[iPD];
4154 }
4155 }
4156 return NULL;
4157}
4158
4159
4160/**
4161 * Gets the GUEST page directory pointer for the specified address.
4162 *
4163 * @returns The page directory in question.
4164 * @returns NULL if the page directory is not present or on an invalid page.
4165 * @param pPGM Pointer to the PGM instance data.
4166 * @param GCPtr The address.
4167 * @param ppPml4e Page Map Level-4 Entry (out)
4168 * @param pPdpe Page directory pointer table entry (out)
4169 * @param piPD Receives the index into the returned page directory
4170 */
4171DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4172{
4173 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4174 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4175 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4176 if (pPml4e->n.u1Present)
4177 {
4178 PCX86PDPT pPdptTemp;
4179 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4180 AssertRCReturn(rc, NULL);
4181
4182 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4183 *pPdpe = pPdptTemp->a[iPdPt];
4184 if (pPdptTemp->a[iPdPt].n.u1Present)
4185 {
4186 PX86PDPAE pPD;
4187 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4188 AssertRCReturn(rc, NULL);
4189
4190 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4191 return pPD;
4192 }
4193 }
4194 return 0;
4195}
4196
4197#endif /* !IN_RC */
4198
4199/**
4200 * Gets the shadow page directory, 32-bit.
4201 *
4202 * @returns Pointer to the shadow 32-bit PD.
4203 * @param pPGM Pointer to the PGM instance data.
4204 */
4205DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4206{
4207#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4208 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4209#else
4210# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4211 PX86PD pShwPd;
4212 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4213 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4214 AssertRCReturn(rc, NULL);
4215 return pShwPd;
4216# else
4217 return pPGM->CTX_SUFF(pShw32BitPd);
4218# endif
4219#endif
4220}
4221
4222
4223/**
4224 * Gets the shadow page directory entry for the specified address, 32-bit.
4225 *
4226 * @returns Shadow 32-bit PDE.
4227 * @param pPGM Pointer to the PGM instance data.
4228 * @param GCPtr The address.
4229 */
4230DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4231{
4232 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4233
4234 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4235 if (!pShwPde)
4236 {
4237 X86PDE ZeroPde = {0};
4238 return ZeroPde;
4239 }
4240 return pShwPde->a[iPd];
4241}
4242
4243
4244/**
4245 * Gets the pointer to the shadow page directory entry for the specified
4246 * address, 32-bit.
4247 *
4248 * @returns Pointer to the shadow 32-bit PDE.
4249 * @param pPGM Pointer to the PGM instance data.
4250 * @param GCPtr The address.
4251 */
4252DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4253{
4254 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4255
4256 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4257 AssertReturn(pPde, NULL);
4258 return &pPde->a[iPd];
4259}
4260
4261
4262/**
4263 * Gets the shadow page pointer table, PAE.
4264 *
4265 * @returns Pointer to the shadow PAE PDPT.
4266 * @param pPGM Pointer to the PGM instance data.
4267 */
4268DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4269{
4270#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4271 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4272#else
4273# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4274 PX86PDPT pShwPdpt;
4275 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4276 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4277 AssertRCReturn(rc, 0);
4278 return pShwPdpt;
4279# else
4280 return pPGM->CTX_SUFF(pShwPaePdpt);
4281# endif
4282#endif
4283}
4284
4285
4286/**
4287 * Gets the shadow page directory for the specified address, PAE.
4288 *
4289 * @returns Pointer to the shadow PD.
4290 * @param pPGM Pointer to the PGM instance data.
4291 * @param GCPtr The address.
4292 */
4293DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4294{
4295#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4296 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4297 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4298
4299 if (!pPdpt->a[iPdpt].n.u1Present)
4300 return NULL;
4301
4302 /* Fetch the pgm pool shadow descriptor. */
4303 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4304 AssertReturn(pShwPde, NULL);
4305
4306 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4307#else
4308 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4309# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4310 PX86PDPAE pPD;
4311 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4312 AssertRCReturn(rc, 0);
4313 return pPD;
4314# else
4315 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4316 Assert(pPD);
4317 return pPD;
4318# endif
4319#endif
4320}
4321
4322
4323/**
4324 * Gets the shadow page directory for the specified address, PAE.
4325 *
4326 * @returns Pointer to the shadow PD.
4327 * @param pPGM Pointer to the PGM instance data.
4328 * @param GCPtr The address.
4329 */
4330DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4331{
4332#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4333 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4334
4335 if (!pPdpt->a[iPdpt].n.u1Present)
4336 return NULL;
4337
4338 /* Fetch the pgm pool shadow descriptor. */
4339 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4340 AssertReturn(pShwPde, NULL);
4341
4342 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4343#else
4344 AssertFailed();
4345 return NULL;
4346#endif
4347}
4348
4349
4350/**
4351 * Gets the shadow page directory entry, PAE.
4352 *
4353 * @returns PDE.
4354 * @param pPGM Pointer to the PGM instance data.
4355 * @param GCPtr The address.
4356 */
4357DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4358{
4359 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4360
4361 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4362 if (!pShwPde)
4363 {
4364 X86PDEPAE ZeroPde = {0};
4365 return ZeroPde;
4366 }
4367 return pShwPde->a[iPd];
4368}
4369
4370
4371/**
4372 * Gets the pointer to the shadow page directory entry for an address, PAE.
4373 *
4374 * @returns Pointer to the PDE.
4375 * @param pPGM Pointer to the PGM instance data.
4376 * @param GCPtr The address.
4377 */
4378DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4379{
4380 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4381
4382 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4383 AssertReturn(pPde, NULL);
4384 return &pPde->a[iPd];
4385}
4386
4387#ifndef IN_RC
4388
4389/**
4390 * Gets the shadow page map level-4 pointer.
4391 *
4392 * @returns Pointer to the shadow PML4.
4393 * @param pPGM Pointer to the PGM instance data.
4394 */
4395DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4396{
4397#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4398 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4399#else
4400# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4401 PX86PML4 pShwPml4;
4402 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4403 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4404 AssertRCReturn(rc, 0);
4405 return pShwPml4;
4406# else
4407 Assert(pPGM->CTX_SUFF(pShwRoot));
4408 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4409# endif
4410#endif
4411}
4412
4413
4414/**
4415 * Gets the shadow page map level-4 entry for the specified address.
4416 *
4417 * @returns The entry.
4418 * @param pPGM Pointer to the PGM instance data.
4419 * @param GCPtr The address.
4420 */
4421DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4422{
4423 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4424 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4425
4426 if (!pShwPml4)
4427 {
4428 X86PML4E ZeroPml4e = {0};
4429 return ZeroPml4e;
4430 }
4431 return pShwPml4->a[iPml4];
4432}
4433
4434
4435/**
4436 * Gets the pointer to the specified shadow page map level-4 entry.
4437 *
4438 * @returns The entry.
4439 * @param pPGM Pointer to the PGM instance data.
4440 * @param iPml4 The PML4 index.
4441 */
4442DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4443{
4444 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4445 if (!pShwPml4)
4446 return NULL;
4447 return &pShwPml4->a[iPml4];
4448}
4449
4450
4451/**
4452 * Gets the GUEST page directory pointer for the specified address.
4453 *
4454 * @returns The page directory in question.
4455 * @returns NULL if the page directory is not present or on an invalid page.
4456 * @param pPGM Pointer to the PGM instance data.
4457 * @param GCPtr The address.
4458 * @param piPD Receives the index into the returned page directory
4459 */
4460DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4461{
4462 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4463 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4464 if (pGuestPml4->a[iPml4].n.u1Present)
4465 {
4466 PCX86PDPT pPdptTemp;
4467 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4468 AssertRCReturn(rc, NULL);
4469
4470 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4471 if (pPdptTemp->a[iPdPt].n.u1Present)
4472 {
4473 PX86PDPAE pPD;
4474 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4475 AssertRCReturn(rc, NULL);
4476
4477 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4478 return pPD;
4479 }
4480 }
4481 return NULL;
4482}
4483
4484#endif /* !IN_RC */
4485
4486/**
4487 * Gets the page state for a physical handler.
4488 *
4489 * @returns The physical handler page state.
4490 * @param pCur The physical handler in question.
4491 */
4492DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4493{
4494 switch (pCur->enmType)
4495 {
4496 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4497 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4498
4499 case PGMPHYSHANDLERTYPE_MMIO:
4500 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4501 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4502
4503 default:
4504 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4505 }
4506}
4507
4508
4509/**
4510 * Gets the page state for a virtual handler.
4511 *
4512 * @returns The virtual handler page state.
4513 * @param pCur The virtual handler in question.
4514 * @remarks This should never be used on a hypervisor access handler.
4515 */
4516DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4517{
4518 switch (pCur->enmType)
4519 {
4520 case PGMVIRTHANDLERTYPE_WRITE:
4521 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4522 case PGMVIRTHANDLERTYPE_ALL:
4523 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4524 default:
4525 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4526 }
4527}
4528
4529
4530/**
4531 * Clears one physical page of a virtual handler
4532 *
4533 * @param pPGM Pointer to the PGM instance.
4534 * @param pCur Virtual handler structure
4535 * @param iPage Physical page index
4536 *
4537 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4538 * need to care about other handlers in the same page.
4539 */
4540DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4541{
4542 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4543
4544 /*
4545 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4546 */
4547#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4548 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4549 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4550 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4551#endif
4552 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4553 {
4554 /* We're the head of the alias chain. */
4555 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4556#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4557 AssertReleaseMsg(pRemove != NULL,
4558 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4559 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4560 AssertReleaseMsg(pRemove == pPhys2Virt,
4561 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4562 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4563 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4564 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4565#endif
4566 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4567 {
4568 /* Insert the next list in the alias chain into the tree. */
4569 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4570#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4571 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4572 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4573 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4574#endif
4575 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4576 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4577 AssertRelease(fRc);
4578 }
4579 }
4580 else
4581 {
4582 /* Locate the previous node in the alias chain. */
4583 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4584#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4585 AssertReleaseMsg(pPrev != pPhys2Virt,
4586 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4587 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4588#endif
4589 for (;;)
4590 {
4591 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4592 if (pNext == pPhys2Virt)
4593 {
4594 /* unlink. */
4595 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4596 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4597 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4598 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4599 else
4600 {
4601 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4602 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4603 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4604 }
4605 break;
4606 }
4607
4608 /* next */
4609 if (pNext == pPrev)
4610 {
4611#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4612 AssertReleaseMsg(pNext != pPrev,
4613 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4614 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4615#endif
4616 break;
4617 }
4618 pPrev = pNext;
4619 }
4620 }
4621 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4622 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4623 pPhys2Virt->offNextAlias = 0;
4624 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4625
4626 /*
4627 * Clear the ram flags for this page.
4628 */
4629 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4630 AssertReturnVoid(pPage);
4631 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4632}
4633
4634
4635/**
4636 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4637 *
4638 * @returns Pointer to the shadow page structure.
4639 * @param pPool The pool.
4640 * @param HCPhys The HC physical address of the shadow page.
4641 */
4642DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4643{
4644 /*
4645 * Look up the page.
4646 */
4647 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4648 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4649 return pPage;
4650}
4651
4652
4653/**
4654 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4655 *
4656 * @returns Pointer to the shadow page structure.
4657 * @param pPool The pool.
4658 * @param idx The pool page index.
4659 */
4660DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4661{
4662 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4663 return &pPool->aPages[idx];
4664}
4665
4666
4667#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4668/**
4669 * Clear references to guest physical memory.
4670 *
4671 * @param pPool The pool.
4672 * @param pPoolPage The pool page.
4673 * @param pPhysPage The physical guest page tracking structure.
4674 */
4675DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4676{
4677 /*
4678 * Just deal with the simple case here.
4679 */
4680# ifdef LOG_ENABLED
4681 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4682# endif
4683 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4684 if (cRefs == 1)
4685 {
4686 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4687 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4688 }
4689 else
4690 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4691 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4692}
4693#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4694
4695
4696#ifdef PGMPOOL_WITH_CACHE
4697/**
4698 * Moves the page to the head of the age list.
4699 *
4700 * This is done when the cached page is used in one way or another.
4701 *
4702 * @param pPool The pool.
4703 * @param pPage The cached page.
4704 * @todo inline in PGMInternal.h!
4705 */
4706DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4707{
4708 /*
4709 * Move to the head of the age list.
4710 */
4711 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4712 {
4713 /* unlink */
4714 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4715 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4716 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4717 else
4718 pPool->iAgeTail = pPage->iAgePrev;
4719
4720 /* insert at head */
4721 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4722 pPage->iAgeNext = pPool->iAgeHead;
4723 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4724 pPool->iAgeHead = pPage->idx;
4725 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4726 }
4727}
4728#endif /* PGMPOOL_WITH_CACHE */
4729
4730#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4731
4732/**
4733 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4734 *
4735 * @param pVM VM Handle.
4736 * @param pPage PGM pool page
4737 */
4738DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4739{
4740 Assert(!pPage->fLocked);
4741 pPage->fLocked = true;
4742}
4743
4744
4745/**
4746 * Unlocks a page to allow flushing again
4747 *
4748 * @param pVM VM Handle.
4749 * @param pPage PGM pool page
4750 */
4751DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4752{
4753 Assert(pPage->fLocked);
4754 pPage->fLocked = false;
4755}
4756
4757
4758/**
4759 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4760 *
4761 * @returns VBox status code.
4762 * @param pPage PGM pool page
4763 */
4764DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4765{
4766 if (pPage->fLocked)
4767 {
4768 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4769 if (pPage->cModifications)
4770 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4771 return true;
4772 }
4773 return false;
4774}
4775
4776#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4777
4778/**
4779 * Tells if mappings are to be put into the shadow page table or not
4780 *
4781 * @returns boolean result
4782 * @param pVM VM handle.
4783 */
4784DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4785{
4786#ifdef IN_RING0
4787 /* There are no mappings in VT-x and AMD-V mode. */
4788 Assert(pPGM->fDisableMappings);
4789 return false;
4790#else
4791 return !pPGM->fDisableMappings;
4792#endif
4793}
4794
4795/** @} */
4796
4797#endif
4798
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