VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17522

Last change on this file since 17522 was 17513, checked in by vboxsync, 16 years ago

MM,PGM: Fixed page reservation, include a full set of handy pages for the time being. Fixed page counting statistics.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 196.3 KB
Line 
1/* $Id: PGMInternal.h 17513 2009-03-07 05:44:48Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149
150#ifdef VBOX_WITH_NEW_PHYS_CODE
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
154#endif
155/** @} */
156
157
158/** @name PDPT and PML4 flags.
159 * These are placed in the three bits available for system programs in
160 * the PDPT and PML4 entries.
161 * @{ */
162/** The entry is a permanent one and it's must always be present.
163 * Never free such an entry. */
164#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
165/** Mapping (hypervisor allocated pagetable). */
166#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
167/** @} */
168
169/** @name Page directory flags.
170 * These are placed in the three bits available for system programs in
171 * the page directory entries.
172 * @{ */
173/** Mapping (hypervisor allocated pagetable). */
174#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
177/** @} */
178
179/** @name Page flags.
180 * These are placed in the three bits available for system programs in
181 * the page entries.
182 * @{ */
183/** Made read-only to facilitate dirty bit tracking. */
184#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
185
186#ifndef PGM_PTFLAGS_CSAM_VALIDATED
187/** Scanned and approved by CSAM (tm).
188 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
189 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
190#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
191#endif
192
193/** @} */
194
195/** @name Defines used to indicate the shadow and guest paging in the templates.
196 * @{ */
197#define PGM_TYPE_REAL 1
198#define PGM_TYPE_PROT 2
199#define PGM_TYPE_32BIT 3
200#define PGM_TYPE_PAE 4
201#define PGM_TYPE_AMD64 5
202#define PGM_TYPE_NESTED 6
203#define PGM_TYPE_EPT 7
204#define PGM_TYPE_MAX PGM_TYPE_EPT
205/** @} */
206
207/** Macro for checking if the guest is using paging.
208 * @param uGstType PGM_TYPE_*
209 * @param uShwType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_PAGING(uGstType, uShwType) \
213 ( (uGstType) >= PGM_TYPE_32BIT \
214 && (uShwType) != PGM_TYPE_NESTED \
215 && (uShwType) != PGM_TYPE_EPT)
216
217/** Macro for checking if the guest supports the NX bit.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_NX(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_PAE \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227
228/** @def PGM_HCPHYS_2_PTR
229 * Maps a HC physical page pool address to a virtual address.
230 *
231 * @returns VBox status code.
232 * @param pVM The VM handle.
233 * @param HCPhys The HC physical address to map to a virtual one.
234 * @param ppv Where to store the virtual address. No need to cast this.
235 *
236 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
237 * small page window employeed by that function. Be careful.
238 * @remark There is no need to assert on the result.
239 */
240#ifdef IN_RC
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
243#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
246#else
247# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
248 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
249#endif
250
251/** @def PGM_HCPHYS_2_PTR_BY_PGM
252 * Maps a HC physical page pool address to a virtual address.
253 *
254 * @returns VBox status code.
255 * @param pPGM The PGM instance data.
256 * @param HCPhys The HC physical address to map to a virtual one.
257 * @param ppv Where to store the virtual address. No need to cast this.
258 *
259 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
260 * small page window employeed by that function. Be careful.
261 * @remark There is no need to assert on the result.
262 */
263#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
266#else
267# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
268 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
269#endif
270
271/** @def PGM_GCPHYS_2_PTR
272 * Maps a GC physical page address to a virtual address.
273 *
274 * @returns VBox status code.
275 * @param pVM The VM handle.
276 * @param GCPhys The GC physical address to map to a virtual one.
277 * @param ppv Where to store the virtual address. No need to cast this.
278 *
279 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
280 * small page window employeed by that function. Be careful.
281 * @remark There is no need to assert on the result.
282 */
283#ifdef IN_RC
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
286#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
289#else
290# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
291 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
292#endif
293
294/** @def PGM_GCPHYS_2_PTR_BY_PGM
295 * Maps a GC physical page address to a virtual address.
296 *
297 * @returns VBox status code.
298 * @param pPGM Pointer to the PGM instance data.
299 * @param GCPhys The GC physical address to map to a virtual one.
300 * @param ppv Where to store the virtual address. No need to cast this.
301 *
302 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
303 * small page window employeed by that function. Be careful.
304 * @remark There is no need to assert on the result.
305 */
306#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
307# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
309#else
310# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
311 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
312#endif
313
314/** @def PGM_GCPHYS_2_PTR_EX
315 * Maps a unaligned GC physical page address to a virtual address.
316 *
317 * @returns VBox status code.
318 * @param pVM The VM handle.
319 * @param GCPhys The GC physical address to map to a virtual one.
320 * @param ppv Where to store the virtual address. No need to cast this.
321 *
322 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
323 * small page window employeed by that function. Be careful.
324 * @remark There is no need to assert on the result.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
329#else
330# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
331 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
332#endif
333
334/** @def PGM_INVL_PG
335 * Invalidates a page when in GC does nothing in HC.
336 *
337 * @param GCVirt The virtual address of the page to invalidate.
338 */
339#ifdef IN_RC
340# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
341#elif defined(IN_RING0)
342# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
343#else
344# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
345#endif
346
347/** @def PGM_INVL_BIG_PG
348 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
349 *
350 * @param GCVirt The virtual address within the page directory to invalidate.
351 */
352#ifdef IN_RC
353# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
354#elif defined(IN_RING0)
355# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
356#else
357# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
358#endif
359
360/** @def PGM_INVL_GUEST_TLBS()
361 * Invalidates all guest TLBs.
362 */
363#ifdef IN_RC
364# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
365#elif defined(IN_RING0)
366# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
367#else
368# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
369#endif
370
371
372/**
373 * Structure for tracking GC Mappings.
374 *
375 * This structure is used by linked list in both GC and HC.
376 */
377typedef struct PGMMAPPING
378{
379 /** Pointer to next entry. */
380 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
381 /** Pointer to next entry. */
382 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
383 /** Pointer to next entry. */
384 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
385 /** Indicate whether this entry is finalized. */
386 bool fFinalized;
387 /** Start Virtual address. */
388 RTGCPTR GCPtr;
389 /** Last Virtual address (inclusive). */
390 RTGCPTR GCPtrLast;
391 /** Range size (bytes). */
392 RTGCPTR cb;
393 /** Pointer to relocation callback function. */
394 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
395 /** User argument to the callback. */
396 R3PTRTYPE(void *) pvUser;
397 /** Mapping description / name. For easing debugging. */
398 R3PTRTYPE(const char *) pszDesc;
399 /** Number of page tables. */
400 uint32_t cPTs;
401#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
402 uint32_t uPadding1; /**< Alignment padding. */
403#endif
404 /** Array of page table mapping data. Each entry
405 * describes one page table. The array can be longer
406 * than the declared length.
407 */
408 struct
409 {
410 /** The HC physical address of the page table. */
411 RTHCPHYS HCPhysPT;
412 /** The HC physical address of the first PAE page table. */
413 RTHCPHYS HCPhysPaePT0;
414 /** The HC physical address of the second PAE page table. */
415 RTHCPHYS HCPhysPaePT1;
416 /** The HC virtual address of the 32-bit page table. */
417 R3PTRTYPE(PX86PT) pPTR3;
418 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
419 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
420 /** The GC virtual address of the 32-bit page table. */
421 RCPTRTYPE(PX86PT) pPTRC;
422 /** The GC virtual address of the two PAE page table. */
423 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
424 /** The GC virtual address of the 32-bit page table. */
425 R0PTRTYPE(PX86PT) pPTR0;
426 /** The GC virtual address of the two PAE page table. */
427 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
428 } aPTs[1];
429} PGMMAPPING;
430/** Pointer to structure for tracking GC Mappings. */
431typedef struct PGMMAPPING *PPGMMAPPING;
432
433
434/**
435 * Physical page access handler structure.
436 *
437 * This is used to keep track of physical address ranges
438 * which are being monitored in some kind of way.
439 */
440typedef struct PGMPHYSHANDLER
441{
442 AVLROGCPHYSNODECORE Core;
443 /** Access type. */
444 PGMPHYSHANDLERTYPE enmType;
445 /** Number of pages to update. */
446 uint32_t cPages;
447 /** Pointer to R3 callback function. */
448 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
449 /** User argument for R3 handlers. */
450 R3PTRTYPE(void *) pvUserR3;
451 /** Pointer to R0 callback function. */
452 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
453 /** User argument for R0 handlers. */
454 R0PTRTYPE(void *) pvUserR0;
455 /** Pointer to GC callback function. */
456 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
457 /** User argument for RC handlers. */
458 RCPTRTYPE(void *) pvUserRC;
459 /** Description / Name. For easing debugging. */
460 R3PTRTYPE(const char *) pszDesc;
461#ifdef VBOX_WITH_STATISTICS
462 /** Profiling of this handler. */
463 STAMPROFILE Stat;
464#endif
465} PGMPHYSHANDLER;
466/** Pointer to a physical page access handler structure. */
467typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
468
469
470/**
471 * Cache node for the physical addresses covered by a virtual handler.
472 */
473typedef struct PGMPHYS2VIRTHANDLER
474{
475 /** Core node for the tree based on physical ranges. */
476 AVLROGCPHYSNODECORE Core;
477 /** Offset from this struct to the PGMVIRTHANDLER structure. */
478 int32_t offVirtHandler;
479 /** Offset of the next alias relative to this one.
480 * Bit 0 is used for indicating whether we're in the tree.
481 * Bit 1 is used for indicating that we're the head node.
482 */
483 int32_t offNextAlias;
484} PGMPHYS2VIRTHANDLER;
485/** Pointer to a phys to virtual handler structure. */
486typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
487
488/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489 * node is in the tree. */
490#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
491/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
492 * node is in the head of an alias chain.
493 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
494#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
495/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
496#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
497
498
499/**
500 * Virtual page access handler structure.
501 *
502 * This is used to keep track of virtual address ranges
503 * which are being monitored in some kind of way.
504 */
505typedef struct PGMVIRTHANDLER
506{
507 /** Core node for the tree based on virtual ranges. */
508 AVLROGCPTRNODECORE Core;
509 /** Size of the range (in bytes). */
510 RTGCPTR cb;
511 /** Number of cache pages. */
512 uint32_t cPages;
513 /** Access type. */
514 PGMVIRTHANDLERTYPE enmType;
515 /** Pointer to the RC callback function. */
516 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
517#if HC_ARCH_BITS == 64
518 RTRCPTR padding;
519#endif
520 /** Pointer to the R3 callback function for invalidation. */
521 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
522 /** Pointer to the R3 callback function. */
523 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
524 /** Description / Name. For easing debugging. */
525 R3PTRTYPE(const char *) pszDesc;
526#ifdef VBOX_WITH_STATISTICS
527 /** Profiling of this handler. */
528 STAMPROFILE Stat;
529#endif
530 /** Array of cached physical addresses for the monitored ranged. */
531 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
532} PGMVIRTHANDLER;
533/** Pointer to a virtual page access handler structure. */
534typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
535
536
537/**
538 * Page type.
539 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
540 * @todo convert to \#defines.
541 */
542typedef enum PGMPAGETYPE
543{
544 /** The usual invalid zero entry. */
545 PGMPAGETYPE_INVALID = 0,
546 /** RAM page. (RWX) */
547 PGMPAGETYPE_RAM,
548 /** MMIO2 page. (RWX) */
549 PGMPAGETYPE_MMIO2,
550 /** MMIO2 page aliased over an MMIO page. (RWX)
551 * See PGMHandlerPhysicalPageAlias(). */
552 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
553 /** Shadowed ROM. (RWX) */
554 PGMPAGETYPE_ROM_SHADOW,
555 /** ROM page. (R-X) */
556 PGMPAGETYPE_ROM,
557 /** MMIO page. (---) */
558 PGMPAGETYPE_MMIO,
559 /** End of valid entries. */
560 PGMPAGETYPE_END
561} PGMPAGETYPE;
562AssertCompile(PGMPAGETYPE_END <= 7);
563
564/** @name Page type predicates.
565 * @{ */
566#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
567#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
568#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
569#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
570#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
571/** @} */
572
573
574/**
575 * A Physical Guest Page tracking structure.
576 *
577 * The format of this structure is complicated because we have to fit a lot
578 * of information into as few bits as possible. The format is also subject
579 * to change (there is one comming up soon). Which means that for we'll be
580 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
581 * accessess to the structure.
582 */
583typedef struct PGMPAGE
584{
585 /** The physical address and a whole lot of other stuff. All bits are used! */
586#ifdef VBOX_WITH_NEW_PHYS_CODE
587 RTHCPHYS HCPhysX;
588#else
589 RTHCPHYS HCPhys;
590#define HCPhysX HCPhys /**< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. */
591#endif
592 /** The page state. */
593 uint32_t u2StateX : 2;
594 /** Flag indicating that a write monitored page was written to when set. */
595 uint32_t fWrittenToX : 1;
596 /** For later. */
597 uint32_t fSomethingElse : 1;
598 /** The Page ID.
599 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
600 * The HCPhysX will then be 100% static. */
601 uint32_t idPageX : 28;
602 /** The page type (PGMPAGETYPE). */
603 uint32_t u3Type : 3;
604 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
605 uint32_t u2HandlerPhysStateX : 2;
606 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
607 uint32_t u2HandlerVirtStateX : 2;
608 uint32_t u29B : 25;
609} PGMPAGE;
610AssertCompileSize(PGMPAGE, 16);
611/** Pointer to a physical guest page. */
612typedef PGMPAGE *PPGMPAGE;
613/** Pointer to a const physical guest page. */
614typedef const PGMPAGE *PCPGMPAGE;
615/** Pointer to a physical guest page pointer. */
616typedef PPGMPAGE *PPPGMPAGE;
617
618
619/**
620 * Clears the page structure.
621 * @param pPage Pointer to the physical guest page tracking structure.
622 */
623#define PGM_PAGE_CLEAR(pPage) \
624 do { \
625 (pPage)->HCPhysX = 0; \
626 (pPage)->u2StateX = 0; \
627 (pPage)->fWrittenToX = 0; \
628 (pPage)->fSomethingElse = 0; \
629 (pPage)->idPageX = 0; \
630 (pPage)->u3Type = 0; \
631 (pPage)->u29B = 0; \
632 } while (0)
633
634/**
635 * Initializes the page structure.
636 * @param pPage Pointer to the physical guest page tracking structure.
637 */
638#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
639 do { \
640 (pPage)->HCPhysX = (_HCPhys); \
641 (pPage)->u2StateX = (_uState); \
642 (pPage)->fWrittenToX = 0; \
643 (pPage)->fSomethingElse = 0; \
644 (pPage)->idPageX = (_idPage); \
645 /*(pPage)->u3Type = (_uType); - later */ \
646 PGM_PAGE_SET_TYPE(pPage, _uType); \
647 (pPage)->u29B = 0; \
648 } while (0)
649
650/**
651 * Initializes the page structure of a ZERO page.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#ifdef VBOX_WITH_NEW_PHYS_CODE
655# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
656 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
657#else
658# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
659 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
660#endif
661/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
662# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
663 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
664
665
666/** @name The Page state, PGMPAGE::u2StateX.
667 * @{ */
668/** The zero page.
669 * This is a per-VM page that's never ever mapped writable. */
670#define PGM_PAGE_STATE_ZERO 0
671/** A allocated page.
672 * This is a per-VM page allocated from the page pool (or wherever
673 * we get MMIO2 pages from if the type is MMIO2).
674 */
675#define PGM_PAGE_STATE_ALLOCATED 1
676/** A allocated page that's being monitored for writes.
677 * The shadow page table mappings are read-only. When a write occurs, the
678 * fWrittenTo member is set, the page remapped as read-write and the state
679 * moved back to allocated. */
680#define PGM_PAGE_STATE_WRITE_MONITORED 2
681/** The page is shared, aka. copy-on-write.
682 * This is a page that's shared with other VMs. */
683#define PGM_PAGE_STATE_SHARED 3
684/** @} */
685
686
687/**
688 * Gets the page state.
689 * @returns page state (PGM_PAGE_STATE_*).
690 * @param pPage Pointer to the physical guest page tracking structure.
691 */
692#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
693
694/**
695 * Sets the page state.
696 * @param pPage Pointer to the physical guest page tracking structure.
697 * @param _uState The new page state.
698 */
699#define PGM_PAGE_SET_STATE(pPage, _uState) \
700 do { (pPage)->u2StateX = (_uState); } while (0)
701
702
703/**
704 * Gets the host physical address of the guest page.
705 * @returns host physical address (RTHCPHYS).
706 * @param pPage Pointer to the physical guest page tracking structure.
707 */
708#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
709
710/**
711 * Sets the host physical address of the guest page.
712 * @param pPage Pointer to the physical guest page tracking structure.
713 * @param _HCPhys The new host physical address.
714 */
715#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
716 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
717 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
718
719/**
720 * Get the Page ID.
721 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 */
724#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
725/* later:
726#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
727 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
728*/
729/**
730 * Sets the Page ID.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 */
733#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
734/* later:
735#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
736 | ((_idPage) & 0xfff) \
737 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
738*/
739
740/**
741 * Get the Chunk ID.
742 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 */
745#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
746/* later:
747#if GMM_CHUNKID_SHIFT == 12
748# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
749#elif GMM_CHUNKID_SHIFT > 12
750# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
751#elif GMM_CHUNKID_SHIFT < 12
752# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
753 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
754#else
755# error "GMM_CHUNKID_SHIFT isn't defined or something."
756#endif
757*/
758
759/**
760 * Get the index of the page within the allocaiton chunk.
761 * @returns The page index.
762 * @param pPage Pointer to the physical guest page tracking structure.
763 */
764#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
765/* later:
766#if GMM_CHUNKID_SHIFT <= 12
767# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
768#else
769# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
770 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
771#endif
772*/
773
774
775/**
776 * Gets the page type.
777 * @returns The page type.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 */
780#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
781
782/**
783 * Sets the page type.
784 * @param pPage Pointer to the physical guest page tracking structure.
785 * @param _enmType The new page type (PGMPAGETYPE).
786 */
787#ifdef VBOX_WITH_NEW_PHYS_CODE
788#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
789 do { (pPage)->u3Type = (_enmType); } while (0)
790#else
791#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
792 do { \
793 (pPage)->u3Type = (_enmType); \
794 if ((_enmType) == PGMPAGETYPE_ROM) \
795 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM; \
796 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
797 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
798 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
799 (pPage)->HCPhysX |= MM_RAM_FLAGS_MMIO2; \
800 } while (0)
801#endif
802
803
804/**
805 * Checks if the page is 'reserved'.
806 * @returns true/false.
807 * @param pPage Pointer to the physical guest page tracking structure.
808 */
809#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
810
811/**
812 * Checks if the page is marked for MMIO.
813 * @returns true/false.
814 * @param pPage Pointer to the physical guest page tracking structure.
815 */
816#ifdef VBOX_WITH_NEW_PHYS_CODE
817# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
818#else
819# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
820#endif
821
822/**
823 * Checks if the page is backed by the ZERO page.
824 * @returns true/false.
825 * @param pPage Pointer to the physical guest page tracking structure.
826 */
827#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
828
829/**
830 * Checks if the page is backed by a SHARED page.
831 * @returns true/false.
832 * @param pPage Pointer to the physical guest page tracking structure.
833 */
834#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
835
836
837/**
838 * Marks the paget as written to (for GMM change monitoring).
839 * @param pPage Pointer to the physical guest page tracking structure.
840 */
841#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
842
843/**
844 * Clears the written-to indicator.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
848
849/**
850 * Checks if the page was marked as written-to.
851 * @returns true/false.
852 * @param pPage Pointer to the physical guest page tracking structure.
853 */
854#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
855
856
857/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
858 *
859 * @remarks The values are assigned in order of priority, so we can calculate
860 * the correct state for a page with different handlers installed.
861 * @{ */
862/** No handler installed. */
863#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
864/** Monitoring is temporarily disabled. */
865#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
866/** Write access is monitored. */
867#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
868/** All access is monitored. */
869#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
870/** @} */
871
872/**
873 * Gets the physical access handler state of a page.
874 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
878
879/**
880 * Sets the physical access handler state of a page.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param _uState The new state value.
883 */
884#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
885 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
886
887/**
888 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
889 * @returns true/false
890 * @param pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
893
894/**
895 * Checks if the page has any active physical access handlers.
896 * @returns true/false
897 * @param pPage Pointer to the physical guest page tracking structure.
898 */
899#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
900
901
902/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
903 *
904 * @remarks The values are assigned in order of priority, so we can calculate
905 * the correct state for a page with different handlers installed.
906 * @{ */
907/** No handler installed. */
908#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
909/* 1 is reserved so the lineup is identical with the physical ones. */
910/** Write access is monitored. */
911#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
912/** All access is monitored. */
913#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
914/** @} */
915
916/**
917 * Gets the virtual access handler state of a page.
918 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
922
923/**
924 * Sets the virtual access handler state of a page.
925 * @param pPage Pointer to the physical guest page tracking structure.
926 * @param _uState The new state value.
927 */
928#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
929 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
930
931/**
932 * Checks if the page has any virtual access handlers.
933 * @returns true/false
934 * @param pPage Pointer to the physical guest page tracking structure.
935 */
936#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
937
938/**
939 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
940 * virtual handlers.
941 * @returns true/false
942 * @param pPage Pointer to the physical guest page tracking structure.
943 */
944#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
945
946
947
948/**
949 * Checks if the page has any access handlers, including temporarily disabled ones.
950 * @returns true/false
951 * @param pPage Pointer to the physical guest page tracking structure.
952 */
953#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
954 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
955 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
956
957/**
958 * Checks if the page has any active access handlers.
959 * @returns true/false
960 * @param pPage Pointer to the physical guest page tracking structure.
961 */
962#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
963 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
964 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
965
966/**
967 * Checks if the page has any active access handlers catching all accesses.
968 * @returns true/false
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
972 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
973 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
974
975
976
977
978/** @def PGM_PAGE_GET_TRACKING
979 * Gets the packed shadow page pool tracking data associated with a guest page.
980 * @returns uint16_t containing the data.
981 * @param pPage Pointer to the physical guest page tracking structure.
982 */
983#define PGM_PAGE_GET_TRACKING(pPage) \
984 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
985
986/** @def PGM_PAGE_SET_TRACKING
987 * Sets the packed shadow page pool tracking data associated with a guest page.
988 * @param pPage Pointer to the physical guest page tracking structure.
989 * @param u16TrackingData The tracking data to store.
990 */
991#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
992 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
993
994/** @def PGM_PAGE_GET_TD_CREFS
995 * Gets the @a cRefs tracking data member.
996 * @returns cRefs.
997 * @param pPage Pointer to the physical guest page tracking structure.
998 */
999#define PGM_PAGE_GET_TD_CREFS(pPage) \
1000 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1001
1002#define PGM_PAGE_GET_TD_IDX(pPage) \
1003 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1004
1005/**
1006 * Ram range for GC Phys to HC Phys conversion.
1007 *
1008 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1009 * conversions too, but we'll let MM handle that for now.
1010 *
1011 * This structure is used by linked lists in both GC and HC.
1012 */
1013typedef struct PGMRAMRANGE
1014{
1015 /** Pointer to the next RAM range - for R3. */
1016 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1017 /** Pointer to the next RAM range - for R0. */
1018 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1019 /** Pointer to the next RAM range - for RC. */
1020 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1021 /** Pointer alignment. */
1022 RTRCPTR RCPtrAlignment;
1023 /** Start of the range. Page aligned. */
1024 RTGCPHYS GCPhys;
1025 /** Last address in the range (inclusive). Page aligned (-1). */
1026 RTGCPHYS GCPhysLast;
1027 /** Size of the range. (Page aligned of course). */
1028 RTGCPHYS cb;
1029 /** MM_RAM_* flags */
1030 uint32_t fFlags;
1031 uint32_t u32Alignment; /**< alignment. */
1032#ifndef VBOX_WITH_NEW_PHYS_CODE
1033 /** R3 virtual lookup ranges for chunks.
1034 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1035 * @remarks This is occationally accessed from ring-0!! (not darwin) */
1036# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1037 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1038# else
1039 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1040# endif
1041#endif
1042 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1043 R3PTRTYPE(void *) pvR3;
1044 /** The range description. */
1045 R3PTRTYPE(const char *) pszDesc;
1046
1047 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1048#ifdef VBOX_WITH_NEW_PHYS_CODE
1049 uint32_t au32Reserved[2];
1050#elif HC_ARCH_BITS == 32
1051 uint32_t au32Reserved[1];
1052#endif
1053
1054 /** Array of physical guest page tracking structures. */
1055 PGMPAGE aPages[1];
1056} PGMRAMRANGE;
1057/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1058typedef PGMRAMRANGE *PPGMRAMRANGE;
1059
1060#ifndef VBOX_WITH_NEW_PHYS_CODE
1061/** Return hc ptr corresponding to the ram range and physical offset */
1062#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1063 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1064 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1065#endif
1066
1067/**
1068 * Per page tracking structure for ROM image.
1069 *
1070 * A ROM image may have a shadow page, in which case we may have
1071 * two pages backing it. This structure contains the PGMPAGE for
1072 * both while PGMRAMRANGE have a copy of the active one. It is
1073 * important that these aren't out of sync in any regard other
1074 * than page pool tracking data.
1075 */
1076typedef struct PGMROMPAGE
1077{
1078 /** The page structure for the virgin ROM page. */
1079 PGMPAGE Virgin;
1080 /** The page structure for the shadow RAM page. */
1081 PGMPAGE Shadow;
1082 /** The current protection setting. */
1083 PGMROMPROT enmProt;
1084 /** Pad the structure size to a multiple of 8. */
1085 uint32_t u32Padding;
1086} PGMROMPAGE;
1087/** Pointer to a ROM page tracking structure. */
1088typedef PGMROMPAGE *PPGMROMPAGE;
1089
1090
1091/**
1092 * A registered ROM image.
1093 *
1094 * This is needed to keep track of ROM image since they generally
1095 * intrude into a PGMRAMRANGE. It also keeps track of additional
1096 * info like the two page sets (read-only virgin and read-write shadow),
1097 * the current state of each page.
1098 *
1099 * Because access handlers cannot easily be executed in a different
1100 * context, the ROM ranges needs to be accessible and in all contexts.
1101 */
1102typedef struct PGMROMRANGE
1103{
1104 /** Pointer to the next range - R3. */
1105 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1106 /** Pointer to the next range - R0. */
1107 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1108 /** Pointer to the next range - RC. */
1109 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1110 /** Pointer alignment */
1111 RTRCPTR GCPtrAlignment;
1112 /** Address of the range. */
1113 RTGCPHYS GCPhys;
1114 /** Address of the last byte in the range. */
1115 RTGCPHYS GCPhysLast;
1116 /** Size of the range. */
1117 RTGCPHYS cb;
1118 /** The flags (PGMPHYS_ROM_FLAG_*). */
1119 uint32_t fFlags;
1120 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1121 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1122 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1123 * This is used for strictness checks. */
1124 R3PTRTYPE(const void *) pvOriginal;
1125 /** The ROM description. */
1126 R3PTRTYPE(const char *) pszDesc;
1127 /** The per page tracking structures. */
1128 PGMROMPAGE aPages[1];
1129} PGMROMRANGE;
1130/** Pointer to a ROM range. */
1131typedef PGMROMRANGE *PPGMROMRANGE;
1132
1133
1134/**
1135 * A registered MMIO2 (= Device RAM) range.
1136 *
1137 * There are a few reason why we need to keep track of these
1138 * registrations. One of them is the deregistration & cleanup
1139 * stuff, while another is that the PGMRAMRANGE associated with
1140 * such a region may have to be removed from the ram range list.
1141 *
1142 * Overlapping with a RAM range has to be 100% or none at all. The
1143 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1144 * meditation will be raised if a partial overlap or an overlap of
1145 * ROM pages is encountered. On an overlap we will free all the
1146 * existing RAM pages and put in the ram range pages instead.
1147 */
1148typedef struct PGMMMIO2RANGE
1149{
1150 /** The owner of the range. (a device) */
1151 PPDMDEVINSR3 pDevInsR3;
1152 /** Pointer to the ring-3 mapping of the allocation. */
1153 RTR3PTR pvR3;
1154 /** Pointer to the next range - R3. */
1155 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1156 /** Whether it's mapped or not. */
1157 bool fMapped;
1158 /** Whether it's overlapping or not. */
1159 bool fOverlapping;
1160 /** The PCI region number.
1161 * @remarks This ASSUMES that nobody will ever really need to have multiple
1162 * PCI devices with matching MMIO region numbers on a single device. */
1163 uint8_t iRegion;
1164 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1165 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1166 /** The associated RAM range. */
1167 PGMRAMRANGE RamRange;
1168} PGMMMIO2RANGE;
1169/** Pointer to a MMIO2 range. */
1170typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1171
1172
1173
1174
1175/**
1176 * PGMPhysRead/Write cache entry
1177 */
1178typedef struct PGMPHYSCACHEENTRY
1179{
1180 /** R3 pointer to physical page. */
1181 R3PTRTYPE(uint8_t *) pbR3;
1182 /** GC Physical address for cache entry */
1183 RTGCPHYS GCPhys;
1184#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1185 RTGCPHYS u32Padding0; /**< alignment padding. */
1186#endif
1187} PGMPHYSCACHEENTRY;
1188
1189/**
1190 * PGMPhysRead/Write cache to reduce REM memory access overhead
1191 */
1192typedef struct PGMPHYSCACHE
1193{
1194 /** Bitmap of valid cache entries */
1195 uint64_t aEntries;
1196 /** Cache entries */
1197 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1198} PGMPHYSCACHE;
1199
1200
1201/** Pointer to an allocation chunk ring-3 mapping. */
1202typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1203/** Pointer to an allocation chunk ring-3 mapping pointer. */
1204typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1205
1206/**
1207 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1208 *
1209 * The primary tree (Core) uses the chunk id as key.
1210 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1211 */
1212typedef struct PGMCHUNKR3MAP
1213{
1214 /** The key is the chunk id. */
1215 AVLU32NODECORE Core;
1216 /** The key is the ageing sequence number. */
1217 AVLLU32NODECORE AgeCore;
1218 /** The current age thingy. */
1219 uint32_t iAge;
1220 /** The current reference count. */
1221 uint32_t volatile cRefs;
1222 /** The current permanent reference count. */
1223 uint32_t volatile cPermRefs;
1224 /** The mapping address. */
1225 void *pv;
1226} PGMCHUNKR3MAP;
1227
1228/**
1229 * Allocation chunk ring-3 mapping TLB entry.
1230 */
1231typedef struct PGMCHUNKR3MAPTLBE
1232{
1233 /** The chunk id. */
1234 uint32_t volatile idChunk;
1235#if HC_ARCH_BITS == 64
1236 uint32_t u32Padding; /**< alignment padding. */
1237#endif
1238 /** The chunk map. */
1239#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1240 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1241#else
1242 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1243#endif
1244} PGMCHUNKR3MAPTLBE;
1245/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1246typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1247
1248/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1249 * @remark Must be a power of two value. */
1250#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1251
1252/**
1253 * Allocation chunk ring-3 mapping TLB.
1254 *
1255 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1256 * At first glance this might look kinda odd since AVL trees are
1257 * supposed to give the most optimial lookup times of all trees
1258 * due to their balancing. However, take a tree with 1023 nodes
1259 * in it, that's 10 levels, meaning that most searches has to go
1260 * down 9 levels before they find what they want. This isn't fast
1261 * compared to a TLB hit. There is the factor of cache misses,
1262 * and of course the problem with trees and branch prediction.
1263 * This is why we use TLBs in front of most of the trees.
1264 *
1265 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1266 * difficult when we switch to the new inlined AVL trees (from kStuff).
1267 */
1268typedef struct PGMCHUNKR3MAPTLB
1269{
1270 /** The TLB entries. */
1271 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1272} PGMCHUNKR3MAPTLB;
1273
1274/**
1275 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1276 * @returns Chunk TLB index.
1277 * @param idChunk The Chunk ID.
1278 */
1279#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1280
1281
1282/**
1283 * Ring-3 guest page mapping TLB entry.
1284 * @remarks used in ring-0 as well at the moment.
1285 */
1286typedef struct PGMPAGER3MAPTLBE
1287{
1288 /** Address of the page. */
1289 RTGCPHYS volatile GCPhys;
1290 /** The guest page. */
1291#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1292 R3PTRTYPE(PPGMPAGE) volatile pPage;
1293#else
1294 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1295#endif
1296 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1297#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1298 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1299#else
1300 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1301#endif
1302 /** The address */
1303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1304 R3PTRTYPE(void *) volatile pv;
1305#else
1306 R3R0PTRTYPE(void *) volatile pv;
1307#endif
1308#if HC_ARCH_BITS == 32
1309 uint32_t u32Padding; /**< alignment padding. */
1310#endif
1311} PGMPAGER3MAPTLBE;
1312/** Pointer to an entry in the HC physical TLB. */
1313typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1314
1315
1316/** The number of entries in the ring-3 guest page mapping TLB.
1317 * @remarks The value must be a power of two. */
1318#define PGM_PAGER3MAPTLB_ENTRIES 64
1319
1320/**
1321 * Ring-3 guest page mapping TLB.
1322 * @remarks used in ring-0 as well at the moment.
1323 */
1324typedef struct PGMPAGER3MAPTLB
1325{
1326 /** The TLB entries. */
1327 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1328} PGMPAGER3MAPTLB;
1329/** Pointer to the ring-3 guest page mapping TLB. */
1330typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1331
1332/**
1333 * Calculates the index of the TLB entry for the specified guest page.
1334 * @returns Physical TLB index.
1335 * @param GCPhys The guest physical address.
1336 */
1337#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1338
1339
1340/**
1341 * Mapping cache usage set entry.
1342 *
1343 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1344 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1345 * cache. If it's extended to include ring-3, well, then something will
1346 * have be changed here...
1347 */
1348typedef struct PGMMAPSETENTRY
1349{
1350 /** The mapping cache index. */
1351 uint16_t iPage;
1352 /** The number of references.
1353 * The max is UINT16_MAX - 1. */
1354 uint16_t cRefs;
1355 /** Pointer to the page. */
1356 RTR0PTR pvPage;
1357 /** The physical address for this entry. */
1358 RTHCPHYS HCPhys;
1359} PGMMAPSETENTRY;
1360/** Pointer to a mapping cache usage set entry. */
1361typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1362
1363/**
1364 * Mapping cache usage set.
1365 *
1366 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1367 * done during exits / traps. The set is
1368 */
1369typedef struct PGMMAPSET
1370{
1371 /** The number of occupied entries.
1372 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1373 * dynamic mappings. */
1374 uint32_t cEntries;
1375 /** The start of the current subset.
1376 * This is UINT32_MAX if no subset is currently open. */
1377 uint32_t iSubset;
1378 /** The index of the current CPU, only valid if the set is open. */
1379 int32_t iCpu;
1380 /** The entries. */
1381 PGMMAPSETENTRY aEntries[64];
1382 /** HCPhys -> iEntry fast lookup table.
1383 * Use PGMMAPSET_HASH for hashing.
1384 * The entries may or may not be valid, check against cEntries. */
1385 uint8_t aiHashTable[128];
1386} PGMMAPSET;
1387/** Pointer to the mapping cache set. */
1388typedef PGMMAPSET *PPGMMAPSET;
1389
1390/** PGMMAPSET::cEntries value for a closed set. */
1391#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1392
1393/** Hash function for aiHashTable. */
1394#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1395
1396/** The max fill size (strict builds). */
1397#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1398
1399
1400/** @name Context neutrual page mapper TLB.
1401 *
1402 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1403 * code is writting in a kind of context neutrual way. Time will show whether
1404 * this actually makes sense or not...
1405 *
1406 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1407 * context ends up using a global mapping cache on some platforms
1408 * (darwin).
1409 *
1410 * @{ */
1411/** @typedef PPGMPAGEMAPTLB
1412 * The page mapper TLB pointer type for the current context. */
1413/** @typedef PPGMPAGEMAPTLB
1414 * The page mapper TLB entry pointer type for the current context. */
1415/** @typedef PPGMPAGEMAPTLB
1416 * The page mapper TLB entry pointer pointer type for the current context. */
1417/** @def PGM_PAGEMAPTLB_ENTRIES
1418 * The number of TLB entries in the page mapper TLB for the current context. */
1419/** @def PGM_PAGEMAPTLB_IDX
1420 * Calculate the TLB index for a guest physical address.
1421 * @returns The TLB index.
1422 * @param GCPhys The guest physical address. */
1423/** @typedef PPGMPAGEMAP
1424 * Pointer to a page mapper unit for current context. */
1425/** @typedef PPPGMPAGEMAP
1426 * Pointer to a page mapper unit pointer for current context. */
1427#ifdef IN_RC
1428// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1429// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1430// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1431# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1432# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1433 typedef void * PPGMPAGEMAP;
1434 typedef void ** PPPGMPAGEMAP;
1435//#elif IN_RING0
1436// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1437// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1438// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1439//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1440//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1441// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1442// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1443#else
1444 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1445 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1446 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1447# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1448# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1449 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1450 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1451#endif
1452/** @} */
1453
1454
1455/** @name PGM Pool Indexes.
1456 * Aka. the unique shadow page identifier.
1457 * @{ */
1458/** NIL page pool IDX. */
1459#define NIL_PGMPOOL_IDX 0
1460/** The first normal index. */
1461#define PGMPOOL_IDX_FIRST_SPECIAL 1
1462#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1463/** Page directory (32-bit root). */
1464#define PGMPOOL_IDX_PD 1
1465/** Page Directory Pointer Table (PAE root). */
1466#define PGMPOOL_IDX_PDPT 2
1467/** AMD64 CR3 level index.*/
1468#define PGMPOOL_IDX_AMD64_CR3 3
1469/** Nested paging root.*/
1470#define PGMPOOL_IDX_NESTED_ROOT 4
1471/** The first normal index. */
1472#define PGMPOOL_IDX_FIRST 5
1473#else
1474/** Page directory (32-bit root). */
1475#define PGMPOOL_IDX_PD 1
1476/** The extended PAE page directory (2048 entries, works as root currently). */
1477#define PGMPOOL_IDX_PAE_PD 2
1478/** PAE Page Directory Table 0. */
1479#define PGMPOOL_IDX_PAE_PD_0 3
1480/** PAE Page Directory Table 1. */
1481#define PGMPOOL_IDX_PAE_PD_1 4
1482/** PAE Page Directory Table 2. */
1483#define PGMPOOL_IDX_PAE_PD_2 5
1484/** PAE Page Directory Table 3. */
1485#define PGMPOOL_IDX_PAE_PD_3 6
1486/** Page Directory Pointer Table (PAE root, not currently used). */
1487#define PGMPOOL_IDX_PDPT 7
1488/** AMD64 CR3 level index.*/
1489#define PGMPOOL_IDX_AMD64_CR3 8
1490/** Nested paging root.*/
1491#define PGMPOOL_IDX_NESTED_ROOT 9
1492/** The first normal index. */
1493#define PGMPOOL_IDX_FIRST 10
1494#endif
1495/** The last valid index. (inclusive, 14 bits) */
1496#define PGMPOOL_IDX_LAST 0x3fff
1497/** @} */
1498
1499/** The NIL index for the parent chain. */
1500#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1501
1502/**
1503 * Node in the chain linking a shadowed page to it's parent (user).
1504 */
1505#pragma pack(1)
1506typedef struct PGMPOOLUSER
1507{
1508 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1509 uint16_t iNext;
1510 /** The user page index. */
1511 uint16_t iUser;
1512 /** Index into the user table. */
1513 uint32_t iUserTable;
1514} PGMPOOLUSER, *PPGMPOOLUSER;
1515typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1516#pragma pack()
1517
1518
1519/** The NIL index for the phys ext chain. */
1520#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1521
1522/**
1523 * Node in the chain of physical cross reference extents.
1524 * @todo Calling this an 'extent' is not quite right, find a better name.
1525 */
1526#pragma pack(1)
1527typedef struct PGMPOOLPHYSEXT
1528{
1529 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1530 uint16_t iNext;
1531 /** The user page index. */
1532 uint16_t aidx[3];
1533} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1534typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1535#pragma pack()
1536
1537
1538/**
1539 * The kind of page that's being shadowed.
1540 */
1541typedef enum PGMPOOLKIND
1542{
1543 /** The virtual invalid 0 entry. */
1544 PGMPOOLKIND_INVALID = 0,
1545 /** The entry is free (=unused). */
1546 PGMPOOLKIND_FREE,
1547
1548 /** Shw: 32-bit page table; Gst: no paging */
1549 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1550 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1551 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1552 /** Shw: 32-bit page table; Gst: 4MB page. */
1553 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1554 /** Shw: PAE page table; Gst: no paging */
1555 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1556 /** Shw: PAE page table; Gst: 32-bit page table. */
1557 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1558 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1559 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1560 /** Shw: PAE page table; Gst: PAE page table. */
1561 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1562 /** Shw: PAE page table; Gst: 2MB page. */
1563 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1564
1565 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1566 PGMPOOLKIND_32BIT_PD,
1567 /** Shw: 32-bit page directory. Gst: no paging. */
1568 PGMPOOLKIND_32BIT_PD_PHYS,
1569 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1570 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1571 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1572 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1573 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1574 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1575 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1576 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1577 /** Shw: PAE page directory; Gst: PAE page directory. */
1578 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1579 /** Shw: PAE page directory; Gst: no paging. */
1580 PGMPOOLKIND_PAE_PD_PHYS,
1581
1582 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1583 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1584 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1585 PGMPOOLKIND_PAE_PDPT,
1586 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1587 PGMPOOLKIND_PAE_PDPT_PHYS,
1588
1589 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1590 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1591 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1592 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1593 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1594 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1595 /** Shw: 64-bit page directory table; Gst: no paging */
1596 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1597
1598 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1599 PGMPOOLKIND_64BIT_PML4,
1600
1601 /** Shw: EPT page directory pointer table; Gst: no paging */
1602 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1603 /** Shw: EPT page directory table; Gst: no paging */
1604 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1605 /** Shw: EPT page table; Gst: no paging */
1606 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1607
1608#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1609 /** Shw: Root 32-bit page directory. */
1610 PGMPOOLKIND_ROOT_32BIT_PD,
1611 /** Shw: Root PAE page directory */
1612 PGMPOOLKIND_ROOT_PAE_PD,
1613 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1614 PGMPOOLKIND_ROOT_PDPT,
1615#endif
1616 /** Shw: Root Nested paging table. */
1617 PGMPOOLKIND_ROOT_NESTED,
1618
1619 /** The last valid entry. */
1620 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1621} PGMPOOLKIND;
1622
1623
1624/**
1625 * The tracking data for a page in the pool.
1626 */
1627typedef struct PGMPOOLPAGE
1628{
1629 /** AVL node code with the (R3) physical address of this page. */
1630 AVLOHCPHYSNODECORE Core;
1631 /** Pointer to the R3 mapping of the page. */
1632#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1633 R3PTRTYPE(void *) pvPageR3;
1634#else
1635 R3R0PTRTYPE(void *) pvPageR3;
1636#endif
1637 /** The guest physical address. */
1638#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1639 uint32_t Alignment0;
1640#endif
1641 RTGCPHYS GCPhys;
1642 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1643 uint8_t enmKind;
1644 uint8_t bPadding;
1645 /** The index of this page. */
1646 uint16_t idx;
1647 /** The next entry in the list this page currently resides in.
1648 * It's either in the free list or in the GCPhys hash. */
1649 uint16_t iNext;
1650#ifdef PGMPOOL_WITH_USER_TRACKING
1651 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1652 uint16_t iUserHead;
1653 /** The number of present entries. */
1654 uint16_t cPresent;
1655 /** The first entry in the table which is present. */
1656 uint16_t iFirstPresent;
1657#endif
1658#ifdef PGMPOOL_WITH_MONITORING
1659 /** The number of modifications to the monitored page. */
1660 uint16_t cModifications;
1661 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1662 uint16_t iModifiedNext;
1663 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1664 uint16_t iModifiedPrev;
1665 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1666 uint16_t iMonitoredNext;
1667 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1668 uint16_t iMonitoredPrev;
1669#endif
1670#ifdef PGMPOOL_WITH_CACHE
1671 /** The next page in the age list. */
1672 uint16_t iAgeNext;
1673 /** The previous page in the age list. */
1674 uint16_t iAgePrev;
1675#endif /* PGMPOOL_WITH_CACHE */
1676 /** Used to indicate that the page is zeroed. */
1677 bool fZeroed;
1678 /** Used to indicate that a PT has non-global entries. */
1679 bool fSeenNonGlobal;
1680 /** Used to indicate that we're monitoring writes to the guest page. */
1681 bool fMonitored;
1682 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1683 * (All pages are in the age list.) */
1684 bool fCached;
1685 /** This is used by the R3 access handlers when invoked by an async thread.
1686 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1687 bool volatile fReusedFlushPending;
1688#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1689 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1690 bool fLocked;
1691#else
1692 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1693 * In these cases the access handler acts differently and will check
1694 * for mapping conflicts like the normal CR3 handler.
1695 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1696 * replaced by a list of pages which share access handler.
1697 */
1698 bool fCR3Mix;
1699#endif
1700} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1701
1702
1703#ifdef PGMPOOL_WITH_CACHE
1704/** The hash table size. */
1705# define PGMPOOL_HASH_SIZE 0x40
1706/** The hash function. */
1707# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1708#endif
1709
1710
1711/**
1712 * The shadow page pool instance data.
1713 *
1714 * It's all one big allocation made at init time, except for the
1715 * pages that is. The user nodes follows immediatly after the
1716 * page structures.
1717 */
1718typedef struct PGMPOOL
1719{
1720 /** The VM handle - R3 Ptr. */
1721 PVMR3 pVMR3;
1722 /** The VM handle - R0 Ptr. */
1723 PVMR0 pVMR0;
1724 /** The VM handle - RC Ptr. */
1725 PVMRC pVMRC;
1726 /** The max pool size. This includes the special IDs. */
1727 uint16_t cMaxPages;
1728 /** The current pool size. */
1729 uint16_t cCurPages;
1730 /** The head of the free page list. */
1731 uint16_t iFreeHead;
1732 /* Padding. */
1733 uint16_t u16Padding;
1734#ifdef PGMPOOL_WITH_USER_TRACKING
1735 /** Head of the chain of free user nodes. */
1736 uint16_t iUserFreeHead;
1737 /** The number of user nodes we've allocated. */
1738 uint16_t cMaxUsers;
1739 /** The number of present page table entries in the entire pool. */
1740 uint32_t cPresent;
1741 /** Pointer to the array of user nodes - RC pointer. */
1742 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1743 /** Pointer to the array of user nodes - R3 pointer. */
1744 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1745 /** Pointer to the array of user nodes - R0 pointer. */
1746 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1747#endif /* PGMPOOL_WITH_USER_TRACKING */
1748#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1749 /** Head of the chain of free phys ext nodes. */
1750 uint16_t iPhysExtFreeHead;
1751 /** The number of user nodes we've allocated. */
1752 uint16_t cMaxPhysExts;
1753 /** Pointer to the array of physical xref extent - RC pointer. */
1754 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1755 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1756 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1757 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1758 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1759#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1760#ifdef PGMPOOL_WITH_CACHE
1761 /** Hash table for GCPhys addresses. */
1762 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1763 /** The head of the age list. */
1764 uint16_t iAgeHead;
1765 /** The tail of the age list. */
1766 uint16_t iAgeTail;
1767 /** Set if the cache is enabled. */
1768 bool fCacheEnabled;
1769#endif /* PGMPOOL_WITH_CACHE */
1770#ifdef PGMPOOL_WITH_MONITORING
1771 /** Head of the list of modified pages. */
1772 uint16_t iModifiedHead;
1773 /** The current number of modified pages. */
1774 uint16_t cModifiedPages;
1775 /** Access handler, RC. */
1776 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1777 /** Access handler, R0. */
1778 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1779 /** Access handler, R3. */
1780 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1781 /** The access handler description (HC ptr). */
1782 R3PTRTYPE(const char *) pszAccessHandler;
1783#endif /* PGMPOOL_WITH_MONITORING */
1784 /** The number of pages currently in use. */
1785 uint16_t cUsedPages;
1786#ifdef VBOX_WITH_STATISTICS
1787 /** The high wather mark for cUsedPages. */
1788 uint16_t cUsedPagesHigh;
1789 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1790 /** Profiling pgmPoolAlloc(). */
1791 STAMPROFILEADV StatAlloc;
1792 /** Profiling pgmPoolClearAll(). */
1793 STAMPROFILE StatClearAll;
1794 /** Profiling pgmPoolFlushAllInt(). */
1795 STAMPROFILE StatFlushAllInt;
1796 /** Profiling pgmPoolFlushPage(). */
1797 STAMPROFILE StatFlushPage;
1798 /** Profiling pgmPoolFree(). */
1799 STAMPROFILE StatFree;
1800 /** Profiling time spent zeroing pages. */
1801 STAMPROFILE StatZeroPage;
1802# ifdef PGMPOOL_WITH_USER_TRACKING
1803 /** Profiling of pgmPoolTrackDeref. */
1804 STAMPROFILE StatTrackDeref;
1805 /** Profiling pgmTrackFlushGCPhysPT. */
1806 STAMPROFILE StatTrackFlushGCPhysPT;
1807 /** Profiling pgmTrackFlushGCPhysPTs. */
1808 STAMPROFILE StatTrackFlushGCPhysPTs;
1809 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1810 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1811 /** Number of times we've been out of user records. */
1812 STAMCOUNTER StatTrackFreeUpOneUser;
1813# endif
1814# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1815 /** Profiling deref activity related tracking GC physical pages. */
1816 STAMPROFILE StatTrackDerefGCPhys;
1817 /** Number of linear searches for a HCPhys in the ram ranges. */
1818 STAMCOUNTER StatTrackLinearRamSearches;
1819 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1820 STAMCOUNTER StamTrackPhysExtAllocFailures;
1821# endif
1822# ifdef PGMPOOL_WITH_MONITORING
1823 /** Profiling the RC/R0 access handler. */
1824 STAMPROFILE StatMonitorRZ;
1825 /** Times we've failed interpreting the instruction. */
1826 STAMCOUNTER StatMonitorRZEmulateInstr;
1827 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1828 STAMPROFILE StatMonitorRZFlushPage;
1829 /** Times we've detected fork(). */
1830 STAMCOUNTER StatMonitorRZFork;
1831 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1832 STAMPROFILE StatMonitorRZHandled;
1833 /** Times we've failed interpreting a patch code instruction. */
1834 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1835 /** Times we've failed interpreting a patch code instruction during flushing. */
1836 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1837 /** The number of times we've seen rep prefixes we can't handle. */
1838 STAMCOUNTER StatMonitorRZRepPrefix;
1839 /** Profiling the REP STOSD cases we've handled. */
1840 STAMPROFILE StatMonitorRZRepStosd;
1841
1842 /** Profiling the R3 access handler. */
1843 STAMPROFILE StatMonitorR3;
1844 /** Times we've failed interpreting the instruction. */
1845 STAMCOUNTER StatMonitorR3EmulateInstr;
1846 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1847 STAMPROFILE StatMonitorR3FlushPage;
1848 /** Times we've detected fork(). */
1849 STAMCOUNTER StatMonitorR3Fork;
1850 /** Profiling the R3 access we've handled (except REP STOSD). */
1851 STAMPROFILE StatMonitorR3Handled;
1852 /** The number of times we've seen rep prefixes we can't handle. */
1853 STAMCOUNTER StatMonitorR3RepPrefix;
1854 /** Profiling the REP STOSD cases we've handled. */
1855 STAMPROFILE StatMonitorR3RepStosd;
1856 /** The number of times we're called in an async thread an need to flush. */
1857 STAMCOUNTER StatMonitorR3Async;
1858 /** The high wather mark for cModifiedPages. */
1859 uint16_t cModifiedPagesHigh;
1860 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1861# endif
1862# ifdef PGMPOOL_WITH_CACHE
1863 /** The number of cache hits. */
1864 STAMCOUNTER StatCacheHits;
1865 /** The number of cache misses. */
1866 STAMCOUNTER StatCacheMisses;
1867 /** The number of times we've got a conflict of 'kind' in the cache. */
1868 STAMCOUNTER StatCacheKindMismatches;
1869 /** Number of times we've been out of pages. */
1870 STAMCOUNTER StatCacheFreeUpOne;
1871 /** The number of cacheable allocations. */
1872 STAMCOUNTER StatCacheCacheable;
1873 /** The number of uncacheable allocations. */
1874 STAMCOUNTER StatCacheUncacheable;
1875# endif
1876#elif HC_ARCH_BITS == 64
1877 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1878#endif
1879 /** The AVL tree for looking up a page by its HC physical address. */
1880 AVLOHCPHYSTREE HCPhysTree;
1881 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1882 /** Array of pages. (cMaxPages in length)
1883 * The Id is the index into thist array.
1884 */
1885 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1886} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1887
1888
1889/** @def PGMPOOL_PAGE_2_PTR
1890 * Maps a pool page pool into the current context.
1891 *
1892 * @returns VBox status code.
1893 * @param pVM The VM handle.
1894 * @param pPage The pool page.
1895 *
1896 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1897 * small page window employeed by that function. Be careful.
1898 * @remark There is no need to assert on the result.
1899 */
1900#if defined(IN_RC)
1901# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1902#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1903# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1904#elif defined(VBOX_STRICT)
1905# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1906DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1907{
1908 Assert(pPage && pPage->pvPageR3);
1909 return pPage->pvPageR3;
1910}
1911#else
1912# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1913#endif
1914
1915/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1916 * Maps a pool page pool into the current context.
1917 *
1918 * @returns VBox status code.
1919 * @param pPGM Pointer to the PGM instance data.
1920 * @param pPage The pool page.
1921 *
1922 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1923 * small page window employeed by that function. Be careful.
1924 * @remark There is no need to assert on the result.
1925 */
1926#if defined(IN_RC)
1927# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1928#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1929# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1930#else
1931# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1932#endif
1933
1934
1935/** @name Per guest page tracking data.
1936 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1937 * is to use more bits for it and split it up later on. But for now we'll play
1938 * safe and change as little as possible.
1939 *
1940 * The 16-bit word has two parts:
1941 *
1942 * The first 14-bit forms the @a idx field. It is either the index of a page in
1943 * the shadow page pool, or and index into the extent list.
1944 *
1945 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1946 * shadow page pool references to the page. If cRefs equals
1947 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1948 * (misnomer) table and not the shadow page pool.
1949 *
1950 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1951 * the 16-bit word.
1952 *
1953 * @{ */
1954/** The shift count for getting to the cRefs part. */
1955#define PGMPOOL_TD_CREFS_SHIFT 14
1956/** The mask applied after shifting the tracking data down by
1957 * PGMPOOL_TD_CREFS_SHIFT. */
1958#define PGMPOOL_TD_CREFS_MASK 0x3
1959/** The cRef value used to indiciate that the idx is the head of a
1960 * physical cross reference list. */
1961#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1962/** The shift used to get idx. */
1963#define PGMPOOL_TD_IDX_SHIFT 0
1964/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1965#define PGMPOOL_TD_IDX_MASK 0x3fff
1966/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1967 * simply too many mappings of this page. */
1968#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1969
1970/** @def PGMPOOL_TD_MAKE
1971 * Makes a 16-bit tracking data word.
1972 *
1973 * @returns tracking data.
1974 * @param cRefs The @a cRefs field. Must be within bounds!
1975 * @param idx The @a idx field. Must also be within bounds! */
1976#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1977
1978/** @def PGMPOOL_TD_GET_CREFS
1979 * Get the @a cRefs field from a tracking data word.
1980 *
1981 * @returns The @a cRefs field
1982 * @param u16 The tracking data word. */
1983#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1984
1985/** @def PGMPOOL_TD_GET_IDX
1986 * Get the @a idx field from a tracking data word.
1987 *
1988 * @returns The @a idx field
1989 * @param u16 The tracking data word. */
1990#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1991/** @} */
1992
1993
1994/**
1995 * Trees are using self relative offsets as pointers.
1996 * So, all its data, including the root pointer, must be in the heap for HC and GC
1997 * to have the same layout.
1998 */
1999typedef struct PGMTREES
2000{
2001 /** Physical access handlers (AVL range+offsetptr tree). */
2002 AVLROGCPHYSTREE PhysHandlers;
2003 /** Virtual access handlers (AVL range + GC ptr tree). */
2004 AVLROGCPTRTREE VirtHandlers;
2005 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2006 AVLROGCPHYSTREE PhysToVirtHandlers;
2007 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2008 AVLROGCPTRTREE HyperVirtHandlers;
2009} PGMTREES;
2010/** Pointer to PGM trees. */
2011typedef PGMTREES *PPGMTREES;
2012
2013
2014/** @name Paging mode macros
2015 * @{ */
2016#ifdef IN_RC
2017# define PGM_CTX(a,b) a##RC##b
2018# define PGM_CTX_STR(a,b) a "GC" b
2019# define PGM_CTX_DECL(type) VMMRCDECL(type)
2020#else
2021# ifdef IN_RING3
2022# define PGM_CTX(a,b) a##R3##b
2023# define PGM_CTX_STR(a,b) a "R3" b
2024# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2025# else
2026# define PGM_CTX(a,b) a##R0##b
2027# define PGM_CTX_STR(a,b) a "R0" b
2028# define PGM_CTX_DECL(type) VMMDECL(type)
2029# endif
2030#endif
2031
2032#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2033#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2034#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2035#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2036#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2037#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2038#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2039#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2040#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2041#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2042#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2043#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2044#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2045#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2046#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2047#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2048#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2049
2050#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2051#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2052#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2053#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2054#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2055#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2056#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2057#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2058#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2059#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2060#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2061#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2062#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2063#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2064#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2065#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2066#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2067
2068/* Shw_Gst */
2069#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2070#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2071#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2072#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2073#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2074#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2075#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2076#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2077#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2078#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2079#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2080#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2081#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2082#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2083#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2084#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2085#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2086#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2087#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2088
2089#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2090#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2091#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2092#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2093#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2094#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2095#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2096#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2097#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2098#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2099#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2100#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2101#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2102#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2103#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2104#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2105#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2106#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2107#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2108#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2109#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2110#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2111#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2112#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2113#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2114#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2115#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2116#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2117#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2118#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2119#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2120#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2121#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2122#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2123#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2124#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2125#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2126
2127#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2128#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2129/** @} */
2130
2131/**
2132 * Data for each paging mode.
2133 */
2134typedef struct PGMMODEDATA
2135{
2136 /** The guest mode type. */
2137 uint32_t uGstType;
2138 /** The shadow mode type. */
2139 uint32_t uShwType;
2140
2141 /** @name Function pointers for Shadow paging.
2142 * @{
2143 */
2144 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2145 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2146 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2147 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2148
2149 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2150 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2151
2152 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2153 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2154 /** @} */
2155
2156 /** @name Function pointers for Guest paging.
2157 * @{
2158 */
2159 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2160 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2161 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2162 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2163 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2164#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2165 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2166 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2167#endif
2168#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2169 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2170 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2171 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2172 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2173#endif
2174 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2175 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2176 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2177#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2178 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2179 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2180#endif
2181#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2182 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2183 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2184#endif
2185 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2186 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2187 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2188#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2189 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2190 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2191#endif
2192#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2193 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2194 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2195#endif
2196 /** @} */
2197
2198 /** @name Function pointers for Both Shadow and Guest paging.
2199 * @{
2200 */
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2202 /* no pfnR3BthTrap0eHandler */
2203 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2204 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2207 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2208#ifdef VBOX_STRICT
2209 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2210#endif
2211 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2212 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2213
2214 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2215 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2216 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2219 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2220#ifdef VBOX_STRICT
2221 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2222#endif
2223 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2224 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2225
2226 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2227 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2228 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2231 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2232#ifdef VBOX_STRICT
2233 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2234#endif
2235 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2236 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2237 /** @} */
2238} PGMMODEDATA, *PPGMMODEDATA;
2239
2240
2241
2242/**
2243 * Converts a PGM pointer into a VM pointer.
2244 * @returns Pointer to the VM structure the PGM is part of.
2245 * @param pPGM Pointer to PGM instance data.
2246 */
2247#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2248
2249/**
2250 * PGM Data (part of VM)
2251 */
2252typedef struct PGM
2253{
2254 /** Offset to the VM structure. */
2255 RTINT offVM;
2256 /** Offset of the PGMCPU structure relative to VMCPU. */
2257 int32_t offVCpu;
2258 /** @cfgm{PGM/RamPreAlloc, bool, false}
2259 * Whether to preallocate all the guest RAM or not. */
2260 bool fRamPreAlloc;
2261 /** Alignment padding. */
2262 bool afAlignment0[3];
2263
2264
2265 /*
2266 * This will be redefined at least two more times before we're done, I'm sure.
2267 * The current code is only to get on with the coding.
2268 * - 2004-06-10: initial version, bird.
2269 * - 2004-07-02: 1st time, bird.
2270 * - 2004-10-18: 2nd time, bird.
2271 * - 2005-07-xx: 3rd time, bird.
2272 */
2273
2274 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2275 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2276 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2277 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2278
2279 /** The host paging mode. (This is what SUPLib reports.) */
2280 SUPPAGINGMODE enmHostMode;
2281 /** The shadow paging mode. */
2282 PGMMODE enmShadowMode;
2283 /** The guest paging mode. */
2284 PGMMODE enmGuestMode;
2285
2286 /** The current physical address representing in the guest CR3 register. */
2287 RTGCPHYS GCPhysCR3;
2288 /** Pointer to the 5 page CR3 content mapping.
2289 * The first page is always the CR3 (in some form) while the 4 other pages
2290 * are used of the PDs in PAE mode. */
2291 RTGCPTR GCPtrCR3Mapping;
2292#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2293 uint32_t u32Alignment;
2294#endif
2295#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2296 /** The physical address of the currently monitored guest CR3 page.
2297 * When this value is NIL_RTGCPHYS no page is being monitored. */
2298 RTGCPHYS GCPhysGstCR3Monitored;
2299#endif
2300 /** @name 32-bit Guest Paging.
2301 * @{ */
2302 /** The guest's page directory, R3 pointer. */
2303 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2304#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2305 /** The guest's page directory, R0 pointer. */
2306 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2307#endif
2308 /** The guest's page directory, static RC mapping. */
2309 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2310 /** @} */
2311
2312 /** @name PAE Guest Paging.
2313 * @{ */
2314 /** The guest's page directory pointer table, static RC mapping. */
2315 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2316 /** The guest's page directory pointer table, R3 pointer. */
2317 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2318#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2319 /** The guest's page directory pointer table, R0 pointer. */
2320 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2321#endif
2322
2323 /** The guest's page directories, R3 pointers.
2324 * These are individual pointers and don't have to be adjecent.
2325 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2326 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2327 /** The guest's page directories, R0 pointers.
2328 * Same restrictions as apGstPaePDsR3. */
2329#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2330 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2331#endif
2332 /** The guest's page directories, static GC mapping.
2333 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2334 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2335 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2336 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2337 RTGCPHYS aGCPhysGstPaePDs[4];
2338 /** The physical addresses of the monitored guest page directories (PAE). */
2339 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2340 /** @} */
2341
2342 /** @name AMD64 Guest Paging.
2343 * @{ */
2344 /** The guest's page directory pointer table, R3 pointer. */
2345 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2346#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2347 /** The guest's page directory pointer table, R0 pointer. */
2348 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2349#endif
2350 /** @} */
2351
2352# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2353 /** @name Shadow paging
2354 * @{ */
2355 /** The root page table - R3 Ptr. */
2356 R3PTRTYPE(void *) pShwRootR3;
2357# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2358 /** The root page table - R0 Ptr. */
2359 R0PTRTYPE(void *) pShwRootR0;
2360# endif
2361 /** The root page table - RC Ptr. */
2362 RCPTRTYPE(void *) pShwRootRC;
2363# if HC_ARCH_BITS == 64
2364 uint32_t u32Padding1; /**< alignment padding. */
2365# endif
2366 /** The Physical Address (HC) of the current active shadow CR3. */
2367 RTHCPHYS HCPhysShwCR3;
2368# endif
2369 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2370 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2371 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2372 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2373 /** Pointer to the page of the current active CR3 - RC Ptr. */
2374 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2375 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2376 uint32_t iShwUser;
2377 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2378 uint32_t iShwUserTable;
2379# if HC_ARCH_BITS == 64
2380 RTRCPTR alignment6; /**< structure size alignment. */
2381# endif
2382 /** @} */
2383#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2384 /** @name 32-bit Shadow Paging
2385 * @{ */
2386 /** The 32-Bit PD - R3 Ptr. */
2387 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2388 /** The 32-Bit PD - R0 Ptr. */
2389 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2390 /** The 32-Bit PD - RC Ptr. */
2391 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2392# if HC_ARCH_BITS == 64
2393 uint32_t u32Padding10; /**< alignment padding. */
2394# endif
2395 /** The Physical Address (HC) of the 32-Bit PD. */
2396 RTHCPHYS HCPhysShw32BitPD;
2397 /** @} */
2398
2399 /** @name PAE Shadow Paging
2400 * @{ */
2401 /** The four PDs for the low 4GB - R3 Ptr.
2402 * Even though these are 4 pointers, what they point at is a single table.
2403 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2404 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2405# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2406 /** The four PDs for the low 4GB - R0 Ptr.
2407 * Same kind of mapping as apHCPaePDs. */
2408 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2409# endif
2410 /** The four PDs for the low 4GB - RC Ptr.
2411 * Same kind of mapping as apHCPaePDs. */
2412 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2413 /** The Physical Address (HC) of the four PDs for the low 4GB.
2414 * These are *NOT* 4 contiguous pages. */
2415 RTHCPHYS aHCPhysPaePDs[4];
2416 /** The Physical Address (HC) of the PAE PDPT. */
2417 RTHCPHYS HCPhysShwPaePdpt;
2418 /** The PAE PDPT - R3 Ptr. */
2419 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2420 /** The PAE PDPT - R0 Ptr. */
2421 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2422 /** The PAE PDPT - RC Ptr. */
2423 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2424 /** @} */
2425# if HC_ARCH_BITS == 64
2426 RTRCPTR alignment5; /**< structure size alignment. */
2427# endif
2428 /** @name Nested Shadow Paging
2429 * @{ */
2430 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2431 RTR3PTR pShwNestedRootR3;
2432# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2433 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2434 RTR0PTR pShwNestedRootR0;
2435# endif
2436 /** The Physical Address (HC) of the nested paging root. */
2437 RTHCPHYS HCPhysShwNestedRoot;
2438 /** @} */
2439#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2440
2441 /** @name Function pointers for Shadow paging.
2442 * @{
2443 */
2444 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2445 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2446 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2447 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2448
2449 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2450 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2451
2452 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2453 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2454
2455 /** @} */
2456
2457 /** @name Function pointers for Guest paging.
2458 * @{
2459 */
2460 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2461 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2462 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2463 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2464 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2465#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2466 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2467 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2468#endif
2469#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2470 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2471 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2472 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2473 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2474#endif
2475 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2476 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2477 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2478#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2479 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2480 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2481#endif
2482#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2483 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2484 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2485#endif
2486#if HC_ARCH_BITS == 64
2487 RTRCPTR alignment3; /**< structure size alignment. */
2488#endif
2489
2490 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2491 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2492 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2493#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2494 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2495 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2496#endif
2497#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2498 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2499 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2500#endif
2501 /** @} */
2502
2503 /** @name Function pointers for Both Shadow and Guest paging.
2504 * @{
2505 */
2506 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2507 /* no pfnR3BthTrap0eHandler */
2508 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2509 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2510 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2511 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2512 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2513 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2514 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2515 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2516
2517 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2518 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2519 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2520 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2521 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2522 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2523 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2524 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2525 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2526
2527 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2528 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2529 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2530 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2531 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2532 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2533 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2534 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2535 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2536#if HC_ARCH_BITS == 64
2537 RTRCPTR alignment2; /**< structure size alignment. */
2538#endif
2539 /** @} */
2540
2541 /** Pointer to SHW+GST mode data (function pointers).
2542 * The index into this table is made up from */
2543 R3PTRTYPE(PPGMMODEDATA) paModeData;
2544
2545 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2546 * This is sorted by physical address and contains no overlapping ranges. */
2547 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2548 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2549 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2550 /** RC pointer corresponding to PGM::pRamRangesR3. */
2551 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2552 /** The configured RAM size. */
2553 RTUINT cbRamSize;
2554
2555 /** Pointer to the list of ROM ranges - for R3.
2556 * This is sorted by physical address and contains no overlapping ranges. */
2557 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2558 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2559 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2560 /** RC pointer corresponding to PGM::pRomRangesR3. */
2561 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2562 /** Alignment padding. */
2563 RTRCPTR GCPtrPadding2;
2564
2565 /** Pointer to the list of MMIO2 ranges - for R3.
2566 * Registration order. */
2567 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2568
2569 /** PGM offset based trees - R3 Ptr. */
2570 R3PTRTYPE(PPGMTREES) pTreesR3;
2571 /** PGM offset based trees - R0 Ptr. */
2572 R0PTRTYPE(PPGMTREES) pTreesR0;
2573 /** PGM offset based trees - RC Ptr. */
2574 RCPTRTYPE(PPGMTREES) pTreesRC;
2575
2576 /** Linked list of GC mappings - for RC.
2577 * The list is sorted ascending on address.
2578 */
2579 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2580 /** Linked list of GC mappings - for HC.
2581 * The list is sorted ascending on address.
2582 */
2583 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2584 /** Linked list of GC mappings - for R0.
2585 * The list is sorted ascending on address.
2586 */
2587 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2588
2589 /** Indicates that PGMR3FinalizeMappings has been called and that further
2590 * PGMR3MapIntermediate calls will be rejected. */
2591 bool fFinalizedMappings;
2592 /** If set no conflict checks are required. (boolean) */
2593 bool fMappingsFixed;
2594 /** If set, then no mappings are put into the shadow page table. (boolean) */
2595 bool fDisableMappings;
2596 /** Size of fixed mapping */
2597 uint32_t cbMappingFixed;
2598 /** Base address (GC) of fixed mapping */
2599 RTGCPTR GCPtrMappingFixed;
2600#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2601 uint32_t u32Padding0; /**< alignment padding. */
2602#endif
2603
2604
2605 /** @name Intermediate Context
2606 * @{ */
2607 /** Pointer to the intermediate page directory - Normal. */
2608 R3PTRTYPE(PX86PD) pInterPD;
2609 /** Pointer to the intermedate page tables - Normal.
2610 * There are two page tables, one for the identity mapping and one for
2611 * the host context mapping (of the core code). */
2612 R3PTRTYPE(PX86PT) apInterPTs[2];
2613 /** Pointer to the intermedate page tables - PAE. */
2614 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2615 /** Pointer to the intermedate page directory - PAE. */
2616 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2617 /** Pointer to the intermedate page directory - PAE. */
2618 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2619 /** Pointer to the intermedate page-map level 4 - AMD64. */
2620 R3PTRTYPE(PX86PML4) pInterPaePML4;
2621 /** Pointer to the intermedate page directory - AMD64. */
2622 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2623 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2624 RTHCPHYS HCPhysInterPD;
2625 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2626 RTHCPHYS HCPhysInterPaePDPT;
2627 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2628 RTHCPHYS HCPhysInterPaePML4;
2629 /** @} */
2630
2631 /** Base address of the dynamic page mapping area.
2632 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2633 */
2634 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2635 /** The index of the last entry used in the dynamic page mapping area. */
2636 RTUINT iDynPageMapLast;
2637 /** Cache containing the last entries in the dynamic page mapping area.
2638 * The cache size is covering half of the mapping area. */
2639 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2640 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2641
2642 /** The address of the ring-0 mapping cache if we're making use of it. */
2643 RTR0PTR pvR0DynMapUsed;
2644#if HC_ARCH_BITS == 32
2645 RTR0PTR R0PtrPadding0; /**< Alignment. */
2646#endif
2647
2648
2649 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2650 RTGCPHYS GCPhys4MBPSEMask;
2651
2652 /** A20 gate mask.
2653 * Our current approach to A20 emulation is to let REM do it and don't bother
2654 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2655 * But whould need arrise, we'll subject physical addresses to this mask. */
2656 RTGCPHYS GCPhysA20Mask;
2657 /** A20 gate state - boolean! */
2658 RTUINT fA20Enabled;
2659
2660 /** What needs syncing (PGM_SYNC_*).
2661 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2662 * PGMFlushTLB, and PGMR3Load. */
2663 RTUINT fSyncFlags;
2664
2665 /** PGM critical section.
2666 * This protects the physical & virtual access handlers, ram ranges,
2667 * and the page flag updating (some of it anyway).
2668 */
2669 PDMCRITSECT CritSect;
2670
2671 /** Shadow Page Pool - R3 Ptr. */
2672 R3PTRTYPE(PPGMPOOL) pPoolR3;
2673 /** Shadow Page Pool - R0 Ptr. */
2674 R0PTRTYPE(PPGMPOOL) pPoolR0;
2675 /** Shadow Page Pool - RC Ptr. */
2676 RCPTRTYPE(PPGMPOOL) pPoolRC;
2677
2678 /** We're not in a state which permits writes to guest memory.
2679 * (Only used in strict builds.) */
2680 bool fNoMorePhysWrites;
2681
2682 /** Flush the cache on the next access. */
2683 bool fPhysCacheFlushPending;
2684/** @todo r=bird: Fix member names!*/
2685 /** PGMPhysRead cache */
2686 PGMPHYSCACHE pgmphysreadcache;
2687 /** PGMPhysWrite cache */
2688 PGMPHYSCACHE pgmphyswritecache;
2689
2690 /**
2691 * Data associated with managing the ring-3 mappings of the allocation chunks.
2692 */
2693 struct
2694 {
2695 /** The chunk tree, ordered by chunk id. */
2696#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2697 R3PTRTYPE(PAVLU32NODECORE) pTree;
2698#else
2699 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2700#endif
2701 /** The chunk mapping TLB. */
2702 PGMCHUNKR3MAPTLB Tlb;
2703 /** The number of mapped chunks. */
2704 uint32_t c;
2705 /** The maximum number of mapped chunks.
2706 * @cfgm PGM/MaxRing3Chunks */
2707 uint32_t cMax;
2708 /** The chunk age tree, ordered by ageing sequence number. */
2709 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2710 /** The current time. */
2711 uint32_t iNow;
2712 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2713 uint32_t AgeingCountdown;
2714 } ChunkR3Map;
2715
2716 /**
2717 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2718 */
2719 PGMPAGER3MAPTLB PhysTlbHC;
2720
2721 /** @name The zero page.
2722 * @{ */
2723 /** The host physical address of the zero page. */
2724 RTHCPHYS HCPhysZeroPg;
2725 /** The ring-3 mapping of the zero page. */
2726 RTR3PTR pvZeroPgR3;
2727 /** The ring-0 mapping of the zero page. */
2728 RTR0PTR pvZeroPgR0;
2729 /** The GC mapping of the zero page. */
2730 RTGCPTR pvZeroPgGC;
2731#if GC_ARCH_BITS != 32
2732 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2733#endif
2734 /** @}*/
2735
2736 /** The number of handy pages. */
2737 uint32_t cHandyPages;
2738 /**
2739 * Array of handy pages.
2740 *
2741 * This array is used in a two way communication between pgmPhysAllocPage
2742 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2743 * an intermediary.
2744 *
2745 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2746 * (The current size of 32 pages, means 128 KB of handy memory.)
2747 */
2748 GMMPAGEDESC aHandyPages[32];
2749
2750 /** @name Release Statistics
2751 * @{ */
2752 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2753 uint32_t cPrivatePages; /**< The number of private pages. */
2754 uint32_t cSharedPages; /**< The number of shared pages. */
2755 uint32_t cZeroPages; /**< The number of zero backed pages. */
2756 /** The number of times the guest has switched mode since last reset or statistics reset. */
2757 STAMCOUNTER cGuestModeChanges;
2758 /** The number of times we were forced to change the hypervisor region location. */
2759 STAMCOUNTER cRelocations;
2760 /** @} */
2761
2762#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2763 /** RC: Which statistic this \#PF should be attributed to. */
2764 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2765 RTRCPTR padding0;
2766 /** R0: Which statistic this \#PF should be attributed to. */
2767 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2768 RTR0PTR padding1;
2769
2770 /* Common */
2771# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2772 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2773 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2774 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2775 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2776 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2777 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2778# endif
2779 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2780 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2781
2782 /* R3 only: */
2783 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2784 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2785 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2786 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2787#ifndef VBOX_WITH_NEW_PHYS_CODE
2788 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2789 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2790#endif
2791
2792 /* R0 only: */
2793 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2794 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2795 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2796 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2797 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2798 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2799 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2800 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2801 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2802 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2803 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2804 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2805 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2806 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2807 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2808 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2809 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2810 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2811 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2812 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2813 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2814 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2815 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2816 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2817 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2818 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2819
2820 /* RC only: */
2821 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2822 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2823 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2824 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2825
2826 /* RZ only: */
2827 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2828 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2829 STAMPROFILE StatRZTrap0eTimeSyncPT;
2830 STAMPROFILE StatRZTrap0eTimeMapping;
2831 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2832 STAMPROFILE StatRZTrap0eTimeHandlers;
2833 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2834 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2835 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2836 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2837 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2838 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2839 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2840 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2841 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2842 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2843 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2844 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2845 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2846 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2847 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2848 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2849 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2850 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2851 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2852 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2853 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2854 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2856 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2857 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2858 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2859 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2860 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2861 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2862 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2863 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2864 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2865 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2866 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2867 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2868 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2869 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2870 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2871 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2872 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2873 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2874 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2875 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2876
2877 /* HC - R3 and (maybe) R0: */
2878
2879 /* RZ & R3: */
2880 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2881 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2882 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2883 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2884 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2885 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2886 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2887 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2888 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2889 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2890 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2891 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2892 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2893 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2894 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2895 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2896 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2897 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2898 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2899 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2900 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2901 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2902 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2903 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2904 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2905 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2906 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2907 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2908 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2909 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2910 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2911 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2912 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2913 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2914 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2915 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2916 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2917 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2918 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2919 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2920 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2921 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2922 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2923 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2924 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2925 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2926 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2927/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2928 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2929 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2930 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2931 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2932 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2933 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2934
2935 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2936 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2937 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2938 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2939 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2940 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2941 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2942 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2943 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2944 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2945 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2946 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2947 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2948 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2949 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2950 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2951 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2952 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2953 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2954 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2955 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2956 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2957 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2958 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2959 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2960 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2961 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2962 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2963 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2964 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2965 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2966 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2967 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2968 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2969 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2970 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2971 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2972 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2973 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2974 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2975 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2976 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2977 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2978 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2979 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2980 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2981 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2982/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2983 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2984 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2985 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2986 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2987 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2988 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2989#endif /* VBOX_WITH_STATISTICS */
2990} PGM;
2991/** Pointer to the PGM instance data. */
2992typedef PGM *PPGM;
2993
2994
2995/**
2996 * PGMCPU Data (part of VMCPU).
2997 */
2998typedef struct PGMCPU
2999{
3000 /** Offset to the VMCPU structure. */
3001 RTINT offVMCPU;
3002 /** Automatically tracked physical memory mapping set.
3003 * Ring-0 and strict raw-mode builds. */
3004 PGMMAPSET AutoSet;
3005} PGMCPU;
3006/** Pointer to the per-cpu PGM data. */
3007typedef PGMCPU *PPGMCPU;
3008
3009
3010/** @name PGM::fSyncFlags Flags
3011 * @{
3012 */
3013/** Updates the virtual access handler state bit in PGMPAGE. */
3014#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3015/** Always sync CR3. */
3016#define PGM_SYNC_ALWAYS RT_BIT(1)
3017/** Check monitoring on next CR3 (re)load and invalidate page. */
3018#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3019/** Check guest mapping in SyncCR3. */
3020#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3021/** Clear the page pool (a light weight flush). */
3022#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
3023/** @} */
3024
3025
3026__BEGIN_DECLS
3027
3028int pgmLock(PVM pVM);
3029void pgmUnlock(PVM pVM);
3030
3031int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3032int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3033PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3034void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3035DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3036
3037void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3038bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3039int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3040DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3041#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3042void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3043#else
3044# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3045#endif
3046DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3047
3048
3049int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3050int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3051int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3052int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3053int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3054int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3055int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3056int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3057VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3058#ifdef IN_RING3
3059int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3060int pgmR3PhysRamReset(PVM pVM);
3061int pgmR3PhysRomReset(PVM pVM);
3062# ifndef VBOX_WITH_NEW_PHYS_CODE
3063int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3064# endif
3065
3066int pgmR3PoolInit(PVM pVM);
3067void pgmR3PoolRelocate(PVM pVM);
3068void pgmR3PoolReset(PVM pVM);
3069
3070#endif /* IN_RING3 */
3071#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3072int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3073#endif
3074#if !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && (defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0))
3075void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3076#endif
3077int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3078PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3079void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3080void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3081int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3082void pgmPoolFlushAll(PVM pVM);
3083void pgmPoolClearAll(PVM pVM);
3084int pgmPoolSyncCR3(PVM pVM);
3085int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3086void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3087void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3088int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3089PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3090void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3091void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3092uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3093void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3094#ifdef PGMPOOL_WITH_MONITORING
3095void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3096int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3097void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3098void pgmPoolMonitorModifiedClearAll(PVM pVM);
3099int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3100int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3101#endif
3102
3103#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3104void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3105void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3106int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3107#endif
3108int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3109int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3110
3111#ifndef IN_RC
3112int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3113#endif
3114int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3115
3116__END_DECLS
3117
3118
3119/**
3120 * Gets the PGMRAMRANGE structure for a guest page.
3121 *
3122 * @returns Pointer to the RAM range on success.
3123 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3124 *
3125 * @param pPGM PGM handle.
3126 * @param GCPhys The GC physical address.
3127 */
3128DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3129{
3130 /*
3131 * Optimize for the first range.
3132 */
3133 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3134 RTGCPHYS off = GCPhys - pRam->GCPhys;
3135 if (RT_UNLIKELY(off >= pRam->cb))
3136 {
3137 do
3138 {
3139 pRam = pRam->CTX_SUFF(pNext);
3140 if (RT_UNLIKELY(!pRam))
3141 break;
3142 off = GCPhys - pRam->GCPhys;
3143 } while (off >= pRam->cb);
3144 }
3145 return pRam;
3146}
3147
3148
3149/**
3150 * Gets the PGMPAGE structure for a guest page.
3151 *
3152 * @returns Pointer to the page on success.
3153 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3154 *
3155 * @param pPGM PGM handle.
3156 * @param GCPhys The GC physical address.
3157 */
3158DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3159{
3160 /*
3161 * Optimize for the first range.
3162 */
3163 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3164 RTGCPHYS off = GCPhys - pRam->GCPhys;
3165 if (RT_UNLIKELY(off >= pRam->cb))
3166 {
3167 do
3168 {
3169 pRam = pRam->CTX_SUFF(pNext);
3170 if (RT_UNLIKELY(!pRam))
3171 return NULL;
3172 off = GCPhys - pRam->GCPhys;
3173 } while (off >= pRam->cb);
3174 }
3175 return &pRam->aPages[off >> PAGE_SHIFT];
3176}
3177
3178
3179/**
3180 * Gets the PGMPAGE structure for a guest page.
3181 *
3182 * Old Phys code: Will make sure the page is present.
3183 *
3184 * @returns VBox status code.
3185 * @retval VINF_SUCCESS and a valid *ppPage on success.
3186 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3187 *
3188 * @param pPGM PGM handle.
3189 * @param GCPhys The GC physical address.
3190 * @param ppPage Where to store the page poitner on success.
3191 */
3192DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3193{
3194 /*
3195 * Optimize for the first range.
3196 */
3197 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3198 RTGCPHYS off = GCPhys - pRam->GCPhys;
3199 if (RT_UNLIKELY(off >= pRam->cb))
3200 {
3201 do
3202 {
3203 pRam = pRam->CTX_SUFF(pNext);
3204 if (RT_UNLIKELY(!pRam))
3205 {
3206 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3207 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3208 }
3209 off = GCPhys - pRam->GCPhys;
3210 } while (off >= pRam->cb);
3211 }
3212 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3213#ifndef VBOX_WITH_NEW_PHYS_CODE
3214
3215 /*
3216 * Make sure it's present.
3217 */
3218 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3219 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3220 {
3221#ifdef IN_RING3
3222 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3223#else
3224 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3225#endif
3226 if (RT_FAILURE(rc))
3227 {
3228 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3229 return rc;
3230 }
3231 Assert(rc == VINF_SUCCESS);
3232 }
3233#endif
3234 return VINF_SUCCESS;
3235}
3236
3237
3238
3239
3240/**
3241 * Gets the PGMPAGE structure for a guest page.
3242 *
3243 * Old Phys code: Will make sure the page is present.
3244 *
3245 * @returns VBox status code.
3246 * @retval VINF_SUCCESS and a valid *ppPage on success.
3247 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3248 *
3249 * @param pPGM PGM handle.
3250 * @param GCPhys The GC physical address.
3251 * @param ppPage Where to store the page poitner on success.
3252 * @param ppRamHint Where to read and store the ram list hint.
3253 * The caller initializes this to NULL before the call.
3254 */
3255DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3256{
3257 RTGCPHYS off;
3258 PPGMRAMRANGE pRam = *ppRamHint;
3259 if ( !pRam
3260 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3261 {
3262 pRam = pPGM->CTX_SUFF(pRamRanges);
3263 off = GCPhys - pRam->GCPhys;
3264 if (RT_UNLIKELY(off >= pRam->cb))
3265 {
3266 do
3267 {
3268 pRam = pRam->CTX_SUFF(pNext);
3269 if (RT_UNLIKELY(!pRam))
3270 {
3271 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3272 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3273 }
3274 off = GCPhys - pRam->GCPhys;
3275 } while (off >= pRam->cb);
3276 }
3277 *ppRamHint = pRam;
3278 }
3279 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3280#ifndef VBOX_WITH_NEW_PHYS_CODE
3281
3282 /*
3283 * Make sure it's present.
3284 */
3285 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3286 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3287 {
3288#ifdef IN_RING3
3289 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3290#else
3291 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3292#endif
3293 if (RT_FAILURE(rc))
3294 {
3295 *ppPage = NULL; /* Shut up annoying smart ass. */
3296 return rc;
3297 }
3298 Assert(rc == VINF_SUCCESS);
3299 }
3300#endif
3301 return VINF_SUCCESS;
3302}
3303
3304
3305/**
3306 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3307 *
3308 * @returns Pointer to the page on success.
3309 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3310 *
3311 * @param pPGM PGM handle.
3312 * @param GCPhys The GC physical address.
3313 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3314 */
3315DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3316{
3317 /*
3318 * Optimize for the first range.
3319 */
3320 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3321 RTGCPHYS off = GCPhys - pRam->GCPhys;
3322 if (RT_UNLIKELY(off >= pRam->cb))
3323 {
3324 do
3325 {
3326 pRam = pRam->CTX_SUFF(pNext);
3327 if (RT_UNLIKELY(!pRam))
3328 return NULL;
3329 off = GCPhys - pRam->GCPhys;
3330 } while (off >= pRam->cb);
3331 }
3332 *ppRam = pRam;
3333 return &pRam->aPages[off >> PAGE_SHIFT];
3334}
3335
3336
3337/**
3338 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3339 *
3340 * @returns Pointer to the page on success.
3341 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3342 *
3343 * @param pPGM PGM handle.
3344 * @param GCPhys The GC physical address.
3345 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3346 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3347 */
3348DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3349{
3350 /*
3351 * Optimize for the first range.
3352 */
3353 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3354 RTGCPHYS off = GCPhys - pRam->GCPhys;
3355 if (RT_UNLIKELY(off >= pRam->cb))
3356 {
3357 do
3358 {
3359 pRam = pRam->CTX_SUFF(pNext);
3360 if (RT_UNLIKELY(!pRam))
3361 {
3362 *ppRam = NULL; /* Shut up silly GCC warnings. */
3363 *ppPage = NULL; /* ditto */
3364 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3365 }
3366 off = GCPhys - pRam->GCPhys;
3367 } while (off >= pRam->cb);
3368 }
3369 *ppRam = pRam;
3370 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3371#ifndef VBOX_WITH_NEW_PHYS_CODE
3372
3373 /*
3374 * Make sure it's present.
3375 */
3376 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3377 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3378 {
3379#ifdef IN_RING3
3380 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3381#else
3382 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3383#endif
3384 if (RT_FAILURE(rc))
3385 {
3386 *ppPage = NULL; /* Shut up silly GCC warnings. */
3387 *ppPage = NULL; /* ditto */
3388 return rc;
3389 }
3390 Assert(rc == VINF_SUCCESS);
3391
3392 }
3393#endif
3394 return VINF_SUCCESS;
3395}
3396
3397
3398/**
3399 * Convert GC Phys to HC Phys.
3400 *
3401 * @returns VBox status.
3402 * @param pPGM PGM handle.
3403 * @param GCPhys The GC physical address.
3404 * @param pHCPhys Where to store the corresponding HC physical address.
3405 *
3406 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3407 * Avoid when writing new code!
3408 */
3409DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3410{
3411 PPGMPAGE pPage;
3412 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3413 if (RT_FAILURE(rc))
3414 return rc;
3415 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3416 return VINF_SUCCESS;
3417}
3418
3419#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3420
3421/**
3422 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3423 * optimizes access to pages already in the set.
3424 *
3425 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3426 * @param pPGM Pointer to the PVM instance data.
3427 * @param HCPhys The physical address of the page.
3428 * @param ppv Where to store the mapping address.
3429 */
3430DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3431{
3432 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3433 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3434 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3435 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3436
3437 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3438 unsigned iEntry = pSet->aiHashTable[iHash];
3439 if ( iEntry < pSet->cEntries
3440 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3441 {
3442 *ppv = pSet->aEntries[iEntry].pvPage;
3443 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3444 }
3445 else
3446 {
3447 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3448 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3449 }
3450
3451 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3452 return VINF_SUCCESS;
3453}
3454
3455
3456/**
3457 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3458 * access to pages already in the set.
3459 *
3460 * @returns See PGMDynMapGCPage.
3461 * @param pPGM Pointer to the PVM instance data.
3462 * @param HCPhys The physical address of the page.
3463 * @param ppv Where to store the mapping address.
3464 */
3465DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3466{
3467 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3468 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3469
3470 /*
3471 * Get the ram range.
3472 */
3473 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3474 RTGCPHYS off = GCPhys - pRam->GCPhys;
3475 if (RT_UNLIKELY(off >= pRam->cb
3476 /** @todo || page state stuff */))
3477 {
3478 /* This case is not counted into StatR0DynMapGCPageInl. */
3479 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3480 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3481 }
3482
3483 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3484 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3485
3486 /*
3487 * pgmR0DynMapHCPageInlined with out stats.
3488 */
3489 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3490 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3491 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3492
3493 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3494 unsigned iEntry = pSet->aiHashTable[iHash];
3495 if ( iEntry < pSet->cEntries
3496 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3497 {
3498 *ppv = pSet->aEntries[iEntry].pvPage;
3499 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3500 }
3501 else
3502 {
3503 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3504 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3505 }
3506
3507 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3508 return VINF_SUCCESS;
3509}
3510
3511#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3512#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3513
3514/**
3515 * Maps the page into current context (RC and maybe R0).
3516 *
3517 * @returns pointer to the mapping.
3518 * @param pVM Pointer to the PGM instance data.
3519 * @param pPage The page.
3520 */
3521DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3522{
3523 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3524 {
3525 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3526 void *pv;
3527# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3528 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3529# else
3530 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3531# endif
3532 return pv;
3533 }
3534#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3535 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3536#else
3537 return pgmPoolMapPageFallback(pPGM, pPage);
3538#endif
3539}
3540
3541/**
3542 * Temporarily maps one host page specified by HC physical address, returning
3543 * pointer within the page.
3544 *
3545 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3546 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3547 *
3548 * @returns The address corresponding to HCPhys.
3549 * @param pPGM Pointer to the PVM instance data.
3550 * @param HCPhys HC Physical address of the page.
3551 */
3552DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3553{
3554 void *pv;
3555# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3556 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3557# else
3558 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3559# endif
3560 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3561 return pv;
3562}
3563
3564#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3565
3566#ifndef IN_RC
3567/**
3568 * Queries the Physical TLB entry for a physical guest page,
3569 * attemting to load the TLB entry if necessary.
3570 *
3571 * @returns VBox status code.
3572 * @retval VINF_SUCCESS on success
3573 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3574 *
3575 * @param pPGM The PGM instance handle.
3576 * @param GCPhys The address of the guest page.
3577 * @param ppTlbe Where to store the pointer to the TLB entry.
3578 */
3579DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3580{
3581 int rc;
3582 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3583 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3584 {
3585 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3586 rc = VINF_SUCCESS;
3587 }
3588 else
3589 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3590 *ppTlbe = pTlbe;
3591 return rc;
3592}
3593
3594
3595/**
3596 * Queries the Physical TLB entry for a physical guest page,
3597 * attemting to load the TLB entry if necessary.
3598 *
3599 * @returns VBox status code.
3600 * @retval VINF_SUCCESS on success
3601 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3602 *
3603 * @param pPGM The PGM instance handle.
3604 * @param pPage Pointer to the PGMPAGE structure corresponding to
3605 * GCPhys.
3606 * @param GCPhys The address of the guest page.
3607 * @param ppTlbe Where to store the pointer to the TLB entry.
3608 */
3609DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3610{
3611 int rc;
3612 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3613 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3614 {
3615 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3616 rc = VINF_SUCCESS;
3617 }
3618 else
3619 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3620 *ppTlbe = pTlbe;
3621 return rc;
3622}
3623#endif /* !IN_RC */
3624
3625
3626#ifndef VBOX_WITH_NEW_PHYS_CODE
3627/**
3628 * Convert GC Phys to HC Virt and HC Phys.
3629 *
3630 * @returns VBox status.
3631 * @param pPGM PGM handle.
3632 * @param GCPhys The GC physical address.
3633 * @param pHCPtr Where to store the corresponding HC virtual address.
3634 * @param pHCPhys Where to store the HC Physical address and its flags.
3635 *
3636 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3637 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3638 * Either way, we have to make sure the page is writable in MapCR3.
3639 */
3640DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3641{
3642 PPGMRAMRANGE pRam;
3643 PPGMPAGE pPage;
3644 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3645 if (RT_FAILURE(rc))
3646 {
3647 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3648 *pHCPhys = 0; /* ditto */
3649 return rc;
3650 }
3651 RTGCPHYS off = GCPhys - pRam->GCPhys;
3652
3653 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3654 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3655 {
3656 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3657#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3658 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3659 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3660#else
3661 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3662#endif
3663 return VINF_SUCCESS;
3664 }
3665 if (pRam->pvR3)
3666 {
3667 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3668 return VINF_SUCCESS;
3669 }
3670 *pHCPtr = 0;
3671 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3672}
3673#endif /* VBOX_WITH_NEW_PHYS_CODE */
3674
3675
3676/**
3677 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3678 * Takes PSE-36 into account.
3679 *
3680 * @returns guest physical address
3681 * @param pPGM Pointer to the PGM instance data.
3682 * @param Pde Guest Pde
3683 */
3684DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3685{
3686 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3687 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3688
3689 return GCPhys & pPGM->GCPhys4MBPSEMask;
3690}
3691
3692
3693/**
3694 * Gets the page directory entry for the specified address (32-bit paging).
3695 *
3696 * @returns The page directory entry in question.
3697 * @param pPGM Pointer to the PGM instance data.
3698 * @param GCPtr The address.
3699 */
3700DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3701{
3702#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3703 PCX86PD pGuestPD = 0;
3704 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3705 if (RT_FAILURE(rc))
3706 {
3707 X86PDE ZeroPde = {0};
3708 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3709 }
3710 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3711#else
3712 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3713#endif
3714}
3715
3716
3717/**
3718 * Gets the address of a specific page directory entry (32-bit paging).
3719 *
3720 * @returns Pointer the page directory entry in question.
3721 * @param pPGM Pointer to the PGM instance data.
3722 * @param GCPtr The address.
3723 */
3724DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3725{
3726#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3727 PX86PD pGuestPD = 0;
3728 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3729 AssertRCReturn(rc, 0);
3730 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3731#else
3732 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3733#endif
3734}
3735
3736
3737/**
3738 * Gets the address the guest page directory (32-bit paging).
3739 *
3740 * @returns Pointer the page directory entry in question.
3741 * @param pPGM Pointer to the PGM instance data.
3742 */
3743DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3744{
3745#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3746 PX86PD pGuestPD = 0;
3747 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3748 AssertRCReturn(rc, 0);
3749 return pGuestPD;
3750#else
3751 return pPGM->CTX_SUFF(pGst32BitPd);
3752#endif
3753}
3754
3755
3756/**
3757 * Gets the guest page directory pointer table.
3758 *
3759 * @returns Pointer to the page directory in question.
3760 * @returns NULL if the page directory is not present or on an invalid page.
3761 * @param pPGM Pointer to the PGM instance data.
3762 */
3763DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3764{
3765#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3766 PX86PDPT pGuestPDPT = 0;
3767 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3768 AssertRCReturn(rc, 0);
3769 return pGuestPDPT;
3770#else
3771 return pPGM->CTX_SUFF(pGstPaePdpt);
3772#endif
3773}
3774
3775
3776/**
3777 * Gets the guest page directory pointer table entry for the specified address.
3778 *
3779 * @returns Pointer to the page directory in question.
3780 * @returns NULL if the page directory is not present or on an invalid page.
3781 * @param pPGM Pointer to the PGM instance data.
3782 * @param GCPtr The address.
3783 */
3784DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3785{
3786 AssertGCPtr32(GCPtr);
3787
3788#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3789 PX86PDPT pGuestPDPT = 0;
3790 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3791 AssertRCReturn(rc, 0);
3792 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3793#else
3794 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3795#endif
3796}
3797
3798
3799/**
3800 * Gets the page directory for the specified address.
3801 *
3802 * @returns Pointer to the page directory in question.
3803 * @returns NULL if the page directory is not present or on an invalid page.
3804 * @param pPGM Pointer to the PGM instance data.
3805 * @param GCPtr The address.
3806 */
3807DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3808{
3809 AssertGCPtr32(GCPtr);
3810
3811#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3812 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3813 AssertReturn(pGuestPDPT, 0);
3814#else
3815 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3816#endif
3817 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3818 if (pGuestPDPT->a[iPdPt].n.u1Present)
3819 {
3820#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3821 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3822 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3823#endif
3824
3825 /* cache is out-of-sync. */
3826 PX86PDPAE pPD;
3827 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3828 if (RT_SUCCESS(rc))
3829 return pPD;
3830 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3831 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3832 }
3833 return NULL;
3834}
3835
3836
3837/**
3838 * Gets the page directory entry for the specified address.
3839 *
3840 * @returns Pointer to the page directory entry in question.
3841 * @returns NULL if the page directory is not present or on an invalid page.
3842 * @param pPGM Pointer to the PGM instance data.
3843 * @param GCPtr The address.
3844 */
3845DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3846{
3847 AssertGCPtr32(GCPtr);
3848
3849#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3850 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3851 AssertReturn(pGuestPDPT, 0);
3852#else
3853 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3854#endif
3855 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3856 if (pGuestPDPT->a[iPdPt].n.u1Present)
3857 {
3858 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3859#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3860 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3861 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3862#endif
3863
3864 /* The cache is out-of-sync. */
3865 PX86PDPAE pPD;
3866 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3867 if (RT_SUCCESS(rc))
3868 return &pPD->a[iPD];
3869 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3870 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3871 }
3872 return NULL;
3873}
3874
3875
3876/**
3877 * Gets the page directory entry for the specified address.
3878 *
3879 * @returns The page directory entry in question.
3880 * @returns A non-present entry if the page directory is not present or on an invalid page.
3881 * @param pPGM Pointer to the PGM instance data.
3882 * @param GCPtr The address.
3883 */
3884DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3885{
3886 AssertGCPtr32(GCPtr);
3887
3888#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3889 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3890 if (RT_LIKELY(pGuestPDPT))
3891#else
3892 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3893#endif
3894 {
3895 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3896 if (pGuestPDPT->a[iPdPt].n.u1Present)
3897 {
3898 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3899#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3900 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3901 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3902#endif
3903
3904 /* cache is out-of-sync. */
3905 PX86PDPAE pPD;
3906 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3907 if (RT_SUCCESS(rc))
3908 return pPD->a[iPD];
3909 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3910 }
3911 }
3912 X86PDEPAE ZeroPde = {0};
3913 return ZeroPde;
3914}
3915
3916
3917/**
3918 * Gets the page directory pointer table entry for the specified address
3919 * and returns the index into the page directory
3920 *
3921 * @returns Pointer to the page directory in question.
3922 * @returns NULL if the page directory is not present or on an invalid page.
3923 * @param pPGM Pointer to the PGM instance data.
3924 * @param GCPtr The address.
3925 * @param piPD Receives the index into the returned page directory
3926 * @param pPdpe Receives the page directory pointer entry. Optional.
3927 */
3928DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3929{
3930 AssertGCPtr32(GCPtr);
3931
3932#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3933 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3934 AssertReturn(pGuestPDPT, 0);
3935#else
3936 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3937#endif
3938 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3939 if (pPdpe)
3940 *pPdpe = pGuestPDPT->a[iPdPt];
3941 if (pGuestPDPT->a[iPdPt].n.u1Present)
3942 {
3943 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3944#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3945 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3946 {
3947 *piPD = iPD;
3948 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3949 }
3950#endif
3951
3952 /* cache is out-of-sync. */
3953 PX86PDPAE pPD;
3954 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3955 if (RT_SUCCESS(rc))
3956 {
3957 *piPD = iPD;
3958 return pPD;
3959 }
3960 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3961 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3962 }
3963 return NULL;
3964}
3965
3966#ifndef IN_RC
3967
3968/**
3969 * Gets the page map level-4 pointer for the guest.
3970 *
3971 * @returns Pointer to the PML4 page.
3972 * @param pPGM Pointer to the PGM instance data.
3973 */
3974DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3975{
3976#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3977 PX86PML4 pGuestPml4;
3978 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3979 AssertRCReturn(rc, NULL);
3980 return pGuestPml4;
3981#else
3982 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3983 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3984#endif
3985}
3986
3987
3988/**
3989 * Gets the pointer to a page map level-4 entry.
3990 *
3991 * @returns Pointer to the PML4 entry.
3992 * @param pPGM Pointer to the PGM instance data.
3993 * @param iPml4 The index.
3994 */
3995DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3996{
3997#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3998 PX86PML4 pGuestPml4;
3999 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4000 AssertRCReturn(rc, NULL);
4001 return &pGuestPml4->a[iPml4];
4002#else
4003 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4004 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4005#endif
4006}
4007
4008
4009/**
4010 * Gets a page map level-4 entry.
4011 *
4012 * @returns The PML4 entry.
4013 * @param pPGM Pointer to the PGM instance data.
4014 * @param iPml4 The index.
4015 */
4016DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
4017{
4018#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4019 PX86PML4 pGuestPml4;
4020 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4021 if (RT_FAILURE(rc))
4022 {
4023 X86PML4E ZeroPml4e = {0};
4024 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4025 }
4026 return pGuestPml4->a[iPml4];
4027#else
4028 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4029 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4030#endif
4031}
4032
4033
4034/**
4035 * Gets the page directory pointer entry for the specified address.
4036 *
4037 * @returns Pointer to the page directory pointer entry in question.
4038 * @returns NULL if the page directory is not present or on an invalid page.
4039 * @param pPGM Pointer to the PGM instance data.
4040 * @param GCPtr The address.
4041 * @param ppPml4e Page Map Level-4 Entry (out)
4042 */
4043DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4044{
4045 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4046 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4047 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4048 if (pPml4e->n.u1Present)
4049 {
4050 PX86PDPT pPdpt;
4051 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4052 AssertRCReturn(rc, NULL);
4053
4054 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4055 return &pPdpt->a[iPdPt];
4056 }
4057 return NULL;
4058}
4059
4060
4061/**
4062 * Gets the page directory entry for the specified address.
4063 *
4064 * @returns The page directory entry in question.
4065 * @returns A non-present entry if the page directory is not present or on an invalid page.
4066 * @param pPGM Pointer to the PGM instance data.
4067 * @param GCPtr The address.
4068 * @param ppPml4e Page Map Level-4 Entry (out)
4069 * @param pPdpe Page directory pointer table entry (out)
4070 */
4071DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4072{
4073 X86PDEPAE ZeroPde = {0};
4074 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4075 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4076 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4077 if (pPml4e->n.u1Present)
4078 {
4079 PCX86PDPT pPdptTemp;
4080 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4081 AssertRCReturn(rc, ZeroPde);
4082
4083 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4084 *pPdpe = pPdptTemp->a[iPdPt];
4085 if (pPdptTemp->a[iPdPt].n.u1Present)
4086 {
4087 PCX86PDPAE pPD;
4088 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4089 AssertRCReturn(rc, ZeroPde);
4090
4091 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4092 return pPD->a[iPD];
4093 }
4094 }
4095
4096 return ZeroPde;
4097}
4098
4099
4100/**
4101 * Gets the page directory entry for the specified address.
4102 *
4103 * @returns The page directory entry in question.
4104 * @returns A non-present entry if the page directory is not present or on an invalid page.
4105 * @param pPGM Pointer to the PGM instance data.
4106 * @param GCPtr The address.
4107 */
4108DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4109{
4110 X86PDEPAE ZeroPde = {0};
4111 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4112 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4113 if (pGuestPml4->a[iPml4].n.u1Present)
4114 {
4115 PCX86PDPT pPdptTemp;
4116 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4117 AssertRCReturn(rc, ZeroPde);
4118
4119 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4120 if (pPdptTemp->a[iPdPt].n.u1Present)
4121 {
4122 PCX86PDPAE pPD;
4123 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4124 AssertRCReturn(rc, ZeroPde);
4125
4126 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4127 return pPD->a[iPD];
4128 }
4129 }
4130 return ZeroPde;
4131}
4132
4133
4134/**
4135 * Gets the page directory entry for the specified address.
4136 *
4137 * @returns Pointer to the page directory entry in question.
4138 * @returns NULL if the page directory is not present or on an invalid page.
4139 * @param pPGM Pointer to the PGM instance data.
4140 * @param GCPtr The address.
4141 */
4142DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4143{
4144 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4145 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4146 if (pGuestPml4->a[iPml4].n.u1Present)
4147 {
4148 PCX86PDPT pPdptTemp;
4149 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4150 AssertRCReturn(rc, NULL);
4151
4152 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4153 if (pPdptTemp->a[iPdPt].n.u1Present)
4154 {
4155 PX86PDPAE pPD;
4156 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4157 AssertRCReturn(rc, NULL);
4158
4159 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4160 return &pPD->a[iPD];
4161 }
4162 }
4163 return NULL;
4164}
4165
4166
4167/**
4168 * Gets the GUEST page directory pointer for the specified address.
4169 *
4170 * @returns The page directory in question.
4171 * @returns NULL if the page directory is not present or on an invalid page.
4172 * @param pPGM Pointer to the PGM instance data.
4173 * @param GCPtr The address.
4174 * @param ppPml4e Page Map Level-4 Entry (out)
4175 * @param pPdpe Page directory pointer table entry (out)
4176 * @param piPD Receives the index into the returned page directory
4177 */
4178DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4179{
4180 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4181 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4182 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4183 if (pPml4e->n.u1Present)
4184 {
4185 PCX86PDPT pPdptTemp;
4186 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4187 AssertRCReturn(rc, NULL);
4188
4189 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4190 *pPdpe = pPdptTemp->a[iPdPt];
4191 if (pPdptTemp->a[iPdPt].n.u1Present)
4192 {
4193 PX86PDPAE pPD;
4194 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4195 AssertRCReturn(rc, NULL);
4196
4197 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4198 return pPD;
4199 }
4200 }
4201 return 0;
4202}
4203
4204#endif /* !IN_RC */
4205
4206/**
4207 * Gets the shadow page directory, 32-bit.
4208 *
4209 * @returns Pointer to the shadow 32-bit PD.
4210 * @param pPGM Pointer to the PGM instance data.
4211 */
4212DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4213{
4214#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4215 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4216#else
4217# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4218 PX86PD pShwPd;
4219 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4220 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4221 AssertRCReturn(rc, NULL);
4222 return pShwPd;
4223# else
4224 return pPGM->CTX_SUFF(pShw32BitPd);
4225# endif
4226#endif
4227}
4228
4229
4230/**
4231 * Gets the shadow page directory entry for the specified address, 32-bit.
4232 *
4233 * @returns Shadow 32-bit PDE.
4234 * @param pPGM Pointer to the PGM instance data.
4235 * @param GCPtr The address.
4236 */
4237DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4238{
4239 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4240
4241 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4242 if (!pShwPde)
4243 {
4244 X86PDE ZeroPde = {0};
4245 return ZeroPde;
4246 }
4247 return pShwPde->a[iPd];
4248}
4249
4250
4251/**
4252 * Gets the pointer to the shadow page directory entry for the specified
4253 * address, 32-bit.
4254 *
4255 * @returns Pointer to the shadow 32-bit PDE.
4256 * @param pPGM Pointer to the PGM instance data.
4257 * @param GCPtr The address.
4258 */
4259DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4260{
4261 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4262
4263 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4264 AssertReturn(pPde, NULL);
4265 return &pPde->a[iPd];
4266}
4267
4268
4269/**
4270 * Gets the shadow page pointer table, PAE.
4271 *
4272 * @returns Pointer to the shadow PAE PDPT.
4273 * @param pPGM Pointer to the PGM instance data.
4274 */
4275DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4276{
4277#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4278 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4279#else
4280# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4281 PX86PDPT pShwPdpt;
4282 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4283 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4284 AssertRCReturn(rc, 0);
4285 return pShwPdpt;
4286# else
4287 return pPGM->CTX_SUFF(pShwPaePdpt);
4288# endif
4289#endif
4290}
4291
4292
4293/**
4294 * Gets the shadow page directory for the specified address, PAE.
4295 *
4296 * @returns Pointer to the shadow PD.
4297 * @param pPGM Pointer to the PGM instance data.
4298 * @param GCPtr The address.
4299 */
4300DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4301{
4302#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4303 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4304 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4305
4306 if (!pPdpt->a[iPdpt].n.u1Present)
4307 return NULL;
4308
4309 /* Fetch the pgm pool shadow descriptor. */
4310 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4311 AssertReturn(pShwPde, NULL);
4312
4313 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4314#else
4315 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4316# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4317 PX86PDPAE pPD;
4318 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4319 AssertRCReturn(rc, 0);
4320 return pPD;
4321# else
4322 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4323 Assert(pPD);
4324 return pPD;
4325# endif
4326#endif
4327}
4328
4329
4330/**
4331 * Gets the shadow page directory for the specified address, PAE.
4332 *
4333 * @returns Pointer to the shadow PD.
4334 * @param pPGM Pointer to the PGM instance data.
4335 * @param GCPtr The address.
4336 */
4337DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4338{
4339#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4340 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4341
4342 if (!pPdpt->a[iPdpt].n.u1Present)
4343 return NULL;
4344
4345 /* Fetch the pgm pool shadow descriptor. */
4346 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4347 AssertReturn(pShwPde, NULL);
4348
4349 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4350#else
4351 AssertFailed();
4352 return NULL;
4353#endif
4354}
4355
4356
4357/**
4358 * Gets the shadow page directory entry, PAE.
4359 *
4360 * @returns PDE.
4361 * @param pPGM Pointer to the PGM instance data.
4362 * @param GCPtr The address.
4363 */
4364DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4365{
4366 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4367
4368 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4369 if (!pShwPde)
4370 {
4371 X86PDEPAE ZeroPde = {0};
4372 return ZeroPde;
4373 }
4374 return pShwPde->a[iPd];
4375}
4376
4377
4378/**
4379 * Gets the pointer to the shadow page directory entry for an address, PAE.
4380 *
4381 * @returns Pointer to the PDE.
4382 * @param pPGM Pointer to the PGM instance data.
4383 * @param GCPtr The address.
4384 */
4385DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4386{
4387 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4388
4389 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4390 AssertReturn(pPde, NULL);
4391 return &pPde->a[iPd];
4392}
4393
4394#ifndef IN_RC
4395
4396/**
4397 * Gets the shadow page map level-4 pointer.
4398 *
4399 * @returns Pointer to the shadow PML4.
4400 * @param pPGM Pointer to the PGM instance data.
4401 */
4402DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4403{
4404#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4405 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4406#else
4407# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4408 PX86PML4 pShwPml4;
4409 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4410 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4411 AssertRCReturn(rc, 0);
4412 return pShwPml4;
4413# else
4414 Assert(pPGM->CTX_SUFF(pShwRoot));
4415 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4416# endif
4417#endif
4418}
4419
4420
4421/**
4422 * Gets the shadow page map level-4 entry for the specified address.
4423 *
4424 * @returns The entry.
4425 * @param pPGM Pointer to the PGM instance data.
4426 * @param GCPtr The address.
4427 */
4428DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4429{
4430 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4431 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4432
4433 if (!pShwPml4)
4434 {
4435 X86PML4E ZeroPml4e = {0};
4436 return ZeroPml4e;
4437 }
4438 return pShwPml4->a[iPml4];
4439}
4440
4441
4442/**
4443 * Gets the pointer to the specified shadow page map level-4 entry.
4444 *
4445 * @returns The entry.
4446 * @param pPGM Pointer to the PGM instance data.
4447 * @param iPml4 The PML4 index.
4448 */
4449DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4450{
4451 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4452 if (!pShwPml4)
4453 return NULL;
4454 return &pShwPml4->a[iPml4];
4455}
4456
4457
4458/**
4459 * Gets the GUEST page directory pointer for the specified address.
4460 *
4461 * @returns The page directory in question.
4462 * @returns NULL if the page directory is not present or on an invalid page.
4463 * @param pPGM Pointer to the PGM instance data.
4464 * @param GCPtr The address.
4465 * @param piPD Receives the index into the returned page directory
4466 */
4467DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4468{
4469 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4470 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4471 if (pGuestPml4->a[iPml4].n.u1Present)
4472 {
4473 PCX86PDPT pPdptTemp;
4474 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4475 AssertRCReturn(rc, NULL);
4476
4477 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4478 if (pPdptTemp->a[iPdPt].n.u1Present)
4479 {
4480 PX86PDPAE pPD;
4481 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4482 AssertRCReturn(rc, NULL);
4483
4484 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4485 return pPD;
4486 }
4487 }
4488 return NULL;
4489}
4490
4491#endif /* !IN_RC */
4492
4493/**
4494 * Gets the page state for a physical handler.
4495 *
4496 * @returns The physical handler page state.
4497 * @param pCur The physical handler in question.
4498 */
4499DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4500{
4501 switch (pCur->enmType)
4502 {
4503 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4504 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4505
4506 case PGMPHYSHANDLERTYPE_MMIO:
4507 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4508 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4509
4510 default:
4511 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4512 }
4513}
4514
4515
4516/**
4517 * Gets the page state for a virtual handler.
4518 *
4519 * @returns The virtual handler page state.
4520 * @param pCur The virtual handler in question.
4521 * @remarks This should never be used on a hypervisor access handler.
4522 */
4523DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4524{
4525 switch (pCur->enmType)
4526 {
4527 case PGMVIRTHANDLERTYPE_WRITE:
4528 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4529 case PGMVIRTHANDLERTYPE_ALL:
4530 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4531 default:
4532 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4533 }
4534}
4535
4536
4537/**
4538 * Clears one physical page of a virtual handler
4539 *
4540 * @param pPGM Pointer to the PGM instance.
4541 * @param pCur Virtual handler structure
4542 * @param iPage Physical page index
4543 *
4544 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4545 * need to care about other handlers in the same page.
4546 */
4547DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4548{
4549 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4550
4551 /*
4552 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4553 */
4554#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4555 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4556 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4557 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4558#endif
4559 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4560 {
4561 /* We're the head of the alias chain. */
4562 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4563#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4564 AssertReleaseMsg(pRemove != NULL,
4565 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4566 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4567 AssertReleaseMsg(pRemove == pPhys2Virt,
4568 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4569 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4570 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4571 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4572#endif
4573 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4574 {
4575 /* Insert the next list in the alias chain into the tree. */
4576 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4577#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4578 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4579 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4580 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4581#endif
4582 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4583 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4584 AssertRelease(fRc);
4585 }
4586 }
4587 else
4588 {
4589 /* Locate the previous node in the alias chain. */
4590 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4591#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4592 AssertReleaseMsg(pPrev != pPhys2Virt,
4593 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4594 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4595#endif
4596 for (;;)
4597 {
4598 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4599 if (pNext == pPhys2Virt)
4600 {
4601 /* unlink. */
4602 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4603 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4604 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4605 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4606 else
4607 {
4608 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4609 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4610 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4611 }
4612 break;
4613 }
4614
4615 /* next */
4616 if (pNext == pPrev)
4617 {
4618#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4619 AssertReleaseMsg(pNext != pPrev,
4620 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4621 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4622#endif
4623 break;
4624 }
4625 pPrev = pNext;
4626 }
4627 }
4628 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4629 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4630 pPhys2Virt->offNextAlias = 0;
4631 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4632
4633 /*
4634 * Clear the ram flags for this page.
4635 */
4636 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4637 AssertReturnVoid(pPage);
4638 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4639}
4640
4641
4642/**
4643 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4644 *
4645 * @returns Pointer to the shadow page structure.
4646 * @param pPool The pool.
4647 * @param HCPhys The HC physical address of the shadow page.
4648 */
4649DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4650{
4651 /*
4652 * Look up the page.
4653 */
4654 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4655 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4656 return pPage;
4657}
4658
4659
4660/**
4661 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4662 *
4663 * @returns Pointer to the shadow page structure.
4664 * @param pPool The pool.
4665 * @param idx The pool page index.
4666 */
4667DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4668{
4669 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4670 return &pPool->aPages[idx];
4671}
4672
4673
4674#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4675/**
4676 * Clear references to guest physical memory.
4677 *
4678 * @param pPool The pool.
4679 * @param pPoolPage The pool page.
4680 * @param pPhysPage The physical guest page tracking structure.
4681 */
4682DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4683{
4684 /*
4685 * Just deal with the simple case here.
4686 */
4687# ifdef LOG_ENABLED
4688 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4689# endif
4690 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4691 if (cRefs == 1)
4692 {
4693 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4694 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4695 }
4696 else
4697 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4698 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4699}
4700#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4701
4702
4703#ifdef PGMPOOL_WITH_CACHE
4704/**
4705 * Moves the page to the head of the age list.
4706 *
4707 * This is done when the cached page is used in one way or another.
4708 *
4709 * @param pPool The pool.
4710 * @param pPage The cached page.
4711 * @todo inline in PGMInternal.h!
4712 */
4713DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4714{
4715 /*
4716 * Move to the head of the age list.
4717 */
4718 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4719 {
4720 /* unlink */
4721 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4722 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4723 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4724 else
4725 pPool->iAgeTail = pPage->iAgePrev;
4726
4727 /* insert at head */
4728 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4729 pPage->iAgeNext = pPool->iAgeHead;
4730 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4731 pPool->iAgeHead = pPage->idx;
4732 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4733 }
4734}
4735#endif /* PGMPOOL_WITH_CACHE */
4736
4737#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4738
4739/**
4740 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4741 *
4742 * @param pVM VM Handle.
4743 * @param pPage PGM pool page
4744 */
4745DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4746{
4747 Assert(!pPage->fLocked);
4748 pPage->fLocked = true;
4749}
4750
4751
4752/**
4753 * Unlocks a page to allow flushing again
4754 *
4755 * @param pVM VM Handle.
4756 * @param pPage PGM pool page
4757 */
4758DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4759{
4760 Assert(pPage->fLocked);
4761 pPage->fLocked = false;
4762}
4763
4764
4765/**
4766 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4767 *
4768 * @returns VBox status code.
4769 * @param pPage PGM pool page
4770 */
4771DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4772{
4773 if (pPage->fLocked)
4774 {
4775 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4776 if (pPage->cModifications)
4777 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4778 return true;
4779 }
4780 return false;
4781}
4782
4783#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4784
4785/**
4786 * Tells if mappings are to be put into the shadow page table or not
4787 *
4788 * @returns boolean result
4789 * @param pVM VM handle.
4790 */
4791DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4792{
4793#ifdef IN_RING0
4794 /* There are no mappings in VT-x and AMD-V mode. */
4795 Assert(pPGM->fDisableMappings);
4796 return false;
4797#else
4798 return !pPGM->fDisableMappings;
4799#endif
4800}
4801
4802/** @} */
4803
4804#endif
4805
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette