PGMInternal.h@ 18291

Last change on this file since 18291 was 18291, checked in by vboxsync, 16 years ago
PGM: Map PGMRAMRANGES above 4GB outside HMA (see defect). Changed PGMR3MapPT to take a flag indicating whether PGMR3UnmapPT will be used; this way we can select a more optimal allocation function for the ram ranges. PGMMapResolveConflicts: Walk the list correctly after reloc. pgmMapClearShadowPDEs: Don't clear PGM_PLXFLAGS_MAPPING when we shouldn't (odd PAE cases).
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File size: 191.0 KB

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1	/* $Id: PGMInternal.h 18291 2009-03-26 05:11:07Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/**
57	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58	* Comment it if it will break something.
59	*/
60	#define PGM_OUT_OF_SYNC_IN_GC
61
62	/**
63	* Check and skip global PDEs for non-global flushes
64	*/
65	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67	/**
68	* Sync N pages instead of a whole page table
69	*/
70	#define PGM_SYNC_N_PAGES
71
72	/**
73	* Number of pages to sync during a page fault
74	*
75	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77	*/
78	#define PGM_SYNC_NR_PAGES 8
79
80	/**
81	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82	*/
83	#define PGM_MAX_PHYSCACHE_ENTRIES 64
84	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86	/**
87	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88	*/
89	#define PGM_PHYSMEMACCESS_CACHING
90
91	/** @def PGMPOOL_WITH_CACHE
92	* Enable agressive caching using the page pool.
93	*
94	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95	*/
96	#define PGMPOOL_WITH_CACHE
97
98	/** @def PGMPOOL_WITH_MIXED_PT_CR3
99	* When defined, we'll deal with 'uncachable' pages.
100	*/
101	#ifdef PGMPOOL_WITH_CACHE
102	# define PGMPOOL_WITH_MIXED_PT_CR3
103	#endif
104
105	/** @def PGMPOOL_WITH_MONITORING
106	* Monitor the guest pages which are shadowed.
107	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108	* be enabled as well.
109	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110	*/
111	#ifdef PGMPOOL_WITH_CACHE
112	# define PGMPOOL_WITH_MONITORING
113	#endif
114
115	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116	* Tracking the of shadow pages mapping guest physical pages.
117	*
118	* This is very expensive, the current cache prototype is trying to figure out
119	* whether it will be acceptable with an agressive caching policy.
120	*/
121	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
122	# define PGMPOOL_WITH_GCPHYS_TRACKING
123	#endif
124
125	/** @def PGMPOOL_WITH_USER_TRACKING
126	* Tracking users of shadow pages. This is required for the linking of shadow page
127	* tables and physical guest addresses.
128	*/
129	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
130	# define PGMPOOL_WITH_USER_TRACKING
131	#endif
132
133	/** @def PGMPOOL_CFG_MAX_GROW
134	* The maximum number of pages to add to the pool in one go.
135	*/
136	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
140	*/
141	#ifdef VBOX_STRICT
142	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143	#endif
144
145	#ifdef VBOX_WITH_NEW_PHYS_CODE
146	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
147	* Enables the experimental lazy page allocation code. */
148	/# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
149	#endif
150	/** @} */
151
152
153	/** @name PDPT and PML4 flags.
154	* These are placed in the three bits available for system programs in
155	* the PDPT and PML4 entries.
156	* @{ */
157	/** The entry is a permanent one and it's must always be present.
158	* Never free such an entry. */
159	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
160	/** Mapping (hypervisor allocated pagetable). */
161	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
162	/** @} */
163
164	/** @name Page directory flags.
165	* These are placed in the three bits available for system programs in
166	* the page directory entries.
167	* @{ */
168	/** Mapping (hypervisor allocated pagetable). */
169	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
170	/** Made read-only to facilitate dirty bit tracking. */
171	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
172	/** @} */
173
174	/** @name Page flags.
175	* These are placed in the three bits available for system programs in
176	* the page entries.
177	* @{ */
178	/** Made read-only to facilitate dirty bit tracking. */
179	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
180
181	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
182	/** Scanned and approved by CSAM (tm).
183	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
184	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
185	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
186	#endif
187
188	/** @} */
189
190	/** @name Defines used to indicate the shadow and guest paging in the templates.
191	* @{ */
192	#define PGM_TYPE_REAL 1
193	#define PGM_TYPE_PROT 2
194	#define PGM_TYPE_32BIT 3
195	#define PGM_TYPE_PAE 4
196	#define PGM_TYPE_AMD64 5
197	#define PGM_TYPE_NESTED 6
198	#define PGM_TYPE_EPT 7
199	#define PGM_TYPE_MAX PGM_TYPE_EPT
200	/** @} */
201
202	/** Macro for checking if the guest is using paging.
203	* @param uGstType PGM_TYPE_*
204	* @param uShwType PGM_TYPE_*
205	* @remark ASSUMES certain order of the PGM_TYPE_* values.
206	*/
207	#define PGM_WITH_PAGING(uGstType, uShwType) \
208	( (uGstType) >= PGM_TYPE_32BIT \
209	&& (uShwType) != PGM_TYPE_NESTED \
210	&& (uShwType) != PGM_TYPE_EPT)
211
212	/** Macro for checking if the guest supports the NX bit.
213	* @param uGstType PGM_TYPE_*
214	* @param uShwType PGM_TYPE_*
215	* @remark ASSUMES certain order of the PGM_TYPE_* values.
216	*/
217	#define PGM_WITH_NX(uGstType, uShwType) \
218	( (uGstType) >= PGM_TYPE_PAE \
219	&& (uShwType) != PGM_TYPE_NESTED \
220	&& (uShwType) != PGM_TYPE_EPT)
221
222
223	/** @def PGM_HCPHYS_2_PTR
224	* Maps a HC physical page pool address to a virtual address.
225	*
226	* @returns VBox status code.
227	* @param pVM The VM handle.
228	* @param HCPhys The HC physical address to map to a virtual one.
229	* @param ppv Where to store the virtual address. No need to cast this.
230	*
231	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
232	* small page window employeed by that function. Be careful.
233	* @remark There is no need to assert on the result.
234	*/
235	#ifdef IN_RC
236	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
237	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
238	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
239	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
240	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
241	#else
242	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
243	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
244	#endif
245
246	/** @def PGM_HCPHYS_2_PTR_BY_PGM
247	* Maps a HC physical page pool address to a virtual address.
248	*
249	* @returns VBox status code.
250	* @param pPGM The PGM instance data.
251	* @param HCPhys The HC physical address to map to a virtual one.
252	* @param ppv Where to store the virtual address. No need to cast this.
253	*
254	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
255	* small page window employeed by that function. Be careful.
256	* @remark There is no need to assert on the result.
257	*/
258	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
259	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
260	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
261	#else
262	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
263	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
264	#endif
265
266	/** @def PGM_GCPHYS_2_PTR
267	* Maps a GC physical page address to a virtual address.
268	*
269	* @returns VBox status code.
270	* @param pVM The VM handle.
271	* @param GCPhys The GC physical address to map to a virtual one.
272	* @param ppv Where to store the virtual address. No need to cast this.
273	*
274	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
275	* small page window employeed by that function. Be careful.
276	* @remark There is no need to assert on the result.
277	*/
278	#ifdef IN_RC
279	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
280	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
281	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
282	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
283	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
284	#else
285	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
286	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
287	#endif
288
289	/** @def PGM_GCPHYS_2_PTR_BY_PGM
290	* Maps a GC physical page address to a virtual address.
291	*
292	* @returns VBox status code.
293	* @param pPGM Pointer to the PGM instance data.
294	* @param GCPhys The GC physical address to map to a virtual one.
295	* @param ppv Where to store the virtual address. No need to cast this.
296	*
297	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
298	* small page window employeed by that function. Be careful.
299	* @remark There is no need to assert on the result.
300	*/
301	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
302	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
303	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
304	#else
305	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
306	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
307	#endif
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM The VM handle.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
318	* small page window employeed by that function. Be careful.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
327	#endif
328
329	/** @def PGM_INVL_PG
330	* Invalidates a page when in GC does nothing in HC.
331	*
332	* @param GCVirt The virtual address of the page to invalidate.
333	*/
334	#ifdef IN_RC
335	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
336	#elif defined(IN_RING0)
337	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
338	#else
339	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340	#endif
341
342	/** @def PGM_INVL_BIG_PG
343	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
344	*
345	* @param GCVirt The virtual address within the page directory to invalidate.
346	*/
347	#ifdef IN_RC
348	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
349	#elif defined(IN_RING0)
350	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
351	#else
352	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353	#endif
354
355	/** @def PGM_INVL_GUEST_TLBS()
356	* Invalidates all guest TLBs.
357	*/
358	#ifdef IN_RC
359	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
360	#elif defined(IN_RING0)
361	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
362	#else
363	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364	#endif
365
366	/** Size of the GCPtrConflict array in PGMMAPPING.
367	* @remarks Must be a power of two. */
368	#define PGMMAPPING_CONFLICT_MAX 8
369
370	/**
371	* Structure for tracking GC Mappings.
372	*
373	* This structure is used by linked list in both GC and HC.
374	*/
375	typedef struct PGMMAPPING
376	{
377	/** Pointer to next entry. */
378	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
379	/** Pointer to next entry. */
380	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
381	/** Pointer to next entry. */
382	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
383	/** Indicate whether this entry is finalized. */
384	bool fFinalized;
385	/** Start Virtual address. */
386	RTGCPTR GCPtr;
387	/** Last Virtual address (inclusive). */
388	RTGCPTR GCPtrLast;
389	/** Range size (bytes). */
390	RTGCPTR cb;
391	/** Pointer to relocation callback function. */
392	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
393	/** User argument to the callback. */
394	R3PTRTYPE(void *) pvUser;
395	/** Mapping description / name. For easing debugging. */
396	R3PTRTYPE(const char *) pszDesc;
397	/** Last 8 addresses that caused conflicts. */
398	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
399	/** Number of conflicts for this hypervisor mapping. */
400	uint32_t cConflicts;
401	/** Number of page tables. */
402	uint32_t cPTs;
403
404	/** Array of page table mapping data. Each entry
405	* describes one page table. The array can be longer
406	* than the declared length.
407	*/
408	struct
409	{
410	/** The HC physical address of the page table. */
411	RTHCPHYS HCPhysPT;
412	/** The HC physical address of the first PAE page table. */
413	RTHCPHYS HCPhysPaePT0;
414	/** The HC physical address of the second PAE page table. */
415	RTHCPHYS HCPhysPaePT1;
416	/** The HC virtual address of the 32-bit page table. */
417	R3PTRTYPE(PX86PT) pPTR3;
418	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
419	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
420	/** The GC virtual address of the 32-bit page table. */
421	RCPTRTYPE(PX86PT) pPTRC;
422	/** The GC virtual address of the two PAE page table. */
423	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
424	/** The GC virtual address of the 32-bit page table. */
425	R0PTRTYPE(PX86PT) pPTR0;
426	/** The GC virtual address of the two PAE page table. */
427	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
428	} aPTs[1];
429	} PGMMAPPING;
430	/** Pointer to structure for tracking GC Mappings. */
431	typedef struct PGMMAPPING *PPGMMAPPING;
432
433
434	/**
435	* Physical page access handler structure.
436	*
437	* This is used to keep track of physical address ranges
438	* which are being monitored in some kind of way.
439	*/
440	typedef struct PGMPHYSHANDLER
441	{
442	AVLROGCPHYSNODECORE Core;
443	/** Access type. */
444	PGMPHYSHANDLERTYPE enmType;
445	/** Number of pages to update. */
446	uint32_t cPages;
447	/** Pointer to R3 callback function. */
448	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
449	/** User argument for R3 handlers. */
450	R3PTRTYPE(void *) pvUserR3;
451	/** Pointer to R0 callback function. */
452	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
453	/** User argument for R0 handlers. */
454	R0PTRTYPE(void *) pvUserR0;
455	/** Pointer to GC callback function. */
456	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
457	/** User argument for RC handlers. */
458	RCPTRTYPE(void *) pvUserRC;
459	/** Description / Name. For easing debugging. */
460	R3PTRTYPE(const char *) pszDesc;
461	#ifdef VBOX_WITH_STATISTICS
462	/** Profiling of this handler. */
463	STAMPROFILE Stat;
464	#endif
465	} PGMPHYSHANDLER;
466	/** Pointer to a physical page access handler structure. */
467	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
468
469
470	/**
471	* Cache node for the physical addresses covered by a virtual handler.
472	*/
473	typedef struct PGMPHYS2VIRTHANDLER
474	{
475	/** Core node for the tree based on physical ranges. */
476	AVLROGCPHYSNODECORE Core;
477	/** Offset from this struct to the PGMVIRTHANDLER structure. */
478	int32_t offVirtHandler;
479	/** Offset of the next alias relative to this one.
480	* Bit 0 is used for indicating whether we're in the tree.
481	* Bit 1 is used for indicating that we're the head node.
482	*/
483	int32_t offNextAlias;
484	} PGMPHYS2VIRTHANDLER;
485	/** Pointer to a phys to virtual handler structure. */
486	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
487
488	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489	* node is in the tree. */
490	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
491	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
492	* node is in the head of an alias chain.
493	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
494	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
495	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
496	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
497
498
499	/**
500	* Virtual page access handler structure.
501	*
502	* This is used to keep track of virtual address ranges
503	* which are being monitored in some kind of way.
504	*/
505	typedef struct PGMVIRTHANDLER
506	{
507	/** Core node for the tree based on virtual ranges. */
508	AVLROGCPTRNODECORE Core;
509	/** Size of the range (in bytes). */
510	RTGCPTR cb;
511	/** Number of cache pages. */
512	uint32_t cPages;
513	/** Access type. */
514	PGMVIRTHANDLERTYPE enmType;
515	/** Pointer to the RC callback function. */
516	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
517	#if HC_ARCH_BITS == 64
518	RTRCPTR padding;
519	#endif
520	/** Pointer to the R3 callback function for invalidation. */
521	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
522	/** Pointer to the R3 callback function. */
523	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
524	/** Description / Name. For easing debugging. */
525	R3PTRTYPE(const char *) pszDesc;
526	#ifdef VBOX_WITH_STATISTICS
527	/** Profiling of this handler. */
528	STAMPROFILE Stat;
529	#endif
530	/** Array of cached physical addresses for the monitored ranged. */
531	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
532	} PGMVIRTHANDLER;
533	/** Pointer to a virtual page access handler structure. */
534	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
535
536
537	/**
538	* Page type.
539	*
540	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
541	* @remarks This is used in the saved state, so changes to it requires bumping
542	* the saved state version.
543	* @todo So, convert to \#defines!
544	*/
545	typedef enum PGMPAGETYPE
546	{
547	/** The usual invalid zero entry. */
548	PGMPAGETYPE_INVALID = 0,
549	/** RAM page. (RWX) */
550	PGMPAGETYPE_RAM,
551	/** MMIO2 page. (RWX) */
552	PGMPAGETYPE_MMIO2,
553	/** MMIO2 page aliased over an MMIO page. (RWX)
554	* See PGMHandlerPhysicalPageAlias(). */
555	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
556	/** Shadowed ROM. (RWX) */
557	PGMPAGETYPE_ROM_SHADOW,
558	/** ROM page. (R-X) */
559	PGMPAGETYPE_ROM,
560	/** MMIO page. (---) */
561	PGMPAGETYPE_MMIO,
562	/** End of valid entries. */
563	PGMPAGETYPE_END
564	} PGMPAGETYPE;
565	AssertCompile(PGMPAGETYPE_END <= 7);
566
567	/** @name Page type predicates.
568	* @{ */
569	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
570	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
571	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
572	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
573	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
574	/** @} */
575
576
577	/**
578	* A Physical Guest Page tracking structure.
579	*
580	* The format of this structure is complicated because we have to fit a lot
581	* of information into as few bits as possible. The format is also subject
582	* to change (there is one comming up soon). Which means that for we'll be
583	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
584	* accessess to the structure.
585	*/
586	typedef struct PGMPAGE
587	{
588	/** The physical address and a whole lot of other stuff. All bits are used! */
589	#ifdef VBOX_WITH_NEW_PHYS_CODE
590	RTHCPHYS HCPhysX;
591	#else
592	RTHCPHYS HCPhys;
593	#define HCPhysX HCPhys /*< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. /
594	#endif
595	/** The page state. */
596	uint32_t u2StateX : 2;
597	/** Flag indicating that a write monitored page was written to when set. */
598	uint32_t fWrittenToX : 1;
599	/** For later. */
600	uint32_t fSomethingElse : 1;
601	/** The Page ID.
602	* @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
603	* The HCPhysX will then be 100% static. */
604	uint32_t idPageX : 28;
605	/** The page type (PGMPAGETYPE). */
606	uint32_t u3Type : 3;
607	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
608	uint32_t u2HandlerPhysStateX : 2;
609	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
610	uint32_t u2HandlerVirtStateX : 2;
611	uint32_t u29B : 25;
612	} PGMPAGE;
613	AssertCompileSize(PGMPAGE, 16);
614	/** Pointer to a physical guest page. */
615	typedef PGMPAGE *PPGMPAGE;
616	/** Pointer to a const physical guest page. */
617	typedef const PGMPAGE *PCPGMPAGE;
618	/** Pointer to a physical guest page pointer. */
619	typedef PPGMPAGE *PPPGMPAGE;
620
621
622	/**
623	* Clears the page structure.
624	* @param pPage Pointer to the physical guest page tracking structure.
625	*/
626	#define PGM_PAGE_CLEAR(pPage) \
627	do { \
628	(pPage)->HCPhysX = 0; \
629	(pPage)->u2StateX = 0; \
630	(pPage)->fWrittenToX = 0; \
631	(pPage)->fSomethingElse = 0; \
632	(pPage)->idPageX = 0; \
633	(pPage)->u3Type = 0; \
634	(pPage)->u29B = 0; \
635	} while (0)
636
637	/**
638	* Initializes the page structure.
639	* @param pPage Pointer to the physical guest page tracking structure.
640	*/
641	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
642	do { \
643	(pPage)->HCPhysX = (_HCPhys); \
644	(pPage)->u2StateX = (_uState); \
645	(pPage)->fWrittenToX = 0; \
646	(pPage)->fSomethingElse = 0; \
647	(pPage)->idPageX = (_idPage); \
648	/(pPage)->u3Type = (_uType); - later / \
649	PGM_PAGE_SET_TYPE(pPage, _uType); \
650	(pPage)->u29B = 0; \
651	} while (0)
652
653	/**
654	* Initializes the page structure of a ZERO page.
655	* @param pPage Pointer to the physical guest page tracking structure.
656	*/
657	#ifdef VBOX_WITH_NEW_PHYS_CODE
658	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
659	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
660	#else
661	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
662	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
663	#endif
664	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
665	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
666	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
667
668
669	/** @name The Page state, PGMPAGE::u2StateX.
670	* @{ */
671	/** The zero page.
672	* This is a per-VM page that's never ever mapped writable. */
673	#define PGM_PAGE_STATE_ZERO 0
674	/** A allocated page.
675	* This is a per-VM page allocated from the page pool (or wherever
676	* we get MMIO2 pages from if the type is MMIO2).
677	*/
678	#define PGM_PAGE_STATE_ALLOCATED 1
679	/** A allocated page that's being monitored for writes.
680	* The shadow page table mappings are read-only. When a write occurs, the
681	* fWrittenTo member is set, the page remapped as read-write and the state
682	* moved back to allocated. */
683	#define PGM_PAGE_STATE_WRITE_MONITORED 2
684	/** The page is shared, aka. copy-on-write.
685	* This is a page that's shared with other VMs. */
686	#define PGM_PAGE_STATE_SHARED 3
687	/** @} */
688
689
690	/**
691	* Gets the page state.
692	* @returns page state (PGM_PAGE_STATE_*).
693	* @param pPage Pointer to the physical guest page tracking structure.
694	*/
695	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
696
697	/**
698	* Sets the page state.
699	* @param pPage Pointer to the physical guest page tracking structure.
700	* @param _uState The new page state.
701	*/
702	#define PGM_PAGE_SET_STATE(pPage, _uState) \
703	do { (pPage)->u2StateX = (_uState); } while (0)
704
705
706	/**
707	* Gets the host physical address of the guest page.
708	* @returns host physical address (RTHCPHYS).
709	* @param pPage Pointer to the physical guest page tracking structure.
710	*/
711	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
712
713	/**
714	* Sets the host physical address of the guest page.
715	* @param pPage Pointer to the physical guest page tracking structure.
716	* @param _HCPhys The new host physical address.
717	*/
718	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
719	do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
720	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
721
722	/**
723	* Get the Page ID.
724	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
725	* @param pPage Pointer to the physical guest page tracking structure.
726	*/
727	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
728	/* later:
729	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
730	\| ((uint32_t)(pPage)->HCPhysX & 0xfff) )
731	*/
732	/**
733	* Sets the Page ID.
734	* @param pPage Pointer to the physical guest page tracking structure.
735	*/
736	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
737	/* later:
738	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
739	\| ((_idPage) & 0xfff) \
740	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
741	*/
742
743	/**
744	* Get the Chunk ID.
745	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
746	* @param pPage Pointer to the physical guest page tracking structure.
747	*/
748	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
749	/* later:
750	#if GMM_CHUNKID_SHIFT == 12
751	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
752	#elif GMM_CHUNKID_SHIFT > 12
753	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
754	#elif GMM_CHUNKID_SHIFT < 12
755	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
756	\| ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
757	#else
758	# error "GMM_CHUNKID_SHIFT isn't defined or something."
759	#endif
760	*/
761
762	/**
763	* Get the index of the page within the allocaiton chunk.
764	* @returns The page index.
765	* @param pPage Pointer to the physical guest page tracking structure.
766	*/
767	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
768	/* later:
769	#if GMM_CHUNKID_SHIFT <= 12
770	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
771	#else
772	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
773	\| ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
774	#endif
775	*/
776
777
778	/**
779	* Gets the page type.
780	* @returns The page type.
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
784
785	/**
786	* Sets the page type.
787	* @param pPage Pointer to the physical guest page tracking structure.
788	* @param _enmType The new page type (PGMPAGETYPE).
789	*/
790	#ifdef VBOX_WITH_NEW_PHYS_CODE
791	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
792	do { (pPage)->u3Type = (_enmType); } while (0)
793	#else
794	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
795	do { \
796	(pPage)->u3Type = (_enmType); \
797	if ((_enmType) == PGMPAGETYPE_ROM) \
798	(pPage)->HCPhysX \|= MM_RAM_FLAGS_ROM; \
799	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
800	(pPage)->HCPhysX \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
801	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
802	(pPage)->HCPhysX \|= MM_RAM_FLAGS_MMIO2; \
803	} while (0)
804	#endif
805
806
807	/**
808	* Checks if the page is 'reserved'.
809	* @returns true/false.
810	* @param pPage Pointer to the physical guest page tracking structure.
811	*/
812	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
813
814	/**
815	* Checks if the page is marked for MMIO.
816	* @returns true/false.
817	* @param pPage Pointer to the physical guest page tracking structure.
818	*/
819	#ifdef VBOX_WITH_NEW_PHYS_CODE
820	# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
821	#else
822	# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
823	#endif
824
825	/**
826	* Checks if the page is backed by the ZERO page.
827	* @returns true/false.
828	* @param pPage Pointer to the physical guest page tracking structure.
829	*/
830	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
831
832	/**
833	* Checks if the page is backed by a SHARED page.
834	* @returns true/false.
835	* @param pPage Pointer to the physical guest page tracking structure.
836	*/
837	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
838
839
840	/**
841	* Marks the paget as written to (for GMM change monitoring).
842	* @param pPage Pointer to the physical guest page tracking structure.
843	*/
844	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
845
846	/**
847	* Clears the written-to indicator.
848	* @param pPage Pointer to the physical guest page tracking structure.
849	*/
850	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
851
852	/**
853	* Checks if the page was marked as written-to.
854	* @returns true/false.
855	* @param pPage Pointer to the physical guest page tracking structure.
856	*/
857	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
858
859
860	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
861	*
862	* @remarks The values are assigned in order of priority, so we can calculate
863	* the correct state for a page with different handlers installed.
864	* @{ */
865	/** No handler installed. */
866	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
867	/** Monitoring is temporarily disabled. */
868	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
869	/** Write access is monitored. */
870	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
871	/** All access is monitored. */
872	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
873	/** @} */
874
875	/**
876	* Gets the physical access handler state of a page.
877	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
878	* @param pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
881
882	/**
883	* Sets the physical access handler state of a page.
884	* @param pPage Pointer to the physical guest page tracking structure.
885	* @param _uState The new state value.
886	*/
887	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
888	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
889
890	/**
891	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
892	* @returns true/false
893	* @param pPage Pointer to the physical guest page tracking structure.
894	*/
895	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
896
897	/**
898	* Checks if the page has any active physical access handlers.
899	* @returns true/false
900	* @param pPage Pointer to the physical guest page tracking structure.
901	*/
902	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
903
904
905	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
906	*
907	* @remarks The values are assigned in order of priority, so we can calculate
908	* the correct state for a page with different handlers installed.
909	* @{ */
910	/** No handler installed. */
911	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
912	/* 1 is reserved so the lineup is identical with the physical ones. */
913	/** Write access is monitored. */
914	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
915	/** All access is monitored. */
916	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
917	/** @} */
918
919	/**
920	* Gets the virtual access handler state of a page.
921	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
922	* @param pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
925
926	/**
927	* Sets the virtual access handler state of a page.
928	* @param pPage Pointer to the physical guest page tracking structure.
929	* @param _uState The new state value.
930	*/
931	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
932	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
933
934	/**
935	* Checks if the page has any virtual access handlers.
936	* @returns true/false
937	* @param pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
940
941	/**
942	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
943	* virtual handlers.
944	* @returns true/false
945	* @param pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
948
949
950
951	/**
952	* Checks if the page has any access handlers, including temporarily disabled ones.
953	* @returns true/false
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
957	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
958	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
959
960	/**
961	* Checks if the page has any active access handlers.
962	* @returns true/false
963	* @param pPage Pointer to the physical guest page tracking structure.
964	*/
965	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
966	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
967	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
968
969	/**
970	* Checks if the page has any active access handlers catching all accesses.
971	* @returns true/false
972	* @param pPage Pointer to the physical guest page tracking structure.
973	*/
974	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
975	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
976	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
977
978
979
980
981	/** @def PGM_PAGE_GET_TRACKING
982	* Gets the packed shadow page pool tracking data associated with a guest page.
983	* @returns uint16_t containing the data.
984	* @param pPage Pointer to the physical guest page tracking structure.
985	*/
986	#define PGM_PAGE_GET_TRACKING(pPage) \
987	( ((uint16_t )&(pPage)->HCPhysX + 3) )
988
989	/** @def PGM_PAGE_SET_TRACKING
990	* Sets the packed shadow page pool tracking data associated with a guest page.
991	* @param pPage Pointer to the physical guest page tracking structure.
992	* @param u16TrackingData The tracking data to store.
993	*/
994	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
995	do { ((uint16_t )&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
996
997	/** @def PGM_PAGE_GET_TD_CREFS
998	* Gets the @a cRefs tracking data member.
999	* @returns cRefs.
1000	* @param pPage Pointer to the physical guest page tracking structure.
1001	*/
1002	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1003	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1004
1005	#define PGM_PAGE_GET_TD_IDX(pPage) \
1006	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1007
1008	/**
1009	* Ram range for GC Phys to HC Phys conversion.
1010	*
1011	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1012	* conversions too, but we'll let MM handle that for now.
1013	*
1014	* This structure is used by linked lists in both GC and HC.
1015	*/
1016	typedef struct PGMRAMRANGE
1017	{
1018	/** Start of the range. Page aligned. */
1019	RTGCPHYS GCPhys;
1020	/** Size of the range. (Page aligned of course). */
1021	RTGCPHYS cb;
1022	/** Pointer to the next RAM range - for R3. */
1023	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1024	/** Pointer to the next RAM range - for R0. */
1025	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1026	/** Pointer to the next RAM range - for RC. */
1027	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1028	/** PGM_RAM_RANGE_FLAGS_* flags. */
1029	uint32_t fFlags;
1030	/** Last address in the range (inclusive). Page aligned (-1). */
1031	RTGCPHYS GCPhysLast;
1032	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1033	R3PTRTYPE(void *) pvR3;
1034	#ifndef VBOX_WITH_NEW_PHYS_CODE
1035	/** R3 virtual lookup ranges for chunks.
1036	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1037	* @remarks This is occationally accessed from ring-0!! (not darwin) */
1038	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1039	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1040	# else
1041	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1042	# endif
1043	#endif
1044	/** The range description. */
1045	R3PTRTYPE(const char *) pszDesc;
1046	/** Pointer to self - R0 pointer. */
1047	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1048	/** Pointer to self - RC pointer. */
1049	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1050	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1051	#if HC_ARCH_BITS == (defined(VBOX_WITH_NEW_PHYS_CODE) ? 64 : 32)
1052	uint32_t u32Alignment2;
1053	#endif
1054	/** Array of physical guest page tracking structures. */
1055	PGMPAGE aPages[1];
1056	} PGMRAMRANGE;
1057	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1058	typedef PGMRAMRANGE *PPGMRAMRANGE;
1059
1060	#ifdef VBOX_WITH_NEW_PHYS_CODE
1061	/** @name PGMRAMRANGE::fFlags
1062	* @{ */
1063	/** The RAM range is floating around as an independent guest mapping. */
1064	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1065	/** @} */
1066	#else
1067	/** Return hc ptr corresponding to the ram range and physical offset */
1068	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1069	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1070	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1071	#endif
1072
1073	/**
1074	* Per page tracking structure for ROM image.
1075	*
1076	* A ROM image may have a shadow page, in which case we may have
1077	* two pages backing it. This structure contains the PGMPAGE for
1078	* both while PGMRAMRANGE have a copy of the active one. It is
1079	* important that these aren't out of sync in any regard other
1080	* than page pool tracking data.
1081	*/
1082	typedef struct PGMROMPAGE
1083	{
1084	/** The page structure for the virgin ROM page. */
1085	PGMPAGE Virgin;
1086	/** The page structure for the shadow RAM page. */
1087	PGMPAGE Shadow;
1088	/** The current protection setting. */
1089	PGMROMPROT enmProt;
1090	/** Pad the structure size to a multiple of 8. */
1091	uint32_t u32Padding;
1092	} PGMROMPAGE;
1093	/** Pointer to a ROM page tracking structure. */
1094	typedef PGMROMPAGE *PPGMROMPAGE;
1095
1096
1097	/**
1098	* A registered ROM image.
1099	*
1100	* This is needed to keep track of ROM image since they generally
1101	* intrude into a PGMRAMRANGE. It also keeps track of additional
1102	* info like the two page sets (read-only virgin and read-write shadow),
1103	* the current state of each page.
1104	*
1105	* Because access handlers cannot easily be executed in a different
1106	* context, the ROM ranges needs to be accessible and in all contexts.
1107	*/
1108	typedef struct PGMROMRANGE
1109	{
1110	/** Pointer to the next range - R3. */
1111	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1112	/** Pointer to the next range - R0. */
1113	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1114	/** Pointer to the next range - RC. */
1115	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1116	/** Pointer alignment */
1117	RTRCPTR GCPtrAlignment;
1118	/** Address of the range. */
1119	RTGCPHYS GCPhys;
1120	/** Address of the last byte in the range. */
1121	RTGCPHYS GCPhysLast;
1122	/** Size of the range. */
1123	RTGCPHYS cb;
1124	/** The flags (PGMPHYS_ROM_FLAG_). /
1125	uint32_t fFlags;
1126	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1127	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1128	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1129	* This is used for strictness checks. */
1130	R3PTRTYPE(const void *) pvOriginal;
1131	/** The ROM description. */
1132	R3PTRTYPE(const char *) pszDesc;
1133	/** The per page tracking structures. */
1134	PGMROMPAGE aPages[1];
1135	} PGMROMRANGE;
1136	/** Pointer to a ROM range. */
1137	typedef PGMROMRANGE *PPGMROMRANGE;
1138
1139
1140	/**
1141	* A registered MMIO2 (= Device RAM) range.
1142	*
1143	* There are a few reason why we need to keep track of these
1144	* registrations. One of them is the deregistration & cleanup
1145	* stuff, while another is that the PGMRAMRANGE associated with
1146	* such a region may have to be removed from the ram range list.
1147	*
1148	* Overlapping with a RAM range has to be 100% or none at all. The
1149	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1150	* meditation will be raised if a partial overlap or an overlap of
1151	* ROM pages is encountered. On an overlap we will free all the
1152	* existing RAM pages and put in the ram range pages instead.
1153	*/
1154	typedef struct PGMMMIO2RANGE
1155	{
1156	/** The owner of the range. (a device) */
1157	PPDMDEVINSR3 pDevInsR3;
1158	/** Pointer to the ring-3 mapping of the allocation. */
1159	RTR3PTR pvR3;
1160	/** Pointer to the next range - R3. */
1161	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1162	/** Whether it's mapped or not. */
1163	bool fMapped;
1164	/** Whether it's overlapping or not. */
1165	bool fOverlapping;
1166	/** The PCI region number.
1167	* @remarks This ASSUMES that nobody will ever really need to have multiple
1168	* PCI devices with matching MMIO region numbers on a single device. */
1169	uint8_t iRegion;
1170	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1171	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1172	/** The associated RAM range. */
1173	PGMRAMRANGE RamRange;
1174	} PGMMMIO2RANGE;
1175	/** Pointer to a MMIO2 range. */
1176	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1177
1178
1179
1180
1181	/**
1182	* PGMPhysRead/Write cache entry
1183	*/
1184	typedef struct PGMPHYSCACHEENTRY
1185	{
1186	/** R3 pointer to physical page. */
1187	R3PTRTYPE(uint8_t *) pbR3;
1188	/** GC Physical address for cache entry */
1189	RTGCPHYS GCPhys;
1190	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1191	RTGCPHYS u32Padding0; /*< alignment padding. /
1192	#endif
1193	} PGMPHYSCACHEENTRY;
1194
1195	/**
1196	* PGMPhysRead/Write cache to reduce REM memory access overhead
1197	*/
1198	typedef struct PGMPHYSCACHE
1199	{
1200	/** Bitmap of valid cache entries */
1201	uint64_t aEntries;
1202	/** Cache entries */
1203	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1204	} PGMPHYSCACHE;
1205
1206
1207	/** Pointer to an allocation chunk ring-3 mapping. */
1208	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1209	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1210	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1211
1212	/**
1213	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1214	*
1215	* The primary tree (Core) uses the chunk id as key.
1216	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1217	*/
1218	typedef struct PGMCHUNKR3MAP
1219	{
1220	/** The key is the chunk id. */
1221	AVLU32NODECORE Core;
1222	/** The key is the ageing sequence number. */
1223	AVLLU32NODECORE AgeCore;
1224	/** The current age thingy. */
1225	uint32_t iAge;
1226	/** The current reference count. */
1227	uint32_t volatile cRefs;
1228	/** The current permanent reference count. */
1229	uint32_t volatile cPermRefs;
1230	/** The mapping address. */
1231	void *pv;
1232	} PGMCHUNKR3MAP;
1233
1234	/**
1235	* Allocation chunk ring-3 mapping TLB entry.
1236	*/
1237	typedef struct PGMCHUNKR3MAPTLBE
1238	{
1239	/** The chunk id. */
1240	uint32_t volatile idChunk;
1241	#if HC_ARCH_BITS == 64
1242	uint32_t u32Padding; /*< alignment padding. /
1243	#endif
1244	/** The chunk map. */
1245	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1246	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1247	#else
1248	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1249	#endif
1250	} PGMCHUNKR3MAPTLBE;
1251	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1252	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1253
1254	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1255	* @remark Must be a power of two value. */
1256	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1257
1258	/**
1259	* Allocation chunk ring-3 mapping TLB.
1260	*
1261	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1262	* At first glance this might look kinda odd since AVL trees are
1263	* supposed to give the most optimial lookup times of all trees
1264	* due to their balancing. However, take a tree with 1023 nodes
1265	* in it, that's 10 levels, meaning that most searches has to go
1266	* down 9 levels before they find what they want. This isn't fast
1267	* compared to a TLB hit. There is the factor of cache misses,
1268	* and of course the problem with trees and branch prediction.
1269	* This is why we use TLBs in front of most of the trees.
1270	*
1271	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1272	* difficult when we switch to the new inlined AVL trees (from kStuff).
1273	*/
1274	typedef struct PGMCHUNKR3MAPTLB
1275	{
1276	/** The TLB entries. */
1277	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1278	} PGMCHUNKR3MAPTLB;
1279
1280	/**
1281	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1282	* @returns Chunk TLB index.
1283	* @param idChunk The Chunk ID.
1284	*/
1285	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1286
1287
1288	/**
1289	* Ring-3 guest page mapping TLB entry.
1290	* @remarks used in ring-0 as well at the moment.
1291	*/
1292	typedef struct PGMPAGER3MAPTLBE
1293	{
1294	/** Address of the page. */
1295	RTGCPHYS volatile GCPhys;
1296	/** The guest page. */
1297	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1298	R3PTRTYPE(PPGMPAGE) volatile pPage;
1299	#else
1300	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1301	#endif
1302	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1303	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1304	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1305	#else
1306	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1307	#endif
1308	/** The address */
1309	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1310	R3PTRTYPE(void *) volatile pv;
1311	#else
1312	R3R0PTRTYPE(void *) volatile pv;
1313	#endif
1314	#if HC_ARCH_BITS == 32
1315	uint32_t u32Padding; /*< alignment padding. /
1316	#endif
1317	} PGMPAGER3MAPTLBE;
1318	/** Pointer to an entry in the HC physical TLB. */
1319	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1320
1321
1322	/** The number of entries in the ring-3 guest page mapping TLB.
1323	* @remarks The value must be a power of two. */
1324	#define PGM_PAGER3MAPTLB_ENTRIES 64
1325
1326	/**
1327	* Ring-3 guest page mapping TLB.
1328	* @remarks used in ring-0 as well at the moment.
1329	*/
1330	typedef struct PGMPAGER3MAPTLB
1331	{
1332	/** The TLB entries. */
1333	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1334	} PGMPAGER3MAPTLB;
1335	/** Pointer to the ring-3 guest page mapping TLB. */
1336	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1337
1338	/**
1339	* Calculates the index of the TLB entry for the specified guest page.
1340	* @returns Physical TLB index.
1341	* @param GCPhys The guest physical address.
1342	*/
1343	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1344
1345
1346	/**
1347	* Mapping cache usage set entry.
1348	*
1349	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1350	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1351	* cache. If it's extended to include ring-3, well, then something will
1352	* have be changed here...
1353	*/
1354	typedef struct PGMMAPSETENTRY
1355	{
1356	/** The mapping cache index. */
1357	uint16_t iPage;
1358	/** The number of references.
1359	* The max is UINT16_MAX - 1. */
1360	uint16_t cRefs;
1361	/** Pointer to the page. */
1362	RTR0PTR pvPage;
1363	/** The physical address for this entry. */
1364	RTHCPHYS HCPhys;
1365	} PGMMAPSETENTRY;
1366	/** Pointer to a mapping cache usage set entry. */
1367	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1368
1369	/**
1370	* Mapping cache usage set.
1371	*
1372	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1373	* done during exits / traps. The set is
1374	*/
1375	typedef struct PGMMAPSET
1376	{
1377	/** The number of occupied entries.
1378	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1379	* dynamic mappings. */
1380	uint32_t cEntries;
1381	/** The start of the current subset.
1382	* This is UINT32_MAX if no subset is currently open. */
1383	uint32_t iSubset;
1384	/** The index of the current CPU, only valid if the set is open. */
1385	int32_t iCpu;
1386	/** The entries. */
1387	PGMMAPSETENTRY aEntries[64];
1388	/** HCPhys -> iEntry fast lookup table.
1389	* Use PGMMAPSET_HASH for hashing.
1390	* The entries may or may not be valid, check against cEntries. */
1391	uint8_t aiHashTable[128];
1392	} PGMMAPSET;
1393	/** Pointer to the mapping cache set. */
1394	typedef PGMMAPSET *PPGMMAPSET;
1395
1396	/** PGMMAPSET::cEntries value for a closed set. */
1397	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1398
1399	/** Hash function for aiHashTable. */
1400	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1401
1402	/** The max fill size (strict builds). */
1403	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1404
1405
1406	/** @name Context neutrual page mapper TLB.
1407	*
1408	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1409	* code is writting in a kind of context neutrual way. Time will show whether
1410	* this actually makes sense or not...
1411	*
1412	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1413	* context ends up using a global mapping cache on some platforms
1414	* (darwin).
1415	*
1416	* @{ */
1417	/** @typedef PPGMPAGEMAPTLB
1418	* The page mapper TLB pointer type for the current context. */
1419	/** @typedef PPGMPAGEMAPTLB
1420	* The page mapper TLB entry pointer type for the current context. */
1421	/** @typedef PPGMPAGEMAPTLB
1422	* The page mapper TLB entry pointer pointer type for the current context. */
1423	/** @def PGM_PAGEMAPTLB_ENTRIES
1424	* The number of TLB entries in the page mapper TLB for the current context. */
1425	/** @def PGM_PAGEMAPTLB_IDX
1426	* Calculate the TLB index for a guest physical address.
1427	* @returns The TLB index.
1428	* @param GCPhys The guest physical address. */
1429	/** @typedef PPGMPAGEMAP
1430	* Pointer to a page mapper unit for current context. */
1431	/** @typedef PPPGMPAGEMAP
1432	* Pointer to a page mapper unit pointer for current context. */
1433	#ifdef IN_RC
1434	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1435	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1436	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1437	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1438	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1439	typedef void * PPGMPAGEMAP;
1440	typedef void ** PPPGMPAGEMAP;
1441	//#elif IN_RING0
1442	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1443	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1444	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1445	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1446	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1447	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1448	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1449	#else
1450	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1451	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1452	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1453	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1454	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1455	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1456	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1457	#endif
1458	/** @} */
1459
1460
1461	/** @name PGM Pool Indexes.
1462	* Aka. the unique shadow page identifier.
1463	* @{ */
1464	/** NIL page pool IDX. */
1465	#define NIL_PGMPOOL_IDX 0
1466	/** The first normal index. */
1467	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1468	/** Page directory (32-bit root). */
1469	#define PGMPOOL_IDX_PD 1
1470	/** Page Directory Pointer Table (PAE root). */
1471	#define PGMPOOL_IDX_PDPT 2
1472	/** AMD64 CR3 level index.*/
1473	#define PGMPOOL_IDX_AMD64_CR3 3
1474	/** Nested paging root.*/
1475	#define PGMPOOL_IDX_NESTED_ROOT 4
1476	/** The first normal index. */
1477	#define PGMPOOL_IDX_FIRST 5
1478	/** The last valid index. (inclusive, 14 bits) */
1479	#define PGMPOOL_IDX_LAST 0x3fff
1480	/** @} */
1481
1482	/** The NIL index for the parent chain. */
1483	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1484
1485	/**
1486	* Node in the chain linking a shadowed page to it's parent (user).
1487	*/
1488	#pragma pack(1)
1489	typedef struct PGMPOOLUSER
1490	{
1491	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1492	uint16_t iNext;
1493	/** The user page index. */
1494	uint16_t iUser;
1495	/** Index into the user table. */
1496	uint32_t iUserTable;
1497	} PGMPOOLUSER, *PPGMPOOLUSER;
1498	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1499	#pragma pack()
1500
1501
1502	/** The NIL index for the phys ext chain. */
1503	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1504
1505	/**
1506	* Node in the chain of physical cross reference extents.
1507	* @todo Calling this an 'extent' is not quite right, find a better name.
1508	*/
1509	#pragma pack(1)
1510	typedef struct PGMPOOLPHYSEXT
1511	{
1512	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1513	uint16_t iNext;
1514	/** The user page index. */
1515	uint16_t aidx[3];
1516	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1517	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1518	#pragma pack()
1519
1520
1521	/**
1522	* The kind of page that's being shadowed.
1523	*/
1524	typedef enum PGMPOOLKIND
1525	{
1526	/** The virtual invalid 0 entry. */
1527	PGMPOOLKIND_INVALID = 0,
1528	/** The entry is free (=unused). */
1529	PGMPOOLKIND_FREE,
1530
1531	/** Shw: 32-bit page table; Gst: no paging */
1532	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1533	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1534	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1535	/** Shw: 32-bit page table; Gst: 4MB page. */
1536	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1537	/** Shw: PAE page table; Gst: no paging */
1538	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1539	/** Shw: PAE page table; Gst: 32-bit page table. */
1540	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1541	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1542	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1543	/** Shw: PAE page table; Gst: PAE page table. */
1544	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1545	/** Shw: PAE page table; Gst: 2MB page. */
1546	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1547
1548	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1549	PGMPOOLKIND_32BIT_PD,
1550	/** Shw: 32-bit page directory. Gst: no paging. */
1551	PGMPOOLKIND_32BIT_PD_PHYS,
1552	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1553	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1554	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1555	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1556	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1557	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1558	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1559	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1560	/** Shw: PAE page directory; Gst: PAE page directory. */
1561	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1562	/** Shw: PAE page directory; Gst: no paging. */
1563	PGMPOOLKIND_PAE_PD_PHYS,
1564
1565	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1566	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1567	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1568	PGMPOOLKIND_PAE_PDPT,
1569	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1570	PGMPOOLKIND_PAE_PDPT_PHYS,
1571
1572	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1573	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1574	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1575	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1576	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1577	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1578	/** Shw: 64-bit page directory table; Gst: no paging */
1579	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1580
1581	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1582	PGMPOOLKIND_64BIT_PML4,
1583
1584	/** Shw: EPT page directory pointer table; Gst: no paging */
1585	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1586	/** Shw: EPT page directory table; Gst: no paging */
1587	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1588	/** Shw: EPT page table; Gst: no paging */
1589	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1590
1591	/** Shw: Root Nested paging table. */
1592	PGMPOOLKIND_ROOT_NESTED,
1593
1594	/** The last valid entry. */
1595	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1596	} PGMPOOLKIND;
1597
1598
1599	/**
1600	* The tracking data for a page in the pool.
1601	*/
1602	typedef struct PGMPOOLPAGE
1603	{
1604	/** AVL node code with the (R3) physical address of this page. */
1605	AVLOHCPHYSNODECORE Core;
1606	/** Pointer to the R3 mapping of the page. */
1607	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1608	R3PTRTYPE(void *) pvPageR3;
1609	#else
1610	R3R0PTRTYPE(void *) pvPageR3;
1611	#endif
1612	/** The guest physical address. */
1613	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1614	uint32_t Alignment0;
1615	#endif
1616	RTGCPHYS GCPhys;
1617	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1618	uint8_t enmKind;
1619	uint8_t bPadding;
1620	/** The index of this page. */
1621	uint16_t idx;
1622	/** The next entry in the list this page currently resides in.
1623	* It's either in the free list or in the GCPhys hash. */
1624	uint16_t iNext;
1625	#ifdef PGMPOOL_WITH_USER_TRACKING
1626	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1627	uint16_t iUserHead;
1628	/** The number of present entries. */
1629	uint16_t cPresent;
1630	/** The first entry in the table which is present. */
1631	uint16_t iFirstPresent;
1632	#endif
1633	#ifdef PGMPOOL_WITH_MONITORING
1634	/** The number of modifications to the monitored page. */
1635	uint16_t cModifications;
1636	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1637	uint16_t iModifiedNext;
1638	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1639	uint16_t iModifiedPrev;
1640	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1641	uint16_t iMonitoredNext;
1642	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1643	uint16_t iMonitoredPrev;
1644	#endif
1645	#ifdef PGMPOOL_WITH_CACHE
1646	/** The next page in the age list. */
1647	uint16_t iAgeNext;
1648	/** The previous page in the age list. */
1649	uint16_t iAgePrev;
1650	#endif /* PGMPOOL_WITH_CACHE */
1651	/** Used to indicate that the page is zeroed. */
1652	bool fZeroed;
1653	/** Used to indicate that a PT has non-global entries. */
1654	bool fSeenNonGlobal;
1655	/** Used to indicate that we're monitoring writes to the guest page. */
1656	bool fMonitored;
1657	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1658	* (All pages are in the age list.) */
1659	bool fCached;
1660	/** This is used by the R3 access handlers when invoked by an async thread.
1661	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1662	bool volatile fReusedFlushPending;
1663	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1664	bool fLocked;
1665	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1666
1667
1668	#ifdef PGMPOOL_WITH_CACHE
1669	/** The hash table size. */
1670	# define PGMPOOL_HASH_SIZE 0x40
1671	/** The hash function. */
1672	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1673	#endif
1674
1675
1676	/**
1677	* The shadow page pool instance data.
1678	*
1679	* It's all one big allocation made at init time, except for the
1680	* pages that is. The user nodes follows immediatly after the
1681	* page structures.
1682	*/
1683	typedef struct PGMPOOL
1684	{
1685	/** The VM handle - R3 Ptr. */
1686	PVMR3 pVMR3;
1687	/** The VM handle - R0 Ptr. */
1688	PVMR0 pVMR0;
1689	/** The VM handle - RC Ptr. */
1690	PVMRC pVMRC;
1691	/** The max pool size. This includes the special IDs. */
1692	uint16_t cMaxPages;
1693	/** The current pool size. */
1694	uint16_t cCurPages;
1695	/** The head of the free page list. */
1696	uint16_t iFreeHead;
1697	/* Padding. */
1698	uint16_t u16Padding;
1699	#ifdef PGMPOOL_WITH_USER_TRACKING
1700	/** Head of the chain of free user nodes. */
1701	uint16_t iUserFreeHead;
1702	/** The number of user nodes we've allocated. */
1703	uint16_t cMaxUsers;
1704	/** The number of present page table entries in the entire pool. */
1705	uint32_t cPresent;
1706	/** Pointer to the array of user nodes - RC pointer. */
1707	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1708	/** Pointer to the array of user nodes - R3 pointer. */
1709	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1710	/** Pointer to the array of user nodes - R0 pointer. */
1711	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1712	#endif /* PGMPOOL_WITH_USER_TRACKING */
1713	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1714	/** Head of the chain of free phys ext nodes. */
1715	uint16_t iPhysExtFreeHead;
1716	/** The number of user nodes we've allocated. */
1717	uint16_t cMaxPhysExts;
1718	/** Pointer to the array of physical xref extent - RC pointer. */
1719	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1720	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1721	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1722	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1723	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1724	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1725	#ifdef PGMPOOL_WITH_CACHE
1726	/** Hash table for GCPhys addresses. */
1727	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1728	/** The head of the age list. */
1729	uint16_t iAgeHead;
1730	/** The tail of the age list. */
1731	uint16_t iAgeTail;
1732	/** Set if the cache is enabled. */
1733	bool fCacheEnabled;
1734	#endif /* PGMPOOL_WITH_CACHE */
1735	#ifdef PGMPOOL_WITH_MONITORING
1736	/** Head of the list of modified pages. */
1737	uint16_t iModifiedHead;
1738	/** The current number of modified pages. */
1739	uint16_t cModifiedPages;
1740	/** Access handler, RC. */
1741	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1742	/** Access handler, R0. */
1743	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1744	/** Access handler, R3. */
1745	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1746	/** The access handler description (HC ptr). */
1747	R3PTRTYPE(const char *) pszAccessHandler;
1748	#endif /* PGMPOOL_WITH_MONITORING */
1749	/** The number of pages currently in use. */
1750	uint16_t cUsedPages;
1751	#ifdef VBOX_WITH_STATISTICS
1752	/** The high wather mark for cUsedPages. */
1753	uint16_t cUsedPagesHigh;
1754	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1755	/** Profiling pgmPoolAlloc(). */
1756	STAMPROFILEADV StatAlloc;
1757	/** Profiling pgmPoolClearAll(). */
1758	STAMPROFILE StatClearAll;
1759	/** Profiling pgmPoolFlushAllInt(). */
1760	STAMPROFILE StatFlushAllInt;
1761	/** Profiling pgmPoolFlushPage(). */
1762	STAMPROFILE StatFlushPage;
1763	/** Profiling pgmPoolFree(). */
1764	STAMPROFILE StatFree;
1765	/** Profiling time spent zeroing pages. */
1766	STAMPROFILE StatZeroPage;
1767	# ifdef PGMPOOL_WITH_USER_TRACKING
1768	/** Profiling of pgmPoolTrackDeref. */
1769	STAMPROFILE StatTrackDeref;
1770	/** Profiling pgmTrackFlushGCPhysPT. */
1771	STAMPROFILE StatTrackFlushGCPhysPT;
1772	/** Profiling pgmTrackFlushGCPhysPTs. */
1773	STAMPROFILE StatTrackFlushGCPhysPTs;
1774	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1775	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1776	/** Number of times we've been out of user records. */
1777	STAMCOUNTER StatTrackFreeUpOneUser;
1778	# endif
1779	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1780	/** Profiling deref activity related tracking GC physical pages. */
1781	STAMPROFILE StatTrackDerefGCPhys;
1782	/** Number of linear searches for a HCPhys in the ram ranges. */
1783	STAMCOUNTER StatTrackLinearRamSearches;
1784	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1785	STAMCOUNTER StamTrackPhysExtAllocFailures;
1786	# endif
1787	# ifdef PGMPOOL_WITH_MONITORING
1788	/** Profiling the RC/R0 access handler. */
1789	STAMPROFILE StatMonitorRZ;
1790	/** Times we've failed interpreting the instruction. */
1791	STAMCOUNTER StatMonitorRZEmulateInstr;
1792	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1793	STAMPROFILE StatMonitorRZFlushPage;
1794	/** Times we've detected fork(). */
1795	STAMCOUNTER StatMonitorRZFork;
1796	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1797	STAMPROFILE StatMonitorRZHandled;
1798	/** Times we've failed interpreting a patch code instruction. */
1799	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1800	/** Times we've failed interpreting a patch code instruction during flushing. */
1801	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1802	/** The number of times we've seen rep prefixes we can't handle. */
1803	STAMCOUNTER StatMonitorRZRepPrefix;
1804	/** Profiling the REP STOSD cases we've handled. */
1805	STAMPROFILE StatMonitorRZRepStosd;
1806
1807	/** Profiling the R3 access handler. */
1808	STAMPROFILE StatMonitorR3;
1809	/** Times we've failed interpreting the instruction. */
1810	STAMCOUNTER StatMonitorR3EmulateInstr;
1811	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1812	STAMPROFILE StatMonitorR3FlushPage;
1813	/** Times we've detected fork(). */
1814	STAMCOUNTER StatMonitorR3Fork;
1815	/** Profiling the R3 access we've handled (except REP STOSD). */
1816	STAMPROFILE StatMonitorR3Handled;
1817	/** The number of times we've seen rep prefixes we can't handle. */
1818	STAMCOUNTER StatMonitorR3RepPrefix;
1819	/** Profiling the REP STOSD cases we've handled. */
1820	STAMPROFILE StatMonitorR3RepStosd;
1821	/** The number of times we're called in an async thread an need to flush. */
1822	STAMCOUNTER StatMonitorR3Async;
1823	/** The high wather mark for cModifiedPages. */
1824	uint16_t cModifiedPagesHigh;
1825	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1826	# endif
1827	# ifdef PGMPOOL_WITH_CACHE
1828	/** The number of cache hits. */
1829	STAMCOUNTER StatCacheHits;
1830	/** The number of cache misses. */
1831	STAMCOUNTER StatCacheMisses;
1832	/** The number of times we've got a conflict of 'kind' in the cache. */
1833	STAMCOUNTER StatCacheKindMismatches;
1834	/** Number of times we've been out of pages. */
1835	STAMCOUNTER StatCacheFreeUpOne;
1836	/** The number of cacheable allocations. */
1837	STAMCOUNTER StatCacheCacheable;
1838	/** The number of uncacheable allocations. */
1839	STAMCOUNTER StatCacheUncacheable;
1840	# endif
1841	#elif HC_ARCH_BITS == 64
1842	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1843	#endif
1844	/** The AVL tree for looking up a page by its HC physical address. */
1845	AVLOHCPHYSTREE HCPhysTree;
1846	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1847	/** Array of pages. (cMaxPages in length)
1848	* The Id is the index into thist array.
1849	*/
1850	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1851	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1852
1853
1854	/** @def PGMPOOL_PAGE_2_PTR
1855	* Maps a pool page pool into the current context.
1856	*
1857	* @returns VBox status code.
1858	* @param pVM The VM handle.
1859	* @param pPage The pool page.
1860	*
1861	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1862	* small page window employeed by that function. Be careful.
1863	* @remark There is no need to assert on the result.
1864	*/
1865	#if defined(IN_RC)
1866	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1867	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1868	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1869	#elif defined(VBOX_STRICT)
1870	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1871	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1872	{
1873	Assert(pPage && pPage->pvPageR3);
1874	return pPage->pvPageR3;
1875	}
1876	#else
1877	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1878	#endif
1879
1880	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1881	* Maps a pool page pool into the current context.
1882	*
1883	* @returns VBox status code.
1884	* @param pPGM Pointer to the PGM instance data.
1885	* @param pPage The pool page.
1886	*
1887	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1888	* small page window employeed by that function. Be careful.
1889	* @remark There is no need to assert on the result.
1890	*/
1891	#if defined(IN_RC)
1892	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1893	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1894	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1895	#else
1896	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1897	#endif
1898
1899
1900	/** @name Per guest page tracking data.
1901	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1902	* is to use more bits for it and split it up later on. But for now we'll play
1903	* safe and change as little as possible.
1904	*
1905	* The 16-bit word has two parts:
1906	*
1907	* The first 14-bit forms the @a idx field. It is either the index of a page in
1908	* the shadow page pool, or and index into the extent list.
1909	*
1910	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
1911	* shadow page pool references to the page. If cRefs equals
1912	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1913	* (misnomer) table and not the shadow page pool.
1914	*
1915	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1916	* the 16-bit word.
1917	*
1918	* @{ */
1919	/** The shift count for getting to the cRefs part. */
1920	#define PGMPOOL_TD_CREFS_SHIFT 14
1921	/** The mask applied after shifting the tracking data down by
1922	* PGMPOOL_TD_CREFS_SHIFT. */
1923	#define PGMPOOL_TD_CREFS_MASK 0x3
1924	/** The cRef value used to indiciate that the idx is the head of a
1925	* physical cross reference list. */
1926	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1927	/** The shift used to get idx. */
1928	#define PGMPOOL_TD_IDX_SHIFT 0
1929	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1930	#define PGMPOOL_TD_IDX_MASK 0x3fff
1931	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1932	* simply too many mappings of this page. */
1933	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1934
1935	/** @def PGMPOOL_TD_MAKE
1936	* Makes a 16-bit tracking data word.
1937	*
1938	* @returns tracking data.
1939	* @param cRefs The @a cRefs field. Must be within bounds!
1940	* @param idx The @a idx field. Must also be within bounds! */
1941	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
1942
1943	/** @def PGMPOOL_TD_GET_CREFS
1944	* Get the @a cRefs field from a tracking data word.
1945	*
1946	* @returns The @a cRefs field
1947	* @param u16 The tracking data word. */
1948	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1949
1950	/** @def PGMPOOL_TD_GET_IDX
1951	* Get the @a idx field from a tracking data word.
1952	*
1953	* @returns The @a idx field
1954	* @param u16 The tracking data word. */
1955	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1956	/** @} */
1957
1958
1959	/**
1960	* Trees are using self relative offsets as pointers.
1961	* So, all its data, including the root pointer, must be in the heap for HC and GC
1962	* to have the same layout.
1963	*/
1964	typedef struct PGMTREES
1965	{
1966	/** Physical access handlers (AVL range+offsetptr tree). */
1967	AVLROGCPHYSTREE PhysHandlers;
1968	/** Virtual access handlers (AVL range + GC ptr tree). */
1969	AVLROGCPTRTREE VirtHandlers;
1970	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1971	AVLROGCPHYSTREE PhysToVirtHandlers;
1972	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1973	AVLROGCPTRTREE HyperVirtHandlers;
1974	} PGMTREES;
1975	/** Pointer to PGM trees. */
1976	typedef PGMTREES *PPGMTREES;
1977
1978
1979	/** @name Paging mode macros
1980	* @{ */
1981	#ifdef IN_RC
1982	# define PGM_CTX(a,b) a##RC##b
1983	# define PGM_CTX_STR(a,b) a "GC" b
1984	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1985	#else
1986	# ifdef IN_RING3
1987	# define PGM_CTX(a,b) a##R3##b
1988	# define PGM_CTX_STR(a,b) a "R3" b
1989	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1990	# else
1991	# define PGM_CTX(a,b) a##R0##b
1992	# define PGM_CTX_STR(a,b) a "R0" b
1993	# define PGM_CTX_DECL(type) VMMDECL(type)
1994	# endif
1995	#endif
1996
1997	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1998	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1999	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2000	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2001	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2002	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2003	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2004	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2005	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2006	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2007	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2008	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2009	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2010	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2011	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2012	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2013	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2014
2015	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2016	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2017	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2018	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2019	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2020	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2021	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2022	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2023	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2024	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2025	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2026	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2027	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2028	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2029	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2030	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2031	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2032
2033	/* Shw_Gst */
2034	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2035	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2036	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2037	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2038	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2039	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2040	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2041	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2042	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2043	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2044	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2045	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2046	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2047	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2048	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2049	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2050	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2051	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2052	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2053
2054	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2055	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2056	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2057	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2058	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2059	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2060	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2061	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2062	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2063	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2064	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2065	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2066	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2067	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2068	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2069	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2070	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2071	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2072	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2073	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2074	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2075	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2076	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2077	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2078	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2079	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2080	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2081	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2082	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2083	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2084	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2085	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2086	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2087	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2088	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2089	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2090	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2091
2092	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2093	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2094	/** @} */
2095
2096	/**
2097	* Data for each paging mode.
2098	*/
2099	typedef struct PGMMODEDATA
2100	{
2101	/** The guest mode type. */
2102	uint32_t uGstType;
2103	/** The shadow mode type. */
2104	uint32_t uShwType;
2105
2106	/** @name Function pointers for Shadow paging.
2107	* @{
2108	*/
2109	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2110	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2111	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2112	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2113
2114	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2115	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2116
2117	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2118	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2119	/** @} */
2120
2121	/** @name Function pointers for Guest paging.
2122	* @{
2123	*/
2124	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2125	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2126	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2127	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2128	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2129	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2130	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2131	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2132	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2133	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2134	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2135	/** @} */
2136
2137	/** @name Function pointers for Both Shadow and Guest paging.
2138	* @{
2139	*/
2140	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2141	/* no pfnR3BthTrap0eHandler */
2142	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2143	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2144	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2145	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2146	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2147	#ifdef VBOX_STRICT
2148	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2149	#endif
2150	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2151	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2152
2153	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2154	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2155	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2156	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2157	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2158	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2159	#ifdef VBOX_STRICT
2160	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2161	#endif
2162	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2163	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2164
2165	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2166	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2167	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2168	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2169	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2170	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2171	#ifdef VBOX_STRICT
2172	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2173	#endif
2174	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2175	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2176	/** @} */
2177	} PGMMODEDATA, *PPGMMODEDATA;
2178
2179
2180
2181	/**
2182	* Converts a PGM pointer into a VM pointer.
2183	* @returns Pointer to the VM structure the PGM is part of.
2184	* @param pPGM Pointer to PGM instance data.
2185	*/
2186	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2187
2188	/**
2189	* PGM Data (part of VM)
2190	*/
2191	typedef struct PGM
2192	{
2193	/** Offset to the VM structure. */
2194	RTINT offVM;
2195	/** Offset of the PGMCPU structure relative to VMCPU. */
2196	int32_t offVCpu;
2197	/** @cfgm{PGM/RamPreAlloc, bool, false}
2198	* Whether to preallocate all the guest RAM or not. */
2199	bool fRamPreAlloc;
2200	/** Alignment padding. */
2201	bool afAlignment0[3];
2202
2203
2204	/*
2205	* This will be redefined at least two more times before we're done, I'm sure.
2206	* The current code is only to get on with the coding.
2207	* - 2004-06-10: initial version, bird.
2208	* - 2004-07-02: 1st time, bird.
2209	* - 2004-10-18: 2nd time, bird.
2210	* - 2005-07-xx: 3rd time, bird.
2211	*/
2212
2213	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2214	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2215	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2216	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2217
2218	/** The host paging mode. (This is what SUPLib reports.) */
2219	SUPPAGINGMODE enmHostMode;
2220	/** The shadow paging mode. */
2221	PGMMODE enmShadowMode;
2222	/** The guest paging mode. */
2223	PGMMODE enmGuestMode;
2224
2225	/** The current physical address representing in the guest CR3 register. */
2226	RTGCPHYS GCPhysCR3;
2227	/** Pointer to the 5 page CR3 content mapping.
2228	* The first page is always the CR3 (in some form) while the 4 other pages
2229	* are used of the PDs in PAE mode. */
2230	RTGCPTR GCPtrCR3Mapping;
2231	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2232	uint32_t u32Alignment;
2233	#endif
2234	/** @name 32-bit Guest Paging.
2235	* @{ */
2236	/** The guest's page directory, R3 pointer. */
2237	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2238	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2239	/** The guest's page directory, R0 pointer. */
2240	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2241	#endif
2242	/** The guest's page directory, static RC mapping. */
2243	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2244	/** @} */
2245
2246	/** @name PAE Guest Paging.
2247	* @{ */
2248	/** The guest's page directory pointer table, static RC mapping. */
2249	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2250	/** The guest's page directory pointer table, R3 pointer. */
2251	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2252	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2253	/** The guest's page directory pointer table, R0 pointer. */
2254	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2255	#endif
2256
2257	/** The guest's page directories, R3 pointers.
2258	* These are individual pointers and don't have to be adjecent.
2259	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2260	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2261	/** The guest's page directories, R0 pointers.
2262	* Same restrictions as apGstPaePDsR3. */
2263	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2264	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2265	#endif
2266	/** The guest's page directories, static GC mapping.
2267	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2268	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2269	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2270	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2271	RTGCPHYS aGCPhysGstPaePDs[4];
2272	/** The physical addresses of the monitored guest page directories (PAE). */
2273	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2274	/** @} */
2275
2276	/** @name AMD64 Guest Paging.
2277	* @{ */
2278	/** The guest's page directory pointer table, R3 pointer. */
2279	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2280	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2281	/** The guest's page directory pointer table, R0 pointer. */
2282	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2283	#endif
2284	/** @} */
2285
2286	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2287	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2288	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2289	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2290	/** Pointer to the page of the current active CR3 - RC Ptr. */
2291	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2292	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2293	uint32_t iShwUser;
2294	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2295	uint32_t iShwUserTable;
2296	# if HC_ARCH_BITS == 64
2297	RTRCPTR alignment6; /*< structure size alignment. /
2298	# endif
2299	/** @} */
2300
2301	/** @name Function pointers for Shadow paging.
2302	* @{
2303	*/
2304	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2305	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2306	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2307	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2308
2309	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2310	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2311
2312	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2313	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2314
2315	/** @} */
2316
2317	/** @name Function pointers for Guest paging.
2318	* @{
2319	*/
2320	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2321	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2322	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2323	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2324	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2325	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2326	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2327	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2328	#if HC_ARCH_BITS == 64
2329	RTRCPTR alignment3; /*< structure size alignment. /
2330	#endif
2331
2332	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2333	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2334	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2335	/** @} */
2336
2337	/** @name Function pointers for Both Shadow and Guest paging.
2338	* @{
2339	*/
2340	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2341	/* no pfnR3BthTrap0eHandler */
2342	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2343	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2344	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2345	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2346	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2347	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2348	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2349	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2350
2351	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2352	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2353	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2354	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2355	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2356	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2357	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2358	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2359	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2360
2361	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2362	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2363	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2364	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2365	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2366	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2367	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2368	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2369	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2370	#if HC_ARCH_BITS == 64
2371	RTRCPTR alignment2; /*< structure size alignment. /
2372	#endif
2373	/** @} */
2374
2375	/** Pointer to SHW+GST mode data (function pointers).
2376	* The index into this table is made up from */
2377	R3PTRTYPE(PPGMMODEDATA) paModeData;
2378
2379	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2380	* This is sorted by physical address and contains no overlapping ranges. */
2381	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2382	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2383	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2384	/** RC pointer corresponding to PGM::pRamRangesR3. */
2385	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2386	/** The configured RAM size.
2387	* @remarks Do NOT use this, it's too small to hold the whole stuff.
2388	* @todo Remove with VBOX_WITH_NEW_PHYS_CODE! */
2389	RTUINT cbRamSize;
2390
2391	/** Pointer to the list of ROM ranges - for R3.
2392	* This is sorted by physical address and contains no overlapping ranges. */
2393	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2394	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2395	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2396	/** RC pointer corresponding to PGM::pRomRangesR3. */
2397	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2398	/** Alignment padding. */
2399	RTRCPTR GCPtrPadding2;
2400
2401	/** Pointer to the list of MMIO2 ranges - for R3.
2402	* Registration order. */
2403	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2404
2405	/** PGM offset based trees - R3 Ptr. */
2406	R3PTRTYPE(PPGMTREES) pTreesR3;
2407	/** PGM offset based trees - R0 Ptr. */
2408	R0PTRTYPE(PPGMTREES) pTreesR0;
2409	/** PGM offset based trees - RC Ptr. */
2410	RCPTRTYPE(PPGMTREES) pTreesRC;
2411
2412	/** Linked list of GC mappings - for RC.
2413	* The list is sorted ascending on address.
2414	*/
2415	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2416	/** Linked list of GC mappings - for HC.
2417	* The list is sorted ascending on address.
2418	*/
2419	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2420	/** Linked list of GC mappings - for R0.
2421	* The list is sorted ascending on address.
2422	*/
2423	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2424
2425	/** Indicates that PGMR3FinalizeMappings has been called and that further
2426	* PGMR3MapIntermediate calls will be rejected. */
2427	bool fFinalizedMappings;
2428	/** If set no conflict checks are required. (boolean) */
2429	bool fMappingsFixed;
2430	/** If set, then no mappings are put into the shadow page table. (boolean) */
2431	bool fDisableMappings;
2432	/** Size of fixed mapping */
2433	uint32_t cbMappingFixed;
2434	/** Base address (GC) of fixed mapping */
2435	RTGCPTR GCPtrMappingFixed;
2436	/** The address of the previous RAM range mapping. */
2437	RTGCPTR GCPtrPrevRamRangeMapping;
2438
2439	/** @name Intermediate Context
2440	* @{ */
2441	/** Pointer to the intermediate page directory - Normal. */
2442	R3PTRTYPE(PX86PD) pInterPD;
2443	/** Pointer to the intermedate page tables - Normal.
2444	* There are two page tables, one for the identity mapping and one for
2445	* the host context mapping (of the core code). */
2446	R3PTRTYPE(PX86PT) apInterPTs[2];
2447	/** Pointer to the intermedate page tables - PAE. */
2448	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2449	/** Pointer to the intermedate page directory - PAE. */
2450	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2451	/** Pointer to the intermedate page directory - PAE. */
2452	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2453	/** Pointer to the intermedate page-map level 4 - AMD64. */
2454	R3PTRTYPE(PX86PML4) pInterPaePML4;
2455	/** Pointer to the intermedate page directory - AMD64. */
2456	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2457	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2458	RTHCPHYS HCPhysInterPD;
2459	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2460	RTHCPHYS HCPhysInterPaePDPT;
2461	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2462	RTHCPHYS HCPhysInterPaePML4;
2463	/** @} */
2464
2465	/** Base address of the dynamic page mapping area.
2466	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2467	*/
2468	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2469	/** The index of the last entry used in the dynamic page mapping area. */
2470	RTUINT iDynPageMapLast;
2471	/** Cache containing the last entries in the dynamic page mapping area.
2472	* The cache size is covering half of the mapping area. */
2473	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2474	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2475
2476	/** The address of the ring-0 mapping cache if we're making use of it. */
2477	RTR0PTR pvR0DynMapUsed;
2478	#if HC_ARCH_BITS == 32
2479	RTR0PTR R0PtrPadding0; /*< Alignment. /
2480	#endif
2481
2482
2483	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2484	RTGCPHYS GCPhys4MBPSEMask;
2485
2486	/** A20 gate mask.
2487	* Our current approach to A20 emulation is to let REM do it and don't bother
2488	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2489	* But whould need arrise, we'll subject physical addresses to this mask. */
2490	RTGCPHYS GCPhysA20Mask;
2491	/** A20 gate state - boolean! */
2492	bool fA20Enabled;
2493
2494	/** What needs syncing (PGM_SYNC_*).
2495	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2496	* PGMFlushTLB, and PGMR3Load. */
2497	RTUINT fSyncFlags;
2498
2499	/** PGM critical section.
2500	* This protects the physical & virtual access handlers, ram ranges,
2501	* and the page flag updating (some of it anyway).
2502	*/
2503	PDMCRITSECT CritSect;
2504
2505	/** Shadow Page Pool - R3 Ptr. */
2506	R3PTRTYPE(PPGMPOOL) pPoolR3;
2507	/** Shadow Page Pool - R0 Ptr. */
2508	R0PTRTYPE(PPGMPOOL) pPoolR0;
2509	/** Shadow Page Pool - RC Ptr. */
2510	RCPTRTYPE(PPGMPOOL) pPoolRC;
2511
2512	/** We're not in a state which permits writes to guest memory.
2513	* (Only used in strict builds.) */
2514	bool fNoMorePhysWrites;
2515
2516	/** Flush the cache on the next access. */
2517	bool fPhysCacheFlushPending;
2518	/** @todo r=bird: Fix member names!*/
2519	/** PGMPhysRead cache */
2520	PGMPHYSCACHE pgmphysreadcache;
2521	/** PGMPhysWrite cache */
2522	PGMPHYSCACHE pgmphyswritecache;
2523
2524	/**
2525	* Data associated with managing the ring-3 mappings of the allocation chunks.
2526	*/
2527	struct
2528	{
2529	/** The chunk tree, ordered by chunk id. */
2530	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2531	R3PTRTYPE(PAVLU32NODECORE) pTree;
2532	#else
2533	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2534	#endif
2535	/** The chunk mapping TLB. */
2536	PGMCHUNKR3MAPTLB Tlb;
2537	/** The number of mapped chunks. */
2538	uint32_t c;
2539	/** The maximum number of mapped chunks.
2540	* @cfgm PGM/MaxRing3Chunks */
2541	uint32_t cMax;
2542	/** The chunk age tree, ordered by ageing sequence number. */
2543	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2544	/** The current time. */
2545	uint32_t iNow;
2546	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2547	uint32_t AgeingCountdown;
2548	} ChunkR3Map;
2549
2550	/**
2551	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2552	*/
2553	PGMPAGER3MAPTLB PhysTlbHC;
2554
2555	/** @name The zero page.
2556	* @{ */
2557	/** The host physical address of the zero page. */
2558	RTHCPHYS HCPhysZeroPg;
2559	/** The ring-3 mapping of the zero page. */
2560	RTR3PTR pvZeroPgR3;
2561	/** The ring-0 mapping of the zero page. */
2562	RTR0PTR pvZeroPgR0;
2563	/** The GC mapping of the zero page. */
2564	RTGCPTR pvZeroPgGC;
2565	#if GC_ARCH_BITS != 32
2566	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2567	#endif
2568	/** @}*/
2569
2570	/** The number of handy pages. */
2571	uint32_t cHandyPages;
2572	/**
2573	* Array of handy pages.
2574	*
2575	* This array is used in a two way communication between pgmPhysAllocPage
2576	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2577	* an intermediary.
2578	*
2579	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2580	* (The current size of 32 pages, means 128 KB of handy memory.)
2581	*/
2582	GMMPAGEDESC aHandyPages[32];
2583
2584	/** @name Release Statistics
2585	* @{ */
2586	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2587	uint32_t cPrivatePages; /*< The number of private pages. /
2588	uint32_t cSharedPages; /*< The number of shared pages. /
2589	uint32_t cZeroPages; /*< The number of zero backed pages. /
2590	/** The number of times the guest has switched mode since last reset or statistics reset. */
2591	STAMCOUNTER cGuestModeChanges;
2592	/** The number of times we were forced to change the hypervisor region location. */
2593	STAMCOUNTER cRelocations;
2594	/** @} */
2595
2596	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2597	/** RC: Which statistic this \#PF should be attributed to. */
2598	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2599	RTRCPTR padding0;
2600	/** R0: Which statistic this \#PF should be attributed to. */
2601	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2602	RTR0PTR padding1;
2603
2604	/* Common */
2605	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2606	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2607	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2608	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2609	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2610	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2611	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2612	# endif
2613	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2614	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2615
2616	/* R3 only: */
2617	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2618	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2619	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2620	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2621	#ifndef VBOX_WITH_NEW_PHYS_CODE
2622	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2623	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2624	#endif
2625
2626	/* R0 only: */
2627	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2628	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2629	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2630	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2631	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2632	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2633	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2634	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2635	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2636	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2637	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2638	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2639	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2640	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2641	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2642	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2643	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2644	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2645	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2646	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2647	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2648	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2649	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2650	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2651	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2652	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2653
2654	/* RC only: */
2655	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2656	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2657	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2658	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2659
2660	/* RZ only: */
2661	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2662	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2663	STAMPROFILE StatRZTrap0eTimeSyncPT;
2664	STAMPROFILE StatRZTrap0eTimeMapping;
2665	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2666	STAMPROFILE StatRZTrap0eTimeHandlers;
2667	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2668	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2669	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2670	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2671	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2672	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2673	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2674	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2675	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2676	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2677	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2678	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2679	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2680	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2681	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2682	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2683	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2684	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2685	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2686	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2687	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2688	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2689	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2690	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2691	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2692	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2693	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2694	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2695	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2696	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2697	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2698	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2699	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2700	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2701	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2702	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2703	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2704	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2705	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2706	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2707	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2708	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2709	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2710
2711	/* HC - R3 and (maybe) R0: */
2712
2713	/* RZ & R3: */
2714	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2715	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2716	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2717	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2718	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2719	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2720	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2721	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2722	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2723	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2724	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2725	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2726	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2727	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2728	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2729	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2730	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2731	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2732	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2733	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2734	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2735	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2736	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2737	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2738	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2739	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2740	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2741	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2742	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2743	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2744	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2745	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2746	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2747	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2748	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2749	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2750	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2751	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2752	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2753	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2754	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2755	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2756	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2757	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2758	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2759	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2760	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2761	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2762	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2763	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2764	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2765	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2766	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2767	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2768
2769	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2770	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2771	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2772	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2773	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2774	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2775	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2776	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2777	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2778	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2779	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2780	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2781	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2782	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2783	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2784	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2785	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2786	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2787	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2788	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2789	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2790	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2791	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2792	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2793	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2794	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2795	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2796	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2797	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2798	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2799	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2800	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2801	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2802	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2803	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2804	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2805	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2806	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2807	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2808	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2809	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2810	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2811	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2812	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2813	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2814	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2815	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2816	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2817	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2818	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2819	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2820	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2821	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2822	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2823	#endif /* VBOX_WITH_STATISTICS */
2824	} PGM;
2825	/** Pointer to the PGM instance data. */
2826	typedef PGM *PPGM;
2827
2828
2829	/**
2830	* PGMCPU Data (part of VMCPU).
2831	*/
2832	typedef struct PGMCPU
2833	{
2834	/** Offset to the VMCPU structure. */
2835	RTINT offVMCPU;
2836	/** Automatically tracked physical memory mapping set.
2837	* Ring-0 and strict raw-mode builds. */
2838	PGMMAPSET AutoSet;
2839	} PGMCPU;
2840	/** Pointer to the per-cpu PGM data. */
2841	typedef PGMCPU *PPGMCPU;
2842
2843
2844	/** @name PGM::fSyncFlags Flags
2845	* @{
2846	*/
2847	/** Updates the virtual access handler state bit in PGMPAGE. */
2848	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2849	/** Always sync CR3. */
2850	#define PGM_SYNC_ALWAYS RT_BIT(1)
2851	/** Check monitoring on next CR3 (re)load and invalidate page. */
2852	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2853	/** Check guest mapping in SyncCR3. */
2854	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2855	/** Clear the page pool (a light weight flush). */
2856	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2857	/** @} */
2858
2859
2860	__BEGIN_DECLS
2861
2862	int pgmLock(PVM pVM);
2863	void pgmUnlock(PVM pVM);
2864
2865	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2866	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2867	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2868	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2869	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2870
2871	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2872	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2873	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2874	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2875	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2876	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2877	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2878	#else
2879	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2880	#endif
2881	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2882
2883
2884	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2885	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2886	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2887	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2888	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2889	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2890	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2891	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2892	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2893	#ifdef IN_RING3
2894	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2895	void pgmR3PhysRelinkRamRanges(PVM pVM);
2896	int pgmR3PhysRamReset(PVM pVM);
2897	int pgmR3PhysRomReset(PVM pVM);
2898	# ifndef VBOX_WITH_NEW_PHYS_CODE
2899	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2900	# endif
2901
2902	int pgmR3PoolInit(PVM pVM);
2903	void pgmR3PoolRelocate(PVM pVM);
2904	void pgmR3PoolReset(PVM pVM);
2905
2906	#endif /* IN_RING3 */
2907	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2908	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2909	#endif
2910	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2911	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2912	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2913	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2914	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2915	void pgmPoolFlushAll(PVM pVM);
2916	void pgmPoolClearAll(PVM pVM);
2917	int pgmPoolSyncCR3(PVM pVM);
2918	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
2919	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2920	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2921	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2922	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2923	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2924	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2925	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2926	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2927	#ifdef PGMPOOL_WITH_MONITORING
2928	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2929	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2930	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2931	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2932	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2933	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2934	#endif
2935
2936	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2937	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
2938	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2939	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2940
2941	int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2942	#ifndef IN_RC
2943	int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2944	#endif
2945	int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
2946
2947	PX86PD pgmGstLazyMap32BitPD(PPGM pPGM);
2948	PX86PDPT pgmGstLazyMapPaePDPT(PPGM pPGM);
2949	PX86PDPAE pgmGstLazyMapPaePD(PPGM pPGM, uint32_t iPdpt);
2950	PX86PML4 pgmGstLazyMapPml4(PPGM pPGM);
2951
2952	__END_DECLS
2953
2954
2955	/**
2956	* Gets the PGMRAMRANGE structure for a guest page.
2957	*
2958	* @returns Pointer to the RAM range on success.
2959	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2960	*
2961	* @param pPGM PGM handle.
2962	* @param GCPhys The GC physical address.
2963	*/
2964	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2965	{
2966	/*
2967	* Optimize for the first range.
2968	*/
2969	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2970	RTGCPHYS off = GCPhys - pRam->GCPhys;
2971	if (RT_UNLIKELY(off >= pRam->cb))
2972	{
2973	do
2974	{
2975	pRam = pRam->CTX_SUFF(pNext);
2976	if (RT_UNLIKELY(!pRam))
2977	break;
2978	off = GCPhys - pRam->GCPhys;
2979	} while (off >= pRam->cb);
2980	}
2981	return pRam;
2982	}
2983
2984
2985	/**
2986	* Gets the PGMPAGE structure for a guest page.
2987	*
2988	* @returns Pointer to the page on success.
2989	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2990	*
2991	* @param pPGM PGM handle.
2992	* @param GCPhys The GC physical address.
2993	*/
2994	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2995	{
2996	/*
2997	* Optimize for the first range.
2998	*/
2999	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3000	RTGCPHYS off = GCPhys - pRam->GCPhys;
3001	if (RT_UNLIKELY(off >= pRam->cb))
3002	{
3003	do
3004	{
3005	pRam = pRam->CTX_SUFF(pNext);
3006	if (RT_UNLIKELY(!pRam))
3007	return NULL;
3008	off = GCPhys - pRam->GCPhys;
3009	} while (off >= pRam->cb);
3010	}
3011	return &pRam->aPages[off >> PAGE_SHIFT];
3012	}
3013
3014
3015	/**
3016	* Gets the PGMPAGE structure for a guest page.
3017	*
3018	* Old Phys code: Will make sure the page is present.
3019	*
3020	* @returns VBox status code.
3021	* @retval VINF_SUCCESS and a valid *ppPage on success.
3022	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3023	*
3024	* @param pPGM PGM handle.
3025	* @param GCPhys The GC physical address.
3026	* @param ppPage Where to store the page poitner on success.
3027	*/
3028	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3029	{
3030	/*
3031	* Optimize for the first range.
3032	*/
3033	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3034	RTGCPHYS off = GCPhys - pRam->GCPhys;
3035	if (RT_UNLIKELY(off >= pRam->cb))
3036	{
3037	do
3038	{
3039	pRam = pRam->CTX_SUFF(pNext);
3040	if (RT_UNLIKELY(!pRam))
3041	{
3042	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3043	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3044	}
3045	off = GCPhys - pRam->GCPhys;
3046	} while (off >= pRam->cb);
3047	}
3048	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3049	#ifndef VBOX_WITH_NEW_PHYS_CODE
3050
3051	/*
3052	* Make sure it's present.
3053	*/
3054	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3055	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3056	{
3057	#ifdef IN_RING3
3058	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3059	#else
3060	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3061	#endif
3062	if (RT_FAILURE(rc))
3063	{
3064	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3065	return rc;
3066	}
3067	Assert(rc == VINF_SUCCESS);
3068	}
3069	#endif
3070	return VINF_SUCCESS;
3071	}
3072
3073
3074
3075
3076	/**
3077	* Gets the PGMPAGE structure for a guest page.
3078	*
3079	* Old Phys code: Will make sure the page is present.
3080	*
3081	* @returns VBox status code.
3082	* @retval VINF_SUCCESS and a valid *ppPage on success.
3083	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3084	*
3085	* @param pPGM PGM handle.
3086	* @param GCPhys The GC physical address.
3087	* @param ppPage Where to store the page poitner on success.
3088	* @param ppRamHint Where to read and store the ram list hint.
3089	* The caller initializes this to NULL before the call.
3090	*/
3091	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3092	{
3093	RTGCPHYS off;
3094	PPGMRAMRANGE pRam = *ppRamHint;
3095	if ( !pRam
3096	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3097	{
3098	pRam = pPGM->CTX_SUFF(pRamRanges);
3099	off = GCPhys - pRam->GCPhys;
3100	if (RT_UNLIKELY(off >= pRam->cb))
3101	{
3102	do
3103	{
3104	pRam = pRam->CTX_SUFF(pNext);
3105	if (RT_UNLIKELY(!pRam))
3106	{
3107	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3108	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3109	}
3110	off = GCPhys - pRam->GCPhys;
3111	} while (off >= pRam->cb);
3112	}
3113	*ppRamHint = pRam;
3114	}
3115	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3116	#ifndef VBOX_WITH_NEW_PHYS_CODE
3117
3118	/*
3119	* Make sure it's present.
3120	*/
3121	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3122	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3123	{
3124	#ifdef IN_RING3
3125	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3126	#else
3127	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3128	#endif
3129	if (RT_FAILURE(rc))
3130	{
3131	ppPage = NULL; / Shut up annoying smart ass. */
3132	return rc;
3133	}
3134	Assert(rc == VINF_SUCCESS);
3135	}
3136	#endif
3137	return VINF_SUCCESS;
3138	}
3139
3140
3141	/**
3142	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3143	*
3144	* @returns Pointer to the page on success.
3145	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3146	*
3147	* @param pPGM PGM handle.
3148	* @param GCPhys The GC physical address.
3149	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3150	*/
3151	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3152	{
3153	/*
3154	* Optimize for the first range.
3155	*/
3156	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3157	RTGCPHYS off = GCPhys - pRam->GCPhys;
3158	if (RT_UNLIKELY(off >= pRam->cb))
3159	{
3160	do
3161	{
3162	pRam = pRam->CTX_SUFF(pNext);
3163	if (RT_UNLIKELY(!pRam))
3164	return NULL;
3165	off = GCPhys - pRam->GCPhys;
3166	} while (off >= pRam->cb);
3167	}
3168	*ppRam = pRam;
3169	return &pRam->aPages[off >> PAGE_SHIFT];
3170	}
3171
3172
3173	/**
3174	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3175	*
3176	* @returns Pointer to the page on success.
3177	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3178	*
3179	* @param pPGM PGM handle.
3180	* @param GCPhys The GC physical address.
3181	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3182	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3183	*/
3184	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3185	{
3186	/*
3187	* Optimize for the first range.
3188	*/
3189	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3190	RTGCPHYS off = GCPhys - pRam->GCPhys;
3191	if (RT_UNLIKELY(off >= pRam->cb))
3192	{
3193	do
3194	{
3195	pRam = pRam->CTX_SUFF(pNext);
3196	if (RT_UNLIKELY(!pRam))
3197	{
3198	ppRam = NULL; / Shut up silly GCC warnings. */
3199	ppPage = NULL; / ditto */
3200	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3201	}
3202	off = GCPhys - pRam->GCPhys;
3203	} while (off >= pRam->cb);
3204	}
3205	*ppRam = pRam;
3206	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3207	#ifndef VBOX_WITH_NEW_PHYS_CODE
3208
3209	/*
3210	* Make sure it's present.
3211	*/
3212	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3213	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3214	{
3215	#ifdef IN_RING3
3216	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3217	#else
3218	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3219	#endif
3220	if (RT_FAILURE(rc))
3221	{
3222	ppPage = NULL; / Shut up silly GCC warnings. */
3223	ppPage = NULL; / ditto */
3224	return rc;
3225	}
3226	Assert(rc == VINF_SUCCESS);
3227
3228	}
3229	#endif
3230	return VINF_SUCCESS;
3231	}
3232
3233
3234	/**
3235	* Convert GC Phys to HC Phys.
3236	*
3237	* @returns VBox status.
3238	* @param pPGM PGM handle.
3239	* @param GCPhys The GC physical address.
3240	* @param pHCPhys Where to store the corresponding HC physical address.
3241	*
3242	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3243	* Avoid when writing new code!
3244	*/
3245	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3246	{
3247	PPGMPAGE pPage;
3248	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3249	if (RT_FAILURE(rc))
3250	return rc;
3251	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3252	return VINF_SUCCESS;
3253	}
3254
3255	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3256
3257	/**
3258	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3259	* optimizes access to pages already in the set.
3260	*
3261	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3262	* @param pPGM Pointer to the PVM instance data.
3263	* @param HCPhys The physical address of the page.
3264	* @param ppv Where to store the mapping address.
3265	*/
3266	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3267	{
3268	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3269	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3270	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3271	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3272
3273	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3274	unsigned iEntry = pSet->aiHashTable[iHash];
3275	if ( iEntry < pSet->cEntries
3276	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3277	{
3278	*ppv = pSet->aEntries[iEntry].pvPage;
3279	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3280	}
3281	else
3282	{
3283	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3284	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3285	}
3286
3287	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3288	return VINF_SUCCESS;
3289	}
3290
3291
3292	/**
3293	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3294	* access to pages already in the set.
3295	*
3296	* @returns See PGMDynMapGCPage.
3297	* @param pPGM Pointer to the PVM instance data.
3298	* @param HCPhys The physical address of the page.
3299	* @param ppv Where to store the mapping address.
3300	*/
3301	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3302	{
3303	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3304	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3305
3306	/*
3307	* Get the ram range.
3308	*/
3309	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3310	RTGCPHYS off = GCPhys - pRam->GCPhys;
3311	if (RT_UNLIKELY(off >= pRam->cb
3312	/** @todo \|\| page state stuff */))
3313	{
3314	/* This case is not counted into StatR0DynMapGCPageInl. */
3315	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3316	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3317	}
3318
3319	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3320	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3321
3322	/*
3323	* pgmR0DynMapHCPageInlined with out stats.
3324	*/
3325	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3326	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3327	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3328
3329	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3330	unsigned iEntry = pSet->aiHashTable[iHash];
3331	if ( iEntry < pSet->cEntries
3332	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3333	{
3334	*ppv = pSet->aEntries[iEntry].pvPage;
3335	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3336	}
3337	else
3338	{
3339	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3340	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3341	}
3342
3343	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3344	return VINF_SUCCESS;
3345	}
3346
3347	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3348	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3349
3350	/**
3351	* Maps the page into current context (RC and maybe R0).
3352	*
3353	* @returns pointer to the mapping.
3354	* @param pVM Pointer to the PGM instance data.
3355	* @param pPage The page.
3356	*/
3357	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3358	{
3359	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3360	{
3361	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3362	void *pv;
3363	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3364	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3365	# else
3366	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3367	# endif
3368	return pv;
3369	}
3370	AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3371	}
3372
3373	/**
3374	* Temporarily maps one host page specified by HC physical address, returning
3375	* pointer within the page.
3376	*
3377	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3378	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3379	*
3380	* @returns The address corresponding to HCPhys.
3381	* @param pPGM Pointer to the PVM instance data.
3382	* @param HCPhys HC Physical address of the page.
3383	*/
3384	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3385	{
3386	void *pv;
3387	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3388	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3389	# else
3390	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3391	# endif
3392	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3393	return pv;
3394	}
3395
3396	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3397
3398	#ifndef IN_RC
3399	/**
3400	* Queries the Physical TLB entry for a physical guest page,
3401	* attemting to load the TLB entry if necessary.
3402	*
3403	* @returns VBox status code.
3404	* @retval VINF_SUCCESS on success
3405	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3406	*
3407	* @param pPGM The PGM instance handle.
3408	* @param GCPhys The address of the guest page.
3409	* @param ppTlbe Where to store the pointer to the TLB entry.
3410	*/
3411	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3412	{
3413	int rc;
3414	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3415	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3416	{
3417	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3418	rc = VINF_SUCCESS;
3419	}
3420	else
3421	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3422	*ppTlbe = pTlbe;
3423	return rc;
3424	}
3425
3426
3427	/**
3428	* Queries the Physical TLB entry for a physical guest page,
3429	* attemting to load the TLB entry if necessary.
3430	*
3431	* @returns VBox status code.
3432	* @retval VINF_SUCCESS on success
3433	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3434	*
3435	* @param pPGM The PGM instance handle.
3436	* @param pPage Pointer to the PGMPAGE structure corresponding to
3437	* GCPhys.
3438	* @param GCPhys The address of the guest page.
3439	* @param ppTlbe Where to store the pointer to the TLB entry.
3440	*/
3441	DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3442	{
3443	int rc;
3444	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3445	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3446	{
3447	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3448	rc = VINF_SUCCESS;
3449	}
3450	else
3451	rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3452	*ppTlbe = pTlbe;
3453	return rc;
3454	}
3455	#endif /* !IN_RC */
3456
3457
3458	#ifndef VBOX_WITH_NEW_PHYS_CODE
3459	/**
3460	* Convert GC Phys to HC Virt and HC Phys.
3461	*
3462	* @returns VBox status.
3463	* @param pPGM PGM handle.
3464	* @param GCPhys The GC physical address.
3465	* @param pHCPtr Where to store the corresponding HC virtual address.
3466	* @param pHCPhys Where to store the HC Physical address and its flags.
3467	*
3468	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3469	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3470	* Either way, we have to make sure the page is writable in MapCR3.
3471	*/
3472	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3473	{
3474	PPGMRAMRANGE pRam;
3475	PPGMPAGE pPage;
3476	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3477	if (RT_FAILURE(rc))
3478	{
3479	pHCPtr = 0; / Shut up crappy GCC warnings */
3480	pHCPhys = 0; / ditto */
3481	return rc;
3482	}
3483	RTGCPHYS off = GCPhys - pRam->GCPhys;
3484
3485	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3486	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3487	{
3488	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3489	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3490	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3491	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3492	#else
3493	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3494	#endif
3495	return VINF_SUCCESS;
3496	}
3497	if (pRam->pvR3)
3498	{
3499	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3500	return VINF_SUCCESS;
3501	}
3502	*pHCPtr = 0;
3503	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3504	}
3505	#endif /* VBOX_WITH_NEW_PHYS_CODE */
3506
3507
3508	/**
3509	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3510	* Takes PSE-36 into account.
3511	*
3512	* @returns guest physical address
3513	* @param pPGM Pointer to the PGM instance data.
3514	* @param Pde Guest Pde
3515	*/
3516	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3517	{
3518	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3519	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3520
3521	return GCPhys & pPGM->GCPhys4MBPSEMask;
3522	}
3523
3524
3525	/**
3526	* Gets the page directory entry for the specified address (32-bit paging).
3527	*
3528	* @returns The page directory entry in question.
3529	* @param pPGM Pointer to the PGM instance data.
3530	* @param GCPtr The address.
3531	*/
3532	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3533	{
3534	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3535	PCX86PD pGuestPD = NULL;
3536	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3537	if (RT_FAILURE(rc))
3538	{
3539	X86PDE ZeroPde = {0};
3540	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3541	}
3542	#else
3543	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3544	# ifdef VBOX_WITH_NEW_PHYS_CODE
3545	# ifdef IN_RING3
3546	if (!pGuestPD)
3547	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3548	# endif
3549	# endif
3550	#endif
3551	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3552	}
3553
3554
3555	/**
3556	* Gets the address of a specific page directory entry (32-bit paging).
3557	*
3558	* @returns Pointer the page directory entry in question.
3559	* @param pPGM Pointer to the PGM instance data.
3560	* @param GCPtr The address.
3561	*/
3562	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3563	{
3564	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3565	PX86PD pGuestPD = NULL;
3566	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3567	AssertRCReturn(rc, NULL);
3568	#else
3569	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3570	# ifdef VBOX_WITH_NEW_PHYS_CODE
3571	# ifdef IN_RING3
3572	if (!pGuestPD)
3573	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3574	# endif
3575	# endif
3576	#endif
3577	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3578	}
3579
3580
3581	/**
3582	* Gets the address the guest page directory (32-bit paging).
3583	*
3584	* @returns Pointer the page directory entry in question.
3585	* @param pPGM Pointer to the PGM instance data.
3586	*/
3587	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3588	{
3589	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3590	PX86PD pGuestPD = NULL;
3591	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3592	AssertRCReturn(rc, NULL);
3593	#else
3594	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3595	# ifdef VBOX_WITH_NEW_PHYS_CODE
3596	# ifdef IN_RING3
3597	if (!pGuestPD)
3598	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3599	# endif
3600	# endif
3601	#endif
3602	return pGuestPD;
3603	}
3604
3605
3606	/**
3607	* Gets the guest page directory pointer table.
3608	*
3609	* @returns Pointer to the page directory in question.
3610	* @returns NULL if the page directory is not present or on an invalid page.
3611	* @param pPGM Pointer to the PGM instance data.
3612	*/
3613	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3614	{
3615	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3616	PX86PDPT pGuestPDPT = NULL;
3617	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3618	AssertRCReturn(rc, NULL);
3619	#else
3620	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3621	# ifdef VBOX_WITH_NEW_PHYS_CODE
3622	# ifdef IN_RING3
3623	if (!pGuestPDPT)
3624	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3625	# endif
3626	# endif
3627	#endif
3628	return pGuestPDPT;
3629	}
3630
3631
3632	/**
3633	* Gets the guest page directory pointer table entry for the specified address.
3634	*
3635	* @returns Pointer to the page directory in question.
3636	* @returns NULL if the page directory is not present or on an invalid page.
3637	* @param pPGM Pointer to the PGM instance data.
3638	* @param GCPtr The address.
3639	*/
3640	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3641	{
3642	AssertGCPtr32(GCPtr);
3643
3644	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3645	PX86PDPT pGuestPDPT = 0;
3646	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3647	AssertRCReturn(rc, 0);
3648	#else
3649	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3650	# ifdef VBOX_WITH_NEW_PHYS_CODE
3651	# ifdef IN_RING3
3652	if (!pGuestPDPT)
3653	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3654	# endif
3655	# endif
3656	#endif
3657	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3658	}
3659
3660
3661	/**
3662	* Gets the page directory for the specified address.
3663	*
3664	* @returns Pointer to the page directory in question.
3665	* @returns NULL if the page directory is not present or on an invalid page.
3666	* @param pPGM Pointer to the PGM instance data.
3667	* @param GCPtr The address.
3668	*/
3669	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3670	{
3671	AssertGCPtr32(GCPtr);
3672
3673	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3674	AssertReturn(pGuestPDPT, NULL);
3675	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3676	if (pGuestPDPT->a[iPdpt].n.u1Present)
3677	{
3678	#ifdef VBOX_WITH_NEW_PHYS_CODE
3679	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3680	PX86PDPAE pGuestPD = NULL;
3681	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3682	AssertRCReturn(rc, NULL);
3683	#else
3684	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3685	if ( !pGuestPD
3686	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3687	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3688	#endif
3689	return pGuestPD;
3690	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3691	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3692	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3693	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3694	#endif
3695
3696	/* cache is out-of-sync. */
3697	PX86PDPAE pPD;
3698	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3699	if (RT_SUCCESS(rc))
3700	return pPD;
3701	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdpt].u));
3702	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3703	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3704	}
3705	return NULL;
3706	}
3707
3708
3709	/**
3710	* Gets the page directory entry for the specified address.
3711	*
3712	* @returns Pointer to the page directory entry in question.
3713	* @returns NULL if the page directory is not present or on an invalid page.
3714	* @param pPGM Pointer to the PGM instance data.
3715	* @param GCPtr The address.
3716	*/
3717	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3718	{
3719	AssertGCPtr32(GCPtr);
3720
3721	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3722	AssertReturn(pGuestPDPT, NULL);
3723	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3724	if (pGuestPDPT->a[iPdpt].n.u1Present)
3725	{
3726	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3727	#ifdef VBOX_WITH_NEW_PHYS_CODE
3728	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3729	PX86PDPAE pGuestPD = NULL;
3730	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3731	AssertRCReturn(rc, NULL);
3732	#else
3733	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3734	if ( !pGuestPD
3735	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3736	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3737	#endif
3738	return &pGuestPD->a[iPD];
3739	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3740	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3741	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3742	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdpt]->a[iPD];
3743	#endif
3744
3745	/* The cache is out-of-sync. */
3746	PX86PDPAE pPD;
3747	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3748	if (RT_SUCCESS(rc))
3749	return &pPD->a[iPD];
3750	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdpt].u));
3751	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3752	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3753	}
3754	return NULL;
3755	}
3756
3757
3758	/**
3759	* Gets the page directory entry for the specified address.
3760	*
3761	* @returns The page directory entry in question.
3762	* @returns A non-present entry if the page directory is not present or on an invalid page.
3763	* @param pPGM Pointer to the PGM instance data.
3764	* @param GCPtr The address.
3765	*/
3766	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3767	{
3768	AssertGCPtr32(GCPtr);
3769	X86PDEPAE ZeroPde = {0};
3770	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3771	if (RT_LIKELY(pGuestPDPT))
3772	{
3773	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3774	if (pGuestPDPT->a[iPdpt].n.u1Present)
3775	{
3776	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3777	#ifdef VBOX_WITH_NEW_PHYS_CODE
3778	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3779	PX86PDPAE pGuestPD = NULL;
3780	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3781	AssertRCReturn(rc, ZeroPde);
3782	#else
3783	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3784	if ( !pGuestPD
3785	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3786	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3787	#endif
3788	return pGuestPD->a[iPD];
3789	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3790	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3791	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3792	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt]->a[iPD];
3793	#endif
3794
3795	/* cache is out-of-sync. */
3796	PX86PDPAE pPD;
3797	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3798	if (RT_SUCCESS(rc))
3799	return pPD->a[iPD];
3800	AssertMsgFailed(("Impossible! rc=%d PDPE=%RX64\n", rc, pGuestPDPT->a[iPdpt].u));
3801	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3802	}
3803	}
3804	return ZeroPde;
3805	}
3806
3807
3808	/**
3809	* Gets the page directory pointer table entry for the specified address
3810	* and returns the index into the page directory
3811	*
3812	* @returns Pointer to the page directory in question.
3813	* @returns NULL if the page directory is not present or on an invalid page.
3814	* @param pPGM Pointer to the PGM instance data.
3815	* @param GCPtr The address.
3816	* @param piPD Receives the index into the returned page directory
3817	* @param pPdpe Receives the page directory pointer entry. Optional.
3818	*/
3819	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3820	{
3821	AssertGCPtr32(GCPtr);
3822
3823	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3824	AssertReturn(pGuestPDPT, NULL);
3825	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3826	if (pPdpe)
3827	*pPdpe = pGuestPDPT->a[iPdpt];
3828	if (pGuestPDPT->a[iPdpt].n.u1Present)
3829	{
3830	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3831	#ifdef VBOX_WITH_NEW_PHYS_CODE
3832	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3833	PX86PDPAE pGuestPD = NULL;
3834	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3835	AssertRCReturn(rc, NULL);
3836	#else
3837	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3838	if ( !pGuestPD
3839	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3840	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3841	#endif
3842	*piPD = iPD;
3843	return pGuestPD;
3844	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3845	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3846	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3847	{
3848	*piPD = iPD;
3849	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3850	}
3851	#endif
3852
3853	/* cache is out-of-sync. */
3854	PX86PDPAE pPD;
3855	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3856	if (RT_SUCCESS(rc))
3857	{
3858	*piPD = iPD;
3859	return pPD;
3860	}
3861	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdpt].u));
3862	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3863	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3864	}
3865	return NULL;
3866	}
3867
3868	#ifndef IN_RC
3869
3870	/**
3871	* Gets the page map level-4 pointer for the guest.
3872	*
3873	* @returns Pointer to the PML4 page.
3874	* @param pPGM Pointer to the PGM instance data.
3875	*/
3876	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3877	{
3878	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3879	PX86PML4 pGuestPml4;
3880	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3881	AssertRCReturn(rc, NULL);
3882	#else
3883	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3884	# ifdef VBOX_WITH_NEW_PHYS_CODE
3885	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3886	if (!pGuestPml4)
3887	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3888	# endif
3889	# endif
3890	Assert(pGuestPml4);
3891	#endif
3892	return pGuestPml4;
3893	}
3894
3895
3896	/**
3897	* Gets the pointer to a page map level-4 entry.
3898	*
3899	* @returns Pointer to the PML4 entry.
3900	* @param pPGM Pointer to the PGM instance data.
3901	* @param iPml4 The index.
3902	*/
3903	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3904	{
3905	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3906	PX86PML4 pGuestPml4;
3907	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3908	AssertRCReturn(rc, NULL);
3909	#else
3910	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3911	# ifdef VBOX_WITH_NEW_PHYS_CODE
3912	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3913	if (!pGuestPml4)
3914	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3915	# endif
3916	# endif
3917	Assert(pGuestPml4);
3918	#endif
3919	return &pGuestPml4->a[iPml4];
3920	}
3921
3922
3923	/**
3924	* Gets a page map level-4 entry.
3925	*
3926	* @returns The PML4 entry.
3927	* @param pPGM Pointer to the PGM instance data.
3928	* @param iPml4 The index.
3929	*/
3930	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3931	{
3932	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3933	PX86PML4 pGuestPml4;
3934	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3935	if (RT_FAILURE(rc))
3936	{
3937	X86PML4E ZeroPml4e = {0};
3938	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3939	}
3940	#else
3941	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3942	# ifdef VBOX_WITH_NEW_PHYS_CODE
3943	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3944	if (!pGuestPml4)
3945	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3946	# endif
3947	# endif
3948	Assert(pGuestPml4);
3949	#endif
3950	return pGuestPml4->a[iPml4];
3951	}
3952
3953
3954	/**
3955	* Gets the page directory pointer entry for the specified address.
3956	*
3957	* @returns Pointer to the page directory pointer entry in question.
3958	* @returns NULL if the page directory is not present or on an invalid page.
3959	* @param pPGM Pointer to the PGM instance data.
3960	* @param GCPtr The address.
3961	* @param ppPml4e Page Map Level-4 Entry (out)
3962	*/
3963	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3964	{
3965	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3966	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3967	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3968	if (pPml4e->n.u1Present)
3969	{
3970	PX86PDPT pPdpt;
3971	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3972	AssertRCReturn(rc, NULL);
3973
3974	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3975	return &pPdpt->a[iPdpt];
3976	}
3977	return NULL;
3978	}
3979
3980
3981	/**
3982	* Gets the page directory entry for the specified address.
3983	*
3984	* @returns The page directory entry in question.
3985	* @returns A non-present entry if the page directory is not present or on an invalid page.
3986	* @param pPGM Pointer to the PGM instance data.
3987	* @param GCPtr The address.
3988	* @param ppPml4e Page Map Level-4 Entry (out)
3989	* @param pPdpe Page directory pointer table entry (out)
3990	*/
3991	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3992	{
3993	X86PDEPAE ZeroPde = {0};
3994	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3995	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3996	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3997	if (pPml4e->n.u1Present)
3998	{
3999	PCX86PDPT pPdptTemp;
4000	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4001	AssertRCReturn(rc, ZeroPde);
4002
4003	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4004	*pPdpe = pPdptTemp->a[iPdpt];
4005	if (pPdptTemp->a[iPdpt].n.u1Present)
4006	{
4007	PCX86PDPAE pPD;
4008	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4009	AssertRCReturn(rc, ZeroPde);
4010
4011	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4012	return pPD->a[iPD];
4013	}
4014	}
4015
4016	return ZeroPde;
4017	}
4018
4019
4020	/**
4021	* Gets the page directory entry for the specified address.
4022	*
4023	* @returns The page directory entry in question.
4024	* @returns A non-present entry if the page directory is not present or on an invalid page.
4025	* @param pPGM Pointer to the PGM instance data.
4026	* @param GCPtr The address.
4027	*/
4028	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4029	{
4030	X86PDEPAE ZeroPde = {0};
4031	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4032	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4033	if (pGuestPml4->a[iPml4].n.u1Present)
4034	{
4035	PCX86PDPT pPdptTemp;
4036	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4037	AssertRCReturn(rc, ZeroPde);
4038
4039	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4040	if (pPdptTemp->a[iPdpt].n.u1Present)
4041	{
4042	PCX86PDPAE pPD;
4043	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4044	AssertRCReturn(rc, ZeroPde);
4045
4046	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4047	return pPD->a[iPD];
4048	}
4049	}
4050	return ZeroPde;
4051	}
4052
4053
4054	/**
4055	* Gets the page directory entry for the specified address.
4056	*
4057	* @returns Pointer to the page directory entry in question.
4058	* @returns NULL if the page directory is not present or on an invalid page.
4059	* @param pPGM Pointer to the PGM instance data.
4060	* @param GCPtr The address.
4061	*/
4062	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4063	{
4064	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4065	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4066	if (pGuestPml4->a[iPml4].n.u1Present)
4067	{
4068	PCX86PDPT pPdptTemp;
4069	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4070	AssertRCReturn(rc, NULL);
4071
4072	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4073	if (pPdptTemp->a[iPdpt].n.u1Present)
4074	{
4075	PX86PDPAE pPD;
4076	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4077	AssertRCReturn(rc, NULL);
4078
4079	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4080	return &pPD->a[iPD];
4081	}
4082	}
4083	return NULL;
4084	}
4085
4086
4087	/**
4088	* Gets the GUEST page directory pointer for the specified address.
4089	*
4090	* @returns The page directory in question.
4091	* @returns NULL if the page directory is not present or on an invalid page.
4092	* @param pPGM Pointer to the PGM instance data.
4093	* @param GCPtr The address.
4094	* @param ppPml4e Page Map Level-4 Entry (out)
4095	* @param pPdpe Page directory pointer table entry (out)
4096	* @param piPD Receives the index into the returned page directory
4097	*/
4098	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4099	{
4100	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4101	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4102	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4103	if (pPml4e->n.u1Present)
4104	{
4105	PCX86PDPT pPdptTemp;
4106	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4107	AssertRCReturn(rc, NULL);
4108
4109	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4110	*pPdpe = pPdptTemp->a[iPdpt];
4111	if (pPdptTemp->a[iPdpt].n.u1Present)
4112	{
4113	PX86PDPAE pPD;
4114	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4115	AssertRCReturn(rc, NULL);
4116
4117	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4118	return pPD;
4119	}
4120	}
4121	return 0;
4122	}
4123
4124	#endif /* !IN_RC */
4125
4126	/**
4127	* Gets the shadow page directory, 32-bit.
4128	*
4129	* @returns Pointer to the shadow 32-bit PD.
4130	* @param pPGM Pointer to the PGM instance data.
4131	*/
4132	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4133	{
4134	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4135	}
4136
4137
4138	/**
4139	* Gets the shadow page directory entry for the specified address, 32-bit.
4140	*
4141	* @returns Shadow 32-bit PDE.
4142	* @param pPGM Pointer to the PGM instance data.
4143	* @param GCPtr The address.
4144	*/
4145	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4146	{
4147	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4148
4149	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4150	if (!pShwPde)
4151	{
4152	X86PDE ZeroPde = {0};
4153	return ZeroPde;
4154	}
4155	return pShwPde->a[iPd];
4156	}
4157
4158
4159	/**
4160	* Gets the pointer to the shadow page directory entry for the specified
4161	* address, 32-bit.
4162	*
4163	* @returns Pointer to the shadow 32-bit PDE.
4164	* @param pPGM Pointer to the PGM instance data.
4165	* @param GCPtr The address.
4166	*/
4167	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4168	{
4169	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4170
4171	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4172	AssertReturn(pPde, NULL);
4173	return &pPde->a[iPd];
4174	}
4175
4176
4177	/**
4178	* Gets the shadow page pointer table, PAE.
4179	*
4180	* @returns Pointer to the shadow PAE PDPT.
4181	* @param pPGM Pointer to the PGM instance data.
4182	*/
4183	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4184	{
4185	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4186	}
4187
4188
4189	/**
4190	* Gets the shadow page directory for the specified address, PAE.
4191	*
4192	* @returns Pointer to the shadow PD.
4193	* @param pPGM Pointer to the PGM instance data.
4194	* @param GCPtr The address.
4195	*/
4196	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4197	{
4198	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4199	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4200
4201	if (!pPdpt->a[iPdpt].n.u1Present)
4202	return NULL;
4203
4204	/* Fetch the pgm pool shadow descriptor. */
4205	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4206	AssertReturn(pShwPde, NULL);
4207
4208	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4209	}
4210
4211
4212	/**
4213	* Gets the shadow page directory for the specified address, PAE.
4214	*
4215	* @returns Pointer to the shadow PD.
4216	* @param pPGM Pointer to the PGM instance data.
4217	* @param GCPtr The address.
4218	*/
4219	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4220	{
4221	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4222
4223	if (!pPdpt->a[iPdpt].n.u1Present)
4224	return NULL;
4225
4226	/* Fetch the pgm pool shadow descriptor. */
4227	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4228	AssertReturn(pShwPde, NULL);
4229
4230	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4231	}
4232
4233
4234	/**
4235	* Gets the shadow page directory entry, PAE.
4236	*
4237	* @returns PDE.
4238	* @param pPGM Pointer to the PGM instance data.
4239	* @param GCPtr The address.
4240	*/
4241	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4242	{
4243	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4244
4245	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4246	if (!pShwPde)
4247	{
4248	X86PDEPAE ZeroPde = {0};
4249	return ZeroPde;
4250	}
4251	return pShwPde->a[iPd];
4252	}
4253
4254
4255	/**
4256	* Gets the pointer to the shadow page directory entry for an address, PAE.
4257	*
4258	* @returns Pointer to the PDE.
4259	* @param pPGM Pointer to the PGM instance data.
4260	* @param GCPtr The address.
4261	*/
4262	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4263	{
4264	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4265
4266	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4267	AssertReturn(pPde, NULL);
4268	return &pPde->a[iPd];
4269	}
4270
4271	#ifndef IN_RC
4272
4273	/**
4274	* Gets the shadow page map level-4 pointer.
4275	*
4276	* @returns Pointer to the shadow PML4.
4277	* @param pPGM Pointer to the PGM instance data.
4278	*/
4279	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4280	{
4281	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4282	}
4283
4284
4285	/**
4286	* Gets the shadow page map level-4 entry for the specified address.
4287	*
4288	* @returns The entry.
4289	* @param pPGM Pointer to the PGM instance data.
4290	* @param GCPtr The address.
4291	*/
4292	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4293	{
4294	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4295	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4296
4297	if (!pShwPml4)
4298	{
4299	X86PML4E ZeroPml4e = {0};
4300	return ZeroPml4e;
4301	}
4302	return pShwPml4->a[iPml4];
4303	}
4304
4305
4306	/**
4307	* Gets the pointer to the specified shadow page map level-4 entry.
4308	*
4309	* @returns The entry.
4310	* @param pPGM Pointer to the PGM instance data.
4311	* @param iPml4 The PML4 index.
4312	*/
4313	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4314	{
4315	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4316	if (!pShwPml4)
4317	return NULL;
4318	return &pShwPml4->a[iPml4];
4319	}
4320
4321
4322	/**
4323	* Gets the GUEST page directory pointer for the specified address.
4324	*
4325	* @returns The page directory in question.
4326	* @returns NULL if the page directory is not present or on an invalid page.
4327	* @param pPGM Pointer to the PGM instance data.
4328	* @param GCPtr The address.
4329	* @param piPD Receives the index into the returned page directory
4330	*/
4331	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4332	{
4333	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4334	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4335	if (pGuestPml4->a[iPml4].n.u1Present)
4336	{
4337	PCX86PDPT pPdptTemp;
4338	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4339	AssertRCReturn(rc, NULL);
4340
4341	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4342	if (pPdptTemp->a[iPdpt].n.u1Present)
4343	{
4344	PX86PDPAE pPD;
4345	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4346	AssertRCReturn(rc, NULL);
4347
4348	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4349	return pPD;
4350	}
4351	}
4352	return NULL;
4353	}
4354
4355	#endif /* !IN_RC */
4356
4357	/**
4358	* Gets the page state for a physical handler.
4359	*
4360	* @returns The physical handler page state.
4361	* @param pCur The physical handler in question.
4362	*/
4363	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4364	{
4365	switch (pCur->enmType)
4366	{
4367	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4368	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4369
4370	case PGMPHYSHANDLERTYPE_MMIO:
4371	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4372	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4373
4374	default:
4375	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4376	}
4377	}
4378
4379
4380	/**
4381	* Gets the page state for a virtual handler.
4382	*
4383	* @returns The virtual handler page state.
4384	* @param pCur The virtual handler in question.
4385	* @remarks This should never be used on a hypervisor access handler.
4386	*/
4387	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4388	{
4389	switch (pCur->enmType)
4390	{
4391	case PGMVIRTHANDLERTYPE_WRITE:
4392	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4393	case PGMVIRTHANDLERTYPE_ALL:
4394	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4395	default:
4396	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4397	}
4398	}
4399
4400
4401	/**
4402	* Clears one physical page of a virtual handler
4403	*
4404	* @param pPGM Pointer to the PGM instance.
4405	* @param pCur Virtual handler structure
4406	* @param iPage Physical page index
4407	*
4408	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4409	* need to care about other handlers in the same page.
4410	*/
4411	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4412	{
4413	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4414
4415	/*
4416	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4417	*/
4418	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4419	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4420	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4421	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4422	#endif
4423	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4424	{
4425	/* We're the head of the alias chain. */
4426	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4427	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4428	AssertReleaseMsg(pRemove != NULL,
4429	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4430	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4431	AssertReleaseMsg(pRemove == pPhys2Virt,
4432	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4433	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4434	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4435	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4436	#endif
4437	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4438	{
4439	/* Insert the next list in the alias chain into the tree. */
4440	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4441	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4442	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4443	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4444	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4445	#endif
4446	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4447	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4448	AssertRelease(fRc);
4449	}
4450	}
4451	else
4452	{
4453	/* Locate the previous node in the alias chain. */
4454	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4455	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4456	AssertReleaseMsg(pPrev != pPhys2Virt,
4457	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4458	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4459	#endif
4460	for (;;)
4461	{
4462	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4463	if (pNext == pPhys2Virt)
4464	{
4465	/* unlink. */
4466	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4467	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4468	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4469	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4470	else
4471	{
4472	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4473	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4474	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4475	}
4476	break;
4477	}
4478
4479	/* next */
4480	if (pNext == pPrev)
4481	{
4482	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4483	AssertReleaseMsg(pNext != pPrev,
4484	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4485	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4486	#endif
4487	break;
4488	}
4489	pPrev = pNext;
4490	}
4491	}
4492	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4493	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4494	pPhys2Virt->offNextAlias = 0;
4495	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4496
4497	/*
4498	* Clear the ram flags for this page.
4499	*/
4500	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4501	AssertReturnVoid(pPage);
4502	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4503	}
4504
4505
4506	/**
4507	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4508	*
4509	* @returns Pointer to the shadow page structure.
4510	* @param pPool The pool.
4511	* @param HCPhys The HC physical address of the shadow page.
4512	*/
4513	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4514	{
4515	/*
4516	* Look up the page.
4517	*/
4518	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4519	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4520	return pPage;
4521	}
4522
4523
4524	/**
4525	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4526	*
4527	* @returns Pointer to the shadow page structure.
4528	* @param pPool The pool.
4529	* @param idx The pool page index.
4530	*/
4531	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4532	{
4533	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4534	return &pPool->aPages[idx];
4535	}
4536
4537
4538	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4539	/**
4540	* Clear references to guest physical memory.
4541	*
4542	* @param pPool The pool.
4543	* @param pPoolPage The pool page.
4544	* @param pPhysPage The physical guest page tracking structure.
4545	*/
4546	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4547	{
4548	/*
4549	* Just deal with the simple case here.
4550	*/
4551	# ifdef LOG_ENABLED
4552	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4553	# endif
4554	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4555	if (cRefs == 1)
4556	{
4557	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4558	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4559	}
4560	else
4561	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4562	Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4563	}
4564	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4565
4566
4567	#ifdef PGMPOOL_WITH_CACHE
4568	/**
4569	* Moves the page to the head of the age list.
4570	*
4571	* This is done when the cached page is used in one way or another.
4572	*
4573	* @param pPool The pool.
4574	* @param pPage The cached page.
4575	* @todo inline in PGMInternal.h!
4576	*/
4577	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4578	{
4579	/*
4580	* Move to the head of the age list.
4581	*/
4582	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4583	{
4584	/* unlink */
4585	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4586	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4587	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4588	else
4589	pPool->iAgeTail = pPage->iAgePrev;
4590
4591	/* insert at head */
4592	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4593	pPage->iAgeNext = pPool->iAgeHead;
4594	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4595	pPool->iAgeHead = pPage->idx;
4596	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4597	}
4598	}
4599	#endif /* PGMPOOL_WITH_CACHE */
4600
4601	/**
4602	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4603	*
4604	* @param pVM VM Handle.
4605	* @param pPage PGM pool page
4606	*/
4607	DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4608	{
4609	Assert(!pPage->fLocked);
4610	pPage->fLocked = true;
4611	}
4612
4613
4614	/**
4615	* Unlocks a page to allow flushing again
4616	*
4617	* @param pVM VM Handle.
4618	* @param pPage PGM pool page
4619	*/
4620	DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4621	{
4622	Assert(pPage->fLocked);
4623	pPage->fLocked = false;
4624	}
4625
4626
4627	/**
4628	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4629	*
4630	* @returns VBox status code.
4631	* @param pPage PGM pool page
4632	*/
4633	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4634	{
4635	if (pPage->fLocked)
4636	{
4637	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4638	if (pPage->cModifications)
4639	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4640	return true;
4641	}
4642	return false;
4643	}
4644
4645	/**
4646	* Tells if mappings are to be put into the shadow page table or not
4647	*
4648	* @returns boolean result
4649	* @param pVM VM handle.
4650	*/
4651	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4652	{
4653	#ifdef IN_RING0
4654	/* There are no mappings in VT-x and AMD-V mode. */
4655	Assert(pPGM->fDisableMappings);
4656	return false;
4657	#else
4658	return !pPGM->fDisableMappings;
4659	#endif
4660	}
4661
4662	/** @} */
4663
4664	#endif
4665

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 18291

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