PGMInternal.h@ 18344

Last change on this file since 18344 was 18344, checked in by vboxsync, 16 years ago
PGMInternal.h: build fix for the old phys code.
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1	/* $Id: PGMInternal.h 18344 2009-03-26 18:35:33Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/**
57	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58	* Comment it if it will break something.
59	*/
60	#define PGM_OUT_OF_SYNC_IN_GC
61
62	/**
63	* Check and skip global PDEs for non-global flushes
64	*/
65	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67	/**
68	* Sync N pages instead of a whole page table
69	*/
70	#define PGM_SYNC_N_PAGES
71
72	/**
73	* Number of pages to sync during a page fault
74	*
75	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77	*/
78	#define PGM_SYNC_NR_PAGES 8
79
80	/**
81	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82	*/
83	#define PGM_MAX_PHYSCACHE_ENTRIES 64
84	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86	/**
87	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88	*/
89	#define PGM_PHYSMEMACCESS_CACHING
90
91	/** @def PGMPOOL_WITH_CACHE
92	* Enable agressive caching using the page pool.
93	*
94	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95	*/
96	#define PGMPOOL_WITH_CACHE
97
98	/** @def PGMPOOL_WITH_MIXED_PT_CR3
99	* When defined, we'll deal with 'uncachable' pages.
100	*/
101	#ifdef PGMPOOL_WITH_CACHE
102	# define PGMPOOL_WITH_MIXED_PT_CR3
103	#endif
104
105	/** @def PGMPOOL_WITH_MONITORING
106	* Monitor the guest pages which are shadowed.
107	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108	* be enabled as well.
109	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110	*/
111	#ifdef PGMPOOL_WITH_CACHE
112	# define PGMPOOL_WITH_MONITORING
113	#endif
114
115	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116	* Tracking the of shadow pages mapping guest physical pages.
117	*
118	* This is very expensive, the current cache prototype is trying to figure out
119	* whether it will be acceptable with an agressive caching policy.
120	*/
121	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
122	# define PGMPOOL_WITH_GCPHYS_TRACKING
123	#endif
124
125	/** @def PGMPOOL_WITH_USER_TRACKING
126	* Tracking users of shadow pages. This is required for the linking of shadow page
127	* tables and physical guest addresses.
128	*/
129	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
130	# define PGMPOOL_WITH_USER_TRACKING
131	#endif
132
133	/** @def PGMPOOL_CFG_MAX_GROW
134	* The maximum number of pages to add to the pool in one go.
135	*/
136	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
140	*/
141	#ifdef VBOX_STRICT
142	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143	#endif
144
145	#ifdef VBOX_WITH_NEW_PHYS_CODE
146	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
147	* Enables the experimental lazy page allocation code. */
148	/# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
149	#endif
150	/** @} */
151
152
153	/** @name PDPT and PML4 flags.
154	* These are placed in the three bits available for system programs in
155	* the PDPT and PML4 entries.
156	* @{ */
157	/** The entry is a permanent one and it's must always be present.
158	* Never free such an entry. */
159	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
160	/** Mapping (hypervisor allocated pagetable). */
161	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
162	/** @} */
163
164	/** @name Page directory flags.
165	* These are placed in the three bits available for system programs in
166	* the page directory entries.
167	* @{ */
168	/** Mapping (hypervisor allocated pagetable). */
169	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
170	/** Made read-only to facilitate dirty bit tracking. */
171	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
172	/** @} */
173
174	/** @name Page flags.
175	* These are placed in the three bits available for system programs in
176	* the page entries.
177	* @{ */
178	/** Made read-only to facilitate dirty bit tracking. */
179	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
180
181	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
182	/** Scanned and approved by CSAM (tm).
183	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
184	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
185	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
186	#endif
187
188	/** @} */
189
190	/** @name Defines used to indicate the shadow and guest paging in the templates.
191	* @{ */
192	#define PGM_TYPE_REAL 1
193	#define PGM_TYPE_PROT 2
194	#define PGM_TYPE_32BIT 3
195	#define PGM_TYPE_PAE 4
196	#define PGM_TYPE_AMD64 5
197	#define PGM_TYPE_NESTED 6
198	#define PGM_TYPE_EPT 7
199	#define PGM_TYPE_MAX PGM_TYPE_EPT
200	/** @} */
201
202	/** Macro for checking if the guest is using paging.
203	* @param uGstType PGM_TYPE_*
204	* @param uShwType PGM_TYPE_*
205	* @remark ASSUMES certain order of the PGM_TYPE_* values.
206	*/
207	#define PGM_WITH_PAGING(uGstType, uShwType) \
208	( (uGstType) >= PGM_TYPE_32BIT \
209	&& (uShwType) != PGM_TYPE_NESTED \
210	&& (uShwType) != PGM_TYPE_EPT)
211
212	/** Macro for checking if the guest supports the NX bit.
213	* @param uGstType PGM_TYPE_*
214	* @param uShwType PGM_TYPE_*
215	* @remark ASSUMES certain order of the PGM_TYPE_* values.
216	*/
217	#define PGM_WITH_NX(uGstType, uShwType) \
218	( (uGstType) >= PGM_TYPE_PAE \
219	&& (uShwType) != PGM_TYPE_NESTED \
220	&& (uShwType) != PGM_TYPE_EPT)
221
222
223	/** @def PGM_HCPHYS_2_PTR
224	* Maps a HC physical page pool address to a virtual address.
225	*
226	* @returns VBox status code.
227	* @param pVM The VM handle.
228	* @param HCPhys The HC physical address to map to a virtual one.
229	* @param ppv Where to store the virtual address. No need to cast this.
230	*
231	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
232	* small page window employeed by that function. Be careful.
233	* @remark There is no need to assert on the result.
234	*/
235	#ifdef IN_RC
236	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
237	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
238	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
239	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
240	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
241	#else
242	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
243	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
244	#endif
245
246	/** @def PGM_HCPHYS_2_PTR_BY_PGM
247	* Maps a HC physical page pool address to a virtual address.
248	*
249	* @returns VBox status code.
250	* @param pPGM The PGM instance data.
251	* @param HCPhys The HC physical address to map to a virtual one.
252	* @param ppv Where to store the virtual address. No need to cast this.
253	*
254	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
255	* small page window employeed by that function. Be careful.
256	* @remark There is no need to assert on the result.
257	*/
258	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
259	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
260	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
261	#else
262	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
263	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
264	#endif
265
266	/** @def PGM_GCPHYS_2_PTR
267	* Maps a GC physical page address to a virtual address.
268	*
269	* @returns VBox status code.
270	* @param pVM The VM handle.
271	* @param GCPhys The GC physical address to map to a virtual one.
272	* @param ppv Where to store the virtual address. No need to cast this.
273	*
274	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
275	* small page window employeed by that function. Be careful.
276	* @remark There is no need to assert on the result.
277	*/
278	#ifdef IN_RC
279	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
280	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
281	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
282	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
283	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
284	#else
285	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
286	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
287	#endif
288
289	/** @def PGM_GCPHYS_2_PTR_BY_PGM
290	* Maps a GC physical page address to a virtual address.
291	*
292	* @returns VBox status code.
293	* @param pPGM Pointer to the PGM instance data.
294	* @param GCPhys The GC physical address to map to a virtual one.
295	* @param ppv Where to store the virtual address. No need to cast this.
296	*
297	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
298	* small page window employeed by that function. Be careful.
299	* @remark There is no need to assert on the result.
300	*/
301	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
302	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
303	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
304	#else
305	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
306	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
307	#endif
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM The VM handle.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
318	* small page window employeed by that function. Be careful.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
327	#endif
328
329	/** @def PGM_INVL_PG
330	* Invalidates a page when in GC does nothing in HC.
331	*
332	* @param GCVirt The virtual address of the page to invalidate.
333	*/
334	#ifdef IN_RC
335	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
336	#elif defined(IN_RING0)
337	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
338	#else
339	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340	#endif
341
342	/** @def PGM_INVL_BIG_PG
343	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
344	*
345	* @param GCVirt The virtual address within the page directory to invalidate.
346	*/
347	#ifdef IN_RC
348	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
349	#elif defined(IN_RING0)
350	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
351	#else
352	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353	#endif
354
355	/** @def PGM_INVL_GUEST_TLBS()
356	* Invalidates all guest TLBs.
357	*/
358	#ifdef IN_RC
359	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
360	#elif defined(IN_RING0)
361	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
362	#else
363	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364	#endif
365
366	/** Size of the GCPtrConflict array in PGMMAPPING.
367	* @remarks Must be a power of two. */
368	#define PGMMAPPING_CONFLICT_MAX 8
369
370	/**
371	* Structure for tracking GC Mappings.
372	*
373	* This structure is used by linked list in both GC and HC.
374	*/
375	typedef struct PGMMAPPING
376	{
377	/** Pointer to next entry. */
378	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
379	/** Pointer to next entry. */
380	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
381	/** Pointer to next entry. */
382	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
383	/** Indicate whether this entry is finalized. */
384	bool fFinalized;
385	/** Start Virtual address. */
386	RTGCPTR GCPtr;
387	/** Last Virtual address (inclusive). */
388	RTGCPTR GCPtrLast;
389	/** Range size (bytes). */
390	RTGCPTR cb;
391	/** Pointer to relocation callback function. */
392	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
393	/** User argument to the callback. */
394	R3PTRTYPE(void *) pvUser;
395	/** Mapping description / name. For easing debugging. */
396	R3PTRTYPE(const char *) pszDesc;
397	/** Last 8 addresses that caused conflicts. */
398	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
399	/** Number of conflicts for this hypervisor mapping. */
400	uint32_t cConflicts;
401	/** Number of page tables. */
402	uint32_t cPTs;
403
404	/** Array of page table mapping data. Each entry
405	* describes one page table. The array can be longer
406	* than the declared length.
407	*/
408	struct
409	{
410	/** The HC physical address of the page table. */
411	RTHCPHYS HCPhysPT;
412	/** The HC physical address of the first PAE page table. */
413	RTHCPHYS HCPhysPaePT0;
414	/** The HC physical address of the second PAE page table. */
415	RTHCPHYS HCPhysPaePT1;
416	/** The HC virtual address of the 32-bit page table. */
417	R3PTRTYPE(PX86PT) pPTR3;
418	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
419	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
420	/** The GC virtual address of the 32-bit page table. */
421	RCPTRTYPE(PX86PT) pPTRC;
422	/** The GC virtual address of the two PAE page table. */
423	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
424	/** The GC virtual address of the 32-bit page table. */
425	R0PTRTYPE(PX86PT) pPTR0;
426	/** The GC virtual address of the two PAE page table. */
427	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
428	} aPTs[1];
429	} PGMMAPPING;
430	/** Pointer to structure for tracking GC Mappings. */
431	typedef struct PGMMAPPING *PPGMMAPPING;
432
433
434	/**
435	* Physical page access handler structure.
436	*
437	* This is used to keep track of physical address ranges
438	* which are being monitored in some kind of way.
439	*/
440	typedef struct PGMPHYSHANDLER
441	{
442	AVLROGCPHYSNODECORE Core;
443	/** Access type. */
444	PGMPHYSHANDLERTYPE enmType;
445	/** Number of pages to update. */
446	uint32_t cPages;
447	/** Pointer to R3 callback function. */
448	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
449	/** User argument for R3 handlers. */
450	R3PTRTYPE(void *) pvUserR3;
451	/** Pointer to R0 callback function. */
452	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
453	/** User argument for R0 handlers. */
454	R0PTRTYPE(void *) pvUserR0;
455	/** Pointer to GC callback function. */
456	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
457	/** User argument for RC handlers. */
458	RCPTRTYPE(void *) pvUserRC;
459	/** Description / Name. For easing debugging. */
460	R3PTRTYPE(const char *) pszDesc;
461	#ifdef VBOX_WITH_STATISTICS
462	/** Profiling of this handler. */
463	STAMPROFILE Stat;
464	#endif
465	} PGMPHYSHANDLER;
466	/** Pointer to a physical page access handler structure. */
467	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
468
469
470	/**
471	* Cache node for the physical addresses covered by a virtual handler.
472	*/
473	typedef struct PGMPHYS2VIRTHANDLER
474	{
475	/** Core node for the tree based on physical ranges. */
476	AVLROGCPHYSNODECORE Core;
477	/** Offset from this struct to the PGMVIRTHANDLER structure. */
478	int32_t offVirtHandler;
479	/** Offset of the next alias relative to this one.
480	* Bit 0 is used for indicating whether we're in the tree.
481	* Bit 1 is used for indicating that we're the head node.
482	*/
483	int32_t offNextAlias;
484	} PGMPHYS2VIRTHANDLER;
485	/** Pointer to a phys to virtual handler structure. */
486	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
487
488	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489	* node is in the tree. */
490	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
491	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
492	* node is in the head of an alias chain.
493	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
494	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
495	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
496	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
497
498
499	/**
500	* Virtual page access handler structure.
501	*
502	* This is used to keep track of virtual address ranges
503	* which are being monitored in some kind of way.
504	*/
505	typedef struct PGMVIRTHANDLER
506	{
507	/** Core node for the tree based on virtual ranges. */
508	AVLROGCPTRNODECORE Core;
509	/** Size of the range (in bytes). */
510	RTGCPTR cb;
511	/** Number of cache pages. */
512	uint32_t cPages;
513	/** Access type. */
514	PGMVIRTHANDLERTYPE enmType;
515	/** Pointer to the RC callback function. */
516	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
517	#if HC_ARCH_BITS == 64
518	RTRCPTR padding;
519	#endif
520	/** Pointer to the R3 callback function for invalidation. */
521	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
522	/** Pointer to the R3 callback function. */
523	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
524	/** Description / Name. For easing debugging. */
525	R3PTRTYPE(const char *) pszDesc;
526	#ifdef VBOX_WITH_STATISTICS
527	/** Profiling of this handler. */
528	STAMPROFILE Stat;
529	#endif
530	/** Array of cached physical addresses for the monitored ranged. */
531	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
532	} PGMVIRTHANDLER;
533	/** Pointer to a virtual page access handler structure. */
534	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
535
536
537	/**
538	* Page type.
539	*
540	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
541	* @remarks This is used in the saved state, so changes to it requires bumping
542	* the saved state version.
543	* @todo So, convert to \#defines!
544	*/
545	typedef enum PGMPAGETYPE
546	{
547	/** The usual invalid zero entry. */
548	PGMPAGETYPE_INVALID = 0,
549	/** RAM page. (RWX) */
550	PGMPAGETYPE_RAM,
551	/** MMIO2 page. (RWX) */
552	PGMPAGETYPE_MMIO2,
553	/** MMIO2 page aliased over an MMIO page. (RWX)
554	* See PGMHandlerPhysicalPageAlias(). */
555	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
556	/** Shadowed ROM. (RWX) */
557	PGMPAGETYPE_ROM_SHADOW,
558	/** ROM page. (R-X) */
559	PGMPAGETYPE_ROM,
560	/** MMIO page. (---) */
561	PGMPAGETYPE_MMIO,
562	/** End of valid entries. */
563	PGMPAGETYPE_END
564	} PGMPAGETYPE;
565	AssertCompile(PGMPAGETYPE_END <= 7);
566
567	/** @name Page type predicates.
568	* @{ */
569	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
570	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
571	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
572	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
573	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
574	/** @} */
575
576
577	/**
578	* A Physical Guest Page tracking structure.
579	*
580	* The format of this structure is complicated because we have to fit a lot
581	* of information into as few bits as possible. The format is also subject
582	* to change (there is one comming up soon). Which means that for we'll be
583	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
584	* accessess to the structure.
585	*/
586	typedef struct PGMPAGE
587	{
588	/** The physical address and a whole lot of other stuff. All bits are used! */
589	#ifdef VBOX_WITH_NEW_PHYS_CODE
590	RTHCPHYS HCPhysX;
591	#else
592	RTHCPHYS HCPhys;
593	#define HCPhysX HCPhys /*< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. /
594	#endif
595	/** The page state. */
596	uint32_t u2StateX : 2;
597	/** Flag indicating that a write monitored page was written to when set. */
598	uint32_t fWrittenToX : 1;
599	/** For later. */
600	uint32_t fSomethingElse : 1;
601	/** The Page ID.
602	* @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
603	* The HCPhysX will then be 100% static. */
604	uint32_t idPageX : 28;
605	/** The page type (PGMPAGETYPE). */
606	uint32_t u3Type : 3;
607	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
608	uint32_t u2HandlerPhysStateX : 2;
609	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
610	uint32_t u2HandlerVirtStateX : 2;
611	uint32_t u29B : 25;
612	} PGMPAGE;
613	AssertCompileSize(PGMPAGE, 16);
614	/** Pointer to a physical guest page. */
615	typedef PGMPAGE *PPGMPAGE;
616	/** Pointer to a const physical guest page. */
617	typedef const PGMPAGE *PCPGMPAGE;
618	/** Pointer to a physical guest page pointer. */
619	typedef PPGMPAGE *PPPGMPAGE;
620
621
622	/**
623	* Clears the page structure.
624	* @param pPage Pointer to the physical guest page tracking structure.
625	*/
626	#define PGM_PAGE_CLEAR(pPage) \
627	do { \
628	(pPage)->HCPhysX = 0; \
629	(pPage)->u2StateX = 0; \
630	(pPage)->fWrittenToX = 0; \
631	(pPage)->fSomethingElse = 0; \
632	(pPage)->idPageX = 0; \
633	(pPage)->u3Type = 0; \
634	(pPage)->u29B = 0; \
635	} while (0)
636
637	/**
638	* Initializes the page structure.
639	* @param pPage Pointer to the physical guest page tracking structure.
640	*/
641	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
642	do { \
643	(pPage)->HCPhysX = (_HCPhys); \
644	(pPage)->u2StateX = (_uState); \
645	(pPage)->fWrittenToX = 0; \
646	(pPage)->fSomethingElse = 0; \
647	(pPage)->idPageX = (_idPage); \
648	/(pPage)->u3Type = (_uType); - later / \
649	PGM_PAGE_SET_TYPE(pPage, _uType); \
650	(pPage)->u29B = 0; \
651	} while (0)
652
653	/**
654	* Initializes the page structure of a ZERO page.
655	* @param pPage Pointer to the physical guest page tracking structure.
656	*/
657	#ifdef VBOX_WITH_NEW_PHYS_CODE
658	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
659	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
660	#else
661	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
662	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
663	#endif
664	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
665	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
666	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
667
668
669	/** @name The Page state, PGMPAGE::u2StateX.
670	* @{ */
671	/** The zero page.
672	* This is a per-VM page that's never ever mapped writable. */
673	#define PGM_PAGE_STATE_ZERO 0
674	/** A allocated page.
675	* This is a per-VM page allocated from the page pool (or wherever
676	* we get MMIO2 pages from if the type is MMIO2).
677	*/
678	#define PGM_PAGE_STATE_ALLOCATED 1
679	/** A allocated page that's being monitored for writes.
680	* The shadow page table mappings are read-only. When a write occurs, the
681	* fWrittenTo member is set, the page remapped as read-write and the state
682	* moved back to allocated. */
683	#define PGM_PAGE_STATE_WRITE_MONITORED 2
684	/** The page is shared, aka. copy-on-write.
685	* This is a page that's shared with other VMs. */
686	#define PGM_PAGE_STATE_SHARED 3
687	/** @} */
688
689
690	/**
691	* Gets the page state.
692	* @returns page state (PGM_PAGE_STATE_*).
693	* @param pPage Pointer to the physical guest page tracking structure.
694	*/
695	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
696
697	/**
698	* Sets the page state.
699	* @param pPage Pointer to the physical guest page tracking structure.
700	* @param _uState The new page state.
701	*/
702	#define PGM_PAGE_SET_STATE(pPage, _uState) \
703	do { (pPage)->u2StateX = (_uState); } while (0)
704
705
706	/**
707	* Gets the host physical address of the guest page.
708	* @returns host physical address (RTHCPHYS).
709	* @param pPage Pointer to the physical guest page tracking structure.
710	*/
711	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
712
713	/**
714	* Sets the host physical address of the guest page.
715	* @param pPage Pointer to the physical guest page tracking structure.
716	* @param _HCPhys The new host physical address.
717	*/
718	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
719	do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
720	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
721
722	/**
723	* Get the Page ID.
724	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
725	* @param pPage Pointer to the physical guest page tracking structure.
726	*/
727	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
728	/* later:
729	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
730	\| ((uint32_t)(pPage)->HCPhysX & 0xfff) )
731	*/
732	/**
733	* Sets the Page ID.
734	* @param pPage Pointer to the physical guest page tracking structure.
735	*/
736	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
737	/* later:
738	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
739	\| ((_idPage) & 0xfff) \
740	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
741	*/
742
743	/**
744	* Get the Chunk ID.
745	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
746	* @param pPage Pointer to the physical guest page tracking structure.
747	*/
748	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
749	/* later:
750	#if GMM_CHUNKID_SHIFT == 12
751	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
752	#elif GMM_CHUNKID_SHIFT > 12
753	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
754	#elif GMM_CHUNKID_SHIFT < 12
755	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
756	\| ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
757	#else
758	# error "GMM_CHUNKID_SHIFT isn't defined or something."
759	#endif
760	*/
761
762	/**
763	* Get the index of the page within the allocaiton chunk.
764	* @returns The page index.
765	* @param pPage Pointer to the physical guest page tracking structure.
766	*/
767	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
768	/* later:
769	#if GMM_CHUNKID_SHIFT <= 12
770	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
771	#else
772	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
773	\| ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
774	#endif
775	*/
776
777
778	/**
779	* Gets the page type.
780	* @returns The page type.
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
784
785	/**
786	* Sets the page type.
787	* @param pPage Pointer to the physical guest page tracking structure.
788	* @param _enmType The new page type (PGMPAGETYPE).
789	*/
790	#ifdef VBOX_WITH_NEW_PHYS_CODE
791	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
792	do { (pPage)->u3Type = (_enmType); } while (0)
793	#else
794	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
795	do { \
796	(pPage)->u3Type = (_enmType); \
797	if ((_enmType) == PGMPAGETYPE_ROM) \
798	(pPage)->HCPhysX \|= MM_RAM_FLAGS_ROM; \
799	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
800	(pPage)->HCPhysX \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
801	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
802	(pPage)->HCPhysX \|= MM_RAM_FLAGS_MMIO2; \
803	} while (0)
804	#endif
805
806
807	/**
808	* Checks if the page is 'reserved'.
809	* @returns true/false.
810	* @param pPage Pointer to the physical guest page tracking structure.
811	*/
812	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
813
814	/**
815	* Checks if the page is marked for MMIO.
816	* @returns true/false.
817	* @param pPage Pointer to the physical guest page tracking structure.
818	*/
819	#ifdef VBOX_WITH_NEW_PHYS_CODE
820	# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
821	#else
822	# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
823	#endif
824
825	/**
826	* Checks if the page is backed by the ZERO page.
827	* @returns true/false.
828	* @param pPage Pointer to the physical guest page tracking structure.
829	*/
830	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
831
832	/**
833	* Checks if the page is backed by a SHARED page.
834	* @returns true/false.
835	* @param pPage Pointer to the physical guest page tracking structure.
836	*/
837	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
838
839
840	/**
841	* Marks the paget as written to (for GMM change monitoring).
842	* @param pPage Pointer to the physical guest page tracking structure.
843	*/
844	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
845
846	/**
847	* Clears the written-to indicator.
848	* @param pPage Pointer to the physical guest page tracking structure.
849	*/
850	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
851
852	/**
853	* Checks if the page was marked as written-to.
854	* @returns true/false.
855	* @param pPage Pointer to the physical guest page tracking structure.
856	*/
857	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
858
859
860	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
861	*
862	* @remarks The values are assigned in order of priority, so we can calculate
863	* the correct state for a page with different handlers installed.
864	* @{ */
865	/** No handler installed. */
866	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
867	/** Monitoring is temporarily disabled. */
868	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
869	/** Write access is monitored. */
870	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
871	/** All access is monitored. */
872	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
873	/** @} */
874
875	/**
876	* Gets the physical access handler state of a page.
877	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
878	* @param pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
881
882	/**
883	* Sets the physical access handler state of a page.
884	* @param pPage Pointer to the physical guest page tracking structure.
885	* @param _uState The new state value.
886	*/
887	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
888	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
889
890	/**
891	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
892	* @returns true/false
893	* @param pPage Pointer to the physical guest page tracking structure.
894	*/
895	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
896
897	/**
898	* Checks if the page has any active physical access handlers.
899	* @returns true/false
900	* @param pPage Pointer to the physical guest page tracking structure.
901	*/
902	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
903
904
905	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
906	*
907	* @remarks The values are assigned in order of priority, so we can calculate
908	* the correct state for a page with different handlers installed.
909	* @{ */
910	/** No handler installed. */
911	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
912	/* 1 is reserved so the lineup is identical with the physical ones. */
913	/** Write access is monitored. */
914	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
915	/** All access is monitored. */
916	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
917	/** @} */
918
919	/**
920	* Gets the virtual access handler state of a page.
921	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
922	* @param pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
925
926	/**
927	* Sets the virtual access handler state of a page.
928	* @param pPage Pointer to the physical guest page tracking structure.
929	* @param _uState The new state value.
930	*/
931	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
932	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
933
934	/**
935	* Checks if the page has any virtual access handlers.
936	* @returns true/false
937	* @param pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
940
941	/**
942	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
943	* virtual handlers.
944	* @returns true/false
945	* @param pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
948
949
950
951	/**
952	* Checks if the page has any access handlers, including temporarily disabled ones.
953	* @returns true/false
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
957	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
958	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
959
960	/**
961	* Checks if the page has any active access handlers.
962	* @returns true/false
963	* @param pPage Pointer to the physical guest page tracking structure.
964	*/
965	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
966	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
967	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
968
969	/**
970	* Checks if the page has any active access handlers catching all accesses.
971	* @returns true/false
972	* @param pPage Pointer to the physical guest page tracking structure.
973	*/
974	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
975	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
976	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
977
978
979
980
981	/** @def PGM_PAGE_GET_TRACKING
982	* Gets the packed shadow page pool tracking data associated with a guest page.
983	* @returns uint16_t containing the data.
984	* @param pPage Pointer to the physical guest page tracking structure.
985	*/
986	#define PGM_PAGE_GET_TRACKING(pPage) \
987	( ((uint16_t )&(pPage)->HCPhysX + 3) )
988
989	/** @def PGM_PAGE_SET_TRACKING
990	* Sets the packed shadow page pool tracking data associated with a guest page.
991	* @param pPage Pointer to the physical guest page tracking structure.
992	* @param u16TrackingData The tracking data to store.
993	*/
994	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
995	do { ((uint16_t )&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
996
997	/** @def PGM_PAGE_GET_TD_CREFS
998	* Gets the @a cRefs tracking data member.
999	* @returns cRefs.
1000	* @param pPage Pointer to the physical guest page tracking structure.
1001	*/
1002	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1003	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1004
1005	#define PGM_PAGE_GET_TD_IDX(pPage) \
1006	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1007
1008	/**
1009	* Ram range for GC Phys to HC Phys conversion.
1010	*
1011	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1012	* conversions too, but we'll let MM handle that for now.
1013	*
1014	* This structure is used by linked lists in both GC and HC.
1015	*/
1016	typedef struct PGMRAMRANGE
1017	{
1018	/** Start of the range. Page aligned. */
1019	RTGCPHYS GCPhys;
1020	/** Size of the range. (Page aligned of course). */
1021	RTGCPHYS cb;
1022	/** Pointer to the next RAM range - for R3. */
1023	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1024	/** Pointer to the next RAM range - for R0. */
1025	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1026	/** Pointer to the next RAM range - for RC. */
1027	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1028	/** PGM_RAM_RANGE_FLAGS_* flags. */
1029	uint32_t fFlags;
1030	/** Last address in the range (inclusive). Page aligned (-1). */
1031	RTGCPHYS GCPhysLast;
1032	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1033	R3PTRTYPE(void *) pvR3;
1034	#ifndef VBOX_WITH_NEW_PHYS_CODE
1035	/** R3 virtual lookup ranges for chunks.
1036	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1037	* @remarks This is occationally accessed from ring-0!! (not darwin) */
1038	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1039	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1040	# else
1041	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1042	# endif
1043	#endif
1044	/** The range description. */
1045	R3PTRTYPE(const char *) pszDesc;
1046	/** Pointer to self - R0 pointer. */
1047	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1048	/** Pointer to self - RC pointer. */
1049	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1050	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1051	#ifdef VBOX_WITH_NEW_PHYS_CODE
1052	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1053	#else
1054	# if HC_ARCH_BITS == 32
1055	uint32_t u32Alignment2;
1056	# endif
1057	#endif
1058	/** Array of physical guest page tracking structures. */
1059	PGMPAGE aPages[1];
1060	} PGMRAMRANGE;
1061	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1062	typedef PGMRAMRANGE *PPGMRAMRANGE;
1063
1064	/** @name PGMRAMRANGE::fFlags
1065	* @{ */
1066	/** The RAM range is floating around as an independent guest mapping. */
1067	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1068	/** @} */
1069
1070	#ifndef VBOX_WITH_NEW_PHYS_CODE
1071	/** Return hc ptr corresponding to the ram range and physical offset */
1072	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1073	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1074	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1075	#endif
1076
1077	/**
1078	* Per page tracking structure for ROM image.
1079	*
1080	* A ROM image may have a shadow page, in which case we may have
1081	* two pages backing it. This structure contains the PGMPAGE for
1082	* both while PGMRAMRANGE have a copy of the active one. It is
1083	* important that these aren't out of sync in any regard other
1084	* than page pool tracking data.
1085	*/
1086	typedef struct PGMROMPAGE
1087	{
1088	/** The page structure for the virgin ROM page. */
1089	PGMPAGE Virgin;
1090	/** The page structure for the shadow RAM page. */
1091	PGMPAGE Shadow;
1092	/** The current protection setting. */
1093	PGMROMPROT enmProt;
1094	/** Pad the structure size to a multiple of 8. */
1095	uint32_t u32Padding;
1096	} PGMROMPAGE;
1097	/** Pointer to a ROM page tracking structure. */
1098	typedef PGMROMPAGE *PPGMROMPAGE;
1099
1100
1101	/**
1102	* A registered ROM image.
1103	*
1104	* This is needed to keep track of ROM image since they generally
1105	* intrude into a PGMRAMRANGE. It also keeps track of additional
1106	* info like the two page sets (read-only virgin and read-write shadow),
1107	* the current state of each page.
1108	*
1109	* Because access handlers cannot easily be executed in a different
1110	* context, the ROM ranges needs to be accessible and in all contexts.
1111	*/
1112	typedef struct PGMROMRANGE
1113	{
1114	/** Pointer to the next range - R3. */
1115	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1116	/** Pointer to the next range - R0. */
1117	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1118	/** Pointer to the next range - RC. */
1119	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1120	/** Pointer alignment */
1121	RTRCPTR GCPtrAlignment;
1122	/** Address of the range. */
1123	RTGCPHYS GCPhys;
1124	/** Address of the last byte in the range. */
1125	RTGCPHYS GCPhysLast;
1126	/** Size of the range. */
1127	RTGCPHYS cb;
1128	/** The flags (PGMPHYS_ROM_FLAG_). /
1129	uint32_t fFlags;
1130	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1131	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1132	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1133	* This is used for strictness checks. */
1134	R3PTRTYPE(const void *) pvOriginal;
1135	/** The ROM description. */
1136	R3PTRTYPE(const char *) pszDesc;
1137	/** The per page tracking structures. */
1138	PGMROMPAGE aPages[1];
1139	} PGMROMRANGE;
1140	/** Pointer to a ROM range. */
1141	typedef PGMROMRANGE *PPGMROMRANGE;
1142
1143
1144	/**
1145	* A registered MMIO2 (= Device RAM) range.
1146	*
1147	* There are a few reason why we need to keep track of these
1148	* registrations. One of them is the deregistration & cleanup
1149	* stuff, while another is that the PGMRAMRANGE associated with
1150	* such a region may have to be removed from the ram range list.
1151	*
1152	* Overlapping with a RAM range has to be 100% or none at all. The
1153	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1154	* meditation will be raised if a partial overlap or an overlap of
1155	* ROM pages is encountered. On an overlap we will free all the
1156	* existing RAM pages and put in the ram range pages instead.
1157	*/
1158	typedef struct PGMMMIO2RANGE
1159	{
1160	/** The owner of the range. (a device) */
1161	PPDMDEVINSR3 pDevInsR3;
1162	/** Pointer to the ring-3 mapping of the allocation. */
1163	RTR3PTR pvR3;
1164	/** Pointer to the next range - R3. */
1165	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1166	/** Whether it's mapped or not. */
1167	bool fMapped;
1168	/** Whether it's overlapping or not. */
1169	bool fOverlapping;
1170	/** The PCI region number.
1171	* @remarks This ASSUMES that nobody will ever really need to have multiple
1172	* PCI devices with matching MMIO region numbers on a single device. */
1173	uint8_t iRegion;
1174	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1175	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1176	/** The associated RAM range. */
1177	PGMRAMRANGE RamRange;
1178	} PGMMMIO2RANGE;
1179	/** Pointer to a MMIO2 range. */
1180	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1181
1182
1183
1184
1185	/**
1186	* PGMPhysRead/Write cache entry
1187	*/
1188	typedef struct PGMPHYSCACHEENTRY
1189	{
1190	/** R3 pointer to physical page. */
1191	R3PTRTYPE(uint8_t *) pbR3;
1192	/** GC Physical address for cache entry */
1193	RTGCPHYS GCPhys;
1194	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1195	RTGCPHYS u32Padding0; /*< alignment padding. /
1196	#endif
1197	} PGMPHYSCACHEENTRY;
1198
1199	/**
1200	* PGMPhysRead/Write cache to reduce REM memory access overhead
1201	*/
1202	typedef struct PGMPHYSCACHE
1203	{
1204	/** Bitmap of valid cache entries */
1205	uint64_t aEntries;
1206	/** Cache entries */
1207	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1208	} PGMPHYSCACHE;
1209
1210
1211	/** Pointer to an allocation chunk ring-3 mapping. */
1212	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1213	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1214	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1215
1216	/**
1217	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1218	*
1219	* The primary tree (Core) uses the chunk id as key.
1220	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1221	*/
1222	typedef struct PGMCHUNKR3MAP
1223	{
1224	/** The key is the chunk id. */
1225	AVLU32NODECORE Core;
1226	/** The key is the ageing sequence number. */
1227	AVLLU32NODECORE AgeCore;
1228	/** The current age thingy. */
1229	uint32_t iAge;
1230	/** The current reference count. */
1231	uint32_t volatile cRefs;
1232	/** The current permanent reference count. */
1233	uint32_t volatile cPermRefs;
1234	/** The mapping address. */
1235	void *pv;
1236	} PGMCHUNKR3MAP;
1237
1238	/**
1239	* Allocation chunk ring-3 mapping TLB entry.
1240	*/
1241	typedef struct PGMCHUNKR3MAPTLBE
1242	{
1243	/** The chunk id. */
1244	uint32_t volatile idChunk;
1245	#if HC_ARCH_BITS == 64
1246	uint32_t u32Padding; /*< alignment padding. /
1247	#endif
1248	/** The chunk map. */
1249	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1251	#else
1252	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1253	#endif
1254	} PGMCHUNKR3MAPTLBE;
1255	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1256	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1257
1258	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1259	* @remark Must be a power of two value. */
1260	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1261
1262	/**
1263	* Allocation chunk ring-3 mapping TLB.
1264	*
1265	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1266	* At first glance this might look kinda odd since AVL trees are
1267	* supposed to give the most optimial lookup times of all trees
1268	* due to their balancing. However, take a tree with 1023 nodes
1269	* in it, that's 10 levels, meaning that most searches has to go
1270	* down 9 levels before they find what they want. This isn't fast
1271	* compared to a TLB hit. There is the factor of cache misses,
1272	* and of course the problem with trees and branch prediction.
1273	* This is why we use TLBs in front of most of the trees.
1274	*
1275	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1276	* difficult when we switch to the new inlined AVL trees (from kStuff).
1277	*/
1278	typedef struct PGMCHUNKR3MAPTLB
1279	{
1280	/** The TLB entries. */
1281	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1282	} PGMCHUNKR3MAPTLB;
1283
1284	/**
1285	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1286	* @returns Chunk TLB index.
1287	* @param idChunk The Chunk ID.
1288	*/
1289	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1290
1291
1292	/**
1293	* Ring-3 guest page mapping TLB entry.
1294	* @remarks used in ring-0 as well at the moment.
1295	*/
1296	typedef struct PGMPAGER3MAPTLBE
1297	{
1298	/** Address of the page. */
1299	RTGCPHYS volatile GCPhys;
1300	/** The guest page. */
1301	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1302	R3PTRTYPE(PPGMPAGE) volatile pPage;
1303	#else
1304	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1305	#endif
1306	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1307	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1308	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1309	#else
1310	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1311	#endif
1312	/** The address */
1313	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1314	R3PTRTYPE(void *) volatile pv;
1315	#else
1316	R3R0PTRTYPE(void *) volatile pv;
1317	#endif
1318	#if HC_ARCH_BITS == 32
1319	uint32_t u32Padding; /*< alignment padding. /
1320	#endif
1321	} PGMPAGER3MAPTLBE;
1322	/** Pointer to an entry in the HC physical TLB. */
1323	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1324
1325
1326	/** The number of entries in the ring-3 guest page mapping TLB.
1327	* @remarks The value must be a power of two. */
1328	#define PGM_PAGER3MAPTLB_ENTRIES 64
1329
1330	/**
1331	* Ring-3 guest page mapping TLB.
1332	* @remarks used in ring-0 as well at the moment.
1333	*/
1334	typedef struct PGMPAGER3MAPTLB
1335	{
1336	/** The TLB entries. */
1337	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1338	} PGMPAGER3MAPTLB;
1339	/** Pointer to the ring-3 guest page mapping TLB. */
1340	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1341
1342	/**
1343	* Calculates the index of the TLB entry for the specified guest page.
1344	* @returns Physical TLB index.
1345	* @param GCPhys The guest physical address.
1346	*/
1347	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1348
1349
1350	/**
1351	* Mapping cache usage set entry.
1352	*
1353	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1354	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1355	* cache. If it's extended to include ring-3, well, then something will
1356	* have be changed here...
1357	*/
1358	typedef struct PGMMAPSETENTRY
1359	{
1360	/** The mapping cache index. */
1361	uint16_t iPage;
1362	/** The number of references.
1363	* The max is UINT16_MAX - 1. */
1364	uint16_t cRefs;
1365	/** Pointer to the page. */
1366	RTR0PTR pvPage;
1367	/** The physical address for this entry. */
1368	RTHCPHYS HCPhys;
1369	} PGMMAPSETENTRY;
1370	/** Pointer to a mapping cache usage set entry. */
1371	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1372
1373	/**
1374	* Mapping cache usage set.
1375	*
1376	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1377	* done during exits / traps. The set is
1378	*/
1379	typedef struct PGMMAPSET
1380	{
1381	/** The number of occupied entries.
1382	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1383	* dynamic mappings. */
1384	uint32_t cEntries;
1385	/** The start of the current subset.
1386	* This is UINT32_MAX if no subset is currently open. */
1387	uint32_t iSubset;
1388	/** The index of the current CPU, only valid if the set is open. */
1389	int32_t iCpu;
1390	/** The entries. */
1391	PGMMAPSETENTRY aEntries[64];
1392	/** HCPhys -> iEntry fast lookup table.
1393	* Use PGMMAPSET_HASH for hashing.
1394	* The entries may or may not be valid, check against cEntries. */
1395	uint8_t aiHashTable[128];
1396	} PGMMAPSET;
1397	/** Pointer to the mapping cache set. */
1398	typedef PGMMAPSET *PPGMMAPSET;
1399
1400	/** PGMMAPSET::cEntries value for a closed set. */
1401	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1402
1403	/** Hash function for aiHashTable. */
1404	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1405
1406	/** The max fill size (strict builds). */
1407	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1408
1409
1410	/** @name Context neutrual page mapper TLB.
1411	*
1412	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1413	* code is writting in a kind of context neutrual way. Time will show whether
1414	* this actually makes sense or not...
1415	*
1416	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1417	* context ends up using a global mapping cache on some platforms
1418	* (darwin).
1419	*
1420	* @{ */
1421	/** @typedef PPGMPAGEMAPTLB
1422	* The page mapper TLB pointer type for the current context. */
1423	/** @typedef PPGMPAGEMAPTLB
1424	* The page mapper TLB entry pointer type for the current context. */
1425	/** @typedef PPGMPAGEMAPTLB
1426	* The page mapper TLB entry pointer pointer type for the current context. */
1427	/** @def PGM_PAGEMAPTLB_ENTRIES
1428	* The number of TLB entries in the page mapper TLB for the current context. */
1429	/** @def PGM_PAGEMAPTLB_IDX
1430	* Calculate the TLB index for a guest physical address.
1431	* @returns The TLB index.
1432	* @param GCPhys The guest physical address. */
1433	/** @typedef PPGMPAGEMAP
1434	* Pointer to a page mapper unit for current context. */
1435	/** @typedef PPPGMPAGEMAP
1436	* Pointer to a page mapper unit pointer for current context. */
1437	#ifdef IN_RC
1438	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1439	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1440	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1441	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1442	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1443	typedef void * PPGMPAGEMAP;
1444	typedef void ** PPPGMPAGEMAP;
1445	//#elif IN_RING0
1446	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1447	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1448	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1449	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1450	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1451	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1452	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1453	#else
1454	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1455	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1456	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1457	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1458	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1459	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1460	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1461	#endif
1462	/** @} */
1463
1464
1465	/** @name PGM Pool Indexes.
1466	* Aka. the unique shadow page identifier.
1467	* @{ */
1468	/** NIL page pool IDX. */
1469	#define NIL_PGMPOOL_IDX 0
1470	/** The first normal index. */
1471	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1472	/** Page directory (32-bit root). */
1473	#define PGMPOOL_IDX_PD 1
1474	/** Page Directory Pointer Table (PAE root). */
1475	#define PGMPOOL_IDX_PDPT 2
1476	/** AMD64 CR3 level index.*/
1477	#define PGMPOOL_IDX_AMD64_CR3 3
1478	/** Nested paging root.*/
1479	#define PGMPOOL_IDX_NESTED_ROOT 4
1480	/** The first normal index. */
1481	#define PGMPOOL_IDX_FIRST 5
1482	/** The last valid index. (inclusive, 14 bits) */
1483	#define PGMPOOL_IDX_LAST 0x3fff
1484	/** @} */
1485
1486	/** The NIL index for the parent chain. */
1487	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1488
1489	/**
1490	* Node in the chain linking a shadowed page to it's parent (user).
1491	*/
1492	#pragma pack(1)
1493	typedef struct PGMPOOLUSER
1494	{
1495	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1496	uint16_t iNext;
1497	/** The user page index. */
1498	uint16_t iUser;
1499	/** Index into the user table. */
1500	uint32_t iUserTable;
1501	} PGMPOOLUSER, *PPGMPOOLUSER;
1502	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1503	#pragma pack()
1504
1505
1506	/** The NIL index for the phys ext chain. */
1507	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1508
1509	/**
1510	* Node in the chain of physical cross reference extents.
1511	* @todo Calling this an 'extent' is not quite right, find a better name.
1512	*/
1513	#pragma pack(1)
1514	typedef struct PGMPOOLPHYSEXT
1515	{
1516	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1517	uint16_t iNext;
1518	/** The user page index. */
1519	uint16_t aidx[3];
1520	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1521	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1522	#pragma pack()
1523
1524
1525	/**
1526	* The kind of page that's being shadowed.
1527	*/
1528	typedef enum PGMPOOLKIND
1529	{
1530	/** The virtual invalid 0 entry. */
1531	PGMPOOLKIND_INVALID = 0,
1532	/** The entry is free (=unused). */
1533	PGMPOOLKIND_FREE,
1534
1535	/** Shw: 32-bit page table; Gst: no paging */
1536	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1537	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1538	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1539	/** Shw: 32-bit page table; Gst: 4MB page. */
1540	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1541	/** Shw: PAE page table; Gst: no paging */
1542	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1543	/** Shw: PAE page table; Gst: 32-bit page table. */
1544	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1545	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1546	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1547	/** Shw: PAE page table; Gst: PAE page table. */
1548	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1549	/** Shw: PAE page table; Gst: 2MB page. */
1550	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1551
1552	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1553	PGMPOOLKIND_32BIT_PD,
1554	/** Shw: 32-bit page directory. Gst: no paging. */
1555	PGMPOOLKIND_32BIT_PD_PHYS,
1556	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1557	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1558	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1559	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1560	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1561	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1562	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1563	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1564	/** Shw: PAE page directory; Gst: PAE page directory. */
1565	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1566	/** Shw: PAE page directory; Gst: no paging. */
1567	PGMPOOLKIND_PAE_PD_PHYS,
1568
1569	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1570	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1571	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1572	PGMPOOLKIND_PAE_PDPT,
1573	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1574	PGMPOOLKIND_PAE_PDPT_PHYS,
1575
1576	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1577	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1578	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1579	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1580	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1581	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1582	/** Shw: 64-bit page directory table; Gst: no paging */
1583	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1584
1585	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1586	PGMPOOLKIND_64BIT_PML4,
1587
1588	/** Shw: EPT page directory pointer table; Gst: no paging */
1589	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1590	/** Shw: EPT page directory table; Gst: no paging */
1591	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1592	/** Shw: EPT page table; Gst: no paging */
1593	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1594
1595	/** Shw: Root Nested paging table. */
1596	PGMPOOLKIND_ROOT_NESTED,
1597
1598	/** The last valid entry. */
1599	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1600	} PGMPOOLKIND;
1601
1602
1603	/**
1604	* The tracking data for a page in the pool.
1605	*/
1606	typedef struct PGMPOOLPAGE
1607	{
1608	/** AVL node code with the (R3) physical address of this page. */
1609	AVLOHCPHYSNODECORE Core;
1610	/** Pointer to the R3 mapping of the page. */
1611	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1612	R3PTRTYPE(void *) pvPageR3;
1613	#else
1614	R3R0PTRTYPE(void *) pvPageR3;
1615	#endif
1616	/** The guest physical address. */
1617	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1618	uint32_t Alignment0;
1619	#endif
1620	RTGCPHYS GCPhys;
1621	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1622	uint8_t enmKind;
1623	uint8_t bPadding;
1624	/** The index of this page. */
1625	uint16_t idx;
1626	/** The next entry in the list this page currently resides in.
1627	* It's either in the free list or in the GCPhys hash. */
1628	uint16_t iNext;
1629	#ifdef PGMPOOL_WITH_USER_TRACKING
1630	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1631	uint16_t iUserHead;
1632	/** The number of present entries. */
1633	uint16_t cPresent;
1634	/** The first entry in the table which is present. */
1635	uint16_t iFirstPresent;
1636	#endif
1637	#ifdef PGMPOOL_WITH_MONITORING
1638	/** The number of modifications to the monitored page. */
1639	uint16_t cModifications;
1640	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1641	uint16_t iModifiedNext;
1642	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1643	uint16_t iModifiedPrev;
1644	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1645	uint16_t iMonitoredNext;
1646	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1647	uint16_t iMonitoredPrev;
1648	#endif
1649	#ifdef PGMPOOL_WITH_CACHE
1650	/** The next page in the age list. */
1651	uint16_t iAgeNext;
1652	/** The previous page in the age list. */
1653	uint16_t iAgePrev;
1654	#endif /* PGMPOOL_WITH_CACHE */
1655	/** Used to indicate that the page is zeroed. */
1656	bool fZeroed;
1657	/** Used to indicate that a PT has non-global entries. */
1658	bool fSeenNonGlobal;
1659	/** Used to indicate that we're monitoring writes to the guest page. */
1660	bool fMonitored;
1661	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1662	* (All pages are in the age list.) */
1663	bool fCached;
1664	/** This is used by the R3 access handlers when invoked by an async thread.
1665	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1666	bool volatile fReusedFlushPending;
1667	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1668	bool fLocked;
1669	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1670
1671
1672	#ifdef PGMPOOL_WITH_CACHE
1673	/** The hash table size. */
1674	# define PGMPOOL_HASH_SIZE 0x40
1675	/** The hash function. */
1676	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1677	#endif
1678
1679
1680	/**
1681	* The shadow page pool instance data.
1682	*
1683	* It's all one big allocation made at init time, except for the
1684	* pages that is. The user nodes follows immediatly after the
1685	* page structures.
1686	*/
1687	typedef struct PGMPOOL
1688	{
1689	/** The VM handle - R3 Ptr. */
1690	PVMR3 pVMR3;
1691	/** The VM handle - R0 Ptr. */
1692	PVMR0 pVMR0;
1693	/** The VM handle - RC Ptr. */
1694	PVMRC pVMRC;
1695	/** The max pool size. This includes the special IDs. */
1696	uint16_t cMaxPages;
1697	/** The current pool size. */
1698	uint16_t cCurPages;
1699	/** The head of the free page list. */
1700	uint16_t iFreeHead;
1701	/* Padding. */
1702	uint16_t u16Padding;
1703	#ifdef PGMPOOL_WITH_USER_TRACKING
1704	/** Head of the chain of free user nodes. */
1705	uint16_t iUserFreeHead;
1706	/** The number of user nodes we've allocated. */
1707	uint16_t cMaxUsers;
1708	/** The number of present page table entries in the entire pool. */
1709	uint32_t cPresent;
1710	/** Pointer to the array of user nodes - RC pointer. */
1711	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1712	/** Pointer to the array of user nodes - R3 pointer. */
1713	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1714	/** Pointer to the array of user nodes - R0 pointer. */
1715	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1716	#endif /* PGMPOOL_WITH_USER_TRACKING */
1717	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1718	/** Head of the chain of free phys ext nodes. */
1719	uint16_t iPhysExtFreeHead;
1720	/** The number of user nodes we've allocated. */
1721	uint16_t cMaxPhysExts;
1722	/** Pointer to the array of physical xref extent - RC pointer. */
1723	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1724	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1725	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1726	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1727	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1728	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1729	#ifdef PGMPOOL_WITH_CACHE
1730	/** Hash table for GCPhys addresses. */
1731	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1732	/** The head of the age list. */
1733	uint16_t iAgeHead;
1734	/** The tail of the age list. */
1735	uint16_t iAgeTail;
1736	/** Set if the cache is enabled. */
1737	bool fCacheEnabled;
1738	#endif /* PGMPOOL_WITH_CACHE */
1739	#ifdef PGMPOOL_WITH_MONITORING
1740	/** Head of the list of modified pages. */
1741	uint16_t iModifiedHead;
1742	/** The current number of modified pages. */
1743	uint16_t cModifiedPages;
1744	/** Access handler, RC. */
1745	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1746	/** Access handler, R0. */
1747	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1748	/** Access handler, R3. */
1749	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1750	/** The access handler description (HC ptr). */
1751	R3PTRTYPE(const char *) pszAccessHandler;
1752	#endif /* PGMPOOL_WITH_MONITORING */
1753	/** The number of pages currently in use. */
1754	uint16_t cUsedPages;
1755	#ifdef VBOX_WITH_STATISTICS
1756	/** The high wather mark for cUsedPages. */
1757	uint16_t cUsedPagesHigh;
1758	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1759	/** Profiling pgmPoolAlloc(). */
1760	STAMPROFILEADV StatAlloc;
1761	/** Profiling pgmPoolClearAll(). */
1762	STAMPROFILE StatClearAll;
1763	/** Profiling pgmPoolFlushAllInt(). */
1764	STAMPROFILE StatFlushAllInt;
1765	/** Profiling pgmPoolFlushPage(). */
1766	STAMPROFILE StatFlushPage;
1767	/** Profiling pgmPoolFree(). */
1768	STAMPROFILE StatFree;
1769	/** Profiling time spent zeroing pages. */
1770	STAMPROFILE StatZeroPage;
1771	# ifdef PGMPOOL_WITH_USER_TRACKING
1772	/** Profiling of pgmPoolTrackDeref. */
1773	STAMPROFILE StatTrackDeref;
1774	/** Profiling pgmTrackFlushGCPhysPT. */
1775	STAMPROFILE StatTrackFlushGCPhysPT;
1776	/** Profiling pgmTrackFlushGCPhysPTs. */
1777	STAMPROFILE StatTrackFlushGCPhysPTs;
1778	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1779	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1780	/** Number of times we've been out of user records. */
1781	STAMCOUNTER StatTrackFreeUpOneUser;
1782	# endif
1783	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1784	/** Profiling deref activity related tracking GC physical pages. */
1785	STAMPROFILE StatTrackDerefGCPhys;
1786	/** Number of linear searches for a HCPhys in the ram ranges. */
1787	STAMCOUNTER StatTrackLinearRamSearches;
1788	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1789	STAMCOUNTER StamTrackPhysExtAllocFailures;
1790	# endif
1791	# ifdef PGMPOOL_WITH_MONITORING
1792	/** Profiling the RC/R0 access handler. */
1793	STAMPROFILE StatMonitorRZ;
1794	/** Times we've failed interpreting the instruction. */
1795	STAMCOUNTER StatMonitorRZEmulateInstr;
1796	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1797	STAMPROFILE StatMonitorRZFlushPage;
1798	/** Times we've detected fork(). */
1799	STAMCOUNTER StatMonitorRZFork;
1800	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1801	STAMPROFILE StatMonitorRZHandled;
1802	/** Times we've failed interpreting a patch code instruction. */
1803	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1804	/** Times we've failed interpreting a patch code instruction during flushing. */
1805	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1806	/** The number of times we've seen rep prefixes we can't handle. */
1807	STAMCOUNTER StatMonitorRZRepPrefix;
1808	/** Profiling the REP STOSD cases we've handled. */
1809	STAMPROFILE StatMonitorRZRepStosd;
1810
1811	/** Profiling the R3 access handler. */
1812	STAMPROFILE StatMonitorR3;
1813	/** Times we've failed interpreting the instruction. */
1814	STAMCOUNTER StatMonitorR3EmulateInstr;
1815	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1816	STAMPROFILE StatMonitorR3FlushPage;
1817	/** Times we've detected fork(). */
1818	STAMCOUNTER StatMonitorR3Fork;
1819	/** Profiling the R3 access we've handled (except REP STOSD). */
1820	STAMPROFILE StatMonitorR3Handled;
1821	/** The number of times we've seen rep prefixes we can't handle. */
1822	STAMCOUNTER StatMonitorR3RepPrefix;
1823	/** Profiling the REP STOSD cases we've handled. */
1824	STAMPROFILE StatMonitorR3RepStosd;
1825	/** The number of times we're called in an async thread an need to flush. */
1826	STAMCOUNTER StatMonitorR3Async;
1827	/** The high wather mark for cModifiedPages. */
1828	uint16_t cModifiedPagesHigh;
1829	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1830	# endif
1831	# ifdef PGMPOOL_WITH_CACHE
1832	/** The number of cache hits. */
1833	STAMCOUNTER StatCacheHits;
1834	/** The number of cache misses. */
1835	STAMCOUNTER StatCacheMisses;
1836	/** The number of times we've got a conflict of 'kind' in the cache. */
1837	STAMCOUNTER StatCacheKindMismatches;
1838	/** Number of times we've been out of pages. */
1839	STAMCOUNTER StatCacheFreeUpOne;
1840	/** The number of cacheable allocations. */
1841	STAMCOUNTER StatCacheCacheable;
1842	/** The number of uncacheable allocations. */
1843	STAMCOUNTER StatCacheUncacheable;
1844	# endif
1845	#elif HC_ARCH_BITS == 64
1846	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1847	#endif
1848	/** The AVL tree for looking up a page by its HC physical address. */
1849	AVLOHCPHYSTREE HCPhysTree;
1850	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1851	/** Array of pages. (cMaxPages in length)
1852	* The Id is the index into thist array.
1853	*/
1854	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1855	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1856
1857
1858	/** @def PGMPOOL_PAGE_2_PTR
1859	* Maps a pool page pool into the current context.
1860	*
1861	* @returns VBox status code.
1862	* @param pVM The VM handle.
1863	* @param pPage The pool page.
1864	*
1865	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1866	* small page window employeed by that function. Be careful.
1867	* @remark There is no need to assert on the result.
1868	*/
1869	#if defined(IN_RC)
1870	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1871	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1872	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1873	#elif defined(VBOX_STRICT)
1874	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1875	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1876	{
1877	Assert(pPage && pPage->pvPageR3);
1878	return pPage->pvPageR3;
1879	}
1880	#else
1881	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1882	#endif
1883
1884	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1885	* Maps a pool page pool into the current context.
1886	*
1887	* @returns VBox status code.
1888	* @param pPGM Pointer to the PGM instance data.
1889	* @param pPage The pool page.
1890	*
1891	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1892	* small page window employeed by that function. Be careful.
1893	* @remark There is no need to assert on the result.
1894	*/
1895	#if defined(IN_RC)
1896	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1897	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1898	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1899	#else
1900	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1901	#endif
1902
1903
1904	/** @name Per guest page tracking data.
1905	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1906	* is to use more bits for it and split it up later on. But for now we'll play
1907	* safe and change as little as possible.
1908	*
1909	* The 16-bit word has two parts:
1910	*
1911	* The first 14-bit forms the @a idx field. It is either the index of a page in
1912	* the shadow page pool, or and index into the extent list.
1913	*
1914	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
1915	* shadow page pool references to the page. If cRefs equals
1916	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1917	* (misnomer) table and not the shadow page pool.
1918	*
1919	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1920	* the 16-bit word.
1921	*
1922	* @{ */
1923	/** The shift count for getting to the cRefs part. */
1924	#define PGMPOOL_TD_CREFS_SHIFT 14
1925	/** The mask applied after shifting the tracking data down by
1926	* PGMPOOL_TD_CREFS_SHIFT. */
1927	#define PGMPOOL_TD_CREFS_MASK 0x3
1928	/** The cRef value used to indiciate that the idx is the head of a
1929	* physical cross reference list. */
1930	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1931	/** The shift used to get idx. */
1932	#define PGMPOOL_TD_IDX_SHIFT 0
1933	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1934	#define PGMPOOL_TD_IDX_MASK 0x3fff
1935	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1936	* simply too many mappings of this page. */
1937	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1938
1939	/** @def PGMPOOL_TD_MAKE
1940	* Makes a 16-bit tracking data word.
1941	*
1942	* @returns tracking data.
1943	* @param cRefs The @a cRefs field. Must be within bounds!
1944	* @param idx The @a idx field. Must also be within bounds! */
1945	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
1946
1947	/** @def PGMPOOL_TD_GET_CREFS
1948	* Get the @a cRefs field from a tracking data word.
1949	*
1950	* @returns The @a cRefs field
1951	* @param u16 The tracking data word. */
1952	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1953
1954	/** @def PGMPOOL_TD_GET_IDX
1955	* Get the @a idx field from a tracking data word.
1956	*
1957	* @returns The @a idx field
1958	* @param u16 The tracking data word. */
1959	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1960	/** @} */
1961
1962
1963	/**
1964	* Trees are using self relative offsets as pointers.
1965	* So, all its data, including the root pointer, must be in the heap for HC and GC
1966	* to have the same layout.
1967	*/
1968	typedef struct PGMTREES
1969	{
1970	/** Physical access handlers (AVL range+offsetptr tree). */
1971	AVLROGCPHYSTREE PhysHandlers;
1972	/** Virtual access handlers (AVL range + GC ptr tree). */
1973	AVLROGCPTRTREE VirtHandlers;
1974	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1975	AVLROGCPHYSTREE PhysToVirtHandlers;
1976	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1977	AVLROGCPTRTREE HyperVirtHandlers;
1978	} PGMTREES;
1979	/** Pointer to PGM trees. */
1980	typedef PGMTREES *PPGMTREES;
1981
1982
1983	/** @name Paging mode macros
1984	* @{ */
1985	#ifdef IN_RC
1986	# define PGM_CTX(a,b) a##RC##b
1987	# define PGM_CTX_STR(a,b) a "GC" b
1988	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1989	#else
1990	# ifdef IN_RING3
1991	# define PGM_CTX(a,b) a##R3##b
1992	# define PGM_CTX_STR(a,b) a "R3" b
1993	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1994	# else
1995	# define PGM_CTX(a,b) a##R0##b
1996	# define PGM_CTX_STR(a,b) a "R0" b
1997	# define PGM_CTX_DECL(type) VMMDECL(type)
1998	# endif
1999	#endif
2000
2001	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2002	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2003	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2004	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2005	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2006	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2007	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2008	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2009	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2010	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2011	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2012	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2013	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2014	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2015	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2016	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2017	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2018
2019	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2020	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2021	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2022	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2023	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2024	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2025	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2026	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2027	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2028	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2029	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2030	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2031	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2032	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2033	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2034	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2035	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2036
2037	/* Shw_Gst */
2038	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2039	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2040	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2041	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2042	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2043	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2044	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2045	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2046	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2047	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2048	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2049	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2050	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2051	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2052	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2053	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2054	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2055	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2056	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2057
2058	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2059	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2060	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2061	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2062	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2063	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2064	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2065	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2066	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2067	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2068	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2069	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2070	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2071	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2072	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2073	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2074	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2075	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2076	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2077	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2078	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2079	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2080	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2081	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2082	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2083	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2084	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2085	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2086	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2087	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2088	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2089	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2090	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2091	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2092	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2093	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2094	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2095
2096	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2097	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2098	/** @} */
2099
2100	/**
2101	* Data for each paging mode.
2102	*/
2103	typedef struct PGMMODEDATA
2104	{
2105	/** The guest mode type. */
2106	uint32_t uGstType;
2107	/** The shadow mode type. */
2108	uint32_t uShwType;
2109
2110	/** @name Function pointers for Shadow paging.
2111	* @{
2112	*/
2113	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2114	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2115	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2116	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2117
2118	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2119	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2120
2121	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2122	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2123	/** @} */
2124
2125	/** @name Function pointers for Guest paging.
2126	* @{
2127	*/
2128	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2129	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2130	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2131	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2132	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2133	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2134	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2135	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2136	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2137	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2138	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2139	/** @} */
2140
2141	/** @name Function pointers for Both Shadow and Guest paging.
2142	* @{
2143	*/
2144	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2145	/* no pfnR3BthTrap0eHandler */
2146	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2147	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2148	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2149	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2150	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2151	#ifdef VBOX_STRICT
2152	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2153	#endif
2154	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2155	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2156
2157	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2158	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2159	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2160	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2161	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2162	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2163	#ifdef VBOX_STRICT
2164	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2165	#endif
2166	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2167	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2168
2169	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2170	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2171	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2172	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2173	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2174	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2175	#ifdef VBOX_STRICT
2176	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2177	#endif
2178	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2179	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2180	/** @} */
2181	} PGMMODEDATA, *PPGMMODEDATA;
2182
2183
2184
2185	/**
2186	* Converts a PGM pointer into a VM pointer.
2187	* @returns Pointer to the VM structure the PGM is part of.
2188	* @param pPGM Pointer to PGM instance data.
2189	*/
2190	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2191
2192	/**
2193	* PGM Data (part of VM)
2194	*/
2195	typedef struct PGM
2196	{
2197	/** Offset to the VM structure. */
2198	RTINT offVM;
2199	/** Offset of the PGMCPU structure relative to VMCPU. */
2200	int32_t offVCpu;
2201	/** @cfgm{PGM/RamPreAlloc, bool, false}
2202	* Whether to preallocate all the guest RAM or not. */
2203	bool fRamPreAlloc;
2204	/** Alignment padding. */
2205	bool afAlignment0[3];
2206
2207
2208	/*
2209	* This will be redefined at least two more times before we're done, I'm sure.
2210	* The current code is only to get on with the coding.
2211	* - 2004-06-10: initial version, bird.
2212	* - 2004-07-02: 1st time, bird.
2213	* - 2004-10-18: 2nd time, bird.
2214	* - 2005-07-xx: 3rd time, bird.
2215	*/
2216
2217	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2218	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2219	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2220	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2221
2222	/** The host paging mode. (This is what SUPLib reports.) */
2223	SUPPAGINGMODE enmHostMode;
2224	/** The shadow paging mode. */
2225	PGMMODE enmShadowMode;
2226	/** The guest paging mode. */
2227	PGMMODE enmGuestMode;
2228
2229	/** The current physical address representing in the guest CR3 register. */
2230	RTGCPHYS GCPhysCR3;
2231	/** Pointer to the 5 page CR3 content mapping.
2232	* The first page is always the CR3 (in some form) while the 4 other pages
2233	* are used of the PDs in PAE mode. */
2234	RTGCPTR GCPtrCR3Mapping;
2235	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2236	uint32_t u32Alignment;
2237	#endif
2238	/** @name 32-bit Guest Paging.
2239	* @{ */
2240	/** The guest's page directory, R3 pointer. */
2241	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2242	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2243	/** The guest's page directory, R0 pointer. */
2244	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2245	#endif
2246	/** The guest's page directory, static RC mapping. */
2247	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2248	/** @} */
2249
2250	/** @name PAE Guest Paging.
2251	* @{ */
2252	/** The guest's page directory pointer table, static RC mapping. */
2253	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2254	/** The guest's page directory pointer table, R3 pointer. */
2255	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2256	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2257	/** The guest's page directory pointer table, R0 pointer. */
2258	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2259	#endif
2260
2261	/** The guest's page directories, R3 pointers.
2262	* These are individual pointers and don't have to be adjecent.
2263	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2264	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2265	/** The guest's page directories, R0 pointers.
2266	* Same restrictions as apGstPaePDsR3. */
2267	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2268	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2269	#endif
2270	/** The guest's page directories, static GC mapping.
2271	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2272	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2273	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2274	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2275	RTGCPHYS aGCPhysGstPaePDs[4];
2276	/** The physical addresses of the monitored guest page directories (PAE). */
2277	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2278	/** @} */
2279
2280	/** @name AMD64 Guest Paging.
2281	* @{ */
2282	/** The guest's page directory pointer table, R3 pointer. */
2283	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2284	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2285	/** The guest's page directory pointer table, R0 pointer. */
2286	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2287	#endif
2288	/** @} */
2289
2290	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2291	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2292	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2293	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2294	/** Pointer to the page of the current active CR3 - RC Ptr. */
2295	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2296	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2297	uint32_t iShwUser;
2298	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2299	uint32_t iShwUserTable;
2300	# if HC_ARCH_BITS == 64
2301	RTRCPTR alignment6; /*< structure size alignment. /
2302	# endif
2303	/** @} */
2304
2305	/** @name Function pointers for Shadow paging.
2306	* @{
2307	*/
2308	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2309	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2310	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2311	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2312
2313	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2314	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2315
2316	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2317	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2318
2319	/** @} */
2320
2321	/** @name Function pointers for Guest paging.
2322	* @{
2323	*/
2324	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2325	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2326	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2327	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2328	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2329	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2330	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2331	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2332	#if HC_ARCH_BITS == 64
2333	RTRCPTR alignment3; /*< structure size alignment. /
2334	#endif
2335
2336	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2337	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2338	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2339	/** @} */
2340
2341	/** @name Function pointers for Both Shadow and Guest paging.
2342	* @{
2343	*/
2344	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2345	/* no pfnR3BthTrap0eHandler */
2346	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2347	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2348	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2349	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2350	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2351	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2352	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2353	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2354
2355	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2356	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2357	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2358	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2359	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2360	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2361	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2362	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2363	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2364
2365	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2366	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2367	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2368	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2369	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2370	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2371	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2372	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2373	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2374	#if HC_ARCH_BITS == 64
2375	RTRCPTR alignment2; /*< structure size alignment. /
2376	#endif
2377	/** @} */
2378
2379	/** Pointer to SHW+GST mode data (function pointers).
2380	* The index into this table is made up from */
2381	R3PTRTYPE(PPGMMODEDATA) paModeData;
2382
2383	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2384	* This is sorted by physical address and contains no overlapping ranges. */
2385	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2386	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2387	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2388	/** RC pointer corresponding to PGM::pRamRangesR3. */
2389	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2390	/** The configured RAM size.
2391	* @remarks Do NOT use this, it's too small to hold the whole stuff.
2392	* @todo Remove with VBOX_WITH_NEW_PHYS_CODE! */
2393	RTUINT cbRamSize;
2394
2395	/** Pointer to the list of ROM ranges - for R3.
2396	* This is sorted by physical address and contains no overlapping ranges. */
2397	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2398	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2399	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2400	/** RC pointer corresponding to PGM::pRomRangesR3. */
2401	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2402	/** Alignment padding. */
2403	RTRCPTR GCPtrPadding2;
2404
2405	/** Pointer to the list of MMIO2 ranges - for R3.
2406	* Registration order. */
2407	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2408
2409	/** PGM offset based trees - R3 Ptr. */
2410	R3PTRTYPE(PPGMTREES) pTreesR3;
2411	/** PGM offset based trees - R0 Ptr. */
2412	R0PTRTYPE(PPGMTREES) pTreesR0;
2413	/** PGM offset based trees - RC Ptr. */
2414	RCPTRTYPE(PPGMTREES) pTreesRC;
2415
2416	/** Linked list of GC mappings - for RC.
2417	* The list is sorted ascending on address.
2418	*/
2419	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2420	/** Linked list of GC mappings - for HC.
2421	* The list is sorted ascending on address.
2422	*/
2423	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2424	/** Linked list of GC mappings - for R0.
2425	* The list is sorted ascending on address.
2426	*/
2427	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2428
2429	/** Indicates that PGMR3FinalizeMappings has been called and that further
2430	* PGMR3MapIntermediate calls will be rejected. */
2431	bool fFinalizedMappings;
2432	/** If set no conflict checks are required. (boolean) */
2433	bool fMappingsFixed;
2434	/** If set, then no mappings are put into the shadow page table. (boolean) */
2435	bool fDisableMappings;
2436	/** Size of fixed mapping */
2437	uint32_t cbMappingFixed;
2438	/** Base address (GC) of fixed mapping */
2439	RTGCPTR GCPtrMappingFixed;
2440	/** The address of the previous RAM range mapping. */
2441	RTGCPTR GCPtrPrevRamRangeMapping;
2442
2443	/** @name Intermediate Context
2444	* @{ */
2445	/** Pointer to the intermediate page directory - Normal. */
2446	R3PTRTYPE(PX86PD) pInterPD;
2447	/** Pointer to the intermedate page tables - Normal.
2448	* There are two page tables, one for the identity mapping and one for
2449	* the host context mapping (of the core code). */
2450	R3PTRTYPE(PX86PT) apInterPTs[2];
2451	/** Pointer to the intermedate page tables - PAE. */
2452	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2453	/** Pointer to the intermedate page directory - PAE. */
2454	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2455	/** Pointer to the intermedate page directory - PAE. */
2456	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2457	/** Pointer to the intermedate page-map level 4 - AMD64. */
2458	R3PTRTYPE(PX86PML4) pInterPaePML4;
2459	/** Pointer to the intermedate page directory - AMD64. */
2460	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2461	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2462	RTHCPHYS HCPhysInterPD;
2463	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2464	RTHCPHYS HCPhysInterPaePDPT;
2465	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2466	RTHCPHYS HCPhysInterPaePML4;
2467	/** @} */
2468
2469	/** Base address of the dynamic page mapping area.
2470	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2471	*/
2472	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2473	/** The index of the last entry used in the dynamic page mapping area. */
2474	RTUINT iDynPageMapLast;
2475	/** Cache containing the last entries in the dynamic page mapping area.
2476	* The cache size is covering half of the mapping area. */
2477	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2478	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2479
2480	/** The address of the ring-0 mapping cache if we're making use of it. */
2481	RTR0PTR pvR0DynMapUsed;
2482	#if HC_ARCH_BITS == 32
2483	RTR0PTR R0PtrPadding0; /*< Alignment. /
2484	#endif
2485
2486
2487	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2488	RTGCPHYS GCPhys4MBPSEMask;
2489
2490	/** A20 gate mask.
2491	* Our current approach to A20 emulation is to let REM do it and don't bother
2492	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2493	* But whould need arrise, we'll subject physical addresses to this mask. */
2494	RTGCPHYS GCPhysA20Mask;
2495	/** A20 gate state - boolean! */
2496	bool fA20Enabled;
2497
2498	/** What needs syncing (PGM_SYNC_*).
2499	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2500	* PGMFlushTLB, and PGMR3Load. */
2501	RTUINT fSyncFlags;
2502
2503	/** PGM critical section.
2504	* This protects the physical & virtual access handlers, ram ranges,
2505	* and the page flag updating (some of it anyway).
2506	*/
2507	PDMCRITSECT CritSect;
2508
2509	/** Shadow Page Pool - R3 Ptr. */
2510	R3PTRTYPE(PPGMPOOL) pPoolR3;
2511	/** Shadow Page Pool - R0 Ptr. */
2512	R0PTRTYPE(PPGMPOOL) pPoolR0;
2513	/** Shadow Page Pool - RC Ptr. */
2514	RCPTRTYPE(PPGMPOOL) pPoolRC;
2515
2516	/** We're not in a state which permits writes to guest memory.
2517	* (Only used in strict builds.) */
2518	bool fNoMorePhysWrites;
2519
2520	/** Flush the cache on the next access. */
2521	bool fPhysCacheFlushPending;
2522	/** @todo r=bird: Fix member names!*/
2523	/** PGMPhysRead cache */
2524	PGMPHYSCACHE pgmphysreadcache;
2525	/** PGMPhysWrite cache */
2526	PGMPHYSCACHE pgmphyswritecache;
2527
2528	/**
2529	* Data associated with managing the ring-3 mappings of the allocation chunks.
2530	*/
2531	struct
2532	{
2533	/** The chunk tree, ordered by chunk id. */
2534	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2535	R3PTRTYPE(PAVLU32NODECORE) pTree;
2536	#else
2537	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2538	#endif
2539	/** The chunk mapping TLB. */
2540	PGMCHUNKR3MAPTLB Tlb;
2541	/** The number of mapped chunks. */
2542	uint32_t c;
2543	/** The maximum number of mapped chunks.
2544	* @cfgm PGM/MaxRing3Chunks */
2545	uint32_t cMax;
2546	/** The chunk age tree, ordered by ageing sequence number. */
2547	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2548	/** The current time. */
2549	uint32_t iNow;
2550	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2551	uint32_t AgeingCountdown;
2552	} ChunkR3Map;
2553
2554	/**
2555	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2556	*/
2557	PGMPAGER3MAPTLB PhysTlbHC;
2558
2559	/** @name The zero page.
2560	* @{ */
2561	/** The host physical address of the zero page. */
2562	RTHCPHYS HCPhysZeroPg;
2563	/** The ring-3 mapping of the zero page. */
2564	RTR3PTR pvZeroPgR3;
2565	/** The ring-0 mapping of the zero page. */
2566	RTR0PTR pvZeroPgR0;
2567	/** The GC mapping of the zero page. */
2568	RTGCPTR pvZeroPgGC;
2569	#if GC_ARCH_BITS != 32
2570	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2571	#endif
2572	/** @}*/
2573
2574	/** The number of handy pages. */
2575	uint32_t cHandyPages;
2576	/**
2577	* Array of handy pages.
2578	*
2579	* This array is used in a two way communication between pgmPhysAllocPage
2580	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2581	* an intermediary.
2582	*
2583	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2584	* (The current size of 32 pages, means 128 KB of handy memory.)
2585	*/
2586	GMMPAGEDESC aHandyPages[32];
2587
2588	/** @name Release Statistics
2589	* @{ */
2590	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2591	uint32_t cPrivatePages; /*< The number of private pages. /
2592	uint32_t cSharedPages; /*< The number of shared pages. /
2593	uint32_t cZeroPages; /*< The number of zero backed pages. /
2594	/** The number of times the guest has switched mode since last reset or statistics reset. */
2595	STAMCOUNTER cGuestModeChanges;
2596	/** The number of times we were forced to change the hypervisor region location. */
2597	STAMCOUNTER cRelocations;
2598	/** @} */
2599
2600	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2601	/** RC: Which statistic this \#PF should be attributed to. */
2602	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2603	RTRCPTR padding0;
2604	/** R0: Which statistic this \#PF should be attributed to. */
2605	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2606	RTR0PTR padding1;
2607
2608	/* Common */
2609	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2610	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2611	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2612	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2613	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2614	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2615	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2616	# endif
2617	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2618	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2619
2620	/* R3 only: */
2621	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2622	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2623	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2624	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2625	#ifndef VBOX_WITH_NEW_PHYS_CODE
2626	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2627	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2628	#endif
2629
2630	/* R0 only: */
2631	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2632	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2633	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2634	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2635	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2636	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2637	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2638	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2639	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2640	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2641	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2642	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2643	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2644	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2645	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2646	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2647	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2648	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2649	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2650	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2651	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2652	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2653	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2654	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2655	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2656	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2657
2658	/* RC only: */
2659	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2660	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2661	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2662	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2663
2664	/* RZ only: */
2665	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2666	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2667	STAMPROFILE StatRZTrap0eTimeSyncPT;
2668	STAMPROFILE StatRZTrap0eTimeMapping;
2669	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2670	STAMPROFILE StatRZTrap0eTimeHandlers;
2671	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2672	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2673	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2674	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2675	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2676	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2677	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2678	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2679	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2680	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2681	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2682	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2683	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2684	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2685	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2686	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2687	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2688	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2689	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2690	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2691	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2692	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2693	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2694	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2695	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2696	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2697	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2698	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2699	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2700	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2701	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2702	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2703	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2704	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2705	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2706	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2707	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2708	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2709	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2710	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2711	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2712	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2713	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2714
2715	/* HC - R3 and (maybe) R0: */
2716
2717	/* RZ & R3: */
2718	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2719	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2720	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2721	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2722	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2723	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2724	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2725	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2726	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2727	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2728	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2729	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2730	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2731	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2732	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2733	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2734	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2735	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2736	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2737	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2738	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2739	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2740	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2741	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2742	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2743	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2744	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2745	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2746	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2747	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2748	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2749	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2750	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2751	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2752	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2753	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2754	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2755	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2756	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2757	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2758	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2759	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2760	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2761	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2762	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2763	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2764	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2765	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2766	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2767	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2768	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2769	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2770	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2771	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2772
2773	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2774	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2775	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2776	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2777	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2778	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2779	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2780	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2781	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2782	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2783	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2784	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2785	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2786	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2787	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2788	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2789	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2790	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2791	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2792	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2793	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2794	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2795	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2796	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2797	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2798	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2799	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2800	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2801	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2802	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2803	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2804	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2805	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2806	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2807	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2808	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2809	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2810	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2811	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2812	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2813	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2814	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2815	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2816	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2817	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2818	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2819	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2820	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2821	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2822	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2823	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2824	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2825	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2826	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2827	#endif /* VBOX_WITH_STATISTICS */
2828	} PGM;
2829	/** Pointer to the PGM instance data. */
2830	typedef PGM *PPGM;
2831
2832
2833	/**
2834	* PGMCPU Data (part of VMCPU).
2835	*/
2836	typedef struct PGMCPU
2837	{
2838	/** Offset to the VMCPU structure. */
2839	RTINT offVMCPU;
2840	/** Automatically tracked physical memory mapping set.
2841	* Ring-0 and strict raw-mode builds. */
2842	PGMMAPSET AutoSet;
2843	} PGMCPU;
2844	/** Pointer to the per-cpu PGM data. */
2845	typedef PGMCPU *PPGMCPU;
2846
2847
2848	/** @name PGM::fSyncFlags Flags
2849	* @{
2850	*/
2851	/** Updates the virtual access handler state bit in PGMPAGE. */
2852	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2853	/** Always sync CR3. */
2854	#define PGM_SYNC_ALWAYS RT_BIT(1)
2855	/** Check monitoring on next CR3 (re)load and invalidate page. */
2856	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2857	/** Check guest mapping in SyncCR3. */
2858	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2859	/** Clear the page pool (a light weight flush). */
2860	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2861	/** @} */
2862
2863
2864	__BEGIN_DECLS
2865
2866	int pgmLock(PVM pVM);
2867	void pgmUnlock(PVM pVM);
2868
2869	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2870	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2871	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2872	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2873	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2874
2875	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2876	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2877	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2878	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2879	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2880	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2881	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2882	#else
2883	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2884	#endif
2885	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2886
2887
2888	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2889	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2890	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2891	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2892	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2893	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2894	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2895	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2896	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2897	#ifdef IN_RING3
2898	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2899	void pgmR3PhysRelinkRamRanges(PVM pVM);
2900	int pgmR3PhysRamReset(PVM pVM);
2901	int pgmR3PhysRomReset(PVM pVM);
2902	# ifndef VBOX_WITH_NEW_PHYS_CODE
2903	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2904	# endif
2905
2906	int pgmR3PoolInit(PVM pVM);
2907	void pgmR3PoolRelocate(PVM pVM);
2908	void pgmR3PoolReset(PVM pVM);
2909
2910	#endif /* IN_RING3 */
2911	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2912	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2913	#endif
2914	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2915	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2916	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2917	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2918	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2919	void pgmPoolFlushAll(PVM pVM);
2920	void pgmPoolClearAll(PVM pVM);
2921	int pgmPoolSyncCR3(PVM pVM);
2922	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
2923	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2924	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2925	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2926	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2927	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2928	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2929	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2930	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2931	#ifdef PGMPOOL_WITH_MONITORING
2932	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2933	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2934	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2935	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2936	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2937	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2938	#endif
2939
2940	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2941	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
2942	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2943	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2944
2945	int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2946	#ifndef IN_RC
2947	int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2948	#endif
2949	int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
2950
2951	PX86PD pgmGstLazyMap32BitPD(PPGM pPGM);
2952	PX86PDPT pgmGstLazyMapPaePDPT(PPGM pPGM);
2953	PX86PDPAE pgmGstLazyMapPaePD(PPGM pPGM, uint32_t iPdpt);
2954	PX86PML4 pgmGstLazyMapPml4(PPGM pPGM);
2955
2956	__END_DECLS
2957
2958
2959	/**
2960	* Gets the PGMRAMRANGE structure for a guest page.
2961	*
2962	* @returns Pointer to the RAM range on success.
2963	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2964	*
2965	* @param pPGM PGM handle.
2966	* @param GCPhys The GC physical address.
2967	*/
2968	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2969	{
2970	/*
2971	* Optimize for the first range.
2972	*/
2973	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2974	RTGCPHYS off = GCPhys - pRam->GCPhys;
2975	if (RT_UNLIKELY(off >= pRam->cb))
2976	{
2977	do
2978	{
2979	pRam = pRam->CTX_SUFF(pNext);
2980	if (RT_UNLIKELY(!pRam))
2981	break;
2982	off = GCPhys - pRam->GCPhys;
2983	} while (off >= pRam->cb);
2984	}
2985	return pRam;
2986	}
2987
2988
2989	/**
2990	* Gets the PGMPAGE structure for a guest page.
2991	*
2992	* @returns Pointer to the page on success.
2993	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2994	*
2995	* @param pPGM PGM handle.
2996	* @param GCPhys The GC physical address.
2997	*/
2998	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2999	{
3000	/*
3001	* Optimize for the first range.
3002	*/
3003	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3004	RTGCPHYS off = GCPhys - pRam->GCPhys;
3005	if (RT_UNLIKELY(off >= pRam->cb))
3006	{
3007	do
3008	{
3009	pRam = pRam->CTX_SUFF(pNext);
3010	if (RT_UNLIKELY(!pRam))
3011	return NULL;
3012	off = GCPhys - pRam->GCPhys;
3013	} while (off >= pRam->cb);
3014	}
3015	return &pRam->aPages[off >> PAGE_SHIFT];
3016	}
3017
3018
3019	/**
3020	* Gets the PGMPAGE structure for a guest page.
3021	*
3022	* Old Phys code: Will make sure the page is present.
3023	*
3024	* @returns VBox status code.
3025	* @retval VINF_SUCCESS and a valid *ppPage on success.
3026	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3027	*
3028	* @param pPGM PGM handle.
3029	* @param GCPhys The GC physical address.
3030	* @param ppPage Where to store the page poitner on success.
3031	*/
3032	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3033	{
3034	/*
3035	* Optimize for the first range.
3036	*/
3037	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3038	RTGCPHYS off = GCPhys - pRam->GCPhys;
3039	if (RT_UNLIKELY(off >= pRam->cb))
3040	{
3041	do
3042	{
3043	pRam = pRam->CTX_SUFF(pNext);
3044	if (RT_UNLIKELY(!pRam))
3045	{
3046	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3047	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3048	}
3049	off = GCPhys - pRam->GCPhys;
3050	} while (off >= pRam->cb);
3051	}
3052	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3053	#ifndef VBOX_WITH_NEW_PHYS_CODE
3054
3055	/*
3056	* Make sure it's present.
3057	*/
3058	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3059	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3060	{
3061	#ifdef IN_RING3
3062	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3063	#else
3064	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3065	#endif
3066	if (RT_FAILURE(rc))
3067	{
3068	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3069	return rc;
3070	}
3071	Assert(rc == VINF_SUCCESS);
3072	}
3073	#endif
3074	return VINF_SUCCESS;
3075	}
3076
3077
3078
3079
3080	/**
3081	* Gets the PGMPAGE structure for a guest page.
3082	*
3083	* Old Phys code: Will make sure the page is present.
3084	*
3085	* @returns VBox status code.
3086	* @retval VINF_SUCCESS and a valid *ppPage on success.
3087	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3088	*
3089	* @param pPGM PGM handle.
3090	* @param GCPhys The GC physical address.
3091	* @param ppPage Where to store the page poitner on success.
3092	* @param ppRamHint Where to read and store the ram list hint.
3093	* The caller initializes this to NULL before the call.
3094	*/
3095	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3096	{
3097	RTGCPHYS off;
3098	PPGMRAMRANGE pRam = *ppRamHint;
3099	if ( !pRam
3100	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3101	{
3102	pRam = pPGM->CTX_SUFF(pRamRanges);
3103	off = GCPhys - pRam->GCPhys;
3104	if (RT_UNLIKELY(off >= pRam->cb))
3105	{
3106	do
3107	{
3108	pRam = pRam->CTX_SUFF(pNext);
3109	if (RT_UNLIKELY(!pRam))
3110	{
3111	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3112	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3113	}
3114	off = GCPhys - pRam->GCPhys;
3115	} while (off >= pRam->cb);
3116	}
3117	*ppRamHint = pRam;
3118	}
3119	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3120	#ifndef VBOX_WITH_NEW_PHYS_CODE
3121
3122	/*
3123	* Make sure it's present.
3124	*/
3125	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3126	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3127	{
3128	#ifdef IN_RING3
3129	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3130	#else
3131	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3132	#endif
3133	if (RT_FAILURE(rc))
3134	{
3135	ppPage = NULL; / Shut up annoying smart ass. */
3136	return rc;
3137	}
3138	Assert(rc == VINF_SUCCESS);
3139	}
3140	#endif
3141	return VINF_SUCCESS;
3142	}
3143
3144
3145	/**
3146	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3147	*
3148	* @returns Pointer to the page on success.
3149	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3150	*
3151	* @param pPGM PGM handle.
3152	* @param GCPhys The GC physical address.
3153	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3154	*/
3155	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3156	{
3157	/*
3158	* Optimize for the first range.
3159	*/
3160	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3161	RTGCPHYS off = GCPhys - pRam->GCPhys;
3162	if (RT_UNLIKELY(off >= pRam->cb))
3163	{
3164	do
3165	{
3166	pRam = pRam->CTX_SUFF(pNext);
3167	if (RT_UNLIKELY(!pRam))
3168	return NULL;
3169	off = GCPhys - pRam->GCPhys;
3170	} while (off >= pRam->cb);
3171	}
3172	*ppRam = pRam;
3173	return &pRam->aPages[off >> PAGE_SHIFT];
3174	}
3175
3176
3177	/**
3178	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3179	*
3180	* @returns Pointer to the page on success.
3181	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3182	*
3183	* @param pPGM PGM handle.
3184	* @param GCPhys The GC physical address.
3185	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3186	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3187	*/
3188	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3189	{
3190	/*
3191	* Optimize for the first range.
3192	*/
3193	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3194	RTGCPHYS off = GCPhys - pRam->GCPhys;
3195	if (RT_UNLIKELY(off >= pRam->cb))
3196	{
3197	do
3198	{
3199	pRam = pRam->CTX_SUFF(pNext);
3200	if (RT_UNLIKELY(!pRam))
3201	{
3202	ppRam = NULL; / Shut up silly GCC warnings. */
3203	ppPage = NULL; / ditto */
3204	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3205	}
3206	off = GCPhys - pRam->GCPhys;
3207	} while (off >= pRam->cb);
3208	}
3209	*ppRam = pRam;
3210	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3211	#ifndef VBOX_WITH_NEW_PHYS_CODE
3212
3213	/*
3214	* Make sure it's present.
3215	*/
3216	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3217	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3218	{
3219	#ifdef IN_RING3
3220	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3221	#else
3222	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3223	#endif
3224	if (RT_FAILURE(rc))
3225	{
3226	ppPage = NULL; / Shut up silly GCC warnings. */
3227	ppPage = NULL; / ditto */
3228	return rc;
3229	}
3230	Assert(rc == VINF_SUCCESS);
3231
3232	}
3233	#endif
3234	return VINF_SUCCESS;
3235	}
3236
3237
3238	/**
3239	* Convert GC Phys to HC Phys.
3240	*
3241	* @returns VBox status.
3242	* @param pPGM PGM handle.
3243	* @param GCPhys The GC physical address.
3244	* @param pHCPhys Where to store the corresponding HC physical address.
3245	*
3246	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3247	* Avoid when writing new code!
3248	*/
3249	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3250	{
3251	PPGMPAGE pPage;
3252	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3253	if (RT_FAILURE(rc))
3254	return rc;
3255	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3256	return VINF_SUCCESS;
3257	}
3258
3259	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3260
3261	/**
3262	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3263	* optimizes access to pages already in the set.
3264	*
3265	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3266	* @param pPGM Pointer to the PVM instance data.
3267	* @param HCPhys The physical address of the page.
3268	* @param ppv Where to store the mapping address.
3269	*/
3270	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3271	{
3272	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3273	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3274	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3275	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3276
3277	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3278	unsigned iEntry = pSet->aiHashTable[iHash];
3279	if ( iEntry < pSet->cEntries
3280	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3281	{
3282	*ppv = pSet->aEntries[iEntry].pvPage;
3283	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3284	}
3285	else
3286	{
3287	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3288	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3289	}
3290
3291	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3292	return VINF_SUCCESS;
3293	}
3294
3295
3296	/**
3297	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3298	* access to pages already in the set.
3299	*
3300	* @returns See PGMDynMapGCPage.
3301	* @param pPGM Pointer to the PVM instance data.
3302	* @param HCPhys The physical address of the page.
3303	* @param ppv Where to store the mapping address.
3304	*/
3305	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3306	{
3307	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3308	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3309
3310	/*
3311	* Get the ram range.
3312	*/
3313	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3314	RTGCPHYS off = GCPhys - pRam->GCPhys;
3315	if (RT_UNLIKELY(off >= pRam->cb
3316	/** @todo \|\| page state stuff */))
3317	{
3318	/* This case is not counted into StatR0DynMapGCPageInl. */
3319	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3320	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3321	}
3322
3323	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3324	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3325
3326	/*
3327	* pgmR0DynMapHCPageInlined with out stats.
3328	*/
3329	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3330	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3331	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3332
3333	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3334	unsigned iEntry = pSet->aiHashTable[iHash];
3335	if ( iEntry < pSet->cEntries
3336	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3337	{
3338	*ppv = pSet->aEntries[iEntry].pvPage;
3339	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3340	}
3341	else
3342	{
3343	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3344	pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3345	}
3346
3347	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3348	return VINF_SUCCESS;
3349	}
3350
3351	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3352	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3353
3354	/**
3355	* Maps the page into current context (RC and maybe R0).
3356	*
3357	* @returns pointer to the mapping.
3358	* @param pVM Pointer to the PGM instance data.
3359	* @param pPage The page.
3360	*/
3361	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3362	{
3363	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3364	{
3365	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3366	void *pv;
3367	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3368	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3369	# else
3370	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3371	# endif
3372	return pv;
3373	}
3374	AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3375	}
3376
3377	/**
3378	* Temporarily maps one host page specified by HC physical address, returning
3379	* pointer within the page.
3380	*
3381	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3382	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3383	*
3384	* @returns The address corresponding to HCPhys.
3385	* @param pPGM Pointer to the PVM instance data.
3386	* @param HCPhys HC Physical address of the page.
3387	*/
3388	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3389	{
3390	void *pv;
3391	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3392	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3393	# else
3394	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3395	# endif
3396	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3397	return pv;
3398	}
3399
3400	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3401
3402	#ifndef IN_RC
3403	/**
3404	* Queries the Physical TLB entry for a physical guest page,
3405	* attemting to load the TLB entry if necessary.
3406	*
3407	* @returns VBox status code.
3408	* @retval VINF_SUCCESS on success
3409	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3410	*
3411	* @param pPGM The PGM instance handle.
3412	* @param GCPhys The address of the guest page.
3413	* @param ppTlbe Where to store the pointer to the TLB entry.
3414	*/
3415	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3416	{
3417	int rc;
3418	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3419	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3420	{
3421	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3422	rc = VINF_SUCCESS;
3423	}
3424	else
3425	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3426	*ppTlbe = pTlbe;
3427	return rc;
3428	}
3429
3430
3431	/**
3432	* Queries the Physical TLB entry for a physical guest page,
3433	* attemting to load the TLB entry if necessary.
3434	*
3435	* @returns VBox status code.
3436	* @retval VINF_SUCCESS on success
3437	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3438	*
3439	* @param pPGM The PGM instance handle.
3440	* @param pPage Pointer to the PGMPAGE structure corresponding to
3441	* GCPhys.
3442	* @param GCPhys The address of the guest page.
3443	* @param ppTlbe Where to store the pointer to the TLB entry.
3444	*/
3445	DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3446	{
3447	int rc;
3448	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3449	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3450	{
3451	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3452	rc = VINF_SUCCESS;
3453	}
3454	else
3455	rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3456	*ppTlbe = pTlbe;
3457	return rc;
3458	}
3459	#endif /* !IN_RC */
3460
3461
3462	#ifndef VBOX_WITH_NEW_PHYS_CODE
3463	/**
3464	* Convert GC Phys to HC Virt and HC Phys.
3465	*
3466	* @returns VBox status.
3467	* @param pPGM PGM handle.
3468	* @param GCPhys The GC physical address.
3469	* @param pHCPtr Where to store the corresponding HC virtual address.
3470	* @param pHCPhys Where to store the HC Physical address and its flags.
3471	*
3472	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3473	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3474	* Either way, we have to make sure the page is writable in MapCR3.
3475	*/
3476	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3477	{
3478	PPGMRAMRANGE pRam;
3479	PPGMPAGE pPage;
3480	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3481	if (RT_FAILURE(rc))
3482	{
3483	pHCPtr = 0; / Shut up crappy GCC warnings */
3484	pHCPhys = 0; / ditto */
3485	return rc;
3486	}
3487	RTGCPHYS off = GCPhys - pRam->GCPhys;
3488
3489	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3490	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3491	{
3492	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3493	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3494	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3495	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3496	#else
3497	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3498	#endif
3499	return VINF_SUCCESS;
3500	}
3501	if (pRam->pvR3)
3502	{
3503	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3504	return VINF_SUCCESS;
3505	}
3506	*pHCPtr = 0;
3507	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3508	}
3509	#endif /* VBOX_WITH_NEW_PHYS_CODE */
3510
3511
3512	/**
3513	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3514	* Takes PSE-36 into account.
3515	*
3516	* @returns guest physical address
3517	* @param pPGM Pointer to the PGM instance data.
3518	* @param Pde Guest Pde
3519	*/
3520	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3521	{
3522	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3523	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3524
3525	return GCPhys & pPGM->GCPhys4MBPSEMask;
3526	}
3527
3528
3529	/**
3530	* Gets the page directory entry for the specified address (32-bit paging).
3531	*
3532	* @returns The page directory entry in question.
3533	* @param pPGM Pointer to the PGM instance data.
3534	* @param GCPtr The address.
3535	*/
3536	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3537	{
3538	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3539	PCX86PD pGuestPD = NULL;
3540	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3541	if (RT_FAILURE(rc))
3542	{
3543	X86PDE ZeroPde = {0};
3544	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3545	}
3546	#else
3547	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3548	# ifdef VBOX_WITH_NEW_PHYS_CODE
3549	# ifdef IN_RING3
3550	if (!pGuestPD)
3551	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3552	# endif
3553	# endif
3554	#endif
3555	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3556	}
3557
3558
3559	/**
3560	* Gets the address of a specific page directory entry (32-bit paging).
3561	*
3562	* @returns Pointer the page directory entry in question.
3563	* @param pPGM Pointer to the PGM instance data.
3564	* @param GCPtr The address.
3565	*/
3566	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3567	{
3568	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3569	PX86PD pGuestPD = NULL;
3570	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3571	AssertRCReturn(rc, NULL);
3572	#else
3573	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3574	# ifdef VBOX_WITH_NEW_PHYS_CODE
3575	# ifdef IN_RING3
3576	if (!pGuestPD)
3577	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3578	# endif
3579	# endif
3580	#endif
3581	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3582	}
3583
3584
3585	/**
3586	* Gets the address the guest page directory (32-bit paging).
3587	*
3588	* @returns Pointer the page directory entry in question.
3589	* @param pPGM Pointer to the PGM instance data.
3590	*/
3591	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3592	{
3593	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3594	PX86PD pGuestPD = NULL;
3595	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3596	AssertRCReturn(rc, NULL);
3597	#else
3598	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3599	# ifdef VBOX_WITH_NEW_PHYS_CODE
3600	# ifdef IN_RING3
3601	if (!pGuestPD)
3602	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3603	# endif
3604	# endif
3605	#endif
3606	return pGuestPD;
3607	}
3608
3609
3610	/**
3611	* Gets the guest page directory pointer table.
3612	*
3613	* @returns Pointer to the page directory in question.
3614	* @returns NULL if the page directory is not present or on an invalid page.
3615	* @param pPGM Pointer to the PGM instance data.
3616	*/
3617	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3618	{
3619	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3620	PX86PDPT pGuestPDPT = NULL;
3621	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3622	AssertRCReturn(rc, NULL);
3623	#else
3624	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3625	# ifdef VBOX_WITH_NEW_PHYS_CODE
3626	# ifdef IN_RING3
3627	if (!pGuestPDPT)
3628	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3629	# endif
3630	# endif
3631	#endif
3632	return pGuestPDPT;
3633	}
3634
3635
3636	/**
3637	* Gets the guest page directory pointer table entry for the specified address.
3638	*
3639	* @returns Pointer to the page directory in question.
3640	* @returns NULL if the page directory is not present or on an invalid page.
3641	* @param pPGM Pointer to the PGM instance data.
3642	* @param GCPtr The address.
3643	*/
3644	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3645	{
3646	AssertGCPtr32(GCPtr);
3647
3648	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3649	PX86PDPT pGuestPDPT = 0;
3650	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3651	AssertRCReturn(rc, 0);
3652	#else
3653	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3654	# ifdef VBOX_WITH_NEW_PHYS_CODE
3655	# ifdef IN_RING3
3656	if (!pGuestPDPT)
3657	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3658	# endif
3659	# endif
3660	#endif
3661	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3662	}
3663
3664
3665	/**
3666	* Gets the page directory for the specified address.
3667	*
3668	* @returns Pointer to the page directory in question.
3669	* @returns NULL if the page directory is not present or on an invalid page.
3670	* @param pPGM Pointer to the PGM instance data.
3671	* @param GCPtr The address.
3672	*/
3673	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3674	{
3675	AssertGCPtr32(GCPtr);
3676
3677	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3678	AssertReturn(pGuestPDPT, NULL);
3679	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3680	if (pGuestPDPT->a[iPdpt].n.u1Present)
3681	{
3682	#ifdef VBOX_WITH_NEW_PHYS_CODE
3683	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3684	PX86PDPAE pGuestPD = NULL;
3685	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3686	AssertRCReturn(rc, NULL);
3687	#else
3688	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3689	if ( !pGuestPD
3690	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3691	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3692	#endif
3693	return pGuestPD;
3694	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3695	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3696	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3697	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3698	#endif
3699
3700	/* cache is out-of-sync. */
3701	PX86PDPAE pPD;
3702	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3703	if (RT_SUCCESS(rc))
3704	return pPD;
3705	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdpt].u));
3706	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3707	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3708	}
3709	return NULL;
3710	}
3711
3712
3713	/**
3714	* Gets the page directory entry for the specified address.
3715	*
3716	* @returns Pointer to the page directory entry in question.
3717	* @returns NULL if the page directory is not present or on an invalid page.
3718	* @param pPGM Pointer to the PGM instance data.
3719	* @param GCPtr The address.
3720	*/
3721	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3722	{
3723	AssertGCPtr32(GCPtr);
3724
3725	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3726	AssertReturn(pGuestPDPT, NULL);
3727	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3728	if (pGuestPDPT->a[iPdpt].n.u1Present)
3729	{
3730	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3731	#ifdef VBOX_WITH_NEW_PHYS_CODE
3732	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3733	PX86PDPAE pGuestPD = NULL;
3734	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3735	AssertRCReturn(rc, NULL);
3736	#else
3737	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3738	if ( !pGuestPD
3739	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3740	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3741	#endif
3742	return &pGuestPD->a[iPD];
3743	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3744	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3745	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3746	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdpt]->a[iPD];
3747	#endif
3748
3749	/* The cache is out-of-sync. */
3750	PX86PDPAE pPD;
3751	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3752	if (RT_SUCCESS(rc))
3753	return &pPD->a[iPD];
3754	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdpt].u));
3755	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3756	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3757	}
3758	return NULL;
3759	}
3760
3761
3762	/**
3763	* Gets the page directory entry for the specified address.
3764	*
3765	* @returns The page directory entry in question.
3766	* @returns A non-present entry if the page directory is not present or on an invalid page.
3767	* @param pPGM Pointer to the PGM instance data.
3768	* @param GCPtr The address.
3769	*/
3770	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3771	{
3772	AssertGCPtr32(GCPtr);
3773	X86PDEPAE ZeroPde = {0};
3774	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3775	if (RT_LIKELY(pGuestPDPT))
3776	{
3777	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3778	if (pGuestPDPT->a[iPdpt].n.u1Present)
3779	{
3780	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3781	#ifdef VBOX_WITH_NEW_PHYS_CODE
3782	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3783	PX86PDPAE pGuestPD = NULL;
3784	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3785	AssertRCReturn(rc, ZeroPde);
3786	#else
3787	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3788	if ( !pGuestPD
3789	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3790	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3791	#endif
3792	return pGuestPD->a[iPD];
3793	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3794	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3795	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3796	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt]->a[iPD];
3797	#endif
3798
3799	/* cache is out-of-sync. */
3800	PX86PDPAE pPD;
3801	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3802	if (RT_SUCCESS(rc))
3803	return pPD->a[iPD];
3804	AssertMsgFailed(("Impossible! rc=%d PDPE=%RX64\n", rc, pGuestPDPT->a[iPdpt].u));
3805	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3806	}
3807	}
3808	return ZeroPde;
3809	}
3810
3811
3812	/**
3813	* Gets the page directory pointer table entry for the specified address
3814	* and returns the index into the page directory
3815	*
3816	* @returns Pointer to the page directory in question.
3817	* @returns NULL if the page directory is not present or on an invalid page.
3818	* @param pPGM Pointer to the PGM instance data.
3819	* @param GCPtr The address.
3820	* @param piPD Receives the index into the returned page directory
3821	* @param pPdpe Receives the page directory pointer entry. Optional.
3822	*/
3823	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3824	{
3825	AssertGCPtr32(GCPtr);
3826
3827	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3828	AssertReturn(pGuestPDPT, NULL);
3829	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3830	if (pPdpe)
3831	*pPdpe = pGuestPDPT->a[iPdpt];
3832	if (pGuestPDPT->a[iPdpt].n.u1Present)
3833	{
3834	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3835	#ifdef VBOX_WITH_NEW_PHYS_CODE
3836	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3837	PX86PDPAE pGuestPD = NULL;
3838	int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3839	AssertRCReturn(rc, NULL);
3840	#else
3841	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3842	if ( !pGuestPD
3843	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3844	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3845	#endif
3846	*piPD = iPD;
3847	return pGuestPD;
3848	#else /* !VBOX_WITH_NEW_PHYS_CODE */
3849	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3850	if ((pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdpt])
3851	{
3852	*piPD = iPD;
3853	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3854	}
3855	#endif
3856
3857	/* cache is out-of-sync. */
3858	PX86PDPAE pPD;
3859	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3860	if (RT_SUCCESS(rc))
3861	{
3862	*piPD = iPD;
3863	return pPD;
3864	}
3865	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdpt].u));
3866	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3867	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3868	}
3869	return NULL;
3870	}
3871
3872	#ifndef IN_RC
3873
3874	/**
3875	* Gets the page map level-4 pointer for the guest.
3876	*
3877	* @returns Pointer to the PML4 page.
3878	* @param pPGM Pointer to the PGM instance data.
3879	*/
3880	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3881	{
3882	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3883	PX86PML4 pGuestPml4;
3884	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3885	AssertRCReturn(rc, NULL);
3886	#else
3887	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3888	# ifdef VBOX_WITH_NEW_PHYS_CODE
3889	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3890	if (!pGuestPml4)
3891	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3892	# endif
3893	# endif
3894	Assert(pGuestPml4);
3895	#endif
3896	return pGuestPml4;
3897	}
3898
3899
3900	/**
3901	* Gets the pointer to a page map level-4 entry.
3902	*
3903	* @returns Pointer to the PML4 entry.
3904	* @param pPGM Pointer to the PGM instance data.
3905	* @param iPml4 The index.
3906	*/
3907	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3908	{
3909	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3910	PX86PML4 pGuestPml4;
3911	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3912	AssertRCReturn(rc, NULL);
3913	#else
3914	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3915	# ifdef VBOX_WITH_NEW_PHYS_CODE
3916	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3917	if (!pGuestPml4)
3918	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3919	# endif
3920	# endif
3921	Assert(pGuestPml4);
3922	#endif
3923	return &pGuestPml4->a[iPml4];
3924	}
3925
3926
3927	/**
3928	* Gets a page map level-4 entry.
3929	*
3930	* @returns The PML4 entry.
3931	* @param pPGM Pointer to the PGM instance data.
3932	* @param iPml4 The index.
3933	*/
3934	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3935	{
3936	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3937	PX86PML4 pGuestPml4;
3938	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3939	if (RT_FAILURE(rc))
3940	{
3941	X86PML4E ZeroPml4e = {0};
3942	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3943	}
3944	#else
3945	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3946	# ifdef VBOX_WITH_NEW_PHYS_CODE
3947	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3948	if (!pGuestPml4)
3949	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3950	# endif
3951	# endif
3952	Assert(pGuestPml4);
3953	#endif
3954	return pGuestPml4->a[iPml4];
3955	}
3956
3957
3958	/**
3959	* Gets the page directory pointer entry for the specified address.
3960	*
3961	* @returns Pointer to the page directory pointer entry in question.
3962	* @returns NULL if the page directory is not present or on an invalid page.
3963	* @param pPGM Pointer to the PGM instance data.
3964	* @param GCPtr The address.
3965	* @param ppPml4e Page Map Level-4 Entry (out)
3966	*/
3967	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3968	{
3969	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3970	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3971	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3972	if (pPml4e->n.u1Present)
3973	{
3974	PX86PDPT pPdpt;
3975	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3976	AssertRCReturn(rc, NULL);
3977
3978	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3979	return &pPdpt->a[iPdpt];
3980	}
3981	return NULL;
3982	}
3983
3984
3985	/**
3986	* Gets the page directory entry for the specified address.
3987	*
3988	* @returns The page directory entry in question.
3989	* @returns A non-present entry if the page directory is not present or on an invalid page.
3990	* @param pPGM Pointer to the PGM instance data.
3991	* @param GCPtr The address.
3992	* @param ppPml4e Page Map Level-4 Entry (out)
3993	* @param pPdpe Page directory pointer table entry (out)
3994	*/
3995	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3996	{
3997	X86PDEPAE ZeroPde = {0};
3998	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3999	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4000	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4001	if (pPml4e->n.u1Present)
4002	{
4003	PCX86PDPT pPdptTemp;
4004	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4005	AssertRCReturn(rc, ZeroPde);
4006
4007	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4008	*pPdpe = pPdptTemp->a[iPdpt];
4009	if (pPdptTemp->a[iPdpt].n.u1Present)
4010	{
4011	PCX86PDPAE pPD;
4012	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4013	AssertRCReturn(rc, ZeroPde);
4014
4015	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4016	return pPD->a[iPD];
4017	}
4018	}
4019
4020	return ZeroPde;
4021	}
4022
4023
4024	/**
4025	* Gets the page directory entry for the specified address.
4026	*
4027	* @returns The page directory entry in question.
4028	* @returns A non-present entry if the page directory is not present or on an invalid page.
4029	* @param pPGM Pointer to the PGM instance data.
4030	* @param GCPtr The address.
4031	*/
4032	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4033	{
4034	X86PDEPAE ZeroPde = {0};
4035	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4036	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4037	if (pGuestPml4->a[iPml4].n.u1Present)
4038	{
4039	PCX86PDPT pPdptTemp;
4040	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4041	AssertRCReturn(rc, ZeroPde);
4042
4043	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4044	if (pPdptTemp->a[iPdpt].n.u1Present)
4045	{
4046	PCX86PDPAE pPD;
4047	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4048	AssertRCReturn(rc, ZeroPde);
4049
4050	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4051	return pPD->a[iPD];
4052	}
4053	}
4054	return ZeroPde;
4055	}
4056
4057
4058	/**
4059	* Gets the page directory entry for the specified address.
4060	*
4061	* @returns Pointer to the page directory entry in question.
4062	* @returns NULL if the page directory is not present or on an invalid page.
4063	* @param pPGM Pointer to the PGM instance data.
4064	* @param GCPtr The address.
4065	*/
4066	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4067	{
4068	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4069	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4070	if (pGuestPml4->a[iPml4].n.u1Present)
4071	{
4072	PCX86PDPT pPdptTemp;
4073	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4074	AssertRCReturn(rc, NULL);
4075
4076	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4077	if (pPdptTemp->a[iPdpt].n.u1Present)
4078	{
4079	PX86PDPAE pPD;
4080	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4081	AssertRCReturn(rc, NULL);
4082
4083	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4084	return &pPD->a[iPD];
4085	}
4086	}
4087	return NULL;
4088	}
4089
4090
4091	/**
4092	* Gets the GUEST page directory pointer for the specified address.
4093	*
4094	* @returns The page directory in question.
4095	* @returns NULL if the page directory is not present or on an invalid page.
4096	* @param pPGM Pointer to the PGM instance data.
4097	* @param GCPtr The address.
4098	* @param ppPml4e Page Map Level-4 Entry (out)
4099	* @param pPdpe Page directory pointer table entry (out)
4100	* @param piPD Receives the index into the returned page directory
4101	*/
4102	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4103	{
4104	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4105	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4106	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4107	if (pPml4e->n.u1Present)
4108	{
4109	PCX86PDPT pPdptTemp;
4110	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4111	AssertRCReturn(rc, NULL);
4112
4113	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4114	*pPdpe = pPdptTemp->a[iPdpt];
4115	if (pPdptTemp->a[iPdpt].n.u1Present)
4116	{
4117	PX86PDPAE pPD;
4118	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4119	AssertRCReturn(rc, NULL);
4120
4121	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4122	return pPD;
4123	}
4124	}
4125	return 0;
4126	}
4127
4128	#endif /* !IN_RC */
4129
4130	/**
4131	* Gets the shadow page directory, 32-bit.
4132	*
4133	* @returns Pointer to the shadow 32-bit PD.
4134	* @param pPGM Pointer to the PGM instance data.
4135	*/
4136	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4137	{
4138	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4139	}
4140
4141
4142	/**
4143	* Gets the shadow page directory entry for the specified address, 32-bit.
4144	*
4145	* @returns Shadow 32-bit PDE.
4146	* @param pPGM Pointer to the PGM instance data.
4147	* @param GCPtr The address.
4148	*/
4149	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4150	{
4151	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4152
4153	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4154	if (!pShwPde)
4155	{
4156	X86PDE ZeroPde = {0};
4157	return ZeroPde;
4158	}
4159	return pShwPde->a[iPd];
4160	}
4161
4162
4163	/**
4164	* Gets the pointer to the shadow page directory entry for the specified
4165	* address, 32-bit.
4166	*
4167	* @returns Pointer to the shadow 32-bit PDE.
4168	* @param pPGM Pointer to the PGM instance data.
4169	* @param GCPtr The address.
4170	*/
4171	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4172	{
4173	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4174
4175	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4176	AssertReturn(pPde, NULL);
4177	return &pPde->a[iPd];
4178	}
4179
4180
4181	/**
4182	* Gets the shadow page pointer table, PAE.
4183	*
4184	* @returns Pointer to the shadow PAE PDPT.
4185	* @param pPGM Pointer to the PGM instance data.
4186	*/
4187	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4188	{
4189	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4190	}
4191
4192
4193	/**
4194	* Gets the shadow page directory for the specified address, PAE.
4195	*
4196	* @returns Pointer to the shadow PD.
4197	* @param pPGM Pointer to the PGM instance data.
4198	* @param GCPtr The address.
4199	*/
4200	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4201	{
4202	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4203	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4204
4205	if (!pPdpt->a[iPdpt].n.u1Present)
4206	return NULL;
4207
4208	/* Fetch the pgm pool shadow descriptor. */
4209	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4210	AssertReturn(pShwPde, NULL);
4211
4212	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4213	}
4214
4215
4216	/**
4217	* Gets the shadow page directory for the specified address, PAE.
4218	*
4219	* @returns Pointer to the shadow PD.
4220	* @param pPGM Pointer to the PGM instance data.
4221	* @param GCPtr The address.
4222	*/
4223	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4224	{
4225	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4226
4227	if (!pPdpt->a[iPdpt].n.u1Present)
4228	return NULL;
4229
4230	/* Fetch the pgm pool shadow descriptor. */
4231	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4232	AssertReturn(pShwPde, NULL);
4233
4234	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4235	}
4236
4237
4238	/**
4239	* Gets the shadow page directory entry, PAE.
4240	*
4241	* @returns PDE.
4242	* @param pPGM Pointer to the PGM instance data.
4243	* @param GCPtr The address.
4244	*/
4245	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4246	{
4247	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4248
4249	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4250	if (!pShwPde)
4251	{
4252	X86PDEPAE ZeroPde = {0};
4253	return ZeroPde;
4254	}
4255	return pShwPde->a[iPd];
4256	}
4257
4258
4259	/**
4260	* Gets the pointer to the shadow page directory entry for an address, PAE.
4261	*
4262	* @returns Pointer to the PDE.
4263	* @param pPGM Pointer to the PGM instance data.
4264	* @param GCPtr The address.
4265	*/
4266	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4267	{
4268	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4269
4270	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4271	AssertReturn(pPde, NULL);
4272	return &pPde->a[iPd];
4273	}
4274
4275	#ifndef IN_RC
4276
4277	/**
4278	* Gets the shadow page map level-4 pointer.
4279	*
4280	* @returns Pointer to the shadow PML4.
4281	* @param pPGM Pointer to the PGM instance data.
4282	*/
4283	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4284	{
4285	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4286	}
4287
4288
4289	/**
4290	* Gets the shadow page map level-4 entry for the specified address.
4291	*
4292	* @returns The entry.
4293	* @param pPGM Pointer to the PGM instance data.
4294	* @param GCPtr The address.
4295	*/
4296	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4297	{
4298	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4299	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4300
4301	if (!pShwPml4)
4302	{
4303	X86PML4E ZeroPml4e = {0};
4304	return ZeroPml4e;
4305	}
4306	return pShwPml4->a[iPml4];
4307	}
4308
4309
4310	/**
4311	* Gets the pointer to the specified shadow page map level-4 entry.
4312	*
4313	* @returns The entry.
4314	* @param pPGM Pointer to the PGM instance data.
4315	* @param iPml4 The PML4 index.
4316	*/
4317	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4318	{
4319	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4320	if (!pShwPml4)
4321	return NULL;
4322	return &pShwPml4->a[iPml4];
4323	}
4324
4325
4326	/**
4327	* Gets the GUEST page directory pointer for the specified address.
4328	*
4329	* @returns The page directory in question.
4330	* @returns NULL if the page directory is not present or on an invalid page.
4331	* @param pPGM Pointer to the PGM instance data.
4332	* @param GCPtr The address.
4333	* @param piPD Receives the index into the returned page directory
4334	*/
4335	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4336	{
4337	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4338	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4339	if (pGuestPml4->a[iPml4].n.u1Present)
4340	{
4341	PCX86PDPT pPdptTemp;
4342	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4343	AssertRCReturn(rc, NULL);
4344
4345	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4346	if (pPdptTemp->a[iPdpt].n.u1Present)
4347	{
4348	PX86PDPAE pPD;
4349	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4350	AssertRCReturn(rc, NULL);
4351
4352	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4353	return pPD;
4354	}
4355	}
4356	return NULL;
4357	}
4358
4359	#endif /* !IN_RC */
4360
4361	/**
4362	* Gets the page state for a physical handler.
4363	*
4364	* @returns The physical handler page state.
4365	* @param pCur The physical handler in question.
4366	*/
4367	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4368	{
4369	switch (pCur->enmType)
4370	{
4371	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4372	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4373
4374	case PGMPHYSHANDLERTYPE_MMIO:
4375	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4376	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4377
4378	default:
4379	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4380	}
4381	}
4382
4383
4384	/**
4385	* Gets the page state for a virtual handler.
4386	*
4387	* @returns The virtual handler page state.
4388	* @param pCur The virtual handler in question.
4389	* @remarks This should never be used on a hypervisor access handler.
4390	*/
4391	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4392	{
4393	switch (pCur->enmType)
4394	{
4395	case PGMVIRTHANDLERTYPE_WRITE:
4396	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4397	case PGMVIRTHANDLERTYPE_ALL:
4398	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4399	default:
4400	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4401	}
4402	}
4403
4404
4405	/**
4406	* Clears one physical page of a virtual handler
4407	*
4408	* @param pPGM Pointer to the PGM instance.
4409	* @param pCur Virtual handler structure
4410	* @param iPage Physical page index
4411	*
4412	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4413	* need to care about other handlers in the same page.
4414	*/
4415	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4416	{
4417	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4418
4419	/*
4420	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4421	*/
4422	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4423	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4424	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4425	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4426	#endif
4427	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4428	{
4429	/* We're the head of the alias chain. */
4430	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4431	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4432	AssertReleaseMsg(pRemove != NULL,
4433	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4434	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4435	AssertReleaseMsg(pRemove == pPhys2Virt,
4436	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4437	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4438	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4439	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4440	#endif
4441	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4442	{
4443	/* Insert the next list in the alias chain into the tree. */
4444	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4445	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4446	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4447	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4448	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4449	#endif
4450	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4451	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4452	AssertRelease(fRc);
4453	}
4454	}
4455	else
4456	{
4457	/* Locate the previous node in the alias chain. */
4458	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4459	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4460	AssertReleaseMsg(pPrev != pPhys2Virt,
4461	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4462	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4463	#endif
4464	for (;;)
4465	{
4466	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4467	if (pNext == pPhys2Virt)
4468	{
4469	/* unlink. */
4470	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4471	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4472	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4473	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4474	else
4475	{
4476	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4477	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4478	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4479	}
4480	break;
4481	}
4482
4483	/* next */
4484	if (pNext == pPrev)
4485	{
4486	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4487	AssertReleaseMsg(pNext != pPrev,
4488	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4489	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4490	#endif
4491	break;
4492	}
4493	pPrev = pNext;
4494	}
4495	}
4496	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4497	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4498	pPhys2Virt->offNextAlias = 0;
4499	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4500
4501	/*
4502	* Clear the ram flags for this page.
4503	*/
4504	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4505	AssertReturnVoid(pPage);
4506	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4507	}
4508
4509
4510	/**
4511	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4512	*
4513	* @returns Pointer to the shadow page structure.
4514	* @param pPool The pool.
4515	* @param HCPhys The HC physical address of the shadow page.
4516	*/
4517	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4518	{
4519	/*
4520	* Look up the page.
4521	*/
4522	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4523	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4524	return pPage;
4525	}
4526
4527
4528	/**
4529	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4530	*
4531	* @returns Pointer to the shadow page structure.
4532	* @param pPool The pool.
4533	* @param idx The pool page index.
4534	*/
4535	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4536	{
4537	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4538	return &pPool->aPages[idx];
4539	}
4540
4541
4542	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4543	/**
4544	* Clear references to guest physical memory.
4545	*
4546	* @param pPool The pool.
4547	* @param pPoolPage The pool page.
4548	* @param pPhysPage The physical guest page tracking structure.
4549	*/
4550	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4551	{
4552	/*
4553	* Just deal with the simple case here.
4554	*/
4555	# ifdef LOG_ENABLED
4556	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4557	# endif
4558	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4559	if (cRefs == 1)
4560	{
4561	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4562	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4563	}
4564	else
4565	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4566	Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4567	}
4568	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4569
4570
4571	#ifdef PGMPOOL_WITH_CACHE
4572	/**
4573	* Moves the page to the head of the age list.
4574	*
4575	* This is done when the cached page is used in one way or another.
4576	*
4577	* @param pPool The pool.
4578	* @param pPage The cached page.
4579	* @todo inline in PGMInternal.h!
4580	*/
4581	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4582	{
4583	/*
4584	* Move to the head of the age list.
4585	*/
4586	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4587	{
4588	/* unlink */
4589	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4590	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4591	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4592	else
4593	pPool->iAgeTail = pPage->iAgePrev;
4594
4595	/* insert at head */
4596	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4597	pPage->iAgeNext = pPool->iAgeHead;
4598	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4599	pPool->iAgeHead = pPage->idx;
4600	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4601	}
4602	}
4603	#endif /* PGMPOOL_WITH_CACHE */
4604
4605	/**
4606	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4607	*
4608	* @param pVM VM Handle.
4609	* @param pPage PGM pool page
4610	*/
4611	DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4612	{
4613	Assert(!pPage->fLocked);
4614	pPage->fLocked = true;
4615	}
4616
4617
4618	/**
4619	* Unlocks a page to allow flushing again
4620	*
4621	* @param pVM VM Handle.
4622	* @param pPage PGM pool page
4623	*/
4624	DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4625	{
4626	Assert(pPage->fLocked);
4627	pPage->fLocked = false;
4628	}
4629
4630
4631	/**
4632	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4633	*
4634	* @returns VBox status code.
4635	* @param pPage PGM pool page
4636	*/
4637	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4638	{
4639	if (pPage->fLocked)
4640	{
4641	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4642	if (pPage->cModifications)
4643	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4644	return true;
4645	}
4646	return false;
4647	}
4648
4649	/**
4650	* Tells if mappings are to be put into the shadow page table or not
4651	*
4652	* @returns boolean result
4653	* @param pVM VM handle.
4654	*/
4655	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4656	{
4657	#ifdef IN_RING0
4658	/* There are no mappings in VT-x and AMD-V mode. */
4659	Assert(pPGM->fDisableMappings);
4660	return false;
4661	#else
4662	return !pPGM->fDisableMappings;
4663	#endif
4664	}
4665
4666	/** @} */
4667
4668	#endif
4669

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 18344

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