VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 18761

Last change on this file since 18761 was 18746, checked in by vboxsync, 16 years ago

PGMInternal.h: Marked PGM_SYNC_MONITOR_CR3 as obsolete and scheduled it for removal after 2.2.0.
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1/* $Id: PGMInternal.h 18746 2009-04-06 11:20:27Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/**
57 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58 * Comment it if it will break something.
59 */
60#define PGM_OUT_OF_SYNC_IN_GC
61
62/**
63 * Check and skip global PDEs for non-global flushes
64 */
65#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67/**
68 * Sync N pages instead of a whole page table
69 */
70#define PGM_SYNC_N_PAGES
71
72/**
73 * Number of pages to sync during a page fault
74 *
75 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77 */
78#define PGM_SYNC_NR_PAGES 8
79
80/**
81 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82 */
83#define PGM_MAX_PHYSCACHE_ENTRIES 64
84#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86/**
87 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88 */
89#define PGM_PHYSMEMACCESS_CACHING
90
91/** @def PGMPOOL_WITH_CACHE
92 * Enable agressive caching using the page pool.
93 *
94 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95 */
96#define PGMPOOL_WITH_CACHE
97
98/** @def PGMPOOL_WITH_MIXED_PT_CR3
99 * When defined, we'll deal with 'uncachable' pages.
100 */
101#ifdef PGMPOOL_WITH_CACHE
102# define PGMPOOL_WITH_MIXED_PT_CR3
103#endif
104
105/** @def PGMPOOL_WITH_MONITORING
106 * Monitor the guest pages which are shadowed.
107 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108 * be enabled as well.
109 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110 */
111#ifdef PGMPOOL_WITH_CACHE
112# define PGMPOOL_WITH_MONITORING
113#endif
114
115/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116 * Tracking the of shadow pages mapping guest physical pages.
117 *
118 * This is very expensive, the current cache prototype is trying to figure out
119 * whether it will be acceptable with an agressive caching policy.
120 */
121#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
122# define PGMPOOL_WITH_GCPHYS_TRACKING
123#endif
124
125/** @def PGMPOOL_WITH_USER_TRACKING
126 * Tracking users of shadow pages. This is required for the linking of shadow page
127 * tables and physical guest addresses.
128 */
129#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
130# define PGMPOOL_WITH_USER_TRACKING
131#endif
132
133/** @def PGMPOOL_CFG_MAX_GROW
134 * The maximum number of pages to add to the pool in one go.
135 */
136#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
140 */
141#ifdef VBOX_STRICT
142# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143#endif
144
145/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
146 * Enables the experimental lazy page allocation code. */
147/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
148
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** @} */
188
189/** @name Defines used to indicate the shadow and guest paging in the templates.
190 * @{ */
191#define PGM_TYPE_REAL 1
192#define PGM_TYPE_PROT 2
193#define PGM_TYPE_32BIT 3
194#define PGM_TYPE_PAE 4
195#define PGM_TYPE_AMD64 5
196#define PGM_TYPE_NESTED 6
197#define PGM_TYPE_EPT 7
198#define PGM_TYPE_MAX PGM_TYPE_EPT
199/** @} */
200
201/** Macro for checking if the guest is using paging.
202 * @param uGstType PGM_TYPE_*
203 * @param uShwType PGM_TYPE_*
204 * @remark ASSUMES certain order of the PGM_TYPE_* values.
205 */
206#define PGM_WITH_PAGING(uGstType, uShwType) \
207 ( (uGstType) >= PGM_TYPE_32BIT \
208 && (uShwType) != PGM_TYPE_NESTED \
209 && (uShwType) != PGM_TYPE_EPT)
210
211/** Macro for checking if the guest supports the NX bit.
212 * @param uGstType PGM_TYPE_*
213 * @param uShwType PGM_TYPE_*
214 * @remark ASSUMES certain order of the PGM_TYPE_* values.
215 */
216#define PGM_WITH_NX(uGstType, uShwType) \
217 ( (uGstType) >= PGM_TYPE_PAE \
218 && (uShwType) != PGM_TYPE_NESTED \
219 && (uShwType) != PGM_TYPE_EPT)
220
221
222/** @def PGM_HCPHYS_2_PTR
223 * Maps a HC physical page pool address to a virtual address.
224 *
225 * @returns VBox status code.
226 * @param pVM The VM handle.
227 * @param HCPhys The HC physical address to map to a virtual one.
228 * @param ppv Where to store the virtual address. No need to cast this.
229 *
230 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
231 * small page window employeed by that function. Be careful.
232 * @remark There is no need to assert on the result.
233 */
234#ifdef IN_RC
235# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
237#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
240#else
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
243#endif
244
245/** @def PGM_HCPHYS_2_PTR_BY_PGM
246 * Maps a HC physical page pool address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pPGM The PGM instance data.
250 * @param HCPhys The HC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
258# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
259 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
260#else
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
263#endif
264
265/** @def PGM_GCPHYS_2_PTR
266 * Maps a GC physical page address to a virtual address.
267 *
268 * @returns VBox status code.
269 * @param pVM The VM handle.
270 * @param GCPhys The GC physical address to map to a virtual one.
271 * @param ppv Where to store the virtual address. No need to cast this.
272 *
273 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
274 * small page window employeed by that function. Be careful.
275 * @remark There is no need to assert on the result.
276 */
277#ifdef IN_RC
278# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
280#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
283#else
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
286#endif
287
288/** @def PGM_GCPHYS_2_PTR_BY_PGM
289 * Maps a GC physical page address to a virtual address.
290 *
291 * @returns VBox status code.
292 * @param pPGM Pointer to the PGM instance data.
293 * @param GCPhys The GC physical address to map to a virtual one.
294 * @param ppv Where to store the virtual address. No need to cast this.
295 *
296 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
297 * small page window employeed by that function. Be careful.
298 * @remark There is no need to assert on the result.
299 */
300#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
301# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
302 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
303#else
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
306#endif
307
308/** @def PGM_GCPHYS_2_PTR_EX
309 * Maps a unaligned GC physical page address to a virtual address.
310 *
311 * @returns VBox status code.
312 * @param pVM The VM handle.
313 * @param GCPhys The GC physical address to map to a virtual one.
314 * @param ppv Where to store the virtual address. No need to cast this.
315 *
316 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
317 * small page window employeed by that function. Be careful.
318 * @remark There is no need to assert on the result.
319 */
320#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
321# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
322 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
323#else
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
326#endif
327
328/** @def PGM_INVL_PG
329 * Invalidates a page when in GC does nothing in HC.
330 *
331 * @param GCVirt The virtual address of the page to invalidate.
332 */
333#ifdef IN_RC
334# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
335#elif defined(IN_RING0)
336# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
337#else
338# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
339#endif
340
341/** @def PGM_INVL_BIG_PG
342 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
343 *
344 * @param GCVirt The virtual address within the page directory to invalidate.
345 */
346#ifdef IN_RC
347# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
348#elif defined(IN_RING0)
349# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
350#else
351# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
352#endif
353
354/** @def PGM_INVL_GUEST_TLBS()
355 * Invalidates all guest TLBs.
356 */
357#ifdef IN_RC
358# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
359#elif defined(IN_RING0)
360# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
361#else
362# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
363#endif
364
365/** Size of the GCPtrConflict array in PGMMAPPING.
366 * @remarks Must be a power of two. */
367#define PGMMAPPING_CONFLICT_MAX 8
368
369/**
370 * Structure for tracking GC Mappings.
371 *
372 * This structure is used by linked list in both GC and HC.
373 */
374typedef struct PGMMAPPING
375{
376 /** Pointer to next entry. */
377 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378 /** Pointer to next entry. */
379 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380 /** Pointer to next entry. */
381 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382 /** Indicate whether this entry is finalized. */
383 bool fFinalized;
384 /** Start Virtual address. */
385 RTGCPTR GCPtr;
386 /** Last Virtual address (inclusive). */
387 RTGCPTR GCPtrLast;
388 /** Range size (bytes). */
389 RTGCPTR cb;
390 /** Pointer to relocation callback function. */
391 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392 /** User argument to the callback. */
393 R3PTRTYPE(void *) pvUser;
394 /** Mapping description / name. For easing debugging. */
395 R3PTRTYPE(const char *) pszDesc;
396 /** Last 8 addresses that caused conflicts. */
397 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
398 /** Number of conflicts for this hypervisor mapping. */
399 uint32_t cConflicts;
400 /** Number of page tables. */
401 uint32_t cPTs;
402
403 /** Array of page table mapping data. Each entry
404 * describes one page table. The array can be longer
405 * than the declared length.
406 */
407 struct
408 {
409 /** The HC physical address of the page table. */
410 RTHCPHYS HCPhysPT;
411 /** The HC physical address of the first PAE page table. */
412 RTHCPHYS HCPhysPaePT0;
413 /** The HC physical address of the second PAE page table. */
414 RTHCPHYS HCPhysPaePT1;
415 /** The HC virtual address of the 32-bit page table. */
416 R3PTRTYPE(PX86PT) pPTR3;
417 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
418 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
419 /** The GC virtual address of the 32-bit page table. */
420 RCPTRTYPE(PX86PT) pPTRC;
421 /** The GC virtual address of the two PAE page table. */
422 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
423 /** The GC virtual address of the 32-bit page table. */
424 R0PTRTYPE(PX86PT) pPTR0;
425 /** The GC virtual address of the two PAE page table. */
426 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
427 } aPTs[1];
428} PGMMAPPING;
429/** Pointer to structure for tracking GC Mappings. */
430typedef struct PGMMAPPING *PPGMMAPPING;
431
432
433/**
434 * Physical page access handler structure.
435 *
436 * This is used to keep track of physical address ranges
437 * which are being monitored in some kind of way.
438 */
439typedef struct PGMPHYSHANDLER
440{
441 AVLROGCPHYSNODECORE Core;
442 /** Access type. */
443 PGMPHYSHANDLERTYPE enmType;
444 /** Number of pages to update. */
445 uint32_t cPages;
446 /** Pointer to R3 callback function. */
447 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
448 /** User argument for R3 handlers. */
449 R3PTRTYPE(void *) pvUserR3;
450 /** Pointer to R0 callback function. */
451 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
452 /** User argument for R0 handlers. */
453 R0PTRTYPE(void *) pvUserR0;
454 /** Pointer to GC callback function. */
455 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
456 /** User argument for RC handlers. */
457 RCPTRTYPE(void *) pvUserRC;
458 /** Description / Name. For easing debugging. */
459 R3PTRTYPE(const char *) pszDesc;
460#ifdef VBOX_WITH_STATISTICS
461 /** Profiling of this handler. */
462 STAMPROFILE Stat;
463#endif
464} PGMPHYSHANDLER;
465/** Pointer to a physical page access handler structure. */
466typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
467
468
469/**
470 * Cache node for the physical addresses covered by a virtual handler.
471 */
472typedef struct PGMPHYS2VIRTHANDLER
473{
474 /** Core node for the tree based on physical ranges. */
475 AVLROGCPHYSNODECORE Core;
476 /** Offset from this struct to the PGMVIRTHANDLER structure. */
477 int32_t offVirtHandler;
478 /** Offset of the next alias relative to this one.
479 * Bit 0 is used for indicating whether we're in the tree.
480 * Bit 1 is used for indicating that we're the head node.
481 */
482 int32_t offNextAlias;
483} PGMPHYS2VIRTHANDLER;
484/** Pointer to a phys to virtual handler structure. */
485typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
486
487/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
488 * node is in the tree. */
489#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
490/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
491 * node is in the head of an alias chain.
492 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
493#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
494/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
495#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
496
497
498/**
499 * Virtual page access handler structure.
500 *
501 * This is used to keep track of virtual address ranges
502 * which are being monitored in some kind of way.
503 */
504typedef struct PGMVIRTHANDLER
505{
506 /** Core node for the tree based on virtual ranges. */
507 AVLROGCPTRNODECORE Core;
508 /** Size of the range (in bytes). */
509 RTGCPTR cb;
510 /** Number of cache pages. */
511 uint32_t cPages;
512 /** Access type. */
513 PGMVIRTHANDLERTYPE enmType;
514 /** Pointer to the RC callback function. */
515 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
516#if HC_ARCH_BITS == 64
517 RTRCPTR padding;
518#endif
519 /** Pointer to the R3 callback function for invalidation. */
520 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
521 /** Pointer to the R3 callback function. */
522 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
523 /** Description / Name. For easing debugging. */
524 R3PTRTYPE(const char *) pszDesc;
525#ifdef VBOX_WITH_STATISTICS
526 /** Profiling of this handler. */
527 STAMPROFILE Stat;
528#endif
529 /** Array of cached physical addresses for the monitored ranged. */
530 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
531} PGMVIRTHANDLER;
532/** Pointer to a virtual page access handler structure. */
533typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
534
535
536/**
537 * Page type.
538 *
539 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
540 * @remarks This is used in the saved state, so changes to it requires bumping
541 * the saved state version.
542 * @todo So, convert to \#defines!
543 */
544typedef enum PGMPAGETYPE
545{
546 /** The usual invalid zero entry. */
547 PGMPAGETYPE_INVALID = 0,
548 /** RAM page. (RWX) */
549 PGMPAGETYPE_RAM,
550 /** MMIO2 page. (RWX) */
551 PGMPAGETYPE_MMIO2,
552 /** MMIO2 page aliased over an MMIO page. (RWX)
553 * See PGMHandlerPhysicalPageAlias(). */
554 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
555 /** Shadowed ROM. (RWX) */
556 PGMPAGETYPE_ROM_SHADOW,
557 /** ROM page. (R-X) */
558 PGMPAGETYPE_ROM,
559 /** MMIO page. (---) */
560 PGMPAGETYPE_MMIO,
561 /** End of valid entries. */
562 PGMPAGETYPE_END
563} PGMPAGETYPE;
564AssertCompile(PGMPAGETYPE_END <= 7);
565
566/** @name Page type predicates.
567 * @{ */
568#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
569#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
570#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
571#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
572#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
573/** @} */
574
575
576/**
577 * A Physical Guest Page tracking structure.
578 *
579 * The format of this structure is complicated because we have to fit a lot
580 * of information into as few bits as possible. The format is also subject
581 * to change (there is one comming up soon). Which means that for we'll be
582 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
583 * accessess to the structure.
584 */
585typedef struct PGMPAGE
586{
587 /** The physical address and a whole lot of other stuff. All bits are used! */
588 RTHCPHYS HCPhysX;
589 /** The page state. */
590 uint32_t u2StateX : 2;
591 /** Flag indicating that a write monitored page was written to when set. */
592 uint32_t fWrittenToX : 1;
593 /** For later. */
594 uint32_t fSomethingElse : 1;
595 /** The Page ID.
596 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
597 * The HCPhysX will then be 100% static. */
598 uint32_t idPageX : 28;
599 /** The page type (PGMPAGETYPE). */
600 uint32_t u3Type : 3;
601 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
602 uint32_t u2HandlerPhysStateX : 2;
603 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
604 uint32_t u2HandlerVirtStateX : 2;
605 uint32_t u29B : 25;
606} PGMPAGE;
607AssertCompileSize(PGMPAGE, 16);
608/** Pointer to a physical guest page. */
609typedef PGMPAGE *PPGMPAGE;
610/** Pointer to a const physical guest page. */
611typedef const PGMPAGE *PCPGMPAGE;
612/** Pointer to a physical guest page pointer. */
613typedef PPGMPAGE *PPPGMPAGE;
614
615
616/**
617 * Clears the page structure.
618 * @param pPage Pointer to the physical guest page tracking structure.
619 */
620#define PGM_PAGE_CLEAR(pPage) \
621 do { \
622 (pPage)->HCPhysX = 0; \
623 (pPage)->u2StateX = 0; \
624 (pPage)->fWrittenToX = 0; \
625 (pPage)->fSomethingElse = 0; \
626 (pPage)->idPageX = 0; \
627 (pPage)->u3Type = 0; \
628 (pPage)->u29B = 0; \
629 } while (0)
630
631/**
632 * Initializes the page structure.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
636 do { \
637 (pPage)->HCPhysX = (_HCPhys); \
638 (pPage)->u2StateX = (_uState); \
639 (pPage)->fWrittenToX = 0; \
640 (pPage)->fSomethingElse = 0; \
641 (pPage)->idPageX = (_idPage); \
642 /*(pPage)->u3Type = (_uType); - later */ \
643 PGM_PAGE_SET_TYPE(pPage, _uType); \
644 (pPage)->u29B = 0; \
645 } while (0)
646
647/**
648 * Initializes the page structure of a ZERO page.
649 * @param pPage Pointer to the physical guest page tracking structure.
650 */
651#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
652 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
653/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
654# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
655 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
656
657
658/** @name The Page state, PGMPAGE::u2StateX.
659 * @{ */
660/** The zero page.
661 * This is a per-VM page that's never ever mapped writable. */
662#define PGM_PAGE_STATE_ZERO 0
663/** A allocated page.
664 * This is a per-VM page allocated from the page pool (or wherever
665 * we get MMIO2 pages from if the type is MMIO2).
666 */
667#define PGM_PAGE_STATE_ALLOCATED 1
668/** A allocated page that's being monitored for writes.
669 * The shadow page table mappings are read-only. When a write occurs, the
670 * fWrittenTo member is set, the page remapped as read-write and the state
671 * moved back to allocated. */
672#define PGM_PAGE_STATE_WRITE_MONITORED 2
673/** The page is shared, aka. copy-on-write.
674 * This is a page that's shared with other VMs. */
675#define PGM_PAGE_STATE_SHARED 3
676/** @} */
677
678
679/**
680 * Gets the page state.
681 * @returns page state (PGM_PAGE_STATE_*).
682 * @param pPage Pointer to the physical guest page tracking structure.
683 */
684#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
685
686/**
687 * Sets the page state.
688 * @param pPage Pointer to the physical guest page tracking structure.
689 * @param _uState The new page state.
690 */
691#define PGM_PAGE_SET_STATE(pPage, _uState) \
692 do { (pPage)->u2StateX = (_uState); } while (0)
693
694
695/**
696 * Gets the host physical address of the guest page.
697 * @returns host physical address (RTHCPHYS).
698 * @param pPage Pointer to the physical guest page tracking structure.
699 */
700#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
701
702/**
703 * Sets the host physical address of the guest page.
704 * @param pPage Pointer to the physical guest page tracking structure.
705 * @param _HCPhys The new host physical address.
706 */
707#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
708 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
709 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
710
711/**
712 * Get the Page ID.
713 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
714 * @param pPage Pointer to the physical guest page tracking structure.
715 */
716#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
717/* later:
718#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
719 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
720*/
721/**
722 * Sets the Page ID.
723 * @param pPage Pointer to the physical guest page tracking structure.
724 */
725#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
726/* later:
727#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
728 | ((_idPage) & 0xfff) \
729 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
730*/
731
732/**
733 * Get the Chunk ID.
734 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
735 * @param pPage Pointer to the physical guest page tracking structure.
736 */
737#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
738/* later:
739#if GMM_CHUNKID_SHIFT == 12
740# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
741#elif GMM_CHUNKID_SHIFT > 12
742# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
743#elif GMM_CHUNKID_SHIFT < 12
744# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
745 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
746#else
747# error "GMM_CHUNKID_SHIFT isn't defined or something."
748#endif
749*/
750
751/**
752 * Get the index of the page within the allocaiton chunk.
753 * @returns The page index.
754 * @param pPage Pointer to the physical guest page tracking structure.
755 */
756#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
757/* later:
758#if GMM_CHUNKID_SHIFT <= 12
759# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
760#else
761# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
762 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
763#endif
764*/
765
766
767/**
768 * Gets the page type.
769 * @returns The page type.
770 * @param pPage Pointer to the physical guest page tracking structure.
771 */
772#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
773
774/**
775 * Sets the page type.
776 * @param pPage Pointer to the physical guest page tracking structure.
777 * @param _enmType The new page type (PGMPAGETYPE).
778 */
779#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
780 do { (pPage)->u3Type = (_enmType); } while (0)
781
782/**
783 * Checks if the page is marked for MMIO.
784 * @returns true/false.
785 * @param pPage Pointer to the physical guest page tracking structure.
786 */
787#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
788
789/**
790 * Checks if the page is backed by the ZERO page.
791 * @returns true/false.
792 * @param pPage Pointer to the physical guest page tracking structure.
793 */
794#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
795
796/**
797 * Checks if the page is backed by a SHARED page.
798 * @returns true/false.
799 * @param pPage Pointer to the physical guest page tracking structure.
800 */
801#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
802
803
804/**
805 * Marks the paget as written to (for GMM change monitoring).
806 * @param pPage Pointer to the physical guest page tracking structure.
807 */
808#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
809
810/**
811 * Clears the written-to indicator.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 */
814#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
815
816/**
817 * Checks if the page was marked as written-to.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
822
823
824/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
825 *
826 * @remarks The values are assigned in order of priority, so we can calculate
827 * the correct state for a page with different handlers installed.
828 * @{ */
829/** No handler installed. */
830#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
831/** Monitoring is temporarily disabled. */
832#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
833/** Write access is monitored. */
834#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
835/** All access is monitored. */
836#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
837/** @} */
838
839/**
840 * Gets the physical access handler state of a page.
841 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
842 * @param pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
845
846/**
847 * Sets the physical access handler state of a page.
848 * @param pPage Pointer to the physical guest page tracking structure.
849 * @param _uState The new state value.
850 */
851#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
852 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
853
854/**
855 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
856 * @returns true/false
857 * @param pPage Pointer to the physical guest page tracking structure.
858 */
859#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
860
861/**
862 * Checks if the page has any active physical access handlers.
863 * @returns true/false
864 * @param pPage Pointer to the physical guest page tracking structure.
865 */
866#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
867
868
869/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
870 *
871 * @remarks The values are assigned in order of priority, so we can calculate
872 * the correct state for a page with different handlers installed.
873 * @{ */
874/** No handler installed. */
875#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
876/* 1 is reserved so the lineup is identical with the physical ones. */
877/** Write access is monitored. */
878#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
879/** All access is monitored. */
880#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
881/** @} */
882
883/**
884 * Gets the virtual access handler state of a page.
885 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
886 * @param pPage Pointer to the physical guest page tracking structure.
887 */
888#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
889
890/**
891 * Sets the virtual access handler state of a page.
892 * @param pPage Pointer to the physical guest page tracking structure.
893 * @param _uState The new state value.
894 */
895#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
896 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
897
898/**
899 * Checks if the page has any virtual access handlers.
900 * @returns true/false
901 * @param pPage Pointer to the physical guest page tracking structure.
902 */
903#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
904
905/**
906 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
907 * virtual handlers.
908 * @returns true/false
909 * @param pPage Pointer to the physical guest page tracking structure.
910 */
911#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
912
913
914
915/**
916 * Checks if the page has any access handlers, including temporarily disabled ones.
917 * @returns true/false
918 * @param pPage Pointer to the physical guest page tracking structure.
919 */
920#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
921 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
922 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
923
924/**
925 * Checks if the page has any active access handlers.
926 * @returns true/false
927 * @param pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
930 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
931 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
932
933/**
934 * Checks if the page has any active access handlers catching all accesses.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
939 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
940 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
941
942
943
944
945/** @def PGM_PAGE_GET_TRACKING
946 * Gets the packed shadow page pool tracking data associated with a guest page.
947 * @returns uint16_t containing the data.
948 * @param pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_GET_TRACKING(pPage) \
951 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
952
953/** @def PGM_PAGE_SET_TRACKING
954 * Sets the packed shadow page pool tracking data associated with a guest page.
955 * @param pPage Pointer to the physical guest page tracking structure.
956 * @param u16TrackingData The tracking data to store.
957 */
958#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
959 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
960
961/** @def PGM_PAGE_GET_TD_CREFS
962 * Gets the @a cRefs tracking data member.
963 * @returns cRefs.
964 * @param pPage Pointer to the physical guest page tracking structure.
965 */
966#define PGM_PAGE_GET_TD_CREFS(pPage) \
967 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
968
969#define PGM_PAGE_GET_TD_IDX(pPage) \
970 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
971
972/**
973 * Ram range for GC Phys to HC Phys conversion.
974 *
975 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
976 * conversions too, but we'll let MM handle that for now.
977 *
978 * This structure is used by linked lists in both GC and HC.
979 */
980typedef struct PGMRAMRANGE
981{
982 /** Start of the range. Page aligned. */
983 RTGCPHYS GCPhys;
984 /** Size of the range. (Page aligned of course). */
985 RTGCPHYS cb;
986 /** Pointer to the next RAM range - for R3. */
987 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
988 /** Pointer to the next RAM range - for R0. */
989 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
990 /** Pointer to the next RAM range - for RC. */
991 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
992 /** PGM_RAM_RANGE_FLAGS_* flags. */
993 uint32_t fFlags;
994 /** Last address in the range (inclusive). Page aligned (-1). */
995 RTGCPHYS GCPhysLast;
996 /** Start of the HC mapping of the range. This is only used for MMIO2. */
997 R3PTRTYPE(void *) pvR3;
998 /** The range description. */
999 R3PTRTYPE(const char *) pszDesc;
1000 /** Pointer to self - R0 pointer. */
1001 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1002 /** Pointer to self - RC pointer. */
1003 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1004 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1005 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1006 /** Array of physical guest page tracking structures. */
1007 PGMPAGE aPages[1];
1008} PGMRAMRANGE;
1009/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1010typedef PGMRAMRANGE *PPGMRAMRANGE;
1011
1012/** @name PGMRAMRANGE::fFlags
1013 * @{ */
1014/** The RAM range is floating around as an independent guest mapping. */
1015#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1016/** @} */
1017
1018
1019/**
1020 * Per page tracking structure for ROM image.
1021 *
1022 * A ROM image may have a shadow page, in which case we may have
1023 * two pages backing it. This structure contains the PGMPAGE for
1024 * both while PGMRAMRANGE have a copy of the active one. It is
1025 * important that these aren't out of sync in any regard other
1026 * than page pool tracking data.
1027 */
1028typedef struct PGMROMPAGE
1029{
1030 /** The page structure for the virgin ROM page. */
1031 PGMPAGE Virgin;
1032 /** The page structure for the shadow RAM page. */
1033 PGMPAGE Shadow;
1034 /** The current protection setting. */
1035 PGMROMPROT enmProt;
1036 /** Pad the structure size to a multiple of 8. */
1037 uint32_t u32Padding;
1038} PGMROMPAGE;
1039/** Pointer to a ROM page tracking structure. */
1040typedef PGMROMPAGE *PPGMROMPAGE;
1041
1042
1043/**
1044 * A registered ROM image.
1045 *
1046 * This is needed to keep track of ROM image since they generally
1047 * intrude into a PGMRAMRANGE. It also keeps track of additional
1048 * info like the two page sets (read-only virgin and read-write shadow),
1049 * the current state of each page.
1050 *
1051 * Because access handlers cannot easily be executed in a different
1052 * context, the ROM ranges needs to be accessible and in all contexts.
1053 */
1054typedef struct PGMROMRANGE
1055{
1056 /** Pointer to the next range - R3. */
1057 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1058 /** Pointer to the next range - R0. */
1059 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1060 /** Pointer to the next range - RC. */
1061 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1062 /** Pointer alignment */
1063 RTRCPTR GCPtrAlignment;
1064 /** Address of the range. */
1065 RTGCPHYS GCPhys;
1066 /** Address of the last byte in the range. */
1067 RTGCPHYS GCPhysLast;
1068 /** Size of the range. */
1069 RTGCPHYS cb;
1070 /** The flags (PGMPHYS_ROM_FLAG_*). */
1071 uint32_t fFlags;
1072 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1073 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1074 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1075 * This is used for strictness checks. */
1076 R3PTRTYPE(const void *) pvOriginal;
1077 /** The ROM description. */
1078 R3PTRTYPE(const char *) pszDesc;
1079 /** The per page tracking structures. */
1080 PGMROMPAGE aPages[1];
1081} PGMROMRANGE;
1082/** Pointer to a ROM range. */
1083typedef PGMROMRANGE *PPGMROMRANGE;
1084
1085
1086/**
1087 * A registered MMIO2 (= Device RAM) range.
1088 *
1089 * There are a few reason why we need to keep track of these
1090 * registrations. One of them is the deregistration & cleanup
1091 * stuff, while another is that the PGMRAMRANGE associated with
1092 * such a region may have to be removed from the ram range list.
1093 *
1094 * Overlapping with a RAM range has to be 100% or none at all. The
1095 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1096 * meditation will be raised if a partial overlap or an overlap of
1097 * ROM pages is encountered. On an overlap we will free all the
1098 * existing RAM pages and put in the ram range pages instead.
1099 */
1100typedef struct PGMMMIO2RANGE
1101{
1102 /** The owner of the range. (a device) */
1103 PPDMDEVINSR3 pDevInsR3;
1104 /** Pointer to the ring-3 mapping of the allocation. */
1105 RTR3PTR pvR3;
1106 /** Pointer to the next range - R3. */
1107 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1108 /** Whether it's mapped or not. */
1109 bool fMapped;
1110 /** Whether it's overlapping or not. */
1111 bool fOverlapping;
1112 /** The PCI region number.
1113 * @remarks This ASSUMES that nobody will ever really need to have multiple
1114 * PCI devices with matching MMIO region numbers on a single device. */
1115 uint8_t iRegion;
1116 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1117 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1118 /** The associated RAM range. */
1119 PGMRAMRANGE RamRange;
1120} PGMMMIO2RANGE;
1121/** Pointer to a MMIO2 range. */
1122typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1123
1124
1125
1126
1127/**
1128 * PGMPhysRead/Write cache entry
1129 */
1130typedef struct PGMPHYSCACHEENTRY
1131{
1132 /** R3 pointer to physical page. */
1133 R3PTRTYPE(uint8_t *) pbR3;
1134 /** GC Physical address for cache entry */
1135 RTGCPHYS GCPhys;
1136#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1137 RTGCPHYS u32Padding0; /**< alignment padding. */
1138#endif
1139} PGMPHYSCACHEENTRY;
1140
1141/**
1142 * PGMPhysRead/Write cache to reduce REM memory access overhead
1143 */
1144typedef struct PGMPHYSCACHE
1145{
1146 /** Bitmap of valid cache entries */
1147 uint64_t aEntries;
1148 /** Cache entries */
1149 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1150} PGMPHYSCACHE;
1151
1152
1153/** Pointer to an allocation chunk ring-3 mapping. */
1154typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1155/** Pointer to an allocation chunk ring-3 mapping pointer. */
1156typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1157
1158/**
1159 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1160 *
1161 * The primary tree (Core) uses the chunk id as key.
1162 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1163 */
1164typedef struct PGMCHUNKR3MAP
1165{
1166 /** The key is the chunk id. */
1167 AVLU32NODECORE Core;
1168 /** The key is the ageing sequence number. */
1169 AVLLU32NODECORE AgeCore;
1170 /** The current age thingy. */
1171 uint32_t iAge;
1172 /** The current reference count. */
1173 uint32_t volatile cRefs;
1174 /** The current permanent reference count. */
1175 uint32_t volatile cPermRefs;
1176 /** The mapping address. */
1177 void *pv;
1178} PGMCHUNKR3MAP;
1179
1180/**
1181 * Allocation chunk ring-3 mapping TLB entry.
1182 */
1183typedef struct PGMCHUNKR3MAPTLBE
1184{
1185 /** The chunk id. */
1186 uint32_t volatile idChunk;
1187#if HC_ARCH_BITS == 64
1188 uint32_t u32Padding; /**< alignment padding. */
1189#endif
1190 /** The chunk map. */
1191#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1192 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1193#else
1194 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1195#endif
1196} PGMCHUNKR3MAPTLBE;
1197/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1198typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1199
1200/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1201 * @remark Must be a power of two value. */
1202#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1203
1204/**
1205 * Allocation chunk ring-3 mapping TLB.
1206 *
1207 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1208 * At first glance this might look kinda odd since AVL trees are
1209 * supposed to give the most optimial lookup times of all trees
1210 * due to their balancing. However, take a tree with 1023 nodes
1211 * in it, that's 10 levels, meaning that most searches has to go
1212 * down 9 levels before they find what they want. This isn't fast
1213 * compared to a TLB hit. There is the factor of cache misses,
1214 * and of course the problem with trees and branch prediction.
1215 * This is why we use TLBs in front of most of the trees.
1216 *
1217 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1218 * difficult when we switch to the new inlined AVL trees (from kStuff).
1219 */
1220typedef struct PGMCHUNKR3MAPTLB
1221{
1222 /** The TLB entries. */
1223 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1224} PGMCHUNKR3MAPTLB;
1225
1226/**
1227 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1228 * @returns Chunk TLB index.
1229 * @param idChunk The Chunk ID.
1230 */
1231#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1232
1233
1234/**
1235 * Ring-3 guest page mapping TLB entry.
1236 * @remarks used in ring-0 as well at the moment.
1237 */
1238typedef struct PGMPAGER3MAPTLBE
1239{
1240 /** Address of the page. */
1241 RTGCPHYS volatile GCPhys;
1242 /** The guest page. */
1243#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1244 R3PTRTYPE(PPGMPAGE) volatile pPage;
1245#else
1246 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1247#endif
1248 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1249#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1251#else
1252 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1253#endif
1254 /** The address */
1255#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1256 R3PTRTYPE(void *) volatile pv;
1257#else
1258 R3R0PTRTYPE(void *) volatile pv;
1259#endif
1260#if HC_ARCH_BITS == 32
1261 uint32_t u32Padding; /**< alignment padding. */
1262#endif
1263} PGMPAGER3MAPTLBE;
1264/** Pointer to an entry in the HC physical TLB. */
1265typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1266
1267
1268/** The number of entries in the ring-3 guest page mapping TLB.
1269 * @remarks The value must be a power of two. */
1270#define PGM_PAGER3MAPTLB_ENTRIES 64
1271
1272/**
1273 * Ring-3 guest page mapping TLB.
1274 * @remarks used in ring-0 as well at the moment.
1275 */
1276typedef struct PGMPAGER3MAPTLB
1277{
1278 /** The TLB entries. */
1279 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1280} PGMPAGER3MAPTLB;
1281/** Pointer to the ring-3 guest page mapping TLB. */
1282typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1283
1284/**
1285 * Calculates the index of the TLB entry for the specified guest page.
1286 * @returns Physical TLB index.
1287 * @param GCPhys The guest physical address.
1288 */
1289#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1290
1291
1292/**
1293 * Mapping cache usage set entry.
1294 *
1295 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1296 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1297 * cache. If it's extended to include ring-3, well, then something will
1298 * have be changed here...
1299 */
1300typedef struct PGMMAPSETENTRY
1301{
1302 /** The mapping cache index. */
1303 uint16_t iPage;
1304 /** The number of references.
1305 * The max is UINT16_MAX - 1. */
1306 uint16_t cRefs;
1307 /** Pointer to the page. */
1308 RTR0PTR pvPage;
1309 /** The physical address for this entry. */
1310 RTHCPHYS HCPhys;
1311} PGMMAPSETENTRY;
1312/** Pointer to a mapping cache usage set entry. */
1313typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1314
1315/**
1316 * Mapping cache usage set.
1317 *
1318 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1319 * done during exits / traps. The set is
1320 */
1321typedef struct PGMMAPSET
1322{
1323 /** The number of occupied entries.
1324 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1325 * dynamic mappings. */
1326 uint32_t cEntries;
1327 /** The start of the current subset.
1328 * This is UINT32_MAX if no subset is currently open. */
1329 uint32_t iSubset;
1330 /** The index of the current CPU, only valid if the set is open. */
1331 int32_t iCpu;
1332 /** The entries. */
1333 PGMMAPSETENTRY aEntries[64];
1334 /** HCPhys -> iEntry fast lookup table.
1335 * Use PGMMAPSET_HASH for hashing.
1336 * The entries may or may not be valid, check against cEntries. */
1337 uint8_t aiHashTable[128];
1338} PGMMAPSET;
1339/** Pointer to the mapping cache set. */
1340typedef PGMMAPSET *PPGMMAPSET;
1341
1342/** PGMMAPSET::cEntries value for a closed set. */
1343#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1344
1345/** Hash function for aiHashTable. */
1346#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1347
1348/** The max fill size (strict builds). */
1349#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1350
1351
1352/** @name Context neutrual page mapper TLB.
1353 *
1354 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1355 * code is writting in a kind of context neutrual way. Time will show whether
1356 * this actually makes sense or not...
1357 *
1358 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1359 * context ends up using a global mapping cache on some platforms
1360 * (darwin).
1361 *
1362 * @{ */
1363/** @typedef PPGMPAGEMAPTLB
1364 * The page mapper TLB pointer type for the current context. */
1365/** @typedef PPGMPAGEMAPTLB
1366 * The page mapper TLB entry pointer type for the current context. */
1367/** @typedef PPGMPAGEMAPTLB
1368 * The page mapper TLB entry pointer pointer type for the current context. */
1369/** @def PGM_PAGEMAPTLB_ENTRIES
1370 * The number of TLB entries in the page mapper TLB for the current context. */
1371/** @def PGM_PAGEMAPTLB_IDX
1372 * Calculate the TLB index for a guest physical address.
1373 * @returns The TLB index.
1374 * @param GCPhys The guest physical address. */
1375/** @typedef PPGMPAGEMAP
1376 * Pointer to a page mapper unit for current context. */
1377/** @typedef PPPGMPAGEMAP
1378 * Pointer to a page mapper unit pointer for current context. */
1379#ifdef IN_RC
1380// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1381// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1382// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1383# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1384# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1385 typedef void * PPGMPAGEMAP;
1386 typedef void ** PPPGMPAGEMAP;
1387//#elif IN_RING0
1388// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1389// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1390// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1391//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1392//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1393// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1394// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1395#else
1396 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1397 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1398 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1399# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1400# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1401 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1402 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1403#endif
1404/** @} */
1405
1406
1407/** @name PGM Pool Indexes.
1408 * Aka. the unique shadow page identifier.
1409 * @{ */
1410/** NIL page pool IDX. */
1411#define NIL_PGMPOOL_IDX 0
1412/** The first normal index. */
1413#define PGMPOOL_IDX_FIRST_SPECIAL 1
1414/** Page directory (32-bit root). */
1415#define PGMPOOL_IDX_PD 1
1416/** Page Directory Pointer Table (PAE root). */
1417#define PGMPOOL_IDX_PDPT 2
1418/** AMD64 CR3 level index.*/
1419#define PGMPOOL_IDX_AMD64_CR3 3
1420/** Nested paging root.*/
1421#define PGMPOOL_IDX_NESTED_ROOT 4
1422/** The first normal index. */
1423#define PGMPOOL_IDX_FIRST 5
1424/** The last valid index. (inclusive, 14 bits) */
1425#define PGMPOOL_IDX_LAST 0x3fff
1426/** @} */
1427
1428/** The NIL index for the parent chain. */
1429#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1430
1431/**
1432 * Node in the chain linking a shadowed page to it's parent (user).
1433 */
1434#pragma pack(1)
1435typedef struct PGMPOOLUSER
1436{
1437 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1438 uint16_t iNext;
1439 /** The user page index. */
1440 uint16_t iUser;
1441 /** Index into the user table. */
1442 uint32_t iUserTable;
1443} PGMPOOLUSER, *PPGMPOOLUSER;
1444typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1445#pragma pack()
1446
1447
1448/** The NIL index for the phys ext chain. */
1449#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1450
1451/**
1452 * Node in the chain of physical cross reference extents.
1453 * @todo Calling this an 'extent' is not quite right, find a better name.
1454 */
1455#pragma pack(1)
1456typedef struct PGMPOOLPHYSEXT
1457{
1458 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1459 uint16_t iNext;
1460 /** The user page index. */
1461 uint16_t aidx[3];
1462} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1463typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1464#pragma pack()
1465
1466
1467/**
1468 * The kind of page that's being shadowed.
1469 */
1470typedef enum PGMPOOLKIND
1471{
1472 /** The virtual invalid 0 entry. */
1473 PGMPOOLKIND_INVALID = 0,
1474 /** The entry is free (=unused). */
1475 PGMPOOLKIND_FREE,
1476
1477 /** Shw: 32-bit page table; Gst: no paging */
1478 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1479 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1480 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1481 /** Shw: 32-bit page table; Gst: 4MB page. */
1482 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1483 /** Shw: PAE page table; Gst: no paging */
1484 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1485 /** Shw: PAE page table; Gst: 32-bit page table. */
1486 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1487 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1488 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1489 /** Shw: PAE page table; Gst: PAE page table. */
1490 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1491 /** Shw: PAE page table; Gst: 2MB page. */
1492 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1493
1494 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1495 PGMPOOLKIND_32BIT_PD,
1496 /** Shw: 32-bit page directory. Gst: no paging. */
1497 PGMPOOLKIND_32BIT_PD_PHYS,
1498 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1499 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1500 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1501 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1502 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1503 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1504 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1505 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1506 /** Shw: PAE page directory; Gst: PAE page directory. */
1507 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1508 /** Shw: PAE page directory; Gst: no paging. */
1509 PGMPOOLKIND_PAE_PD_PHYS,
1510
1511 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1512 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1513 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1514 PGMPOOLKIND_PAE_PDPT,
1515 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1516 PGMPOOLKIND_PAE_PDPT_PHYS,
1517
1518 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1519 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1520 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1521 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1522 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1523 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1524 /** Shw: 64-bit page directory table; Gst: no paging */
1525 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1526
1527 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1528 PGMPOOLKIND_64BIT_PML4,
1529
1530 /** Shw: EPT page directory pointer table; Gst: no paging */
1531 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1532 /** Shw: EPT page directory table; Gst: no paging */
1533 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1534 /** Shw: EPT page table; Gst: no paging */
1535 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1536
1537 /** Shw: Root Nested paging table. */
1538 PGMPOOLKIND_ROOT_NESTED,
1539
1540 /** The last valid entry. */
1541 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1542} PGMPOOLKIND;
1543
1544
1545/**
1546 * The tracking data for a page in the pool.
1547 */
1548typedef struct PGMPOOLPAGE
1549{
1550 /** AVL node code with the (R3) physical address of this page. */
1551 AVLOHCPHYSNODECORE Core;
1552 /** Pointer to the R3 mapping of the page. */
1553#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1554 R3PTRTYPE(void *) pvPageR3;
1555#else
1556 R3R0PTRTYPE(void *) pvPageR3;
1557#endif
1558 /** The guest physical address. */
1559#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1560 uint32_t Alignment0;
1561#endif
1562 RTGCPHYS GCPhys;
1563 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1564 uint8_t enmKind;
1565 uint8_t bPadding;
1566 /** The index of this page. */
1567 uint16_t idx;
1568 /** The next entry in the list this page currently resides in.
1569 * It's either in the free list or in the GCPhys hash. */
1570 uint16_t iNext;
1571#ifdef PGMPOOL_WITH_USER_TRACKING
1572 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1573 uint16_t iUserHead;
1574 /** The number of present entries. */
1575 uint16_t cPresent;
1576 /** The first entry in the table which is present. */
1577 uint16_t iFirstPresent;
1578#endif
1579#ifdef PGMPOOL_WITH_MONITORING
1580 /** The number of modifications to the monitored page. */
1581 uint16_t cModifications;
1582 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1583 uint16_t iModifiedNext;
1584 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1585 uint16_t iModifiedPrev;
1586 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1587 uint16_t iMonitoredNext;
1588 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1589 uint16_t iMonitoredPrev;
1590#endif
1591#ifdef PGMPOOL_WITH_CACHE
1592 /** The next page in the age list. */
1593 uint16_t iAgeNext;
1594 /** The previous page in the age list. */
1595 uint16_t iAgePrev;
1596#endif /* PGMPOOL_WITH_CACHE */
1597 /** Used to indicate that the page is zeroed. */
1598 bool fZeroed;
1599 /** Used to indicate that a PT has non-global entries. */
1600 bool fSeenNonGlobal;
1601 /** Used to indicate that we're monitoring writes to the guest page. */
1602 bool fMonitored;
1603 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1604 * (All pages are in the age list.) */
1605 bool fCached;
1606 /** This is used by the R3 access handlers when invoked by an async thread.
1607 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1608 bool volatile fReusedFlushPending;
1609 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1610 bool fLocked;
1611} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1612/** Pointer to a const pool page. */
1613typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1614
1615
1616#ifdef PGMPOOL_WITH_CACHE
1617/** The hash table size. */
1618# define PGMPOOL_HASH_SIZE 0x40
1619/** The hash function. */
1620# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1621#endif
1622
1623
1624/**
1625 * The shadow page pool instance data.
1626 *
1627 * It's all one big allocation made at init time, except for the
1628 * pages that is. The user nodes follows immediatly after the
1629 * page structures.
1630 */
1631typedef struct PGMPOOL
1632{
1633 /** The VM handle - R3 Ptr. */
1634 PVMR3 pVMR3;
1635 /** The VM handle - R0 Ptr. */
1636 PVMR0 pVMR0;
1637 /** The VM handle - RC Ptr. */
1638 PVMRC pVMRC;
1639 /** The max pool size. This includes the special IDs. */
1640 uint16_t cMaxPages;
1641 /** The current pool size. */
1642 uint16_t cCurPages;
1643 /** The head of the free page list. */
1644 uint16_t iFreeHead;
1645 /* Padding. */
1646 uint16_t u16Padding;
1647#ifdef PGMPOOL_WITH_USER_TRACKING
1648 /** Head of the chain of free user nodes. */
1649 uint16_t iUserFreeHead;
1650 /** The number of user nodes we've allocated. */
1651 uint16_t cMaxUsers;
1652 /** The number of present page table entries in the entire pool. */
1653 uint32_t cPresent;
1654 /** Pointer to the array of user nodes - RC pointer. */
1655 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1656 /** Pointer to the array of user nodes - R3 pointer. */
1657 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1658 /** Pointer to the array of user nodes - R0 pointer. */
1659 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1660#endif /* PGMPOOL_WITH_USER_TRACKING */
1661#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1662 /** Head of the chain of free phys ext nodes. */
1663 uint16_t iPhysExtFreeHead;
1664 /** The number of user nodes we've allocated. */
1665 uint16_t cMaxPhysExts;
1666 /** Pointer to the array of physical xref extent - RC pointer. */
1667 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1668 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1669 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1670 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1671 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1672#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1673#ifdef PGMPOOL_WITH_CACHE
1674 /** Hash table for GCPhys addresses. */
1675 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1676 /** The head of the age list. */
1677 uint16_t iAgeHead;
1678 /** The tail of the age list. */
1679 uint16_t iAgeTail;
1680 /** Set if the cache is enabled. */
1681 bool fCacheEnabled;
1682#endif /* PGMPOOL_WITH_CACHE */
1683#ifdef PGMPOOL_WITH_MONITORING
1684 /** Head of the list of modified pages. */
1685 uint16_t iModifiedHead;
1686 /** The current number of modified pages. */
1687 uint16_t cModifiedPages;
1688 /** Access handler, RC. */
1689 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1690 /** Access handler, R0. */
1691 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1692 /** Access handler, R3. */
1693 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1694 /** The access handler description (HC ptr). */
1695 R3PTRTYPE(const char *) pszAccessHandler;
1696#endif /* PGMPOOL_WITH_MONITORING */
1697 /** The number of pages currently in use. */
1698 uint16_t cUsedPages;
1699#ifdef VBOX_WITH_STATISTICS
1700 /** The high wather mark for cUsedPages. */
1701 uint16_t cUsedPagesHigh;
1702 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1703 /** Profiling pgmPoolAlloc(). */
1704 STAMPROFILEADV StatAlloc;
1705 /** Profiling pgmPoolClearAll(). */
1706 STAMPROFILE StatClearAll;
1707 /** Profiling pgmPoolFlushAllInt(). */
1708 STAMPROFILE StatFlushAllInt;
1709 /** Profiling pgmPoolFlushPage(). */
1710 STAMPROFILE StatFlushPage;
1711 /** Profiling pgmPoolFree(). */
1712 STAMPROFILE StatFree;
1713 /** Profiling time spent zeroing pages. */
1714 STAMPROFILE StatZeroPage;
1715# ifdef PGMPOOL_WITH_USER_TRACKING
1716 /** Profiling of pgmPoolTrackDeref. */
1717 STAMPROFILE StatTrackDeref;
1718 /** Profiling pgmTrackFlushGCPhysPT. */
1719 STAMPROFILE StatTrackFlushGCPhysPT;
1720 /** Profiling pgmTrackFlushGCPhysPTs. */
1721 STAMPROFILE StatTrackFlushGCPhysPTs;
1722 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1723 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1724 /** Number of times we've been out of user records. */
1725 STAMCOUNTER StatTrackFreeUpOneUser;
1726# endif
1727# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1728 /** Profiling deref activity related tracking GC physical pages. */
1729 STAMPROFILE StatTrackDerefGCPhys;
1730 /** Number of linear searches for a HCPhys in the ram ranges. */
1731 STAMCOUNTER StatTrackLinearRamSearches;
1732 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1733 STAMCOUNTER StamTrackPhysExtAllocFailures;
1734# endif
1735# ifdef PGMPOOL_WITH_MONITORING
1736 /** Profiling the RC/R0 access handler. */
1737 STAMPROFILE StatMonitorRZ;
1738 /** Times we've failed interpreting the instruction. */
1739 STAMCOUNTER StatMonitorRZEmulateInstr;
1740 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1741 STAMPROFILE StatMonitorRZFlushPage;
1742 /** Times we've detected fork(). */
1743 STAMCOUNTER StatMonitorRZFork;
1744 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1745 STAMPROFILE StatMonitorRZHandled;
1746 /** Times we've failed interpreting a patch code instruction. */
1747 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1748 /** Times we've failed interpreting a patch code instruction during flushing. */
1749 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1750 /** The number of times we've seen rep prefixes we can't handle. */
1751 STAMCOUNTER StatMonitorRZRepPrefix;
1752 /** Profiling the REP STOSD cases we've handled. */
1753 STAMPROFILE StatMonitorRZRepStosd;
1754
1755 /** Profiling the R3 access handler. */
1756 STAMPROFILE StatMonitorR3;
1757 /** Times we've failed interpreting the instruction. */
1758 STAMCOUNTER StatMonitorR3EmulateInstr;
1759 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1760 STAMPROFILE StatMonitorR3FlushPage;
1761 /** Times we've detected fork(). */
1762 STAMCOUNTER StatMonitorR3Fork;
1763 /** Profiling the R3 access we've handled (except REP STOSD). */
1764 STAMPROFILE StatMonitorR3Handled;
1765 /** The number of times we've seen rep prefixes we can't handle. */
1766 STAMCOUNTER StatMonitorR3RepPrefix;
1767 /** Profiling the REP STOSD cases we've handled. */
1768 STAMPROFILE StatMonitorR3RepStosd;
1769 /** The number of times we're called in an async thread an need to flush. */
1770 STAMCOUNTER StatMonitorR3Async;
1771 /** The high wather mark for cModifiedPages. */
1772 uint16_t cModifiedPagesHigh;
1773 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1774# endif
1775# ifdef PGMPOOL_WITH_CACHE
1776 /** The number of cache hits. */
1777 STAMCOUNTER StatCacheHits;
1778 /** The number of cache misses. */
1779 STAMCOUNTER StatCacheMisses;
1780 /** The number of times we've got a conflict of 'kind' in the cache. */
1781 STAMCOUNTER StatCacheKindMismatches;
1782 /** Number of times we've been out of pages. */
1783 STAMCOUNTER StatCacheFreeUpOne;
1784 /** The number of cacheable allocations. */
1785 STAMCOUNTER StatCacheCacheable;
1786 /** The number of uncacheable allocations. */
1787 STAMCOUNTER StatCacheUncacheable;
1788# endif
1789#elif HC_ARCH_BITS == 64
1790 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1791#endif
1792 /** The AVL tree for looking up a page by its HC physical address. */
1793 AVLOHCPHYSTREE HCPhysTree;
1794 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1795 /** Array of pages. (cMaxPages in length)
1796 * The Id is the index into thist array.
1797 */
1798 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1799} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1800
1801
1802/** @def PGMPOOL_PAGE_2_PTR
1803 * Maps a pool page pool into the current context.
1804 *
1805 * @returns VBox status code.
1806 * @param pVM The VM handle.
1807 * @param pPage The pool page.
1808 *
1809 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1810 * small page window employeed by that function. Be careful.
1811 * @remark There is no need to assert on the result.
1812 */
1813#if defined(IN_RC)
1814# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1815#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1816# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1817#elif defined(VBOX_STRICT)
1818# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1819DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1820{
1821 Assert(pPage && pPage->pvPageR3);
1822 return pPage->pvPageR3;
1823}
1824#else
1825# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1826#endif
1827
1828/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1829 * Maps a pool page pool into the current context.
1830 *
1831 * @returns VBox status code.
1832 * @param pPGM Pointer to the PGM instance data.
1833 * @param pPage The pool page.
1834 *
1835 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1836 * small page window employeed by that function. Be careful.
1837 * @remark There is no need to assert on the result.
1838 */
1839#if defined(IN_RC)
1840# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1841#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1842# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1843#else
1844# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1845#endif
1846
1847
1848/** @name Per guest page tracking data.
1849 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1850 * is to use more bits for it and split it up later on. But for now we'll play
1851 * safe and change as little as possible.
1852 *
1853 * The 16-bit word has two parts:
1854 *
1855 * The first 14-bit forms the @a idx field. It is either the index of a page in
1856 * the shadow page pool, or and index into the extent list.
1857 *
1858 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1859 * shadow page pool references to the page. If cRefs equals
1860 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1861 * (misnomer) table and not the shadow page pool.
1862 *
1863 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1864 * the 16-bit word.
1865 *
1866 * @{ */
1867/** The shift count for getting to the cRefs part. */
1868#define PGMPOOL_TD_CREFS_SHIFT 14
1869/** The mask applied after shifting the tracking data down by
1870 * PGMPOOL_TD_CREFS_SHIFT. */
1871#define PGMPOOL_TD_CREFS_MASK 0x3
1872/** The cRef value used to indiciate that the idx is the head of a
1873 * physical cross reference list. */
1874#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1875/** The shift used to get idx. */
1876#define PGMPOOL_TD_IDX_SHIFT 0
1877/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1878#define PGMPOOL_TD_IDX_MASK 0x3fff
1879/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1880 * simply too many mappings of this page. */
1881#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1882
1883/** @def PGMPOOL_TD_MAKE
1884 * Makes a 16-bit tracking data word.
1885 *
1886 * @returns tracking data.
1887 * @param cRefs The @a cRefs field. Must be within bounds!
1888 * @param idx The @a idx field. Must also be within bounds! */
1889#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1890
1891/** @def PGMPOOL_TD_GET_CREFS
1892 * Get the @a cRefs field from a tracking data word.
1893 *
1894 * @returns The @a cRefs field
1895 * @param u16 The tracking data word. */
1896#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1897
1898/** @def PGMPOOL_TD_GET_IDX
1899 * Get the @a idx field from a tracking data word.
1900 *
1901 * @returns The @a idx field
1902 * @param u16 The tracking data word. */
1903#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1904/** @} */
1905
1906
1907/**
1908 * Trees are using self relative offsets as pointers.
1909 * So, all its data, including the root pointer, must be in the heap for HC and GC
1910 * to have the same layout.
1911 */
1912typedef struct PGMTREES
1913{
1914 /** Physical access handlers (AVL range+offsetptr tree). */
1915 AVLROGCPHYSTREE PhysHandlers;
1916 /** Virtual access handlers (AVL range + GC ptr tree). */
1917 AVLROGCPTRTREE VirtHandlers;
1918 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1919 AVLROGCPHYSTREE PhysToVirtHandlers;
1920 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1921 AVLROGCPTRTREE HyperVirtHandlers;
1922} PGMTREES;
1923/** Pointer to PGM trees. */
1924typedef PGMTREES *PPGMTREES;
1925
1926
1927/** @name Paging mode macros
1928 * @{ */
1929#ifdef IN_RC
1930# define PGM_CTX(a,b) a##RC##b
1931# define PGM_CTX_STR(a,b) a "GC" b
1932# define PGM_CTX_DECL(type) VMMRCDECL(type)
1933#else
1934# ifdef IN_RING3
1935# define PGM_CTX(a,b) a##R3##b
1936# define PGM_CTX_STR(a,b) a "R3" b
1937# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1938# else
1939# define PGM_CTX(a,b) a##R0##b
1940# define PGM_CTX_STR(a,b) a "R0" b
1941# define PGM_CTX_DECL(type) VMMDECL(type)
1942# endif
1943#endif
1944
1945#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1946#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1947#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1948#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1949#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1950#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1951#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1952#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1953#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1954#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1955#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1956#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1957#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1958#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1959#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1960#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1961#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1962
1963#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1964#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1965#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1966#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1967#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1968#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1969#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1970#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1971#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1972#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1973#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1974#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1975#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1976#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1977#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1978#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1979#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1980
1981/* Shw_Gst */
1982#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1983#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1984#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1985#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1986#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1987#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1988#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1989#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1990#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1991#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1992#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1993#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1994#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1995#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1996#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1997#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1998#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1999#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2000#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2001
2002#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2003#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2004#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2005#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2006#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2007#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2008#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2009#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2010#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2011#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2012#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2013#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2014#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2015#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2016#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2017#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2018#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2019#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2020#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2021#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2022#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2023#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2024#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2025#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2026#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2027#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2028#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2029#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2030#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2031#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2032#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2033#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2034#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2035#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2036#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2037#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2038#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2039
2040#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2041#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2042/** @} */
2043
2044/**
2045 * Data for each paging mode.
2046 */
2047typedef struct PGMMODEDATA
2048{
2049 /** The guest mode type. */
2050 uint32_t uGstType;
2051 /** The shadow mode type. */
2052 uint32_t uShwType;
2053
2054 /** @name Function pointers for Shadow paging.
2055 * @{
2056 */
2057 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2058 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2059 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2060 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2061
2062 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2063 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2064
2065 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2066 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2067 /** @} */
2068
2069 /** @name Function pointers for Guest paging.
2070 * @{
2071 */
2072 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2073 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2074 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2075 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2076 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2077 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2078 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2079 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2080 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2081 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2082 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2083 /** @} */
2084
2085 /** @name Function pointers for Both Shadow and Guest paging.
2086 * @{
2087 */
2088 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2089 /* no pfnR3BthTrap0eHandler */
2090 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2091 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2092 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2093 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2094 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2095#ifdef VBOX_STRICT
2096 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2097#endif
2098 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2099 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2100
2101 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2102 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2103 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2104 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2105 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2106 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2107#ifdef VBOX_STRICT
2108 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2109#endif
2110 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2111 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2112
2113 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2114 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2115 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2116 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2117 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2118 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2119#ifdef VBOX_STRICT
2120 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2121#endif
2122 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2123 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2124 /** @} */
2125} PGMMODEDATA, *PPGMMODEDATA;
2126
2127
2128
2129/**
2130 * Converts a PGM pointer into a VM pointer.
2131 * @returns Pointer to the VM structure the PGM is part of.
2132 * @param pPGM Pointer to PGM instance data.
2133 */
2134#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2135
2136/**
2137 * PGM Data (part of VM)
2138 */
2139typedef struct PGM
2140{
2141 /** Offset to the VM structure. */
2142 RTINT offVM;
2143 /** Offset of the PGMCPU structure relative to VMCPU. */
2144 int32_t offVCpu;
2145 /** @cfgm{PGM/RamPreAlloc, bool, false}
2146 * Whether to preallocate all the guest RAM or not. */
2147 bool fRamPreAlloc;
2148 /** Alignment padding. */
2149 bool afAlignment0[3];
2150
2151
2152 /*
2153 * This will be redefined at least two more times before we're done, I'm sure.
2154 * The current code is only to get on with the coding.
2155 * - 2004-06-10: initial version, bird.
2156 * - 2004-07-02: 1st time, bird.
2157 * - 2004-10-18: 2nd time, bird.
2158 * - 2005-07-xx: 3rd time, bird.
2159 */
2160
2161 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2162 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2163 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2164 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2165
2166 /** The host paging mode. (This is what SUPLib reports.) */
2167 SUPPAGINGMODE enmHostMode;
2168 /** The shadow paging mode. */
2169 PGMMODE enmShadowMode;
2170 /** The guest paging mode. */
2171 PGMMODE enmGuestMode;
2172
2173 /** The current physical address representing in the guest CR3 register. */
2174 RTGCPHYS GCPhysCR3;
2175 /** Pointer to the 5 page CR3 content mapping.
2176 * The first page is always the CR3 (in some form) while the 4 other pages
2177 * are used of the PDs in PAE mode. */
2178 RTGCPTR GCPtrCR3Mapping;
2179#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2180 uint32_t u32Alignment;
2181#endif
2182 /** @name 32-bit Guest Paging.
2183 * @{ */
2184 /** The guest's page directory, R3 pointer. */
2185 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2186#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2187 /** The guest's page directory, R0 pointer. */
2188 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2189#endif
2190 /** The guest's page directory, static RC mapping. */
2191 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2192 /** @} */
2193
2194 /** @name PAE Guest Paging.
2195 * @{ */
2196 /** The guest's page directory pointer table, static RC mapping. */
2197 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2198 /** The guest's page directory pointer table, R3 pointer. */
2199 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2200#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2201 /** The guest's page directory pointer table, R0 pointer. */
2202 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2203#endif
2204
2205 /** The guest's page directories, R3 pointers.
2206 * These are individual pointers and don't have to be adjecent.
2207 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2208 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2209 /** The guest's page directories, R0 pointers.
2210 * Same restrictions as apGstPaePDsR3. */
2211#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2212 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2213#endif
2214 /** The guest's page directories, static GC mapping.
2215 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2216 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2217 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2218 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2219 RTGCPHYS aGCPhysGstPaePDs[4];
2220 /** The physical addresses of the monitored guest page directories (PAE). */
2221 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2222 /** @} */
2223
2224 /** @name AMD64 Guest Paging.
2225 * @{ */
2226 /** The guest's page directory pointer table, R3 pointer. */
2227 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2228#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2229 /** The guest's page directory pointer table, R0 pointer. */
2230 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2231#endif
2232 /** @} */
2233
2234 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2235 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2236 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2237 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2238 /** Pointer to the page of the current active CR3 - RC Ptr. */
2239 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2240 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2241 uint32_t iShwUser;
2242 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2243 uint32_t iShwUserTable;
2244# if HC_ARCH_BITS == 64
2245 RTRCPTR alignment6; /**< structure size alignment. */
2246# endif
2247 /** @} */
2248
2249 /** @name Function pointers for Shadow paging.
2250 * @{
2251 */
2252 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2253 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2254 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2255 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2256
2257 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2258 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2259
2260 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2261 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2262
2263 /** @} */
2264
2265 /** @name Function pointers for Guest paging.
2266 * @{
2267 */
2268 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2269 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2270 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2271 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2272 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2273 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2274 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2275 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2276#if HC_ARCH_BITS == 64
2277 RTRCPTR alignment3; /**< structure size alignment. */
2278#endif
2279
2280 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2281 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2282 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2283 /** @} */
2284
2285 /** @name Function pointers for Both Shadow and Guest paging.
2286 * @{
2287 */
2288 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2289 /* no pfnR3BthTrap0eHandler */
2290 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2291 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2292 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2293 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2294 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2295 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2296 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2297 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2298
2299 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2300 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2301 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2302 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2303 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2304 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2305 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2306 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2307 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2308
2309 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2310 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2311 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2312 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2313 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2314 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2315 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2316 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2317 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2318#if HC_ARCH_BITS == 64
2319 RTRCPTR alignment2; /**< structure size alignment. */
2320#endif
2321 /** @} */
2322
2323 /** Pointer to SHW+GST mode data (function pointers).
2324 * The index into this table is made up from */
2325 R3PTRTYPE(PPGMMODEDATA) paModeData;
2326
2327 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2328 * This is sorted by physical address and contains no overlapping ranges. */
2329 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2330 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2331 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2332 /** RC pointer corresponding to PGM::pRamRangesR3. */
2333 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2334 RTRCPTR alignment4; /**< structure alignment. */
2335
2336 /** Pointer to the list of ROM ranges - for R3.
2337 * This is sorted by physical address and contains no overlapping ranges. */
2338 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2339 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2340 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2341 /** RC pointer corresponding to PGM::pRomRangesR3. */
2342 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2343 /** Alignment padding. */
2344 RTRCPTR GCPtrPadding2;
2345
2346 /** Pointer to the list of MMIO2 ranges - for R3.
2347 * Registration order. */
2348 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2349
2350 /** PGM offset based trees - R3 Ptr. */
2351 R3PTRTYPE(PPGMTREES) pTreesR3;
2352 /** PGM offset based trees - R0 Ptr. */
2353 R0PTRTYPE(PPGMTREES) pTreesR0;
2354 /** PGM offset based trees - RC Ptr. */
2355 RCPTRTYPE(PPGMTREES) pTreesRC;
2356
2357 /** Linked list of GC mappings - for RC.
2358 * The list is sorted ascending on address.
2359 */
2360 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2361 /** Linked list of GC mappings - for HC.
2362 * The list is sorted ascending on address.
2363 */
2364 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2365 /** Linked list of GC mappings - for R0.
2366 * The list is sorted ascending on address.
2367 */
2368 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2369
2370 /** Indicates that PGMR3FinalizeMappings has been called and that further
2371 * PGMR3MapIntermediate calls will be rejected. */
2372 bool fFinalizedMappings;
2373 /** If set no conflict checks are required. (boolean) */
2374 bool fMappingsFixed;
2375 /** If set, then no mappings are put into the shadow page table. (boolean) */
2376 bool fDisableMappings;
2377 /** Size of fixed mapping */
2378 uint32_t cbMappingFixed;
2379 /** Base address (GC) of fixed mapping */
2380 RTGCPTR GCPtrMappingFixed;
2381 /** The address of the previous RAM range mapping. */
2382 RTGCPTR GCPtrPrevRamRangeMapping;
2383
2384 /** @name Intermediate Context
2385 * @{ */
2386 /** Pointer to the intermediate page directory - Normal. */
2387 R3PTRTYPE(PX86PD) pInterPD;
2388 /** Pointer to the intermedate page tables - Normal.
2389 * There are two page tables, one for the identity mapping and one for
2390 * the host context mapping (of the core code). */
2391 R3PTRTYPE(PX86PT) apInterPTs[2];
2392 /** Pointer to the intermedate page tables - PAE. */
2393 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2394 /** Pointer to the intermedate page directory - PAE. */
2395 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2396 /** Pointer to the intermedate page directory - PAE. */
2397 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2398 /** Pointer to the intermedate page-map level 4 - AMD64. */
2399 R3PTRTYPE(PX86PML4) pInterPaePML4;
2400 /** Pointer to the intermedate page directory - AMD64. */
2401 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2402 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2403 RTHCPHYS HCPhysInterPD;
2404 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2405 RTHCPHYS HCPhysInterPaePDPT;
2406 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2407 RTHCPHYS HCPhysInterPaePML4;
2408 /** @} */
2409
2410 /** Base address of the dynamic page mapping area.
2411 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2412 */
2413 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2414 /** The index of the last entry used in the dynamic page mapping area. */
2415 RTUINT iDynPageMapLast;
2416 /** Cache containing the last entries in the dynamic page mapping area.
2417 * The cache size is covering half of the mapping area. */
2418 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2419 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2420
2421 /** The address of the ring-0 mapping cache if we're making use of it. */
2422 RTR0PTR pvR0DynMapUsed;
2423#if HC_ARCH_BITS == 32
2424 RTR0PTR R0PtrPadding0; /**< Alignment. */
2425#endif
2426
2427
2428 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2429 RTGCPHYS GCPhys4MBPSEMask;
2430
2431 /** A20 gate mask.
2432 * Our current approach to A20 emulation is to let REM do it and don't bother
2433 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2434 * But whould need arrise, we'll subject physical addresses to this mask. */
2435 RTGCPHYS GCPhysA20Mask;
2436 /** A20 gate state - boolean! */
2437 bool fA20Enabled;
2438
2439 /** What needs syncing (PGM_SYNC_*).
2440 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2441 * PGMFlushTLB, and PGMR3Load. */
2442 RTUINT fSyncFlags;
2443
2444 /** PGM critical section.
2445 * This protects the physical & virtual access handlers, ram ranges,
2446 * and the page flag updating (some of it anyway).
2447 */
2448 PDMCRITSECT CritSect;
2449
2450 /** Shadow Page Pool - R3 Ptr. */
2451 R3PTRTYPE(PPGMPOOL) pPoolR3;
2452 /** Shadow Page Pool - R0 Ptr. */
2453 R0PTRTYPE(PPGMPOOL) pPoolR0;
2454 /** Shadow Page Pool - RC Ptr. */
2455 RCPTRTYPE(PPGMPOOL) pPoolRC;
2456
2457 /** We're not in a state which permits writes to guest memory.
2458 * (Only used in strict builds.) */
2459 bool fNoMorePhysWrites;
2460
2461 /** Flush the cache on the next access. */
2462 bool fPhysCacheFlushPending;
2463/** @todo r=bird: Fix member names!*/
2464 /** PGMPhysRead cache */
2465 PGMPHYSCACHE pgmphysreadcache;
2466 /** PGMPhysWrite cache */
2467 PGMPHYSCACHE pgmphyswritecache;
2468
2469 /**
2470 * Data associated with managing the ring-3 mappings of the allocation chunks.
2471 */
2472 struct
2473 {
2474 /** The chunk tree, ordered by chunk id. */
2475#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2476 R3PTRTYPE(PAVLU32NODECORE) pTree;
2477#else
2478 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2479#endif
2480 /** The chunk mapping TLB. */
2481 PGMCHUNKR3MAPTLB Tlb;
2482 /** The number of mapped chunks. */
2483 uint32_t c;
2484 /** The maximum number of mapped chunks.
2485 * @cfgm PGM/MaxRing3Chunks */
2486 uint32_t cMax;
2487 /** The chunk age tree, ordered by ageing sequence number. */
2488 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2489 /** The current time. */
2490 uint32_t iNow;
2491 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2492 uint32_t AgeingCountdown;
2493 } ChunkR3Map;
2494
2495 /**
2496 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2497 */
2498 PGMPAGER3MAPTLB PhysTlbHC;
2499
2500 /** @name The zero page.
2501 * @{ */
2502 /** The host physical address of the zero page. */
2503 RTHCPHYS HCPhysZeroPg;
2504 /** The ring-3 mapping of the zero page. */
2505 RTR3PTR pvZeroPgR3;
2506 /** The ring-0 mapping of the zero page. */
2507 RTR0PTR pvZeroPgR0;
2508 /** The GC mapping of the zero page. */
2509 RTGCPTR pvZeroPgRC;
2510#if GC_ARCH_BITS != 32
2511 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2512#endif
2513 /** @}*/
2514
2515 /** The number of handy pages. */
2516 uint32_t cHandyPages;
2517 /**
2518 * Array of handy pages.
2519 *
2520 * This array is used in a two way communication between pgmPhysAllocPage
2521 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2522 * an intermediary.
2523 *
2524 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2525 * (The current size of 32 pages, means 128 KB of handy memory.)
2526 */
2527 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2528
2529 /** @name Error injection.
2530 * @{ */
2531 /** Inject handy page allocation errors pretending we're completely out of
2532 * memory. */
2533 bool volatile fErrInjHandyPages;
2534 /** Padding. */
2535 bool afReserved[7];
2536 /** @} */
2537
2538 /** @name Release Statistics
2539 * @{ */
2540 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2541 uint32_t cPrivatePages; /**< The number of private pages. */
2542 uint32_t cSharedPages; /**< The number of shared pages. */
2543 uint32_t cZeroPages; /**< The number of zero backed pages. */
2544 /** The number of times the guest has switched mode since last reset or statistics reset. */
2545 STAMCOUNTER cGuestModeChanges;
2546 /** The number of times we were forced to change the hypervisor region location. */
2547 STAMCOUNTER cRelocations;
2548 /** @} */
2549
2550#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2551 /** RC: Which statistic this \#PF should be attributed to. */
2552 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2553 RTRCPTR padding0;
2554 /** R0: Which statistic this \#PF should be attributed to. */
2555 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2556 RTR0PTR padding1;
2557
2558 /* Common */
2559# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2560 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2561 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2562 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2563 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2564 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2565 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2566# endif
2567 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2568 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2569
2570 /* R3 only: */
2571 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2572 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2573 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2574 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2575
2576 /* R0 only: */
2577 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2578 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2579 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2580 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2581 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2582 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2583 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2584 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2585 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2586 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2587 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2588 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2589 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2590 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2591 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2592 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2593 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2594 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2595 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2596 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2597 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2598 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2599 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2600 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2601 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2602 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2603
2604 /* RC only: */
2605 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2606 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2607 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2608 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2609
2610 /* RZ only: */
2611 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2612 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2613 STAMPROFILE StatRZTrap0eTimeSyncPT;
2614 STAMPROFILE StatRZTrap0eTimeMapping;
2615 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2616 STAMPROFILE StatRZTrap0eTimeHandlers;
2617 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2618 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2619 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2620 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2621 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2622 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2623 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2624 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2625 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2626 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2627 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2628 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2629 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2630 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2631 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2632 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2633 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2634 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2635 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2636 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2637 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2638 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2639 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2640 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2641 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2642 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2643 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2644 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2645 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2646 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2647 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2648 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2649 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2650 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2651 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2652 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2653 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2654 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2655 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2656 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2657 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2658 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2659 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2660
2661 /* HC - R3 and (maybe) R0: */
2662
2663 /* RZ & R3: */
2664 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2665 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2666 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2667 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2668 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2669 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2670 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2671 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2672 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2673 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2674 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2675 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2676 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2677 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2678 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2679 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2680 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2681 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2682 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2683 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2684 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2685 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2686 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2687 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2688 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2689 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2690 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2691 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2692 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2693 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2694 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2695 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2696 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2697 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2698 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2699 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2700 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2701 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2702 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2703 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2704 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2705 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2706 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2707 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2708 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2709 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2710 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2711/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2712 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2713 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2714 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2715 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2716 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2717 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2718
2719 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2720 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2721 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2722 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2723 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2724 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2725 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2726 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2727 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2728 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2729 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2730 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2731 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2732 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2733 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2734 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2735 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2736 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2737 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2738 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2739 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2740 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2741 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2742 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2743 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2744 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2745 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2746 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2747 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2748 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2749 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2750 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2751 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2752 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2753 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2754 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2755 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2756 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2757 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2758 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2759 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2760 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2761 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2762 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2763 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2764 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2765 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2766/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2767 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2768 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2769 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2770 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2771 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2772 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2773#endif /* VBOX_WITH_STATISTICS */
2774} PGM;
2775/** Pointer to the PGM instance data. */
2776typedef PGM *PPGM;
2777
2778
2779/**
2780 * PGMCPU Data (part of VMCPU).
2781 */
2782typedef struct PGMCPU
2783{
2784 /** Offset to the VMCPU structure. */
2785 RTINT offVMCPU;
2786 /** Automatically tracked physical memory mapping set.
2787 * Ring-0 and strict raw-mode builds. */
2788 PGMMAPSET AutoSet;
2789} PGMCPU;
2790/** Pointer to the per-cpu PGM data. */
2791typedef PGMCPU *PPGMCPU;
2792
2793
2794/** @name PGM::fSyncFlags Flags
2795 * @{
2796 */
2797/** Updates the virtual access handler state bit in PGMPAGE. */
2798#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2799/** Always sync CR3. */
2800#define PGM_SYNC_ALWAYS RT_BIT(1)
2801/** Check monitoring on next CR3 (re)load and invalidate page.
2802 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2803#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2804/** Check guest mapping in SyncCR3. */
2805#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2806/** Clear the page pool (a light weight flush). */
2807#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2808/** @} */
2809
2810
2811__BEGIN_DECLS
2812
2813int pgmLock(PVM pVM);
2814void pgmUnlock(PVM pVM);
2815
2816int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2817int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2818PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2819void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2820DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2821
2822void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2823bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2824void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2825int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2826DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2827#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2828void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2829#else
2830# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2831#endif
2832DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2833
2834
2835int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2836int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2837int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2838int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2839int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2840int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2841int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2842int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2843VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2844#ifdef IN_RING3
2845int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2846void pgmR3PhysRelinkRamRanges(PVM pVM);
2847int pgmR3PhysRamReset(PVM pVM);
2848int pgmR3PhysRomReset(PVM pVM);
2849
2850int pgmR3PoolInit(PVM pVM);
2851void pgmR3PoolRelocate(PVM pVM);
2852void pgmR3PoolReset(PVM pVM);
2853
2854#endif /* IN_RING3 */
2855#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2856int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2857#endif
2858int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2859PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2860void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2861void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2862int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2863void pgmPoolFlushAll(PVM pVM);
2864void pgmPoolClearAll(PVM pVM);
2865int pgmPoolSyncCR3(PVM pVM);
2866int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
2867void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2868void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2869int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2870PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2871void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2872void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2873uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2874void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2875#ifdef PGMPOOL_WITH_MONITORING
2876void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2877int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2878void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2879void pgmPoolMonitorModifiedClearAll(PVM pVM);
2880int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2881int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2882#endif
2883
2884void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2885void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
2886int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2887int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2888
2889int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2890#ifndef IN_RC
2891int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2892#endif
2893int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
2894
2895PX86PD pgmGstLazyMap32BitPD(PPGM pPGM);
2896PX86PDPT pgmGstLazyMapPaePDPT(PPGM pPGM);
2897PX86PDPAE pgmGstLazyMapPaePD(PPGM pPGM, uint32_t iPdpt);
2898PX86PML4 pgmGstLazyMapPml4(PPGM pPGM);
2899
2900__END_DECLS
2901
2902
2903/**
2904 * Gets the PGMRAMRANGE structure for a guest page.
2905 *
2906 * @returns Pointer to the RAM range on success.
2907 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2908 *
2909 * @param pPGM PGM handle.
2910 * @param GCPhys The GC physical address.
2911 */
2912DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2913{
2914 /*
2915 * Optimize for the first range.
2916 */
2917 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2918 RTGCPHYS off = GCPhys - pRam->GCPhys;
2919 if (RT_UNLIKELY(off >= pRam->cb))
2920 {
2921 do
2922 {
2923 pRam = pRam->CTX_SUFF(pNext);
2924 if (RT_UNLIKELY(!pRam))
2925 break;
2926 off = GCPhys - pRam->GCPhys;
2927 } while (off >= pRam->cb);
2928 }
2929 return pRam;
2930}
2931
2932
2933/**
2934 * Gets the PGMPAGE structure for a guest page.
2935 *
2936 * @returns Pointer to the page on success.
2937 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2938 *
2939 * @param pPGM PGM handle.
2940 * @param GCPhys The GC physical address.
2941 */
2942DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2943{
2944 /*
2945 * Optimize for the first range.
2946 */
2947 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2948 RTGCPHYS off = GCPhys - pRam->GCPhys;
2949 if (RT_UNLIKELY(off >= pRam->cb))
2950 {
2951 do
2952 {
2953 pRam = pRam->CTX_SUFF(pNext);
2954 if (RT_UNLIKELY(!pRam))
2955 return NULL;
2956 off = GCPhys - pRam->GCPhys;
2957 } while (off >= pRam->cb);
2958 }
2959 return &pRam->aPages[off >> PAGE_SHIFT];
2960}
2961
2962
2963/**
2964 * Gets the PGMPAGE structure for a guest page.
2965 *
2966 * Old Phys code: Will make sure the page is present.
2967 *
2968 * @returns VBox status code.
2969 * @retval VINF_SUCCESS and a valid *ppPage on success.
2970 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2971 *
2972 * @param pPGM PGM handle.
2973 * @param GCPhys The GC physical address.
2974 * @param ppPage Where to store the page poitner on success.
2975 */
2976DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2977{
2978 /*
2979 * Optimize for the first range.
2980 */
2981 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2982 RTGCPHYS off = GCPhys - pRam->GCPhys;
2983 if (RT_UNLIKELY(off >= pRam->cb))
2984 {
2985 do
2986 {
2987 pRam = pRam->CTX_SUFF(pNext);
2988 if (RT_UNLIKELY(!pRam))
2989 {
2990 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2991 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2992 }
2993 off = GCPhys - pRam->GCPhys;
2994 } while (off >= pRam->cb);
2995 }
2996 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2997 return VINF_SUCCESS;
2998}
2999
3000
3001
3002
3003/**
3004 * Gets the PGMPAGE structure for a guest page.
3005 *
3006 * Old Phys code: Will make sure the page is present.
3007 *
3008 * @returns VBox status code.
3009 * @retval VINF_SUCCESS and a valid *ppPage on success.
3010 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3011 *
3012 * @param pPGM PGM handle.
3013 * @param GCPhys The GC physical address.
3014 * @param ppPage Where to store the page poitner on success.
3015 * @param ppRamHint Where to read and store the ram list hint.
3016 * The caller initializes this to NULL before the call.
3017 */
3018DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3019{
3020 RTGCPHYS off;
3021 PPGMRAMRANGE pRam = *ppRamHint;
3022 if ( !pRam
3023 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3024 {
3025 pRam = pPGM->CTX_SUFF(pRamRanges);
3026 off = GCPhys - pRam->GCPhys;
3027 if (RT_UNLIKELY(off >= pRam->cb))
3028 {
3029 do
3030 {
3031 pRam = pRam->CTX_SUFF(pNext);
3032 if (RT_UNLIKELY(!pRam))
3033 {
3034 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3035 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3036 }
3037 off = GCPhys - pRam->GCPhys;
3038 } while (off >= pRam->cb);
3039 }
3040 *ppRamHint = pRam;
3041 }
3042 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3043 return VINF_SUCCESS;
3044}
3045
3046
3047/**
3048 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3049 *
3050 * @returns Pointer to the page on success.
3051 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3052 *
3053 * @param pPGM PGM handle.
3054 * @param GCPhys The GC physical address.
3055 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3056 */
3057DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3058{
3059 /*
3060 * Optimize for the first range.
3061 */
3062 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3063 RTGCPHYS off = GCPhys - pRam->GCPhys;
3064 if (RT_UNLIKELY(off >= pRam->cb))
3065 {
3066 do
3067 {
3068 pRam = pRam->CTX_SUFF(pNext);
3069 if (RT_UNLIKELY(!pRam))
3070 return NULL;
3071 off = GCPhys - pRam->GCPhys;
3072 } while (off >= pRam->cb);
3073 }
3074 *ppRam = pRam;
3075 return &pRam->aPages[off >> PAGE_SHIFT];
3076}
3077
3078
3079/**
3080 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3081 *
3082 * @returns Pointer to the page on success.
3083 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3084 *
3085 * @param pPGM PGM handle.
3086 * @param GCPhys The GC physical address.
3087 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3088 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3089 */
3090DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3091{
3092 /*
3093 * Optimize for the first range.
3094 */
3095 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3096 RTGCPHYS off = GCPhys - pRam->GCPhys;
3097 if (RT_UNLIKELY(off >= pRam->cb))
3098 {
3099 do
3100 {
3101 pRam = pRam->CTX_SUFF(pNext);
3102 if (RT_UNLIKELY(!pRam))
3103 {
3104 *ppRam = NULL; /* Shut up silly GCC warnings. */
3105 *ppPage = NULL; /* ditto */
3106 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3107 }
3108 off = GCPhys - pRam->GCPhys;
3109 } while (off >= pRam->cb);
3110 }
3111 *ppRam = pRam;
3112 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3113 return VINF_SUCCESS;
3114}
3115
3116
3117/**
3118 * Convert GC Phys to HC Phys.
3119 *
3120 * @returns VBox status.
3121 * @param pPGM PGM handle.
3122 * @param GCPhys The GC physical address.
3123 * @param pHCPhys Where to store the corresponding HC physical address.
3124 *
3125 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3126 * Avoid when writing new code!
3127 */
3128DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3129{
3130 PPGMPAGE pPage;
3131 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3132 if (RT_FAILURE(rc))
3133 return rc;
3134 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3135 return VINF_SUCCESS;
3136}
3137
3138#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3139
3140/**
3141 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3142 * optimizes access to pages already in the set.
3143 *
3144 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3145 * @param pPGM Pointer to the PVM instance data.
3146 * @param HCPhys The physical address of the page.
3147 * @param ppv Where to store the mapping address.
3148 */
3149DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3150{
3151 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3152 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3153 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3154 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3155
3156 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3157 unsigned iEntry = pSet->aiHashTable[iHash];
3158 if ( iEntry < pSet->cEntries
3159 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3160 {
3161 *ppv = pSet->aEntries[iEntry].pvPage;
3162 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3163 }
3164 else
3165 {
3166 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3167 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3168 }
3169
3170 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3171 return VINF_SUCCESS;
3172}
3173
3174
3175/**
3176 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3177 * access to pages already in the set.
3178 *
3179 * @returns See PGMDynMapGCPage.
3180 * @param pPGM Pointer to the PVM instance data.
3181 * @param HCPhys The physical address of the page.
3182 * @param ppv Where to store the mapping address.
3183 */
3184DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3185{
3186 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3187 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3188
3189 /*
3190 * Get the ram range.
3191 */
3192 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3193 RTGCPHYS off = GCPhys - pRam->GCPhys;
3194 if (RT_UNLIKELY(off >= pRam->cb
3195 /** @todo || page state stuff */))
3196 {
3197 /* This case is not counted into StatR0DynMapGCPageInl. */
3198 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3199 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3200 }
3201
3202 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3203 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3204
3205 /*
3206 * pgmR0DynMapHCPageInlined with out stats.
3207 */
3208 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3209 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3210 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3211
3212 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3213 unsigned iEntry = pSet->aiHashTable[iHash];
3214 if ( iEntry < pSet->cEntries
3215 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3216 {
3217 *ppv = pSet->aEntries[iEntry].pvPage;
3218 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3219 }
3220 else
3221 {
3222 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3223 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3224 }
3225
3226 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3227 return VINF_SUCCESS;
3228}
3229
3230#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3231#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3232
3233/**
3234 * Maps the page into current context (RC and maybe R0).
3235 *
3236 * @returns pointer to the mapping.
3237 * @param pVM Pointer to the PGM instance data.
3238 * @param pPage The page.
3239 */
3240DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3241{
3242 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3243 {
3244 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3245 void *pv;
3246# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3247 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3248# else
3249 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3250# endif
3251 return pv;
3252 }
3253 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3254}
3255
3256/**
3257 * Temporarily maps one host page specified by HC physical address, returning
3258 * pointer within the page.
3259 *
3260 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3261 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3262 *
3263 * @returns The address corresponding to HCPhys.
3264 * @param pPGM Pointer to the PVM instance data.
3265 * @param HCPhys HC Physical address of the page.
3266 */
3267DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3268{
3269 void *pv;
3270# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3271 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3272# else
3273 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3274# endif
3275 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3276 return pv;
3277}
3278
3279#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3280#ifndef IN_RC
3281
3282/**
3283 * Queries the Physical TLB entry for a physical guest page,
3284 * attemting to load the TLB entry if necessary.
3285 *
3286 * @returns VBox status code.
3287 * @retval VINF_SUCCESS on success
3288 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3289 *
3290 * @param pPGM The PGM instance handle.
3291 * @param GCPhys The address of the guest page.
3292 * @param ppTlbe Where to store the pointer to the TLB entry.
3293 */
3294DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3295{
3296 int rc;
3297 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3298 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3299 {
3300 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3301 rc = VINF_SUCCESS;
3302 }
3303 else
3304 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3305 *ppTlbe = pTlbe;
3306 return rc;
3307}
3308
3309
3310/**
3311 * Queries the Physical TLB entry for a physical guest page,
3312 * attemting to load the TLB entry if necessary.
3313 *
3314 * @returns VBox status code.
3315 * @retval VINF_SUCCESS on success
3316 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3317 *
3318 * @param pPGM The PGM instance handle.
3319 * @param pPage Pointer to the PGMPAGE structure corresponding to
3320 * GCPhys.
3321 * @param GCPhys The address of the guest page.
3322 * @param ppTlbe Where to store the pointer to the TLB entry.
3323 */
3324DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3325{
3326 int rc;
3327 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3328 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3329 {
3330 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3331 rc = VINF_SUCCESS;
3332 }
3333 else
3334 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3335 *ppTlbe = pTlbe;
3336 return rc;
3337}
3338
3339#endif /* !IN_RC */
3340
3341/**
3342 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3343 * Takes PSE-36 into account.
3344 *
3345 * @returns guest physical address
3346 * @param pPGM Pointer to the PGM instance data.
3347 * @param Pde Guest Pde
3348 */
3349DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3350{
3351 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3352 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3353
3354 return GCPhys & pPGM->GCPhys4MBPSEMask;
3355}
3356
3357
3358/**
3359 * Gets the page directory entry for the specified address (32-bit paging).
3360 *
3361 * @returns The page directory entry in question.
3362 * @param pPGM Pointer to the PGM instance data.
3363 * @param GCPtr The address.
3364 */
3365DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3366{
3367#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3368 PCX86PD pGuestPD = NULL;
3369 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3370 if (RT_FAILURE(rc))
3371 {
3372 X86PDE ZeroPde = {0};
3373 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3374 }
3375#else
3376 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3377# ifdef IN_RING3
3378 if (!pGuestPD)
3379 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3380# endif
3381#endif
3382 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3383}
3384
3385
3386/**
3387 * Gets the address of a specific page directory entry (32-bit paging).
3388 *
3389 * @returns Pointer the page directory entry in question.
3390 * @param pPGM Pointer to the PGM instance data.
3391 * @param GCPtr The address.
3392 */
3393DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3394{
3395#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3396 PX86PD pGuestPD = NULL;
3397 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3398 AssertRCReturn(rc, NULL);
3399#else
3400 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3401# ifdef IN_RING3
3402 if (!pGuestPD)
3403 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3404# endif
3405#endif
3406 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3407}
3408
3409
3410/**
3411 * Gets the address the guest page directory (32-bit paging).
3412 *
3413 * @returns Pointer the page directory entry in question.
3414 * @param pPGM Pointer to the PGM instance data.
3415 */
3416DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3417{
3418#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3419 PX86PD pGuestPD = NULL;
3420 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3421 AssertRCReturn(rc, NULL);
3422#else
3423 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3424# ifdef IN_RING3
3425 if (!pGuestPD)
3426 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3427# endif
3428#endif
3429 return pGuestPD;
3430}
3431
3432
3433/**
3434 * Gets the guest page directory pointer table.
3435 *
3436 * @returns Pointer to the page directory in question.
3437 * @returns NULL if the page directory is not present or on an invalid page.
3438 * @param pPGM Pointer to the PGM instance data.
3439 */
3440DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3441{
3442#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3443 PX86PDPT pGuestPDPT = NULL;
3444 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3445 AssertRCReturn(rc, NULL);
3446#else
3447 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3448# ifdef IN_RING3
3449 if (!pGuestPDPT)
3450 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3451# endif
3452#endif
3453 return pGuestPDPT;
3454}
3455
3456
3457/**
3458 * Gets the guest page directory pointer table entry for the specified address.
3459 *
3460 * @returns Pointer to the page directory in question.
3461 * @returns NULL if the page directory is not present or on an invalid page.
3462 * @param pPGM Pointer to the PGM instance data.
3463 * @param GCPtr The address.
3464 */
3465DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3466{
3467 AssertGCPtr32(GCPtr);
3468
3469#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3470 PX86PDPT pGuestPDPT = 0;
3471 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3472 AssertRCReturn(rc, 0);
3473#else
3474 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3475# ifdef IN_RING3
3476 if (!pGuestPDPT)
3477 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3478# endif
3479#endif
3480 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3481}
3482
3483
3484/**
3485 * Gets the page directory for the specified address.
3486 *
3487 * @returns Pointer to the page directory in question.
3488 * @returns NULL if the page directory is not present or on an invalid page.
3489 * @param pPGM Pointer to the PGM instance data.
3490 * @param GCPtr The address.
3491 */
3492DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3493{
3494 AssertGCPtr32(GCPtr);
3495
3496 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3497 AssertReturn(pGuestPDPT, NULL);
3498 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3499 if (pGuestPDPT->a[iPdpt].n.u1Present)
3500 {
3501#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3502 PX86PDPAE pGuestPD = NULL;
3503 int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3504 AssertRCReturn(rc, NULL);
3505#else
3506 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3507 if ( !pGuestPD
3508 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3509 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3510#endif
3511 return pGuestPD;
3512 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3513 }
3514 return NULL;
3515}
3516
3517
3518/**
3519 * Gets the page directory entry for the specified address.
3520 *
3521 * @returns Pointer to the page directory entry in question.
3522 * @returns NULL if the page directory is not present or on an invalid page.
3523 * @param pPGM Pointer to the PGM instance data.
3524 * @param GCPtr The address.
3525 */
3526DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3527{
3528 AssertGCPtr32(GCPtr);
3529
3530 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3531 AssertReturn(pGuestPDPT, NULL);
3532 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3533 if (pGuestPDPT->a[iPdpt].n.u1Present)
3534 {
3535 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3536#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3537 PX86PDPAE pGuestPD = NULL;
3538 int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3539 AssertRCReturn(rc, NULL);
3540#else
3541 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3542 if ( !pGuestPD
3543 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3544 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3545#endif
3546 return &pGuestPD->a[iPD];
3547 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3548 }
3549 return NULL;
3550}
3551
3552
3553/**
3554 * Gets the page directory entry for the specified address.
3555 *
3556 * @returns The page directory entry in question.
3557 * @returns A non-present entry if the page directory is not present or on an invalid page.
3558 * @param pPGM Pointer to the PGM instance data.
3559 * @param GCPtr The address.
3560 */
3561DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3562{
3563 AssertGCPtr32(GCPtr);
3564 X86PDEPAE ZeroPde = {0};
3565 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3566 if (RT_LIKELY(pGuestPDPT))
3567 {
3568 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3569 if (pGuestPDPT->a[iPdpt].n.u1Present)
3570 {
3571 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3572#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3573 PX86PDPAE pGuestPD = NULL;
3574 int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3575 AssertRCReturn(rc, ZeroPde);
3576#else
3577 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3578 if ( !pGuestPD
3579 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3580 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3581#endif
3582 return pGuestPD->a[iPD];
3583 }
3584 }
3585 return ZeroPde;
3586}
3587
3588
3589/**
3590 * Gets the page directory pointer table entry for the specified address
3591 * and returns the index into the page directory
3592 *
3593 * @returns Pointer to the page directory in question.
3594 * @returns NULL if the page directory is not present or on an invalid page.
3595 * @param pPGM Pointer to the PGM instance data.
3596 * @param GCPtr The address.
3597 * @param piPD Receives the index into the returned page directory
3598 * @param pPdpe Receives the page directory pointer entry. Optional.
3599 */
3600DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3601{
3602 AssertGCPtr32(GCPtr);
3603
3604 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3605 AssertReturn(pGuestPDPT, NULL);
3606 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3607 if (pPdpe)
3608 *pPdpe = pGuestPDPT->a[iPdpt];
3609 if (pGuestPDPT->a[iPdpt].n.u1Present)
3610 {
3611 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3612#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3613 PX86PDPAE pGuestPD = NULL;
3614 int rc = pgmR0DynMapGCPageInlined(pPGM, pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3615 AssertRCReturn(rc, NULL);
3616#else
3617 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3618 if ( !pGuestPD
3619 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3620 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3621#endif
3622 *piPD = iPD;
3623 return pGuestPD;
3624 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3625 }
3626 return NULL;
3627}
3628
3629#ifndef IN_RC
3630
3631/**
3632 * Gets the page map level-4 pointer for the guest.
3633 *
3634 * @returns Pointer to the PML4 page.
3635 * @param pPGM Pointer to the PGM instance data.
3636 */
3637DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3638{
3639#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3640 PX86PML4 pGuestPml4;
3641 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3642 AssertRCReturn(rc, NULL);
3643#else
3644 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3645# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3646 if (!pGuestPml4)
3647 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3648# endif
3649 Assert(pGuestPml4);
3650#endif
3651 return pGuestPml4;
3652}
3653
3654
3655/**
3656 * Gets the pointer to a page map level-4 entry.
3657 *
3658 * @returns Pointer to the PML4 entry.
3659 * @param pPGM Pointer to the PGM instance data.
3660 * @param iPml4 The index.
3661 */
3662DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3663{
3664#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3665 PX86PML4 pGuestPml4;
3666 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3667 AssertRCReturn(rc, NULL);
3668#else
3669 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3670# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3671 if (!pGuestPml4)
3672 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3673# endif
3674 Assert(pGuestPml4);
3675#endif
3676 return &pGuestPml4->a[iPml4];
3677}
3678
3679
3680/**
3681 * Gets a page map level-4 entry.
3682 *
3683 * @returns The PML4 entry.
3684 * @param pPGM Pointer to the PGM instance data.
3685 * @param iPml4 The index.
3686 */
3687DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3688{
3689#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3690 PX86PML4 pGuestPml4;
3691 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3692 if (RT_FAILURE(rc))
3693 {
3694 X86PML4E ZeroPml4e = {0};
3695 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3696 }
3697#else
3698 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3699# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3700 if (!pGuestPml4)
3701 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3702# endif
3703 Assert(pGuestPml4);
3704#endif
3705 return pGuestPml4->a[iPml4];
3706}
3707
3708
3709/**
3710 * Gets the page directory pointer entry for the specified address.
3711 *
3712 * @returns Pointer to the page directory pointer entry in question.
3713 * @returns NULL if the page directory is not present or on an invalid page.
3714 * @param pPGM Pointer to the PGM instance data.
3715 * @param GCPtr The address.
3716 * @param ppPml4e Page Map Level-4 Entry (out)
3717 */
3718DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3719{
3720 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3721 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3722 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3723 if (pPml4e->n.u1Present)
3724 {
3725 PX86PDPT pPdpt;
3726 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3727 AssertRCReturn(rc, NULL);
3728
3729 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3730 return &pPdpt->a[iPdpt];
3731 }
3732 return NULL;
3733}
3734
3735
3736/**
3737 * Gets the page directory entry for the specified address.
3738 *
3739 * @returns The page directory entry in question.
3740 * @returns A non-present entry if the page directory is not present or on an invalid page.
3741 * @param pPGM Pointer to the PGM instance data.
3742 * @param GCPtr The address.
3743 * @param ppPml4e Page Map Level-4 Entry (out)
3744 * @param pPdpe Page directory pointer table entry (out)
3745 */
3746DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3747{
3748 X86PDEPAE ZeroPde = {0};
3749 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3750 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3751 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3752 if (pPml4e->n.u1Present)
3753 {
3754 PCX86PDPT pPdptTemp;
3755 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3756 AssertRCReturn(rc, ZeroPde);
3757
3758 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3759 *pPdpe = pPdptTemp->a[iPdpt];
3760 if (pPdptTemp->a[iPdpt].n.u1Present)
3761 {
3762 PCX86PDPAE pPD;
3763 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3764 AssertRCReturn(rc, ZeroPde);
3765
3766 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3767 return pPD->a[iPD];
3768 }
3769 }
3770
3771 return ZeroPde;
3772}
3773
3774
3775/**
3776 * Gets the page directory entry for the specified address.
3777 *
3778 * @returns The page directory entry in question.
3779 * @returns A non-present entry if the page directory is not present or on an invalid page.
3780 * @param pPGM Pointer to the PGM instance data.
3781 * @param GCPtr The address.
3782 */
3783DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
3784{
3785 X86PDEPAE ZeroPde = {0};
3786 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3787 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3788 if (pGuestPml4->a[iPml4].n.u1Present)
3789 {
3790 PCX86PDPT pPdptTemp;
3791 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3792 AssertRCReturn(rc, ZeroPde);
3793
3794 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3795 if (pPdptTemp->a[iPdpt].n.u1Present)
3796 {
3797 PCX86PDPAE pPD;
3798 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3799 AssertRCReturn(rc, ZeroPde);
3800
3801 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3802 return pPD->a[iPD];
3803 }
3804 }
3805 return ZeroPde;
3806}
3807
3808
3809/**
3810 * Gets the page directory entry for the specified address.
3811 *
3812 * @returns Pointer to the page directory entry in question.
3813 * @returns NULL if the page directory is not present or on an invalid page.
3814 * @param pPGM Pointer to the PGM instance data.
3815 * @param GCPtr The address.
3816 */
3817DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
3818{
3819 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3820 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3821 if (pGuestPml4->a[iPml4].n.u1Present)
3822 {
3823 PCX86PDPT pPdptTemp;
3824 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3825 AssertRCReturn(rc, NULL);
3826
3827 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3828 if (pPdptTemp->a[iPdpt].n.u1Present)
3829 {
3830 PX86PDPAE pPD;
3831 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3832 AssertRCReturn(rc, NULL);
3833
3834 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3835 return &pPD->a[iPD];
3836 }
3837 }
3838 return NULL;
3839}
3840
3841
3842/**
3843 * Gets the GUEST page directory pointer for the specified address.
3844 *
3845 * @returns The page directory in question.
3846 * @returns NULL if the page directory is not present or on an invalid page.
3847 * @param pPGM Pointer to the PGM instance data.
3848 * @param GCPtr The address.
3849 * @param ppPml4e Page Map Level-4 Entry (out)
3850 * @param pPdpe Page directory pointer table entry (out)
3851 * @param piPD Receives the index into the returned page directory
3852 */
3853DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3854{
3855 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3856 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3857 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3858 if (pPml4e->n.u1Present)
3859 {
3860 PCX86PDPT pPdptTemp;
3861 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3862 AssertRCReturn(rc, NULL);
3863
3864 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3865 *pPdpe = pPdptTemp->a[iPdpt];
3866 if (pPdptTemp->a[iPdpt].n.u1Present)
3867 {
3868 PX86PDPAE pPD;
3869 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3870 AssertRCReturn(rc, NULL);
3871
3872 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3873 return pPD;
3874 }
3875 }
3876 return 0;
3877}
3878
3879#endif /* !IN_RC */
3880
3881/**
3882 * Gets the shadow page directory, 32-bit.
3883 *
3884 * @returns Pointer to the shadow 32-bit PD.
3885 * @param pPGM Pointer to the PGM instance data.
3886 */
3887DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
3888{
3889 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
3890}
3891
3892
3893/**
3894 * Gets the shadow page directory entry for the specified address, 32-bit.
3895 *
3896 * @returns Shadow 32-bit PDE.
3897 * @param pPGM Pointer to the PGM instance data.
3898 * @param GCPtr The address.
3899 */
3900DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
3901{
3902 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
3903
3904 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
3905 if (!pShwPde)
3906 {
3907 X86PDE ZeroPde = {0};
3908 return ZeroPde;
3909 }
3910 return pShwPde->a[iPd];
3911}
3912
3913
3914/**
3915 * Gets the pointer to the shadow page directory entry for the specified
3916 * address, 32-bit.
3917 *
3918 * @returns Pointer to the shadow 32-bit PDE.
3919 * @param pPGM Pointer to the PGM instance data.
3920 * @param GCPtr The address.
3921 */
3922DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3923{
3924 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
3925
3926 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
3927 AssertReturn(pPde, NULL);
3928 return &pPde->a[iPd];
3929}
3930
3931
3932/**
3933 * Gets the shadow page pointer table, PAE.
3934 *
3935 * @returns Pointer to the shadow PAE PDPT.
3936 * @param pPGM Pointer to the PGM instance data.
3937 */
3938DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
3939{
3940 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
3941}
3942
3943
3944/**
3945 * Gets the shadow page directory for the specified address, PAE.
3946 *
3947 * @returns Pointer to the shadow PD.
3948 * @param pPGM Pointer to the PGM instance data.
3949 * @param GCPtr The address.
3950 */
3951DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
3952{
3953 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3954 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
3955
3956 if (!pPdpt->a[iPdpt].n.u1Present)
3957 return NULL;
3958
3959 /* Fetch the pgm pool shadow descriptor. */
3960 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
3961 AssertReturn(pShwPde, NULL);
3962
3963 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
3964}
3965
3966
3967/**
3968 * Gets the shadow page directory for the specified address, PAE.
3969 *
3970 * @returns Pointer to the shadow PD.
3971 * @param pPGM Pointer to the PGM instance data.
3972 * @param GCPtr The address.
3973 */
3974DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
3975{
3976 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3977
3978 if (!pPdpt->a[iPdpt].n.u1Present)
3979 return NULL;
3980
3981 /* Fetch the pgm pool shadow descriptor. */
3982 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
3983 AssertReturn(pShwPde, NULL);
3984
3985 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
3986}
3987
3988
3989/**
3990 * Gets the shadow page directory entry, PAE.
3991 *
3992 * @returns PDE.
3993 * @param pPGM Pointer to the PGM instance data.
3994 * @param GCPtr The address.
3995 */
3996DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3997{
3998 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3999
4000 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4001 if (!pShwPde)
4002 {
4003 X86PDEPAE ZeroPde = {0};
4004 return ZeroPde;
4005 }
4006 return pShwPde->a[iPd];
4007}
4008
4009
4010/**
4011 * Gets the pointer to the shadow page directory entry for an address, PAE.
4012 *
4013 * @returns Pointer to the PDE.
4014 * @param pPGM Pointer to the PGM instance data.
4015 * @param GCPtr The address.
4016 */
4017DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4018{
4019 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4020
4021 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4022 AssertReturn(pPde, NULL);
4023 return &pPde->a[iPd];
4024}
4025
4026#ifndef IN_RC
4027
4028/**
4029 * Gets the shadow page map level-4 pointer.
4030 *
4031 * @returns Pointer to the shadow PML4.
4032 * @param pPGM Pointer to the PGM instance data.
4033 */
4034DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4035{
4036 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4037}
4038
4039
4040/**
4041 * Gets the shadow page map level-4 entry for the specified address.
4042 *
4043 * @returns The entry.
4044 * @param pPGM Pointer to the PGM instance data.
4045 * @param GCPtr The address.
4046 */
4047DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4048{
4049 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4050 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4051
4052 if (!pShwPml4)
4053 {
4054 X86PML4E ZeroPml4e = {0};
4055 return ZeroPml4e;
4056 }
4057 return pShwPml4->a[iPml4];
4058}
4059
4060
4061/**
4062 * Gets the pointer to the specified shadow page map level-4 entry.
4063 *
4064 * @returns The entry.
4065 * @param pPGM Pointer to the PGM instance data.
4066 * @param iPml4 The PML4 index.
4067 */
4068DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4069{
4070 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4071 if (!pShwPml4)
4072 return NULL;
4073 return &pShwPml4->a[iPml4];
4074}
4075
4076
4077/**
4078 * Gets the GUEST page directory pointer for the specified address.
4079 *
4080 * @returns The page directory in question.
4081 * @returns NULL if the page directory is not present or on an invalid page.
4082 * @param pPGM Pointer to the PGM instance data.
4083 * @param GCPtr The address.
4084 * @param piPD Receives the index into the returned page directory
4085 */
4086DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4087{
4088 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4089 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4090 if (pGuestPml4->a[iPml4].n.u1Present)
4091 {
4092 PCX86PDPT pPdptTemp;
4093 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4094 AssertRCReturn(rc, NULL);
4095
4096 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4097 if (pPdptTemp->a[iPdpt].n.u1Present)
4098 {
4099 PX86PDPAE pPD;
4100 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4101 AssertRCReturn(rc, NULL);
4102
4103 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4104 return pPD;
4105 }
4106 }
4107 return NULL;
4108}
4109
4110#endif /* !IN_RC */
4111
4112/**
4113 * Gets the page state for a physical handler.
4114 *
4115 * @returns The physical handler page state.
4116 * @param pCur The physical handler in question.
4117 */
4118DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4119{
4120 switch (pCur->enmType)
4121 {
4122 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4123 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4124
4125 case PGMPHYSHANDLERTYPE_MMIO:
4126 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4127 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4128
4129 default:
4130 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4131 }
4132}
4133
4134
4135/**
4136 * Gets the page state for a virtual handler.
4137 *
4138 * @returns The virtual handler page state.
4139 * @param pCur The virtual handler in question.
4140 * @remarks This should never be used on a hypervisor access handler.
4141 */
4142DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4143{
4144 switch (pCur->enmType)
4145 {
4146 case PGMVIRTHANDLERTYPE_WRITE:
4147 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4148 case PGMVIRTHANDLERTYPE_ALL:
4149 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4150 default:
4151 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4152 }
4153}
4154
4155
4156/**
4157 * Clears one physical page of a virtual handler
4158 *
4159 * @param pPGM Pointer to the PGM instance.
4160 * @param pCur Virtual handler structure
4161 * @param iPage Physical page index
4162 *
4163 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4164 * need to care about other handlers in the same page.
4165 */
4166DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4167{
4168 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4169
4170 /*
4171 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4172 */
4173#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4174 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4175 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4176 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4177#endif
4178 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4179 {
4180 /* We're the head of the alias chain. */
4181 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4182#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4183 AssertReleaseMsg(pRemove != NULL,
4184 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4185 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4186 AssertReleaseMsg(pRemove == pPhys2Virt,
4187 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4188 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4189 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4190 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4191#endif
4192 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4193 {
4194 /* Insert the next list in the alias chain into the tree. */
4195 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4196#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4197 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4198 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4199 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4200#endif
4201 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4202 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4203 AssertRelease(fRc);
4204 }
4205 }
4206 else
4207 {
4208 /* Locate the previous node in the alias chain. */
4209 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4210#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4211 AssertReleaseMsg(pPrev != pPhys2Virt,
4212 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4213 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4214#endif
4215 for (;;)
4216 {
4217 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4218 if (pNext == pPhys2Virt)
4219 {
4220 /* unlink. */
4221 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4222 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4223 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4224 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4225 else
4226 {
4227 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4228 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4229 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4230 }
4231 break;
4232 }
4233
4234 /* next */
4235 if (pNext == pPrev)
4236 {
4237#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4238 AssertReleaseMsg(pNext != pPrev,
4239 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4240 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4241#endif
4242 break;
4243 }
4244 pPrev = pNext;
4245 }
4246 }
4247 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4248 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4249 pPhys2Virt->offNextAlias = 0;
4250 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4251
4252 /*
4253 * Clear the ram flags for this page.
4254 */
4255 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4256 AssertReturnVoid(pPage);
4257 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4258}
4259
4260
4261/**
4262 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4263 *
4264 * @returns Pointer to the shadow page structure.
4265 * @param pPool The pool.
4266 * @param HCPhys The HC physical address of the shadow page.
4267 */
4268DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4269{
4270 /*
4271 * Look up the page.
4272 */
4273 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4274 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4275 return pPage;
4276}
4277
4278
4279/**
4280 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4281 *
4282 * @returns Pointer to the shadow page structure.
4283 * @param pPool The pool.
4284 * @param idx The pool page index.
4285 */
4286DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4287{
4288 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4289 return &pPool->aPages[idx];
4290}
4291
4292
4293#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4294/**
4295 * Clear references to guest physical memory.
4296 *
4297 * @param pPool The pool.
4298 * @param pPoolPage The pool page.
4299 * @param pPhysPage The physical guest page tracking structure.
4300 */
4301DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4302{
4303 /*
4304 * Just deal with the simple case here.
4305 */
4306# ifdef LOG_ENABLED
4307 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4308# endif
4309 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4310 if (cRefs == 1)
4311 {
4312 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4313 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4314 }
4315 else
4316 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4317 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4318}
4319#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4320
4321
4322#ifdef PGMPOOL_WITH_CACHE
4323/**
4324 * Moves the page to the head of the age list.
4325 *
4326 * This is done when the cached page is used in one way or another.
4327 *
4328 * @param pPool The pool.
4329 * @param pPage The cached page.
4330 */
4331DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4332{
4333 /*
4334 * Move to the head of the age list.
4335 */
4336 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4337 {
4338 /* unlink */
4339 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4340 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4341 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4342 else
4343 pPool->iAgeTail = pPage->iAgePrev;
4344
4345 /* insert at head */
4346 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4347 pPage->iAgeNext = pPool->iAgeHead;
4348 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4349 pPool->iAgeHead = pPage->idx;
4350 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4351 }
4352}
4353#endif /* PGMPOOL_WITH_CACHE */
4354
4355/**
4356 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4357 *
4358 * @param pVM VM Handle.
4359 * @param pPage PGM pool page
4360 */
4361DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4362{
4363 Assert(!pPage->fLocked);
4364 pPage->fLocked = true;
4365}
4366
4367
4368/**
4369 * Unlocks a page to allow flushing again
4370 *
4371 * @param pVM VM Handle.
4372 * @param pPage PGM pool page
4373 */
4374DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4375{
4376 Assert(pPage->fLocked);
4377 pPage->fLocked = false;
4378}
4379
4380
4381/**
4382 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4383 *
4384 * @returns VBox status code.
4385 * @param pPage PGM pool page
4386 */
4387DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4388{
4389 if (pPage->fLocked)
4390 {
4391 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4392 if (pPage->cModifications)
4393 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4394 return true;
4395 }
4396 return false;
4397}
4398
4399/**
4400 * Tells if mappings are to be put into the shadow page table or not
4401 *
4402 * @returns boolean result
4403 * @param pVM VM handle.
4404 */
4405DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4406{
4407#ifdef IN_RING0
4408 /* There are no mappings in VT-x and AMD-V mode. */
4409 Assert(pPGM->fDisableMappings);
4410 return false;
4411#else
4412 return !pPGM->fDisableMappings;
4413#endif
4414}
4415
4416/** @} */
4417
4418#endif
4419
4420
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