PGMInternal.h@ 21116

Last change on this file since 21116 was 20808, checked in by vboxsync, 16 years ago
Removed dead code
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1	/* $Id: PGMInternal.h 20808 2009-06-23 08:43:53Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/critsect.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59	* Comment it if it will break something.
60	*/
61	#define PGM_OUT_OF_SYNC_IN_GC
62
63	/**
64	* Check and skip global PDEs for non-global flushes
65	*/
66	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68	/**
69	* Sync N pages instead of a whole page table
70	*/
71	#define PGM_SYNC_N_PAGES
72
73	/**
74	* Number of pages to sync during a page fault
75	*
76	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
77	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
78	*/
79	#define PGM_SYNC_NR_PAGES 8
80
81	/**
82	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
83	*/
84	#define PGM_MAX_PHYSCACHE_ENTRIES 64
85	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
86
87	/** @def PGMPOOL_WITH_CACHE
88	* Enable agressive caching using the page pool.
89	*
90	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
91	*/
92	#define PGMPOOL_WITH_CACHE
93
94	/** @def PGMPOOL_WITH_MIXED_PT_CR3
95	* When defined, we'll deal with 'uncachable' pages.
96	*/
97	#ifdef PGMPOOL_WITH_CACHE
98	# define PGMPOOL_WITH_MIXED_PT_CR3
99	#endif
100
101	/** @def PGMPOOL_WITH_MONITORING
102	* Monitor the guest pages which are shadowed.
103	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
104	* be enabled as well.
105	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
106	*/
107	#ifdef PGMPOOL_WITH_CACHE
108	# define PGMPOOL_WITH_MONITORING
109	#endif
110
111	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
112	* Tracking the of shadow pages mapping guest physical pages.
113	*
114	* This is very expensive, the current cache prototype is trying to figure out
115	* whether it will be acceptable with an agressive caching policy.
116	*/
117	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
118	# define PGMPOOL_WITH_GCPHYS_TRACKING
119	#endif
120
121	/** @def PGMPOOL_WITH_USER_TRACKING
122	* Tracking users of shadow pages. This is required for the linking of shadow page
123	* tables and physical guest addresses.
124	*/
125	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
126	# define PGMPOOL_WITH_USER_TRACKING
127	#endif
128
129	/** @def PGMPOOL_CFG_MAX_GROW
130	* The maximum number of pages to add to the pool in one go.
131	*/
132	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
133
134	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
135	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
136	*/
137	#ifdef VBOX_STRICT
138	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	#endif
140
141	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
142	* Enables the experimental lazy page allocation code. */
143	/# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
144
145	/** @} */
146
147
148	/** @name PDPT and PML4 flags.
149	* These are placed in the three bits available for system programs in
150	* the PDPT and PML4 entries.
151	* @{ */
152	/** The entry is a permanent one and it's must always be present.
153	* Never free such an entry. */
154	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
155	/** Mapping (hypervisor allocated pagetable). */
156	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
157	/** @} */
158
159	/** @name Page directory flags.
160	* These are placed in the three bits available for system programs in
161	* the page directory entries.
162	* @{ */
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
165	/** Made read-only to facilitate dirty bit tracking. */
166	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
167	/** @} */
168
169	/** @name Page flags.
170	* These are placed in the three bits available for system programs in
171	* the page entries.
172	* @{ */
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
175
176	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
177	/** Scanned and approved by CSAM (tm).
178	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
179	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
180	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
181	#endif
182
183	/** @} */
184
185	/** @name Defines used to indicate the shadow and guest paging in the templates.
186	* @{ */
187	#define PGM_TYPE_REAL 1
188	#define PGM_TYPE_PROT 2
189	#define PGM_TYPE_32BIT 3
190	#define PGM_TYPE_PAE 4
191	#define PGM_TYPE_AMD64 5
192	#define PGM_TYPE_NESTED 6
193	#define PGM_TYPE_EPT 7
194	#define PGM_TYPE_MAX PGM_TYPE_EPT
195	/** @} */
196
197	/** Macro for checking if the guest is using paging.
198	* @param uGstType PGM_TYPE_*
199	* @param uShwType PGM_TYPE_*
200	* @remark ASSUMES certain order of the PGM_TYPE_* values.
201	*/
202	#define PGM_WITH_PAGING(uGstType, uShwType) \
203	( (uGstType) >= PGM_TYPE_32BIT \
204	&& (uShwType) != PGM_TYPE_NESTED \
205	&& (uShwType) != PGM_TYPE_EPT)
206
207	/** Macro for checking if the guest supports the NX bit.
208	* @param uGstType PGM_TYPE_*
209	* @param uShwType PGM_TYPE_*
210	* @remark ASSUMES certain order of the PGM_TYPE_* values.
211	*/
212	#define PGM_WITH_NX(uGstType, uShwType) \
213	( (uGstType) >= PGM_TYPE_PAE \
214	&& (uShwType) != PGM_TYPE_NESTED \
215	&& (uShwType) != PGM_TYPE_EPT)
216
217
218	/** @def PGM_HCPHYS_2_PTR
219	* Maps a HC physical page pool address to a virtual address.
220	*
221	* @returns VBox status code.
222	* @param pVM The VM handle.
223	* @param HCPhys The HC physical address to map to a virtual one.
224	* @param ppv Where to store the virtual address. No need to cast this.
225	*
226	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
227	* small page window employeed by that function. Be careful.
228	* @remark There is no need to assert on the result.
229	*/
230	#ifdef IN_RC
231	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
232	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
233	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
234	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
236	#else
237	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
239	#endif
240
241	/** @def PGM_HCPHYS_2_PTR_BY_PGM
242	* Maps a HC physical page pool address to a virtual address.
243	*
244	* @returns VBox status code.
245	* @param pPGM The PGM instance data.
246	* @param HCPhys The HC physical address to map to a virtual one.
247	* @param ppv Where to store the virtual address. No need to cast this.
248	*
249	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
250	* small page window employeed by that function. Be careful.
251	* @remark There is no need to assert on the result.
252	*/
253	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
254	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
255	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
256	#else
257	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
259	#endif
260
261	/** @def PGM_GCPHYS_2_PTR
262	* Maps a GC physical page address to a virtual address.
263	*
264	* @returns VBox status code.
265	* @param pVM The VM handle.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
270	* small page window employeed by that function. Be careful.
271	* @remark There is no need to assert on the result.
272	*/
273	#ifdef IN_RC
274	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
275	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
276	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
277	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
279	#else
280	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
282	#endif
283
284	/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
285	* Maps a GC physical page address to a virtual address.
286	*
287	* @returns VBox status code.
288	* @param pPGM Pointer to the PGM instance data.
289	* @param GCPhys The GC physical address to map to a virtual one.
290	* @param ppv Where to store the virtual address. No need to cast this.
291	*
292	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
293	* small page window employeed by that function. Be careful.
294	* @remark There is no need to assert on the result.
295	*/
296	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
297	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
298	pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
299	#else
300	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
301	PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
302	#endif
303
304	/** @def PGM_GCPHYS_2_PTR_EX
305	* Maps a unaligned GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pVM The VM handle.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313	* small page window employeed by that function. Be careful.
314	* @remark There is no need to assert on the result.
315	*/
316	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
317	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
318	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
319	#else
320	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
322	#endif
323
324	/** @def PGM_INVL_PG
325	* Invalidates a page.
326	*
327	* @param pVCpu The VMCPU handle.
328	* @param GCVirt The virtual address of the page to invalidate.
329	*/
330	#ifdef IN_RC
331	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
332	#elif defined(IN_RING0)
333	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
334	#else
335	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
336	#endif
337
338	/** @def PGM_INVL_PG
339	* Invalidates a page on all VCPUs
340	*
341	* @param pVM The VM handle.
342	* @param GCVirt The virtual address of the page to invalidate.
343	*/
344	#ifdef IN_RC
345	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
346	#elif defined(IN_RING0)
347	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
348	#else
349	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
350	#endif
351
352	/** @def PGM_INVL_BIG_PG
353	* Invalidates a 4MB page directory entry.
354	*
355	* @param pVCpu The VMCPU handle.
356	* @param GCVirt The virtual address within the page directory to invalidate.
357	*/
358	#ifdef IN_RC
359	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
360	#elif defined(IN_RING0)
361	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
362	#else
363	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
364	#endif
365
366	/** @def PGM_INVL_VCPU_TLBS()
367	* Invalidates the TLBs of the specified VCPU
368	*
369	* @param pVCpu The VMCPU handle.
370	*/
371	#ifdef IN_RC
372	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
373	#elif defined(IN_RING0)
374	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
375	#else
376	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
377	#endif
378
379	/** @def PGM_INVL_ALL_VCPU_TLBS()
380	* Invalidates the TLBs of all VCPUs
381	*
382	* @param pVM The VM handle.
383	*/
384	#ifdef IN_RC
385	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
386	#elif defined(IN_RING0)
387	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
388	#else
389	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
390	#endif
391
392	/** Size of the GCPtrConflict array in PGMMAPPING.
393	* @remarks Must be a power of two. */
394	#define PGMMAPPING_CONFLICT_MAX 8
395
396	/**
397	* Structure for tracking GC Mappings.
398	*
399	* This structure is used by linked list in both GC and HC.
400	*/
401	typedef struct PGMMAPPING
402	{
403	/** Pointer to next entry. */
404	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
405	/** Pointer to next entry. */
406	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
407	/** Pointer to next entry. */
408	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
409	/** Indicate whether this entry is finalized. */
410	bool fFinalized;
411	/** Start Virtual address. */
412	RTGCPTR GCPtr;
413	/** Last Virtual address (inclusive). */
414	RTGCPTR GCPtrLast;
415	/** Range size (bytes). */
416	RTGCPTR cb;
417	/** Pointer to relocation callback function. */
418	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
419	/** User argument to the callback. */
420	R3PTRTYPE(void *) pvUser;
421	/** Mapping description / name. For easing debugging. */
422	R3PTRTYPE(const char *) pszDesc;
423	/** Last 8 addresses that caused conflicts. */
424	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
425	/** Number of conflicts for this hypervisor mapping. */
426	uint32_t cConflicts;
427	/** Number of page tables. */
428	uint32_t cPTs;
429
430	/** Array of page table mapping data. Each entry
431	* describes one page table. The array can be longer
432	* than the declared length.
433	*/
434	struct
435	{
436	/** The HC physical address of the page table. */
437	RTHCPHYS HCPhysPT;
438	/** The HC physical address of the first PAE page table. */
439	RTHCPHYS HCPhysPaePT0;
440	/** The HC physical address of the second PAE page table. */
441	RTHCPHYS HCPhysPaePT1;
442	/** The HC virtual address of the 32-bit page table. */
443	R3PTRTYPE(PX86PT) pPTR3;
444	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
445	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
446	/** The RC virtual address of the 32-bit page table. */
447	RCPTRTYPE(PX86PT) pPTRC;
448	/** The RC virtual address of the two PAE page table. */
449	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
450	/** The R0 virtual address of the 32-bit page table. */
451	R0PTRTYPE(PX86PT) pPTR0;
452	/** The R0 virtual address of the two PAE page table. */
453	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
454	} aPTs[1];
455	} PGMMAPPING;
456	/** Pointer to structure for tracking GC Mappings. */
457	typedef struct PGMMAPPING *PPGMMAPPING;
458
459
460	/**
461	* Physical page access handler structure.
462	*
463	* This is used to keep track of physical address ranges
464	* which are being monitored in some kind of way.
465	*/
466	typedef struct PGMPHYSHANDLER
467	{
468	AVLROGCPHYSNODECORE Core;
469	/** Access type. */
470	PGMPHYSHANDLERTYPE enmType;
471	/** Number of pages to update. */
472	uint32_t cPages;
473	/** Pointer to R3 callback function. */
474	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
475	/** User argument for R3 handlers. */
476	R3PTRTYPE(void *) pvUserR3;
477	/** Pointer to R0 callback function. */
478	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
479	/** User argument for R0 handlers. */
480	R0PTRTYPE(void *) pvUserR0;
481	/** Pointer to RC callback function. */
482	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
483	/** User argument for RC handlers. */
484	RCPTRTYPE(void *) pvUserRC;
485	/** Description / Name. For easing debugging. */
486	R3PTRTYPE(const char *) pszDesc;
487	#ifdef VBOX_WITH_STATISTICS
488	/** Profiling of this handler. */
489	STAMPROFILE Stat;
490	#endif
491	} PGMPHYSHANDLER;
492	/** Pointer to a physical page access handler structure. */
493	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
494
495
496	/**
497	* Cache node for the physical addresses covered by a virtual handler.
498	*/
499	typedef struct PGMPHYS2VIRTHANDLER
500	{
501	/** Core node for the tree based on physical ranges. */
502	AVLROGCPHYSNODECORE Core;
503	/** Offset from this struct to the PGMVIRTHANDLER structure. */
504	int32_t offVirtHandler;
505	/** Offset of the next alias relative to this one.
506	* Bit 0 is used for indicating whether we're in the tree.
507	* Bit 1 is used for indicating that we're the head node.
508	*/
509	int32_t offNextAlias;
510	} PGMPHYS2VIRTHANDLER;
511	/** Pointer to a phys to virtual handler structure. */
512	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
513
514	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
515	* node is in the tree. */
516	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
517	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
518	* node is in the head of an alias chain.
519	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
520	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
521	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
522	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
523
524
525	/**
526	* Virtual page access handler structure.
527	*
528	* This is used to keep track of virtual address ranges
529	* which are being monitored in some kind of way.
530	*/
531	typedef struct PGMVIRTHANDLER
532	{
533	/** Core node for the tree based on virtual ranges. */
534	AVLROGCPTRNODECORE Core;
535	/** Size of the range (in bytes). */
536	RTGCPTR cb;
537	/** Number of cache pages. */
538	uint32_t cPages;
539	/** Access type. */
540	PGMVIRTHANDLERTYPE enmType;
541	/** Pointer to the RC callback function. */
542	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
543	#if HC_ARCH_BITS == 64
544	RTRCPTR padding;
545	#endif
546	/** Pointer to the R3 callback function for invalidation. */
547	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
548	/** Pointer to the R3 callback function. */
549	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
550	/** Description / Name. For easing debugging. */
551	R3PTRTYPE(const char *) pszDesc;
552	#ifdef VBOX_WITH_STATISTICS
553	/** Profiling of this handler. */
554	STAMPROFILE Stat;
555	#endif
556	/** Array of cached physical addresses for the monitored ranged. */
557	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
558	} PGMVIRTHANDLER;
559	/** Pointer to a virtual page access handler structure. */
560	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
561
562
563	/**
564	* Page type.
565	*
566	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
567	* @remarks This is used in the saved state, so changes to it requires bumping
568	* the saved state version.
569	* @todo So, convert to \#defines!
570	*/
571	typedef enum PGMPAGETYPE
572	{
573	/** The usual invalid zero entry. */
574	PGMPAGETYPE_INVALID = 0,
575	/** RAM page. (RWX) */
576	PGMPAGETYPE_RAM,
577	/** MMIO2 page. (RWX) */
578	PGMPAGETYPE_MMIO2,
579	/** MMIO2 page aliased over an MMIO page. (RWX)
580	* See PGMHandlerPhysicalPageAlias(). */
581	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
582	/** Shadowed ROM. (RWX) */
583	PGMPAGETYPE_ROM_SHADOW,
584	/** ROM page. (R-X) */
585	PGMPAGETYPE_ROM,
586	/** MMIO page. (---) */
587	PGMPAGETYPE_MMIO,
588	/** End of valid entries. */
589	PGMPAGETYPE_END
590	} PGMPAGETYPE;
591	AssertCompile(PGMPAGETYPE_END <= 7);
592
593	/** @name Page type predicates.
594	* @{ */
595	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
596	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
597	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
598	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
599	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
600	/** @} */
601
602
603	/**
604	* A Physical Guest Page tracking structure.
605	*
606	* The format of this structure is complicated because we have to fit a lot
607	* of information into as few bits as possible. The format is also subject
608	* to change (there is one comming up soon). Which means that for we'll be
609	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
610	* accessess to the structure.
611	*/
612	typedef struct PGMPAGE
613	{
614	/** The physical address and a whole lot of other stuff. All bits are used! */
615	RTHCPHYS HCPhysX;
616	/** The page state. */
617	uint32_t u2StateX : 2;
618	/** Flag indicating that a write monitored page was written to when set. */
619	uint32_t fWrittenToX : 1;
620	/** For later. */
621	uint32_t fSomethingElse : 1;
622	/** The Page ID.
623	* @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
624	* The HCPhysX will then be 100% static. */
625	uint32_t idPageX : 28;
626	/** The page type (PGMPAGETYPE). */
627	uint32_t u3Type : 3;
628	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
629	uint32_t u2HandlerPhysStateX : 2;
630	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
631	uint32_t u2HandlerVirtStateX : 2;
632	uint32_t u29B : 25;
633	} PGMPAGE;
634	AssertCompileSize(PGMPAGE, 16);
635	/** Pointer to a physical guest page. */
636	typedef PGMPAGE *PPGMPAGE;
637	/** Pointer to a const physical guest page. */
638	typedef const PGMPAGE *PCPGMPAGE;
639	/** Pointer to a physical guest page pointer. */
640	typedef PPGMPAGE *PPPGMPAGE;
641
642
643	/**
644	* Clears the page structure.
645	* @param pPage Pointer to the physical guest page tracking structure.
646	*/
647	#define PGM_PAGE_CLEAR(pPage) \
648	do { \
649	(pPage)->HCPhysX = 0; \
650	(pPage)->u2StateX = 0; \
651	(pPage)->fWrittenToX = 0; \
652	(pPage)->fSomethingElse = 0; \
653	(pPage)->idPageX = 0; \
654	(pPage)->u3Type = 0; \
655	(pPage)->u29B = 0; \
656	} while (0)
657
658	/**
659	* Initializes the page structure.
660	* @param pPage Pointer to the physical guest page tracking structure.
661	*/
662	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
663	do { \
664	(pPage)->HCPhysX = (_HCPhys); \
665	(pPage)->u2StateX = (_uState); \
666	(pPage)->fWrittenToX = 0; \
667	(pPage)->fSomethingElse = 0; \
668	(pPage)->idPageX = (_idPage); \
669	/(pPage)->u3Type = (_uType); - later / \
670	PGM_PAGE_SET_TYPE(pPage, _uType); \
671	(pPage)->u29B = 0; \
672	} while (0)
673
674	/**
675	* Initializes the page structure of a ZERO page.
676	* @param pPage Pointer to the physical guest page tracking structure.
677	*/
678	#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
679	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
680	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
681	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
682	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
683
684
685	/** @name The Page state, PGMPAGE::u2StateX.
686	* @{ */
687	/** The zero page.
688	* This is a per-VM page that's never ever mapped writable. */
689	#define PGM_PAGE_STATE_ZERO 0
690	/** A allocated page.
691	* This is a per-VM page allocated from the page pool (or wherever
692	* we get MMIO2 pages from if the type is MMIO2).
693	*/
694	#define PGM_PAGE_STATE_ALLOCATED 1
695	/** A allocated page that's being monitored for writes.
696	* The shadow page table mappings are read-only. When a write occurs, the
697	* fWrittenTo member is set, the page remapped as read-write and the state
698	* moved back to allocated. */
699	#define PGM_PAGE_STATE_WRITE_MONITORED 2
700	/** The page is shared, aka. copy-on-write.
701	* This is a page that's shared with other VMs. */
702	#define PGM_PAGE_STATE_SHARED 3
703	/** @} */
704
705
706	/**
707	* Gets the page state.
708	* @returns page state (PGM_PAGE_STATE_*).
709	* @param pPage Pointer to the physical guest page tracking structure.
710	*/
711	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
712
713	/**
714	* Sets the page state.
715	* @param pPage Pointer to the physical guest page tracking structure.
716	* @param _uState The new page state.
717	*/
718	#define PGM_PAGE_SET_STATE(pPage, _uState) \
719	do { (pPage)->u2StateX = (_uState); } while (0)
720
721
722	/**
723	* Gets the host physical address of the guest page.
724	* @returns host physical address (RTHCPHYS).
725	* @param pPage Pointer to the physical guest page tracking structure.
726	*/
727	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
728
729	/**
730	* Sets the host physical address of the guest page.
731	* @param pPage Pointer to the physical guest page tracking structure.
732	* @param _HCPhys The new host physical address.
733	*/
734	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
735	do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
736	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
737
738	/**
739	* Get the Page ID.
740	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
741	* @param pPage Pointer to the physical guest page tracking structure.
742	*/
743	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
744	/* later:
745	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
746	\| ((uint32_t)(pPage)->HCPhysX & 0xfff) )
747	*/
748	/**
749	* Sets the Page ID.
750	* @param pPage Pointer to the physical guest page tracking structure.
751	*/
752	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
753	/* later:
754	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
755	\| ((_idPage) & 0xfff) \
756	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
757	*/
758
759	/**
760	* Get the Chunk ID.
761	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
762	* @param pPage Pointer to the physical guest page tracking structure.
763	*/
764	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
765	/* later:
766	#if GMM_CHUNKID_SHIFT == 12
767	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
768	#elif GMM_CHUNKID_SHIFT > 12
769	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
770	#elif GMM_CHUNKID_SHIFT < 12
771	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
772	\| ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
773	#else
774	# error "GMM_CHUNKID_SHIFT isn't defined or something."
775	#endif
776	*/
777
778	/**
779	* Get the index of the page within the allocaiton chunk.
780	* @returns The page index.
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
784	/* later:
785	#if GMM_CHUNKID_SHIFT <= 12
786	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
787	#else
788	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
789	\| ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
790	#endif
791	*/
792
793
794	/**
795	* Gets the page type.
796	* @returns The page type.
797	* @param pPage Pointer to the physical guest page tracking structure.
798	*/
799	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
800
801	/**
802	* Sets the page type.
803	* @param pPage Pointer to the physical guest page tracking structure.
804	* @param _enmType The new page type (PGMPAGETYPE).
805	*/
806	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
807	do { (pPage)->u3Type = (_enmType); } while (0)
808
809	/**
810	* Checks if the page is marked for MMIO.
811	* @returns true/false.
812	* @param pPage Pointer to the physical guest page tracking structure.
813	*/
814	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
815
816	/**
817	* Checks if the page is backed by the ZERO page.
818	* @returns true/false.
819	* @param pPage Pointer to the physical guest page tracking structure.
820	*/
821	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
822
823	/**
824	* Checks if the page is backed by a SHARED page.
825	* @returns true/false.
826	* @param pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
829
830
831	/**
832	* Marks the paget as written to (for GMM change monitoring).
833	* @param pPage Pointer to the physical guest page tracking structure.
834	*/
835	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
836
837	/**
838	* Clears the written-to indicator.
839	* @param pPage Pointer to the physical guest page tracking structure.
840	*/
841	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
842
843	/**
844	* Checks if the page was marked as written-to.
845	* @returns true/false.
846	* @param pPage Pointer to the physical guest page tracking structure.
847	*/
848	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
849
850
851	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
852	*
853	* @remarks The values are assigned in order of priority, so we can calculate
854	* the correct state for a page with different handlers installed.
855	* @{ */
856	/** No handler installed. */
857	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
858	/** Monitoring is temporarily disabled. */
859	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
860	/** Write access is monitored. */
861	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
862	/** All access is monitored. */
863	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
864	/** @} */
865
866	/**
867	* Gets the physical access handler state of a page.
868	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
869	* @param pPage Pointer to the physical guest page tracking structure.
870	*/
871	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
872
873	/**
874	* Sets the physical access handler state of a page.
875	* @param pPage Pointer to the physical guest page tracking structure.
876	* @param _uState The new state value.
877	*/
878	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
879	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
880
881	/**
882	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
883	* @returns true/false
884	* @param pPage Pointer to the physical guest page tracking structure.
885	*/
886	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
887
888	/**
889	* Checks if the page has any active physical access handlers.
890	* @returns true/false
891	* @param pPage Pointer to the physical guest page tracking structure.
892	*/
893	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
894
895
896	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
897	*
898	* @remarks The values are assigned in order of priority, so we can calculate
899	* the correct state for a page with different handlers installed.
900	* @{ */
901	/** No handler installed. */
902	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
903	/* 1 is reserved so the lineup is identical with the physical ones. */
904	/** Write access is monitored. */
905	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
906	/** All access is monitored. */
907	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
908	/** @} */
909
910	/**
911	* Gets the virtual access handler state of a page.
912	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
913	* @param pPage Pointer to the physical guest page tracking structure.
914	*/
915	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
916
917	/**
918	* Sets the virtual access handler state of a page.
919	* @param pPage Pointer to the physical guest page tracking structure.
920	* @param _uState The new state value.
921	*/
922	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
923	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
924
925	/**
926	* Checks if the page has any virtual access handlers.
927	* @returns true/false
928	* @param pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
931
932	/**
933	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
934	* virtual handlers.
935	* @returns true/false
936	* @param pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
939
940
941
942	/**
943	* Checks if the page has any access handlers, including temporarily disabled ones.
944	* @returns true/false
945	* @param pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
948	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
949	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951	/**
952	* Checks if the page has any active access handlers.
953	* @returns true/false
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
957	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
958	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
959
960	/**
961	* Checks if the page has any active access handlers catching all accesses.
962	* @returns true/false
963	* @param pPage Pointer to the physical guest page tracking structure.
964	*/
965	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
967	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
968
969
970
971
972	/** @def PGM_PAGE_GET_TRACKING
973	* Gets the packed shadow page pool tracking data associated with a guest page.
974	* @returns uint16_t containing the data.
975	* @param pPage Pointer to the physical guest page tracking structure.
976	*/
977	#define PGM_PAGE_GET_TRACKING(pPage) \
978	( ((uint16_t )&(pPage)->HCPhysX + 3) )
979
980	/** @def PGM_PAGE_SET_TRACKING
981	* Sets the packed shadow page pool tracking data associated with a guest page.
982	* @param pPage Pointer to the physical guest page tracking structure.
983	* @param u16TrackingData The tracking data to store.
984	*/
985	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
986	do { ((uint16_t )&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
987
988	/** @def PGM_PAGE_GET_TD_CREFS
989	* Gets the @a cRefs tracking data member.
990	* @returns cRefs.
991	* @param pPage Pointer to the physical guest page tracking structure.
992	*/
993	#define PGM_PAGE_GET_TD_CREFS(pPage) \
994	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
995
996	#define PGM_PAGE_GET_TD_IDX(pPage) \
997	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
998
999	/**
1000	* Ram range for GC Phys to HC Phys conversion.
1001	*
1002	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1003	* conversions too, but we'll let MM handle that for now.
1004	*
1005	* This structure is used by linked lists in both GC and HC.
1006	*/
1007	typedef struct PGMRAMRANGE
1008	{
1009	/** Start of the range. Page aligned. */
1010	RTGCPHYS GCPhys;
1011	/** Size of the range. (Page aligned of course). */
1012	RTGCPHYS cb;
1013	/** Pointer to the next RAM range - for R3. */
1014	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1015	/** Pointer to the next RAM range - for R0. */
1016	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1017	/** Pointer to the next RAM range - for RC. */
1018	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1019	/** PGM_RAM_RANGE_FLAGS_* flags. */
1020	uint32_t fFlags;
1021	/** Last address in the range (inclusive). Page aligned (-1). */
1022	RTGCPHYS GCPhysLast;
1023	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1024	R3PTRTYPE(void *) pvR3;
1025	/** The range description. */
1026	R3PTRTYPE(const char *) pszDesc;
1027	/** Pointer to self - R0 pointer. */
1028	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1029	/** Pointer to self - RC pointer. */
1030	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1031	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1032	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1033	/** Array of physical guest page tracking structures. */
1034	PGMPAGE aPages[1];
1035	} PGMRAMRANGE;
1036	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1037	typedef PGMRAMRANGE *PPGMRAMRANGE;
1038
1039	/** @name PGMRAMRANGE::fFlags
1040	* @{ */
1041	/** The RAM range is floating around as an independent guest mapping. */
1042	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1043	/** @} */
1044
1045
1046	/**
1047	* Per page tracking structure for ROM image.
1048	*
1049	* A ROM image may have a shadow page, in which case we may have
1050	* two pages backing it. This structure contains the PGMPAGE for
1051	* both while PGMRAMRANGE have a copy of the active one. It is
1052	* important that these aren't out of sync in any regard other
1053	* than page pool tracking data.
1054	*/
1055	typedef struct PGMROMPAGE
1056	{
1057	/** The page structure for the virgin ROM page. */
1058	PGMPAGE Virgin;
1059	/** The page structure for the shadow RAM page. */
1060	PGMPAGE Shadow;
1061	/** The current protection setting. */
1062	PGMROMPROT enmProt;
1063	/** Pad the structure size to a multiple of 8. */
1064	uint32_t u32Padding;
1065	} PGMROMPAGE;
1066	/** Pointer to a ROM page tracking structure. */
1067	typedef PGMROMPAGE *PPGMROMPAGE;
1068
1069
1070	/**
1071	* A registered ROM image.
1072	*
1073	* This is needed to keep track of ROM image since they generally
1074	* intrude into a PGMRAMRANGE. It also keeps track of additional
1075	* info like the two page sets (read-only virgin and read-write shadow),
1076	* the current state of each page.
1077	*
1078	* Because access handlers cannot easily be executed in a different
1079	* context, the ROM ranges needs to be accessible and in all contexts.
1080	*/
1081	typedef struct PGMROMRANGE
1082	{
1083	/** Pointer to the next range - R3. */
1084	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1085	/** Pointer to the next range - R0. */
1086	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1087	/** Pointer to the next range - RC. */
1088	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1089	/** Pointer alignment */
1090	RTRCPTR GCPtrAlignment;
1091	/** Address of the range. */
1092	RTGCPHYS GCPhys;
1093	/** Address of the last byte in the range. */
1094	RTGCPHYS GCPhysLast;
1095	/** Size of the range. */
1096	RTGCPHYS cb;
1097	/** The flags (PGMPHYS_ROM_FLAG_). /
1098	uint32_t fFlags;
1099	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1100	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1101	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1102	* This is used for strictness checks. */
1103	R3PTRTYPE(const void *) pvOriginal;
1104	/** The ROM description. */
1105	R3PTRTYPE(const char *) pszDesc;
1106	/** The per page tracking structures. */
1107	PGMROMPAGE aPages[1];
1108	} PGMROMRANGE;
1109	/** Pointer to a ROM range. */
1110	typedef PGMROMRANGE *PPGMROMRANGE;
1111
1112
1113	/**
1114	* A registered MMIO2 (= Device RAM) range.
1115	*
1116	* There are a few reason why we need to keep track of these
1117	* registrations. One of them is the deregistration & cleanup
1118	* stuff, while another is that the PGMRAMRANGE associated with
1119	* such a region may have to be removed from the ram range list.
1120	*
1121	* Overlapping with a RAM range has to be 100% or none at all. The
1122	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1123	* meditation will be raised if a partial overlap or an overlap of
1124	* ROM pages is encountered. On an overlap we will free all the
1125	* existing RAM pages and put in the ram range pages instead.
1126	*/
1127	typedef struct PGMMMIO2RANGE
1128	{
1129	/** The owner of the range. (a device) */
1130	PPDMDEVINSR3 pDevInsR3;
1131	/** Pointer to the ring-3 mapping of the allocation. */
1132	RTR3PTR pvR3;
1133	/** Pointer to the next range - R3. */
1134	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1135	/** Whether it's mapped or not. */
1136	bool fMapped;
1137	/** Whether it's overlapping or not. */
1138	bool fOverlapping;
1139	/** The PCI region number.
1140	* @remarks This ASSUMES that nobody will ever really need to have multiple
1141	* PCI devices with matching MMIO region numbers on a single device. */
1142	uint8_t iRegion;
1143	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1144	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1145	/** The associated RAM range. */
1146	PGMRAMRANGE RamRange;
1147	} PGMMMIO2RANGE;
1148	/** Pointer to a MMIO2 range. */
1149	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1150
1151
1152
1153
1154	/**
1155	* PGMPhysRead/Write cache entry
1156	*/
1157	typedef struct PGMPHYSCACHEENTRY
1158	{
1159	/** R3 pointer to physical page. */
1160	R3PTRTYPE(uint8_t *) pbR3;
1161	/** GC Physical address for cache entry */
1162	RTGCPHYS GCPhys;
1163	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1164	RTGCPHYS u32Padding0; /*< alignment padding. /
1165	#endif
1166	} PGMPHYSCACHEENTRY;
1167
1168	/**
1169	* PGMPhysRead/Write cache to reduce REM memory access overhead
1170	*/
1171	typedef struct PGMPHYSCACHE
1172	{
1173	/** Bitmap of valid cache entries */
1174	uint64_t aEntries;
1175	/** Cache entries */
1176	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1177	} PGMPHYSCACHE;
1178
1179
1180	/** Pointer to an allocation chunk ring-3 mapping. */
1181	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1182	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1183	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1184
1185	/**
1186	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1187	*
1188	* The primary tree (Core) uses the chunk id as key.
1189	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1190	*/
1191	typedef struct PGMCHUNKR3MAP
1192	{
1193	/** The key is the chunk id. */
1194	AVLU32NODECORE Core;
1195	/** The key is the ageing sequence number. */
1196	AVLLU32NODECORE AgeCore;
1197	/** The current age thingy. */
1198	uint32_t iAge;
1199	/** The current reference count. */
1200	uint32_t volatile cRefs;
1201	/** The current permanent reference count. */
1202	uint32_t volatile cPermRefs;
1203	/** The mapping address. */
1204	void *pv;
1205	} PGMCHUNKR3MAP;
1206
1207	/**
1208	* Allocation chunk ring-3 mapping TLB entry.
1209	*/
1210	typedef struct PGMCHUNKR3MAPTLBE
1211	{
1212	/** The chunk id. */
1213	uint32_t volatile idChunk;
1214	#if HC_ARCH_BITS == 64
1215	uint32_t u32Padding; /*< alignment padding. /
1216	#endif
1217	/** The chunk map. */
1218	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1220	#else
1221	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1222	#endif
1223	} PGMCHUNKR3MAPTLBE;
1224	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1225	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1226
1227	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1228	* @remark Must be a power of two value. */
1229	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1230
1231	/**
1232	* Allocation chunk ring-3 mapping TLB.
1233	*
1234	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1235	* At first glance this might look kinda odd since AVL trees are
1236	* supposed to give the most optimial lookup times of all trees
1237	* due to their balancing. However, take a tree with 1023 nodes
1238	* in it, that's 10 levels, meaning that most searches has to go
1239	* down 9 levels before they find what they want. This isn't fast
1240	* compared to a TLB hit. There is the factor of cache misses,
1241	* and of course the problem with trees and branch prediction.
1242	* This is why we use TLBs in front of most of the trees.
1243	*
1244	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1245	* difficult when we switch to the new inlined AVL trees (from kStuff).
1246	*/
1247	typedef struct PGMCHUNKR3MAPTLB
1248	{
1249	/** The TLB entries. */
1250	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1251	} PGMCHUNKR3MAPTLB;
1252
1253	/**
1254	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1255	* @returns Chunk TLB index.
1256	* @param idChunk The Chunk ID.
1257	*/
1258	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1259
1260
1261	/**
1262	* Ring-3 guest page mapping TLB entry.
1263	* @remarks used in ring-0 as well at the moment.
1264	*/
1265	typedef struct PGMPAGER3MAPTLBE
1266	{
1267	/** Address of the page. */
1268	RTGCPHYS volatile GCPhys;
1269	/** The guest page. */
1270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1271	R3PTRTYPE(PPGMPAGE) volatile pPage;
1272	#else
1273	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1274	#endif
1275	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1276	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1277	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1278	#else
1279	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1280	#endif
1281	/** The address */
1282	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1283	R3PTRTYPE(void *) volatile pv;
1284	#else
1285	R3R0PTRTYPE(void *) volatile pv;
1286	#endif
1287	#if HC_ARCH_BITS == 32
1288	uint32_t u32Padding; /*< alignment padding. /
1289	#endif
1290	} PGMPAGER3MAPTLBE;
1291	/** Pointer to an entry in the HC physical TLB. */
1292	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1293
1294
1295	/** The number of entries in the ring-3 guest page mapping TLB.
1296	* @remarks The value must be a power of two. */
1297	#define PGM_PAGER3MAPTLB_ENTRIES 64
1298
1299	/**
1300	* Ring-3 guest page mapping TLB.
1301	* @remarks used in ring-0 as well at the moment.
1302	*/
1303	typedef struct PGMPAGER3MAPTLB
1304	{
1305	/** The TLB entries. */
1306	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1307	} PGMPAGER3MAPTLB;
1308	/** Pointer to the ring-3 guest page mapping TLB. */
1309	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1310
1311	/**
1312	* Calculates the index of the TLB entry for the specified guest page.
1313	* @returns Physical TLB index.
1314	* @param GCPhys The guest physical address.
1315	*/
1316	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1317
1318
1319	/**
1320	* Mapping cache usage set entry.
1321	*
1322	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1323	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1324	* cache. If it's extended to include ring-3, well, then something will
1325	* have be changed here...
1326	*/
1327	typedef struct PGMMAPSETENTRY
1328	{
1329	/** The mapping cache index. */
1330	uint16_t iPage;
1331	/** The number of references.
1332	* The max is UINT16_MAX - 1. */
1333	uint16_t cRefs;
1334	#if HC_ARCH_BITS == 64
1335	uint32_t alignment;
1336	#endif
1337	/** Pointer to the page. */
1338	RTR0PTR pvPage;
1339	/** The physical address for this entry. */
1340	RTHCPHYS HCPhys;
1341	} PGMMAPSETENTRY;
1342	/** Pointer to a mapping cache usage set entry. */
1343	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1344
1345	/**
1346	* Mapping cache usage set.
1347	*
1348	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1349	* done during exits / traps. The set is
1350	*/
1351	typedef struct PGMMAPSET
1352	{
1353	/** The number of occupied entries.
1354	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1355	* dynamic mappings. */
1356	uint32_t cEntries;
1357	/** The start of the current subset.
1358	* This is UINT32_MAX if no subset is currently open. */
1359	uint32_t iSubset;
1360	/** The index of the current CPU, only valid if the set is open. */
1361	int32_t iCpu;
1362	#if HC_ARCH_BITS == 64
1363	uint32_t alignment;
1364	#endif
1365	/** The entries. */
1366	PGMMAPSETENTRY aEntries[64];
1367	/** HCPhys -> iEntry fast lookup table.
1368	* Use PGMMAPSET_HASH for hashing.
1369	* The entries may or may not be valid, check against cEntries. */
1370	uint8_t aiHashTable[128];
1371	} PGMMAPSET;
1372	/** Pointer to the mapping cache set. */
1373	typedef PGMMAPSET *PPGMMAPSET;
1374
1375	/** PGMMAPSET::cEntries value for a closed set. */
1376	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1377
1378	/** Hash function for aiHashTable. */
1379	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1380
1381	/** The max fill size (strict builds). */
1382	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1383
1384
1385	/** @name Context neutrual page mapper TLB.
1386	*
1387	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1388	* code is writting in a kind of context neutrual way. Time will show whether
1389	* this actually makes sense or not...
1390	*
1391	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1392	* context ends up using a global mapping cache on some platforms
1393	* (darwin).
1394	*
1395	* @{ */
1396	/** @typedef PPGMPAGEMAPTLB
1397	* The page mapper TLB pointer type for the current context. */
1398	/** @typedef PPGMPAGEMAPTLB
1399	* The page mapper TLB entry pointer type for the current context. */
1400	/** @typedef PPGMPAGEMAPTLB
1401	* The page mapper TLB entry pointer pointer type for the current context. */
1402	/** @def PGM_PAGEMAPTLB_ENTRIES
1403	* The number of TLB entries in the page mapper TLB for the current context. */
1404	/** @def PGM_PAGEMAPTLB_IDX
1405	* Calculate the TLB index for a guest physical address.
1406	* @returns The TLB index.
1407	* @param GCPhys The guest physical address. */
1408	/** @typedef PPGMPAGEMAP
1409	* Pointer to a page mapper unit for current context. */
1410	/** @typedef PPPGMPAGEMAP
1411	* Pointer to a page mapper unit pointer for current context. */
1412	#ifdef IN_RC
1413	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1414	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1415	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1416	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1417	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1418	typedef void * PPGMPAGEMAP;
1419	typedef void ** PPPGMPAGEMAP;
1420	//#elif IN_RING0
1421	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1422	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1423	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1424	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1425	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1426	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1427	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1428	#else
1429	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1430	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1431	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1432	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1433	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1434	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1435	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1436	#endif
1437	/** @} */
1438
1439
1440	/** @name PGM Pool Indexes.
1441	* Aka. the unique shadow page identifier.
1442	* @{ */
1443	/** NIL page pool IDX. */
1444	#define NIL_PGMPOOL_IDX 0
1445	/** The first normal index. */
1446	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1447	/** Page directory (32-bit root). */
1448	#define PGMPOOL_IDX_PD 1
1449	/** Page Directory Pointer Table (PAE root). */
1450	#define PGMPOOL_IDX_PDPT 2
1451	/** AMD64 CR3 level index.*/
1452	#define PGMPOOL_IDX_AMD64_CR3 3
1453	/** Nested paging root.*/
1454	#define PGMPOOL_IDX_NESTED_ROOT 4
1455	/** The first normal index. */
1456	#define PGMPOOL_IDX_FIRST 5
1457	/** The last valid index. (inclusive, 14 bits) */
1458	#define PGMPOOL_IDX_LAST 0x3fff
1459	/** @} */
1460
1461	/** The NIL index for the parent chain. */
1462	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1463
1464	/**
1465	* Node in the chain linking a shadowed page to it's parent (user).
1466	*/
1467	#pragma pack(1)
1468	typedef struct PGMPOOLUSER
1469	{
1470	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1471	uint16_t iNext;
1472	/** The user page index. */
1473	uint16_t iUser;
1474	/** Index into the user table. */
1475	uint32_t iUserTable;
1476	} PGMPOOLUSER, *PPGMPOOLUSER;
1477	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1478	#pragma pack()
1479
1480
1481	/** The NIL index for the phys ext chain. */
1482	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1483
1484	/**
1485	* Node in the chain of physical cross reference extents.
1486	* @todo Calling this an 'extent' is not quite right, find a better name.
1487	*/
1488	#pragma pack(1)
1489	typedef struct PGMPOOLPHYSEXT
1490	{
1491	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1492	uint16_t iNext;
1493	/** The user page index. */
1494	uint16_t aidx[3];
1495	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1496	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1497	#pragma pack()
1498
1499
1500	/**
1501	* The kind of page that's being shadowed.
1502	*/
1503	typedef enum PGMPOOLKIND
1504	{
1505	/** The virtual invalid 0 entry. */
1506	PGMPOOLKIND_INVALID = 0,
1507	/** The entry is free (=unused). */
1508	PGMPOOLKIND_FREE,
1509
1510	/** Shw: 32-bit page table; Gst: no paging */
1511	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1512	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1513	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1514	/** Shw: 32-bit page table; Gst: 4MB page. */
1515	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1516	/** Shw: PAE page table; Gst: no paging */
1517	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1518	/** Shw: PAE page table; Gst: 32-bit page table. */
1519	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1520	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1521	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1522	/** Shw: PAE page table; Gst: PAE page table. */
1523	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1524	/** Shw: PAE page table; Gst: 2MB page. */
1525	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1526
1527	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1528	PGMPOOLKIND_32BIT_PD,
1529	/** Shw: 32-bit page directory. Gst: no paging. */
1530	PGMPOOLKIND_32BIT_PD_PHYS,
1531	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1532	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1533	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1534	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1535	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1536	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1537	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1538	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1539	/** Shw: PAE page directory; Gst: PAE page directory. */
1540	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1541	/** Shw: PAE page directory; Gst: no paging. */
1542	PGMPOOLKIND_PAE_PD_PHYS,
1543
1544	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1545	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1546	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1547	PGMPOOLKIND_PAE_PDPT,
1548	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1549	PGMPOOLKIND_PAE_PDPT_PHYS,
1550
1551	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1552	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1553	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1554	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1555	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1556	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1557	/** Shw: 64-bit page directory table; Gst: no paging */
1558	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1559
1560	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1561	PGMPOOLKIND_64BIT_PML4,
1562
1563	/** Shw: EPT page directory pointer table; Gst: no paging */
1564	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1565	/** Shw: EPT page directory table; Gst: no paging */
1566	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1567	/** Shw: EPT page table; Gst: no paging */
1568	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1569
1570	/** Shw: Root Nested paging table. */
1571	PGMPOOLKIND_ROOT_NESTED,
1572
1573	/** The last valid entry. */
1574	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1575	} PGMPOOLKIND;
1576
1577	/**
1578	* The access attributes of the page; only applies to big pages.
1579	*/
1580	typedef enum
1581	{
1582	PGMPOOLACCESS_DONTCARE = 0,
1583	PGMPOOLACCESS_USER_RW,
1584	PGMPOOLACCESS_USER_R,
1585	PGMPOOLACCESS_SUPERVISOR_RW,
1586	PGMPOOLACCESS_SUPERVISOR_R
1587	} PGMPOOLACCESS;
1588
1589	/**
1590	* The tracking data for a page in the pool.
1591	*/
1592	typedef struct PGMPOOLPAGE
1593	{
1594	/** AVL node code with the (R3) physical address of this page. */
1595	AVLOHCPHYSNODECORE Core;
1596	/** Pointer to the R3 mapping of the page. */
1597	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1598	R3PTRTYPE(void *) pvPageR3;
1599	#else
1600	R3R0PTRTYPE(void *) pvPageR3;
1601	#endif
1602	/** The guest physical address. */
1603	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1604	uint32_t Alignment0;
1605	#endif
1606	RTGCPHYS GCPhys;
1607	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1608	uint8_t enmKind;
1609	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1610	uint8_t enmAccess;
1611	/** The index of this page. */
1612	uint16_t idx;
1613	/** The next entry in the list this page currently resides in.
1614	* It's either in the free list or in the GCPhys hash. */
1615	uint16_t iNext;
1616	#ifdef PGMPOOL_WITH_USER_TRACKING
1617	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1618	uint16_t iUserHead;
1619	/** The number of present entries. */
1620	uint16_t cPresent;
1621	/** The first entry in the table which is present. */
1622	uint16_t iFirstPresent;
1623	#endif
1624	#ifdef PGMPOOL_WITH_MONITORING
1625	/** The number of modifications to the monitored page. */
1626	uint16_t cModifications;
1627	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1628	uint16_t iModifiedNext;
1629	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1630	uint16_t iModifiedPrev;
1631	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1632	uint16_t iMonitoredNext;
1633	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1634	uint16_t iMonitoredPrev;
1635	#endif
1636	#ifdef PGMPOOL_WITH_CACHE
1637	/** The next page in the age list. */
1638	uint16_t iAgeNext;
1639	/** The previous page in the age list. */
1640	uint16_t iAgePrev;
1641	#endif /* PGMPOOL_WITH_CACHE */
1642	/** Used to indicate that the page is zeroed. */
1643	bool fZeroed;
1644	/** Used to indicate that a PT has non-global entries. */
1645	bool fSeenNonGlobal;
1646	/** Used to indicate that we're monitoring writes to the guest page. */
1647	bool fMonitored;
1648	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1649	* (All pages are in the age list.) */
1650	bool fCached;
1651	/** This is used by the R3 access handlers when invoked by an async thread.
1652	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1653	bool volatile fReusedFlushPending;
1654	bool bPadding1;
1655
1656	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1657	uint32_t cLocked;
1658	uint32_t bPadding2;
1659	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1660	/** Pointer to a const pool page. */
1661	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1662
1663
1664	#ifdef PGMPOOL_WITH_CACHE
1665	/** The hash table size. */
1666	# define PGMPOOL_HASH_SIZE 0x40
1667	/** The hash function. */
1668	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1669	#endif
1670
1671
1672	/**
1673	* The shadow page pool instance data.
1674	*
1675	* It's all one big allocation made at init time, except for the
1676	* pages that is. The user nodes follows immediatly after the
1677	* page structures.
1678	*/
1679	typedef struct PGMPOOL
1680	{
1681	/** The VM handle - R3 Ptr. */
1682	PVMR3 pVMR3;
1683	/** The VM handle - R0 Ptr. */
1684	PVMR0 pVMR0;
1685	/** The VM handle - RC Ptr. */
1686	PVMRC pVMRC;
1687	/** The max pool size. This includes the special IDs. */
1688	uint16_t cMaxPages;
1689	/** The current pool size. */
1690	uint16_t cCurPages;
1691	/** The head of the free page list. */
1692	uint16_t iFreeHead;
1693	/* Padding. */
1694	uint16_t u16Padding;
1695	#ifdef PGMPOOL_WITH_USER_TRACKING
1696	/** Head of the chain of free user nodes. */
1697	uint16_t iUserFreeHead;
1698	/** The number of user nodes we've allocated. */
1699	uint16_t cMaxUsers;
1700	/** The number of present page table entries in the entire pool. */
1701	uint32_t cPresent;
1702	/** Pointer to the array of user nodes - RC pointer. */
1703	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1704	/** Pointer to the array of user nodes - R3 pointer. */
1705	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1706	/** Pointer to the array of user nodes - R0 pointer. */
1707	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1708	#endif /* PGMPOOL_WITH_USER_TRACKING */
1709	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1710	/** Head of the chain of free phys ext nodes. */
1711	uint16_t iPhysExtFreeHead;
1712	/** The number of user nodes we've allocated. */
1713	uint16_t cMaxPhysExts;
1714	/** Pointer to the array of physical xref extent - RC pointer. */
1715	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1716	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1717	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1718	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1719	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1720	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1721	#ifdef PGMPOOL_WITH_CACHE
1722	/** Hash table for GCPhys addresses. */
1723	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1724	/** The head of the age list. */
1725	uint16_t iAgeHead;
1726	/** The tail of the age list. */
1727	uint16_t iAgeTail;
1728	/** Set if the cache is enabled. */
1729	bool fCacheEnabled;
1730	#endif /* PGMPOOL_WITH_CACHE */
1731	#ifdef PGMPOOL_WITH_MONITORING
1732	/** Head of the list of modified pages. */
1733	uint16_t iModifiedHead;
1734	/** The current number of modified pages. */
1735	uint16_t cModifiedPages;
1736	/** Access handler, RC. */
1737	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1738	/** Access handler, R0. */
1739	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1740	/** Access handler, R3. */
1741	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1742	/** The access handler description (HC ptr). */
1743	R3PTRTYPE(const char *) pszAccessHandler;
1744	#endif /* PGMPOOL_WITH_MONITORING */
1745	/** The number of pages currently in use. */
1746	uint16_t cUsedPages;
1747	#ifdef VBOX_WITH_STATISTICS
1748	/** The high wather mark for cUsedPages. */
1749	uint16_t cUsedPagesHigh;
1750	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1751	/** Profiling pgmPoolAlloc(). */
1752	STAMPROFILEADV StatAlloc;
1753	/** Profiling pgmPoolClearAll(). */
1754	STAMPROFILE StatClearAll;
1755	/** Profiling pgmPoolFlushAllInt(). */
1756	STAMPROFILE StatFlushAllInt;
1757	/** Profiling pgmPoolFlushPage(). */
1758	STAMPROFILE StatFlushPage;
1759	/** Profiling pgmPoolFree(). */
1760	STAMPROFILE StatFree;
1761	/** Profiling time spent zeroing pages. */
1762	STAMPROFILE StatZeroPage;
1763	# ifdef PGMPOOL_WITH_USER_TRACKING
1764	/** Profiling of pgmPoolTrackDeref. */
1765	STAMPROFILE StatTrackDeref;
1766	/** Profiling pgmTrackFlushGCPhysPT. */
1767	STAMPROFILE StatTrackFlushGCPhysPT;
1768	/** Profiling pgmTrackFlushGCPhysPTs. */
1769	STAMPROFILE StatTrackFlushGCPhysPTs;
1770	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1771	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1772	/** Number of times we've been out of user records. */
1773	STAMCOUNTER StatTrackFreeUpOneUser;
1774	# endif
1775	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1776	/** Profiling deref activity related tracking GC physical pages. */
1777	STAMPROFILE StatTrackDerefGCPhys;
1778	/** Number of linear searches for a HCPhys in the ram ranges. */
1779	STAMCOUNTER StatTrackLinearRamSearches;
1780	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1781	STAMCOUNTER StamTrackPhysExtAllocFailures;
1782	# endif
1783	# ifdef PGMPOOL_WITH_MONITORING
1784	/** Profiling the RC/R0 access handler. */
1785	STAMPROFILE StatMonitorRZ;
1786	/** Times we've failed interpreting the instruction. */
1787	STAMCOUNTER StatMonitorRZEmulateInstr;
1788	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1789	STAMPROFILE StatMonitorRZFlushPage;
1790	/** Times we've detected fork(). */
1791	STAMCOUNTER StatMonitorRZFork;
1792	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1793	STAMPROFILE StatMonitorRZHandled;
1794	/** Times we've failed interpreting a patch code instruction. */
1795	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1796	/** Times we've failed interpreting a patch code instruction during flushing. */
1797	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1798	/** The number of times we've seen rep prefixes we can't handle. */
1799	STAMCOUNTER StatMonitorRZRepPrefix;
1800	/** Profiling the REP STOSD cases we've handled. */
1801	STAMPROFILE StatMonitorRZRepStosd;
1802
1803	/** Profiling the R3 access handler. */
1804	STAMPROFILE StatMonitorR3;
1805	/** Times we've failed interpreting the instruction. */
1806	STAMCOUNTER StatMonitorR3EmulateInstr;
1807	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1808	STAMPROFILE StatMonitorR3FlushPage;
1809	/** Times we've detected fork(). */
1810	STAMCOUNTER StatMonitorR3Fork;
1811	/** Profiling the R3 access we've handled (except REP STOSD). */
1812	STAMPROFILE StatMonitorR3Handled;
1813	/** The number of times we've seen rep prefixes we can't handle. */
1814	STAMCOUNTER StatMonitorR3RepPrefix;
1815	/** Profiling the REP STOSD cases we've handled. */
1816	STAMPROFILE StatMonitorR3RepStosd;
1817	/** The number of times we're called in an async thread an need to flush. */
1818	STAMCOUNTER StatMonitorR3Async;
1819	/** The high wather mark for cModifiedPages. */
1820	uint16_t cModifiedPagesHigh;
1821	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1822	# endif
1823	# ifdef PGMPOOL_WITH_CACHE
1824	/** The number of cache hits. */
1825	STAMCOUNTER StatCacheHits;
1826	/** The number of cache misses. */
1827	STAMCOUNTER StatCacheMisses;
1828	/** The number of times we've got a conflict of 'kind' in the cache. */
1829	STAMCOUNTER StatCacheKindMismatches;
1830	/** Number of times we've been out of pages. */
1831	STAMCOUNTER StatCacheFreeUpOne;
1832	/** The number of cacheable allocations. */
1833	STAMCOUNTER StatCacheCacheable;
1834	/** The number of uncacheable allocations. */
1835	STAMCOUNTER StatCacheUncacheable;
1836	# endif
1837	#elif HC_ARCH_BITS == 64
1838	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1839	#endif
1840	/** The AVL tree for looking up a page by its HC physical address. */
1841	AVLOHCPHYSTREE HCPhysTree;
1842	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1843	/** Array of pages. (cMaxPages in length)
1844	* The Id is the index into thist array.
1845	*/
1846	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1847	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1848
1849
1850	/** @def PGMPOOL_PAGE_2_PTR
1851	* Maps a pool page pool into the current context.
1852	*
1853	* @returns VBox status code.
1854	* @param pVM The VM handle.
1855	* @param pPage The pool page.
1856	*
1857	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1858	* small page window employeed by that function. Be careful.
1859	* @remark There is no need to assert on the result.
1860	*/
1861	#if defined(IN_RC)
1862	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1863	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1864	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1865	#elif defined(VBOX_STRICT)
1866	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1867	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1868	{
1869	Assert(pPage && pPage->pvPageR3);
1870	return pPage->pvPageR3;
1871	}
1872	#else
1873	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1874	#endif
1875
1876	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1877	* Maps a pool page pool into the current context.
1878	*
1879	* @returns VBox status code.
1880	* @param pPGM Pointer to the PGM instance data.
1881	* @param pPage The pool page.
1882	*
1883	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1884	* small page window employeed by that function. Be careful.
1885	* @remark There is no need to assert on the result.
1886	*/
1887	#if defined(IN_RC)
1888	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1889	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1890	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1891	#else
1892	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1893	#endif
1894
1895	/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1896	* Maps a pool page pool into the current context.
1897	*
1898	* @returns VBox status code.
1899	* @param pPGM Pointer to the PGMCPU instance data.
1900	* @param pPage The pool page.
1901	*
1902	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1903	* small page window employeed by that function. Be careful.
1904	* @remark There is no need to assert on the result.
1905	*/
1906	#if defined(IN_RC)
1907	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1908	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1909	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1910	#else
1911	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1912	#endif
1913
1914
1915	/** @name Per guest page tracking data.
1916	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1917	* is to use more bits for it and split it up later on. But for now we'll play
1918	* safe and change as little as possible.
1919	*
1920	* The 16-bit word has two parts:
1921	*
1922	* The first 14-bit forms the @a idx field. It is either the index of a page in
1923	* the shadow page pool, or and index into the extent list.
1924	*
1925	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
1926	* shadow page pool references to the page. If cRefs equals
1927	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1928	* (misnomer) table and not the shadow page pool.
1929	*
1930	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1931	* the 16-bit word.
1932	*
1933	* @{ */
1934	/** The shift count for getting to the cRefs part. */
1935	#define PGMPOOL_TD_CREFS_SHIFT 14
1936	/** The mask applied after shifting the tracking data down by
1937	* PGMPOOL_TD_CREFS_SHIFT. */
1938	#define PGMPOOL_TD_CREFS_MASK 0x3
1939	/** The cRef value used to indiciate that the idx is the head of a
1940	* physical cross reference list. */
1941	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1942	/** The shift used to get idx. */
1943	#define PGMPOOL_TD_IDX_SHIFT 0
1944	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1945	#define PGMPOOL_TD_IDX_MASK 0x3fff
1946	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1947	* simply too many mappings of this page. */
1948	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1949
1950	/** @def PGMPOOL_TD_MAKE
1951	* Makes a 16-bit tracking data word.
1952	*
1953	* @returns tracking data.
1954	* @param cRefs The @a cRefs field. Must be within bounds!
1955	* @param idx The @a idx field. Must also be within bounds! */
1956	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
1957
1958	/** @def PGMPOOL_TD_GET_CREFS
1959	* Get the @a cRefs field from a tracking data word.
1960	*
1961	* @returns The @a cRefs field
1962	* @param u16 The tracking data word. */
1963	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1964
1965	/** @def PGMPOOL_TD_GET_IDX
1966	* Get the @a idx field from a tracking data word.
1967	*
1968	* @returns The @a idx field
1969	* @param u16 The tracking data word. */
1970	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1971	/** @} */
1972
1973
1974	/**
1975	* Trees are using self relative offsets as pointers.
1976	* So, all its data, including the root pointer, must be in the heap for HC and GC
1977	* to have the same layout.
1978	*/
1979	typedef struct PGMTREES
1980	{
1981	/** Physical access handlers (AVL range+offsetptr tree). */
1982	AVLROGCPHYSTREE PhysHandlers;
1983	/** Virtual access handlers (AVL range + GC ptr tree). */
1984	AVLROGCPTRTREE VirtHandlers;
1985	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1986	AVLROGCPHYSTREE PhysToVirtHandlers;
1987	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1988	AVLROGCPTRTREE HyperVirtHandlers;
1989	} PGMTREES;
1990	/** Pointer to PGM trees. */
1991	typedef PGMTREES *PPGMTREES;
1992
1993
1994	/** @name Paging mode macros
1995	* @{ */
1996	#ifdef IN_RC
1997	# define PGM_CTX(a,b) a##RC##b
1998	# define PGM_CTX_STR(a,b) a "GC" b
1999	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2000	#else
2001	# ifdef IN_RING3
2002	# define PGM_CTX(a,b) a##R3##b
2003	# define PGM_CTX_STR(a,b) a "R3" b
2004	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2005	# else
2006	# define PGM_CTX(a,b) a##R0##b
2007	# define PGM_CTX_STR(a,b) a "R0" b
2008	# define PGM_CTX_DECL(type) VMMDECL(type)
2009	# endif
2010	#endif
2011
2012	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2013	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2014	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2015	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2016	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2017	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2018	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2019	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2020	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2021	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2022	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2023	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2024	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2025	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2026	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2027	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2028	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2029
2030	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2031	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2032	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2033	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2034	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2035	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2036	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2037	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2038	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2039	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2040	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2041	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2042	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2043	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2044	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2045	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2046	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2047
2048	/* Shw_Gst */
2049	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2050	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2051	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2052	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2053	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2054	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2055	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2056	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2057	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2058	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2059	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2060	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2061	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2062	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2063	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2064	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2065	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2066	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2067	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2068
2069	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2070	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2071	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2072	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2073	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2074	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2075	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2076	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2077	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2078	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2079	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2080	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2081	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2082	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2083	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2084	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2085	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2086	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2087	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2088	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2089	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2090	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2091	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2092	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2093	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2094	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2095	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2096	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2097	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2098	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2099	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2100	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2101	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2102	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2103	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2104	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2105	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2106
2107	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2108	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2109	/** @} */
2110
2111	/**
2112	* Data for each paging mode.
2113	*/
2114	typedef struct PGMMODEDATA
2115	{
2116	/** The guest mode type. */
2117	uint32_t uGstType;
2118	/** The shadow mode type. */
2119	uint32_t uShwType;
2120
2121	/** @name Function pointers for Shadow paging.
2122	* @{
2123	*/
2124	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2125	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2126	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2127	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2128
2129	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2130	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2131
2132	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2133	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2134	/** @} */
2135
2136	/** @name Function pointers for Guest paging.
2137	* @{
2138	*/
2139	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2140	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2141	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2142	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2143	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2144	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2145	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2146	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2147	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2148	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2149	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2150	/** @} */
2151
2152	/** @name Function pointers for Both Shadow and Guest paging.
2153	* @{
2154	*/
2155	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2156	/* no pfnR3BthTrap0eHandler */
2157	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2158	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2159	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2160	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2161	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2162	#ifdef VBOX_STRICT
2163	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2164	#endif
2165	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2166	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2167
2168	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2169	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2170	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2171	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2172	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2173	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2174	#ifdef VBOX_STRICT
2175	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2176	#endif
2177	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2178	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2179
2180	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2181	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2182	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2183	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2184	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2185	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2186	#ifdef VBOX_STRICT
2187	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2188	#endif
2189	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2190	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2191	/** @} */
2192	} PGMMODEDATA, *PPGMMODEDATA;
2193
2194
2195
2196	/**
2197	* Converts a PGM pointer into a VM pointer.
2198	* @returns Pointer to the VM structure the PGM is part of.
2199	* @param pPGM Pointer to PGM instance data.
2200	*/
2201	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2202
2203	/**
2204	* PGM Data (part of VM)
2205	*/
2206	typedef struct PGM
2207	{
2208	/** Offset to the VM structure. */
2209	RTINT offVM;
2210	/** Offset of the PGMCPU structure relative to VMCPU. */
2211	RTINT offVCpuPGM;
2212
2213	/** @cfgm{RamPreAlloc, boolean, false}
2214	* Indicates whether the base RAM should all be allocated before starting
2215	* the VM (default), or if it should be allocated when first written to.
2216	*/
2217	bool fRamPreAlloc;
2218	/** Alignment padding. */
2219	bool afAlignment0[11];
2220
2221	/*
2222	* This will be redefined at least two more times before we're done, I'm sure.
2223	* The current code is only to get on with the coding.
2224	* - 2004-06-10: initial version, bird.
2225	* - 2004-07-02: 1st time, bird.
2226	* - 2004-10-18: 2nd time, bird.
2227	* - 2005-07-xx: 3rd time, bird.
2228	*/
2229
2230	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2231	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2232	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2233	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2234
2235	/** The host paging mode. (This is what SUPLib reports.) */
2236	SUPPAGINGMODE enmHostMode;
2237
2238	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2239	RTGCPHYS GCPhys4MBPSEMask;
2240
2241	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2242	* This is sorted by physical address and contains no overlapping ranges. */
2243	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2244	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2245	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2246	/** RC pointer corresponding to PGM::pRamRangesR3. */
2247	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2248	RTRCPTR alignment4; /*< structure alignment. /
2249
2250	/** Pointer to the list of ROM ranges - for R3.
2251	* This is sorted by physical address and contains no overlapping ranges. */
2252	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2253	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2254	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2255	/** RC pointer corresponding to PGM::pRomRangesR3. */
2256	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2257	/** Alignment padding. */
2258	RTRCPTR GCPtrPadding2;
2259
2260	/** Pointer to the list of MMIO2 ranges - for R3.
2261	* Registration order. */
2262	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2263
2264	/** PGM offset based trees - R3 Ptr. */
2265	R3PTRTYPE(PPGMTREES) pTreesR3;
2266	/** PGM offset based trees - R0 Ptr. */
2267	R0PTRTYPE(PPGMTREES) pTreesR0;
2268	/** PGM offset based trees - RC Ptr. */
2269	RCPTRTYPE(PPGMTREES) pTreesRC;
2270
2271	/** Linked list of GC mappings - for RC.
2272	* The list is sorted ascending on address.
2273	*/
2274	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2275	/** Linked list of GC mappings - for HC.
2276	* The list is sorted ascending on address.
2277	*/
2278	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2279	/** Linked list of GC mappings - for R0.
2280	* The list is sorted ascending on address.
2281	*/
2282	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2283
2284	/** Pointer to the 5 page CR3 content mapping.
2285	* The first page is always the CR3 (in some form) while the 4 other pages
2286	* are used of the PDs in PAE mode. */
2287	RTGCPTR GCPtrCR3Mapping;
2288	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2289	uint32_t u32Alignment;
2290	#endif
2291
2292	/** Indicates that PGMR3FinalizeMappings has been called and that further
2293	* PGMR3MapIntermediate calls will be rejected. */
2294	bool fFinalizedMappings;
2295	/** If set no conflict checks are required. (boolean) */
2296	bool fMappingsFixed;
2297	/** If set, then no mappings are put into the shadow page table. (boolean) */
2298	bool fDisableMappings;
2299	/** Size of fixed mapping */
2300	uint32_t cbMappingFixed;
2301	/** Base address (GC) of fixed mapping */
2302	RTGCPTR GCPtrMappingFixed;
2303	/** The address of the previous RAM range mapping. */
2304	RTGCPTR GCPtrPrevRamRangeMapping;
2305
2306	/** @name Intermediate Context
2307	* @{ */
2308	/** Pointer to the intermediate page directory - Normal. */
2309	R3PTRTYPE(PX86PD) pInterPD;
2310	/** Pointer to the intermedate page tables - Normal.
2311	* There are two page tables, one for the identity mapping and one for
2312	* the host context mapping (of the core code). */
2313	R3PTRTYPE(PX86PT) apInterPTs[2];
2314	/** Pointer to the intermedate page tables - PAE. */
2315	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2316	/** Pointer to the intermedate page directory - PAE. */
2317	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2318	/** Pointer to the intermedate page directory - PAE. */
2319	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2320	/** Pointer to the intermedate page-map level 4 - AMD64. */
2321	R3PTRTYPE(PX86PML4) pInterPaePML4;
2322	/** Pointer to the intermedate page directory - AMD64. */
2323	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2324	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2325	RTHCPHYS HCPhysInterPD;
2326	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2327	RTHCPHYS HCPhysInterPaePDPT;
2328	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2329	RTHCPHYS HCPhysInterPaePML4;
2330	/** @} */
2331
2332	/** Base address of the dynamic page mapping area.
2333	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2334	*/
2335	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2336	/** The index of the last entry used in the dynamic page mapping area. */
2337	RTUINT iDynPageMapLast;
2338	/** Cache containing the last entries in the dynamic page mapping area.
2339	* The cache size is covering half of the mapping area. */
2340	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2341	/** Keep a lock counter for the full (!) mapping area. */
2342	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2343
2344	/** The address of the ring-0 mapping cache if we're making use of it. */
2345	RTR0PTR pvR0DynMapUsed;
2346
2347	/** PGM critical section.
2348	* This protects the physical & virtual access handlers, ram ranges,
2349	* and the page flag updating (some of it anyway).
2350	*/
2351	PDMCRITSECT CritSect;
2352
2353	/** Pointer to SHW+GST mode data (function pointers).
2354	* The index into this table is made up from */
2355	R3PTRTYPE(PPGMMODEDATA) paModeData;
2356
2357	/** Shadow Page Pool - R3 Ptr. */
2358	R3PTRTYPE(PPGMPOOL) pPoolR3;
2359	/** Shadow Page Pool - R0 Ptr. */
2360	R0PTRTYPE(PPGMPOOL) pPoolR0;
2361	/** Shadow Page Pool - RC Ptr. */
2362	RCPTRTYPE(PPGMPOOL) pPoolRC;
2363
2364	/** We're not in a state which permits writes to guest memory.
2365	* (Only used in strict builds.) */
2366	bool fNoMorePhysWrites;
2367
2368	/**
2369	* Data associated with managing the ring-3 mappings of the allocation chunks.
2370	*/
2371	struct
2372	{
2373	/** The chunk tree, ordered by chunk id. */
2374	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2375	R3PTRTYPE(PAVLU32NODECORE) pTree;
2376	#else
2377	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2378	#endif
2379	/** The chunk mapping TLB. */
2380	PGMCHUNKR3MAPTLB Tlb;
2381	/** The number of mapped chunks. */
2382	uint32_t c;
2383	/** The maximum number of mapped chunks.
2384	* @cfgm PGM/MaxRing3Chunks */
2385	uint32_t cMax;
2386	/** The chunk age tree, ordered by ageing sequence number. */
2387	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2388	/** The current time. */
2389	uint32_t iNow;
2390	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2391	uint32_t AgeingCountdown;
2392	} ChunkR3Map;
2393
2394	/**
2395	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2396	*/
2397	PGMPAGER3MAPTLB PhysTlbHC;
2398
2399	/** @name The zero page.
2400	* @{ */
2401	/** The host physical address of the zero page. */
2402	RTHCPHYS HCPhysZeroPg;
2403	/** The ring-3 mapping of the zero page. */
2404	RTR3PTR pvZeroPgR3;
2405	/** The ring-0 mapping of the zero page. */
2406	RTR0PTR pvZeroPgR0;
2407	/** The GC mapping of the zero page. */
2408	RTGCPTR pvZeroPgRC;
2409	#if GC_ARCH_BITS != 32
2410	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2411	#endif
2412	/** @}*/
2413
2414	/** The number of handy pages. */
2415	uint32_t cHandyPages;
2416	/**
2417	* Array of handy pages.
2418	*
2419	* This array is used in a two way communication between pgmPhysAllocPage
2420	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2421	* an intermediary.
2422	*
2423	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2424	* (The current size of 32 pages, means 128 KB of handy memory.)
2425	*/
2426	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2427
2428	/** @name Error injection.
2429	* @{ */
2430	/** Inject handy page allocation errors pretending we're completely out of
2431	* memory. */
2432	bool volatile fErrInjHandyPages;
2433	/** Padding. */
2434	bool afReserved[7];
2435	/** @} */
2436
2437	/** @name Release Statistics
2438	* @{ */
2439	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2440	uint32_t cPrivatePages; /*< The number of private pages. /
2441	uint32_t cSharedPages; /*< The number of shared pages. /
2442	uint32_t cZeroPages; /*< The number of zero backed pages. /
2443
2444	/** The number of times we were forced to change the hypervisor region location. */
2445	STAMCOUNTER cRelocations;
2446	/** @} */
2447
2448	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2449	/* R3 only: */
2450	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2451	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2452
2453	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2454	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2455	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2456	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2457	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2458	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2459	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2460	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2461	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2462	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2463	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2464	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2465	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2466	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2467	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2468	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2469	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2470	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2471	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2472	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2473	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2474	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2475
2476	/* RC only: */
2477	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache misses /
2478	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache hits /
2479	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2480	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2481
2482	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2483	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2484	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2485	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2486	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2487	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2488	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2489	# endif
2490	#endif
2491	} PGM;
2492	/** Pointer to the PGM instance data. */
2493	typedef PGM *PPGM;
2494
2495
2496	/**
2497	* Converts a PGMCPU pointer into a VM pointer.
2498	* @returns Pointer to the VM structure the PGM is part of.
2499	* @param pPGM Pointer to PGMCPU instance data.
2500	*/
2501	#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2502
2503	/**
2504	* Converts a PGMCPU pointer into a PGM pointer.
2505	* @returns Pointer to the VM structure the PGM is part of.
2506	* @param pPGM Pointer to PGMCPU instance data.
2507	*/
2508	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2509
2510	/**
2511	* PGMCPU Data (part of VMCPU).
2512	*/
2513	typedef struct PGMCPU
2514	{
2515	/** Offset to the VM structure. */
2516	RTINT offVM;
2517	/** Offset to the VMCPU structure. */
2518	RTINT offVCpu;
2519	/** Offset of the PGM structure relative to VMCPU. */
2520	RTINT offPGM;
2521	RTINT uPadding0; /*< structure size alignment. /
2522
2523	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2524	/** Automatically tracked physical memory mapping set.
2525	* Ring-0 and strict raw-mode builds. */
2526	PGMMAPSET AutoSet;
2527	#endif
2528
2529	/** A20 gate mask.
2530	* Our current approach to A20 emulation is to let REM do it and don't bother
2531	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2532	* But whould need arrise, we'll subject physical addresses to this mask. */
2533	RTGCPHYS GCPhysA20Mask;
2534	/** A20 gate state - boolean! */
2535	bool fA20Enabled;
2536
2537	/** What needs syncing (PGM_SYNC_*).
2538	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2539	* PGMFlushTLB, and PGMR3Load. */
2540	RTUINT fSyncFlags;
2541
2542	/** The shadow paging mode. */
2543	PGMMODE enmShadowMode;
2544	/** The guest paging mode. */
2545	PGMMODE enmGuestMode;
2546
2547	/** The current physical address representing in the guest CR3 register. */
2548	RTGCPHYS GCPhysCR3;
2549
2550	/** @name 32-bit Guest Paging.
2551	* @{ */
2552	/** The guest's page directory, R3 pointer. */
2553	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2554	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2555	/** The guest's page directory, R0 pointer. */
2556	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2557	#endif
2558	/** The guest's page directory, static RC mapping. */
2559	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2560	/** @} */
2561
2562	/** @name PAE Guest Paging.
2563	* @{ */
2564	/** The guest's page directory pointer table, static RC mapping. */
2565	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2566	/** The guest's page directory pointer table, R3 pointer. */
2567	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2568	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2569	/** The guest's page directory pointer table, R0 pointer. */
2570	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2571	#endif
2572
2573	/** The guest's page directories, R3 pointers.
2574	* These are individual pointers and don't have to be adjecent.
2575	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2576	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2577	/** The guest's page directories, R0 pointers.
2578	* Same restrictions as apGstPaePDsR3. */
2579	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2580	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2581	#endif
2582	/** The guest's page directories, static GC mapping.
2583	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2584	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2585	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2586	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2587	RTGCPHYS aGCPhysGstPaePDs[4];
2588	/** The physical addresses of the monitored guest page directories (PAE). */
2589	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2590	/** @} */
2591
2592	/** @name AMD64 Guest Paging.
2593	* @{ */
2594	/** The guest's page directory pointer table, R3 pointer. */
2595	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2596	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2597	/** The guest's page directory pointer table, R0 pointer. */
2598	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2599	#endif
2600	/** @} */
2601
2602	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2603	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2604	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2605	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2606	/** Pointer to the page of the current active CR3 - RC Ptr. */
2607	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2608	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2609	uint32_t iShwUser;
2610	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2611	uint32_t iShwUserTable;
2612	# if HC_ARCH_BITS == 64
2613	RTRCPTR alignment6; /*< structure size alignment. /
2614	# endif
2615	/** @} */
2616
2617	/** @name Function pointers for Shadow paging.
2618	* @{
2619	*/
2620	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2621	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2622	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2623	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2624
2625	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2626	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2627
2628	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2629	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2630
2631	/** @} */
2632
2633	/** @name Function pointers for Guest paging.
2634	* @{
2635	*/
2636	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2637	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2638	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2639	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2640	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2641	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2642	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2643	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2644	#if HC_ARCH_BITS == 64
2645	RTRCPTR alignment3; /*< structure size alignment. /
2646	#endif
2647
2648	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2649	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2650	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2651	/** @} */
2652
2653	/** @name Function pointers for Both Shadow and Guest paging.
2654	* @{
2655	*/
2656	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2657	/* no pfnR3BthTrap0eHandler */
2658	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2659	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2660	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2661	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2662	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2663	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2664	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2665	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2666
2667	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2668	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2669	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2670	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2671	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2672	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2673	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2674	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2675	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2676
2677	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2678	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2679	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2680	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2681	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2682	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2683	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2684	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2685	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2686	#if HC_ARCH_BITS == 64
2687	RTRCPTR alignment2; /*< structure size alignment. /
2688	#endif
2689	/** @} */
2690
2691	/** For saving stack space, the disassembler state is allocated here instead of
2692	* on the stack.
2693	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2694	union
2695	{
2696	/** The disassembler scratch space. */
2697	DISCPUSTATE DisState;
2698	/** Padding. */
2699	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2700	};
2701
2702	/** @name Release Statistics
2703	* @{ */
2704	/** The number of times the guest has switched mode since last reset or statistics reset. */
2705	STAMCOUNTER cGuestModeChanges;
2706	/** @} */
2707
2708	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2709	/** @name Statistics
2710	* @{ */
2711	/** RC: Which statistic this \#PF should be attributed to. */
2712	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2713	RTRCPTR padding0;
2714	/** R0: Which statistic this \#PF should be attributed to. */
2715	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2716	RTR0PTR padding1;
2717
2718	/* Common */
2719	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2720	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2721
2722	/* R0 only: */
2723	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2724	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2725	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2726	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2727	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2728	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2729	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2730	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2731	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2732	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2733	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2734	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2735	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2736	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2737	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2738	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2739	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2740	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2741	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2742	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2743	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2744	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2745	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2746	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2747	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2748	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2749
2750	/* RZ only: */
2751	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2752	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2753	STAMPROFILE StatRZTrap0eTimeSyncPT;
2754	STAMPROFILE StatRZTrap0eTimeMapping;
2755	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2756	STAMPROFILE StatRZTrap0eTimeHandlers;
2757	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2758	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2759	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2760	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2761	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2762	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2763	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2764	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2765	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2766	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2767	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2768	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2769	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2770	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2771	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2772	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2773	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2774	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2775	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2776	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2777	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2778	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2779	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2780	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2781	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2782	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2783	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2784	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2785	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2786	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2787	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2788	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2789	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2790	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2791	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2792	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2793	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2794	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2795	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2796	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2797	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2798	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2799	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2800
2801	/* HC - R3 and (maybe) R0: */
2802
2803	/* RZ & R3: */
2804	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2805	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2806	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2807	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2808	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2809	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2810	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2811	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2812	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2813	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2814	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2815	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2816	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2817	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2818	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2819	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2820	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2821	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2822	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2823	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2824	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2825	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2826	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
2827	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2828	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2829	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2830	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2831	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2832	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2833	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2834	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2835	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2836	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2837	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2838	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2839	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2840	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2841	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2842	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2843	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2844	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2845	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2846	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2847	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2848
2849	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2850	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2851	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2852	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2853	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2854	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2855	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2856	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2857	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2858	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2859	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2860	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2861	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2862	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2863	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2864	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2865	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2866	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2867	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2868	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2869	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2870	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2871	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2872	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2873	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2874	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2875	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2876	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2877	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2878	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2879	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2880	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2881	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2882	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2883	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2884	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2885	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2886	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2887	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2888	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2889	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2890	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2891	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2892	/** @} */
2893	#endif /* VBOX_WITH_STATISTICS */
2894	} PGMCPU;
2895	/** Pointer to the per-cpu PGM data. */
2896	typedef PGMCPU *PPGMCPU;
2897
2898
2899	/** @name PGM::fSyncFlags Flags
2900	* @{
2901	*/
2902	/** Updates the virtual access handler state bit in PGMPAGE. */
2903	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2904	/** Always sync CR3. */
2905	#define PGM_SYNC_ALWAYS RT_BIT(1)
2906	/** Check monitoring on next CR3 (re)load and invalidate page.
2907	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2908	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2909	/** Check guest mapping in SyncCR3. */
2910	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2911	/** Clear the page pool (a light weight flush). */
2912	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2913	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2914	/** @} */
2915
2916
2917	RT_C_DECLS_BEGIN
2918
2919	int pgmLock(PVM pVM);
2920	void pgmUnlock(PVM pVM);
2921
2922	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2923	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2924	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2925	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2926	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2927
2928	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2929	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2930	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2931	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2932	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2933	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2934	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2935	#else
2936	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2937	#endif
2938	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2939
2940
2941	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2942	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2943	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2944	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2945	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2946	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2947	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2948	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2949	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2950	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2951	#ifdef IN_RING3
2952	void pgmR3PhysRelinkRamRanges(PVM pVM);
2953	int pgmR3PhysRamPreAllocate(PVM pVM);
2954	int pgmR3PhysRamReset(PVM pVM);
2955	int pgmR3PhysRomReset(PVM pVM);
2956	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2957
2958	int pgmR3PoolInit(PVM pVM);
2959	void pgmR3PoolRelocate(PVM pVM);
2960	void pgmR3PoolReset(PVM pVM);
2961
2962	#endif /* IN_RING3 */
2963	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2964	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2965	#endif
2966	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
2967
2968	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
2969	{
2970	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
2971	}
2972
2973	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2974	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2975	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2976	void pgmPoolClearAll(PVM pVM);
2977	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
2978	int pgmPoolSyncCR3(PVMCPU pVCpu);
2979	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
2980	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2981	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2982	#ifdef PGMPOOL_WITH_MONITORING
2983	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2984	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2985	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2986	#endif
2987
2988	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
2989	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
2990
2991	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2992	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
2993	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2994	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2995
2996	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2997	#ifndef IN_RC
2998	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2999	#endif
3000	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3001
3002	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3003	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3004	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3005	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3006
3007	RT_C_DECLS_END
3008
3009
3010	/**
3011	* Gets the PGMRAMRANGE structure for a guest page.
3012	*
3013	* @returns Pointer to the RAM range on success.
3014	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3015	*
3016	* @param pPGM PGM handle.
3017	* @param GCPhys The GC physical address.
3018	*/
3019	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3020	{
3021	/*
3022	* Optimize for the first range.
3023	*/
3024	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3025	RTGCPHYS off = GCPhys - pRam->GCPhys;
3026	if (RT_UNLIKELY(off >= pRam->cb))
3027	{
3028	do
3029	{
3030	pRam = pRam->CTX_SUFF(pNext);
3031	if (RT_UNLIKELY(!pRam))
3032	break;
3033	off = GCPhys - pRam->GCPhys;
3034	} while (off >= pRam->cb);
3035	}
3036	return pRam;
3037	}
3038
3039
3040	/**
3041	* Gets the PGMPAGE structure for a guest page.
3042	*
3043	* @returns Pointer to the page on success.
3044	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3045	*
3046	* @param pPGM PGM handle.
3047	* @param GCPhys The GC physical address.
3048	*/
3049	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3050	{
3051	/*
3052	* Optimize for the first range.
3053	*/
3054	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3055	RTGCPHYS off = GCPhys - pRam->GCPhys;
3056	if (RT_UNLIKELY(off >= pRam->cb))
3057	{
3058	do
3059	{
3060	pRam = pRam->CTX_SUFF(pNext);
3061	if (RT_UNLIKELY(!pRam))
3062	return NULL;
3063	off = GCPhys - pRam->GCPhys;
3064	} while (off >= pRam->cb);
3065	}
3066	return &pRam->aPages[off >> PAGE_SHIFT];
3067	}
3068
3069
3070	/**
3071	* Gets the PGMPAGE structure for a guest page.
3072	*
3073	* Old Phys code: Will make sure the page is present.
3074	*
3075	* @returns VBox status code.
3076	* @retval VINF_SUCCESS and a valid *ppPage on success.
3077	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3078	*
3079	* @param pPGM PGM handle.
3080	* @param GCPhys The GC physical address.
3081	* @param ppPage Where to store the page poitner on success.
3082	*/
3083	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3084	{
3085	/*
3086	* Optimize for the first range.
3087	*/
3088	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3089	RTGCPHYS off = GCPhys - pRam->GCPhys;
3090	if (RT_UNLIKELY(off >= pRam->cb))
3091	{
3092	do
3093	{
3094	pRam = pRam->CTX_SUFF(pNext);
3095	if (RT_UNLIKELY(!pRam))
3096	{
3097	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3098	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3099	}
3100	off = GCPhys - pRam->GCPhys;
3101	} while (off >= pRam->cb);
3102	}
3103	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3104	return VINF_SUCCESS;
3105	}
3106
3107
3108
3109
3110	/**
3111	* Gets the PGMPAGE structure for a guest page.
3112	*
3113	* Old Phys code: Will make sure the page is present.
3114	*
3115	* @returns VBox status code.
3116	* @retval VINF_SUCCESS and a valid *ppPage on success.
3117	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3118	*
3119	* @param pPGM PGM handle.
3120	* @param GCPhys The GC physical address.
3121	* @param ppPage Where to store the page poitner on success.
3122	* @param ppRamHint Where to read and store the ram list hint.
3123	* The caller initializes this to NULL before the call.
3124	*/
3125	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3126	{
3127	RTGCPHYS off;
3128	PPGMRAMRANGE pRam = *ppRamHint;
3129	if ( !pRam
3130	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3131	{
3132	pRam = pPGM->CTX_SUFF(pRamRanges);
3133	off = GCPhys - pRam->GCPhys;
3134	if (RT_UNLIKELY(off >= pRam->cb))
3135	{
3136	do
3137	{
3138	pRam = pRam->CTX_SUFF(pNext);
3139	if (RT_UNLIKELY(!pRam))
3140	{
3141	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3142	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3143	}
3144	off = GCPhys - pRam->GCPhys;
3145	} while (off >= pRam->cb);
3146	}
3147	*ppRamHint = pRam;
3148	}
3149	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3150	return VINF_SUCCESS;
3151	}
3152
3153
3154	/**
3155	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3156	*
3157	* @returns Pointer to the page on success.
3158	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3159	*
3160	* @param pPGM PGM handle.
3161	* @param GCPhys The GC physical address.
3162	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3163	*/
3164	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3165	{
3166	/*
3167	* Optimize for the first range.
3168	*/
3169	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3170	RTGCPHYS off = GCPhys - pRam->GCPhys;
3171	if (RT_UNLIKELY(off >= pRam->cb))
3172	{
3173	do
3174	{
3175	pRam = pRam->CTX_SUFF(pNext);
3176	if (RT_UNLIKELY(!pRam))
3177	return NULL;
3178	off = GCPhys - pRam->GCPhys;
3179	} while (off >= pRam->cb);
3180	}
3181	*ppRam = pRam;
3182	return &pRam->aPages[off >> PAGE_SHIFT];
3183	}
3184
3185
3186	/**
3187	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3188	*
3189	* @returns Pointer to the page on success.
3190	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3191	*
3192	* @param pPGM PGM handle.
3193	* @param GCPhys The GC physical address.
3194	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3195	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3196	*/
3197	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3198	{
3199	/*
3200	* Optimize for the first range.
3201	*/
3202	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3203	RTGCPHYS off = GCPhys - pRam->GCPhys;
3204	if (RT_UNLIKELY(off >= pRam->cb))
3205	{
3206	do
3207	{
3208	pRam = pRam->CTX_SUFF(pNext);
3209	if (RT_UNLIKELY(!pRam))
3210	{
3211	ppRam = NULL; / Shut up silly GCC warnings. */
3212	ppPage = NULL; / ditto */
3213	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3214	}
3215	off = GCPhys - pRam->GCPhys;
3216	} while (off >= pRam->cb);
3217	}
3218	*ppRam = pRam;
3219	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3220	return VINF_SUCCESS;
3221	}
3222
3223
3224	/**
3225	* Convert GC Phys to HC Phys.
3226	*
3227	* @returns VBox status.
3228	* @param pPGM PGM handle.
3229	* @param GCPhys The GC physical address.
3230	* @param pHCPhys Where to store the corresponding HC physical address.
3231	*
3232	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3233	* Avoid when writing new code!
3234	*/
3235	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3236	{
3237	PPGMPAGE pPage;
3238	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3239	if (RT_FAILURE(rc))
3240	return rc;
3241	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3242	return VINF_SUCCESS;
3243	}
3244
3245	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3246
3247	/**
3248	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3249	* optimizes access to pages already in the set.
3250	*
3251	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3252	* @param pPGM Pointer to the PVM instance data.
3253	* @param HCPhys The physical address of the page.
3254	* @param ppv Where to store the mapping address.
3255	*/
3256	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3257	{
3258	PVM pVM = PGM2VM(pPGM);
3259	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3260	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3261
3262	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3263	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3264	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3265
3266	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3267	unsigned iEntry = pSet->aiHashTable[iHash];
3268	if ( iEntry < pSet->cEntries
3269	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3270	{
3271	*ppv = pSet->aEntries[iEntry].pvPage;
3272	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3273	}
3274	else
3275	{
3276	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3277	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3278	}
3279
3280	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3281	return VINF_SUCCESS;
3282	}
3283
3284
3285	/**
3286	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3287	* access to pages already in the set.
3288	*
3289	* @returns See PGMDynMapGCPage.
3290	* @param pPGM Pointer to the PVM instance data.
3291	* @param HCPhys The physical address of the page.
3292	* @param ppv Where to store the mapping address.
3293	*/
3294	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3295	{
3296	PVM pVM = PGM2VM(pPGM);
3297	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3298
3299	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3300	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3301
3302	/*
3303	* Get the ram range.
3304	*/
3305	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3306	RTGCPHYS off = GCPhys - pRam->GCPhys;
3307	if (RT_UNLIKELY(off >= pRam->cb
3308	/** @todo \|\| page state stuff */))
3309	{
3310	/* This case is not counted into StatR0DynMapGCPageInl. */
3311	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3312	return PGMDynMapGCPage(pVM, GCPhys, ppv);
3313	}
3314
3315	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3316	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3317
3318	/*
3319	* pgmR0DynMapHCPageInlined with out stats.
3320	*/
3321	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3322	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3323	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3324
3325	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3326	unsigned iEntry = pSet->aiHashTable[iHash];
3327	if ( iEntry < pSet->cEntries
3328	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3329	{
3330	*ppv = pSet->aEntries[iEntry].pvPage;
3331	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3332	}
3333	else
3334	{
3335	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3336	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3337	}
3338
3339	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3340	return VINF_SUCCESS;
3341	}
3342
3343
3344	/**
3345	* Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3346	* access to pages already in the set.
3347	*
3348	* @returns See PGMDynMapGCPage.
3349	* @param pPGM Pointer to the PVM instance data.
3350	* @param HCPhys The physical address of the page.
3351	* @param ppv Where to store the mapping address.
3352	*/
3353	DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3354	{
3355	PVM pVM = PGM2VM(pPGM);
3356	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3357
3358	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3359
3360	/*
3361	* Get the ram range.
3362	*/
3363	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3364	RTGCPHYS off = GCPhys - pRam->GCPhys;
3365	if (RT_UNLIKELY(off >= pRam->cb
3366	/** @todo \|\| page state stuff */))
3367	{
3368	/* This case is not counted into StatR0DynMapGCPageInl. */
3369	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3370	return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3371	}
3372
3373	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3374	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3375
3376	/*
3377	* pgmR0DynMapHCPageInlined with out stats.
3378	*/
3379	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3380	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3381	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3382
3383	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3384	unsigned iEntry = pSet->aiHashTable[iHash];
3385	if ( iEntry < pSet->cEntries
3386	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3387	{
3388	ppv = (void )((uintptr_t)pSet->aEntries[iEntry].pvPage \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3389	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3390	}
3391	else
3392	{
3393	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3394	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3395	ppv = (void )((uintptr_t)*ppv \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3396	}
3397
3398	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3399	return VINF_SUCCESS;
3400	}
3401
3402	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3403	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3404
3405	/**
3406	* Maps the page into current context (RC and maybe R0).
3407	*
3408	* @returns pointer to the mapping.
3409	* @param pVM Pointer to the PGM instance data.
3410	* @param pPage The page.
3411	*/
3412	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3413	{
3414	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3415	{
3416	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3417	void *pv;
3418	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3419	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3420	# else
3421	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3422	# endif
3423	return pv;
3424	}
3425	AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3426	}
3427
3428	/**
3429	* Temporarily maps one host page specified by HC physical address, returning
3430	* pointer within the page.
3431	*
3432	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3433	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3434	*
3435	* @returns The address corresponding to HCPhys.
3436	* @param pPGM Pointer to the PVM instance data.
3437	* @param HCPhys HC Physical address of the page.
3438	*/
3439	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3440	{
3441	void *pv;
3442	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3443	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3444	# else
3445	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3446	# endif
3447	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3448	return pv;
3449	}
3450
3451	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3452	#ifndef IN_RC
3453
3454	/**
3455	* Queries the Physical TLB entry for a physical guest page,
3456	* attempting to load the TLB entry if necessary.
3457	*
3458	* @returns VBox status code.
3459	* @retval VINF_SUCCESS on success
3460	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3461	*
3462	* @param pPGM The PGM instance handle.
3463	* @param GCPhys The address of the guest page.
3464	* @param ppTlbe Where to store the pointer to the TLB entry.
3465	*/
3466	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3467	{
3468	int rc;
3469	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3470	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3471	{
3472	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3473	rc = VINF_SUCCESS;
3474	}
3475	else
3476	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3477	*ppTlbe = pTlbe;
3478	return rc;
3479	}
3480
3481
3482	/**
3483	* Queries the Physical TLB entry for a physical guest page,
3484	* attempting to load the TLB entry if necessary.
3485	*
3486	* @returns VBox status code.
3487	* @retval VINF_SUCCESS on success
3488	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3489	*
3490	* @param pPGM The PGM instance handle.
3491	* @param pPage Pointer to the PGMPAGE structure corresponding to
3492	* GCPhys.
3493	* @param GCPhys The address of the guest page.
3494	* @param ppTlbe Where to store the pointer to the TLB entry.
3495	*/
3496	DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3497	{
3498	int rc;
3499	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3500	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3501	{
3502	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3503	rc = VINF_SUCCESS;
3504	}
3505	else
3506	rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3507	*ppTlbe = pTlbe;
3508	return rc;
3509	}
3510
3511	#endif /* !IN_RC */
3512
3513	/**
3514	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3515	* Takes PSE-36 into account.
3516	*
3517	* @returns guest physical address
3518	* @param pPGM Pointer to the PGM instance data.
3519	* @param Pde Guest Pde
3520	*/
3521	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3522	{
3523	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3524	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3525
3526	return GCPhys & pPGM->GCPhys4MBPSEMask;
3527	}
3528
3529
3530	/**
3531	* Gets the page directory entry for the specified address (32-bit paging).
3532	*
3533	* @returns The page directory entry in question.
3534	* @param pPGM Pointer to the PGM instance data.
3535	* @param GCPtr The address.
3536	*/
3537	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3538	{
3539	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3540	PCX86PD pGuestPD = NULL;
3541	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3542	if (RT_FAILURE(rc))
3543	{
3544	X86PDE ZeroPde = {0};
3545	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3546	}
3547	#else
3548	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3549	# ifdef IN_RING3
3550	if (!pGuestPD)
3551	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3552	# endif
3553	#endif
3554	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3555	}
3556
3557
3558	/**
3559	* Gets the address of a specific page directory entry (32-bit paging).
3560	*
3561	* @returns Pointer the page directory entry in question.
3562	* @param pPGM Pointer to the PGM instance data.
3563	* @param GCPtr The address.
3564	*/
3565	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3566	{
3567	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3568	PX86PD pGuestPD = NULL;
3569	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3570	AssertRCReturn(rc, NULL);
3571	#else
3572	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3573	# ifdef IN_RING3
3574	if (!pGuestPD)
3575	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3576	# endif
3577	#endif
3578	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3579	}
3580
3581
3582	/**
3583	* Gets the address the guest page directory (32-bit paging).
3584	*
3585	* @returns Pointer the page directory entry in question.
3586	* @param pPGM Pointer to the PGM instance data.
3587	*/
3588	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3589	{
3590	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3591	PX86PD pGuestPD = NULL;
3592	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3593	AssertRCReturn(rc, NULL);
3594	#else
3595	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3596	# ifdef IN_RING3
3597	if (!pGuestPD)
3598	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3599	# endif
3600	#endif
3601	return pGuestPD;
3602	}
3603
3604
3605	/**
3606	* Gets the guest page directory pointer table.
3607	*
3608	* @returns Pointer to the page directory in question.
3609	* @returns NULL if the page directory is not present or on an invalid page.
3610	* @param pPGM Pointer to the PGM instance data.
3611	*/
3612	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3613	{
3614	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3615	PX86PDPT pGuestPDPT = NULL;
3616	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3617	AssertRCReturn(rc, NULL);
3618	#else
3619	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3620	# ifdef IN_RING3
3621	if (!pGuestPDPT)
3622	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3623	# endif
3624	#endif
3625	return pGuestPDPT;
3626	}
3627
3628
3629	/**
3630	* Gets the guest page directory pointer table entry for the specified address.
3631	*
3632	* @returns Pointer to the page directory in question.
3633	* @returns NULL if the page directory is not present or on an invalid page.
3634	* @param pPGM Pointer to the PGM instance data.
3635	* @param GCPtr The address.
3636	*/
3637	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3638	{
3639	AssertGCPtr32(GCPtr);
3640
3641	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3642	PX86PDPT pGuestPDPT = 0;
3643	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3644	AssertRCReturn(rc, 0);
3645	#else
3646	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3647	# ifdef IN_RING3
3648	if (!pGuestPDPT)
3649	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3650	# endif
3651	#endif
3652	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3653	}
3654
3655
3656	/**
3657	* Gets the page directory for the specified address.
3658	*
3659	* @returns Pointer to the page directory in question.
3660	* @returns NULL if the page directory is not present or on an invalid page.
3661	* @param pPGM Pointer to the PGM instance data.
3662	* @param GCPtr The address.
3663	*/
3664	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3665	{
3666	AssertGCPtr32(GCPtr);
3667
3668	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3669	AssertReturn(pGuestPDPT, NULL);
3670	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3671	if (pGuestPDPT->a[iPdpt].n.u1Present)
3672	{
3673	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3674	PX86PDPAE pGuestPD = NULL;
3675	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3676	AssertRCReturn(rc, NULL);
3677	#else
3678	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3679	if ( !pGuestPD
3680	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3681	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3682	#endif
3683	return pGuestPD;
3684	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3685	}
3686	return NULL;
3687	}
3688
3689
3690	/**
3691	* Gets the page directory entry for the specified address.
3692	*
3693	* @returns Pointer to the page directory entry in question.
3694	* @returns NULL if the page directory is not present or on an invalid page.
3695	* @param pPGM Pointer to the PGM instance data.
3696	* @param GCPtr The address.
3697	*/
3698	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3699	{
3700	AssertGCPtr32(GCPtr);
3701
3702	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3703	AssertReturn(pGuestPDPT, NULL);
3704	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3705	if (pGuestPDPT->a[iPdpt].n.u1Present)
3706	{
3707	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3708	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3709	PX86PDPAE pGuestPD = NULL;
3710	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3711	AssertRCReturn(rc, NULL);
3712	#else
3713	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3714	if ( !pGuestPD
3715	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3716	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3717	#endif
3718	return &pGuestPD->a[iPD];
3719	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3720	}
3721	return NULL;
3722	}
3723
3724
3725	/**
3726	* Gets the page directory entry for the specified address.
3727	*
3728	* @returns The page directory entry in question.
3729	* @returns A non-present entry if the page directory is not present or on an invalid page.
3730	* @param pPGM Pointer to the PGM instance data.
3731	* @param GCPtr The address.
3732	*/
3733	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3734	{
3735	AssertGCPtr32(GCPtr);
3736	X86PDEPAE ZeroPde = {0};
3737	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3738	if (RT_LIKELY(pGuestPDPT))
3739	{
3740	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3741	if (pGuestPDPT->a[iPdpt].n.u1Present)
3742	{
3743	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3744	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3745	PX86PDPAE pGuestPD = NULL;
3746	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3747	AssertRCReturn(rc, ZeroPde);
3748	#else
3749	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3750	if ( !pGuestPD
3751	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3752	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3753	#endif
3754	return pGuestPD->a[iPD];
3755	}
3756	}
3757	return ZeroPde;
3758	}
3759
3760
3761	/**
3762	* Gets the page directory pointer table entry for the specified address
3763	* and returns the index into the page directory
3764	*
3765	* @returns Pointer to the page directory in question.
3766	* @returns NULL if the page directory is not present or on an invalid page.
3767	* @param pPGM Pointer to the PGM instance data.
3768	* @param GCPtr The address.
3769	* @param piPD Receives the index into the returned page directory
3770	* @param pPdpe Receives the page directory pointer entry. Optional.
3771	*/
3772	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3773	{
3774	AssertGCPtr32(GCPtr);
3775
3776	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3777	AssertReturn(pGuestPDPT, NULL);
3778	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3779	if (pPdpe)
3780	*pPdpe = pGuestPDPT->a[iPdpt];
3781	if (pGuestPDPT->a[iPdpt].n.u1Present)
3782	{
3783	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3784	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3785	PX86PDPAE pGuestPD = NULL;
3786	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3787	AssertRCReturn(rc, NULL);
3788	#else
3789	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3790	if ( !pGuestPD
3791	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3792	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3793	#endif
3794	*piPD = iPD;
3795	return pGuestPD;
3796	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3797	}
3798	return NULL;
3799	}
3800
3801	#ifndef IN_RC
3802
3803	/**
3804	* Gets the page map level-4 pointer for the guest.
3805	*
3806	* @returns Pointer to the PML4 page.
3807	* @param pPGM Pointer to the PGM instance data.
3808	*/
3809	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3810	{
3811	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3812	PX86PML4 pGuestPml4;
3813	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3814	AssertRCReturn(rc, NULL);
3815	#else
3816	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3817	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3818	if (!pGuestPml4)
3819	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3820	# endif
3821	Assert(pGuestPml4);
3822	#endif
3823	return pGuestPml4;
3824	}
3825
3826
3827	/**
3828	* Gets the pointer to a page map level-4 entry.
3829	*
3830	* @returns Pointer to the PML4 entry.
3831	* @param pPGM Pointer to the PGM instance data.
3832	* @param iPml4 The index.
3833	*/
3834	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3835	{
3836	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3837	PX86PML4 pGuestPml4;
3838	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3839	AssertRCReturn(rc, NULL);
3840	#else
3841	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3842	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3843	if (!pGuestPml4)
3844	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3845	# endif
3846	Assert(pGuestPml4);
3847	#endif
3848	return &pGuestPml4->a[iPml4];
3849	}
3850
3851
3852	/**
3853	* Gets a page map level-4 entry.
3854	*
3855	* @returns The PML4 entry.
3856	* @param pPGM Pointer to the PGM instance data.
3857	* @param iPml4 The index.
3858	*/
3859	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3860	{
3861	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3862	PX86PML4 pGuestPml4;
3863	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3864	if (RT_FAILURE(rc))
3865	{
3866	X86PML4E ZeroPml4e = {0};
3867	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3868	}
3869	#else
3870	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3871	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3872	if (!pGuestPml4)
3873	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3874	# endif
3875	Assert(pGuestPml4);
3876	#endif
3877	return pGuestPml4->a[iPml4];
3878	}
3879
3880
3881	/**
3882	* Gets the page directory pointer entry for the specified address.
3883	*
3884	* @returns Pointer to the page directory pointer entry in question.
3885	* @returns NULL if the page directory is not present or on an invalid page.
3886	* @param pPGM Pointer to the PGM instance data.
3887	* @param GCPtr The address.
3888	* @param ppPml4e Page Map Level-4 Entry (out)
3889	*/
3890	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3891	{
3892	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3893	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3894	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3895	if (pPml4e->n.u1Present)
3896	{
3897	PX86PDPT pPdpt;
3898	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3899	AssertRCReturn(rc, NULL);
3900
3901	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3902	return &pPdpt->a[iPdpt];
3903	}
3904	return NULL;
3905	}
3906
3907
3908	/**
3909	* Gets the page directory entry for the specified address.
3910	*
3911	* @returns The page directory entry in question.
3912	* @returns A non-present entry if the page directory is not present or on an invalid page.
3913	* @param pPGM Pointer to the PGM instance data.
3914	* @param GCPtr The address.
3915	* @param ppPml4e Page Map Level-4 Entry (out)
3916	* @param pPdpe Page directory pointer table entry (out)
3917	*/
3918	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3919	{
3920	X86PDEPAE ZeroPde = {0};
3921	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3922	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3923	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3924	if (pPml4e->n.u1Present)
3925	{
3926	PCX86PDPT pPdptTemp;
3927	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3928	AssertRCReturn(rc, ZeroPde);
3929
3930	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3931	*pPdpe = pPdptTemp->a[iPdpt];
3932	if (pPdptTemp->a[iPdpt].n.u1Present)
3933	{
3934	PCX86PDPAE pPD;
3935	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3936	AssertRCReturn(rc, ZeroPde);
3937
3938	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3939	return pPD->a[iPD];
3940	}
3941	}
3942
3943	return ZeroPde;
3944	}
3945
3946
3947	/**
3948	* Gets the page directory entry for the specified address.
3949	*
3950	* @returns The page directory entry in question.
3951	* @returns A non-present entry if the page directory is not present or on an invalid page.
3952	* @param pPGM Pointer to the PGM instance data.
3953	* @param GCPtr The address.
3954	*/
3955	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3956	{
3957	X86PDEPAE ZeroPde = {0};
3958	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3959	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3960	if (pGuestPml4->a[iPml4].n.u1Present)
3961	{
3962	PCX86PDPT pPdptTemp;
3963	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3964	AssertRCReturn(rc, ZeroPde);
3965
3966	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3967	if (pPdptTemp->a[iPdpt].n.u1Present)
3968	{
3969	PCX86PDPAE pPD;
3970	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3971	AssertRCReturn(rc, ZeroPde);
3972
3973	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3974	return pPD->a[iPD];
3975	}
3976	}
3977	return ZeroPde;
3978	}
3979
3980
3981	/**
3982	* Gets the page directory entry for the specified address.
3983	*
3984	* @returns Pointer to the page directory entry in question.
3985	* @returns NULL if the page directory is not present or on an invalid page.
3986	* @param pPGM Pointer to the PGM instance data.
3987	* @param GCPtr The address.
3988	*/
3989	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3990	{
3991	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3992	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3993	if (pGuestPml4->a[iPml4].n.u1Present)
3994	{
3995	PCX86PDPT pPdptTemp;
3996	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3997	AssertRCReturn(rc, NULL);
3998
3999	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4000	if (pPdptTemp->a[iPdpt].n.u1Present)
4001	{
4002	PX86PDPAE pPD;
4003	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4004	AssertRCReturn(rc, NULL);
4005
4006	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4007	return &pPD->a[iPD];
4008	}
4009	}
4010	return NULL;
4011	}
4012
4013
4014	/**
4015	* Gets the GUEST page directory pointer for the specified address.
4016	*
4017	* @returns The page directory in question.
4018	* @returns NULL if the page directory is not present or on an invalid page.
4019	* @param pPGM Pointer to the PGM instance data.
4020	* @param GCPtr The address.
4021	* @param ppPml4e Page Map Level-4 Entry (out)
4022	* @param pPdpe Page directory pointer table entry (out)
4023	* @param piPD Receives the index into the returned page directory
4024	*/
4025	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4026	{
4027	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4028	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4029	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4030	if (pPml4e->n.u1Present)
4031	{
4032	PCX86PDPT pPdptTemp;
4033	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4034	AssertRCReturn(rc, NULL);
4035
4036	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4037	*pPdpe = pPdptTemp->a[iPdpt];
4038	if (pPdptTemp->a[iPdpt].n.u1Present)
4039	{
4040	PX86PDPAE pPD;
4041	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4042	AssertRCReturn(rc, NULL);
4043
4044	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4045	return pPD;
4046	}
4047	}
4048	return 0;
4049	}
4050
4051	#endif /* !IN_RC */
4052
4053	/**
4054	* Gets the shadow page directory, 32-bit.
4055	*
4056	* @returns Pointer to the shadow 32-bit PD.
4057	* @param pPGM Pointer to the PGM instance data.
4058	*/
4059	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4060	{
4061	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4062	}
4063
4064
4065	/**
4066	* Gets the shadow page directory entry for the specified address, 32-bit.
4067	*
4068	* @returns Shadow 32-bit PDE.
4069	* @param pPGM Pointer to the PGM instance data.
4070	* @param GCPtr The address.
4071	*/
4072	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4073	{
4074	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4075
4076	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4077	if (!pShwPde)
4078	{
4079	X86PDE ZeroPde = {0};
4080	return ZeroPde;
4081	}
4082	return pShwPde->a[iPd];
4083	}
4084
4085
4086	/**
4087	* Gets the pointer to the shadow page directory entry for the specified
4088	* address, 32-bit.
4089	*
4090	* @returns Pointer to the shadow 32-bit PDE.
4091	* @param pPGM Pointer to the PGM instance data.
4092	* @param GCPtr The address.
4093	*/
4094	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4095	{
4096	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4097
4098	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4099	AssertReturn(pPde, NULL);
4100	return &pPde->a[iPd];
4101	}
4102
4103
4104	/**
4105	* Gets the shadow page pointer table, PAE.
4106	*
4107	* @returns Pointer to the shadow PAE PDPT.
4108	* @param pPGM Pointer to the PGM instance data.
4109	*/
4110	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4111	{
4112	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4113	}
4114
4115
4116	/**
4117	* Gets the shadow page directory for the specified address, PAE.
4118	*
4119	* @returns Pointer to the shadow PD.
4120	* @param pPGM Pointer to the PGM instance data.
4121	* @param GCPtr The address.
4122	*/
4123	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4124	{
4125	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4126	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4127
4128	if (!pPdpt->a[iPdpt].n.u1Present)
4129	return NULL;
4130
4131	/* Fetch the pgm pool shadow descriptor. */
4132	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4133	AssertReturn(pShwPde, NULL);
4134
4135	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4136	}
4137
4138
4139	/**
4140	* Gets the shadow page directory for the specified address, PAE.
4141	*
4142	* @returns Pointer to the shadow PD.
4143	* @param pPGM Pointer to the PGM instance data.
4144	* @param GCPtr The address.
4145	*/
4146	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4147	{
4148	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4149
4150	if (!pPdpt->a[iPdpt].n.u1Present)
4151	return NULL;
4152
4153	/* Fetch the pgm pool shadow descriptor. */
4154	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4155	AssertReturn(pShwPde, NULL);
4156
4157	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4158	}
4159
4160
4161	/**
4162	* Gets the shadow page directory entry, PAE.
4163	*
4164	* @returns PDE.
4165	* @param pPGM Pointer to the PGM instance data.
4166	* @param GCPtr The address.
4167	*/
4168	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4169	{
4170	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4171
4172	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4173	if (!pShwPde)
4174	{
4175	X86PDEPAE ZeroPde = {0};
4176	return ZeroPde;
4177	}
4178	return pShwPde->a[iPd];
4179	}
4180
4181
4182	/**
4183	* Gets the pointer to the shadow page directory entry for an address, PAE.
4184	*
4185	* @returns Pointer to the PDE.
4186	* @param pPGM Pointer to the PGM instance data.
4187	* @param GCPtr The address.
4188	*/
4189	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4190	{
4191	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4192
4193	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4194	AssertReturn(pPde, NULL);
4195	return &pPde->a[iPd];
4196	}
4197
4198	#ifndef IN_RC
4199
4200	/**
4201	* Gets the shadow page map level-4 pointer.
4202	*
4203	* @returns Pointer to the shadow PML4.
4204	* @param pPGM Pointer to the PGM instance data.
4205	*/
4206	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4207	{
4208	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4209	}
4210
4211
4212	/**
4213	* Gets the shadow page map level-4 entry for the specified address.
4214	*
4215	* @returns The entry.
4216	* @param pPGM Pointer to the PGM instance data.
4217	* @param GCPtr The address.
4218	*/
4219	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4220	{
4221	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4222	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4223
4224	if (!pShwPml4)
4225	{
4226	X86PML4E ZeroPml4e = {0};
4227	return ZeroPml4e;
4228	}
4229	return pShwPml4->a[iPml4];
4230	}
4231
4232
4233	/**
4234	* Gets the pointer to the specified shadow page map level-4 entry.
4235	*
4236	* @returns The entry.
4237	* @param pPGM Pointer to the PGM instance data.
4238	* @param iPml4 The PML4 index.
4239	*/
4240	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4241	{
4242	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4243	if (!pShwPml4)
4244	return NULL;
4245	return &pShwPml4->a[iPml4];
4246	}
4247
4248
4249	/**
4250	* Gets the GUEST page directory pointer for the specified address.
4251	*
4252	* @returns The page directory in question.
4253	* @returns NULL if the page directory is not present or on an invalid page.
4254	* @param pPGM Pointer to the PGM instance data.
4255	* @param GCPtr The address.
4256	* @param piPD Receives the index into the returned page directory
4257	*/
4258	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4259	{
4260	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4261	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4262	if (pGuestPml4->a[iPml4].n.u1Present)
4263	{
4264	PCX86PDPT pPdptTemp;
4265	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4266	AssertRCReturn(rc, NULL);
4267
4268	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4269	if (pPdptTemp->a[iPdpt].n.u1Present)
4270	{
4271	PX86PDPAE pPD;
4272	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4273	AssertRCReturn(rc, NULL);
4274
4275	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4276	return pPD;
4277	}
4278	}
4279	return NULL;
4280	}
4281
4282	#endif /* !IN_RC */
4283
4284	/**
4285	* Gets the page state for a physical handler.
4286	*
4287	* @returns The physical handler page state.
4288	* @param pCur The physical handler in question.
4289	*/
4290	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4291	{
4292	switch (pCur->enmType)
4293	{
4294	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4295	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4296
4297	case PGMPHYSHANDLERTYPE_MMIO:
4298	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4299	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4300
4301	default:
4302	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4303	}
4304	}
4305
4306
4307	/**
4308	* Gets the page state for a virtual handler.
4309	*
4310	* @returns The virtual handler page state.
4311	* @param pCur The virtual handler in question.
4312	* @remarks This should never be used on a hypervisor access handler.
4313	*/
4314	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4315	{
4316	switch (pCur->enmType)
4317	{
4318	case PGMVIRTHANDLERTYPE_WRITE:
4319	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4320	case PGMVIRTHANDLERTYPE_ALL:
4321	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4322	default:
4323	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4324	}
4325	}
4326
4327
4328	/**
4329	* Clears one physical page of a virtual handler
4330	*
4331	* @param pPGM Pointer to the PGM instance.
4332	* @param pCur Virtual handler structure
4333	* @param iPage Physical page index
4334	*
4335	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4336	* need to care about other handlers in the same page.
4337	*/
4338	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4339	{
4340	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4341
4342	/*
4343	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4344	*/
4345	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4346	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4347	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4348	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4349	#endif
4350	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4351	{
4352	/* We're the head of the alias chain. */
4353	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4354	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4355	AssertReleaseMsg(pRemove != NULL,
4356	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4357	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4358	AssertReleaseMsg(pRemove == pPhys2Virt,
4359	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4360	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4361	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4362	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4363	#endif
4364	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4365	{
4366	/* Insert the next list in the alias chain into the tree. */
4367	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4368	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4369	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4370	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4371	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4372	#endif
4373	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4374	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4375	AssertRelease(fRc);
4376	}
4377	}
4378	else
4379	{
4380	/* Locate the previous node in the alias chain. */
4381	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4382	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4383	AssertReleaseMsg(pPrev != pPhys2Virt,
4384	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4385	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4386	#endif
4387	for (;;)
4388	{
4389	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4390	if (pNext == pPhys2Virt)
4391	{
4392	/* unlink. */
4393	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4394	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4395	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4396	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4397	else
4398	{
4399	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4400	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4401	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4402	}
4403	break;
4404	}
4405
4406	/* next */
4407	if (pNext == pPrev)
4408	{
4409	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4410	AssertReleaseMsg(pNext != pPrev,
4411	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4412	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4413	#endif
4414	break;
4415	}
4416	pPrev = pNext;
4417	}
4418	}
4419	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4420	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4421	pPhys2Virt->offNextAlias = 0;
4422	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4423
4424	/*
4425	* Clear the ram flags for this page.
4426	*/
4427	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4428	AssertReturnVoid(pPage);
4429	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4430	}
4431
4432
4433	/**
4434	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4435	*
4436	* @returns Pointer to the shadow page structure.
4437	* @param pPool The pool.
4438	* @param idx The pool page index.
4439	*/
4440	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4441	{
4442	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4443	return &pPool->aPages[idx];
4444	}
4445
4446
4447	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4448	/**
4449	* Clear references to guest physical memory.
4450	*
4451	* @param pPool The pool.
4452	* @param pPoolPage The pool page.
4453	* @param pPhysPage The physical guest page tracking structure.
4454	*/
4455	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4456	{
4457	/*
4458	* Just deal with the simple case here.
4459	*/
4460	# ifdef LOG_ENABLED
4461	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4462	# endif
4463	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4464	if (cRefs == 1)
4465	{
4466	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4467	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4468	}
4469	else
4470	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4471	Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4472	}
4473	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4474
4475
4476	#ifdef PGMPOOL_WITH_CACHE
4477	/**
4478	* Moves the page to the head of the age list.
4479	*
4480	* This is done when the cached page is used in one way or another.
4481	*
4482	* @param pPool The pool.
4483	* @param pPage The cached page.
4484	*/
4485	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4486	{
4487	PVM pVM = pPool->CTX_SUFF(pVM);
4488	pgmLock(pVM);
4489
4490	/*
4491	* Move to the head of the age list.
4492	*/
4493	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4494	{
4495	/* unlink */
4496	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4497	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4498	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4499	else
4500	pPool->iAgeTail = pPage->iAgePrev;
4501
4502	/* insert at head */
4503	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4504	pPage->iAgeNext = pPool->iAgeHead;
4505	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4506	pPool->iAgeHead = pPage->idx;
4507	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4508	}
4509	pgmUnlock(pVM);
4510	}
4511	#endif /* PGMPOOL_WITH_CACHE */
4512
4513	/**
4514	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4515	*
4516	* @param pVM VM Handle.
4517	* @param pPage PGM pool page
4518	*/
4519	DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4520	{
4521	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4522	ASMAtomicIncU32(&pPage->cLocked);
4523	}
4524
4525
4526	/**
4527	* Unlocks a page to allow flushing again
4528	*
4529	* @param pVM VM Handle.
4530	* @param pPage PGM pool page
4531	*/
4532	DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4533	{
4534	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4535	Assert(pPage->cLocked);
4536	ASMAtomicDecU32(&pPage->cLocked);
4537	}
4538
4539
4540	/**
4541	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4542	*
4543	* @returns VBox status code.
4544	* @param pPage PGM pool page
4545	*/
4546	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4547	{
4548	if (pPage->cLocked)
4549	{
4550	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4551	if (pPage->cModifications)
4552	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4553	return true;
4554	}
4555	return false;
4556	}
4557
4558	/**
4559	* Tells if mappings are to be put into the shadow page table or not
4560	*
4561	* @returns boolean result
4562	* @param pVM VM handle.
4563	*/
4564	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4565	{
4566	#ifdef IN_RING0
4567	/* There are no mappings in VT-x and AMD-V mode. */
4568	Assert(pPGM->fDisableMappings);
4569	return false;
4570	#else
4571	return !pPGM->fDisableMappings;
4572	#endif
4573	}
4574
4575	/** @} */
4576
4577	#endif
4578
4579

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 21116

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