PGMInternal.h@ 22242

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1	/* $Id: PGMInternal.h 22170 2009-08-11 15:01:56Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/critsect.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59	* Comment it if it will break something.
60	*/
61	#define PGM_OUT_OF_SYNC_IN_GC
62
63	/**
64	* Check and skip global PDEs for non-global flushes
65	*/
66	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68	/**
69	* Sync N pages instead of a whole page table
70	*/
71	#define PGM_SYNC_N_PAGES
72
73	/**
74	* Number of pages to sync during a page fault
75	*
76	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
77	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
78	*/
79	#define PGM_SYNC_NR_PAGES 8
80
81	/**
82	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
83	*/
84	#define PGM_MAX_PHYSCACHE_ENTRIES 64
85	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
86
87	/** @def PGMPOOL_WITH_CACHE
88	* Enable agressive caching using the page pool.
89	*
90	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
91	*/
92	#define PGMPOOL_WITH_CACHE
93
94	/** @def PGMPOOL_WITH_MIXED_PT_CR3
95	* When defined, we'll deal with 'uncachable' pages.
96	*/
97	#ifdef PGMPOOL_WITH_CACHE
98	# define PGMPOOL_WITH_MIXED_PT_CR3
99	#endif
100
101	/** @def PGMPOOL_WITH_MONITORING
102	* Monitor the guest pages which are shadowed.
103	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
104	* be enabled as well.
105	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
106	*/
107	#ifdef PGMPOOL_WITH_CACHE
108	# define PGMPOOL_WITH_MONITORING
109	#endif
110
111	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
112	* Tracking the of shadow pages mapping guest physical pages.
113	*
114	* This is very expensive, the current cache prototype is trying to figure out
115	* whether it will be acceptable with an agressive caching policy.
116	*/
117	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
118	# define PGMPOOL_WITH_GCPHYS_TRACKING
119	#endif
120
121	/** @def PGMPOOL_WITH_USER_TRACKING
122	* Tracking users of shadow pages. This is required for the linking of shadow page
123	* tables and physical guest addresses.
124	*/
125	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
126	# define PGMPOOL_WITH_USER_TRACKING
127	#endif
128
129	/** @def PGMPOOL_CFG_MAX_GROW
130	* The maximum number of pages to add to the pool in one go.
131	*/
132	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
133
134	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
135	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
136	*/
137	#ifdef VBOX_STRICT
138	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	#endif
140
141	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
142	* Enables the experimental lazy page allocation code. */
143	/# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
144
145	/** @} */
146
147
148	/** @name PDPT and PML4 flags.
149	* These are placed in the three bits available for system programs in
150	* the PDPT and PML4 entries.
151	* @{ */
152	/** The entry is a permanent one and it's must always be present.
153	* Never free such an entry. */
154	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
155	/** Mapping (hypervisor allocated pagetable). */
156	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
157	/** @} */
158
159	/** @name Page directory flags.
160	* These are placed in the three bits available for system programs in
161	* the page directory entries.
162	* @{ */
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
165	/** Made read-only to facilitate dirty bit tracking. */
166	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
167	/** @} */
168
169	/** @name Page flags.
170	* These are placed in the three bits available for system programs in
171	* the page entries.
172	* @{ */
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
175
176	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
177	/** Scanned and approved by CSAM (tm).
178	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
179	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
180	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
181	#endif
182
183	/** @} */
184
185	/** @name Defines used to indicate the shadow and guest paging in the templates.
186	* @{ */
187	#define PGM_TYPE_REAL 1
188	#define PGM_TYPE_PROT 2
189	#define PGM_TYPE_32BIT 3
190	#define PGM_TYPE_PAE 4
191	#define PGM_TYPE_AMD64 5
192	#define PGM_TYPE_NESTED 6
193	#define PGM_TYPE_EPT 7
194	#define PGM_TYPE_MAX PGM_TYPE_EPT
195	/** @} */
196
197	/** Macro for checking if the guest is using paging.
198	* @param uGstType PGM_TYPE_*
199	* @param uShwType PGM_TYPE_*
200	* @remark ASSUMES certain order of the PGM_TYPE_* values.
201	*/
202	#define PGM_WITH_PAGING(uGstType, uShwType) \
203	( (uGstType) >= PGM_TYPE_32BIT \
204	&& (uShwType) != PGM_TYPE_NESTED \
205	&& (uShwType) != PGM_TYPE_EPT)
206
207	/** Macro for checking if the guest supports the NX bit.
208	* @param uGstType PGM_TYPE_*
209	* @param uShwType PGM_TYPE_*
210	* @remark ASSUMES certain order of the PGM_TYPE_* values.
211	*/
212	#define PGM_WITH_NX(uGstType, uShwType) \
213	( (uGstType) >= PGM_TYPE_PAE \
214	&& (uShwType) != PGM_TYPE_NESTED \
215	&& (uShwType) != PGM_TYPE_EPT)
216
217
218	/** @def PGM_HCPHYS_2_PTR
219	* Maps a HC physical page pool address to a virtual address.
220	*
221	* @returns VBox status code.
222	* @param pVM The VM handle.
223	* @param HCPhys The HC physical address to map to a virtual one.
224	* @param ppv Where to store the virtual address. No need to cast this.
225	*
226	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
227	* small page window employeed by that function. Be careful.
228	* @remark There is no need to assert on the result.
229	*/
230	#ifdef IN_RC
231	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
232	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
233	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
234	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
236	#else
237	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
239	#endif
240
241	/** @def PGM_HCPHYS_2_PTR_BY_PGM
242	* Maps a HC physical page pool address to a virtual address.
243	*
244	* @returns VBox status code.
245	* @param pPGM The PGM instance data.
246	* @param HCPhys The HC physical address to map to a virtual one.
247	* @param ppv Where to store the virtual address. No need to cast this.
248	*
249	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
250	* small page window employeed by that function. Be careful.
251	* @remark There is no need to assert on the result.
252	*/
253	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
254	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
255	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
256	#else
257	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
259	#endif
260
261	/** @def PGM_GCPHYS_2_PTR
262	* Maps a GC physical page address to a virtual address.
263	*
264	* @returns VBox status code.
265	* @param pVM The VM handle.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
270	* small page window employeed by that function. Be careful.
271	* @remark There is no need to assert on the result.
272	*/
273	#ifdef IN_RC
274	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
275	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
276	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
277	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
279	#else
280	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
282	#endif
283
284	/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
285	* Maps a GC physical page address to a virtual address.
286	*
287	* @returns VBox status code.
288	* @param pPGM Pointer to the PGM instance data.
289	* @param GCPhys The GC physical address to map to a virtual one.
290	* @param ppv Where to store the virtual address. No need to cast this.
291	*
292	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
293	* small page window employeed by that function. Be careful.
294	* @remark There is no need to assert on the result.
295	*/
296	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
297	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
298	pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
299	#else
300	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
301	PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
302	#endif
303
304	/** @def PGM_GCPHYS_2_PTR_EX
305	* Maps a unaligned GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pVM The VM handle.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313	* small page window employeed by that function. Be careful.
314	* @remark There is no need to assert on the result.
315	*/
316	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
317	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
318	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
319	#else
320	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
322	#endif
323
324	/** @def PGM_INVL_PG
325	* Invalidates a page.
326	*
327	* @param pVCpu The VMCPU handle.
328	* @param GCVirt The virtual address of the page to invalidate.
329	*/
330	#ifdef IN_RC
331	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
332	#elif defined(IN_RING0)
333	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
334	#else
335	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
336	#endif
337
338	/** @def PGM_INVL_PG
339	* Invalidates a page on all VCPUs
340	*
341	* @param pVM The VM handle.
342	* @param GCVirt The virtual address of the page to invalidate.
343	*/
344	#ifdef IN_RC
345	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
346	#elif defined(IN_RING0)
347	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
348	#else
349	# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
350	#endif
351
352	/** @def PGM_INVL_BIG_PG
353	* Invalidates a 4MB page directory entry.
354	*
355	* @param pVCpu The VMCPU handle.
356	* @param GCVirt The virtual address within the page directory to invalidate.
357	*/
358	#ifdef IN_RC
359	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
360	#elif defined(IN_RING0)
361	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
362	#else
363	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
364	#endif
365
366	/** @def PGM_INVL_VCPU_TLBS()
367	* Invalidates the TLBs of the specified VCPU
368	*
369	* @param pVCpu The VMCPU handle.
370	*/
371	#ifdef IN_RC
372	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
373	#elif defined(IN_RING0)
374	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
375	#else
376	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
377	#endif
378
379	/** @def PGM_INVL_ALL_VCPU_TLBS()
380	* Invalidates the TLBs of all VCPUs
381	*
382	* @param pVM The VM handle.
383	*/
384	#ifdef IN_RC
385	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
386	#elif defined(IN_RING0)
387	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
388	#else
389	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
390	#endif
391
392	/** Size of the GCPtrConflict array in PGMMAPPING.
393	* @remarks Must be a power of two. */
394	#define PGMMAPPING_CONFLICT_MAX 8
395
396	/**
397	* Structure for tracking GC Mappings.
398	*
399	* This structure is used by linked list in both GC and HC.
400	*/
401	typedef struct PGMMAPPING
402	{
403	/** Pointer to next entry. */
404	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
405	/** Pointer to next entry. */
406	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
407	/** Pointer to next entry. */
408	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
409	/** Indicate whether this entry is finalized. */
410	bool fFinalized;
411	/** Start Virtual address. */
412	RTGCPTR GCPtr;
413	/** Last Virtual address (inclusive). */
414	RTGCPTR GCPtrLast;
415	/** Range size (bytes). */
416	RTGCPTR cb;
417	/** Pointer to relocation callback function. */
418	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
419	/** User argument to the callback. */
420	R3PTRTYPE(void *) pvUser;
421	/** Mapping description / name. For easing debugging. */
422	R3PTRTYPE(const char *) pszDesc;
423	/** Last 8 addresses that caused conflicts. */
424	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
425	/** Number of conflicts for this hypervisor mapping. */
426	uint32_t cConflicts;
427	/** Number of page tables. */
428	uint32_t cPTs;
429
430	/** Array of page table mapping data. Each entry
431	* describes one page table. The array can be longer
432	* than the declared length.
433	*/
434	struct
435	{
436	/** The HC physical address of the page table. */
437	RTHCPHYS HCPhysPT;
438	/** The HC physical address of the first PAE page table. */
439	RTHCPHYS HCPhysPaePT0;
440	/** The HC physical address of the second PAE page table. */
441	RTHCPHYS HCPhysPaePT1;
442	/** The HC virtual address of the 32-bit page table. */
443	R3PTRTYPE(PX86PT) pPTR3;
444	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
445	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
446	/** The RC virtual address of the 32-bit page table. */
447	RCPTRTYPE(PX86PT) pPTRC;
448	/** The RC virtual address of the two PAE page table. */
449	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
450	/** The R0 virtual address of the 32-bit page table. */
451	R0PTRTYPE(PX86PT) pPTR0;
452	/** The R0 virtual address of the two PAE page table. */
453	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
454	} aPTs[1];
455	} PGMMAPPING;
456	/** Pointer to structure for tracking GC Mappings. */
457	typedef struct PGMMAPPING *PPGMMAPPING;
458
459
460	/**
461	* Physical page access handler structure.
462	*
463	* This is used to keep track of physical address ranges
464	* which are being monitored in some kind of way.
465	*/
466	typedef struct PGMPHYSHANDLER
467	{
468	AVLROGCPHYSNODECORE Core;
469	/** Access type. */
470	PGMPHYSHANDLERTYPE enmType;
471	/** Number of pages to update. */
472	uint32_t cPages;
473	/** Pointer to R3 callback function. */
474	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
475	/** User argument for R3 handlers. */
476	R3PTRTYPE(void *) pvUserR3;
477	/** Pointer to R0 callback function. */
478	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
479	/** User argument for R0 handlers. */
480	R0PTRTYPE(void *) pvUserR0;
481	/** Pointer to RC callback function. */
482	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
483	/** User argument for RC handlers. */
484	RCPTRTYPE(void *) pvUserRC;
485	/** Description / Name. For easing debugging. */
486	R3PTRTYPE(const char *) pszDesc;
487	#ifdef VBOX_WITH_STATISTICS
488	/** Profiling of this handler. */
489	STAMPROFILE Stat;
490	#endif
491	} PGMPHYSHANDLER;
492	/** Pointer to a physical page access handler structure. */
493	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
494
495
496	/**
497	* Cache node for the physical addresses covered by a virtual handler.
498	*/
499	typedef struct PGMPHYS2VIRTHANDLER
500	{
501	/** Core node for the tree based on physical ranges. */
502	AVLROGCPHYSNODECORE Core;
503	/** Offset from this struct to the PGMVIRTHANDLER structure. */
504	int32_t offVirtHandler;
505	/** Offset of the next alias relative to this one.
506	* Bit 0 is used for indicating whether we're in the tree.
507	* Bit 1 is used for indicating that we're the head node.
508	*/
509	int32_t offNextAlias;
510	} PGMPHYS2VIRTHANDLER;
511	/** Pointer to a phys to virtual handler structure. */
512	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
513
514	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
515	* node is in the tree. */
516	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
517	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
518	* node is in the head of an alias chain.
519	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
520	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
521	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
522	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
523
524
525	/**
526	* Virtual page access handler structure.
527	*
528	* This is used to keep track of virtual address ranges
529	* which are being monitored in some kind of way.
530	*/
531	typedef struct PGMVIRTHANDLER
532	{
533	/** Core node for the tree based on virtual ranges. */
534	AVLROGCPTRNODECORE Core;
535	/** Size of the range (in bytes). */
536	RTGCPTR cb;
537	/** Number of cache pages. */
538	uint32_t cPages;
539	/** Access type. */
540	PGMVIRTHANDLERTYPE enmType;
541	/** Pointer to the RC callback function. */
542	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
543	#if HC_ARCH_BITS == 64
544	RTRCPTR padding;
545	#endif
546	/** Pointer to the R3 callback function for invalidation. */
547	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
548	/** Pointer to the R3 callback function. */
549	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
550	/** Description / Name. For easing debugging. */
551	R3PTRTYPE(const char *) pszDesc;
552	#ifdef VBOX_WITH_STATISTICS
553	/** Profiling of this handler. */
554	STAMPROFILE Stat;
555	#endif
556	/** Array of cached physical addresses for the monitored ranged. */
557	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
558	} PGMVIRTHANDLER;
559	/** Pointer to a virtual page access handler structure. */
560	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
561
562
563	/**
564	* Page type.
565	*
566	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
567	* @remarks This is used in the saved state, so changes to it requires bumping
568	* the saved state version.
569	* @todo So, convert to \#defines!
570	*/
571	typedef enum PGMPAGETYPE
572	{
573	/** The usual invalid zero entry. */
574	PGMPAGETYPE_INVALID = 0,
575	/** RAM page. (RWX) */
576	PGMPAGETYPE_RAM,
577	/** MMIO2 page. (RWX) */
578	PGMPAGETYPE_MMIO2,
579	/** MMIO2 page aliased over an MMIO page. (RWX)
580	* See PGMHandlerPhysicalPageAlias(). */
581	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
582	/** Shadowed ROM. (RWX) */
583	PGMPAGETYPE_ROM_SHADOW,
584	/** ROM page. (R-X) */
585	PGMPAGETYPE_ROM,
586	/** MMIO page. (---) */
587	PGMPAGETYPE_MMIO,
588	/** End of valid entries. */
589	PGMPAGETYPE_END
590	} PGMPAGETYPE;
591	AssertCompile(PGMPAGETYPE_END <= 7);
592
593	/** @name Page type predicates.
594	* @{ */
595	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
596	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
597	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
598	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
599	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
600	/** @} */
601
602
603	/**
604	* A Physical Guest Page tracking structure.
605	*
606	* The format of this structure is complicated because we have to fit a lot
607	* of information into as few bits as possible. The format is also subject
608	* to change (there is one comming up soon). Which means that for we'll be
609	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
610	* accessess to the structure.
611	*/
612	typedef struct PGMPAGE
613	{
614	/** The physical address and a whole lot of other stuff. All bits are used! */
615	RTHCPHYS HCPhysX;
616	/** The page state. */
617	uint32_t u2StateX : 2;
618	/** Flag indicating that a write monitored page was written to when set. */
619	uint32_t fWrittenToX : 1;
620	/** For later. */
621	uint32_t fSomethingElse : 1;
622	/** The Page ID.
623	* @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
624	* The HCPhysX will then be 100% static. */
625	uint32_t idPageX : 28;
626	/** The page type (PGMPAGETYPE). */
627	uint32_t u3Type : 3;
628	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
629	uint32_t u2HandlerPhysStateX : 2;
630	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
631	uint32_t u2HandlerVirtStateX : 2;
632	uint32_t u29B : 25;
633	} PGMPAGE;
634	AssertCompileSize(PGMPAGE, 16);
635	/** Pointer to a physical guest page. */
636	typedef PGMPAGE *PPGMPAGE;
637	/** Pointer to a const physical guest page. */
638	typedef const PGMPAGE *PCPGMPAGE;
639	/** Pointer to a physical guest page pointer. */
640	typedef PPGMPAGE *PPPGMPAGE;
641
642
643	/**
644	* Clears the page structure.
645	* @param pPage Pointer to the physical guest page tracking structure.
646	*/
647	#define PGM_PAGE_CLEAR(pPage) \
648	do { \
649	(pPage)->HCPhysX = 0; \
650	(pPage)->u2StateX = 0; \
651	(pPage)->fWrittenToX = 0; \
652	(pPage)->fSomethingElse = 0; \
653	(pPage)->idPageX = 0; \
654	(pPage)->u3Type = 0; \
655	(pPage)->u29B = 0; \
656	} while (0)
657
658	/**
659	* Initializes the page structure.
660	* @param pPage Pointer to the physical guest page tracking structure.
661	*/
662	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
663	do { \
664	(pPage)->HCPhysX = (_HCPhys); \
665	(pPage)->u2StateX = (_uState); \
666	(pPage)->fWrittenToX = 0; \
667	(pPage)->fSomethingElse = 0; \
668	(pPage)->idPageX = (_idPage); \
669	/(pPage)->u3Type = (_uType); - later / \
670	PGM_PAGE_SET_TYPE(pPage, _uType); \
671	(pPage)->u29B = 0; \
672	} while (0)
673
674	/**
675	* Initializes the page structure of a ZERO page.
676	* @param pPage Pointer to the physical guest page tracking structure.
677	*/
678	#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
679	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
680	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
681	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
682	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
683
684
685	/** @name The Page state, PGMPAGE::u2StateX.
686	* @{ */
687	/** The zero page.
688	* This is a per-VM page that's never ever mapped writable. */
689	#define PGM_PAGE_STATE_ZERO 0
690	/** A allocated page.
691	* This is a per-VM page allocated from the page pool (or wherever
692	* we get MMIO2 pages from if the type is MMIO2).
693	*/
694	#define PGM_PAGE_STATE_ALLOCATED 1
695	/** A allocated page that's being monitored for writes.
696	* The shadow page table mappings are read-only. When a write occurs, the
697	* fWrittenTo member is set, the page remapped as read-write and the state
698	* moved back to allocated. */
699	#define PGM_PAGE_STATE_WRITE_MONITORED 2
700	/** The page is shared, aka. copy-on-write.
701	* This is a page that's shared with other VMs. */
702	#define PGM_PAGE_STATE_SHARED 3
703	/** @} */
704
705
706	/**
707	* Gets the page state.
708	* @returns page state (PGM_PAGE_STATE_*).
709	* @param pPage Pointer to the physical guest page tracking structure.
710	*/
711	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
712
713	/**
714	* Sets the page state.
715	* @param pPage Pointer to the physical guest page tracking structure.
716	* @param _uState The new page state.
717	*/
718	#define PGM_PAGE_SET_STATE(pPage, _uState) \
719	do { (pPage)->u2StateX = (_uState); } while (0)
720
721
722	/**
723	* Gets the host physical address of the guest page.
724	* @returns host physical address (RTHCPHYS).
725	* @param pPage Pointer to the physical guest page tracking structure.
726	*/
727	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
728
729	/**
730	* Sets the host physical address of the guest page.
731	* @param pPage Pointer to the physical guest page tracking structure.
732	* @param _HCPhys The new host physical address.
733	*/
734	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
735	do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
736	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
737
738	/**
739	* Get the Page ID.
740	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
741	* @param pPage Pointer to the physical guest page tracking structure.
742	*/
743	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
744	/* later:
745	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
746	\| ((uint32_t)(pPage)->HCPhysX & 0xfff) )
747	*/
748	/**
749	* Sets the Page ID.
750	* @param pPage Pointer to the physical guest page tracking structure.
751	*/
752	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
753	/* later:
754	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
755	\| ((_idPage) & 0xfff) \
756	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
757	*/
758
759	/**
760	* Get the Chunk ID.
761	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
762	* @param pPage Pointer to the physical guest page tracking structure.
763	*/
764	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
765	/* later:
766	#if GMM_CHUNKID_SHIFT == 12
767	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
768	#elif GMM_CHUNKID_SHIFT > 12
769	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
770	#elif GMM_CHUNKID_SHIFT < 12
771	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
772	\| ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
773	#else
774	# error "GMM_CHUNKID_SHIFT isn't defined or something."
775	#endif
776	*/
777
778	/**
779	* Get the index of the page within the allocaiton chunk.
780	* @returns The page index.
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
784	/* later:
785	#if GMM_CHUNKID_SHIFT <= 12
786	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
787	#else
788	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
789	\| ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
790	#endif
791	*/
792
793
794	/**
795	* Gets the page type.
796	* @returns The page type.
797	* @param pPage Pointer to the physical guest page tracking structure.
798	*/
799	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
800
801	/**
802	* Sets the page type.
803	* @param pPage Pointer to the physical guest page tracking structure.
804	* @param _enmType The new page type (PGMPAGETYPE).
805	*/
806	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
807	do { (pPage)->u3Type = (_enmType); } while (0)
808
809	/**
810	* Checks if the page is marked for MMIO.
811	* @returns true/false.
812	* @param pPage Pointer to the physical guest page tracking structure.
813	*/
814	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
815
816	/**
817	* Checks if the page is backed by the ZERO page.
818	* @returns true/false.
819	* @param pPage Pointer to the physical guest page tracking structure.
820	*/
821	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
822
823	/**
824	* Checks if the page is backed by a SHARED page.
825	* @returns true/false.
826	* @param pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
829
830
831	/**
832	* Marks the paget as written to (for GMM change monitoring).
833	* @param pPage Pointer to the physical guest page tracking structure.
834	*/
835	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
836
837	/**
838	* Clears the written-to indicator.
839	* @param pPage Pointer to the physical guest page tracking structure.
840	*/
841	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
842
843	/**
844	* Checks if the page was marked as written-to.
845	* @returns true/false.
846	* @param pPage Pointer to the physical guest page tracking structure.
847	*/
848	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
849
850
851	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
852	*
853	* @remarks The values are assigned in order of priority, so we can calculate
854	* the correct state for a page with different handlers installed.
855	* @{ */
856	/** No handler installed. */
857	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
858	/** Monitoring is temporarily disabled. */
859	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
860	/** Write access is monitored. */
861	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
862	/** All access is monitored. */
863	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
864	/** @} */
865
866	/**
867	* Gets the physical access handler state of a page.
868	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
869	* @param pPage Pointer to the physical guest page tracking structure.
870	*/
871	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
872
873	/**
874	* Sets the physical access handler state of a page.
875	* @param pPage Pointer to the physical guest page tracking structure.
876	* @param _uState The new state value.
877	*/
878	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
879	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
880
881	/**
882	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
883	* @returns true/false
884	* @param pPage Pointer to the physical guest page tracking structure.
885	*/
886	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
887
888	/**
889	* Checks if the page has any active physical access handlers.
890	* @returns true/false
891	* @param pPage Pointer to the physical guest page tracking structure.
892	*/
893	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
894
895
896	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
897	*
898	* @remarks The values are assigned in order of priority, so we can calculate
899	* the correct state for a page with different handlers installed.
900	* @{ */
901	/** No handler installed. */
902	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
903	/* 1 is reserved so the lineup is identical with the physical ones. */
904	/** Write access is monitored. */
905	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
906	/** All access is monitored. */
907	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
908	/** @} */
909
910	/**
911	* Gets the virtual access handler state of a page.
912	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
913	* @param pPage Pointer to the physical guest page tracking structure.
914	*/
915	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
916
917	/**
918	* Sets the virtual access handler state of a page.
919	* @param pPage Pointer to the physical guest page tracking structure.
920	* @param _uState The new state value.
921	*/
922	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
923	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
924
925	/**
926	* Checks if the page has any virtual access handlers.
927	* @returns true/false
928	* @param pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
931
932	/**
933	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
934	* virtual handlers.
935	* @returns true/false
936	* @param pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
939
940
941
942	/**
943	* Checks if the page has any access handlers, including temporarily disabled ones.
944	* @returns true/false
945	* @param pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
948	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
949	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951	/**
952	* Checks if the page has any active access handlers.
953	* @returns true/false
954	* @param pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
957	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
958	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
959
960	/**
961	* Checks if the page has any active access handlers catching all accesses.
962	* @returns true/false
963	* @param pPage Pointer to the physical guest page tracking structure.
964	*/
965	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
967	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
968
969
970
971
972	/** @def PGM_PAGE_GET_TRACKING
973	* Gets the packed shadow page pool tracking data associated with a guest page.
974	* @returns uint16_t containing the data.
975	* @param pPage Pointer to the physical guest page tracking structure.
976	*/
977	#define PGM_PAGE_GET_TRACKING(pPage) \
978	( ((uint16_t )&(pPage)->HCPhysX + 3) )
979
980	/** @def PGM_PAGE_SET_TRACKING
981	* Sets the packed shadow page pool tracking data associated with a guest page.
982	* @param pPage Pointer to the physical guest page tracking structure.
983	* @param u16TrackingData The tracking data to store.
984	*/
985	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
986	do { ((uint16_t )&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
987
988	/** @def PGM_PAGE_GET_TD_CREFS
989	* Gets the @a cRefs tracking data member.
990	* @returns cRefs.
991	* @param pPage Pointer to the physical guest page tracking structure.
992	*/
993	#define PGM_PAGE_GET_TD_CREFS(pPage) \
994	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
995
996	#define PGM_PAGE_GET_TD_IDX(pPage) \
997	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
998
999	/**
1000	* Ram range for GC Phys to HC Phys conversion.
1001	*
1002	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1003	* conversions too, but we'll let MM handle that for now.
1004	*
1005	* This structure is used by linked lists in both GC and HC.
1006	*/
1007	typedef struct PGMRAMRANGE
1008	{
1009	/** Start of the range. Page aligned. */
1010	RTGCPHYS GCPhys;
1011	/** Size of the range. (Page aligned of course). */
1012	RTGCPHYS cb;
1013	/** Pointer to the next RAM range - for R3. */
1014	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1015	/** Pointer to the next RAM range - for R0. */
1016	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1017	/** Pointer to the next RAM range - for RC. */
1018	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1019	/** PGM_RAM_RANGE_FLAGS_* flags. */
1020	uint32_t fFlags;
1021	/** Last address in the range (inclusive). Page aligned (-1). */
1022	RTGCPHYS GCPhysLast;
1023	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1024	R3PTRTYPE(void *) pvR3;
1025	/** The range description. */
1026	R3PTRTYPE(const char *) pszDesc;
1027	/** Pointer to self - R0 pointer. */
1028	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1029	/** Pointer to self - RC pointer. */
1030	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1031	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1032	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1033	/** Array of physical guest page tracking structures. */
1034	PGMPAGE aPages[1];
1035	} PGMRAMRANGE;
1036	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1037	typedef PGMRAMRANGE *PPGMRAMRANGE;
1038
1039	/** @name PGMRAMRANGE::fFlags
1040	* @{ */
1041	/** The RAM range is floating around as an independent guest mapping. */
1042	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1043	/** @} */
1044
1045
1046	/**
1047	* Per page tracking structure for ROM image.
1048	*
1049	* A ROM image may have a shadow page, in which case we may have
1050	* two pages backing it. This structure contains the PGMPAGE for
1051	* both while PGMRAMRANGE have a copy of the active one. It is
1052	* important that these aren't out of sync in any regard other
1053	* than page pool tracking data.
1054	*/
1055	typedef struct PGMROMPAGE
1056	{
1057	/** The page structure for the virgin ROM page. */
1058	PGMPAGE Virgin;
1059	/** The page structure for the shadow RAM page. */
1060	PGMPAGE Shadow;
1061	/** The current protection setting. */
1062	PGMROMPROT enmProt;
1063	/** Pad the structure size to a multiple of 8. */
1064	uint32_t u32Padding;
1065	} PGMROMPAGE;
1066	/** Pointer to a ROM page tracking structure. */
1067	typedef PGMROMPAGE *PPGMROMPAGE;
1068
1069
1070	/**
1071	* A registered ROM image.
1072	*
1073	* This is needed to keep track of ROM image since they generally
1074	* intrude into a PGMRAMRANGE. It also keeps track of additional
1075	* info like the two page sets (read-only virgin and read-write shadow),
1076	* the current state of each page.
1077	*
1078	* Because access handlers cannot easily be executed in a different
1079	* context, the ROM ranges needs to be accessible and in all contexts.
1080	*/
1081	typedef struct PGMROMRANGE
1082	{
1083	/** Pointer to the next range - R3. */
1084	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1085	/** Pointer to the next range - R0. */
1086	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1087	/** Pointer to the next range - RC. */
1088	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1089	/** Pointer alignment */
1090	RTRCPTR GCPtrAlignment;
1091	/** Address of the range. */
1092	RTGCPHYS GCPhys;
1093	/** Address of the last byte in the range. */
1094	RTGCPHYS GCPhysLast;
1095	/** Size of the range. */
1096	RTGCPHYS cb;
1097	/** The flags (PGMPHYS_ROM_FLAG_). /
1098	uint32_t fFlags;
1099	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1100	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1101	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1102	* This is used for strictness checks. */
1103	R3PTRTYPE(const void *) pvOriginal;
1104	/** The ROM description. */
1105	R3PTRTYPE(const char *) pszDesc;
1106	/** The per page tracking structures. */
1107	PGMROMPAGE aPages[1];
1108	} PGMROMRANGE;
1109	/** Pointer to a ROM range. */
1110	typedef PGMROMRANGE *PPGMROMRANGE;
1111
1112
1113	/**
1114	* A registered MMIO2 (= Device RAM) range.
1115	*
1116	* There are a few reason why we need to keep track of these
1117	* registrations. One of them is the deregistration & cleanup
1118	* stuff, while another is that the PGMRAMRANGE associated with
1119	* such a region may have to be removed from the ram range list.
1120	*
1121	* Overlapping with a RAM range has to be 100% or none at all. The
1122	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1123	* meditation will be raised if a partial overlap or an overlap of
1124	* ROM pages is encountered. On an overlap we will free all the
1125	* existing RAM pages and put in the ram range pages instead.
1126	*/
1127	typedef struct PGMMMIO2RANGE
1128	{
1129	/** The owner of the range. (a device) */
1130	PPDMDEVINSR3 pDevInsR3;
1131	/** Pointer to the ring-3 mapping of the allocation. */
1132	RTR3PTR pvR3;
1133	/** Pointer to the next range - R3. */
1134	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1135	/** Whether it's mapped or not. */
1136	bool fMapped;
1137	/** Whether it's overlapping or not. */
1138	bool fOverlapping;
1139	/** The PCI region number.
1140	* @remarks This ASSUMES that nobody will ever really need to have multiple
1141	* PCI devices with matching MMIO region numbers on a single device. */
1142	uint8_t iRegion;
1143	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1144	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1145	/** The associated RAM range. */
1146	PGMRAMRANGE RamRange;
1147	} PGMMMIO2RANGE;
1148	/** Pointer to a MMIO2 range. */
1149	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1150
1151
1152
1153
1154	/**
1155	* PGMPhysRead/Write cache entry
1156	*/
1157	typedef struct PGMPHYSCACHEENTRY
1158	{
1159	/** R3 pointer to physical page. */
1160	R3PTRTYPE(uint8_t *) pbR3;
1161	/** GC Physical address for cache entry */
1162	RTGCPHYS GCPhys;
1163	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1164	RTGCPHYS u32Padding0; /*< alignment padding. /
1165	#endif
1166	} PGMPHYSCACHEENTRY;
1167
1168	/**
1169	* PGMPhysRead/Write cache to reduce REM memory access overhead
1170	*/
1171	typedef struct PGMPHYSCACHE
1172	{
1173	/** Bitmap of valid cache entries */
1174	uint64_t aEntries;
1175	/** Cache entries */
1176	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1177	} PGMPHYSCACHE;
1178
1179
1180	/** Pointer to an allocation chunk ring-3 mapping. */
1181	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1182	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1183	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1184
1185	/**
1186	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1187	*
1188	* The primary tree (Core) uses the chunk id as key.
1189	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1190	*/
1191	typedef struct PGMCHUNKR3MAP
1192	{
1193	/** The key is the chunk id. */
1194	AVLU32NODECORE Core;
1195	/** The key is the ageing sequence number. */
1196	AVLLU32NODECORE AgeCore;
1197	/** The current age thingy. */
1198	uint32_t iAge;
1199	/** The current reference count. */
1200	uint32_t volatile cRefs;
1201	/** The current permanent reference count. */
1202	uint32_t volatile cPermRefs;
1203	/** The mapping address. */
1204	void *pv;
1205	} PGMCHUNKR3MAP;
1206
1207	/**
1208	* Allocation chunk ring-3 mapping TLB entry.
1209	*/
1210	typedef struct PGMCHUNKR3MAPTLBE
1211	{
1212	/** The chunk id. */
1213	uint32_t volatile idChunk;
1214	#if HC_ARCH_BITS == 64
1215	uint32_t u32Padding; /*< alignment padding. /
1216	#endif
1217	/** The chunk map. */
1218	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1220	#else
1221	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1222	#endif
1223	} PGMCHUNKR3MAPTLBE;
1224	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1225	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1226
1227	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1228	* @remark Must be a power of two value. */
1229	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1230
1231	/**
1232	* Allocation chunk ring-3 mapping TLB.
1233	*
1234	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1235	* At first glance this might look kinda odd since AVL trees are
1236	* supposed to give the most optimial lookup times of all trees
1237	* due to their balancing. However, take a tree with 1023 nodes
1238	* in it, that's 10 levels, meaning that most searches has to go
1239	* down 9 levels before they find what they want. This isn't fast
1240	* compared to a TLB hit. There is the factor of cache misses,
1241	* and of course the problem with trees and branch prediction.
1242	* This is why we use TLBs in front of most of the trees.
1243	*
1244	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1245	* difficult when we switch to the new inlined AVL trees (from kStuff).
1246	*/
1247	typedef struct PGMCHUNKR3MAPTLB
1248	{
1249	/** The TLB entries. */
1250	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1251	} PGMCHUNKR3MAPTLB;
1252
1253	/**
1254	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1255	* @returns Chunk TLB index.
1256	* @param idChunk The Chunk ID.
1257	*/
1258	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1259
1260
1261	/**
1262	* Ring-3 guest page mapping TLB entry.
1263	* @remarks used in ring-0 as well at the moment.
1264	*/
1265	typedef struct PGMPAGER3MAPTLBE
1266	{
1267	/** Address of the page. */
1268	RTGCPHYS volatile GCPhys;
1269	/** The guest page. */
1270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1271	R3PTRTYPE(PPGMPAGE) volatile pPage;
1272	#else
1273	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1274	#endif
1275	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1276	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1277	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1278	#else
1279	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1280	#endif
1281	/** The address */
1282	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1283	R3PTRTYPE(void *) volatile pv;
1284	#else
1285	R3R0PTRTYPE(void *) volatile pv;
1286	#endif
1287	#if HC_ARCH_BITS == 32
1288	uint32_t u32Padding; /*< alignment padding. /
1289	#endif
1290	} PGMPAGER3MAPTLBE;
1291	/** Pointer to an entry in the HC physical TLB. */
1292	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1293
1294
1295	/** The number of entries in the ring-3 guest page mapping TLB.
1296	* @remarks The value must be a power of two. */
1297	#define PGM_PAGER3MAPTLB_ENTRIES 64
1298
1299	/**
1300	* Ring-3 guest page mapping TLB.
1301	* @remarks used in ring-0 as well at the moment.
1302	*/
1303	typedef struct PGMPAGER3MAPTLB
1304	{
1305	/** The TLB entries. */
1306	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1307	} PGMPAGER3MAPTLB;
1308	/** Pointer to the ring-3 guest page mapping TLB. */
1309	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1310
1311	/**
1312	* Calculates the index of the TLB entry for the specified guest page.
1313	* @returns Physical TLB index.
1314	* @param GCPhys The guest physical address.
1315	*/
1316	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1317
1318
1319	/**
1320	* Mapping cache usage set entry.
1321	*
1322	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1323	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1324	* cache. If it's extended to include ring-3, well, then something will
1325	* have be changed here...
1326	*/
1327	typedef struct PGMMAPSETENTRY
1328	{
1329	/** The mapping cache index. */
1330	uint16_t iPage;
1331	/** The number of references.
1332	* The max is UINT16_MAX - 1. */
1333	uint16_t cRefs;
1334	#if HC_ARCH_BITS == 64
1335	uint32_t alignment;
1336	#endif
1337	/** Pointer to the page. */
1338	RTR0PTR pvPage;
1339	/** The physical address for this entry. */
1340	RTHCPHYS HCPhys;
1341	} PGMMAPSETENTRY;
1342	/** Pointer to a mapping cache usage set entry. */
1343	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1344
1345	/**
1346	* Mapping cache usage set.
1347	*
1348	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1349	* done during exits / traps. The set is
1350	*/
1351	typedef struct PGMMAPSET
1352	{
1353	/** The number of occupied entries.
1354	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1355	* dynamic mappings. */
1356	uint32_t cEntries;
1357	/** The start of the current subset.
1358	* This is UINT32_MAX if no subset is currently open. */
1359	uint32_t iSubset;
1360	/** The index of the current CPU, only valid if the set is open. */
1361	int32_t iCpu;
1362	#if HC_ARCH_BITS == 64
1363	uint32_t alignment;
1364	#endif
1365	/** The entries. */
1366	PGMMAPSETENTRY aEntries[64];
1367	/** HCPhys -> iEntry fast lookup table.
1368	* Use PGMMAPSET_HASH for hashing.
1369	* The entries may or may not be valid, check against cEntries. */
1370	uint8_t aiHashTable[128];
1371	} PGMMAPSET;
1372	/** Pointer to the mapping cache set. */
1373	typedef PGMMAPSET *PPGMMAPSET;
1374
1375	/** PGMMAPSET::cEntries value for a closed set. */
1376	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1377
1378	/** Hash function for aiHashTable. */
1379	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1380
1381	/** The max fill size (strict builds). */
1382	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1383
1384
1385	/** @name Context neutrual page mapper TLB.
1386	*
1387	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1388	* code is writting in a kind of context neutrual way. Time will show whether
1389	* this actually makes sense or not...
1390	*
1391	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1392	* context ends up using a global mapping cache on some platforms
1393	* (darwin).
1394	*
1395	* @{ */
1396	/** @typedef PPGMPAGEMAPTLB
1397	* The page mapper TLB pointer type for the current context. */
1398	/** @typedef PPGMPAGEMAPTLB
1399	* The page mapper TLB entry pointer type for the current context. */
1400	/** @typedef PPGMPAGEMAPTLB
1401	* The page mapper TLB entry pointer pointer type for the current context. */
1402	/** @def PGM_PAGEMAPTLB_ENTRIES
1403	* The number of TLB entries in the page mapper TLB for the current context. */
1404	/** @def PGM_PAGEMAPTLB_IDX
1405	* Calculate the TLB index for a guest physical address.
1406	* @returns The TLB index.
1407	* @param GCPhys The guest physical address. */
1408	/** @typedef PPGMPAGEMAP
1409	* Pointer to a page mapper unit for current context. */
1410	/** @typedef PPPGMPAGEMAP
1411	* Pointer to a page mapper unit pointer for current context. */
1412	#ifdef IN_RC
1413	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1414	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1415	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1416	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1417	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1418	typedef void * PPGMPAGEMAP;
1419	typedef void ** PPPGMPAGEMAP;
1420	//#elif IN_RING0
1421	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1422	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1423	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1424	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1425	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1426	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1427	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1428	#else
1429	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1430	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1431	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1432	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1433	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1434	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1435	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1436	#endif
1437	/** @} */
1438
1439
1440	/** @name PGM Pool Indexes.
1441	* Aka. the unique shadow page identifier.
1442	* @{ */
1443	/** NIL page pool IDX. */
1444	#define NIL_PGMPOOL_IDX 0
1445	/** The first normal index. */
1446	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1447	/** Page directory (32-bit root). */
1448	#define PGMPOOL_IDX_PD 1
1449	/** Page Directory Pointer Table (PAE root). */
1450	#define PGMPOOL_IDX_PDPT 2
1451	/** AMD64 CR3 level index.*/
1452	#define PGMPOOL_IDX_AMD64_CR3 3
1453	/** Nested paging root.*/
1454	#define PGMPOOL_IDX_NESTED_ROOT 4
1455	/** The first normal index. */
1456	#define PGMPOOL_IDX_FIRST 5
1457	/** The last valid index. (inclusive, 14 bits) */
1458	#define PGMPOOL_IDX_LAST 0x3fff
1459	/** @} */
1460
1461	/** The NIL index for the parent chain. */
1462	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1463
1464	/**
1465	* Node in the chain linking a shadowed page to it's parent (user).
1466	*/
1467	#pragma pack(1)
1468	typedef struct PGMPOOLUSER
1469	{
1470	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1471	uint16_t iNext;
1472	/** The user page index. */
1473	uint16_t iUser;
1474	/** Index into the user table. */
1475	uint32_t iUserTable;
1476	} PGMPOOLUSER, *PPGMPOOLUSER;
1477	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1478	#pragma pack()
1479
1480
1481	/** The NIL index for the phys ext chain. */
1482	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1483
1484	/**
1485	* Node in the chain of physical cross reference extents.
1486	* @todo Calling this an 'extent' is not quite right, find a better name.
1487	*/
1488	#pragma pack(1)
1489	typedef struct PGMPOOLPHYSEXT
1490	{
1491	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1492	uint16_t iNext;
1493	/** The user page index. */
1494	uint16_t aidx[3];
1495	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1496	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1497	#pragma pack()
1498
1499
1500	/**
1501	* The kind of page that's being shadowed.
1502	*/
1503	typedef enum PGMPOOLKIND
1504	{
1505	/** The virtual invalid 0 entry. */
1506	PGMPOOLKIND_INVALID = 0,
1507	/** The entry is free (=unused). */
1508	PGMPOOLKIND_FREE,
1509
1510	/** Shw: 32-bit page table; Gst: no paging */
1511	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1512	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1513	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1514	/** Shw: 32-bit page table; Gst: 4MB page. */
1515	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1516	/** Shw: PAE page table; Gst: no paging */
1517	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1518	/** Shw: PAE page table; Gst: 32-bit page table. */
1519	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1520	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1521	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1522	/** Shw: PAE page table; Gst: PAE page table. */
1523	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1524	/** Shw: PAE page table; Gst: 2MB page. */
1525	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1526
1527	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1528	PGMPOOLKIND_32BIT_PD,
1529	/** Shw: 32-bit page directory. Gst: no paging. */
1530	PGMPOOLKIND_32BIT_PD_PHYS,
1531	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1532	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1533	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1534	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1535	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1536	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1537	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1538	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1539	/** Shw: PAE page directory; Gst: PAE page directory. */
1540	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1541	/** Shw: PAE page directory; Gst: no paging. */
1542	PGMPOOLKIND_PAE_PD_PHYS,
1543
1544	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1545	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1546	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1547	PGMPOOLKIND_PAE_PDPT,
1548	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1549	PGMPOOLKIND_PAE_PDPT_PHYS,
1550
1551	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1552	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1553	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1554	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1555	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1556	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1557	/** Shw: 64-bit page directory table; Gst: no paging */
1558	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1559
1560	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1561	PGMPOOLKIND_64BIT_PML4,
1562
1563	/** Shw: EPT page directory pointer table; Gst: no paging */
1564	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1565	/** Shw: EPT page directory table; Gst: no paging */
1566	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1567	/** Shw: EPT page table; Gst: no paging */
1568	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1569
1570	/** Shw: Root Nested paging table. */
1571	PGMPOOLKIND_ROOT_NESTED,
1572
1573	/** The last valid entry. */
1574	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1575	} PGMPOOLKIND;
1576
1577	/**
1578	* The access attributes of the page; only applies to big pages.
1579	*/
1580	typedef enum
1581	{
1582	PGMPOOLACCESS_DONTCARE = 0,
1583	PGMPOOLACCESS_USER_RW,
1584	PGMPOOLACCESS_USER_R,
1585	PGMPOOLACCESS_USER_RW_NX,
1586	PGMPOOLACCESS_USER_R_NX,
1587	PGMPOOLACCESS_SUPERVISOR_RW,
1588	PGMPOOLACCESS_SUPERVISOR_R,
1589	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1590	PGMPOOLACCESS_SUPERVISOR_R_NX
1591	} PGMPOOLACCESS;
1592
1593	/**
1594	* The tracking data for a page in the pool.
1595	*/
1596	typedef struct PGMPOOLPAGE
1597	{
1598	/** AVL node code with the (R3) physical address of this page. */
1599	AVLOHCPHYSNODECORE Core;
1600	/** Pointer to the R3 mapping of the page. */
1601	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1602	R3PTRTYPE(void *) pvPageR3;
1603	#else
1604	R3R0PTRTYPE(void *) pvPageR3;
1605	#endif
1606	/** The guest physical address. */
1607	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1608	uint32_t Alignment0;
1609	#endif
1610	RTGCPHYS GCPhys;
1611	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1612	uint8_t enmKind;
1613	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1614	uint8_t enmAccess;
1615	/** The index of this page. */
1616	uint16_t idx;
1617	/** The next entry in the list this page currently resides in.
1618	* It's either in the free list or in the GCPhys hash. */
1619	uint16_t iNext;
1620	#ifdef PGMPOOL_WITH_USER_TRACKING
1621	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1622	uint16_t iUserHead;
1623	/** The number of present entries. */
1624	uint16_t cPresent;
1625	/** The first entry in the table which is present. */
1626	uint16_t iFirstPresent;
1627	#endif
1628	#ifdef PGMPOOL_WITH_MONITORING
1629	/** The number of modifications to the monitored page. */
1630	uint16_t cModifications;
1631	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1632	uint16_t iModifiedNext;
1633	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1634	uint16_t iModifiedPrev;
1635	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1636	uint16_t iMonitoredNext;
1637	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1638	uint16_t iMonitoredPrev;
1639	#endif
1640	#ifdef PGMPOOL_WITH_CACHE
1641	/** The next page in the age list. */
1642	uint16_t iAgeNext;
1643	/** The previous page in the age list. */
1644	uint16_t iAgePrev;
1645	#endif /* PGMPOOL_WITH_CACHE */
1646	/** Used to indicate that the page is zeroed. */
1647	bool fZeroed;
1648	/** Used to indicate that a PT has non-global entries. */
1649	bool fSeenNonGlobal;
1650	/** Used to indicate that we're monitoring writes to the guest page. */
1651	bool fMonitored;
1652	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1653	* (All pages are in the age list.) */
1654	bool fCached;
1655	/** This is used by the R3 access handlers when invoked by an async thread.
1656	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1657	bool volatile fReusedFlushPending;
1658	bool bPadding1;
1659
1660	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1661	uint32_t cLocked;
1662	uint32_t bPadding2;
1663	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1664	/** Pointer to a const pool page. */
1665	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1666
1667
1668	#ifdef PGMPOOL_WITH_CACHE
1669	/** The hash table size. */
1670	# define PGMPOOL_HASH_SIZE 0x40
1671	/** The hash function. */
1672	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1673	#endif
1674
1675
1676	/**
1677	* The shadow page pool instance data.
1678	*
1679	* It's all one big allocation made at init time, except for the
1680	* pages that is. The user nodes follows immediatly after the
1681	* page structures.
1682	*/
1683	typedef struct PGMPOOL
1684	{
1685	/** The VM handle - R3 Ptr. */
1686	PVMR3 pVMR3;
1687	/** The VM handle - R0 Ptr. */
1688	PVMR0 pVMR0;
1689	/** The VM handle - RC Ptr. */
1690	PVMRC pVMRC;
1691	/** The max pool size. This includes the special IDs. */
1692	uint16_t cMaxPages;
1693	/** The current pool size. */
1694	uint16_t cCurPages;
1695	/** The head of the free page list. */
1696	uint16_t iFreeHead;
1697	/* Padding. */
1698	uint16_t u16Padding;
1699	#ifdef PGMPOOL_WITH_USER_TRACKING
1700	/** Head of the chain of free user nodes. */
1701	uint16_t iUserFreeHead;
1702	/** The number of user nodes we've allocated. */
1703	uint16_t cMaxUsers;
1704	/** The number of present page table entries in the entire pool. */
1705	uint32_t cPresent;
1706	/** Pointer to the array of user nodes - RC pointer. */
1707	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1708	/** Pointer to the array of user nodes - R3 pointer. */
1709	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1710	/** Pointer to the array of user nodes - R0 pointer. */
1711	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1712	#endif /* PGMPOOL_WITH_USER_TRACKING */
1713	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1714	/** Head of the chain of free phys ext nodes. */
1715	uint16_t iPhysExtFreeHead;
1716	/** The number of user nodes we've allocated. */
1717	uint16_t cMaxPhysExts;
1718	/** Pointer to the array of physical xref extent - RC pointer. */
1719	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1720	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1721	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1722	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1723	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1724	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1725	#ifdef PGMPOOL_WITH_CACHE
1726	/** Hash table for GCPhys addresses. */
1727	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1728	/** The head of the age list. */
1729	uint16_t iAgeHead;
1730	/** The tail of the age list. */
1731	uint16_t iAgeTail;
1732	/** Set if the cache is enabled. */
1733	bool fCacheEnabled;
1734	#endif /* PGMPOOL_WITH_CACHE */
1735	#ifdef PGMPOOL_WITH_MONITORING
1736	/** Head of the list of modified pages. */
1737	uint16_t iModifiedHead;
1738	/** The current number of modified pages. */
1739	uint16_t cModifiedPages;
1740	/** Access handler, RC. */
1741	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1742	/** Access handler, R0. */
1743	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1744	/** Access handler, R3. */
1745	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1746	/** The access handler description (HC ptr). */
1747	R3PTRTYPE(const char *) pszAccessHandler;
1748	#endif /* PGMPOOL_WITH_MONITORING */
1749	/** The number of pages currently in use. */
1750	uint16_t cUsedPages;
1751	#ifdef VBOX_WITH_STATISTICS
1752	/** The high wather mark for cUsedPages. */
1753	uint16_t cUsedPagesHigh;
1754	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1755	/** Profiling pgmPoolAlloc(). */
1756	STAMPROFILEADV StatAlloc;
1757	/** Profiling pgmPoolClearAll(). */
1758	STAMPROFILE StatClearAll;
1759	/** Profiling pgmPoolFlushAllInt(). */
1760	STAMPROFILE StatFlushAllInt;
1761	/** Profiling pgmPoolFlushPage(). */
1762	STAMPROFILE StatFlushPage;
1763	/** Profiling pgmPoolFree(). */
1764	STAMPROFILE StatFree;
1765	/** Profiling time spent zeroing pages. */
1766	STAMPROFILE StatZeroPage;
1767	# ifdef PGMPOOL_WITH_USER_TRACKING
1768	/** Profiling of pgmPoolTrackDeref. */
1769	STAMPROFILE StatTrackDeref;
1770	/** Profiling pgmTrackFlushGCPhysPT. */
1771	STAMPROFILE StatTrackFlushGCPhysPT;
1772	/** Profiling pgmTrackFlushGCPhysPTs. */
1773	STAMPROFILE StatTrackFlushGCPhysPTs;
1774	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1775	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1776	/** Number of times we've been out of user records. */
1777	STAMCOUNTER StatTrackFreeUpOneUser;
1778	# endif
1779	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1780	/** Profiling deref activity related tracking GC physical pages. */
1781	STAMPROFILE StatTrackDerefGCPhys;
1782	/** Number of linear searches for a HCPhys in the ram ranges. */
1783	STAMCOUNTER StatTrackLinearRamSearches;
1784	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1785	STAMCOUNTER StamTrackPhysExtAllocFailures;
1786	# endif
1787	# ifdef PGMPOOL_WITH_MONITORING
1788	/** Profiling the RC/R0 access handler. */
1789	STAMPROFILE StatMonitorRZ;
1790	/** Times we've failed interpreting the instruction. */
1791	STAMCOUNTER StatMonitorRZEmulateInstr;
1792	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1793	STAMPROFILE StatMonitorRZFlushPage;
1794	/** Times we've detected fork(). */
1795	STAMCOUNTER StatMonitorRZFork;
1796	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1797	STAMPROFILE StatMonitorRZHandled;
1798	/** Times we've failed interpreting a patch code instruction. */
1799	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1800	/** Times we've failed interpreting a patch code instruction during flushing. */
1801	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1802	/** The number of times we've seen rep prefixes we can't handle. */
1803	STAMCOUNTER StatMonitorRZRepPrefix;
1804	/** Profiling the REP STOSD cases we've handled. */
1805	STAMPROFILE StatMonitorRZRepStosd;
1806
1807	/** Profiling the R3 access handler. */
1808	STAMPROFILE StatMonitorR3;
1809	/** Times we've failed interpreting the instruction. */
1810	STAMCOUNTER StatMonitorR3EmulateInstr;
1811	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1812	STAMPROFILE StatMonitorR3FlushPage;
1813	/** Times we've detected fork(). */
1814	STAMCOUNTER StatMonitorR3Fork;
1815	/** Profiling the R3 access we've handled (except REP STOSD). */
1816	STAMPROFILE StatMonitorR3Handled;
1817	/** The number of times we've seen rep prefixes we can't handle. */
1818	STAMCOUNTER StatMonitorR3RepPrefix;
1819	/** Profiling the REP STOSD cases we've handled. */
1820	STAMPROFILE StatMonitorR3RepStosd;
1821	/** The number of times we're called in an async thread an need to flush. */
1822	STAMCOUNTER StatMonitorR3Async;
1823	/** The high wather mark for cModifiedPages. */
1824	uint16_t cModifiedPagesHigh;
1825	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1826	# endif
1827	# ifdef PGMPOOL_WITH_CACHE
1828	/** The number of cache hits. */
1829	STAMCOUNTER StatCacheHits;
1830	/** The number of cache misses. */
1831	STAMCOUNTER StatCacheMisses;
1832	/** The number of times we've got a conflict of 'kind' in the cache. */
1833	STAMCOUNTER StatCacheKindMismatches;
1834	/** Number of times we've been out of pages. */
1835	STAMCOUNTER StatCacheFreeUpOne;
1836	/** The number of cacheable allocations. */
1837	STAMCOUNTER StatCacheCacheable;
1838	/** The number of uncacheable allocations. */
1839	STAMCOUNTER StatCacheUncacheable;
1840	# endif
1841	#elif HC_ARCH_BITS == 64
1842	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1843	#endif
1844	/** The AVL tree for looking up a page by its HC physical address. */
1845	AVLOHCPHYSTREE HCPhysTree;
1846	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1847	/** Array of pages. (cMaxPages in length)
1848	* The Id is the index into thist array.
1849	*/
1850	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1851	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1852
1853
1854	/** @def PGMPOOL_PAGE_2_PTR
1855	* Maps a pool page pool into the current context.
1856	*
1857	* @returns VBox status code.
1858	* @param pVM The VM handle.
1859	* @param pPage The pool page.
1860	*
1861	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1862	* small page window employeed by that function. Be careful.
1863	* @remark There is no need to assert on the result.
1864	*/
1865	#if defined(IN_RC)
1866	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1867	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1868	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1869	#elif defined(VBOX_STRICT)
1870	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1871	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1872	{
1873	Assert(pPage && pPage->pvPageR3);
1874	return pPage->pvPageR3;
1875	}
1876	#else
1877	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1878	#endif
1879
1880	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1881	* Maps a pool page pool into the current context.
1882	*
1883	* @returns VBox status code.
1884	* @param pPGM Pointer to the PGM instance data.
1885	* @param pPage The pool page.
1886	*
1887	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1888	* small page window employeed by that function. Be careful.
1889	* @remark There is no need to assert on the result.
1890	*/
1891	#if defined(IN_RC)
1892	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1893	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1894	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1895	#else
1896	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1897	#endif
1898
1899	/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1900	* Maps a pool page pool into the current context.
1901	*
1902	* @returns VBox status code.
1903	* @param pPGM Pointer to the PGMCPU instance data.
1904	* @param pPage The pool page.
1905	*
1906	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1907	* small page window employeed by that function. Be careful.
1908	* @remark There is no need to assert on the result.
1909	*/
1910	#if defined(IN_RC)
1911	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1912	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1913	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1914	#else
1915	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1916	#endif
1917
1918
1919	/** @name Per guest page tracking data.
1920	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1921	* is to use more bits for it and split it up later on. But for now we'll play
1922	* safe and change as little as possible.
1923	*
1924	* The 16-bit word has two parts:
1925	*
1926	* The first 14-bit forms the @a idx field. It is either the index of a page in
1927	* the shadow page pool, or and index into the extent list.
1928	*
1929	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
1930	* shadow page pool references to the page. If cRefs equals
1931	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1932	* (misnomer) table and not the shadow page pool.
1933	*
1934	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1935	* the 16-bit word.
1936	*
1937	* @{ */
1938	/** The shift count for getting to the cRefs part. */
1939	#define PGMPOOL_TD_CREFS_SHIFT 14
1940	/** The mask applied after shifting the tracking data down by
1941	* PGMPOOL_TD_CREFS_SHIFT. */
1942	#define PGMPOOL_TD_CREFS_MASK 0x3
1943	/** The cRef value used to indiciate that the idx is the head of a
1944	* physical cross reference list. */
1945	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1946	/** The shift used to get idx. */
1947	#define PGMPOOL_TD_IDX_SHIFT 0
1948	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1949	#define PGMPOOL_TD_IDX_MASK 0x3fff
1950	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1951	* simply too many mappings of this page. */
1952	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1953
1954	/** @def PGMPOOL_TD_MAKE
1955	* Makes a 16-bit tracking data word.
1956	*
1957	* @returns tracking data.
1958	* @param cRefs The @a cRefs field. Must be within bounds!
1959	* @param idx The @a idx field. Must also be within bounds! */
1960	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
1961
1962	/** @def PGMPOOL_TD_GET_CREFS
1963	* Get the @a cRefs field from a tracking data word.
1964	*
1965	* @returns The @a cRefs field
1966	* @param u16 The tracking data word. */
1967	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1968
1969	/** @def PGMPOOL_TD_GET_IDX
1970	* Get the @a idx field from a tracking data word.
1971	*
1972	* @returns The @a idx field
1973	* @param u16 The tracking data word. */
1974	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1975	/** @} */
1976
1977
1978	/**
1979	* Trees are using self relative offsets as pointers.
1980	* So, all its data, including the root pointer, must be in the heap for HC and GC
1981	* to have the same layout.
1982	*/
1983	typedef struct PGMTREES
1984	{
1985	/** Physical access handlers (AVL range+offsetptr tree). */
1986	AVLROGCPHYSTREE PhysHandlers;
1987	/** Virtual access handlers (AVL range + GC ptr tree). */
1988	AVLROGCPTRTREE VirtHandlers;
1989	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1990	AVLROGCPHYSTREE PhysToVirtHandlers;
1991	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1992	AVLROGCPTRTREE HyperVirtHandlers;
1993	} PGMTREES;
1994	/** Pointer to PGM trees. */
1995	typedef PGMTREES *PPGMTREES;
1996
1997
1998	/** @name Paging mode macros
1999	* @{ */
2000	#ifdef IN_RC
2001	# define PGM_CTX(a,b) a##RC##b
2002	# define PGM_CTX_STR(a,b) a "GC" b
2003	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2004	#else
2005	# ifdef IN_RING3
2006	# define PGM_CTX(a,b) a##R3##b
2007	# define PGM_CTX_STR(a,b) a "R3" b
2008	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2009	# else
2010	# define PGM_CTX(a,b) a##R0##b
2011	# define PGM_CTX_STR(a,b) a "R0" b
2012	# define PGM_CTX_DECL(type) VMMDECL(type)
2013	# endif
2014	#endif
2015
2016	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2017	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2018	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2019	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2020	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2021	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2022	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2023	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2024	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2025	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2026	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2027	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2028	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2029	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2030	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2031	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2032	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2033
2034	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2035	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2036	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2037	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2038	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2039	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2040	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2041	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2042	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2043	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2044	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2045	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2046	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2047	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2048	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2049	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2050	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2051
2052	/* Shw_Gst */
2053	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2054	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2055	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2056	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2057	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2058	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2059	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2060	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2061	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2062	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2063	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2064	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2065	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2066	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2067	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2068	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2069	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2070	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2071	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2072
2073	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2074	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2075	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2076	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2077	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2078	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2079	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2080	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2081	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2082	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2083	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2084	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2085	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2086	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2087	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2088	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2089	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2090	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2091	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2092	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2093	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2094	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2095	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2096	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2097	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2098	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2099	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2100	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2101	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2102	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2103	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2104	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2105	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2106	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2107	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2108	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2109	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2110
2111	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2112	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2113	/** @} */
2114
2115	/**
2116	* Data for each paging mode.
2117	*/
2118	typedef struct PGMMODEDATA
2119	{
2120	/** The guest mode type. */
2121	uint32_t uGstType;
2122	/** The shadow mode type. */
2123	uint32_t uShwType;
2124
2125	/** @name Function pointers for Shadow paging.
2126	* @{
2127	*/
2128	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2129	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2130	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2131	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2132
2133	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2134	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2135
2136	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2137	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2138	/** @} */
2139
2140	/** @name Function pointers for Guest paging.
2141	* @{
2142	*/
2143	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2144	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2145	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2146	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2147	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2148	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2149	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2150	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2151	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2152	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2153	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2154	/** @} */
2155
2156	/** @name Function pointers for Both Shadow and Guest paging.
2157	* @{
2158	*/
2159	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2160	/* no pfnR3BthTrap0eHandler */
2161	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2162	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2163	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2164	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2165	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2166	#ifdef VBOX_STRICT
2167	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2168	#endif
2169	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2170	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2171
2172	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2173	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2174	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2175	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2176	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2177	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2178	#ifdef VBOX_STRICT
2179	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2180	#endif
2181	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2182	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2183
2184	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2185	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2186	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2187	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2188	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2189	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2190	#ifdef VBOX_STRICT
2191	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2192	#endif
2193	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2194	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2195	/** @} */
2196	} PGMMODEDATA, *PPGMMODEDATA;
2197
2198
2199
2200	/**
2201	* Converts a PGM pointer into a VM pointer.
2202	* @returns Pointer to the VM structure the PGM is part of.
2203	* @param pPGM Pointer to PGM instance data.
2204	*/
2205	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2206
2207	/**
2208	* PGM Data (part of VM)
2209	*/
2210	typedef struct PGM
2211	{
2212	/** Offset to the VM structure. */
2213	RTINT offVM;
2214	/** Offset of the PGMCPU structure relative to VMCPU. */
2215	RTINT offVCpuPGM;
2216
2217	/** @cfgm{RamPreAlloc, boolean, false}
2218	* Indicates whether the base RAM should all be allocated before starting
2219	* the VM (default), or if it should be allocated when first written to.
2220	*/
2221	bool fRamPreAlloc;
2222	/** Alignment padding. */
2223	bool afAlignment0[11];
2224
2225	/*
2226	* This will be redefined at least two more times before we're done, I'm sure.
2227	* The current code is only to get on with the coding.
2228	* - 2004-06-10: initial version, bird.
2229	* - 2004-07-02: 1st time, bird.
2230	* - 2004-10-18: 2nd time, bird.
2231	* - 2005-07-xx: 3rd time, bird.
2232	*/
2233
2234	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2235	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2236	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2237	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2238
2239	/** The host paging mode. (This is what SUPLib reports.) */
2240	SUPPAGINGMODE enmHostMode;
2241
2242	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2243	RTGCPHYS GCPhys4MBPSEMask;
2244
2245	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2246	* This is sorted by physical address and contains no overlapping ranges. */
2247	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2248	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2249	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2250	/** RC pointer corresponding to PGM::pRamRangesR3. */
2251	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2252	RTRCPTR alignment4; /*< structure alignment. /
2253
2254	/** Pointer to the list of ROM ranges - for R3.
2255	* This is sorted by physical address and contains no overlapping ranges. */
2256	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2257	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2258	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2259	/** RC pointer corresponding to PGM::pRomRangesR3. */
2260	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2261	/** Alignment padding. */
2262	RTRCPTR GCPtrPadding2;
2263
2264	/** Pointer to the list of MMIO2 ranges - for R3.
2265	* Registration order. */
2266	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2267
2268	/** PGM offset based trees - R3 Ptr. */
2269	R3PTRTYPE(PPGMTREES) pTreesR3;
2270	/** PGM offset based trees - R0 Ptr. */
2271	R0PTRTYPE(PPGMTREES) pTreesR0;
2272	/** PGM offset based trees - RC Ptr. */
2273	RCPTRTYPE(PPGMTREES) pTreesRC;
2274
2275	/** Linked list of GC mappings - for RC.
2276	* The list is sorted ascending on address.
2277	*/
2278	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2279	/** Linked list of GC mappings - for HC.
2280	* The list is sorted ascending on address.
2281	*/
2282	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2283	/** Linked list of GC mappings - for R0.
2284	* The list is sorted ascending on address.
2285	*/
2286	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2287
2288	/** Pointer to the 5 page CR3 content mapping.
2289	* The first page is always the CR3 (in some form) while the 4 other pages
2290	* are used of the PDs in PAE mode. */
2291	RTGCPTR GCPtrCR3Mapping;
2292	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2293	uint32_t u32Alignment;
2294	#endif
2295
2296	/** Indicates that PGMR3FinalizeMappings has been called and that further
2297	* PGMR3MapIntermediate calls will be rejected. */
2298	bool fFinalizedMappings;
2299	/** If set no conflict checks are required. (boolean) */
2300	bool fMappingsFixed;
2301	/** If set, then no mappings are put into the shadow page table. (boolean) */
2302	bool fDisableMappings;
2303	/** Size of fixed mapping */
2304	uint32_t cbMappingFixed;
2305	/** Base address (GC) of fixed mapping */
2306	RTGCPTR GCPtrMappingFixed;
2307	/** The address of the previous RAM range mapping. */
2308	RTGCPTR GCPtrPrevRamRangeMapping;
2309
2310	/** @name Intermediate Context
2311	* @{ */
2312	/** Pointer to the intermediate page directory - Normal. */
2313	R3PTRTYPE(PX86PD) pInterPD;
2314	/** Pointer to the intermedate page tables - Normal.
2315	* There are two page tables, one for the identity mapping and one for
2316	* the host context mapping (of the core code). */
2317	R3PTRTYPE(PX86PT) apInterPTs[2];
2318	/** Pointer to the intermedate page tables - PAE. */
2319	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2320	/** Pointer to the intermedate page directory - PAE. */
2321	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2322	/** Pointer to the intermedate page directory - PAE. */
2323	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2324	/** Pointer to the intermedate page-map level 4 - AMD64. */
2325	R3PTRTYPE(PX86PML4) pInterPaePML4;
2326	/** Pointer to the intermedate page directory - AMD64. */
2327	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2328	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2329	RTHCPHYS HCPhysInterPD;
2330	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2331	RTHCPHYS HCPhysInterPaePDPT;
2332	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2333	RTHCPHYS HCPhysInterPaePML4;
2334	/** @} */
2335
2336	/** Base address of the dynamic page mapping area.
2337	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2338	*/
2339	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2340	/** The index of the last entry used in the dynamic page mapping area. */
2341	RTUINT iDynPageMapLast;
2342	/** Cache containing the last entries in the dynamic page mapping area.
2343	* The cache size is covering half of the mapping area. */
2344	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2345	/** Keep a lock counter for the full (!) mapping area. */
2346	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2347
2348	/** The address of the ring-0 mapping cache if we're making use of it. */
2349	RTR0PTR pvR0DynMapUsed;
2350
2351	/** PGM critical section.
2352	* This protects the physical & virtual access handlers, ram ranges,
2353	* and the page flag updating (some of it anyway).
2354	*/
2355	PDMCRITSECT CritSect;
2356
2357	/** Pointer to SHW+GST mode data (function pointers).
2358	* The index into this table is made up from */
2359	R3PTRTYPE(PPGMMODEDATA) paModeData;
2360
2361	/** Shadow Page Pool - R3 Ptr. */
2362	R3PTRTYPE(PPGMPOOL) pPoolR3;
2363	/** Shadow Page Pool - R0 Ptr. */
2364	R0PTRTYPE(PPGMPOOL) pPoolR0;
2365	/** Shadow Page Pool - RC Ptr. */
2366	RCPTRTYPE(PPGMPOOL) pPoolRC;
2367
2368	/** We're not in a state which permits writes to guest memory.
2369	* (Only used in strict builds.) */
2370	bool fNoMorePhysWrites;
2371
2372	/**
2373	* Data associated with managing the ring-3 mappings of the allocation chunks.
2374	*/
2375	struct
2376	{
2377	/** The chunk tree, ordered by chunk id. */
2378	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2379	R3PTRTYPE(PAVLU32NODECORE) pTree;
2380	#else
2381	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2382	#endif
2383	/** The chunk mapping TLB. */
2384	PGMCHUNKR3MAPTLB Tlb;
2385	/** The number of mapped chunks. */
2386	uint32_t c;
2387	/** The maximum number of mapped chunks.
2388	* @cfgm PGM/MaxRing3Chunks */
2389	uint32_t cMax;
2390	/** The chunk age tree, ordered by ageing sequence number. */
2391	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2392	/** The current time. */
2393	uint32_t iNow;
2394	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2395	uint32_t AgeingCountdown;
2396	} ChunkR3Map;
2397
2398	/**
2399	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2400	*/
2401	PGMPAGER3MAPTLB PhysTlbHC;
2402
2403	/** @name The zero page.
2404	* @{ */
2405	/** The host physical address of the zero page. */
2406	RTHCPHYS HCPhysZeroPg;
2407	/** The ring-3 mapping of the zero page. */
2408	RTR3PTR pvZeroPgR3;
2409	/** The ring-0 mapping of the zero page. */
2410	RTR0PTR pvZeroPgR0;
2411	/** The GC mapping of the zero page. */
2412	RTGCPTR pvZeroPgRC;
2413	#if GC_ARCH_BITS != 32
2414	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2415	#endif
2416	/** @}*/
2417
2418	/** The number of handy pages. */
2419	uint32_t cHandyPages;
2420	/**
2421	* Array of handy pages.
2422	*
2423	* This array is used in a two way communication between pgmPhysAllocPage
2424	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2425	* an intermediary.
2426	*
2427	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2428	* (The current size of 32 pages, means 128 KB of handy memory.)
2429	*/
2430	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2431
2432	/** @name Error injection.
2433	* @{ */
2434	/** Inject handy page allocation errors pretending we're completely out of
2435	* memory. */
2436	bool volatile fErrInjHandyPages;
2437	/** Padding. */
2438	bool afReserved[7];
2439	/** @} */
2440
2441	/** @name Release Statistics
2442	* @{ */
2443	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2444	uint32_t cPrivatePages; /*< The number of private pages. /
2445	uint32_t cSharedPages; /*< The number of shared pages. /
2446	uint32_t cZeroPages; /*< The number of zero backed pages. /
2447
2448	/** The number of times we were forced to change the hypervisor region location. */
2449	STAMCOUNTER cRelocations;
2450	/** @} */
2451
2452	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2453	/* R3 only: */
2454	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2455	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2456
2457	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2458	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2459	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2460	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2461	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2462	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2463	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2464	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2465	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2466	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2467	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2468	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2469	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2470	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2471	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2472	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2473	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2474	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2475	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2476	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2477	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2478	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2479
2480	/* RC only: */
2481	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache misses /
2482	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache hits /
2483	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2484	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2485
2486	STAMCOUNTER StatRZPhysRead;
2487	STAMCOUNTER StatRZPhysReadBytes;
2488	STAMCOUNTER StatRZPhysWrite;
2489	STAMCOUNTER StatRZPhysWriteBytes;
2490	STAMCOUNTER StatR3PhysRead;
2491	STAMCOUNTER StatR3PhysReadBytes;
2492	STAMCOUNTER StatR3PhysWrite;
2493	STAMCOUNTER StatR3PhysWriteBytes;
2494	STAMCOUNTER StatRCPhysRead;
2495	STAMCOUNTER StatRCPhysReadBytes;
2496	STAMCOUNTER StatRCPhysWrite;
2497	STAMCOUNTER StatRCPhysWriteBytes;
2498
2499	STAMCOUNTER StatRZPhysSimpleRead;
2500	STAMCOUNTER StatRZPhysSimpleReadBytes;
2501	STAMCOUNTER StatRZPhysSimpleWrite;
2502	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2503	STAMCOUNTER StatR3PhysSimpleRead;
2504	STAMCOUNTER StatR3PhysSimpleReadBytes;
2505	STAMCOUNTER StatR3PhysSimpleWrite;
2506	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2507	STAMCOUNTER StatRCPhysSimpleRead;
2508	STAMCOUNTER StatRCPhysSimpleReadBytes;
2509	STAMCOUNTER StatRCPhysSimpleWrite;
2510	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2511
2512	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2513	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2514	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2515	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2516	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2517	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2518	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2519	# endif
2520	#endif
2521	} PGM;
2522	/** Pointer to the PGM instance data. */
2523	typedef PGM *PPGM;
2524
2525
2526	/**
2527	* Converts a PGMCPU pointer into a VM pointer.
2528	* @returns Pointer to the VM structure the PGM is part of.
2529	* @param pPGM Pointer to PGMCPU instance data.
2530	*/
2531	#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2532
2533	/**
2534	* Converts a PGMCPU pointer into a PGM pointer.
2535	* @returns Pointer to the VM structure the PGM is part of.
2536	* @param pPGM Pointer to PGMCPU instance data.
2537	*/
2538	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2539
2540	/**
2541	* PGMCPU Data (part of VMCPU).
2542	*/
2543	typedef struct PGMCPU
2544	{
2545	/** Offset to the VM structure. */
2546	RTINT offVM;
2547	/** Offset to the VMCPU structure. */
2548	RTINT offVCpu;
2549	/** Offset of the PGM structure relative to VMCPU. */
2550	RTINT offPGM;
2551	RTINT uPadding0; /*< structure size alignment. /
2552
2553	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2554	/** Automatically tracked physical memory mapping set.
2555	* Ring-0 and strict raw-mode builds. */
2556	PGMMAPSET AutoSet;
2557	#endif
2558
2559	/** A20 gate mask.
2560	* Our current approach to A20 emulation is to let REM do it and don't bother
2561	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2562	* But whould need arrise, we'll subject physical addresses to this mask. */
2563	RTGCPHYS GCPhysA20Mask;
2564	/** A20 gate state - boolean! */
2565	bool fA20Enabled;
2566
2567	/** What needs syncing (PGM_SYNC_*).
2568	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2569	* PGMFlushTLB, and PGMR3Load. */
2570	RTUINT fSyncFlags;
2571
2572	/** The shadow paging mode. */
2573	PGMMODE enmShadowMode;
2574	/** The guest paging mode. */
2575	PGMMODE enmGuestMode;
2576
2577	/** The current physical address representing in the guest CR3 register. */
2578	RTGCPHYS GCPhysCR3;
2579
2580	/** @name 32-bit Guest Paging.
2581	* @{ */
2582	/** The guest's page directory, R3 pointer. */
2583	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2584	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2585	/** The guest's page directory, R0 pointer. */
2586	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2587	#endif
2588	/** The guest's page directory, static RC mapping. */
2589	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2590	/** @} */
2591
2592	/** @name PAE Guest Paging.
2593	* @{ */
2594	/** The guest's page directory pointer table, static RC mapping. */
2595	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2596	/** The guest's page directory pointer table, R3 pointer. */
2597	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2598	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2599	/** The guest's page directory pointer table, R0 pointer. */
2600	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2601	#endif
2602
2603	/** The guest's page directories, R3 pointers.
2604	* These are individual pointers and don't have to be adjecent.
2605	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2606	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2607	/** The guest's page directories, R0 pointers.
2608	* Same restrictions as apGstPaePDsR3. */
2609	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2610	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2611	#endif
2612	/** The guest's page directories, static GC mapping.
2613	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2614	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2615	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2616	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2617	RTGCPHYS aGCPhysGstPaePDs[4];
2618	/** The physical addresses of the monitored guest page directories (PAE). */
2619	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2620	/** @} */
2621
2622	/** @name AMD64 Guest Paging.
2623	* @{ */
2624	/** The guest's page directory pointer table, R3 pointer. */
2625	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2626	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2627	/** The guest's page directory pointer table, R0 pointer. */
2628	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2629	#endif
2630	/** @} */
2631
2632	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2633	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2634	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2635	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2636	/** Pointer to the page of the current active CR3 - RC Ptr. */
2637	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2638	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2639	uint32_t iShwUser;
2640	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2641	uint32_t iShwUserTable;
2642	# if HC_ARCH_BITS == 64
2643	RTRCPTR alignment6; /*< structure size alignment. /
2644	# endif
2645	/** @} */
2646
2647	/** @name Function pointers for Shadow paging.
2648	* @{
2649	*/
2650	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2651	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2652	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2653	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2654
2655	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2656	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2657
2658	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2659	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2660
2661	/** @} */
2662
2663	/** @name Function pointers for Guest paging.
2664	* @{
2665	*/
2666	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2667	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2668	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2669	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2670	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2671	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2672	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2673	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2674	#if HC_ARCH_BITS == 64
2675	RTRCPTR alignment3; /*< structure size alignment. /
2676	#endif
2677
2678	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2679	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2680	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2681	/** @} */
2682
2683	/** @name Function pointers for Both Shadow and Guest paging.
2684	* @{
2685	*/
2686	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2687	/* no pfnR3BthTrap0eHandler */
2688	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2689	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2690	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2691	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2692	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2693	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2694	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2695	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2696
2697	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2698	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2699	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2700	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2701	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2702	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2703	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2704	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2705	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2706
2707	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2708	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2709	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2710	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2711	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2712	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2713	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2714	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2715	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2716	#if HC_ARCH_BITS == 64
2717	RTRCPTR alignment2; /*< structure size alignment. /
2718	#endif
2719	/** @} */
2720
2721	/** For saving stack space, the disassembler state is allocated here instead of
2722	* on the stack.
2723	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2724	union
2725	{
2726	/** The disassembler scratch space. */
2727	DISCPUSTATE DisState;
2728	/** Padding. */
2729	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2730	};
2731
2732	/** @name Release Statistics
2733	* @{ */
2734	/** The number of times the guest has switched mode since last reset or statistics reset. */
2735	STAMCOUNTER cGuestModeChanges;
2736	/** @} */
2737
2738	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2739	/** @name Statistics
2740	* @{ */
2741	/** RC: Which statistic this \#PF should be attributed to. */
2742	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2743	RTRCPTR padding0;
2744	/** R0: Which statistic this \#PF should be attributed to. */
2745	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2746	RTR0PTR padding1;
2747
2748	/* Common */
2749	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2750	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2751
2752	/* R0 only: */
2753	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2754	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2755	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2756	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2757	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2758	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2759	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2760	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2761	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2762	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2763	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2764	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2765	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2766	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2767	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2768	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2769	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2770	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2771	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2772	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2773	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2774	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2775	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2776	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2777	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2778	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
2779
2780	/* RZ only: */
2781	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2782	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2783	STAMPROFILE StatRZTrap0eTimeSyncPT;
2784	STAMPROFILE StatRZTrap0eTimeMapping;
2785	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2786	STAMPROFILE StatRZTrap0eTimeHandlers;
2787	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2788	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2789	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2790	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2791	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2792	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2793	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2794	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2795	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2796	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2797	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2798	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2799	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2800	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2801	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2802	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2803	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2804	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2805	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2806	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2807	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2808	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2809	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2810	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2811	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2812	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2813	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2814	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2815	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2816	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2817	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2818	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2819	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2820	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2821	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2822	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2823	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2824	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2825	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2826	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2827	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2828	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2829	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2830
2831	/* HC - R3 and (maybe) R0: */
2832
2833	/* RZ & R3: */
2834	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2835	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2836	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2837	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2838	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2839	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2840	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2841	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2842	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2843	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2844	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2845	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2846	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2847	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2848	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2849	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2850	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2851	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2852	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2853	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2854	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2855	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2856	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
2857	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2858	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2859	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2860	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2861	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2862	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2863	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2864	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2865	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2866	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2867	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2868	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2869	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2870	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2871	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2872	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2873	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2874	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2875	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2876	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2877	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2878
2879	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2880	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2881	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2882	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2883	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2884	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2885	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2886	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2887	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2888	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2889	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2890	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2891	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2892	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2893	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2894	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2895	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2896	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2897	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2898	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2899	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2900	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2901	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2902	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2903	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2904	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2905	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2906	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2907	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2908	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2909	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2910	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2911	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2912	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2913	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2914	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2915	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2916	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2917	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2918	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2919	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2920	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2921	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2922	/** @} */
2923	#endif /* VBOX_WITH_STATISTICS */
2924	} PGMCPU;
2925	/** Pointer to the per-cpu PGM data. */
2926	typedef PGMCPU *PPGMCPU;
2927
2928
2929	/** @name PGM::fSyncFlags Flags
2930	* @{
2931	*/
2932	/** Updates the virtual access handler state bit in PGMPAGE. */
2933	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2934	/** Always sync CR3. */
2935	#define PGM_SYNC_ALWAYS RT_BIT(1)
2936	/** Check monitoring on next CR3 (re)load and invalidate page.
2937	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2938	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2939	/** Check guest mapping in SyncCR3. */
2940	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2941	/** Clear the page pool (a light weight flush). */
2942	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2943	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2944	/** @} */
2945
2946
2947	RT_C_DECLS_BEGIN
2948
2949	int pgmLock(PVM pVM);
2950	void pgmUnlock(PVM pVM);
2951
2952	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2953	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2954	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2955	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2956	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2957
2958	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2959	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2960	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2961	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2962	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2963	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2964	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2965	#else
2966	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2967	#endif
2968	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2969
2970
2971	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2972	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2973	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2974	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2975	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2976	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2977	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2978	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2979	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2980	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2981	#ifdef IN_RING3
2982	void pgmR3PhysRelinkRamRanges(PVM pVM);
2983	int pgmR3PhysRamPreAllocate(PVM pVM);
2984	int pgmR3PhysRamReset(PVM pVM);
2985	int pgmR3PhysRomReset(PVM pVM);
2986	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2987
2988	int pgmR3PoolInit(PVM pVM);
2989	void pgmR3PoolRelocate(PVM pVM);
2990	void pgmR3PoolReset(PVM pVM);
2991
2992	#endif /* IN_RING3 */
2993	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2994	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2995	#endif
2996	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
2997
2998	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
2999	{
3000	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3001	}
3002
3003	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3004	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3005	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3006	void pgmPoolClearAll(PVM pVM);
3007	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3008	int pgmPoolSyncCR3(PVMCPU pVCpu);
3009	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3010	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3011	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3012	#ifdef PGMPOOL_WITH_MONITORING
3013	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3014	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3015	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3016	#endif
3017
3018	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3019	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3020
3021	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3022	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3023	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3024	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3025
3026	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3027	#ifndef IN_RC
3028	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3029	#endif
3030	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3031
3032	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3033	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3034	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3035	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3036
3037	RT_C_DECLS_END
3038
3039
3040	/**
3041	* Gets the PGMRAMRANGE structure for a guest page.
3042	*
3043	* @returns Pointer to the RAM range on success.
3044	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3045	*
3046	* @param pPGM PGM handle.
3047	* @param GCPhys The GC physical address.
3048	*/
3049	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3050	{
3051	/*
3052	* Optimize for the first range.
3053	*/
3054	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3055	RTGCPHYS off = GCPhys - pRam->GCPhys;
3056	if (RT_UNLIKELY(off >= pRam->cb))
3057	{
3058	do
3059	{
3060	pRam = pRam->CTX_SUFF(pNext);
3061	if (RT_UNLIKELY(!pRam))
3062	break;
3063	off = GCPhys - pRam->GCPhys;
3064	} while (off >= pRam->cb);
3065	}
3066	return pRam;
3067	}
3068
3069
3070	/**
3071	* Gets the PGMPAGE structure for a guest page.
3072	*
3073	* @returns Pointer to the page on success.
3074	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3075	*
3076	* @param pPGM PGM handle.
3077	* @param GCPhys The GC physical address.
3078	*/
3079	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3080	{
3081	/*
3082	* Optimize for the first range.
3083	*/
3084	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3085	RTGCPHYS off = GCPhys - pRam->GCPhys;
3086	if (RT_UNLIKELY(off >= pRam->cb))
3087	{
3088	do
3089	{
3090	pRam = pRam->CTX_SUFF(pNext);
3091	if (RT_UNLIKELY(!pRam))
3092	return NULL;
3093	off = GCPhys - pRam->GCPhys;
3094	} while (off >= pRam->cb);
3095	}
3096	return &pRam->aPages[off >> PAGE_SHIFT];
3097	}
3098
3099
3100	/**
3101	* Gets the PGMPAGE structure for a guest page.
3102	*
3103	* Old Phys code: Will make sure the page is present.
3104	*
3105	* @returns VBox status code.
3106	* @retval VINF_SUCCESS and a valid *ppPage on success.
3107	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3108	*
3109	* @param pPGM PGM handle.
3110	* @param GCPhys The GC physical address.
3111	* @param ppPage Where to store the page poitner on success.
3112	*/
3113	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3114	{
3115	/*
3116	* Optimize for the first range.
3117	*/
3118	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3119	RTGCPHYS off = GCPhys - pRam->GCPhys;
3120	if (RT_UNLIKELY(off >= pRam->cb))
3121	{
3122	do
3123	{
3124	pRam = pRam->CTX_SUFF(pNext);
3125	if (RT_UNLIKELY(!pRam))
3126	{
3127	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3128	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3129	}
3130	off = GCPhys - pRam->GCPhys;
3131	} while (off >= pRam->cb);
3132	}
3133	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3134	return VINF_SUCCESS;
3135	}
3136
3137
3138
3139
3140	/**
3141	* Gets the PGMPAGE structure for a guest page.
3142	*
3143	* Old Phys code: Will make sure the page is present.
3144	*
3145	* @returns VBox status code.
3146	* @retval VINF_SUCCESS and a valid *ppPage on success.
3147	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3148	*
3149	* @param pPGM PGM handle.
3150	* @param GCPhys The GC physical address.
3151	* @param ppPage Where to store the page poitner on success.
3152	* @param ppRamHint Where to read and store the ram list hint.
3153	* The caller initializes this to NULL before the call.
3154	*/
3155	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3156	{
3157	RTGCPHYS off;
3158	PPGMRAMRANGE pRam = *ppRamHint;
3159	if ( !pRam
3160	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3161	{
3162	pRam = pPGM->CTX_SUFF(pRamRanges);
3163	off = GCPhys - pRam->GCPhys;
3164	if (RT_UNLIKELY(off >= pRam->cb))
3165	{
3166	do
3167	{
3168	pRam = pRam->CTX_SUFF(pNext);
3169	if (RT_UNLIKELY(!pRam))
3170	{
3171	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3172	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3173	}
3174	off = GCPhys - pRam->GCPhys;
3175	} while (off >= pRam->cb);
3176	}
3177	*ppRamHint = pRam;
3178	}
3179	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3180	return VINF_SUCCESS;
3181	}
3182
3183
3184	/**
3185	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3186	*
3187	* @returns Pointer to the page on success.
3188	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3189	*
3190	* @param pPGM PGM handle.
3191	* @param GCPhys The GC physical address.
3192	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3193	*/
3194	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3195	{
3196	/*
3197	* Optimize for the first range.
3198	*/
3199	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3200	RTGCPHYS off = GCPhys - pRam->GCPhys;
3201	if (RT_UNLIKELY(off >= pRam->cb))
3202	{
3203	do
3204	{
3205	pRam = pRam->CTX_SUFF(pNext);
3206	if (RT_UNLIKELY(!pRam))
3207	return NULL;
3208	off = GCPhys - pRam->GCPhys;
3209	} while (off >= pRam->cb);
3210	}
3211	*ppRam = pRam;
3212	return &pRam->aPages[off >> PAGE_SHIFT];
3213	}
3214
3215
3216	/**
3217	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3218	*
3219	* @returns Pointer to the page on success.
3220	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3221	*
3222	* @param pPGM PGM handle.
3223	* @param GCPhys The GC physical address.
3224	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3225	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3226	*/
3227	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3228	{
3229	/*
3230	* Optimize for the first range.
3231	*/
3232	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3233	RTGCPHYS off = GCPhys - pRam->GCPhys;
3234	if (RT_UNLIKELY(off >= pRam->cb))
3235	{
3236	do
3237	{
3238	pRam = pRam->CTX_SUFF(pNext);
3239	if (RT_UNLIKELY(!pRam))
3240	{
3241	ppRam = NULL; / Shut up silly GCC warnings. */
3242	ppPage = NULL; / ditto */
3243	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3244	}
3245	off = GCPhys - pRam->GCPhys;
3246	} while (off >= pRam->cb);
3247	}
3248	*ppRam = pRam;
3249	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3250	return VINF_SUCCESS;
3251	}
3252
3253
3254	/**
3255	* Convert GC Phys to HC Phys.
3256	*
3257	* @returns VBox status.
3258	* @param pPGM PGM handle.
3259	* @param GCPhys The GC physical address.
3260	* @param pHCPhys Where to store the corresponding HC physical address.
3261	*
3262	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3263	* Avoid when writing new code!
3264	*/
3265	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3266	{
3267	PPGMPAGE pPage;
3268	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3269	if (RT_FAILURE(rc))
3270	return rc;
3271	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3272	return VINF_SUCCESS;
3273	}
3274
3275	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3276
3277	/**
3278	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3279	* optimizes access to pages already in the set.
3280	*
3281	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3282	* @param pPGM Pointer to the PVM instance data.
3283	* @param HCPhys The physical address of the page.
3284	* @param ppv Where to store the mapping address.
3285	*/
3286	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3287	{
3288	PVM pVM = PGM2VM(pPGM);
3289	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3290	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3291
3292	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3293	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3294	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3295
3296	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3297	unsigned iEntry = pSet->aiHashTable[iHash];
3298	if ( iEntry < pSet->cEntries
3299	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3300	{
3301	*ppv = pSet->aEntries[iEntry].pvPage;
3302	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3303	}
3304	else
3305	{
3306	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3307	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3308	}
3309
3310	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3311	return VINF_SUCCESS;
3312	}
3313
3314
3315	/**
3316	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3317	* access to pages already in the set.
3318	*
3319	* @returns See PGMDynMapGCPage.
3320	* @param pPGM Pointer to the PVM instance data.
3321	* @param HCPhys The physical address of the page.
3322	* @param ppv Where to store the mapping address.
3323	*/
3324	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3325	{
3326	PVM pVM = PGM2VM(pPGM);
3327	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3328
3329	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3330	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3331
3332	/*
3333	* Get the ram range.
3334	*/
3335	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3336	RTGCPHYS off = GCPhys - pRam->GCPhys;
3337	if (RT_UNLIKELY(off >= pRam->cb
3338	/** @todo \|\| page state stuff */))
3339	{
3340	/* This case is not counted into StatR0DynMapGCPageInl. */
3341	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3342	return PGMDynMapGCPage(pVM, GCPhys, ppv);
3343	}
3344
3345	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3346	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3347
3348	/*
3349	* pgmR0DynMapHCPageInlined with out stats.
3350	*/
3351	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3352	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3353	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3354
3355	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3356	unsigned iEntry = pSet->aiHashTable[iHash];
3357	if ( iEntry < pSet->cEntries
3358	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3359	{
3360	*ppv = pSet->aEntries[iEntry].pvPage;
3361	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3362	}
3363	else
3364	{
3365	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3366	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3367	}
3368
3369	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3370	return VINF_SUCCESS;
3371	}
3372
3373
3374	/**
3375	* Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3376	* access to pages already in the set.
3377	*
3378	* @returns See PGMDynMapGCPage.
3379	* @param pPGM Pointer to the PVM instance data.
3380	* @param HCPhys The physical address of the page.
3381	* @param ppv Where to store the mapping address.
3382	*/
3383	DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3384	{
3385	PVM pVM = PGM2VM(pPGM);
3386	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3387
3388	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3389
3390	/*
3391	* Get the ram range.
3392	*/
3393	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3394	RTGCPHYS off = GCPhys - pRam->GCPhys;
3395	if (RT_UNLIKELY(off >= pRam->cb
3396	/** @todo \|\| page state stuff */))
3397	{
3398	/* This case is not counted into StatR0DynMapGCPageInl. */
3399	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3400	return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3401	}
3402
3403	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3404	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3405
3406	/*
3407	* pgmR0DynMapHCPageInlined with out stats.
3408	*/
3409	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3410	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3411	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3412
3413	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3414	unsigned iEntry = pSet->aiHashTable[iHash];
3415	if ( iEntry < pSet->cEntries
3416	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3417	{
3418	ppv = (void )((uintptr_t)pSet->aEntries[iEntry].pvPage \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3419	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3420	}
3421	else
3422	{
3423	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3424	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3425	ppv = (void )((uintptr_t)*ppv \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3426	}
3427
3428	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3429	return VINF_SUCCESS;
3430	}
3431
3432	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3433	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3434
3435	/**
3436	* Maps the page into current context (RC and maybe R0).
3437	*
3438	* @returns pointer to the mapping.
3439	* @param pVM Pointer to the PGM instance data.
3440	* @param pPage The page.
3441	*/
3442	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3443	{
3444	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3445	{
3446	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3447	void *pv;
3448	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3449	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3450	# else
3451	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3452	# endif
3453	return pv;
3454	}
3455	AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3456	}
3457
3458	/**
3459	* Temporarily maps one host page specified by HC physical address, returning
3460	* pointer within the page.
3461	*
3462	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3463	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3464	*
3465	* @returns The address corresponding to HCPhys.
3466	* @param pPGM Pointer to the PVM instance data.
3467	* @param HCPhys HC Physical address of the page.
3468	*/
3469	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3470	{
3471	void *pv;
3472	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3473	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3474	# else
3475	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3476	# endif
3477	pv = (void *)((uintptr_t)pv \| (HCPhys & PAGE_OFFSET_MASK));
3478	return pv;
3479	}
3480
3481	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3482	#ifndef IN_RC
3483
3484	/**
3485	* Queries the Physical TLB entry for a physical guest page,
3486	* attempting to load the TLB entry if necessary.
3487	*
3488	* @returns VBox status code.
3489	* @retval VINF_SUCCESS on success
3490	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3491	*
3492	* @param pPGM The PGM instance handle.
3493	* @param GCPhys The address of the guest page.
3494	* @param ppTlbe Where to store the pointer to the TLB entry.
3495	*/
3496	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3497	{
3498	int rc;
3499	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3500	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3501	{
3502	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3503	rc = VINF_SUCCESS;
3504	}
3505	else
3506	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3507	*ppTlbe = pTlbe;
3508	return rc;
3509	}
3510
3511
3512	/**
3513	* Queries the Physical TLB entry for a physical guest page,
3514	* attempting to load the TLB entry if necessary.
3515	*
3516	* @returns VBox status code.
3517	* @retval VINF_SUCCESS on success
3518	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3519	*
3520	* @param pPGM The PGM instance handle.
3521	* @param pPage Pointer to the PGMPAGE structure corresponding to
3522	* GCPhys.
3523	* @param GCPhys The address of the guest page.
3524	* @param ppTlbe Where to store the pointer to the TLB entry.
3525	*/
3526	DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3527	{
3528	int rc;
3529	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3530	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3531	{
3532	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3533	rc = VINF_SUCCESS;
3534	}
3535	else
3536	rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3537	*ppTlbe = pTlbe;
3538	return rc;
3539	}
3540
3541	#endif /* !IN_RC */
3542
3543	/**
3544	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3545	* Takes PSE-36 into account.
3546	*
3547	* @returns guest physical address
3548	* @param pPGM Pointer to the PGM instance data.
3549	* @param Pde Guest Pde
3550	*/
3551	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3552	{
3553	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3554	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3555
3556	return GCPhys & pPGM->GCPhys4MBPSEMask;
3557	}
3558
3559
3560	/**
3561	* Gets the page directory entry for the specified address (32-bit paging).
3562	*
3563	* @returns The page directory entry in question.
3564	* @param pPGM Pointer to the PGM instance data.
3565	* @param GCPtr The address.
3566	*/
3567	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3568	{
3569	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3570	PCX86PD pGuestPD = NULL;
3571	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3572	if (RT_FAILURE(rc))
3573	{
3574	X86PDE ZeroPde = {0};
3575	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3576	}
3577	#else
3578	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3579	# ifdef IN_RING3
3580	if (!pGuestPD)
3581	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3582	# endif
3583	#endif
3584	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3585	}
3586
3587
3588	/**
3589	* Gets the address of a specific page directory entry (32-bit paging).
3590	*
3591	* @returns Pointer the page directory entry in question.
3592	* @param pPGM Pointer to the PGM instance data.
3593	* @param GCPtr The address.
3594	*/
3595	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3596	{
3597	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3598	PX86PD pGuestPD = NULL;
3599	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3600	AssertRCReturn(rc, NULL);
3601	#else
3602	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3603	# ifdef IN_RING3
3604	if (!pGuestPD)
3605	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3606	# endif
3607	#endif
3608	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3609	}
3610
3611
3612	/**
3613	* Gets the address the guest page directory (32-bit paging).
3614	*
3615	* @returns Pointer the page directory entry in question.
3616	* @param pPGM Pointer to the PGM instance data.
3617	*/
3618	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3619	{
3620	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3621	PX86PD pGuestPD = NULL;
3622	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3623	AssertRCReturn(rc, NULL);
3624	#else
3625	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3626	# ifdef IN_RING3
3627	if (!pGuestPD)
3628	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3629	# endif
3630	#endif
3631	return pGuestPD;
3632	}
3633
3634
3635	/**
3636	* Gets the guest page directory pointer table.
3637	*
3638	* @returns Pointer to the page directory in question.
3639	* @returns NULL if the page directory is not present or on an invalid page.
3640	* @param pPGM Pointer to the PGM instance data.
3641	*/
3642	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3643	{
3644	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3645	PX86PDPT pGuestPDPT = NULL;
3646	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3647	AssertRCReturn(rc, NULL);
3648	#else
3649	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3650	# ifdef IN_RING3
3651	if (!pGuestPDPT)
3652	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3653	# endif
3654	#endif
3655	return pGuestPDPT;
3656	}
3657
3658
3659	/**
3660	* Gets the guest page directory pointer table entry for the specified address.
3661	*
3662	* @returns Pointer to the page directory in question.
3663	* @returns NULL if the page directory is not present or on an invalid page.
3664	* @param pPGM Pointer to the PGM instance data.
3665	* @param GCPtr The address.
3666	*/
3667	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3668	{
3669	AssertGCPtr32(GCPtr);
3670
3671	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3672	PX86PDPT pGuestPDPT = 0;
3673	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3674	AssertRCReturn(rc, 0);
3675	#else
3676	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3677	# ifdef IN_RING3
3678	if (!pGuestPDPT)
3679	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3680	# endif
3681	#endif
3682	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3683	}
3684
3685
3686	/**
3687	* Gets the page directory for the specified address.
3688	*
3689	* @returns Pointer to the page directory in question.
3690	* @returns NULL if the page directory is not present or on an invalid page.
3691	* @param pPGM Pointer to the PGM instance data.
3692	* @param GCPtr The address.
3693	*/
3694	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3695	{
3696	AssertGCPtr32(GCPtr);
3697
3698	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3699	AssertReturn(pGuestPDPT, NULL);
3700	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3701	if (pGuestPDPT->a[iPdpt].n.u1Present)
3702	{
3703	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3704	PX86PDPAE pGuestPD = NULL;
3705	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3706	AssertRCReturn(rc, NULL);
3707	#else
3708	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3709	if ( !pGuestPD
3710	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3711	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3712	#endif
3713	return pGuestPD;
3714	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3715	}
3716	return NULL;
3717	}
3718
3719
3720	/**
3721	* Gets the page directory entry for the specified address.
3722	*
3723	* @returns Pointer to the page directory entry in question.
3724	* @returns NULL if the page directory is not present or on an invalid page.
3725	* @param pPGM Pointer to the PGM instance data.
3726	* @param GCPtr The address.
3727	*/
3728	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3729	{
3730	AssertGCPtr32(GCPtr);
3731
3732	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3733	AssertReturn(pGuestPDPT, NULL);
3734	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3735	if (pGuestPDPT->a[iPdpt].n.u1Present)
3736	{
3737	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3738	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3739	PX86PDPAE pGuestPD = NULL;
3740	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3741	AssertRCReturn(rc, NULL);
3742	#else
3743	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3744	if ( !pGuestPD
3745	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3746	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3747	#endif
3748	return &pGuestPD->a[iPD];
3749	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3750	}
3751	return NULL;
3752	}
3753
3754
3755	/**
3756	* Gets the page directory entry for the specified address.
3757	*
3758	* @returns The page directory entry in question.
3759	* @returns A non-present entry if the page directory is not present or on an invalid page.
3760	* @param pPGM Pointer to the PGM instance data.
3761	* @param GCPtr The address.
3762	*/
3763	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3764	{
3765	AssertGCPtr32(GCPtr);
3766	X86PDEPAE ZeroPde = {0};
3767	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3768	if (RT_LIKELY(pGuestPDPT))
3769	{
3770	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3771	if (pGuestPDPT->a[iPdpt].n.u1Present)
3772	{
3773	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3774	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3775	PX86PDPAE pGuestPD = NULL;
3776	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3777	AssertRCReturn(rc, ZeroPde);
3778	#else
3779	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3780	if ( !pGuestPD
3781	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3782	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3783	#endif
3784	return pGuestPD->a[iPD];
3785	}
3786	}
3787	return ZeroPde;
3788	}
3789
3790
3791	/**
3792	* Gets the page directory pointer table entry for the specified address
3793	* and returns the index into the page directory
3794	*
3795	* @returns Pointer to the page directory in question.
3796	* @returns NULL if the page directory is not present or on an invalid page.
3797	* @param pPGM Pointer to the PGM instance data.
3798	* @param GCPtr The address.
3799	* @param piPD Receives the index into the returned page directory
3800	* @param pPdpe Receives the page directory pointer entry. Optional.
3801	*/
3802	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3803	{
3804	AssertGCPtr32(GCPtr);
3805
3806	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3807	AssertReturn(pGuestPDPT, NULL);
3808	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3809	if (pPdpe)
3810	*pPdpe = pGuestPDPT->a[iPdpt];
3811	if (pGuestPDPT->a[iPdpt].n.u1Present)
3812	{
3813	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3814	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3815	PX86PDPAE pGuestPD = NULL;
3816	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3817	AssertRCReturn(rc, NULL);
3818	#else
3819	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3820	if ( !pGuestPD
3821	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3822	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3823	#endif
3824	*piPD = iPD;
3825	return pGuestPD;
3826	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3827	}
3828	return NULL;
3829	}
3830
3831	#ifndef IN_RC
3832
3833	/**
3834	* Gets the page map level-4 pointer for the guest.
3835	*
3836	* @returns Pointer to the PML4 page.
3837	* @param pPGM Pointer to the PGM instance data.
3838	*/
3839	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3840	{
3841	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3842	PX86PML4 pGuestPml4;
3843	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3844	AssertRCReturn(rc, NULL);
3845	#else
3846	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3847	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3848	if (!pGuestPml4)
3849	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3850	# endif
3851	Assert(pGuestPml4);
3852	#endif
3853	return pGuestPml4;
3854	}
3855
3856
3857	/**
3858	* Gets the pointer to a page map level-4 entry.
3859	*
3860	* @returns Pointer to the PML4 entry.
3861	* @param pPGM Pointer to the PGM instance data.
3862	* @param iPml4 The index.
3863	*/
3864	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3865	{
3866	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3867	PX86PML4 pGuestPml4;
3868	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3869	AssertRCReturn(rc, NULL);
3870	#else
3871	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3872	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3873	if (!pGuestPml4)
3874	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3875	# endif
3876	Assert(pGuestPml4);
3877	#endif
3878	return &pGuestPml4->a[iPml4];
3879	}
3880
3881
3882	/**
3883	* Gets a page map level-4 entry.
3884	*
3885	* @returns The PML4 entry.
3886	* @param pPGM Pointer to the PGM instance data.
3887	* @param iPml4 The index.
3888	*/
3889	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3890	{
3891	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3892	PX86PML4 pGuestPml4;
3893	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3894	if (RT_FAILURE(rc))
3895	{
3896	X86PML4E ZeroPml4e = {0};
3897	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3898	}
3899	#else
3900	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3901	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3902	if (!pGuestPml4)
3903	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3904	# endif
3905	Assert(pGuestPml4);
3906	#endif
3907	return pGuestPml4->a[iPml4];
3908	}
3909
3910
3911	/**
3912	* Gets the page directory pointer entry for the specified address.
3913	*
3914	* @returns Pointer to the page directory pointer entry in question.
3915	* @returns NULL if the page directory is not present or on an invalid page.
3916	* @param pPGM Pointer to the PGM instance data.
3917	* @param GCPtr The address.
3918	* @param ppPml4e Page Map Level-4 Entry (out)
3919	*/
3920	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3921	{
3922	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3923	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3924	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3925	if (pPml4e->n.u1Present)
3926	{
3927	PX86PDPT pPdpt;
3928	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3929	AssertRCReturn(rc, NULL);
3930
3931	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3932	return &pPdpt->a[iPdpt];
3933	}
3934	return NULL;
3935	}
3936
3937
3938	/**
3939	* Gets the page directory entry for the specified address.
3940	*
3941	* @returns The page directory entry in question.
3942	* @returns A non-present entry if the page directory is not present or on an invalid page.
3943	* @param pPGM Pointer to the PGM instance data.
3944	* @param GCPtr The address.
3945	* @param ppPml4e Page Map Level-4 Entry (out)
3946	* @param pPdpe Page directory pointer table entry (out)
3947	*/
3948	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3949	{
3950	X86PDEPAE ZeroPde = {0};
3951	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3952	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3953	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3954	if (pPml4e->n.u1Present)
3955	{
3956	PCX86PDPT pPdptTemp;
3957	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3958	AssertRCReturn(rc, ZeroPde);
3959
3960	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3961	*pPdpe = pPdptTemp->a[iPdpt];
3962	if (pPdptTemp->a[iPdpt].n.u1Present)
3963	{
3964	PCX86PDPAE pPD;
3965	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3966	AssertRCReturn(rc, ZeroPde);
3967
3968	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3969	return pPD->a[iPD];
3970	}
3971	}
3972
3973	return ZeroPde;
3974	}
3975
3976
3977	/**
3978	* Gets the page directory entry for the specified address.
3979	*
3980	* @returns The page directory entry in question.
3981	* @returns A non-present entry if the page directory is not present or on an invalid page.
3982	* @param pPGM Pointer to the PGM instance data.
3983	* @param GCPtr The address.
3984	*/
3985	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3986	{
3987	X86PDEPAE ZeroPde = {0};
3988	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3989	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3990	if (pGuestPml4->a[iPml4].n.u1Present)
3991	{
3992	PCX86PDPT pPdptTemp;
3993	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3994	AssertRCReturn(rc, ZeroPde);
3995
3996	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3997	if (pPdptTemp->a[iPdpt].n.u1Present)
3998	{
3999	PCX86PDPAE pPD;
4000	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4001	AssertRCReturn(rc, ZeroPde);
4002
4003	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4004	return pPD->a[iPD];
4005	}
4006	}
4007	return ZeroPde;
4008	}
4009
4010
4011	/**
4012	* Gets the page directory entry for the specified address.
4013	*
4014	* @returns Pointer to the page directory entry in question.
4015	* @returns NULL if the page directory is not present or on an invalid page.
4016	* @param pPGM Pointer to the PGM instance data.
4017	* @param GCPtr The address.
4018	*/
4019	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4020	{
4021	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4022	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4023	if (pGuestPml4->a[iPml4].n.u1Present)
4024	{
4025	PCX86PDPT pPdptTemp;
4026	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4027	AssertRCReturn(rc, NULL);
4028
4029	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4030	if (pPdptTemp->a[iPdpt].n.u1Present)
4031	{
4032	PX86PDPAE pPD;
4033	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4034	AssertRCReturn(rc, NULL);
4035
4036	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4037	return &pPD->a[iPD];
4038	}
4039	}
4040	return NULL;
4041	}
4042
4043
4044	/**
4045	* Gets the GUEST page directory pointer for the specified address.
4046	*
4047	* @returns The page directory in question.
4048	* @returns NULL if the page directory is not present or on an invalid page.
4049	* @param pPGM Pointer to the PGM instance data.
4050	* @param GCPtr The address.
4051	* @param ppPml4e Page Map Level-4 Entry (out)
4052	* @param pPdpe Page directory pointer table entry (out)
4053	* @param piPD Receives the index into the returned page directory
4054	*/
4055	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4056	{
4057	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4058	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4059	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4060	if (pPml4e->n.u1Present)
4061	{
4062	PCX86PDPT pPdptTemp;
4063	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4064	AssertRCReturn(rc, NULL);
4065
4066	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4067	*pPdpe = pPdptTemp->a[iPdpt];
4068	if (pPdptTemp->a[iPdpt].n.u1Present)
4069	{
4070	PX86PDPAE pPD;
4071	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4072	AssertRCReturn(rc, NULL);
4073
4074	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4075	return pPD;
4076	}
4077	}
4078	return 0;
4079	}
4080
4081	#endif /* !IN_RC */
4082
4083	/**
4084	* Gets the shadow page directory, 32-bit.
4085	*
4086	* @returns Pointer to the shadow 32-bit PD.
4087	* @param pPGM Pointer to the PGM instance data.
4088	*/
4089	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4090	{
4091	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4092	}
4093
4094
4095	/**
4096	* Gets the shadow page directory entry for the specified address, 32-bit.
4097	*
4098	* @returns Shadow 32-bit PDE.
4099	* @param pPGM Pointer to the PGM instance data.
4100	* @param GCPtr The address.
4101	*/
4102	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4103	{
4104	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4105
4106	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4107	if (!pShwPde)
4108	{
4109	X86PDE ZeroPde = {0};
4110	return ZeroPde;
4111	}
4112	return pShwPde->a[iPd];
4113	}
4114
4115
4116	/**
4117	* Gets the pointer to the shadow page directory entry for the specified
4118	* address, 32-bit.
4119	*
4120	* @returns Pointer to the shadow 32-bit PDE.
4121	* @param pPGM Pointer to the PGM instance data.
4122	* @param GCPtr The address.
4123	*/
4124	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4125	{
4126	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4127
4128	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4129	AssertReturn(pPde, NULL);
4130	return &pPde->a[iPd];
4131	}
4132
4133
4134	/**
4135	* Gets the shadow page pointer table, PAE.
4136	*
4137	* @returns Pointer to the shadow PAE PDPT.
4138	* @param pPGM Pointer to the PGM instance data.
4139	*/
4140	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4141	{
4142	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4143	}
4144
4145
4146	/**
4147	* Gets the shadow page directory for the specified address, PAE.
4148	*
4149	* @returns Pointer to the shadow PD.
4150	* @param pPGM Pointer to the PGM instance data.
4151	* @param GCPtr The address.
4152	*/
4153	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4154	{
4155	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4156	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4157
4158	if (!pPdpt->a[iPdpt].n.u1Present)
4159	return NULL;
4160
4161	/* Fetch the pgm pool shadow descriptor. */
4162	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4163	AssertReturn(pShwPde, NULL);
4164
4165	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4166	}
4167
4168
4169	/**
4170	* Gets the shadow page directory for the specified address, PAE.
4171	*
4172	* @returns Pointer to the shadow PD.
4173	* @param pPGM Pointer to the PGM instance data.
4174	* @param GCPtr The address.
4175	*/
4176	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4177	{
4178	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4179
4180	if (!pPdpt->a[iPdpt].n.u1Present)
4181	return NULL;
4182
4183	/* Fetch the pgm pool shadow descriptor. */
4184	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4185	AssertReturn(pShwPde, NULL);
4186
4187	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4188	}
4189
4190
4191	/**
4192	* Gets the shadow page directory entry, PAE.
4193	*
4194	* @returns PDE.
4195	* @param pPGM Pointer to the PGM instance data.
4196	* @param GCPtr The address.
4197	*/
4198	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4199	{
4200	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4201
4202	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4203	if (!pShwPde)
4204	{
4205	X86PDEPAE ZeroPde = {0};
4206	return ZeroPde;
4207	}
4208	return pShwPde->a[iPd];
4209	}
4210
4211
4212	/**
4213	* Gets the pointer to the shadow page directory entry for an address, PAE.
4214	*
4215	* @returns Pointer to the PDE.
4216	* @param pPGM Pointer to the PGM instance data.
4217	* @param GCPtr The address.
4218	*/
4219	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4220	{
4221	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4222
4223	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4224	AssertReturn(pPde, NULL);
4225	return &pPde->a[iPd];
4226	}
4227
4228	#ifndef IN_RC
4229
4230	/**
4231	* Gets the shadow page map level-4 pointer.
4232	*
4233	* @returns Pointer to the shadow PML4.
4234	* @param pPGM Pointer to the PGM instance data.
4235	*/
4236	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4237	{
4238	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4239	}
4240
4241
4242	/**
4243	* Gets the shadow page map level-4 entry for the specified address.
4244	*
4245	* @returns The entry.
4246	* @param pPGM Pointer to the PGM instance data.
4247	* @param GCPtr The address.
4248	*/
4249	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4250	{
4251	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4252	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4253
4254	if (!pShwPml4)
4255	{
4256	X86PML4E ZeroPml4e = {0};
4257	return ZeroPml4e;
4258	}
4259	return pShwPml4->a[iPml4];
4260	}
4261
4262
4263	/**
4264	* Gets the pointer to the specified shadow page map level-4 entry.
4265	*
4266	* @returns The entry.
4267	* @param pPGM Pointer to the PGM instance data.
4268	* @param iPml4 The PML4 index.
4269	*/
4270	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4271	{
4272	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4273	if (!pShwPml4)
4274	return NULL;
4275	return &pShwPml4->a[iPml4];
4276	}
4277
4278
4279	/**
4280	* Gets the GUEST page directory pointer for the specified address.
4281	*
4282	* @returns The page directory in question.
4283	* @returns NULL if the page directory is not present or on an invalid page.
4284	* @param pPGM Pointer to the PGM instance data.
4285	* @param GCPtr The address.
4286	* @param piPD Receives the index into the returned page directory
4287	*/
4288	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4289	{
4290	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4291	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4292	if (pGuestPml4->a[iPml4].n.u1Present)
4293	{
4294	PCX86PDPT pPdptTemp;
4295	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4296	AssertRCReturn(rc, NULL);
4297
4298	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4299	if (pPdptTemp->a[iPdpt].n.u1Present)
4300	{
4301	PX86PDPAE pPD;
4302	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4303	AssertRCReturn(rc, NULL);
4304
4305	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4306	return pPD;
4307	}
4308	}
4309	return NULL;
4310	}
4311
4312	#endif /* !IN_RC */
4313
4314	/**
4315	* Gets the page state for a physical handler.
4316	*
4317	* @returns The physical handler page state.
4318	* @param pCur The physical handler in question.
4319	*/
4320	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4321	{
4322	switch (pCur->enmType)
4323	{
4324	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4325	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4326
4327	case PGMPHYSHANDLERTYPE_MMIO:
4328	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4329	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4330
4331	default:
4332	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4333	}
4334	}
4335
4336
4337	/**
4338	* Gets the page state for a virtual handler.
4339	*
4340	* @returns The virtual handler page state.
4341	* @param pCur The virtual handler in question.
4342	* @remarks This should never be used on a hypervisor access handler.
4343	*/
4344	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4345	{
4346	switch (pCur->enmType)
4347	{
4348	case PGMVIRTHANDLERTYPE_WRITE:
4349	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4350	case PGMVIRTHANDLERTYPE_ALL:
4351	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4352	default:
4353	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4354	}
4355	}
4356
4357
4358	/**
4359	* Clears one physical page of a virtual handler
4360	*
4361	* @param pPGM Pointer to the PGM instance.
4362	* @param pCur Virtual handler structure
4363	* @param iPage Physical page index
4364	*
4365	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4366	* need to care about other handlers in the same page.
4367	*/
4368	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4369	{
4370	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4371
4372	/*
4373	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4374	*/
4375	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4376	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4377	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4378	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4379	#endif
4380	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4381	{
4382	/* We're the head of the alias chain. */
4383	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4384	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4385	AssertReleaseMsg(pRemove != NULL,
4386	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4387	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4388	AssertReleaseMsg(pRemove == pPhys2Virt,
4389	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4390	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4391	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4392	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4393	#endif
4394	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4395	{
4396	/* Insert the next list in the alias chain into the tree. */
4397	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4398	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4399	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4400	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4401	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4402	#endif
4403	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4404	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4405	AssertRelease(fRc);
4406	}
4407	}
4408	else
4409	{
4410	/* Locate the previous node in the alias chain. */
4411	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4412	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4413	AssertReleaseMsg(pPrev != pPhys2Virt,
4414	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4415	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4416	#endif
4417	for (;;)
4418	{
4419	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4420	if (pNext == pPhys2Virt)
4421	{
4422	/* unlink. */
4423	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4424	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4425	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4426	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4427	else
4428	{
4429	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4430	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4431	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4432	}
4433	break;
4434	}
4435
4436	/* next */
4437	if (pNext == pPrev)
4438	{
4439	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4440	AssertReleaseMsg(pNext != pPrev,
4441	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4442	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4443	#endif
4444	break;
4445	}
4446	pPrev = pNext;
4447	}
4448	}
4449	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4450	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4451	pPhys2Virt->offNextAlias = 0;
4452	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4453
4454	/*
4455	* Clear the ram flags for this page.
4456	*/
4457	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4458	AssertReturnVoid(pPage);
4459	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4460	}
4461
4462
4463	/**
4464	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4465	*
4466	* @returns Pointer to the shadow page structure.
4467	* @param pPool The pool.
4468	* @param idx The pool page index.
4469	*/
4470	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4471	{
4472	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4473	return &pPool->aPages[idx];
4474	}
4475
4476
4477	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4478	/**
4479	* Clear references to guest physical memory.
4480	*
4481	* @param pPool The pool.
4482	* @param pPoolPage The pool page.
4483	* @param pPhysPage The physical guest page tracking structure.
4484	*/
4485	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4486	{
4487	/*
4488	* Just deal with the simple case here.
4489	*/
4490	# ifdef LOG_ENABLED
4491	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4492	# endif
4493	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4494	if (cRefs == 1)
4495	{
4496	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4497	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4498	}
4499	else
4500	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4501	Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4502	}
4503	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4504
4505
4506	#ifdef PGMPOOL_WITH_CACHE
4507	/**
4508	* Moves the page to the head of the age list.
4509	*
4510	* This is done when the cached page is used in one way or another.
4511	*
4512	* @param pPool The pool.
4513	* @param pPage The cached page.
4514	*/
4515	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4516	{
4517	PVM pVM = pPool->CTX_SUFF(pVM);
4518	pgmLock(pVM);
4519
4520	/*
4521	* Move to the head of the age list.
4522	*/
4523	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4524	{
4525	/* unlink */
4526	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4527	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4528	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4529	else
4530	pPool->iAgeTail = pPage->iAgePrev;
4531
4532	/* insert at head */
4533	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4534	pPage->iAgeNext = pPool->iAgeHead;
4535	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4536	pPool->iAgeHead = pPage->idx;
4537	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4538	}
4539	pgmUnlock(pVM);
4540	}
4541	#endif /* PGMPOOL_WITH_CACHE */
4542
4543	/**
4544	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4545	*
4546	* @param pVM VM Handle.
4547	* @param pPage PGM pool page
4548	*/
4549	DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4550	{
4551	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4552	ASMAtomicIncU32(&pPage->cLocked);
4553	}
4554
4555
4556	/**
4557	* Unlocks a page to allow flushing again
4558	*
4559	* @param pVM VM Handle.
4560	* @param pPage PGM pool page
4561	*/
4562	DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4563	{
4564	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4565	Assert(pPage->cLocked);
4566	ASMAtomicDecU32(&pPage->cLocked);
4567	}
4568
4569
4570	/**
4571	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4572	*
4573	* @returns VBox status code.
4574	* @param pPage PGM pool page
4575	*/
4576	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4577	{
4578	if (pPage->cLocked)
4579	{
4580	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4581	if (pPage->cModifications)
4582	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4583	return true;
4584	}
4585	return false;
4586	}
4587
4588	/**
4589	* Tells if mappings are to be put into the shadow page table or not
4590	*
4591	* @returns boolean result
4592	* @param pVM VM handle.
4593	*/
4594	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4595	{
4596	#ifdef IN_RING0
4597	/* There are no mappings in VT-x and AMD-V mode. */
4598	Assert(pPGM->fDisableMappings);
4599	return false;
4600	#else
4601	return !pPGM->fDisableMappings;
4602	#endif
4603	}
4604
4605	/** @} */
4606
4607	#endif
4608
4609

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 22242

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