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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 22544

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1/* $Id: PGMInternal.h 22510 2009-08-27 12:01:45Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#ifndef IN_RC
72////# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
73#endif
74
75/**
76 * Sync N pages instead of a whole page table
77 */
78#define PGM_SYNC_N_PAGES
79
80/**
81 * Number of pages to sync during a page fault
82 *
83 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
84 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
85 */
86#define PGM_SYNC_NR_PAGES 8
87
88/**
89 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
90 */
91#define PGM_MAX_PHYSCACHE_ENTRIES 64
92#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKING
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147
148/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
149 * Enables the experimental lazy page allocation code. */
150/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
151
152/** @} */
153
154
155/** @name PDPT and PML4 flags.
156 * These are placed in the three bits available for system programs in
157 * the PDPT and PML4 entries.
158 * @{ */
159/** The entry is a permanent one and it's must always be present.
160 * Never free such an entry. */
161#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
164/** @} */
165
166/** @name Page directory flags.
167 * These are placed in the three bits available for system programs in
168 * the page directory entries.
169 * @{ */
170/** Mapping (hypervisor allocated pagetable). */
171#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
174/** @} */
175
176/** @name Page flags.
177 * These are placed in the three bits available for system programs in
178 * the page entries.
179 * @{ */
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
182
183#ifndef PGM_PTFLAGS_CSAM_VALIDATED
184/** Scanned and approved by CSAM (tm).
185 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
186 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
187#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
188#endif
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page.
333 *
334 * @param pVCpu The VMCPU handle.
335 * @param GCVirt The virtual address of the page to invalidate.
336 */
337#ifdef IN_RC
338# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
339#elif defined(IN_RING0)
340# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
341#else
342# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
343#endif
344
345/** @def PGM_INVL_PG
346 * Invalidates a page on all VCPUs
347 *
348 * @param pVM The VM handle.
349 * @param GCVirt The virtual address of the page to invalidate.
350 */
351#ifdef IN_RC
352# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
353#elif defined(IN_RING0)
354# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
355#else
356# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
357#endif
358
359/** @def PGM_INVL_BIG_PG
360 * Invalidates a 4MB page directory entry.
361 *
362 * @param pVCpu The VMCPU handle.
363 * @param GCVirt The virtual address within the page directory to invalidate.
364 */
365#ifdef IN_RC
366# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
367#elif defined(IN_RING0)
368# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
369#else
370# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
371#endif
372
373/** @def PGM_INVL_VCPU_TLBS()
374 * Invalidates the TLBs of the specified VCPU
375 *
376 * @param pVCpu The VMCPU handle.
377 */
378#ifdef IN_RC
379# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_ALL_VCPU_TLBS()
387 * Invalidates the TLBs of all VCPUs
388 *
389 * @param pVM The VM handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
395#else
396# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
397#endif
398
399/** Size of the GCPtrConflict array in PGMMAPPING.
400 * @remarks Must be a power of two. */
401#define PGMMAPPING_CONFLICT_MAX 8
402
403/**
404 * Structure for tracking GC Mappings.
405 *
406 * This structure is used by linked list in both GC and HC.
407 */
408typedef struct PGMMAPPING
409{
410 /** Pointer to next entry. */
411 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
412 /** Pointer to next entry. */
413 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
414 /** Pointer to next entry. */
415 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
416 /** Indicate whether this entry is finalized. */
417 bool fFinalized;
418 /** Start Virtual address. */
419 RTGCPTR GCPtr;
420 /** Last Virtual address (inclusive). */
421 RTGCPTR GCPtrLast;
422 /** Range size (bytes). */
423 RTGCPTR cb;
424 /** Pointer to relocation callback function. */
425 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
426 /** User argument to the callback. */
427 R3PTRTYPE(void *) pvUser;
428 /** Mapping description / name. For easing debugging. */
429 R3PTRTYPE(const char *) pszDesc;
430 /** Last 8 addresses that caused conflicts. */
431 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
432 /** Number of conflicts for this hypervisor mapping. */
433 uint32_t cConflicts;
434 /** Number of page tables. */
435 uint32_t cPTs;
436
437 /** Array of page table mapping data. Each entry
438 * describes one page table. The array can be longer
439 * than the declared length.
440 */
441 struct
442 {
443 /** The HC physical address of the page table. */
444 RTHCPHYS HCPhysPT;
445 /** The HC physical address of the first PAE page table. */
446 RTHCPHYS HCPhysPaePT0;
447 /** The HC physical address of the second PAE page table. */
448 RTHCPHYS HCPhysPaePT1;
449 /** The HC virtual address of the 32-bit page table. */
450 R3PTRTYPE(PX86PT) pPTR3;
451 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
452 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
453 /** The RC virtual address of the 32-bit page table. */
454 RCPTRTYPE(PX86PT) pPTRC;
455 /** The RC virtual address of the two PAE page table. */
456 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
457 /** The R0 virtual address of the 32-bit page table. */
458 R0PTRTYPE(PX86PT) pPTR0;
459 /** The R0 virtual address of the two PAE page table. */
460 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
461 } aPTs[1];
462} PGMMAPPING;
463/** Pointer to structure for tracking GC Mappings. */
464typedef struct PGMMAPPING *PPGMMAPPING;
465
466
467/**
468 * Physical page access handler structure.
469 *
470 * This is used to keep track of physical address ranges
471 * which are being monitored in some kind of way.
472 */
473typedef struct PGMPHYSHANDLER
474{
475 AVLROGCPHYSNODECORE Core;
476 /** Access type. */
477 PGMPHYSHANDLERTYPE enmType;
478 /** Number of pages to update. */
479 uint32_t cPages;
480 /** Pointer to R3 callback function. */
481 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
482 /** User argument for R3 handlers. */
483 R3PTRTYPE(void *) pvUserR3;
484 /** Pointer to R0 callback function. */
485 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
486 /** User argument for R0 handlers. */
487 R0PTRTYPE(void *) pvUserR0;
488 /** Pointer to RC callback function. */
489 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
490 /** User argument for RC handlers. */
491 RCPTRTYPE(void *) pvUserRC;
492 /** Description / Name. For easing debugging. */
493 R3PTRTYPE(const char *) pszDesc;
494#ifdef VBOX_WITH_STATISTICS
495 /** Profiling of this handler. */
496 STAMPROFILE Stat;
497#endif
498} PGMPHYSHANDLER;
499/** Pointer to a physical page access handler structure. */
500typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
501
502
503/**
504 * Cache node for the physical addresses covered by a virtual handler.
505 */
506typedef struct PGMPHYS2VIRTHANDLER
507{
508 /** Core node for the tree based on physical ranges. */
509 AVLROGCPHYSNODECORE Core;
510 /** Offset from this struct to the PGMVIRTHANDLER structure. */
511 int32_t offVirtHandler;
512 /** Offset of the next alias relative to this one.
513 * Bit 0 is used for indicating whether we're in the tree.
514 * Bit 1 is used for indicating that we're the head node.
515 */
516 int32_t offNextAlias;
517} PGMPHYS2VIRTHANDLER;
518/** Pointer to a phys to virtual handler structure. */
519typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
520
521/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
522 * node is in the tree. */
523#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
524/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
525 * node is in the head of an alias chain.
526 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
527#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
528/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
529#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
530
531
532/**
533 * Virtual page access handler structure.
534 *
535 * This is used to keep track of virtual address ranges
536 * which are being monitored in some kind of way.
537 */
538typedef struct PGMVIRTHANDLER
539{
540 /** Core node for the tree based on virtual ranges. */
541 AVLROGCPTRNODECORE Core;
542 /** Size of the range (in bytes). */
543 RTGCPTR cb;
544 /** Number of cache pages. */
545 uint32_t cPages;
546 /** Access type. */
547 PGMVIRTHANDLERTYPE enmType;
548 /** Pointer to the RC callback function. */
549 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
550#if HC_ARCH_BITS == 64
551 RTRCPTR padding;
552#endif
553 /** Pointer to the R3 callback function for invalidation. */
554 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
555 /** Pointer to the R3 callback function. */
556 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
557 /** Description / Name. For easing debugging. */
558 R3PTRTYPE(const char *) pszDesc;
559#ifdef VBOX_WITH_STATISTICS
560 /** Profiling of this handler. */
561 STAMPROFILE Stat;
562#endif
563 /** Array of cached physical addresses for the monitored ranged. */
564 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
565} PGMVIRTHANDLER;
566/** Pointer to a virtual page access handler structure. */
567typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
568
569
570/**
571 * Page type.
572 *
573 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
574 * @remarks This is used in the saved state, so changes to it requires bumping
575 * the saved state version.
576 * @todo So, convert to \#defines!
577 */
578typedef enum PGMPAGETYPE
579{
580 /** The usual invalid zero entry. */
581 PGMPAGETYPE_INVALID = 0,
582 /** RAM page. (RWX) */
583 PGMPAGETYPE_RAM,
584 /** MMIO2 page. (RWX) */
585 PGMPAGETYPE_MMIO2,
586 /** MMIO2 page aliased over an MMIO page. (RWX)
587 * See PGMHandlerPhysicalPageAlias(). */
588 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
589 /** Shadowed ROM. (RWX) */
590 PGMPAGETYPE_ROM_SHADOW,
591 /** ROM page. (R-X) */
592 PGMPAGETYPE_ROM,
593 /** MMIO page. (---) */
594 PGMPAGETYPE_MMIO,
595 /** End of valid entries. */
596 PGMPAGETYPE_END
597} PGMPAGETYPE;
598AssertCompile(PGMPAGETYPE_END <= 7);
599
600/** @name Page type predicates.
601 * @{ */
602#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
603#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
604#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
605#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
606#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
607/** @} */
608
609
610/**
611 * A Physical Guest Page tracking structure.
612 *
613 * The format of this structure is complicated because we have to fit a lot
614 * of information into as few bits as possible. The format is also subject
615 * to change (there is one comming up soon). Which means that for we'll be
616 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
617 * accessess to the structure.
618 */
619typedef struct PGMPAGE
620{
621 /** The physical address and a whole lot of other stuff. All bits are used! */
622 RTHCPHYS HCPhysX;
623 /** The page state. */
624 uint32_t u2StateX : 2;
625 /** Flag indicating that a write monitored page was written to when set. */
626 uint32_t fWrittenToX : 1;
627 /** For later. */
628 uint32_t fSomethingElse : 1;
629 /** The Page ID.
630 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
631 * The HCPhysX will then be 100% static. */
632 uint32_t idPageX : 28;
633 /** The page type (PGMPAGETYPE). */
634 uint32_t u3Type : 3;
635 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
636 uint32_t u2HandlerPhysStateX : 2;
637 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
638 uint32_t u2HandlerVirtStateX : 2;
639 uint32_t u29B : 25;
640} PGMPAGE;
641AssertCompileSize(PGMPAGE, 16);
642/** Pointer to a physical guest page. */
643typedef PGMPAGE *PPGMPAGE;
644/** Pointer to a const physical guest page. */
645typedef const PGMPAGE *PCPGMPAGE;
646/** Pointer to a physical guest page pointer. */
647typedef PPGMPAGE *PPPGMPAGE;
648
649
650/**
651 * Clears the page structure.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_CLEAR(pPage) \
655 do { \
656 (pPage)->HCPhysX = 0; \
657 (pPage)->u2StateX = 0; \
658 (pPage)->fWrittenToX = 0; \
659 (pPage)->fSomethingElse = 0; \
660 (pPage)->idPageX = 0; \
661 (pPage)->u3Type = 0; \
662 (pPage)->u29B = 0; \
663 } while (0)
664
665/**
666 * Initializes the page structure.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670 do { \
671 (pPage)->HCPhysX = (_HCPhys); \
672 (pPage)->u2StateX = (_uState); \
673 (pPage)->fWrittenToX = 0; \
674 (pPage)->fSomethingElse = 0; \
675 (pPage)->idPageX = (_idPage); \
676 /*(pPage)->u3Type = (_uType); - later */ \
677 PGM_PAGE_SET_TYPE(pPage, _uType); \
678 (pPage)->u29B = 0; \
679 } while (0)
680
681/**
682 * Initializes the page structure of a ZERO page.
683 * @param pPage Pointer to the physical guest page tracking structure.
684 */
685#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
686 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
687/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
688# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
689 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
690
691
692/** @name The Page state, PGMPAGE::u2StateX.
693 * @{ */
694/** The zero page.
695 * This is a per-VM page that's never ever mapped writable. */
696#define PGM_PAGE_STATE_ZERO 0
697/** A allocated page.
698 * This is a per-VM page allocated from the page pool (or wherever
699 * we get MMIO2 pages from if the type is MMIO2).
700 */
701#define PGM_PAGE_STATE_ALLOCATED 1
702/** A allocated page that's being monitored for writes.
703 * The shadow page table mappings are read-only. When a write occurs, the
704 * fWrittenTo member is set, the page remapped as read-write and the state
705 * moved back to allocated. */
706#define PGM_PAGE_STATE_WRITE_MONITORED 2
707/** The page is shared, aka. copy-on-write.
708 * This is a page that's shared with other VMs. */
709#define PGM_PAGE_STATE_SHARED 3
710/** @} */
711
712
713/**
714 * Gets the page state.
715 * @returns page state (PGM_PAGE_STATE_*).
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
719
720/**
721 * Sets the page state.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 * @param _uState The new page state.
724 */
725#define PGM_PAGE_SET_STATE(pPage, _uState) \
726 do { (pPage)->u2StateX = (_uState); } while (0)
727
728
729/**
730 * Gets the host physical address of the guest page.
731 * @returns host physical address (RTHCPHYS).
732 * @param pPage Pointer to the physical guest page tracking structure.
733 */
734#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
735
736/**
737 * Sets the host physical address of the guest page.
738 * @param pPage Pointer to the physical guest page tracking structure.
739 * @param _HCPhys The new host physical address.
740 */
741#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
742 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
743 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
744
745/**
746 * Get the Page ID.
747 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
748 * @param pPage Pointer to the physical guest page tracking structure.
749 */
750#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
751/* later:
752#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
753 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
754*/
755/**
756 * Sets the Page ID.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
760/* later:
761#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
762 | ((_idPage) & 0xfff) \
763 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
764*/
765
766/**
767 * Get the Chunk ID.
768 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 */
771#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
772/* later:
773#if GMM_CHUNKID_SHIFT == 12
774# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
775#elif GMM_CHUNKID_SHIFT > 12
776# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
777#elif GMM_CHUNKID_SHIFT < 12
778# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
779 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
780#else
781# error "GMM_CHUNKID_SHIFT isn't defined or something."
782#endif
783*/
784
785/**
786 * Get the index of the page within the allocaiton chunk.
787 * @returns The page index.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
791/* later:
792#if GMM_CHUNKID_SHIFT <= 12
793# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
794#else
795# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
796 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
797#endif
798*/
799
800
801/**
802 * Gets the page type.
803 * @returns The page type.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
807
808/**
809 * Sets the page type.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 * @param _enmType The new page type (PGMPAGETYPE).
812 */
813#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
814 do { (pPage)->u3Type = (_enmType); } while (0)
815
816/**
817 * Checks if the page is marked for MMIO.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
822
823/**
824 * Checks if the page is backed by the ZERO page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
829
830/**
831 * Checks if the page is backed by a SHARED page.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
836
837
838/**
839 * Marks the paget as written to (for GMM change monitoring).
840 * @param pPage Pointer to the physical guest page tracking structure.
841 */
842#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
843
844/**
845 * Clears the written-to indicator.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
849
850/**
851 * Checks if the page was marked as written-to.
852 * @returns true/false.
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
856
857
858/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
859 *
860 * @remarks The values are assigned in order of priority, so we can calculate
861 * the correct state for a page with different handlers installed.
862 * @{ */
863/** No handler installed. */
864#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
865/** Monitoring is temporarily disabled. */
866#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
867/** Write access is monitored. */
868#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
869/** All access is monitored. */
870#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
871/** @} */
872
873/**
874 * Gets the physical access handler state of a page.
875 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
879
880/**
881 * Sets the physical access handler state of a page.
882 * @param pPage Pointer to the physical guest page tracking structure.
883 * @param _uState The new state value.
884 */
885#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
886 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
887
888/**
889 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
894
895/**
896 * Checks if the page has any active physical access handlers.
897 * @returns true/false
898 * @param pPage Pointer to the physical guest page tracking structure.
899 */
900#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
901
902
903/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
904 *
905 * @remarks The values are assigned in order of priority, so we can calculate
906 * the correct state for a page with different handlers installed.
907 * @{ */
908/** No handler installed. */
909#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
910/* 1 is reserved so the lineup is identical with the physical ones. */
911/** Write access is monitored. */
912#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
913/** All access is monitored. */
914#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
915/** @} */
916
917/**
918 * Gets the virtual access handler state of a page.
919 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
920 * @param pPage Pointer to the physical guest page tracking structure.
921 */
922#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
923
924/**
925 * Sets the virtual access handler state of a page.
926 * @param pPage Pointer to the physical guest page tracking structure.
927 * @param _uState The new state value.
928 */
929#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
930 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
931
932/**
933 * Checks if the page has any virtual access handlers.
934 * @returns true/false
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
938
939/**
940 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
941 * virtual handlers.
942 * @returns true/false
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
946
947
948
949/**
950 * Checks if the page has any access handlers, including temporarily disabled ones.
951 * @returns true/false
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
955 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
956 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
957
958/**
959 * Checks if the page has any active access handlers.
960 * @returns true/false
961 * @param pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
964 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
965 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
966
967/**
968 * Checks if the page has any active access handlers catching all accesses.
969 * @returns true/false
970 * @param pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
973 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
974 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
975
976
977
978
979/** @def PGM_PAGE_GET_TRACKING
980 * Gets the packed shadow page pool tracking data associated with a guest page.
981 * @returns uint16_t containing the data.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 */
984#define PGM_PAGE_GET_TRACKING(pPage) \
985 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
986
987/** @def PGM_PAGE_SET_TRACKING
988 * Sets the packed shadow page pool tracking data associated with a guest page.
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param u16TrackingData The tracking data to store.
991 */
992#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
993 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
994
995/** @def PGM_PAGE_GET_TD_CREFS
996 * Gets the @a cRefs tracking data member.
997 * @returns cRefs.
998 * @param pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_GET_TD_CREFS(pPage) \
1001 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1002
1003#define PGM_PAGE_GET_TD_IDX(pPage) \
1004 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1005
1006/**
1007 * Ram range for GC Phys to HC Phys conversion.
1008 *
1009 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1010 * conversions too, but we'll let MM handle that for now.
1011 *
1012 * This structure is used by linked lists in both GC and HC.
1013 */
1014typedef struct PGMRAMRANGE
1015{
1016 /** Start of the range. Page aligned. */
1017 RTGCPHYS GCPhys;
1018 /** Size of the range. (Page aligned of course). */
1019 RTGCPHYS cb;
1020 /** Pointer to the next RAM range - for R3. */
1021 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1022 /** Pointer to the next RAM range - for R0. */
1023 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1024 /** Pointer to the next RAM range - for RC. */
1025 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1026 /** PGM_RAM_RANGE_FLAGS_* flags. */
1027 uint32_t fFlags;
1028 /** Last address in the range (inclusive). Page aligned (-1). */
1029 RTGCPHYS GCPhysLast;
1030 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1031 R3PTRTYPE(void *) pvR3;
1032 /** The range description. */
1033 R3PTRTYPE(const char *) pszDesc;
1034 /** Pointer to self - R0 pointer. */
1035 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1036 /** Pointer to self - RC pointer. */
1037 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1038 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1039 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1040 /** Array of physical guest page tracking structures. */
1041 PGMPAGE aPages[1];
1042} PGMRAMRANGE;
1043/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1044typedef PGMRAMRANGE *PPGMRAMRANGE;
1045
1046/** @name PGMRAMRANGE::fFlags
1047 * @{ */
1048/** The RAM range is floating around as an independent guest mapping. */
1049#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1050/** @} */
1051
1052
1053/**
1054 * Per page tracking structure for ROM image.
1055 *
1056 * A ROM image may have a shadow page, in which case we may have
1057 * two pages backing it. This structure contains the PGMPAGE for
1058 * both while PGMRAMRANGE have a copy of the active one. It is
1059 * important that these aren't out of sync in any regard other
1060 * than page pool tracking data.
1061 */
1062typedef struct PGMROMPAGE
1063{
1064 /** The page structure for the virgin ROM page. */
1065 PGMPAGE Virgin;
1066 /** The page structure for the shadow RAM page. */
1067 PGMPAGE Shadow;
1068 /** The current protection setting. */
1069 PGMROMPROT enmProt;
1070 /** Pad the structure size to a multiple of 8. */
1071 uint32_t u32Padding;
1072} PGMROMPAGE;
1073/** Pointer to a ROM page tracking structure. */
1074typedef PGMROMPAGE *PPGMROMPAGE;
1075
1076
1077/**
1078 * A registered ROM image.
1079 *
1080 * This is needed to keep track of ROM image since they generally
1081 * intrude into a PGMRAMRANGE. It also keeps track of additional
1082 * info like the two page sets (read-only virgin and read-write shadow),
1083 * the current state of each page.
1084 *
1085 * Because access handlers cannot easily be executed in a different
1086 * context, the ROM ranges needs to be accessible and in all contexts.
1087 */
1088typedef struct PGMROMRANGE
1089{
1090 /** Pointer to the next range - R3. */
1091 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1092 /** Pointer to the next range - R0. */
1093 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1094 /** Pointer to the next range - RC. */
1095 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1096 /** Pointer alignment */
1097 RTRCPTR GCPtrAlignment;
1098 /** Address of the range. */
1099 RTGCPHYS GCPhys;
1100 /** Address of the last byte in the range. */
1101 RTGCPHYS GCPhysLast;
1102 /** Size of the range. */
1103 RTGCPHYS cb;
1104 /** The flags (PGMPHYS_ROM_FLAG_*). */
1105 uint32_t fFlags;
1106 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1107 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1108 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1109 * This is used for strictness checks. */
1110 R3PTRTYPE(const void *) pvOriginal;
1111 /** The ROM description. */
1112 R3PTRTYPE(const char *) pszDesc;
1113 /** The per page tracking structures. */
1114 PGMROMPAGE aPages[1];
1115} PGMROMRANGE;
1116/** Pointer to a ROM range. */
1117typedef PGMROMRANGE *PPGMROMRANGE;
1118
1119
1120/**
1121 * A registered MMIO2 (= Device RAM) range.
1122 *
1123 * There are a few reason why we need to keep track of these
1124 * registrations. One of them is the deregistration & cleanup
1125 * stuff, while another is that the PGMRAMRANGE associated with
1126 * such a region may have to be removed from the ram range list.
1127 *
1128 * Overlapping with a RAM range has to be 100% or none at all. The
1129 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1130 * meditation will be raised if a partial overlap or an overlap of
1131 * ROM pages is encountered. On an overlap we will free all the
1132 * existing RAM pages and put in the ram range pages instead.
1133 */
1134typedef struct PGMMMIO2RANGE
1135{
1136 /** The owner of the range. (a device) */
1137 PPDMDEVINSR3 pDevInsR3;
1138 /** Pointer to the ring-3 mapping of the allocation. */
1139 RTR3PTR pvR3;
1140 /** Pointer to the next range - R3. */
1141 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1142 /** Whether it's mapped or not. */
1143 bool fMapped;
1144 /** Whether it's overlapping or not. */
1145 bool fOverlapping;
1146 /** The PCI region number.
1147 * @remarks This ASSUMES that nobody will ever really need to have multiple
1148 * PCI devices with matching MMIO region numbers on a single device. */
1149 uint8_t iRegion;
1150 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1151 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1152 /** The associated RAM range. */
1153 PGMRAMRANGE RamRange;
1154} PGMMMIO2RANGE;
1155/** Pointer to a MMIO2 range. */
1156typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1157
1158
1159
1160
1161/**
1162 * PGMPhysRead/Write cache entry
1163 */
1164typedef struct PGMPHYSCACHEENTRY
1165{
1166 /** R3 pointer to physical page. */
1167 R3PTRTYPE(uint8_t *) pbR3;
1168 /** GC Physical address for cache entry */
1169 RTGCPHYS GCPhys;
1170#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1171 RTGCPHYS u32Padding0; /**< alignment padding. */
1172#endif
1173} PGMPHYSCACHEENTRY;
1174
1175/**
1176 * PGMPhysRead/Write cache to reduce REM memory access overhead
1177 */
1178typedef struct PGMPHYSCACHE
1179{
1180 /** Bitmap of valid cache entries */
1181 uint64_t aEntries;
1182 /** Cache entries */
1183 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1184} PGMPHYSCACHE;
1185
1186
1187/** Pointer to an allocation chunk ring-3 mapping. */
1188typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1189/** Pointer to an allocation chunk ring-3 mapping pointer. */
1190typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1191
1192/**
1193 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1194 *
1195 * The primary tree (Core) uses the chunk id as key.
1196 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1197 */
1198typedef struct PGMCHUNKR3MAP
1199{
1200 /** The key is the chunk id. */
1201 AVLU32NODECORE Core;
1202 /** The key is the ageing sequence number. */
1203 AVLLU32NODECORE AgeCore;
1204 /** The current age thingy. */
1205 uint32_t iAge;
1206 /** The current reference count. */
1207 uint32_t volatile cRefs;
1208 /** The current permanent reference count. */
1209 uint32_t volatile cPermRefs;
1210 /** The mapping address. */
1211 void *pv;
1212} PGMCHUNKR3MAP;
1213
1214/**
1215 * Allocation chunk ring-3 mapping TLB entry.
1216 */
1217typedef struct PGMCHUNKR3MAPTLBE
1218{
1219 /** The chunk id. */
1220 uint32_t volatile idChunk;
1221#if HC_ARCH_BITS == 64
1222 uint32_t u32Padding; /**< alignment padding. */
1223#endif
1224 /** The chunk map. */
1225#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1226 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1227#else
1228 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1229#endif
1230} PGMCHUNKR3MAPTLBE;
1231/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1232typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1233
1234/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1235 * @remark Must be a power of two value. */
1236#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1237
1238/**
1239 * Allocation chunk ring-3 mapping TLB.
1240 *
1241 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1242 * At first glance this might look kinda odd since AVL trees are
1243 * supposed to give the most optimial lookup times of all trees
1244 * due to their balancing. However, take a tree with 1023 nodes
1245 * in it, that's 10 levels, meaning that most searches has to go
1246 * down 9 levels before they find what they want. This isn't fast
1247 * compared to a TLB hit. There is the factor of cache misses,
1248 * and of course the problem with trees and branch prediction.
1249 * This is why we use TLBs in front of most of the trees.
1250 *
1251 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1252 * difficult when we switch to the new inlined AVL trees (from kStuff).
1253 */
1254typedef struct PGMCHUNKR3MAPTLB
1255{
1256 /** The TLB entries. */
1257 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1258} PGMCHUNKR3MAPTLB;
1259
1260/**
1261 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1262 * @returns Chunk TLB index.
1263 * @param idChunk The Chunk ID.
1264 */
1265#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1266
1267
1268/**
1269 * Ring-3 guest page mapping TLB entry.
1270 * @remarks used in ring-0 as well at the moment.
1271 */
1272typedef struct PGMPAGER3MAPTLBE
1273{
1274 /** Address of the page. */
1275 RTGCPHYS volatile GCPhys;
1276 /** The guest page. */
1277#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1278 R3PTRTYPE(PPGMPAGE) volatile pPage;
1279#else
1280 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1281#endif
1282 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1283#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1284 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1285#else
1286 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1287#endif
1288 /** The address */
1289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1290 R3PTRTYPE(void *) volatile pv;
1291#else
1292 R3R0PTRTYPE(void *) volatile pv;
1293#endif
1294#if HC_ARCH_BITS == 32
1295 uint32_t u32Padding; /**< alignment padding. */
1296#endif
1297} PGMPAGER3MAPTLBE;
1298/** Pointer to an entry in the HC physical TLB. */
1299typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1300
1301
1302/** The number of entries in the ring-3 guest page mapping TLB.
1303 * @remarks The value must be a power of two. */
1304#define PGM_PAGER3MAPTLB_ENTRIES 64
1305
1306/**
1307 * Ring-3 guest page mapping TLB.
1308 * @remarks used in ring-0 as well at the moment.
1309 */
1310typedef struct PGMPAGER3MAPTLB
1311{
1312 /** The TLB entries. */
1313 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1314} PGMPAGER3MAPTLB;
1315/** Pointer to the ring-3 guest page mapping TLB. */
1316typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1317
1318/**
1319 * Calculates the index of the TLB entry for the specified guest page.
1320 * @returns Physical TLB index.
1321 * @param GCPhys The guest physical address.
1322 */
1323#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1324
1325
1326/**
1327 * Mapping cache usage set entry.
1328 *
1329 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1330 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1331 * cache. If it's extended to include ring-3, well, then something will
1332 * have be changed here...
1333 */
1334typedef struct PGMMAPSETENTRY
1335{
1336 /** The mapping cache index. */
1337 uint16_t iPage;
1338 /** The number of references.
1339 * The max is UINT16_MAX - 1. */
1340 uint16_t cRefs;
1341#if HC_ARCH_BITS == 64
1342 uint32_t alignment;
1343#endif
1344 /** Pointer to the page. */
1345 RTR0PTR pvPage;
1346 /** The physical address for this entry. */
1347 RTHCPHYS HCPhys;
1348} PGMMAPSETENTRY;
1349/** Pointer to a mapping cache usage set entry. */
1350typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1351
1352/**
1353 * Mapping cache usage set.
1354 *
1355 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1356 * done during exits / traps. The set is
1357 */
1358typedef struct PGMMAPSET
1359{
1360 /** The number of occupied entries.
1361 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1362 * dynamic mappings. */
1363 uint32_t cEntries;
1364 /** The start of the current subset.
1365 * This is UINT32_MAX if no subset is currently open. */
1366 uint32_t iSubset;
1367 /** The index of the current CPU, only valid if the set is open. */
1368 int32_t iCpu;
1369#if HC_ARCH_BITS == 64
1370 uint32_t alignment;
1371#endif
1372 /** The entries. */
1373 PGMMAPSETENTRY aEntries[64];
1374 /** HCPhys -> iEntry fast lookup table.
1375 * Use PGMMAPSET_HASH for hashing.
1376 * The entries may or may not be valid, check against cEntries. */
1377 uint8_t aiHashTable[128];
1378} PGMMAPSET;
1379/** Pointer to the mapping cache set. */
1380typedef PGMMAPSET *PPGMMAPSET;
1381
1382/** PGMMAPSET::cEntries value for a closed set. */
1383#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1384
1385/** Hash function for aiHashTable. */
1386#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1387
1388/** The max fill size (strict builds). */
1389#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1390
1391
1392/** @name Context neutrual page mapper TLB.
1393 *
1394 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1395 * code is writting in a kind of context neutrual way. Time will show whether
1396 * this actually makes sense or not...
1397 *
1398 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1399 * context ends up using a global mapping cache on some platforms
1400 * (darwin).
1401 *
1402 * @{ */
1403/** @typedef PPGMPAGEMAPTLB
1404 * The page mapper TLB pointer type for the current context. */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB entry pointer type for the current context. */
1407/** @typedef PPGMPAGEMAPTLB
1408 * The page mapper TLB entry pointer pointer type for the current context. */
1409/** @def PGM_PAGEMAPTLB_ENTRIES
1410 * The number of TLB entries in the page mapper TLB for the current context. */
1411/** @def PGM_PAGEMAPTLB_IDX
1412 * Calculate the TLB index for a guest physical address.
1413 * @returns The TLB index.
1414 * @param GCPhys The guest physical address. */
1415/** @typedef PPGMPAGEMAP
1416 * Pointer to a page mapper unit for current context. */
1417/** @typedef PPPGMPAGEMAP
1418 * Pointer to a page mapper unit pointer for current context. */
1419#ifdef IN_RC
1420// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1421// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1422// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1423# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1424# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1425 typedef void * PPGMPAGEMAP;
1426 typedef void ** PPPGMPAGEMAP;
1427//#elif IN_RING0
1428// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1429// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1430// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1431//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1432//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1433// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1434// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1435#else
1436 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1437 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1438 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1439# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1440# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1441 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1442 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1443#endif
1444/** @} */
1445
1446
1447/** @name PGM Pool Indexes.
1448 * Aka. the unique shadow page identifier.
1449 * @{ */
1450/** NIL page pool IDX. */
1451#define NIL_PGMPOOL_IDX 0
1452/** The first normal index. */
1453#define PGMPOOL_IDX_FIRST_SPECIAL 1
1454/** Page directory (32-bit root). */
1455#define PGMPOOL_IDX_PD 1
1456/** Page Directory Pointer Table (PAE root). */
1457#define PGMPOOL_IDX_PDPT 2
1458/** AMD64 CR3 level index.*/
1459#define PGMPOOL_IDX_AMD64_CR3 3
1460/** Nested paging root.*/
1461#define PGMPOOL_IDX_NESTED_ROOT 4
1462/** The first normal index. */
1463#define PGMPOOL_IDX_FIRST 5
1464/** The last valid index. (inclusive, 14 bits) */
1465#define PGMPOOL_IDX_LAST 0x3fff
1466/** @} */
1467
1468/** The NIL index for the parent chain. */
1469#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1470
1471/**
1472 * Node in the chain linking a shadowed page to it's parent (user).
1473 */
1474#pragma pack(1)
1475typedef struct PGMPOOLUSER
1476{
1477 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1478 uint16_t iNext;
1479 /** The user page index. */
1480 uint16_t iUser;
1481 /** Index into the user table. */
1482 uint32_t iUserTable;
1483} PGMPOOLUSER, *PPGMPOOLUSER;
1484typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1485#pragma pack()
1486
1487
1488/** The NIL index for the phys ext chain. */
1489#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1490
1491/**
1492 * Node in the chain of physical cross reference extents.
1493 * @todo Calling this an 'extent' is not quite right, find a better name.
1494 */
1495#pragma pack(1)
1496typedef struct PGMPOOLPHYSEXT
1497{
1498 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1499 uint16_t iNext;
1500 /** The user page index. */
1501 uint16_t aidx[3];
1502} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1503typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1504#pragma pack()
1505
1506
1507/**
1508 * The kind of page that's being shadowed.
1509 */
1510typedef enum PGMPOOLKIND
1511{
1512 /** The virtual invalid 0 entry. */
1513 PGMPOOLKIND_INVALID = 0,
1514 /** The entry is free (=unused). */
1515 PGMPOOLKIND_FREE,
1516
1517 /** Shw: 32-bit page table; Gst: no paging */
1518 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1519 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1520 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1521 /** Shw: 32-bit page table; Gst: 4MB page. */
1522 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1523 /** Shw: PAE page table; Gst: no paging */
1524 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1525 /** Shw: PAE page table; Gst: 32-bit page table. */
1526 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1527 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1528 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1529 /** Shw: PAE page table; Gst: PAE page table. */
1530 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1531 /** Shw: PAE page table; Gst: 2MB page. */
1532 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1533
1534 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1535 PGMPOOLKIND_32BIT_PD,
1536 /** Shw: 32-bit page directory. Gst: no paging. */
1537 PGMPOOLKIND_32BIT_PD_PHYS,
1538 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1539 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1540 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1541 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1542 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1543 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1544 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1545 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1546 /** Shw: PAE page directory; Gst: PAE page directory. */
1547 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1548 /** Shw: PAE page directory; Gst: no paging. */
1549 PGMPOOLKIND_PAE_PD_PHYS,
1550
1551 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1552 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1553 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1554 PGMPOOLKIND_PAE_PDPT,
1555 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1556 PGMPOOLKIND_PAE_PDPT_PHYS,
1557
1558 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1559 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1560 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1561 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1562 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1563 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1564 /** Shw: 64-bit page directory table; Gst: no paging */
1565 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1566
1567 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1568 PGMPOOLKIND_64BIT_PML4,
1569
1570 /** Shw: EPT page directory pointer table; Gst: no paging */
1571 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1572 /** Shw: EPT page directory table; Gst: no paging */
1573 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1574 /** Shw: EPT page table; Gst: no paging */
1575 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1576
1577 /** Shw: Root Nested paging table. */
1578 PGMPOOLKIND_ROOT_NESTED,
1579
1580 /** The last valid entry. */
1581 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1582} PGMPOOLKIND;
1583
1584/**
1585 * The access attributes of the page; only applies to big pages.
1586 */
1587typedef enum
1588{
1589 PGMPOOLACCESS_DONTCARE = 0,
1590 PGMPOOLACCESS_USER_RW,
1591 PGMPOOLACCESS_USER_R,
1592 PGMPOOLACCESS_USER_RW_NX,
1593 PGMPOOLACCESS_USER_R_NX,
1594 PGMPOOLACCESS_SUPERVISOR_RW,
1595 PGMPOOLACCESS_SUPERVISOR_R,
1596 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1597 PGMPOOLACCESS_SUPERVISOR_R_NX
1598} PGMPOOLACCESS;
1599
1600/**
1601 * The tracking data for a page in the pool.
1602 */
1603typedef struct PGMPOOLPAGE
1604{
1605 /** AVL node code with the (R3) physical address of this page. */
1606 AVLOHCPHYSNODECORE Core;
1607 /** Pointer to the R3 mapping of the page. */
1608#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1609 R3PTRTYPE(void *) pvPageR3;
1610#else
1611 R3R0PTRTYPE(void *) pvPageR3;
1612#endif
1613 /** The guest physical address. */
1614#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1615 uint32_t Alignment0;
1616#endif
1617 RTGCPHYS GCPhys;
1618
1619 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1620 RTGCPTR pvLastAccessHandlerRip;
1621 RTGCPTR pvLastAccessHandlerFault;
1622 uint64_t cLastAccessHandlerCount;
1623
1624 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1625 uint8_t enmKind;
1626 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1627 uint8_t enmAccess;
1628 /** The index of this page. */
1629 uint16_t idx;
1630 /** The next entry in the list this page currently resides in.
1631 * It's either in the free list or in the GCPhys hash. */
1632 uint16_t iNext;
1633#ifdef PGMPOOL_WITH_USER_TRACKING
1634 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1635 uint16_t iUserHead;
1636 /** The number of present entries. */
1637 uint16_t cPresent;
1638 /** The first entry in the table which is present. */
1639 uint16_t iFirstPresent;
1640#endif
1641#ifdef PGMPOOL_WITH_MONITORING
1642 /** The number of modifications to the monitored page. */
1643 uint16_t cModifications;
1644 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1645 uint16_t iModifiedNext;
1646 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1647 uint16_t iModifiedPrev;
1648 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1649 uint16_t iMonitoredNext;
1650 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1651 uint16_t iMonitoredPrev;
1652#endif
1653#ifdef PGMPOOL_WITH_CACHE
1654 /** The next page in the age list. */
1655 uint16_t iAgeNext;
1656 /** The previous page in the age list. */
1657 uint16_t iAgePrev;
1658#endif /* PGMPOOL_WITH_CACHE */
1659 /** Used to indicate that the page is zeroed. */
1660 bool fZeroed;
1661 /** Used to indicate that a PT has non-global entries. */
1662 bool fSeenNonGlobal;
1663 /** Used to indicate that we're monitoring writes to the guest page. */
1664 bool fMonitored;
1665 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1666 * (All pages are in the age list.) */
1667 bool fCached;
1668 /** This is used by the R3 access handlers when invoked by an async thread.
1669 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1670 bool volatile fReusedFlushPending;
1671#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1672 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1673 bool fDirty;
1674#else
1675 bool bPadding1;
1676#endif
1677
1678 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1679 uint32_t cLocked;
1680#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1681 uint32_t idxDirty;
1682#else
1683 uint32_t bPadding2;
1684#endif
1685} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1686/** Pointer to a const pool page. */
1687typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1688
1689
1690#ifdef PGMPOOL_WITH_CACHE
1691/** The hash table size. */
1692# define PGMPOOL_HASH_SIZE 0x40
1693/** The hash function. */
1694# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1695#endif
1696
1697
1698/**
1699 * The shadow page pool instance data.
1700 *
1701 * It's all one big allocation made at init time, except for the
1702 * pages that is. The user nodes follows immediatly after the
1703 * page structures.
1704 */
1705typedef struct PGMPOOL
1706{
1707 /** The VM handle - R3 Ptr. */
1708 PVMR3 pVMR3;
1709 /** The VM handle - R0 Ptr. */
1710 PVMR0 pVMR0;
1711 /** The VM handle - RC Ptr. */
1712 PVMRC pVMRC;
1713 /** The max pool size. This includes the special IDs. */
1714 uint16_t cMaxPages;
1715 /** The current pool size. */
1716 uint16_t cCurPages;
1717 /** The head of the free page list. */
1718 uint16_t iFreeHead;
1719 /* Padding. */
1720 uint16_t u16Padding;
1721#ifdef PGMPOOL_WITH_USER_TRACKING
1722 /** Head of the chain of free user nodes. */
1723 uint16_t iUserFreeHead;
1724 /** The number of user nodes we've allocated. */
1725 uint16_t cMaxUsers;
1726 /** The number of present page table entries in the entire pool. */
1727 uint32_t cPresent;
1728 /** Pointer to the array of user nodes - RC pointer. */
1729 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1730 /** Pointer to the array of user nodes - R3 pointer. */
1731 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1732 /** Pointer to the array of user nodes - R0 pointer. */
1733 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1734#endif /* PGMPOOL_WITH_USER_TRACKING */
1735#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1736 /** Head of the chain of free phys ext nodes. */
1737 uint16_t iPhysExtFreeHead;
1738 /** The number of user nodes we've allocated. */
1739 uint16_t cMaxPhysExts;
1740 /** Pointer to the array of physical xref extent - RC pointer. */
1741 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1742 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1743 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1744 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1745 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1746#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1747#ifdef PGMPOOL_WITH_CACHE
1748 /** Hash table for GCPhys addresses. */
1749 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1750 /** The head of the age list. */
1751 uint16_t iAgeHead;
1752 /** The tail of the age list. */
1753 uint16_t iAgeTail;
1754 /** Set if the cache is enabled. */
1755 bool fCacheEnabled;
1756#endif /* PGMPOOL_WITH_CACHE */
1757#ifdef PGMPOOL_WITH_MONITORING
1758 /** Head of the list of modified pages. */
1759 uint16_t iModifiedHead;
1760 /** The current number of modified pages. */
1761 uint16_t cModifiedPages;
1762 /** Access handler, RC. */
1763 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1764 /** Access handler, R0. */
1765 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1766 /** Access handler, R3. */
1767 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1768 /** The access handler description (HC ptr). */
1769 R3PTRTYPE(const char *) pszAccessHandler;
1770# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1771 /* Next available slot. */
1772 uint32_t idxFreeDirtyPage;
1773 /* Number of active dirty pages. */
1774 uint32_t cDirtyPages;
1775 /* Array of current dirty pgm pool page indices. */
1776 uint16_t aIdxDirtyPages[8];
1777 uint64_t aDirtyPages[8][512];
1778# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1779#endif /* PGMPOOL_WITH_MONITORING */
1780 /** The number of pages currently in use. */
1781 uint16_t cUsedPages;
1782#ifdef VBOX_WITH_STATISTICS
1783 /** The high water mark for cUsedPages. */
1784 uint16_t cUsedPagesHigh;
1785 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1786 /** Profiling pgmPoolAlloc(). */
1787 STAMPROFILEADV StatAlloc;
1788 /** Profiling pgmPoolClearAll(). */
1789 STAMPROFILE StatClearAll;
1790 /** Profiling pgmPoolFlushAllInt(). */
1791 STAMPROFILE StatFlushAllInt;
1792 /** Profiling pgmPoolFlushPage(). */
1793 STAMPROFILE StatFlushPage;
1794 /** Profiling pgmPoolFree(). */
1795 STAMPROFILE StatFree;
1796 /** Profiling time spent zeroing pages. */
1797 STAMPROFILE StatZeroPage;
1798# ifdef PGMPOOL_WITH_USER_TRACKING
1799 /** Profiling of pgmPoolTrackDeref. */
1800 STAMPROFILE StatTrackDeref;
1801 /** Profiling pgmTrackFlushGCPhysPT. */
1802 STAMPROFILE StatTrackFlushGCPhysPT;
1803 /** Profiling pgmTrackFlushGCPhysPTs. */
1804 STAMPROFILE StatTrackFlushGCPhysPTs;
1805 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1806 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1807 /** Number of times we've been out of user records. */
1808 STAMCOUNTER StatTrackFreeUpOneUser;
1809# endif
1810# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1811 /** Profiling deref activity related tracking GC physical pages. */
1812 STAMPROFILE StatTrackDerefGCPhys;
1813 /** Number of linear searches for a HCPhys in the ram ranges. */
1814 STAMCOUNTER StatTrackLinearRamSearches;
1815 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1816 STAMCOUNTER StamTrackPhysExtAllocFailures;
1817# endif
1818# ifdef PGMPOOL_WITH_MONITORING
1819 /** Profiling the RC/R0 access handler. */
1820 STAMPROFILE StatMonitorRZ;
1821 /** Times we've failed interpreting the instruction. */
1822 STAMCOUNTER StatMonitorRZEmulateInstr;
1823 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1824 STAMPROFILE StatMonitorRZFlushPage;
1825 /* Times we've detected a page table reinit. */
1826 STAMCOUNTER StatMonitorRZFlushReinit;
1827 /** Times we've detected fork(). */
1828 STAMCOUNTER StatMonitorRZFork;
1829 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1830 STAMPROFILE StatMonitorRZHandled;
1831 /** Times we've failed interpreting a patch code instruction. */
1832 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1833 /** Times we've failed interpreting a patch code instruction during flushing. */
1834 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1835 /** The number of times we've seen rep prefixes we can't handle. */
1836 STAMCOUNTER StatMonitorRZRepPrefix;
1837 /** Profiling the REP STOSD cases we've handled. */
1838 STAMPROFILE StatMonitorRZRepStosd;
1839
1840 /** Profiling the R3 access handler. */
1841 STAMPROFILE StatMonitorR3;
1842 /** Times we've failed interpreting the instruction. */
1843 STAMCOUNTER StatMonitorR3EmulateInstr;
1844 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1845 STAMPROFILE StatMonitorR3FlushPage;
1846 /* Times we've detected a page table reinit. */
1847 STAMCOUNTER StatMonitorR3FlushReinit;
1848 /** Times we've detected fork(). */
1849 STAMCOUNTER StatMonitorR3Fork;
1850 /** Profiling the R3 access we've handled (except REP STOSD). */
1851 STAMPROFILE StatMonitorR3Handled;
1852 /** The number of times we've seen rep prefixes we can't handle. */
1853 STAMCOUNTER StatMonitorR3RepPrefix;
1854 /** Profiling the REP STOSD cases we've handled. */
1855 STAMPROFILE StatMonitorR3RepStosd;
1856 /** The number of times we're called in an async thread an need to flush. */
1857 STAMCOUNTER StatMonitorR3Async;
1858 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
1859 STAMCOUNTER StatResetDirtyPages;
1860 /** Times we've called pgmPoolAddDirtyPage. */
1861 STAMCOUNTER StatDirtyPage;
1862 /** Times we've had to flush duplicates for dirty page management. */
1863 STAMCOUNTER StatDirtyPageDupFlush;
1864
1865 /** The high wather mark for cModifiedPages. */
1866 uint16_t cModifiedPagesHigh;
1867 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1868# endif
1869# ifdef PGMPOOL_WITH_CACHE
1870 /** The number of cache hits. */
1871 STAMCOUNTER StatCacheHits;
1872 /** The number of cache misses. */
1873 STAMCOUNTER StatCacheMisses;
1874 /** The number of times we've got a conflict of 'kind' in the cache. */
1875 STAMCOUNTER StatCacheKindMismatches;
1876 /** Number of times we've been out of pages. */
1877 STAMCOUNTER StatCacheFreeUpOne;
1878 /** The number of cacheable allocations. */
1879 STAMCOUNTER StatCacheCacheable;
1880 /** The number of uncacheable allocations. */
1881 STAMCOUNTER StatCacheUncacheable;
1882# endif
1883#elif HC_ARCH_BITS == 64
1884 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1885#endif
1886 /** The AVL tree for looking up a page by its HC physical address. */
1887 AVLOHCPHYSTREE HCPhysTree;
1888 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1889 /** Array of pages. (cMaxPages in length)
1890 * The Id is the index into thist array.
1891 */
1892 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1893} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1894
1895
1896/** @def PGMPOOL_PAGE_2_PTR
1897 * Maps a pool page pool into the current context.
1898 *
1899 * @returns VBox status code.
1900 * @param pVM The VM handle.
1901 * @param pPage The pool page.
1902 *
1903 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1904 * small page window employeed by that function. Be careful.
1905 * @remark There is no need to assert on the result.
1906 */
1907#if defined(IN_RC)
1908# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1909#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1910# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1911#elif defined(VBOX_STRICT)
1912# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1913DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1914{
1915 Assert(pPage && pPage->pvPageR3);
1916 return pPage->pvPageR3;
1917}
1918#else
1919# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1920#endif
1921
1922/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1923 * Maps a pool page pool into the current context.
1924 *
1925 * @returns VBox status code.
1926 * @param pPGM Pointer to the PGM instance data.
1927 * @param pPage The pool page.
1928 *
1929 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1930 * small page window employeed by that function. Be careful.
1931 * @remark There is no need to assert on the result.
1932 */
1933#if defined(IN_RC)
1934# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1935#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1936# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1937#else
1938# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1939#endif
1940
1941/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1942 * Maps a pool page pool into the current context.
1943 *
1944 * @returns VBox status code.
1945 * @param pPGM Pointer to the PGMCPU instance data.
1946 * @param pPage The pool page.
1947 *
1948 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1949 * small page window employeed by that function. Be careful.
1950 * @remark There is no need to assert on the result.
1951 */
1952#if defined(IN_RC)
1953# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1954#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1955# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1956#else
1957# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1958#endif
1959
1960
1961/** @name Per guest page tracking data.
1962 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1963 * is to use more bits for it and split it up later on. But for now we'll play
1964 * safe and change as little as possible.
1965 *
1966 * The 16-bit word has two parts:
1967 *
1968 * The first 14-bit forms the @a idx field. It is either the index of a page in
1969 * the shadow page pool, or and index into the extent list.
1970 *
1971 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1972 * shadow page pool references to the page. If cRefs equals
1973 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1974 * (misnomer) table and not the shadow page pool.
1975 *
1976 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1977 * the 16-bit word.
1978 *
1979 * @{ */
1980/** The shift count for getting to the cRefs part. */
1981#define PGMPOOL_TD_CREFS_SHIFT 14
1982/** The mask applied after shifting the tracking data down by
1983 * PGMPOOL_TD_CREFS_SHIFT. */
1984#define PGMPOOL_TD_CREFS_MASK 0x3
1985/** The cRef value used to indiciate that the idx is the head of a
1986 * physical cross reference list. */
1987#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1988/** The shift used to get idx. */
1989#define PGMPOOL_TD_IDX_SHIFT 0
1990/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1991#define PGMPOOL_TD_IDX_MASK 0x3fff
1992/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1993 * simply too many mappings of this page. */
1994#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1995
1996/** @def PGMPOOL_TD_MAKE
1997 * Makes a 16-bit tracking data word.
1998 *
1999 * @returns tracking data.
2000 * @param cRefs The @a cRefs field. Must be within bounds!
2001 * @param idx The @a idx field. Must also be within bounds! */
2002#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2003
2004/** @def PGMPOOL_TD_GET_CREFS
2005 * Get the @a cRefs field from a tracking data word.
2006 *
2007 * @returns The @a cRefs field
2008 * @param u16 The tracking data word. */
2009#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2010
2011/** @def PGMPOOL_TD_GET_IDX
2012 * Get the @a idx field from a tracking data word.
2013 *
2014 * @returns The @a idx field
2015 * @param u16 The tracking data word. */
2016#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2017/** @} */
2018
2019
2020/**
2021 * Trees are using self relative offsets as pointers.
2022 * So, all its data, including the root pointer, must be in the heap for HC and GC
2023 * to have the same layout.
2024 */
2025typedef struct PGMTREES
2026{
2027 /** Physical access handlers (AVL range+offsetptr tree). */
2028 AVLROGCPHYSTREE PhysHandlers;
2029 /** Virtual access handlers (AVL range + GC ptr tree). */
2030 AVLROGCPTRTREE VirtHandlers;
2031 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2032 AVLROGCPHYSTREE PhysToVirtHandlers;
2033 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2034 AVLROGCPTRTREE HyperVirtHandlers;
2035} PGMTREES;
2036/** Pointer to PGM trees. */
2037typedef PGMTREES *PPGMTREES;
2038
2039
2040/** @name Paging mode macros
2041 * @{ */
2042#ifdef IN_RC
2043# define PGM_CTX(a,b) a##RC##b
2044# define PGM_CTX_STR(a,b) a "GC" b
2045# define PGM_CTX_DECL(type) VMMRCDECL(type)
2046#else
2047# ifdef IN_RING3
2048# define PGM_CTX(a,b) a##R3##b
2049# define PGM_CTX_STR(a,b) a "R3" b
2050# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2051# else
2052# define PGM_CTX(a,b) a##R0##b
2053# define PGM_CTX_STR(a,b) a "R0" b
2054# define PGM_CTX_DECL(type) VMMDECL(type)
2055# endif
2056#endif
2057
2058#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2059#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2060#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2061#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2062#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2063#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2064#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2065#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2066#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2067#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2068#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2069#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2070#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2071#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2072#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2073#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2074#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2075
2076#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2077#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2078#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2079#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2080#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2081#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2082#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2083#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2084#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2085#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2086#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2087#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2088#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2089#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2090#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2091#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2092#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2093
2094/* Shw_Gst */
2095#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2096#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2097#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2098#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2099#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2100#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2101#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2102#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2103#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2104#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2105#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2106#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2107#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2108#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2109#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2110#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2111#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2112#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2113#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2114
2115#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2116#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2117#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2118#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2119#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2120#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2121#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2122#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2123#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2124#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2125#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2126#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2127#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2128#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2129#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2130#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2131#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2132#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2133#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2134#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2135#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2136#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2137#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2138#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2139#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2140#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2141#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2142#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2143#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2144#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2145#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2146#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2147#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2148#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2149#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2150#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2151#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2152
2153#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2154#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2155/** @} */
2156
2157/**
2158 * Data for each paging mode.
2159 */
2160typedef struct PGMMODEDATA
2161{
2162 /** The guest mode type. */
2163 uint32_t uGstType;
2164 /** The shadow mode type. */
2165 uint32_t uShwType;
2166
2167 /** @name Function pointers for Shadow paging.
2168 * @{
2169 */
2170 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2171 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2172 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2173 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2174
2175 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2176 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2177
2178 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2179 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2180 /** @} */
2181
2182 /** @name Function pointers for Guest paging.
2183 * @{
2184 */
2185 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2186 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2187 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2188 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2189 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2190 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2191 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2192 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2193 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2194 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2195 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2196 /** @} */
2197
2198 /** @name Function pointers for Both Shadow and Guest paging.
2199 * @{
2200 */
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2202 /* no pfnR3BthTrap0eHandler */
2203 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2204 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2207 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2208#ifdef VBOX_STRICT
2209 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2210#endif
2211 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2212 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2213
2214 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2215 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2216 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2219 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2220#ifdef VBOX_STRICT
2221 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2222#endif
2223 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2224 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2225
2226 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2227 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2228 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2231 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2232#ifdef VBOX_STRICT
2233 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2234#endif
2235 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2236 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2237 /** @} */
2238} PGMMODEDATA, *PPGMMODEDATA;
2239
2240
2241
2242/**
2243 * Converts a PGM pointer into a VM pointer.
2244 * @returns Pointer to the VM structure the PGM is part of.
2245 * @param pPGM Pointer to PGM instance data.
2246 */
2247#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2248
2249/**
2250 * PGM Data (part of VM)
2251 */
2252typedef struct PGM
2253{
2254 /** Offset to the VM structure. */
2255 RTINT offVM;
2256 /** Offset of the PGMCPU structure relative to VMCPU. */
2257 RTINT offVCpuPGM;
2258
2259 /** @cfgm{RamPreAlloc, boolean, false}
2260 * Indicates whether the base RAM should all be allocated before starting
2261 * the VM (default), or if it should be allocated when first written to.
2262 */
2263 bool fRamPreAlloc;
2264 /** Alignment padding. */
2265 bool afAlignment0[11];
2266
2267 /*
2268 * This will be redefined at least two more times before we're done, I'm sure.
2269 * The current code is only to get on with the coding.
2270 * - 2004-06-10: initial version, bird.
2271 * - 2004-07-02: 1st time, bird.
2272 * - 2004-10-18: 2nd time, bird.
2273 * - 2005-07-xx: 3rd time, bird.
2274 */
2275
2276 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2277 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2278 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2279 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2280
2281 /** The host paging mode. (This is what SUPLib reports.) */
2282 SUPPAGINGMODE enmHostMode;
2283
2284 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2285 RTGCPHYS GCPhys4MBPSEMask;
2286
2287 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2288 * This is sorted by physical address and contains no overlapping ranges. */
2289 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2290 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2291 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2292 /** RC pointer corresponding to PGM::pRamRangesR3. */
2293 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2294 RTRCPTR alignment4; /**< structure alignment. */
2295
2296 /** Pointer to the list of ROM ranges - for R3.
2297 * This is sorted by physical address and contains no overlapping ranges. */
2298 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2299 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2300 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2301 /** RC pointer corresponding to PGM::pRomRangesR3. */
2302 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2303 /** Alignment padding. */
2304 RTRCPTR GCPtrPadding2;
2305
2306 /** Pointer to the list of MMIO2 ranges - for R3.
2307 * Registration order. */
2308 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2309
2310 /** PGM offset based trees - R3 Ptr. */
2311 R3PTRTYPE(PPGMTREES) pTreesR3;
2312 /** PGM offset based trees - R0 Ptr. */
2313 R0PTRTYPE(PPGMTREES) pTreesR0;
2314 /** PGM offset based trees - RC Ptr. */
2315 RCPTRTYPE(PPGMTREES) pTreesRC;
2316
2317 /** Linked list of GC mappings - for RC.
2318 * The list is sorted ascending on address.
2319 */
2320 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2321 /** Linked list of GC mappings - for HC.
2322 * The list is sorted ascending on address.
2323 */
2324 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2325 /** Linked list of GC mappings - for R0.
2326 * The list is sorted ascending on address.
2327 */
2328 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2329
2330 /** Pointer to the 5 page CR3 content mapping.
2331 * The first page is always the CR3 (in some form) while the 4 other pages
2332 * are used of the PDs in PAE mode. */
2333 RTGCPTR GCPtrCR3Mapping;
2334#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2335 uint32_t u32Alignment;
2336#endif
2337
2338 /** Indicates that PGMR3FinalizeMappings has been called and that further
2339 * PGMR3MapIntermediate calls will be rejected. */
2340 bool fFinalizedMappings;
2341 /** If set no conflict checks are required. (boolean) */
2342 bool fMappingsFixed;
2343 /** If set, then no mappings are put into the shadow page table. (boolean) */
2344 bool fDisableMappings;
2345 /** Size of fixed mapping */
2346 uint32_t cbMappingFixed;
2347 /** Base address (GC) of fixed mapping */
2348 RTGCPTR GCPtrMappingFixed;
2349 /** The address of the previous RAM range mapping. */
2350 RTGCPTR GCPtrPrevRamRangeMapping;
2351
2352 /** @name Intermediate Context
2353 * @{ */
2354 /** Pointer to the intermediate page directory - Normal. */
2355 R3PTRTYPE(PX86PD) pInterPD;
2356 /** Pointer to the intermedate page tables - Normal.
2357 * There are two page tables, one for the identity mapping and one for
2358 * the host context mapping (of the core code). */
2359 R3PTRTYPE(PX86PT) apInterPTs[2];
2360 /** Pointer to the intermedate page tables - PAE. */
2361 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2362 /** Pointer to the intermedate page directory - PAE. */
2363 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2364 /** Pointer to the intermedate page directory - PAE. */
2365 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2366 /** Pointer to the intermedate page-map level 4 - AMD64. */
2367 R3PTRTYPE(PX86PML4) pInterPaePML4;
2368 /** Pointer to the intermedate page directory - AMD64. */
2369 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2370 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2371 RTHCPHYS HCPhysInterPD;
2372 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2373 RTHCPHYS HCPhysInterPaePDPT;
2374 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2375 RTHCPHYS HCPhysInterPaePML4;
2376 /** @} */
2377
2378 /** Base address of the dynamic page mapping area.
2379 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2380 */
2381 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2382 /** The index of the last entry used in the dynamic page mapping area. */
2383 RTUINT iDynPageMapLast;
2384 /** Cache containing the last entries in the dynamic page mapping area.
2385 * The cache size is covering half of the mapping area. */
2386 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2387 /** Keep a lock counter for the full (!) mapping area. */
2388 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2389
2390 /** The address of the ring-0 mapping cache if we're making use of it. */
2391 RTR0PTR pvR0DynMapUsed;
2392
2393 /** PGM critical section.
2394 * This protects the physical & virtual access handlers, ram ranges,
2395 * and the page flag updating (some of it anyway).
2396 */
2397 PDMCRITSECT CritSect;
2398
2399 /** Pointer to SHW+GST mode data (function pointers).
2400 * The index into this table is made up from */
2401 R3PTRTYPE(PPGMMODEDATA) paModeData;
2402
2403 /** Shadow Page Pool - R3 Ptr. */
2404 R3PTRTYPE(PPGMPOOL) pPoolR3;
2405 /** Shadow Page Pool - R0 Ptr. */
2406 R0PTRTYPE(PPGMPOOL) pPoolR0;
2407 /** Shadow Page Pool - RC Ptr. */
2408 RCPTRTYPE(PPGMPOOL) pPoolRC;
2409
2410 /** We're not in a state which permits writes to guest memory.
2411 * (Only used in strict builds.) */
2412 bool fNoMorePhysWrites;
2413
2414 /**
2415 * Data associated with managing the ring-3 mappings of the allocation chunks.
2416 */
2417 struct
2418 {
2419 /** The chunk tree, ordered by chunk id. */
2420#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2421 R3PTRTYPE(PAVLU32NODECORE) pTree;
2422#else
2423 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2424#endif
2425 /** The chunk mapping TLB. */
2426 PGMCHUNKR3MAPTLB Tlb;
2427 /** The number of mapped chunks. */
2428 uint32_t c;
2429 /** The maximum number of mapped chunks.
2430 * @cfgm PGM/MaxRing3Chunks */
2431 uint32_t cMax;
2432 /** The chunk age tree, ordered by ageing sequence number. */
2433 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2434 /** The current time. */
2435 uint32_t iNow;
2436 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2437 uint32_t AgeingCountdown;
2438 } ChunkR3Map;
2439
2440 /**
2441 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2442 */
2443 PGMPAGER3MAPTLB PhysTlbHC;
2444
2445 /** @name The zero page.
2446 * @{ */
2447 /** The host physical address of the zero page. */
2448 RTHCPHYS HCPhysZeroPg;
2449 /** The ring-3 mapping of the zero page. */
2450 RTR3PTR pvZeroPgR3;
2451 /** The ring-0 mapping of the zero page. */
2452 RTR0PTR pvZeroPgR0;
2453 /** The GC mapping of the zero page. */
2454 RTGCPTR pvZeroPgRC;
2455#if GC_ARCH_BITS != 32
2456 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2457#endif
2458 /** @}*/
2459
2460 /** The number of handy pages. */
2461 uint32_t cHandyPages;
2462 /**
2463 * Array of handy pages.
2464 *
2465 * This array is used in a two way communication between pgmPhysAllocPage
2466 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2467 * an intermediary.
2468 *
2469 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2470 * (The current size of 32 pages, means 128 KB of handy memory.)
2471 */
2472 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2473
2474 /** @name Error injection.
2475 * @{ */
2476 /** Inject handy page allocation errors pretending we're completely out of
2477 * memory. */
2478 bool volatile fErrInjHandyPages;
2479 /** Padding. */
2480 bool afReserved[7];
2481 /** @} */
2482
2483 /** @name Release Statistics
2484 * @{ */
2485 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2486 uint32_t cPrivatePages; /**< The number of private pages. */
2487 uint32_t cSharedPages; /**< The number of shared pages. */
2488 uint32_t cZeroPages; /**< The number of zero backed pages. */
2489
2490 /** The number of times we were forced to change the hypervisor region location. */
2491 STAMCOUNTER cRelocations;
2492 /** @} */
2493
2494#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2495 /* R3 only: */
2496 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2497 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2498
2499 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2500 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2501 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2502 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2503 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2504 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2505 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2506 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2507 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2508 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2509 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2510 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2511 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2512 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2513 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2514 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2515 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2516 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2517/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2518 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2519 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2520/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2521
2522 /* RC only: */
2523 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2524 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2525 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2526 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2527
2528 STAMCOUNTER StatRZPhysRead;
2529 STAMCOUNTER StatRZPhysReadBytes;
2530 STAMCOUNTER StatRZPhysWrite;
2531 STAMCOUNTER StatRZPhysWriteBytes;
2532 STAMCOUNTER StatR3PhysRead;
2533 STAMCOUNTER StatR3PhysReadBytes;
2534 STAMCOUNTER StatR3PhysWrite;
2535 STAMCOUNTER StatR3PhysWriteBytes;
2536 STAMCOUNTER StatRCPhysRead;
2537 STAMCOUNTER StatRCPhysReadBytes;
2538 STAMCOUNTER StatRCPhysWrite;
2539 STAMCOUNTER StatRCPhysWriteBytes;
2540
2541 STAMCOUNTER StatRZPhysSimpleRead;
2542 STAMCOUNTER StatRZPhysSimpleReadBytes;
2543 STAMCOUNTER StatRZPhysSimpleWrite;
2544 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2545 STAMCOUNTER StatR3PhysSimpleRead;
2546 STAMCOUNTER StatR3PhysSimpleReadBytes;
2547 STAMCOUNTER StatR3PhysSimpleWrite;
2548 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2549 STAMCOUNTER StatRCPhysSimpleRead;
2550 STAMCOUNTER StatRCPhysSimpleReadBytes;
2551 STAMCOUNTER StatRCPhysSimpleWrite;
2552 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2553
2554# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2555 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2556 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2557 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2558 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2559 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2560 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2561# endif
2562#endif
2563} PGM;
2564/** Pointer to the PGM instance data. */
2565typedef PGM *PPGM;
2566
2567
2568/**
2569 * Converts a PGMCPU pointer into a VM pointer.
2570 * @returns Pointer to the VM structure the PGM is part of.
2571 * @param pPGM Pointer to PGMCPU instance data.
2572 */
2573#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2574
2575/**
2576 * Converts a PGMCPU pointer into a PGM pointer.
2577 * @returns Pointer to the VM structure the PGM is part of.
2578 * @param pPGM Pointer to PGMCPU instance data.
2579 */
2580#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2581
2582/**
2583 * PGMCPU Data (part of VMCPU).
2584 */
2585typedef struct PGMCPU
2586{
2587 /** Offset to the VM structure. */
2588 RTINT offVM;
2589 /** Offset to the VMCPU structure. */
2590 RTINT offVCpu;
2591 /** Offset of the PGM structure relative to VMCPU. */
2592 RTINT offPGM;
2593 RTINT uPadding0; /**< structure size alignment. */
2594
2595#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2596 /** Automatically tracked physical memory mapping set.
2597 * Ring-0 and strict raw-mode builds. */
2598 PGMMAPSET AutoSet;
2599#endif
2600
2601 /** A20 gate mask.
2602 * Our current approach to A20 emulation is to let REM do it and don't bother
2603 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2604 * But whould need arrise, we'll subject physical addresses to this mask. */
2605 RTGCPHYS GCPhysA20Mask;
2606 /** A20 gate state - boolean! */
2607 bool fA20Enabled;
2608
2609 /** What needs syncing (PGM_SYNC_*).
2610 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2611 * PGMFlushTLB, and PGMR3Load. */
2612 RTUINT fSyncFlags;
2613
2614 /** The shadow paging mode. */
2615 PGMMODE enmShadowMode;
2616 /** The guest paging mode. */
2617 PGMMODE enmGuestMode;
2618
2619 /** The current physical address representing in the guest CR3 register. */
2620 RTGCPHYS GCPhysCR3;
2621
2622 /** @name 32-bit Guest Paging.
2623 * @{ */
2624 /** The guest's page directory, R3 pointer. */
2625 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2626#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2627 /** The guest's page directory, R0 pointer. */
2628 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2629#endif
2630 /** The guest's page directory, static RC mapping. */
2631 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2632 /** @} */
2633
2634 /** @name PAE Guest Paging.
2635 * @{ */
2636 /** The guest's page directory pointer table, static RC mapping. */
2637 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2638 /** The guest's page directory pointer table, R3 pointer. */
2639 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2640#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2641 /** The guest's page directory pointer table, R0 pointer. */
2642 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2643#endif
2644
2645 /** The guest's page directories, R3 pointers.
2646 * These are individual pointers and don't have to be adjecent.
2647 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2648 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2649 /** The guest's page directories, R0 pointers.
2650 * Same restrictions as apGstPaePDsR3. */
2651#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2652 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2653#endif
2654 /** The guest's page directories, static GC mapping.
2655 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2656 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2657 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2658 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2659 RTGCPHYS aGCPhysGstPaePDs[4];
2660 /** The physical addresses of the monitored guest page directories (PAE). */
2661 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2662 /** @} */
2663
2664 /** @name AMD64 Guest Paging.
2665 * @{ */
2666 /** The guest's page directory pointer table, R3 pointer. */
2667 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2668#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2669 /** The guest's page directory pointer table, R0 pointer. */
2670 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2671#endif
2672 /** @} */
2673
2674 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2675 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2676 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2677 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2678 /** Pointer to the page of the current active CR3 - RC Ptr. */
2679 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2680 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2681 uint32_t iShwUser;
2682 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2683 uint32_t iShwUserTable;
2684# if HC_ARCH_BITS == 64
2685 RTRCPTR alignment6; /**< structure size alignment. */
2686# endif
2687 /** @} */
2688
2689 /** @name Function pointers for Shadow paging.
2690 * @{
2691 */
2692 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2693 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2694 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2695 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2696
2697 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2698 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2699
2700 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2701 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2702
2703 /** @} */
2704
2705 /** @name Function pointers for Guest paging.
2706 * @{
2707 */
2708 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2709 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2710 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2711 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2712 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2713 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2714 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2715 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2716#if HC_ARCH_BITS == 64
2717 RTRCPTR alignment3; /**< structure size alignment. */
2718#endif
2719
2720 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2721 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2722 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2723 /** @} */
2724
2725 /** @name Function pointers for Both Shadow and Guest paging.
2726 * @{
2727 */
2728 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2729 /* no pfnR3BthTrap0eHandler */
2730 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2731 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2732 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2733 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2734 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2735 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2736 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2737 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2738
2739 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2740 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2741 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2742 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2743 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2744 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2745 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2746 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2747 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2748
2749 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2750 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2751 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2752 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2753 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2754 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2755 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2756 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2757 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2758#if HC_ARCH_BITS == 64
2759 RTRCPTR alignment2; /**< structure size alignment. */
2760#endif
2761 /** @} */
2762
2763 /** For saving stack space, the disassembler state is allocated here instead of
2764 * on the stack.
2765 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2766 union
2767 {
2768 /** The disassembler scratch space. */
2769 DISCPUSTATE DisState;
2770 /** Padding. */
2771 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2772 };
2773
2774 /* Count the number of pgm pool access handler calls. */
2775 uint64_t cPoolAccessHandler;
2776
2777 /** @name Release Statistics
2778 * @{ */
2779 /** The number of times the guest has switched mode since last reset or statistics reset. */
2780 STAMCOUNTER cGuestModeChanges;
2781 /** @} */
2782
2783#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2784 /** @name Statistics
2785 * @{ */
2786 /** RC: Which statistic this \#PF should be attributed to. */
2787 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2788 RTRCPTR padding0;
2789 /** R0: Which statistic this \#PF should be attributed to. */
2790 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2791 RTR0PTR padding1;
2792
2793 /* Common */
2794 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2795 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2796
2797 /* R0 only: */
2798 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2799 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2800 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2801 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2802 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2803 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2804 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2805 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2806 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2807 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2808 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2809 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2810 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2811 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2812 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2813 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2814 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2815 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2816 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2817 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2818 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2819 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2820 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2821 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2822 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2823 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2824
2825 /* RZ only: */
2826 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2827 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2828 STAMPROFILE StatRZTrap0eTimeSyncPT;
2829 STAMPROFILE StatRZTrap0eTimeMapping;
2830 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2831 STAMPROFILE StatRZTrap0eTimeHandlers;
2832 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2833 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2834 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2835 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2836 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2837 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2838 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2839 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2840 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2841 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2842 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2843 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2844 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2845 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2846 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2847 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2848 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2849 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2850 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2851 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2852 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2853 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2854 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2856 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2857 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2858 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2859 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2860 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2861 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2862 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2863 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2864 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2865 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2866 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2867 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2868 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2869 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2870 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2871 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2872 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2873 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2874 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2875
2876 /* HC - R3 and (maybe) R0: */
2877
2878 /* RZ & R3: */
2879 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2880 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2881 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2882 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2883 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2884 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2885 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2886 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2887 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2888 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2889 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2890 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2891 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2892 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2893 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2894 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2895 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2896 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2897 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2898 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2899 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2900 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2901 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
2902 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2903 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2904 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2905 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2906 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2907 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2908 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2909 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2910 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2911 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2912 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2913 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2914 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2915 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2916 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2917 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2918 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2919 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2920 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2921 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2922 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2923
2924 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2925 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2926 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2927 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2928 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2929 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2930 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2931 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2932 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2933 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2934 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2935 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2936 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2937 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2938 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2939 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2940 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2941 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2942 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2943 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2944 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2945 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2946 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2947 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2948 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2949 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2950 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2951 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2952 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2953 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2954 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2955 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2956 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2957 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2958 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2959 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2960 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2961 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2962 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2963 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2964 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2965 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2966 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2967 /** @} */
2968#endif /* VBOX_WITH_STATISTICS */
2969} PGMCPU;
2970/** Pointer to the per-cpu PGM data. */
2971typedef PGMCPU *PPGMCPU;
2972
2973
2974/** @name PGM::fSyncFlags Flags
2975 * @{
2976 */
2977/** Updates the virtual access handler state bit in PGMPAGE. */
2978#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2979/** Always sync CR3. */
2980#define PGM_SYNC_ALWAYS RT_BIT(1)
2981/** Check monitoring on next CR3 (re)load and invalidate page.
2982 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2983#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2984/** Check guest mapping in SyncCR3. */
2985#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2986/** Clear the page pool (a light weight flush). */
2987#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2988#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2989/** @} */
2990
2991
2992RT_C_DECLS_BEGIN
2993
2994int pgmLock(PVM pVM);
2995void pgmUnlock(PVM pVM);
2996
2997int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2998int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2999PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3000void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3001DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3002
3003void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3004bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3005void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3006int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3007DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3008#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3009void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3010#else
3011# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3012#endif
3013DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3014
3015
3016int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3017int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3018int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3019int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3020int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3021int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3022int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3023int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3024int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3025VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3026#ifdef IN_RING3
3027void pgmR3PhysRelinkRamRanges(PVM pVM);
3028int pgmR3PhysRamPreAllocate(PVM pVM);
3029int pgmR3PhysRamReset(PVM pVM);
3030int pgmR3PhysRomReset(PVM pVM);
3031int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3032
3033int pgmR3PoolInit(PVM pVM);
3034void pgmR3PoolRelocate(PVM pVM);
3035void pgmR3PoolReset(PVM pVM);
3036
3037#endif /* IN_RING3 */
3038#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3039int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3040#endif
3041int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3042
3043DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3044{
3045 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3046}
3047
3048void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3049void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3050int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3051void pgmPoolClearAll(PVM pVM);
3052PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3053int pgmPoolSyncCR3(PVMCPU pVCpu);
3054int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3055uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3056void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3057void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3058#ifdef PGMPOOL_WITH_MONITORING
3059void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3060int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3061void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3062#endif
3063
3064void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3065void pgmPoolResetDirtyPages(PVM pVM, bool fForceRemoval = false);
3066
3067int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3068int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3069
3070void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3071void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3072int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3073int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3074
3075int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3076#ifndef IN_RC
3077int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3078#endif
3079int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3080
3081PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3082PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3083PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3084PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3085
3086RT_C_DECLS_END
3087
3088
3089/**
3090 * Gets the PGMRAMRANGE structure for a guest page.
3091 *
3092 * @returns Pointer to the RAM range on success.
3093 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3094 *
3095 * @param pPGM PGM handle.
3096 * @param GCPhys The GC physical address.
3097 */
3098DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3099{
3100 /*
3101 * Optimize for the first range.
3102 */
3103 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3104 RTGCPHYS off = GCPhys - pRam->GCPhys;
3105 if (RT_UNLIKELY(off >= pRam->cb))
3106 {
3107 do
3108 {
3109 pRam = pRam->CTX_SUFF(pNext);
3110 if (RT_UNLIKELY(!pRam))
3111 break;
3112 off = GCPhys - pRam->GCPhys;
3113 } while (off >= pRam->cb);
3114 }
3115 return pRam;
3116}
3117
3118
3119/**
3120 * Gets the PGMPAGE structure for a guest page.
3121 *
3122 * @returns Pointer to the page on success.
3123 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3124 *
3125 * @param pPGM PGM handle.
3126 * @param GCPhys The GC physical address.
3127 */
3128DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3129{
3130 /*
3131 * Optimize for the first range.
3132 */
3133 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3134 RTGCPHYS off = GCPhys - pRam->GCPhys;
3135 if (RT_UNLIKELY(off >= pRam->cb))
3136 {
3137 do
3138 {
3139 pRam = pRam->CTX_SUFF(pNext);
3140 if (RT_UNLIKELY(!pRam))
3141 return NULL;
3142 off = GCPhys - pRam->GCPhys;
3143 } while (off >= pRam->cb);
3144 }
3145 return &pRam->aPages[off >> PAGE_SHIFT];
3146}
3147
3148
3149/**
3150 * Gets the PGMPAGE structure for a guest page.
3151 *
3152 * Old Phys code: Will make sure the page is present.
3153 *
3154 * @returns VBox status code.
3155 * @retval VINF_SUCCESS and a valid *ppPage on success.
3156 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3157 *
3158 * @param pPGM PGM handle.
3159 * @param GCPhys The GC physical address.
3160 * @param ppPage Where to store the page poitner on success.
3161 */
3162DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3163{
3164 /*
3165 * Optimize for the first range.
3166 */
3167 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3168 RTGCPHYS off = GCPhys - pRam->GCPhys;
3169 if (RT_UNLIKELY(off >= pRam->cb))
3170 {
3171 do
3172 {
3173 pRam = pRam->CTX_SUFF(pNext);
3174 if (RT_UNLIKELY(!pRam))
3175 {
3176 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3177 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3178 }
3179 off = GCPhys - pRam->GCPhys;
3180 } while (off >= pRam->cb);
3181 }
3182 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3183 return VINF_SUCCESS;
3184}
3185
3186
3187
3188
3189/**
3190 * Gets the PGMPAGE structure for a guest page.
3191 *
3192 * Old Phys code: Will make sure the page is present.
3193 *
3194 * @returns VBox status code.
3195 * @retval VINF_SUCCESS and a valid *ppPage on success.
3196 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3197 *
3198 * @param pPGM PGM handle.
3199 * @param GCPhys The GC physical address.
3200 * @param ppPage Where to store the page poitner on success.
3201 * @param ppRamHint Where to read and store the ram list hint.
3202 * The caller initializes this to NULL before the call.
3203 */
3204DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3205{
3206 RTGCPHYS off;
3207 PPGMRAMRANGE pRam = *ppRamHint;
3208 if ( !pRam
3209 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3210 {
3211 pRam = pPGM->CTX_SUFF(pRamRanges);
3212 off = GCPhys - pRam->GCPhys;
3213 if (RT_UNLIKELY(off >= pRam->cb))
3214 {
3215 do
3216 {
3217 pRam = pRam->CTX_SUFF(pNext);
3218 if (RT_UNLIKELY(!pRam))
3219 {
3220 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3221 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3222 }
3223 off = GCPhys - pRam->GCPhys;
3224 } while (off >= pRam->cb);
3225 }
3226 *ppRamHint = pRam;
3227 }
3228 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3229 return VINF_SUCCESS;
3230}
3231
3232
3233/**
3234 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3235 *
3236 * @returns Pointer to the page on success.
3237 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3238 *
3239 * @param pPGM PGM handle.
3240 * @param GCPhys The GC physical address.
3241 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3242 */
3243DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3244{
3245 /*
3246 * Optimize for the first range.
3247 */
3248 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3249 RTGCPHYS off = GCPhys - pRam->GCPhys;
3250 if (RT_UNLIKELY(off >= pRam->cb))
3251 {
3252 do
3253 {
3254 pRam = pRam->CTX_SUFF(pNext);
3255 if (RT_UNLIKELY(!pRam))
3256 return NULL;
3257 off = GCPhys - pRam->GCPhys;
3258 } while (off >= pRam->cb);
3259 }
3260 *ppRam = pRam;
3261 return &pRam->aPages[off >> PAGE_SHIFT];
3262}
3263
3264
3265/**
3266 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3267 *
3268 * @returns Pointer to the page on success.
3269 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3270 *
3271 * @param pPGM PGM handle.
3272 * @param GCPhys The GC physical address.
3273 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3274 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3275 */
3276DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3277{
3278 /*
3279 * Optimize for the first range.
3280 */
3281 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3282 RTGCPHYS off = GCPhys - pRam->GCPhys;
3283 if (RT_UNLIKELY(off >= pRam->cb))
3284 {
3285 do
3286 {
3287 pRam = pRam->CTX_SUFF(pNext);
3288 if (RT_UNLIKELY(!pRam))
3289 {
3290 *ppRam = NULL; /* Shut up silly GCC warnings. */
3291 *ppPage = NULL; /* ditto */
3292 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3293 }
3294 off = GCPhys - pRam->GCPhys;
3295 } while (off >= pRam->cb);
3296 }
3297 *ppRam = pRam;
3298 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3299 return VINF_SUCCESS;
3300}
3301
3302
3303/**
3304 * Convert GC Phys to HC Phys.
3305 *
3306 * @returns VBox status.
3307 * @param pPGM PGM handle.
3308 * @param GCPhys The GC physical address.
3309 * @param pHCPhys Where to store the corresponding HC physical address.
3310 *
3311 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3312 * Avoid when writing new code!
3313 */
3314DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3315{
3316 PPGMPAGE pPage;
3317 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3318 if (RT_FAILURE(rc))
3319 return rc;
3320 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3321 return VINF_SUCCESS;
3322}
3323
3324#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3325
3326/**
3327 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3328 * optimizes access to pages already in the set.
3329 *
3330 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3331 * @param pPGM Pointer to the PVM instance data.
3332 * @param HCPhys The physical address of the page.
3333 * @param ppv Where to store the mapping address.
3334 */
3335DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3336{
3337 PVM pVM = PGM2VM(pPGM);
3338 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3339 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3340
3341 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3342 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3343 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3344
3345 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3346 unsigned iEntry = pSet->aiHashTable[iHash];
3347 if ( iEntry < pSet->cEntries
3348 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3349 {
3350 *ppv = pSet->aEntries[iEntry].pvPage;
3351 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3352 }
3353 else
3354 {
3355 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3356 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3357 }
3358
3359 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3360 return VINF_SUCCESS;
3361}
3362
3363
3364/**
3365 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3366 * access to pages already in the set.
3367 *
3368 * @returns See PGMDynMapGCPage.
3369 * @param pPGM Pointer to the PVM instance data.
3370 * @param HCPhys The physical address of the page.
3371 * @param ppv Where to store the mapping address.
3372 */
3373DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3374{
3375 PVM pVM = PGM2VM(pPGM);
3376 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3377
3378 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3379 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3380
3381 /*
3382 * Get the ram range.
3383 */
3384 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3385 RTGCPHYS off = GCPhys - pRam->GCPhys;
3386 if (RT_UNLIKELY(off >= pRam->cb
3387 /** @todo || page state stuff */))
3388 {
3389 /* This case is not counted into StatR0DynMapGCPageInl. */
3390 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3391 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3392 }
3393
3394 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3395 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3396
3397 /*
3398 * pgmR0DynMapHCPageInlined with out stats.
3399 */
3400 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3401 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3402 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3403
3404 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3405 unsigned iEntry = pSet->aiHashTable[iHash];
3406 if ( iEntry < pSet->cEntries
3407 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3408 {
3409 *ppv = pSet->aEntries[iEntry].pvPage;
3410 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3411 }
3412 else
3413 {
3414 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3415 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3416 }
3417
3418 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3419 return VINF_SUCCESS;
3420}
3421
3422
3423/**
3424 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3425 * access to pages already in the set.
3426 *
3427 * @returns See PGMDynMapGCPage.
3428 * @param pPGM Pointer to the PVM instance data.
3429 * @param HCPhys The physical address of the page.
3430 * @param ppv Where to store the mapping address.
3431 */
3432DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3433{
3434 PVM pVM = PGM2VM(pPGM);
3435 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3436
3437 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3438
3439 /*
3440 * Get the ram range.
3441 */
3442 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3443 RTGCPHYS off = GCPhys - pRam->GCPhys;
3444 if (RT_UNLIKELY(off >= pRam->cb
3445 /** @todo || page state stuff */))
3446 {
3447 /* This case is not counted into StatR0DynMapGCPageInl. */
3448 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3449 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3450 }
3451
3452 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3453 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3454
3455 /*
3456 * pgmR0DynMapHCPageInlined with out stats.
3457 */
3458 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3459 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3460 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3461
3462 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3463 unsigned iEntry = pSet->aiHashTable[iHash];
3464 if ( iEntry < pSet->cEntries
3465 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3466 {
3467 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3468 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3469 }
3470 else
3471 {
3472 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3473 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3474 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3475 }
3476
3477 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3478 return VINF_SUCCESS;
3479}
3480
3481#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3482#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3483
3484/**
3485 * Maps the page into current context (RC and maybe R0).
3486 *
3487 * @returns pointer to the mapping.
3488 * @param pVM Pointer to the PGM instance data.
3489 * @param pPage The page.
3490 */
3491DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3492{
3493 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3494 {
3495 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3496 void *pv;
3497# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3498 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3499# else
3500 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3501# endif
3502 return pv;
3503 }
3504 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3505}
3506
3507/**
3508 * Temporarily maps one host page specified by HC physical address, returning
3509 * pointer within the page.
3510 *
3511 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3512 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3513 *
3514 * @returns The address corresponding to HCPhys.
3515 * @param pPGM Pointer to the PVM instance data.
3516 * @param HCPhys HC Physical address of the page.
3517 */
3518DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3519{
3520 void *pv;
3521# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3522 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3523# else
3524 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3525# endif
3526 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3527 return pv;
3528}
3529
3530#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3531#ifndef IN_RC
3532
3533/**
3534 * Queries the Physical TLB entry for a physical guest page,
3535 * attempting to load the TLB entry if necessary.
3536 *
3537 * @returns VBox status code.
3538 * @retval VINF_SUCCESS on success
3539 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3540 *
3541 * @param pPGM The PGM instance handle.
3542 * @param GCPhys The address of the guest page.
3543 * @param ppTlbe Where to store the pointer to the TLB entry.
3544 */
3545DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3546{
3547 int rc;
3548 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3549 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3550 {
3551 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3552 rc = VINF_SUCCESS;
3553 }
3554 else
3555 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3556 *ppTlbe = pTlbe;
3557 return rc;
3558}
3559
3560
3561/**
3562 * Queries the Physical TLB entry for a physical guest page,
3563 * attempting to load the TLB entry if necessary.
3564 *
3565 * @returns VBox status code.
3566 * @retval VINF_SUCCESS on success
3567 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3568 *
3569 * @param pPGM The PGM instance handle.
3570 * @param pPage Pointer to the PGMPAGE structure corresponding to
3571 * GCPhys.
3572 * @param GCPhys The address of the guest page.
3573 * @param ppTlbe Where to store the pointer to the TLB entry.
3574 */
3575DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3576{
3577 int rc;
3578 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3579 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3580 {
3581 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3582 rc = VINF_SUCCESS;
3583 }
3584 else
3585 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3586 *ppTlbe = pTlbe;
3587 return rc;
3588}
3589
3590#endif /* !IN_RC */
3591
3592/**
3593 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3594 * Takes PSE-36 into account.
3595 *
3596 * @returns guest physical address
3597 * @param pPGM Pointer to the PGM instance data.
3598 * @param Pde Guest Pde
3599 */
3600DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3601{
3602 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3603 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3604
3605 return GCPhys & pPGM->GCPhys4MBPSEMask;
3606}
3607
3608
3609/**
3610 * Gets the page directory entry for the specified address (32-bit paging).
3611 *
3612 * @returns The page directory entry in question.
3613 * @param pPGM Pointer to the PGM instance data.
3614 * @param GCPtr The address.
3615 */
3616DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3617{
3618#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3619 PCX86PD pGuestPD = NULL;
3620 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3621 if (RT_FAILURE(rc))
3622 {
3623 X86PDE ZeroPde = {0};
3624 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3625 }
3626#else
3627 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3628# ifdef IN_RING3
3629 if (!pGuestPD)
3630 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3631# endif
3632#endif
3633 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3634}
3635
3636
3637/**
3638 * Gets the address of a specific page directory entry (32-bit paging).
3639 *
3640 * @returns Pointer the page directory entry in question.
3641 * @param pPGM Pointer to the PGM instance data.
3642 * @param GCPtr The address.
3643 */
3644DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3645{
3646#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3647 PX86PD pGuestPD = NULL;
3648 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3649 AssertRCReturn(rc, NULL);
3650#else
3651 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3652# ifdef IN_RING3
3653 if (!pGuestPD)
3654 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3655# endif
3656#endif
3657 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3658}
3659
3660
3661/**
3662 * Gets the address the guest page directory (32-bit paging).
3663 *
3664 * @returns Pointer the page directory entry in question.
3665 * @param pPGM Pointer to the PGM instance data.
3666 */
3667DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3668{
3669#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3670 PX86PD pGuestPD = NULL;
3671 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3672 AssertRCReturn(rc, NULL);
3673#else
3674 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3675# ifdef IN_RING3
3676 if (!pGuestPD)
3677 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3678# endif
3679#endif
3680 return pGuestPD;
3681}
3682
3683
3684/**
3685 * Gets the guest page directory pointer table.
3686 *
3687 * @returns Pointer to the page directory in question.
3688 * @returns NULL if the page directory is not present or on an invalid page.
3689 * @param pPGM Pointer to the PGM instance data.
3690 */
3691DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3692{
3693#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3694 PX86PDPT pGuestPDPT = NULL;
3695 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3696 AssertRCReturn(rc, NULL);
3697#else
3698 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3699# ifdef IN_RING3
3700 if (!pGuestPDPT)
3701 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3702# endif
3703#endif
3704 return pGuestPDPT;
3705}
3706
3707
3708/**
3709 * Gets the guest page directory pointer table entry for the specified address.
3710 *
3711 * @returns Pointer to the page directory in question.
3712 * @returns NULL if the page directory is not present or on an invalid page.
3713 * @param pPGM Pointer to the PGM instance data.
3714 * @param GCPtr The address.
3715 */
3716DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3717{
3718 AssertGCPtr32(GCPtr);
3719
3720#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3721 PX86PDPT pGuestPDPT = 0;
3722 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3723 AssertRCReturn(rc, 0);
3724#else
3725 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3726# ifdef IN_RING3
3727 if (!pGuestPDPT)
3728 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3729# endif
3730#endif
3731 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3732}
3733
3734
3735/**
3736 * Gets the page directory for the specified address.
3737 *
3738 * @returns Pointer to the page directory in question.
3739 * @returns NULL if the page directory is not present or on an invalid page.
3740 * @param pPGM Pointer to the PGM instance data.
3741 * @param GCPtr The address.
3742 */
3743DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3744{
3745 AssertGCPtr32(GCPtr);
3746
3747 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3748 AssertReturn(pGuestPDPT, NULL);
3749 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3750 if (pGuestPDPT->a[iPdpt].n.u1Present)
3751 {
3752#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3753 PX86PDPAE pGuestPD = NULL;
3754 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3755 AssertRCReturn(rc, NULL);
3756#else
3757 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3758 if ( !pGuestPD
3759 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3760 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3761#endif
3762 return pGuestPD;
3763 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3764 }
3765 return NULL;
3766}
3767
3768
3769/**
3770 * Gets the page directory entry for the specified address.
3771 *
3772 * @returns Pointer to the page directory entry in question.
3773 * @returns NULL if the page directory is not present or on an invalid page.
3774 * @param pPGM Pointer to the PGM instance data.
3775 * @param GCPtr The address.
3776 */
3777DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3778{
3779 AssertGCPtr32(GCPtr);
3780
3781 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3782 AssertReturn(pGuestPDPT, NULL);
3783 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3784 if (pGuestPDPT->a[iPdpt].n.u1Present)
3785 {
3786 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3787#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3788 PX86PDPAE pGuestPD = NULL;
3789 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3790 AssertRCReturn(rc, NULL);
3791#else
3792 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3793 if ( !pGuestPD
3794 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3795 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3796#endif
3797 return &pGuestPD->a[iPD];
3798 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3799 }
3800 return NULL;
3801}
3802
3803
3804/**
3805 * Gets the page directory entry for the specified address.
3806 *
3807 * @returns The page directory entry in question.
3808 * @returns A non-present entry if the page directory is not present or on an invalid page.
3809 * @param pPGM Pointer to the PGM instance data.
3810 * @param GCPtr The address.
3811 */
3812DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3813{
3814 AssertGCPtr32(GCPtr);
3815 X86PDEPAE ZeroPde = {0};
3816 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3817 if (RT_LIKELY(pGuestPDPT))
3818 {
3819 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3820 if (pGuestPDPT->a[iPdpt].n.u1Present)
3821 {
3822 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3823#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3824 PX86PDPAE pGuestPD = NULL;
3825 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3826 AssertRCReturn(rc, ZeroPde);
3827#else
3828 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3829 if ( !pGuestPD
3830 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3831 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3832#endif
3833 return pGuestPD->a[iPD];
3834 }
3835 }
3836 return ZeroPde;
3837}
3838
3839
3840/**
3841 * Gets the page directory pointer table entry for the specified address
3842 * and returns the index into the page directory
3843 *
3844 * @returns Pointer to the page directory in question.
3845 * @returns NULL if the page directory is not present or on an invalid page.
3846 * @param pPGM Pointer to the PGM instance data.
3847 * @param GCPtr The address.
3848 * @param piPD Receives the index into the returned page directory
3849 * @param pPdpe Receives the page directory pointer entry. Optional.
3850 */
3851DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3852{
3853 AssertGCPtr32(GCPtr);
3854
3855 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3856 AssertReturn(pGuestPDPT, NULL);
3857 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3858 if (pPdpe)
3859 *pPdpe = pGuestPDPT->a[iPdpt];
3860 if (pGuestPDPT->a[iPdpt].n.u1Present)
3861 {
3862 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3863#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3864 PX86PDPAE pGuestPD = NULL;
3865 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3866 AssertRCReturn(rc, NULL);
3867#else
3868 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3869 if ( !pGuestPD
3870 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3871 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3872#endif
3873 *piPD = iPD;
3874 return pGuestPD;
3875 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3876 }
3877 return NULL;
3878}
3879
3880#ifndef IN_RC
3881
3882/**
3883 * Gets the page map level-4 pointer for the guest.
3884 *
3885 * @returns Pointer to the PML4 page.
3886 * @param pPGM Pointer to the PGM instance data.
3887 */
3888DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3889{
3890#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3891 PX86PML4 pGuestPml4;
3892 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3893 AssertRCReturn(rc, NULL);
3894#else
3895 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3896# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3897 if (!pGuestPml4)
3898 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3899# endif
3900 Assert(pGuestPml4);
3901#endif
3902 return pGuestPml4;
3903}
3904
3905
3906/**
3907 * Gets the pointer to a page map level-4 entry.
3908 *
3909 * @returns Pointer to the PML4 entry.
3910 * @param pPGM Pointer to the PGM instance data.
3911 * @param iPml4 The index.
3912 */
3913DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3914{
3915#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3916 PX86PML4 pGuestPml4;
3917 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3918 AssertRCReturn(rc, NULL);
3919#else
3920 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3921# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3922 if (!pGuestPml4)
3923 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3924# endif
3925 Assert(pGuestPml4);
3926#endif
3927 return &pGuestPml4->a[iPml4];
3928}
3929
3930
3931/**
3932 * Gets a page map level-4 entry.
3933 *
3934 * @returns The PML4 entry.
3935 * @param pPGM Pointer to the PGM instance data.
3936 * @param iPml4 The index.
3937 */
3938DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3939{
3940#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3941 PX86PML4 pGuestPml4;
3942 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3943 if (RT_FAILURE(rc))
3944 {
3945 X86PML4E ZeroPml4e = {0};
3946 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3947 }
3948#else
3949 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3950# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3951 if (!pGuestPml4)
3952 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3953# endif
3954 Assert(pGuestPml4);
3955#endif
3956 return pGuestPml4->a[iPml4];
3957}
3958
3959
3960/**
3961 * Gets the page directory pointer entry for the specified address.
3962 *
3963 * @returns Pointer to the page directory pointer entry in question.
3964 * @returns NULL if the page directory is not present or on an invalid page.
3965 * @param pPGM Pointer to the PGM instance data.
3966 * @param GCPtr The address.
3967 * @param ppPml4e Page Map Level-4 Entry (out)
3968 */
3969DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3970{
3971 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3972 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3973 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3974 if (pPml4e->n.u1Present)
3975 {
3976 PX86PDPT pPdpt;
3977 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3978 AssertRCReturn(rc, NULL);
3979
3980 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3981 return &pPdpt->a[iPdpt];
3982 }
3983 return NULL;
3984}
3985
3986
3987/**
3988 * Gets the page directory entry for the specified address.
3989 *
3990 * @returns The page directory entry in question.
3991 * @returns A non-present entry if the page directory is not present or on an invalid page.
3992 * @param pPGM Pointer to the PGM instance data.
3993 * @param GCPtr The address.
3994 * @param ppPml4e Page Map Level-4 Entry (out)
3995 * @param pPdpe Page directory pointer table entry (out)
3996 */
3997DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3998{
3999 X86PDEPAE ZeroPde = {0};
4000 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4001 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4002 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4003 if (pPml4e->n.u1Present)
4004 {
4005 PCX86PDPT pPdptTemp;
4006 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4007 AssertRCReturn(rc, ZeroPde);
4008
4009 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4010 *pPdpe = pPdptTemp->a[iPdpt];
4011 if (pPdptTemp->a[iPdpt].n.u1Present)
4012 {
4013 PCX86PDPAE pPD;
4014 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4015 AssertRCReturn(rc, ZeroPde);
4016
4017 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4018 return pPD->a[iPD];
4019 }
4020 }
4021
4022 return ZeroPde;
4023}
4024
4025
4026/**
4027 * Gets the page directory entry for the specified address.
4028 *
4029 * @returns The page directory entry in question.
4030 * @returns A non-present entry if the page directory is not present or on an invalid page.
4031 * @param pPGM Pointer to the PGM instance data.
4032 * @param GCPtr The address.
4033 */
4034DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4035{
4036 X86PDEPAE ZeroPde = {0};
4037 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4038 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4039 if (pGuestPml4->a[iPml4].n.u1Present)
4040 {
4041 PCX86PDPT pPdptTemp;
4042 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4043 AssertRCReturn(rc, ZeroPde);
4044
4045 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4046 if (pPdptTemp->a[iPdpt].n.u1Present)
4047 {
4048 PCX86PDPAE pPD;
4049 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4050 AssertRCReturn(rc, ZeroPde);
4051
4052 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4053 return pPD->a[iPD];
4054 }
4055 }
4056 return ZeroPde;
4057}
4058
4059
4060/**
4061 * Gets the page directory entry for the specified address.
4062 *
4063 * @returns Pointer to the page directory entry in question.
4064 * @returns NULL if the page directory is not present or on an invalid page.
4065 * @param pPGM Pointer to the PGM instance data.
4066 * @param GCPtr The address.
4067 */
4068DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4069{
4070 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4071 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4072 if (pGuestPml4->a[iPml4].n.u1Present)
4073 {
4074 PCX86PDPT pPdptTemp;
4075 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4076 AssertRCReturn(rc, NULL);
4077
4078 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4079 if (pPdptTemp->a[iPdpt].n.u1Present)
4080 {
4081 PX86PDPAE pPD;
4082 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4083 AssertRCReturn(rc, NULL);
4084
4085 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4086 return &pPD->a[iPD];
4087 }
4088 }
4089 return NULL;
4090}
4091
4092
4093/**
4094 * Gets the GUEST page directory pointer for the specified address.
4095 *
4096 * @returns The page directory in question.
4097 * @returns NULL if the page directory is not present or on an invalid page.
4098 * @param pPGM Pointer to the PGM instance data.
4099 * @param GCPtr The address.
4100 * @param ppPml4e Page Map Level-4 Entry (out)
4101 * @param pPdpe Page directory pointer table entry (out)
4102 * @param piPD Receives the index into the returned page directory
4103 */
4104DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4105{
4106 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4107 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4108 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4109 if (pPml4e->n.u1Present)
4110 {
4111 PCX86PDPT pPdptTemp;
4112 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4113 AssertRCReturn(rc, NULL);
4114
4115 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4116 *pPdpe = pPdptTemp->a[iPdpt];
4117 if (pPdptTemp->a[iPdpt].n.u1Present)
4118 {
4119 PX86PDPAE pPD;
4120 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4121 AssertRCReturn(rc, NULL);
4122
4123 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4124 return pPD;
4125 }
4126 }
4127 return 0;
4128}
4129
4130#endif /* !IN_RC */
4131
4132/**
4133 * Gets the shadow page directory, 32-bit.
4134 *
4135 * @returns Pointer to the shadow 32-bit PD.
4136 * @param pPGM Pointer to the PGM instance data.
4137 */
4138DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4139{
4140 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4141}
4142
4143
4144/**
4145 * Gets the shadow page directory entry for the specified address, 32-bit.
4146 *
4147 * @returns Shadow 32-bit PDE.
4148 * @param pPGM Pointer to the PGM instance data.
4149 * @param GCPtr The address.
4150 */
4151DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4152{
4153 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4154
4155 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4156 if (!pShwPde)
4157 {
4158 X86PDE ZeroPde = {0};
4159 return ZeroPde;
4160 }
4161 return pShwPde->a[iPd];
4162}
4163
4164
4165/**
4166 * Gets the pointer to the shadow page directory entry for the specified
4167 * address, 32-bit.
4168 *
4169 * @returns Pointer to the shadow 32-bit PDE.
4170 * @param pPGM Pointer to the PGM instance data.
4171 * @param GCPtr The address.
4172 */
4173DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4174{
4175 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4176
4177 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4178 AssertReturn(pPde, NULL);
4179 return &pPde->a[iPd];
4180}
4181
4182
4183/**
4184 * Gets the shadow page pointer table, PAE.
4185 *
4186 * @returns Pointer to the shadow PAE PDPT.
4187 * @param pPGM Pointer to the PGM instance data.
4188 */
4189DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4190{
4191 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4192}
4193
4194
4195/**
4196 * Gets the shadow page directory for the specified address, PAE.
4197 *
4198 * @returns Pointer to the shadow PD.
4199 * @param pPGM Pointer to the PGM instance data.
4200 * @param GCPtr The address.
4201 */
4202DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4203{
4204 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4205 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4206
4207 if (!pPdpt->a[iPdpt].n.u1Present)
4208 return NULL;
4209
4210 /* Fetch the pgm pool shadow descriptor. */
4211 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4212 AssertReturn(pShwPde, NULL);
4213
4214 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4215}
4216
4217
4218/**
4219 * Gets the shadow page directory for the specified address, PAE.
4220 *
4221 * @returns Pointer to the shadow PD.
4222 * @param pPGM Pointer to the PGM instance data.
4223 * @param GCPtr The address.
4224 */
4225DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4226{
4227 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4228
4229 if (!pPdpt->a[iPdpt].n.u1Present)
4230 return NULL;
4231
4232 /* Fetch the pgm pool shadow descriptor. */
4233 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4234 AssertReturn(pShwPde, NULL);
4235
4236 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4237}
4238
4239
4240/**
4241 * Gets the shadow page directory entry, PAE.
4242 *
4243 * @returns PDE.
4244 * @param pPGM Pointer to the PGM instance data.
4245 * @param GCPtr The address.
4246 */
4247DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4248{
4249 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4250
4251 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4252 if (!pShwPde)
4253 {
4254 X86PDEPAE ZeroPde = {0};
4255 return ZeroPde;
4256 }
4257 return pShwPde->a[iPd];
4258}
4259
4260
4261/**
4262 * Gets the pointer to the shadow page directory entry for an address, PAE.
4263 *
4264 * @returns Pointer to the PDE.
4265 * @param pPGM Pointer to the PGM instance data.
4266 * @param GCPtr The address.
4267 */
4268DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4269{
4270 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4271
4272 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4273 AssertReturn(pPde, NULL);
4274 return &pPde->a[iPd];
4275}
4276
4277#ifndef IN_RC
4278
4279/**
4280 * Gets the shadow page map level-4 pointer.
4281 *
4282 * @returns Pointer to the shadow PML4.
4283 * @param pPGM Pointer to the PGM instance data.
4284 */
4285DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4286{
4287 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4288}
4289
4290
4291/**
4292 * Gets the shadow page map level-4 entry for the specified address.
4293 *
4294 * @returns The entry.
4295 * @param pPGM Pointer to the PGM instance data.
4296 * @param GCPtr The address.
4297 */
4298DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4299{
4300 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4301 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4302
4303 if (!pShwPml4)
4304 {
4305 X86PML4E ZeroPml4e = {0};
4306 return ZeroPml4e;
4307 }
4308 return pShwPml4->a[iPml4];
4309}
4310
4311
4312/**
4313 * Gets the pointer to the specified shadow page map level-4 entry.
4314 *
4315 * @returns The entry.
4316 * @param pPGM Pointer to the PGM instance data.
4317 * @param iPml4 The PML4 index.
4318 */
4319DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4320{
4321 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4322 if (!pShwPml4)
4323 return NULL;
4324 return &pShwPml4->a[iPml4];
4325}
4326
4327
4328/**
4329 * Gets the GUEST page directory pointer for the specified address.
4330 *
4331 * @returns The page directory in question.
4332 * @returns NULL if the page directory is not present or on an invalid page.
4333 * @param pPGM Pointer to the PGM instance data.
4334 * @param GCPtr The address.
4335 * @param piPD Receives the index into the returned page directory
4336 */
4337DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4338{
4339 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4340 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4341 if (pGuestPml4->a[iPml4].n.u1Present)
4342 {
4343 PCX86PDPT pPdptTemp;
4344 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4345 AssertRCReturn(rc, NULL);
4346
4347 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4348 if (pPdptTemp->a[iPdpt].n.u1Present)
4349 {
4350 PX86PDPAE pPD;
4351 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4352 AssertRCReturn(rc, NULL);
4353
4354 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4355 return pPD;
4356 }
4357 }
4358 return NULL;
4359}
4360
4361#endif /* !IN_RC */
4362
4363/**
4364 * Gets the page state for a physical handler.
4365 *
4366 * @returns The physical handler page state.
4367 * @param pCur The physical handler in question.
4368 */
4369DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4370{
4371 switch (pCur->enmType)
4372 {
4373 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4374 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4375
4376 case PGMPHYSHANDLERTYPE_MMIO:
4377 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4378 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4379
4380 default:
4381 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4382 }
4383}
4384
4385
4386/**
4387 * Gets the page state for a virtual handler.
4388 *
4389 * @returns The virtual handler page state.
4390 * @param pCur The virtual handler in question.
4391 * @remarks This should never be used on a hypervisor access handler.
4392 */
4393DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4394{
4395 switch (pCur->enmType)
4396 {
4397 case PGMVIRTHANDLERTYPE_WRITE:
4398 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4399 case PGMVIRTHANDLERTYPE_ALL:
4400 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4401 default:
4402 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4403 }
4404}
4405
4406
4407/**
4408 * Clears one physical page of a virtual handler
4409 *
4410 * @param pPGM Pointer to the PGM instance.
4411 * @param pCur Virtual handler structure
4412 * @param iPage Physical page index
4413 *
4414 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4415 * need to care about other handlers in the same page.
4416 */
4417DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4418{
4419 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4420
4421 /*
4422 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4423 */
4424#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4425 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4426 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4427 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4428#endif
4429 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4430 {
4431 /* We're the head of the alias chain. */
4432 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4433#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4434 AssertReleaseMsg(pRemove != NULL,
4435 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4436 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4437 AssertReleaseMsg(pRemove == pPhys2Virt,
4438 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4439 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4440 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4441 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4442#endif
4443 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4444 {
4445 /* Insert the next list in the alias chain into the tree. */
4446 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4447#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4448 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4449 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4450 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4451#endif
4452 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4453 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4454 AssertRelease(fRc);
4455 }
4456 }
4457 else
4458 {
4459 /* Locate the previous node in the alias chain. */
4460 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4461#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4462 AssertReleaseMsg(pPrev != pPhys2Virt,
4463 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4464 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4465#endif
4466 for (;;)
4467 {
4468 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4469 if (pNext == pPhys2Virt)
4470 {
4471 /* unlink. */
4472 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4473 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4474 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4475 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4476 else
4477 {
4478 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4479 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4480 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4481 }
4482 break;
4483 }
4484
4485 /* next */
4486 if (pNext == pPrev)
4487 {
4488#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4489 AssertReleaseMsg(pNext != pPrev,
4490 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4491 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4492#endif
4493 break;
4494 }
4495 pPrev = pNext;
4496 }
4497 }
4498 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4499 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4500 pPhys2Virt->offNextAlias = 0;
4501 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4502
4503 /*
4504 * Clear the ram flags for this page.
4505 */
4506 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4507 AssertReturnVoid(pPage);
4508 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4509}
4510
4511
4512/**
4513 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4514 *
4515 * @returns Pointer to the shadow page structure.
4516 * @param pPool The pool.
4517 * @param idx The pool page index.
4518 */
4519DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4520{
4521 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4522 return &pPool->aPages[idx];
4523}
4524
4525
4526#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4527/**
4528 * Clear references to guest physical memory.
4529 *
4530 * @param pPool The pool.
4531 * @param pPoolPage The pool page.
4532 * @param pPhysPage The physical guest page tracking structure.
4533 */
4534DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4535{
4536 /*
4537 * Just deal with the simple case here.
4538 */
4539# ifdef LOG_ENABLED
4540 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4541# endif
4542 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4543 if (cRefs == 1)
4544 {
4545 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4546 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4547 }
4548 else
4549 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4550 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4551}
4552#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4553
4554
4555#ifdef PGMPOOL_WITH_CACHE
4556/**
4557 * Moves the page to the head of the age list.
4558 *
4559 * This is done when the cached page is used in one way or another.
4560 *
4561 * @param pPool The pool.
4562 * @param pPage The cached page.
4563 */
4564DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4565{
4566 PVM pVM = pPool->CTX_SUFF(pVM);
4567 pgmLock(pVM);
4568
4569 /*
4570 * Move to the head of the age list.
4571 */
4572 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4573 {
4574 /* unlink */
4575 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4576 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4577 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4578 else
4579 pPool->iAgeTail = pPage->iAgePrev;
4580
4581 /* insert at head */
4582 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4583 pPage->iAgeNext = pPool->iAgeHead;
4584 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4585 pPool->iAgeHead = pPage->idx;
4586 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4587 }
4588 pgmUnlock(pVM);
4589}
4590#endif /* PGMPOOL_WITH_CACHE */
4591
4592/**
4593 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4594 *
4595 * @param pVM VM Handle.
4596 * @param pPage PGM pool page
4597 */
4598DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4599{
4600 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4601 ASMAtomicIncU32(&pPage->cLocked);
4602}
4603
4604
4605/**
4606 * Unlocks a page to allow flushing again
4607 *
4608 * @param pVM VM Handle.
4609 * @param pPage PGM pool page
4610 */
4611DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4612{
4613 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4614 Assert(pPage->cLocked);
4615 ASMAtomicDecU32(&pPage->cLocked);
4616}
4617
4618
4619/**
4620 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4621 *
4622 * @returns VBox status code.
4623 * @param pPage PGM pool page
4624 */
4625DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4626{
4627 if (pPage->cLocked)
4628 {
4629 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4630 if (pPage->cModifications)
4631 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4632 return true;
4633 }
4634 return false;
4635}
4636
4637/**
4638 * Tells if mappings are to be put into the shadow page table or not
4639 *
4640 * @returns boolean result
4641 * @param pVM VM handle.
4642 */
4643DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4644{
4645#ifdef IN_RING0
4646 /* There are no mappings in VT-x and AMD-V mode. */
4647 Assert(pPGM->fDisableMappings);
4648 return false;
4649#else
4650 return !pPGM->fDisableMappings;
4651#endif
4652}
4653
4654/** @} */
4655
4656#endif
4657
4658
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