VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 22760

Last change on this file since 22760 was 22760, checked in by vboxsync, 16 years ago

Backed out 51884 (caused gurus) and 51924 (not responsible).
Rewrote pgmPoolAccessHandlerFlush handling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 191.6 KB
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1/* $Id: PGMInternal.h 22760 2009-09-04 08:35:09Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#ifndef IN_RC
72# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
73#endif
74
75/**
76 * Sync N pages instead of a whole page table
77 */
78#define PGM_SYNC_N_PAGES
79
80/**
81 * Number of pages to sync during a page fault
82 *
83 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
84 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
85 */
86#define PGM_SYNC_NR_PAGES 8
87
88/**
89 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
90 */
91#define PGM_MAX_PHYSCACHE_ENTRIES 64
92#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKING
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147
148/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
149 * Enables the experimental lazy page allocation code. */
150/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
151
152/** @} */
153
154
155/** @name PDPT and PML4 flags.
156 * These are placed in the three bits available for system programs in
157 * the PDPT and PML4 entries.
158 * @{ */
159/** The entry is a permanent one and it's must always be present.
160 * Never free such an entry. */
161#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
164/** @} */
165
166/** @name Page directory flags.
167 * These are placed in the three bits available for system programs in
168 * the page directory entries.
169 * @{ */
170/** Mapping (hypervisor allocated pagetable). */
171#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
174/** @} */
175
176/** @name Page flags.
177 * These are placed in the three bits available for system programs in
178 * the page entries.
179 * @{ */
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
182
183#ifndef PGM_PTFLAGS_CSAM_VALIDATED
184/** Scanned and approved by CSAM (tm).
185 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
186 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
187#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
188#endif
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page.
333 *
334 * @param pVCpu The VMCPU handle.
335 * @param GCVirt The virtual address of the page to invalidate.
336 */
337#ifdef IN_RC
338# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
339#elif defined(IN_RING0)
340# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
341#else
342# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
343#endif
344
345/** @def PGM_INVL_PG_ALL_VCPU
346 * Invalidates a page on all VCPUs
347 *
348 * @param pVM The VM handle.
349 * @param GCVirt The virtual address of the page to invalidate.
350 */
351#ifdef IN_RC
352# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
353#elif defined(IN_RING0)
354# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
355#else
356# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
357#endif
358
359/** @def PGM_INVL_BIG_PG
360 * Invalidates a 4MB page directory entry.
361 *
362 * @param pVCpu The VMCPU handle.
363 * @param GCVirt The virtual address within the page directory to invalidate.
364 */
365#ifdef IN_RC
366# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
367#elif defined(IN_RING0)
368# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
369#else
370# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
371#endif
372
373/** @def PGM_INVL_VCPU_TLBS()
374 * Invalidates the TLBs of the specified VCPU
375 *
376 * @param pVCpu The VMCPU handle.
377 */
378#ifdef IN_RC
379# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_ALL_VCPU_TLBS()
387 * Invalidates the TLBs of all VCPUs
388 *
389 * @param pVM The VM handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
395#else
396# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
397#endif
398
399/** Size of the GCPtrConflict array in PGMMAPPING.
400 * @remarks Must be a power of two. */
401#define PGMMAPPING_CONFLICT_MAX 8
402
403/**
404 * Structure for tracking GC Mappings.
405 *
406 * This structure is used by linked list in both GC and HC.
407 */
408typedef struct PGMMAPPING
409{
410 /** Pointer to next entry. */
411 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
412 /** Pointer to next entry. */
413 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
414 /** Pointer to next entry. */
415 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
416 /** Indicate whether this entry is finalized. */
417 bool fFinalized;
418 /** Start Virtual address. */
419 RTGCPTR GCPtr;
420 /** Last Virtual address (inclusive). */
421 RTGCPTR GCPtrLast;
422 /** Range size (bytes). */
423 RTGCPTR cb;
424 /** Pointer to relocation callback function. */
425 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
426 /** User argument to the callback. */
427 R3PTRTYPE(void *) pvUser;
428 /** Mapping description / name. For easing debugging. */
429 R3PTRTYPE(const char *) pszDesc;
430 /** Last 8 addresses that caused conflicts. */
431 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
432 /** Number of conflicts for this hypervisor mapping. */
433 uint32_t cConflicts;
434 /** Number of page tables. */
435 uint32_t cPTs;
436
437 /** Array of page table mapping data. Each entry
438 * describes one page table. The array can be longer
439 * than the declared length.
440 */
441 struct
442 {
443 /** The HC physical address of the page table. */
444 RTHCPHYS HCPhysPT;
445 /** The HC physical address of the first PAE page table. */
446 RTHCPHYS HCPhysPaePT0;
447 /** The HC physical address of the second PAE page table. */
448 RTHCPHYS HCPhysPaePT1;
449 /** The HC virtual address of the 32-bit page table. */
450 R3PTRTYPE(PX86PT) pPTR3;
451 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
452 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
453 /** The RC virtual address of the 32-bit page table. */
454 RCPTRTYPE(PX86PT) pPTRC;
455 /** The RC virtual address of the two PAE page table. */
456 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
457 /** The R0 virtual address of the 32-bit page table. */
458 R0PTRTYPE(PX86PT) pPTR0;
459 /** The R0 virtual address of the two PAE page table. */
460 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
461 } aPTs[1];
462} PGMMAPPING;
463/** Pointer to structure for tracking GC Mappings. */
464typedef struct PGMMAPPING *PPGMMAPPING;
465
466
467/**
468 * Physical page access handler structure.
469 *
470 * This is used to keep track of physical address ranges
471 * which are being monitored in some kind of way.
472 */
473typedef struct PGMPHYSHANDLER
474{
475 AVLROGCPHYSNODECORE Core;
476 /** Access type. */
477 PGMPHYSHANDLERTYPE enmType;
478 /** Number of pages to update. */
479 uint32_t cPages;
480 /** Pointer to R3 callback function. */
481 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
482 /** User argument for R3 handlers. */
483 R3PTRTYPE(void *) pvUserR3;
484 /** Pointer to R0 callback function. */
485 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
486 /** User argument for R0 handlers. */
487 R0PTRTYPE(void *) pvUserR0;
488 /** Pointer to RC callback function. */
489 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
490 /** User argument for RC handlers. */
491 RCPTRTYPE(void *) pvUserRC;
492 /** Description / Name. For easing debugging. */
493 R3PTRTYPE(const char *) pszDesc;
494#ifdef VBOX_WITH_STATISTICS
495 /** Profiling of this handler. */
496 STAMPROFILE Stat;
497#endif
498} PGMPHYSHANDLER;
499/** Pointer to a physical page access handler structure. */
500typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
501
502
503/**
504 * Cache node for the physical addresses covered by a virtual handler.
505 */
506typedef struct PGMPHYS2VIRTHANDLER
507{
508 /** Core node for the tree based on physical ranges. */
509 AVLROGCPHYSNODECORE Core;
510 /** Offset from this struct to the PGMVIRTHANDLER structure. */
511 int32_t offVirtHandler;
512 /** Offset of the next alias relative to this one.
513 * Bit 0 is used for indicating whether we're in the tree.
514 * Bit 1 is used for indicating that we're the head node.
515 */
516 int32_t offNextAlias;
517} PGMPHYS2VIRTHANDLER;
518/** Pointer to a phys to virtual handler structure. */
519typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
520
521/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
522 * node is in the tree. */
523#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
524/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
525 * node is in the head of an alias chain.
526 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
527#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
528/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
529#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
530
531
532/**
533 * Virtual page access handler structure.
534 *
535 * This is used to keep track of virtual address ranges
536 * which are being monitored in some kind of way.
537 */
538typedef struct PGMVIRTHANDLER
539{
540 /** Core node for the tree based on virtual ranges. */
541 AVLROGCPTRNODECORE Core;
542 /** Size of the range (in bytes). */
543 RTGCPTR cb;
544 /** Number of cache pages. */
545 uint32_t cPages;
546 /** Access type. */
547 PGMVIRTHANDLERTYPE enmType;
548 /** Pointer to the RC callback function. */
549 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
550#if HC_ARCH_BITS == 64
551 RTRCPTR padding;
552#endif
553 /** Pointer to the R3 callback function for invalidation. */
554 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
555 /** Pointer to the R3 callback function. */
556 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
557 /** Description / Name. For easing debugging. */
558 R3PTRTYPE(const char *) pszDesc;
559#ifdef VBOX_WITH_STATISTICS
560 /** Profiling of this handler. */
561 STAMPROFILE Stat;
562#endif
563 /** Array of cached physical addresses for the monitored ranged. */
564 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
565} PGMVIRTHANDLER;
566/** Pointer to a virtual page access handler structure. */
567typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
568
569
570/**
571 * Page type.
572 *
573 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
574 * @remarks This is used in the saved state, so changes to it requires bumping
575 * the saved state version.
576 * @todo So, convert to \#defines!
577 */
578typedef enum PGMPAGETYPE
579{
580 /** The usual invalid zero entry. */
581 PGMPAGETYPE_INVALID = 0,
582 /** RAM page. (RWX) */
583 PGMPAGETYPE_RAM,
584 /** MMIO2 page. (RWX) */
585 PGMPAGETYPE_MMIO2,
586 /** MMIO2 page aliased over an MMIO page. (RWX)
587 * See PGMHandlerPhysicalPageAlias(). */
588 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
589 /** Shadowed ROM. (RWX) */
590 PGMPAGETYPE_ROM_SHADOW,
591 /** ROM page. (R-X) */
592 PGMPAGETYPE_ROM,
593 /** MMIO page. (---) */
594 PGMPAGETYPE_MMIO,
595 /** End of valid entries. */
596 PGMPAGETYPE_END
597} PGMPAGETYPE;
598AssertCompile(PGMPAGETYPE_END <= 7);
599
600/** @name Page type predicates.
601 * @{ */
602#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
603#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
604#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
605#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
606#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
607/** @} */
608
609
610/**
611 * A Physical Guest Page tracking structure.
612 *
613 * The format of this structure is complicated because we have to fit a lot
614 * of information into as few bits as possible. The format is also subject
615 * to change (there is one comming up soon). Which means that for we'll be
616 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
617 * accessess to the structure.
618 */
619typedef struct PGMPAGE
620{
621 /** The physical address and a whole lot of other stuff. All bits are used! */
622 RTHCPHYS HCPhysX;
623 /** The page state. */
624 uint32_t u2StateX : 2;
625 /** Flag indicating that a write monitored page was written to when set. */
626 uint32_t fWrittenToX : 1;
627 /** For later. */
628 uint32_t fSomethingElse : 1;
629 /** The Page ID.
630 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
631 * The HCPhysX will then be 100% static. */
632 uint32_t idPageX : 28;
633 /** The page type (PGMPAGETYPE). */
634 uint32_t u3Type : 3;
635 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
636 uint32_t u2HandlerPhysStateX : 2;
637 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
638 uint32_t u2HandlerVirtStateX : 2;
639 uint32_t u29B : 25;
640} PGMPAGE;
641AssertCompileSize(PGMPAGE, 16);
642/** Pointer to a physical guest page. */
643typedef PGMPAGE *PPGMPAGE;
644/** Pointer to a const physical guest page. */
645typedef const PGMPAGE *PCPGMPAGE;
646/** Pointer to a physical guest page pointer. */
647typedef PPGMPAGE *PPPGMPAGE;
648
649
650/**
651 * Clears the page structure.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_CLEAR(pPage) \
655 do { \
656 (pPage)->HCPhysX = 0; \
657 (pPage)->u2StateX = 0; \
658 (pPage)->fWrittenToX = 0; \
659 (pPage)->fSomethingElse = 0; \
660 (pPage)->idPageX = 0; \
661 (pPage)->u3Type = 0; \
662 (pPage)->u29B = 0; \
663 } while (0)
664
665/**
666 * Initializes the page structure.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670 do { \
671 (pPage)->HCPhysX = (_HCPhys); \
672 (pPage)->u2StateX = (_uState); \
673 (pPage)->fWrittenToX = 0; \
674 (pPage)->fSomethingElse = 0; \
675 (pPage)->idPageX = (_idPage); \
676 /*(pPage)->u3Type = (_uType); - later */ \
677 PGM_PAGE_SET_TYPE(pPage, _uType); \
678 (pPage)->u29B = 0; \
679 } while (0)
680
681/**
682 * Initializes the page structure of a ZERO page.
683 * @param pPage Pointer to the physical guest page tracking structure.
684 */
685#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
686 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
687/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
688# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
689 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
690
691
692/** @name The Page state, PGMPAGE::u2StateX.
693 * @{ */
694/** The zero page.
695 * This is a per-VM page that's never ever mapped writable. */
696#define PGM_PAGE_STATE_ZERO 0
697/** A allocated page.
698 * This is a per-VM page allocated from the page pool (or wherever
699 * we get MMIO2 pages from if the type is MMIO2).
700 */
701#define PGM_PAGE_STATE_ALLOCATED 1
702/** A allocated page that's being monitored for writes.
703 * The shadow page table mappings are read-only. When a write occurs, the
704 * fWrittenTo member is set, the page remapped as read-write and the state
705 * moved back to allocated. */
706#define PGM_PAGE_STATE_WRITE_MONITORED 2
707/** The page is shared, aka. copy-on-write.
708 * This is a page that's shared with other VMs. */
709#define PGM_PAGE_STATE_SHARED 3
710/** @} */
711
712
713/**
714 * Gets the page state.
715 * @returns page state (PGM_PAGE_STATE_*).
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
719
720/**
721 * Sets the page state.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 * @param _uState The new page state.
724 */
725#define PGM_PAGE_SET_STATE(pPage, _uState) \
726 do { (pPage)->u2StateX = (_uState); } while (0)
727
728
729/**
730 * Gets the host physical address of the guest page.
731 * @returns host physical address (RTHCPHYS).
732 * @param pPage Pointer to the physical guest page tracking structure.
733 */
734#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
735
736/**
737 * Sets the host physical address of the guest page.
738 * @param pPage Pointer to the physical guest page tracking structure.
739 * @param _HCPhys The new host physical address.
740 */
741#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
742 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
743 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
744
745/**
746 * Get the Page ID.
747 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
748 * @param pPage Pointer to the physical guest page tracking structure.
749 */
750#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
751/* later:
752#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
753 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
754*/
755/**
756 * Sets the Page ID.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
760/* later:
761#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
762 | ((_idPage) & 0xfff) \
763 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
764*/
765
766/**
767 * Get the Chunk ID.
768 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 */
771#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
772/* later:
773#if GMM_CHUNKID_SHIFT == 12
774# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
775#elif GMM_CHUNKID_SHIFT > 12
776# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
777#elif GMM_CHUNKID_SHIFT < 12
778# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
779 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
780#else
781# error "GMM_CHUNKID_SHIFT isn't defined or something."
782#endif
783*/
784
785/**
786 * Get the index of the page within the allocaiton chunk.
787 * @returns The page index.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
791/* later:
792#if GMM_CHUNKID_SHIFT <= 12
793# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
794#else
795# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
796 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
797#endif
798*/
799
800
801/**
802 * Gets the page type.
803 * @returns The page type.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
807
808/**
809 * Sets the page type.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 * @param _enmType The new page type (PGMPAGETYPE).
812 */
813#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
814 do { (pPage)->u3Type = (_enmType); } while (0)
815
816/**
817 * Checks if the page is marked for MMIO.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
822
823/**
824 * Checks if the page is backed by the ZERO page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
829
830/**
831 * Checks if the page is backed by a SHARED page.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
836
837
838/**
839 * Marks the paget as written to (for GMM change monitoring).
840 * @param pPage Pointer to the physical guest page tracking structure.
841 */
842#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
843
844/**
845 * Clears the written-to indicator.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
849
850/**
851 * Checks if the page was marked as written-to.
852 * @returns true/false.
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
856
857
858/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
859 *
860 * @remarks The values are assigned in order of priority, so we can calculate
861 * the correct state for a page with different handlers installed.
862 * @{ */
863/** No handler installed. */
864#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
865/** Monitoring is temporarily disabled. */
866#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
867/** Write access is monitored. */
868#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
869/** All access is monitored. */
870#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
871/** @} */
872
873/**
874 * Gets the physical access handler state of a page.
875 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
879
880/**
881 * Sets the physical access handler state of a page.
882 * @param pPage Pointer to the physical guest page tracking structure.
883 * @param _uState The new state value.
884 */
885#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
886 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
887
888/**
889 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
894
895/**
896 * Checks if the page has any active physical access handlers.
897 * @returns true/false
898 * @param pPage Pointer to the physical guest page tracking structure.
899 */
900#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
901
902
903/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
904 *
905 * @remarks The values are assigned in order of priority, so we can calculate
906 * the correct state for a page with different handlers installed.
907 * @{ */
908/** No handler installed. */
909#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
910/* 1 is reserved so the lineup is identical with the physical ones. */
911/** Write access is monitored. */
912#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
913/** All access is monitored. */
914#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
915/** @} */
916
917/**
918 * Gets the virtual access handler state of a page.
919 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
920 * @param pPage Pointer to the physical guest page tracking structure.
921 */
922#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
923
924/**
925 * Sets the virtual access handler state of a page.
926 * @param pPage Pointer to the physical guest page tracking structure.
927 * @param _uState The new state value.
928 */
929#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
930 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
931
932/**
933 * Checks if the page has any virtual access handlers.
934 * @returns true/false
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
938
939/**
940 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
941 * virtual handlers.
942 * @returns true/false
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
946
947
948
949/**
950 * Checks if the page has any access handlers, including temporarily disabled ones.
951 * @returns true/false
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
955 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
956 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
957
958/**
959 * Checks if the page has any active access handlers.
960 * @returns true/false
961 * @param pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
964 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
965 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
966
967/**
968 * Checks if the page has any active access handlers catching all accesses.
969 * @returns true/false
970 * @param pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
973 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
974 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
975
976
977
978
979/** @def PGM_PAGE_GET_TRACKING
980 * Gets the packed shadow page pool tracking data associated with a guest page.
981 * @returns uint16_t containing the data.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 */
984#define PGM_PAGE_GET_TRACKING(pPage) \
985 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
986
987/** @def PGM_PAGE_SET_TRACKING
988 * Sets the packed shadow page pool tracking data associated with a guest page.
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param u16TrackingData The tracking data to store.
991 */
992#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
993 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
994
995/** @def PGM_PAGE_GET_TD_CREFS
996 * Gets the @a cRefs tracking data member.
997 * @returns cRefs.
998 * @param pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_GET_TD_CREFS(pPage) \
1001 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1002
1003#define PGM_PAGE_GET_TD_IDX(pPage) \
1004 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1005
1006/**
1007 * Ram range for GC Phys to HC Phys conversion.
1008 *
1009 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1010 * conversions too, but we'll let MM handle that for now.
1011 *
1012 * This structure is used by linked lists in both GC and HC.
1013 */
1014typedef struct PGMRAMRANGE
1015{
1016 /** Start of the range. Page aligned. */
1017 RTGCPHYS GCPhys;
1018 /** Size of the range. (Page aligned of course). */
1019 RTGCPHYS cb;
1020 /** Pointer to the next RAM range - for R3. */
1021 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1022 /** Pointer to the next RAM range - for R0. */
1023 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1024 /** Pointer to the next RAM range - for RC. */
1025 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1026 /** PGM_RAM_RANGE_FLAGS_* flags. */
1027 uint32_t fFlags;
1028 /** Last address in the range (inclusive). Page aligned (-1). */
1029 RTGCPHYS GCPhysLast;
1030 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1031 R3PTRTYPE(void *) pvR3;
1032 /** The range description. */
1033 R3PTRTYPE(const char *) pszDesc;
1034 /** Pointer to self - R0 pointer. */
1035 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1036 /** Pointer to self - RC pointer. */
1037 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1038 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1039 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1040 /** Array of physical guest page tracking structures. */
1041 PGMPAGE aPages[1];
1042} PGMRAMRANGE;
1043/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1044typedef PGMRAMRANGE *PPGMRAMRANGE;
1045
1046/** @name PGMRAMRANGE::fFlags
1047 * @{ */
1048/** The RAM range is floating around as an independent guest mapping. */
1049#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1050/** @} */
1051
1052
1053/**
1054 * Per page tracking structure for ROM image.
1055 *
1056 * A ROM image may have a shadow page, in which case we may have
1057 * two pages backing it. This structure contains the PGMPAGE for
1058 * both while PGMRAMRANGE have a copy of the active one. It is
1059 * important that these aren't out of sync in any regard other
1060 * than page pool tracking data.
1061 */
1062typedef struct PGMROMPAGE
1063{
1064 /** The page structure for the virgin ROM page. */
1065 PGMPAGE Virgin;
1066 /** The page structure for the shadow RAM page. */
1067 PGMPAGE Shadow;
1068 /** The current protection setting. */
1069 PGMROMPROT enmProt;
1070 /** Pad the structure size to a multiple of 8. */
1071 uint32_t u32Padding;
1072} PGMROMPAGE;
1073/** Pointer to a ROM page tracking structure. */
1074typedef PGMROMPAGE *PPGMROMPAGE;
1075
1076
1077/**
1078 * A registered ROM image.
1079 *
1080 * This is needed to keep track of ROM image since they generally
1081 * intrude into a PGMRAMRANGE. It also keeps track of additional
1082 * info like the two page sets (read-only virgin and read-write shadow),
1083 * the current state of each page.
1084 *
1085 * Because access handlers cannot easily be executed in a different
1086 * context, the ROM ranges needs to be accessible and in all contexts.
1087 */
1088typedef struct PGMROMRANGE
1089{
1090 /** Pointer to the next range - R3. */
1091 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1092 /** Pointer to the next range - R0. */
1093 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1094 /** Pointer to the next range - RC. */
1095 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1096 /** Pointer alignment */
1097 RTRCPTR GCPtrAlignment;
1098 /** Address of the range. */
1099 RTGCPHYS GCPhys;
1100 /** Address of the last byte in the range. */
1101 RTGCPHYS GCPhysLast;
1102 /** Size of the range. */
1103 RTGCPHYS cb;
1104 /** The flags (PGMPHYS_ROM_FLAG_*). */
1105 uint32_t fFlags;
1106 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1107 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1108 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1109 * This is used for strictness checks. */
1110 R3PTRTYPE(const void *) pvOriginal;
1111 /** The ROM description. */
1112 R3PTRTYPE(const char *) pszDesc;
1113 /** The per page tracking structures. */
1114 PGMROMPAGE aPages[1];
1115} PGMROMRANGE;
1116/** Pointer to a ROM range. */
1117typedef PGMROMRANGE *PPGMROMRANGE;
1118
1119
1120/**
1121 * A registered MMIO2 (= Device RAM) range.
1122 *
1123 * There are a few reason why we need to keep track of these
1124 * registrations. One of them is the deregistration & cleanup
1125 * stuff, while another is that the PGMRAMRANGE associated with
1126 * such a region may have to be removed from the ram range list.
1127 *
1128 * Overlapping with a RAM range has to be 100% or none at all. The
1129 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1130 * meditation will be raised if a partial overlap or an overlap of
1131 * ROM pages is encountered. On an overlap we will free all the
1132 * existing RAM pages and put in the ram range pages instead.
1133 */
1134typedef struct PGMMMIO2RANGE
1135{
1136 /** The owner of the range. (a device) */
1137 PPDMDEVINSR3 pDevInsR3;
1138 /** Pointer to the ring-3 mapping of the allocation. */
1139 RTR3PTR pvR3;
1140 /** Pointer to the next range - R3. */
1141 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1142 /** Whether it's mapped or not. */
1143 bool fMapped;
1144 /** Whether it's overlapping or not. */
1145 bool fOverlapping;
1146 /** The PCI region number.
1147 * @remarks This ASSUMES that nobody will ever really need to have multiple
1148 * PCI devices with matching MMIO region numbers on a single device. */
1149 uint8_t iRegion;
1150 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1151 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1152 /** The associated RAM range. */
1153 PGMRAMRANGE RamRange;
1154} PGMMMIO2RANGE;
1155/** Pointer to a MMIO2 range. */
1156typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1157
1158
1159
1160
1161/**
1162 * PGMPhysRead/Write cache entry
1163 */
1164typedef struct PGMPHYSCACHEENTRY
1165{
1166 /** R3 pointer to physical page. */
1167 R3PTRTYPE(uint8_t *) pbR3;
1168 /** GC Physical address for cache entry */
1169 RTGCPHYS GCPhys;
1170#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1171 RTGCPHYS u32Padding0; /**< alignment padding. */
1172#endif
1173} PGMPHYSCACHEENTRY;
1174
1175/**
1176 * PGMPhysRead/Write cache to reduce REM memory access overhead
1177 */
1178typedef struct PGMPHYSCACHE
1179{
1180 /** Bitmap of valid cache entries */
1181 uint64_t aEntries;
1182 /** Cache entries */
1183 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1184} PGMPHYSCACHE;
1185
1186
1187/** Pointer to an allocation chunk ring-3 mapping. */
1188typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1189/** Pointer to an allocation chunk ring-3 mapping pointer. */
1190typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1191
1192/**
1193 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1194 *
1195 * The primary tree (Core) uses the chunk id as key.
1196 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1197 */
1198typedef struct PGMCHUNKR3MAP
1199{
1200 /** The key is the chunk id. */
1201 AVLU32NODECORE Core;
1202 /** The key is the ageing sequence number. */
1203 AVLLU32NODECORE AgeCore;
1204 /** The current age thingy. */
1205 uint32_t iAge;
1206 /** The current reference count. */
1207 uint32_t volatile cRefs;
1208 /** The current permanent reference count. */
1209 uint32_t volatile cPermRefs;
1210 /** The mapping address. */
1211 void *pv;
1212} PGMCHUNKR3MAP;
1213
1214/**
1215 * Allocation chunk ring-3 mapping TLB entry.
1216 */
1217typedef struct PGMCHUNKR3MAPTLBE
1218{
1219 /** The chunk id. */
1220 uint32_t volatile idChunk;
1221#if HC_ARCH_BITS == 64
1222 uint32_t u32Padding; /**< alignment padding. */
1223#endif
1224 /** The chunk map. */
1225#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1226 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1227#else
1228 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1229#endif
1230} PGMCHUNKR3MAPTLBE;
1231/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1232typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1233
1234/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1235 * @remark Must be a power of two value. */
1236#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1237
1238/**
1239 * Allocation chunk ring-3 mapping TLB.
1240 *
1241 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1242 * At first glance this might look kinda odd since AVL trees are
1243 * supposed to give the most optimial lookup times of all trees
1244 * due to their balancing. However, take a tree with 1023 nodes
1245 * in it, that's 10 levels, meaning that most searches has to go
1246 * down 9 levels before they find what they want. This isn't fast
1247 * compared to a TLB hit. There is the factor of cache misses,
1248 * and of course the problem with trees and branch prediction.
1249 * This is why we use TLBs in front of most of the trees.
1250 *
1251 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1252 * difficult when we switch to the new inlined AVL trees (from kStuff).
1253 */
1254typedef struct PGMCHUNKR3MAPTLB
1255{
1256 /** The TLB entries. */
1257 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1258} PGMCHUNKR3MAPTLB;
1259
1260/**
1261 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1262 * @returns Chunk TLB index.
1263 * @param idChunk The Chunk ID.
1264 */
1265#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1266
1267
1268/**
1269 * Ring-3 guest page mapping TLB entry.
1270 * @remarks used in ring-0 as well at the moment.
1271 */
1272typedef struct PGMPAGER3MAPTLBE
1273{
1274 /** Address of the page. */
1275 RTGCPHYS volatile GCPhys;
1276 /** The guest page. */
1277#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1278 R3PTRTYPE(PPGMPAGE) volatile pPage;
1279#else
1280 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1281#endif
1282 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1283#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1284 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1285#else
1286 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1287#endif
1288 /** The address */
1289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1290 R3PTRTYPE(void *) volatile pv;
1291#else
1292 R3R0PTRTYPE(void *) volatile pv;
1293#endif
1294#if HC_ARCH_BITS == 32
1295 uint32_t u32Padding; /**< alignment padding. */
1296#endif
1297} PGMPAGER3MAPTLBE;
1298/** Pointer to an entry in the HC physical TLB. */
1299typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1300
1301
1302/** The number of entries in the ring-3 guest page mapping TLB.
1303 * @remarks The value must be a power of two. */
1304#define PGM_PAGER3MAPTLB_ENTRIES 64
1305
1306/**
1307 * Ring-3 guest page mapping TLB.
1308 * @remarks used in ring-0 as well at the moment.
1309 */
1310typedef struct PGMPAGER3MAPTLB
1311{
1312 /** The TLB entries. */
1313 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1314} PGMPAGER3MAPTLB;
1315/** Pointer to the ring-3 guest page mapping TLB. */
1316typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1317
1318/**
1319 * Calculates the index of the TLB entry for the specified guest page.
1320 * @returns Physical TLB index.
1321 * @param GCPhys The guest physical address.
1322 */
1323#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1324
1325
1326/**
1327 * Mapping cache usage set entry.
1328 *
1329 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1330 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1331 * cache. If it's extended to include ring-3, well, then something will
1332 * have be changed here...
1333 */
1334typedef struct PGMMAPSETENTRY
1335{
1336 /** The mapping cache index. */
1337 uint16_t iPage;
1338 /** The number of references.
1339 * The max is UINT16_MAX - 1. */
1340 uint16_t cRefs;
1341#if HC_ARCH_BITS == 64
1342 uint32_t alignment;
1343#endif
1344 /** Pointer to the page. */
1345 RTR0PTR pvPage;
1346 /** The physical address for this entry. */
1347 RTHCPHYS HCPhys;
1348} PGMMAPSETENTRY;
1349/** Pointer to a mapping cache usage set entry. */
1350typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1351
1352/**
1353 * Mapping cache usage set.
1354 *
1355 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1356 * done during exits / traps. The set is
1357 */
1358typedef struct PGMMAPSET
1359{
1360 /** The number of occupied entries.
1361 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1362 * dynamic mappings. */
1363 uint32_t cEntries;
1364 /** The start of the current subset.
1365 * This is UINT32_MAX if no subset is currently open. */
1366 uint32_t iSubset;
1367 /** The index of the current CPU, only valid if the set is open. */
1368 int32_t iCpu;
1369#if HC_ARCH_BITS == 64
1370 uint32_t alignment;
1371#endif
1372 /** The entries. */
1373 PGMMAPSETENTRY aEntries[64];
1374 /** HCPhys -> iEntry fast lookup table.
1375 * Use PGMMAPSET_HASH for hashing.
1376 * The entries may or may not be valid, check against cEntries. */
1377 uint8_t aiHashTable[128];
1378} PGMMAPSET;
1379/** Pointer to the mapping cache set. */
1380typedef PGMMAPSET *PPGMMAPSET;
1381
1382/** PGMMAPSET::cEntries value for a closed set. */
1383#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1384
1385/** Hash function for aiHashTable. */
1386#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1387
1388/** The max fill size (strict builds). */
1389#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1390
1391
1392/** @name Context neutrual page mapper TLB.
1393 *
1394 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1395 * code is writting in a kind of context neutrual way. Time will show whether
1396 * this actually makes sense or not...
1397 *
1398 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1399 * context ends up using a global mapping cache on some platforms
1400 * (darwin).
1401 *
1402 * @{ */
1403/** @typedef PPGMPAGEMAPTLB
1404 * The page mapper TLB pointer type for the current context. */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB entry pointer type for the current context. */
1407/** @typedef PPGMPAGEMAPTLB
1408 * The page mapper TLB entry pointer pointer type for the current context. */
1409/** @def PGM_PAGEMAPTLB_ENTRIES
1410 * The number of TLB entries in the page mapper TLB for the current context. */
1411/** @def PGM_PAGEMAPTLB_IDX
1412 * Calculate the TLB index for a guest physical address.
1413 * @returns The TLB index.
1414 * @param GCPhys The guest physical address. */
1415/** @typedef PPGMPAGEMAP
1416 * Pointer to a page mapper unit for current context. */
1417/** @typedef PPPGMPAGEMAP
1418 * Pointer to a page mapper unit pointer for current context. */
1419#ifdef IN_RC
1420// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1421// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1422// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1423# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1424# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1425 typedef void * PPGMPAGEMAP;
1426 typedef void ** PPPGMPAGEMAP;
1427//#elif IN_RING0
1428// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1429// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1430// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1431//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1432//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1433// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1434// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1435#else
1436 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1437 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1438 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1439# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1440# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1441 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1442 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1443#endif
1444/** @} */
1445
1446
1447/** @name PGM Pool Indexes.
1448 * Aka. the unique shadow page identifier.
1449 * @{ */
1450/** NIL page pool IDX. */
1451#define NIL_PGMPOOL_IDX 0
1452/** The first normal index. */
1453#define PGMPOOL_IDX_FIRST_SPECIAL 1
1454/** Page directory (32-bit root). */
1455#define PGMPOOL_IDX_PD 1
1456/** Page Directory Pointer Table (PAE root). */
1457#define PGMPOOL_IDX_PDPT 2
1458/** AMD64 CR3 level index.*/
1459#define PGMPOOL_IDX_AMD64_CR3 3
1460/** Nested paging root.*/
1461#define PGMPOOL_IDX_NESTED_ROOT 4
1462/** The first normal index. */
1463#define PGMPOOL_IDX_FIRST 5
1464/** The last valid index. (inclusive, 14 bits) */
1465#define PGMPOOL_IDX_LAST 0x3fff
1466/** @} */
1467
1468/** The NIL index for the parent chain. */
1469#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1470#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1471
1472/**
1473 * Node in the chain linking a shadowed page to it's parent (user).
1474 */
1475#pragma pack(1)
1476typedef struct PGMPOOLUSER
1477{
1478 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1479 uint16_t iNext;
1480 /** The user page index. */
1481 uint16_t iUser;
1482 /** Index into the user table. */
1483 uint32_t iUserTable;
1484} PGMPOOLUSER, *PPGMPOOLUSER;
1485typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1486#pragma pack()
1487
1488
1489/** The NIL index for the phys ext chain. */
1490#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1491
1492/**
1493 * Node in the chain of physical cross reference extents.
1494 * @todo Calling this an 'extent' is not quite right, find a better name.
1495 */
1496#pragma pack(1)
1497typedef struct PGMPOOLPHYSEXT
1498{
1499 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1500 uint16_t iNext;
1501 /** The user page index. */
1502 uint16_t aidx[3];
1503} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1504typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1505#pragma pack()
1506
1507
1508/**
1509 * The kind of page that's being shadowed.
1510 */
1511typedef enum PGMPOOLKIND
1512{
1513 /** The virtual invalid 0 entry. */
1514 PGMPOOLKIND_INVALID = 0,
1515 /** The entry is free (=unused). */
1516 PGMPOOLKIND_FREE,
1517
1518 /** Shw: 32-bit page table; Gst: no paging */
1519 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1520 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1521 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1522 /** Shw: 32-bit page table; Gst: 4MB page. */
1523 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1524 /** Shw: PAE page table; Gst: no paging */
1525 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1526 /** Shw: PAE page table; Gst: 32-bit page table. */
1527 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1528 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1529 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1530 /** Shw: PAE page table; Gst: PAE page table. */
1531 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1532 /** Shw: PAE page table; Gst: 2MB page. */
1533 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1534
1535 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1536 PGMPOOLKIND_32BIT_PD,
1537 /** Shw: 32-bit page directory. Gst: no paging. */
1538 PGMPOOLKIND_32BIT_PD_PHYS,
1539 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1540 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1541 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1542 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1543 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1544 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1545 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1546 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1547 /** Shw: PAE page directory; Gst: PAE page directory. */
1548 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1549 /** Shw: PAE page directory; Gst: no paging. */
1550 PGMPOOLKIND_PAE_PD_PHYS,
1551
1552 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1553 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1554 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1555 PGMPOOLKIND_PAE_PDPT,
1556 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1557 PGMPOOLKIND_PAE_PDPT_PHYS,
1558
1559 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1560 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1561 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1562 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1563 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1564 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1565 /** Shw: 64-bit page directory table; Gst: no paging */
1566 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1567
1568 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1569 PGMPOOLKIND_64BIT_PML4,
1570
1571 /** Shw: EPT page directory pointer table; Gst: no paging */
1572 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1573 /** Shw: EPT page directory table; Gst: no paging */
1574 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1575 /** Shw: EPT page table; Gst: no paging */
1576 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1577
1578 /** Shw: Root Nested paging table. */
1579 PGMPOOLKIND_ROOT_NESTED,
1580
1581 /** The last valid entry. */
1582 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1583} PGMPOOLKIND;
1584
1585/**
1586 * The access attributes of the page; only applies to big pages.
1587 */
1588typedef enum
1589{
1590 PGMPOOLACCESS_DONTCARE = 0,
1591 PGMPOOLACCESS_USER_RW,
1592 PGMPOOLACCESS_USER_R,
1593 PGMPOOLACCESS_USER_RW_NX,
1594 PGMPOOLACCESS_USER_R_NX,
1595 PGMPOOLACCESS_SUPERVISOR_RW,
1596 PGMPOOLACCESS_SUPERVISOR_R,
1597 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1598 PGMPOOLACCESS_SUPERVISOR_R_NX
1599} PGMPOOLACCESS;
1600
1601/**
1602 * The tracking data for a page in the pool.
1603 */
1604typedef struct PGMPOOLPAGE
1605{
1606 /** AVL node code with the (R3) physical address of this page. */
1607 AVLOHCPHYSNODECORE Core;
1608 /** Pointer to the R3 mapping of the page. */
1609#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1610 R3PTRTYPE(void *) pvPageR3;
1611#else
1612 R3R0PTRTYPE(void *) pvPageR3;
1613#endif
1614 /** The guest physical address. */
1615#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1616 uint32_t Alignment0;
1617#endif
1618 RTGCPHYS GCPhys;
1619
1620 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1621 RTGCPTR pvLastAccessHandlerRip;
1622 RTGCPTR pvLastAccessHandlerFault;
1623 uint64_t cLastAccessHandlerCount;
1624
1625 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1626 uint8_t enmKind;
1627 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1628 uint8_t enmAccess;
1629 /** The index of this page. */
1630 uint16_t idx;
1631 /** The next entry in the list this page currently resides in.
1632 * It's either in the free list or in the GCPhys hash. */
1633 uint16_t iNext;
1634#ifdef PGMPOOL_WITH_USER_TRACKING
1635 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1636 uint16_t iUserHead;
1637 /** The number of present entries. */
1638 uint16_t cPresent;
1639 /** The first entry in the table which is present. */
1640 uint16_t iFirstPresent;
1641#endif
1642#ifdef PGMPOOL_WITH_MONITORING
1643 /** The number of modifications to the monitored page. */
1644 uint16_t cModifications;
1645 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1646 uint16_t iModifiedNext;
1647 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1648 uint16_t iModifiedPrev;
1649 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1650 uint16_t iMonitoredNext;
1651 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1652 uint16_t iMonitoredPrev;
1653#endif
1654#ifdef PGMPOOL_WITH_CACHE
1655 /** The next page in the age list. */
1656 uint16_t iAgeNext;
1657 /** The previous page in the age list. */
1658 uint16_t iAgePrev;
1659#endif /* PGMPOOL_WITH_CACHE */
1660 /** Used to indicate that the page is zeroed. */
1661 bool fZeroed;
1662 /** Used to indicate that a PT has non-global entries. */
1663 bool fSeenNonGlobal;
1664 /** Used to indicate that we're monitoring writes to the guest page. */
1665 bool fMonitored;
1666 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1667 * (All pages are in the age list.) */
1668 bool fCached;
1669 /** This is used by the R3 access handlers when invoked by an async thread.
1670 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1671 bool volatile fReusedFlushPending;
1672 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1673 bool fDirty;
1674
1675 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1676 uint32_t cLocked;
1677 uint32_t idxDirty;
1678 RTGCPTR pvDirtyFault;
1679} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1680/** Pointer to a const pool page. */
1681typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1682
1683
1684#ifdef PGMPOOL_WITH_CACHE
1685/** The hash table size. */
1686# define PGMPOOL_HASH_SIZE 0x40
1687/** The hash function. */
1688# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1689#endif
1690
1691
1692/**
1693 * The shadow page pool instance data.
1694 *
1695 * It's all one big allocation made at init time, except for the
1696 * pages that is. The user nodes follows immediatly after the
1697 * page structures.
1698 */
1699typedef struct PGMPOOL
1700{
1701 /** The VM handle - R3 Ptr. */
1702 PVMR3 pVMR3;
1703 /** The VM handle - R0 Ptr. */
1704 PVMR0 pVMR0;
1705 /** The VM handle - RC Ptr. */
1706 PVMRC pVMRC;
1707 /** The max pool size. This includes the special IDs. */
1708 uint16_t cMaxPages;
1709 /** The current pool size. */
1710 uint16_t cCurPages;
1711 /** The head of the free page list. */
1712 uint16_t iFreeHead;
1713 /* Padding. */
1714 uint16_t u16Padding;
1715#ifdef PGMPOOL_WITH_USER_TRACKING
1716 /** Head of the chain of free user nodes. */
1717 uint16_t iUserFreeHead;
1718 /** The number of user nodes we've allocated. */
1719 uint16_t cMaxUsers;
1720 /** The number of present page table entries in the entire pool. */
1721 uint32_t cPresent;
1722 /** Pointer to the array of user nodes - RC pointer. */
1723 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1724 /** Pointer to the array of user nodes - R3 pointer. */
1725 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1726 /** Pointer to the array of user nodes - R0 pointer. */
1727 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1728#endif /* PGMPOOL_WITH_USER_TRACKING */
1729#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1730 /** Head of the chain of free phys ext nodes. */
1731 uint16_t iPhysExtFreeHead;
1732 /** The number of user nodes we've allocated. */
1733 uint16_t cMaxPhysExts;
1734 /** Pointer to the array of physical xref extent - RC pointer. */
1735 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1736 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1737 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1738 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1739 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1740#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1741#ifdef PGMPOOL_WITH_CACHE
1742 /** Hash table for GCPhys addresses. */
1743 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1744 /** The head of the age list. */
1745 uint16_t iAgeHead;
1746 /** The tail of the age list. */
1747 uint16_t iAgeTail;
1748 /** Set if the cache is enabled. */
1749 bool fCacheEnabled;
1750#endif /* PGMPOOL_WITH_CACHE */
1751#ifdef PGMPOOL_WITH_MONITORING
1752 /** Head of the list of modified pages. */
1753 uint16_t iModifiedHead;
1754 /** The current number of modified pages. */
1755 uint16_t cModifiedPages;
1756 /** Access handler, RC. */
1757 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1758 /** Access handler, R0. */
1759 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1760 /** Access handler, R3. */
1761 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1762 /** The access handler description (HC ptr). */
1763 R3PTRTYPE(const char *) pszAccessHandler;
1764 /* Next available slot. */
1765 uint32_t idxFreeDirtyPage;
1766 /* Number of active dirty pages. */
1767 uint32_t cDirtyPages;
1768 /* Array of current dirty pgm pool page indices. */
1769 uint16_t aIdxDirtyPages[8];
1770 uint64_t aDirtyPages[8][512];
1771#endif /* PGMPOOL_WITH_MONITORING */
1772 /** The number of pages currently in use. */
1773 uint16_t cUsedPages;
1774#ifdef VBOX_WITH_STATISTICS
1775 /** The high water mark for cUsedPages. */
1776 uint16_t cUsedPagesHigh;
1777 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1778 /** Profiling pgmPoolAlloc(). */
1779 STAMPROFILEADV StatAlloc;
1780 /** Profiling pgmPoolClearAll(). */
1781 STAMPROFILE StatClearAll;
1782 /** Profiling pgmPoolFlushAllInt(). */
1783 STAMPROFILE StatFlushAllInt;
1784 /** Profiling pgmPoolFlushPage(). */
1785 STAMPROFILE StatFlushPage;
1786 /** Profiling pgmPoolFree(). */
1787 STAMPROFILE StatFree;
1788 /** Counting explicit flushes by PGMPoolFlushPage(). */
1789 STAMCOUNTER StatForceFlushPage;
1790 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1791 STAMCOUNTER StatForceFlushDirtyPage;
1792 /** Counting flushes for reused pages. */
1793 STAMCOUNTER StatForceFlushReused;
1794 /** Profiling time spent zeroing pages. */
1795 STAMPROFILE StatZeroPage;
1796# ifdef PGMPOOL_WITH_USER_TRACKING
1797 /** Profiling of pgmPoolTrackDeref. */
1798 STAMPROFILE StatTrackDeref;
1799 /** Profiling pgmTrackFlushGCPhysPT. */
1800 STAMPROFILE StatTrackFlushGCPhysPT;
1801 /** Profiling pgmTrackFlushGCPhysPTs. */
1802 STAMPROFILE StatTrackFlushGCPhysPTs;
1803 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1804 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1805 /** Number of times we've been out of user records. */
1806 STAMCOUNTER StatTrackFreeUpOneUser;
1807# endif
1808# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1809 /** Profiling deref activity related tracking GC physical pages. */
1810 STAMPROFILE StatTrackDerefGCPhys;
1811 /** Number of linear searches for a HCPhys in the ram ranges. */
1812 STAMCOUNTER StatTrackLinearRamSearches;
1813 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1814 STAMCOUNTER StamTrackPhysExtAllocFailures;
1815# endif
1816# ifdef PGMPOOL_WITH_MONITORING
1817 /** Profiling the RC/R0 access handler. */
1818 STAMPROFILE StatMonitorRZ;
1819 /** Times we've failed interpreting the instruction. */
1820 STAMCOUNTER StatMonitorRZEmulateInstr;
1821 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1822 STAMPROFILE StatMonitorRZFlushPage;
1823 /* Times we've detected a page table reinit. */
1824 STAMCOUNTER StatMonitorRZFlushReinit;
1825 /** Times we've detected fork(). */
1826 STAMCOUNTER StatMonitorRZFork;
1827 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1828 STAMPROFILE StatMonitorRZHandled;
1829 /** Times we've failed interpreting a patch code instruction. */
1830 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1831 /** Times we've failed interpreting a patch code instruction during flushing. */
1832 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1833 /** The number of times we've seen rep prefixes we can't handle. */
1834 STAMCOUNTER StatMonitorRZRepPrefix;
1835 /** Profiling the REP STOSD cases we've handled. */
1836 STAMPROFILE StatMonitorRZRepStosd;
1837
1838 /** Profiling the R3 access handler. */
1839 STAMPROFILE StatMonitorR3;
1840 /** Times we've failed interpreting the instruction. */
1841 STAMCOUNTER StatMonitorR3EmulateInstr;
1842 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1843 STAMPROFILE StatMonitorR3FlushPage;
1844 /* Times we've detected a page table reinit. */
1845 STAMCOUNTER StatMonitorR3FlushReinit;
1846 /** Times we've detected fork(). */
1847 STAMCOUNTER StatMonitorR3Fork;
1848 /** Profiling the R3 access we've handled (except REP STOSD). */
1849 STAMPROFILE StatMonitorR3Handled;
1850 /** The number of times we've seen rep prefixes we can't handle. */
1851 STAMCOUNTER StatMonitorR3RepPrefix;
1852 /** Profiling the REP STOSD cases we've handled. */
1853 STAMPROFILE StatMonitorR3RepStosd;
1854 /** The number of times we're called in an async thread an need to flush. */
1855 STAMCOUNTER StatMonitorR3Async;
1856 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
1857 STAMCOUNTER StatResetDirtyPages;
1858 /** Times we've called pgmPoolAddDirtyPage. */
1859 STAMCOUNTER StatDirtyPage;
1860 /** Times we've had to flush duplicates for dirty page management. */
1861 STAMCOUNTER StatDirtyPageDupFlush;
1862
1863 /** The high wather mark for cModifiedPages. */
1864 uint16_t cModifiedPagesHigh;
1865 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1866# endif
1867# ifdef PGMPOOL_WITH_CACHE
1868 /** The number of cache hits. */
1869 STAMCOUNTER StatCacheHits;
1870 /** The number of cache misses. */
1871 STAMCOUNTER StatCacheMisses;
1872 /** The number of times we've got a conflict of 'kind' in the cache. */
1873 STAMCOUNTER StatCacheKindMismatches;
1874 /** Number of times we've been out of pages. */
1875 STAMCOUNTER StatCacheFreeUpOne;
1876 /** The number of cacheable allocations. */
1877 STAMCOUNTER StatCacheCacheable;
1878 /** The number of uncacheable allocations. */
1879 STAMCOUNTER StatCacheUncacheable;
1880# endif
1881#elif HC_ARCH_BITS == 64
1882 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1883#endif
1884 /** The AVL tree for looking up a page by its HC physical address. */
1885 AVLOHCPHYSTREE HCPhysTree;
1886 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1887 /** Array of pages. (cMaxPages in length)
1888 * The Id is the index into thist array.
1889 */
1890 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1891} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1892
1893
1894/** @def PGMPOOL_PAGE_2_PTR
1895 * Maps a pool page pool into the current context.
1896 *
1897 * @returns VBox status code.
1898 * @param pVM The VM handle.
1899 * @param pPage The pool page.
1900 *
1901 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1902 * small page window employeed by that function. Be careful.
1903 * @remark There is no need to assert on the result.
1904 */
1905#if defined(IN_RC)
1906# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1907#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1908# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1909#elif defined(VBOX_STRICT)
1910# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1911DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1912{
1913 Assert(pPage && pPage->pvPageR3);
1914 return pPage->pvPageR3;
1915}
1916#else
1917# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1918#endif
1919
1920/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1921 * Maps a pool page pool into the current context.
1922 *
1923 * @returns VBox status code.
1924 * @param pPGM Pointer to the PGM instance data.
1925 * @param pPage The pool page.
1926 *
1927 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1928 * small page window employeed by that function. Be careful.
1929 * @remark There is no need to assert on the result.
1930 */
1931#if defined(IN_RC)
1932# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1933#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1934# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1935#else
1936# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1937#endif
1938
1939/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1940 * Maps a pool page pool into the current context.
1941 *
1942 * @returns VBox status code.
1943 * @param pPGM Pointer to the PGMCPU instance data.
1944 * @param pPage The pool page.
1945 *
1946 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1947 * small page window employeed by that function. Be careful.
1948 * @remark There is no need to assert on the result.
1949 */
1950#if defined(IN_RC)
1951# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1952#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1953# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1954#else
1955# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1956#endif
1957
1958
1959/** @name Per guest page tracking data.
1960 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1961 * is to use more bits for it and split it up later on. But for now we'll play
1962 * safe and change as little as possible.
1963 *
1964 * The 16-bit word has two parts:
1965 *
1966 * The first 14-bit forms the @a idx field. It is either the index of a page in
1967 * the shadow page pool, or and index into the extent list.
1968 *
1969 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1970 * shadow page pool references to the page. If cRefs equals
1971 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1972 * (misnomer) table and not the shadow page pool.
1973 *
1974 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1975 * the 16-bit word.
1976 *
1977 * @{ */
1978/** The shift count for getting to the cRefs part. */
1979#define PGMPOOL_TD_CREFS_SHIFT 14
1980/** The mask applied after shifting the tracking data down by
1981 * PGMPOOL_TD_CREFS_SHIFT. */
1982#define PGMPOOL_TD_CREFS_MASK 0x3
1983/** The cRef value used to indiciate that the idx is the head of a
1984 * physical cross reference list. */
1985#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1986/** The shift used to get idx. */
1987#define PGMPOOL_TD_IDX_SHIFT 0
1988/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1989#define PGMPOOL_TD_IDX_MASK 0x3fff
1990/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1991 * simply too many mappings of this page. */
1992#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1993
1994/** @def PGMPOOL_TD_MAKE
1995 * Makes a 16-bit tracking data word.
1996 *
1997 * @returns tracking data.
1998 * @param cRefs The @a cRefs field. Must be within bounds!
1999 * @param idx The @a idx field. Must also be within bounds! */
2000#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2001
2002/** @def PGMPOOL_TD_GET_CREFS
2003 * Get the @a cRefs field from a tracking data word.
2004 *
2005 * @returns The @a cRefs field
2006 * @param u16 The tracking data word. */
2007#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2008
2009/** @def PGMPOOL_TD_GET_IDX
2010 * Get the @a idx field from a tracking data word.
2011 *
2012 * @returns The @a idx field
2013 * @param u16 The tracking data word. */
2014#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2015/** @} */
2016
2017
2018/**
2019 * Trees are using self relative offsets as pointers.
2020 * So, all its data, including the root pointer, must be in the heap for HC and GC
2021 * to have the same layout.
2022 */
2023typedef struct PGMTREES
2024{
2025 /** Physical access handlers (AVL range+offsetptr tree). */
2026 AVLROGCPHYSTREE PhysHandlers;
2027 /** Virtual access handlers (AVL range + GC ptr tree). */
2028 AVLROGCPTRTREE VirtHandlers;
2029 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2030 AVLROGCPHYSTREE PhysToVirtHandlers;
2031 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2032 AVLROGCPTRTREE HyperVirtHandlers;
2033} PGMTREES;
2034/** Pointer to PGM trees. */
2035typedef PGMTREES *PPGMTREES;
2036
2037
2038/** @name Paging mode macros
2039 * @{ */
2040#ifdef IN_RC
2041# define PGM_CTX(a,b) a##RC##b
2042# define PGM_CTX_STR(a,b) a "GC" b
2043# define PGM_CTX_DECL(type) VMMRCDECL(type)
2044#else
2045# ifdef IN_RING3
2046# define PGM_CTX(a,b) a##R3##b
2047# define PGM_CTX_STR(a,b) a "R3" b
2048# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2049# else
2050# define PGM_CTX(a,b) a##R0##b
2051# define PGM_CTX_STR(a,b) a "R0" b
2052# define PGM_CTX_DECL(type) VMMDECL(type)
2053# endif
2054#endif
2055
2056#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2057#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2058#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2059#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2060#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2061#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2062#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2063#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2064#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2065#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2066#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2067#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2068#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2069#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2070#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2071#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2072#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2073
2074#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2075#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2076#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2077#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2078#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2079#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2080#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2081#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2082#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2083#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2084#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2085#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2086#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2087#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2088#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2089#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2090#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2091
2092/* Shw_Gst */
2093#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2094#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2095#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2096#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2097#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2098#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2099#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2100#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2101#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2102#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2103#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2104#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2105#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2106#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2107#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2108#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2109#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2110#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2111#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2112
2113#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2114#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2115#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2116#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2117#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2118#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2119#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2120#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2121#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2122#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2123#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2124#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2125#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2126#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2127#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2128#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2129#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2130#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2131#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2132#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2133#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2134#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2135#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2136#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2137#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2138#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2139#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2140#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2141#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2142#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2143#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2144#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2145#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2146#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2147#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2148#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2149#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2150
2151#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2152#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2153/** @} */
2154
2155/**
2156 * Data for each paging mode.
2157 */
2158typedef struct PGMMODEDATA
2159{
2160 /** The guest mode type. */
2161 uint32_t uGstType;
2162 /** The shadow mode type. */
2163 uint32_t uShwType;
2164
2165 /** @name Function pointers for Shadow paging.
2166 * @{
2167 */
2168 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2169 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2170 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2171 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2172
2173 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2174 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2175
2176 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2177 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2178 /** @} */
2179
2180 /** @name Function pointers for Guest paging.
2181 * @{
2182 */
2183 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2184 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2185 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2186 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2187 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2188 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2189 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2190 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2191 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2192 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2193 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2194 /** @} */
2195
2196 /** @name Function pointers for Both Shadow and Guest paging.
2197 * @{
2198 */
2199 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2200 /* no pfnR3BthTrap0eHandler */
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2202 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2203 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2204 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2206#ifdef VBOX_STRICT
2207 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2208#endif
2209 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2210 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2211
2212 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2213 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2214 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2215 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2216 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2218#ifdef VBOX_STRICT
2219 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2220#endif
2221 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2222 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2223
2224 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2225 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2226 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2227 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2228 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2230#ifdef VBOX_STRICT
2231 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2232#endif
2233 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2234 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2235 /** @} */
2236} PGMMODEDATA, *PPGMMODEDATA;
2237
2238
2239
2240/**
2241 * Converts a PGM pointer into a VM pointer.
2242 * @returns Pointer to the VM structure the PGM is part of.
2243 * @param pPGM Pointer to PGM instance data.
2244 */
2245#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2246
2247/**
2248 * PGM Data (part of VM)
2249 */
2250typedef struct PGM
2251{
2252 /** Offset to the VM structure. */
2253 RTINT offVM;
2254 /** Offset of the PGMCPU structure relative to VMCPU. */
2255 RTINT offVCpuPGM;
2256
2257 /** @cfgm{RamPreAlloc, boolean, false}
2258 * Indicates whether the base RAM should all be allocated before starting
2259 * the VM (default), or if it should be allocated when first written to.
2260 */
2261 bool fRamPreAlloc;
2262 /** Alignment padding. */
2263 bool afAlignment0[11];
2264
2265 /*
2266 * This will be redefined at least two more times before we're done, I'm sure.
2267 * The current code is only to get on with the coding.
2268 * - 2004-06-10: initial version, bird.
2269 * - 2004-07-02: 1st time, bird.
2270 * - 2004-10-18: 2nd time, bird.
2271 * - 2005-07-xx: 3rd time, bird.
2272 */
2273
2274 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2275 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2276 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2277 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2278
2279 /** The host paging mode. (This is what SUPLib reports.) */
2280 SUPPAGINGMODE enmHostMode;
2281
2282 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2283 RTGCPHYS GCPhys4MBPSEMask;
2284
2285 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2286 * This is sorted by physical address and contains no overlapping ranges. */
2287 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2288 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2289 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2290 /** RC pointer corresponding to PGM::pRamRangesR3. */
2291 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2292 RTRCPTR alignment4; /**< structure alignment. */
2293
2294 /** Pointer to the list of ROM ranges - for R3.
2295 * This is sorted by physical address and contains no overlapping ranges. */
2296 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2297 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2298 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2299 /** RC pointer corresponding to PGM::pRomRangesR3. */
2300 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2301 /** Alignment padding. */
2302 RTRCPTR GCPtrPadding2;
2303
2304 /** Pointer to the list of MMIO2 ranges - for R3.
2305 * Registration order. */
2306 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2307
2308 /** PGM offset based trees - R3 Ptr. */
2309 R3PTRTYPE(PPGMTREES) pTreesR3;
2310 /** PGM offset based trees - R0 Ptr. */
2311 R0PTRTYPE(PPGMTREES) pTreesR0;
2312 /** PGM offset based trees - RC Ptr. */
2313 RCPTRTYPE(PPGMTREES) pTreesRC;
2314
2315 /** Linked list of GC mappings - for RC.
2316 * The list is sorted ascending on address.
2317 */
2318 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2319 /** Linked list of GC mappings - for HC.
2320 * The list is sorted ascending on address.
2321 */
2322 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2323 /** Linked list of GC mappings - for R0.
2324 * The list is sorted ascending on address.
2325 */
2326 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2327
2328 /** Pointer to the 5 page CR3 content mapping.
2329 * The first page is always the CR3 (in some form) while the 4 other pages
2330 * are used of the PDs in PAE mode. */
2331 RTGCPTR GCPtrCR3Mapping;
2332#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2333 uint32_t u32Alignment;
2334#endif
2335
2336 /** Indicates that PGMR3FinalizeMappings has been called and that further
2337 * PGMR3MapIntermediate calls will be rejected. */
2338 bool fFinalizedMappings;
2339 /** If set no conflict checks are required. (boolean) */
2340 bool fMappingsFixed;
2341 /** If set, then no mappings are put into the shadow page table. (boolean) */
2342 bool fDisableMappings;
2343 /** Size of fixed mapping */
2344 uint32_t cbMappingFixed;
2345 /** Base address (GC) of fixed mapping */
2346 RTGCPTR GCPtrMappingFixed;
2347 /** The address of the previous RAM range mapping. */
2348 RTGCPTR GCPtrPrevRamRangeMapping;
2349
2350 /** @name Intermediate Context
2351 * @{ */
2352 /** Pointer to the intermediate page directory - Normal. */
2353 R3PTRTYPE(PX86PD) pInterPD;
2354 /** Pointer to the intermedate page tables - Normal.
2355 * There are two page tables, one for the identity mapping and one for
2356 * the host context mapping (of the core code). */
2357 R3PTRTYPE(PX86PT) apInterPTs[2];
2358 /** Pointer to the intermedate page tables - PAE. */
2359 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2360 /** Pointer to the intermedate page directory - PAE. */
2361 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2362 /** Pointer to the intermedate page directory - PAE. */
2363 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2364 /** Pointer to the intermedate page-map level 4 - AMD64. */
2365 R3PTRTYPE(PX86PML4) pInterPaePML4;
2366 /** Pointer to the intermedate page directory - AMD64. */
2367 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2368 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2369 RTHCPHYS HCPhysInterPD;
2370 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2371 RTHCPHYS HCPhysInterPaePDPT;
2372 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2373 RTHCPHYS HCPhysInterPaePML4;
2374 /** @} */
2375
2376 /** Base address of the dynamic page mapping area.
2377 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2378 */
2379 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2380 /** The index of the last entry used in the dynamic page mapping area. */
2381 RTUINT iDynPageMapLast;
2382 /** Cache containing the last entries in the dynamic page mapping area.
2383 * The cache size is covering half of the mapping area. */
2384 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2385 /** Keep a lock counter for the full (!) mapping area. */
2386 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2387
2388 /** The address of the ring-0 mapping cache if we're making use of it. */
2389 RTR0PTR pvR0DynMapUsed;
2390
2391 /** PGM critical section.
2392 * This protects the physical & virtual access handlers, ram ranges,
2393 * and the page flag updating (some of it anyway).
2394 */
2395 PDMCRITSECT CritSect;
2396
2397 /** Pointer to SHW+GST mode data (function pointers).
2398 * The index into this table is made up from */
2399 R3PTRTYPE(PPGMMODEDATA) paModeData;
2400
2401 /** Shadow Page Pool - R3 Ptr. */
2402 R3PTRTYPE(PPGMPOOL) pPoolR3;
2403 /** Shadow Page Pool - R0 Ptr. */
2404 R0PTRTYPE(PPGMPOOL) pPoolR0;
2405 /** Shadow Page Pool - RC Ptr. */
2406 RCPTRTYPE(PPGMPOOL) pPoolRC;
2407
2408 /** We're not in a state which permits writes to guest memory.
2409 * (Only used in strict builds.) */
2410 bool fNoMorePhysWrites;
2411
2412 /**
2413 * Data associated with managing the ring-3 mappings of the allocation chunks.
2414 */
2415 struct
2416 {
2417 /** The chunk tree, ordered by chunk id. */
2418#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2419 R3PTRTYPE(PAVLU32NODECORE) pTree;
2420#else
2421 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2422#endif
2423 /** The chunk mapping TLB. */
2424 PGMCHUNKR3MAPTLB Tlb;
2425 /** The number of mapped chunks. */
2426 uint32_t c;
2427 /** The maximum number of mapped chunks.
2428 * @cfgm PGM/MaxRing3Chunks */
2429 uint32_t cMax;
2430 /** The chunk age tree, ordered by ageing sequence number. */
2431 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2432 /** The current time. */
2433 uint32_t iNow;
2434 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2435 uint32_t AgeingCountdown;
2436 } ChunkR3Map;
2437
2438 /**
2439 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2440 */
2441 PGMPAGER3MAPTLB PhysTlbHC;
2442
2443 /** @name The zero page.
2444 * @{ */
2445 /** The host physical address of the zero page. */
2446 RTHCPHYS HCPhysZeroPg;
2447 /** The ring-3 mapping of the zero page. */
2448 RTR3PTR pvZeroPgR3;
2449 /** The ring-0 mapping of the zero page. */
2450 RTR0PTR pvZeroPgR0;
2451 /** The GC mapping of the zero page. */
2452 RTGCPTR pvZeroPgRC;
2453#if GC_ARCH_BITS != 32
2454 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2455#endif
2456 /** @}*/
2457
2458 /** The number of handy pages. */
2459 uint32_t cHandyPages;
2460 /**
2461 * Array of handy pages.
2462 *
2463 * This array is used in a two way communication between pgmPhysAllocPage
2464 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2465 * an intermediary.
2466 *
2467 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2468 * (The current size of 32 pages, means 128 KB of handy memory.)
2469 */
2470 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2471
2472 /** @name Error injection.
2473 * @{ */
2474 /** Inject handy page allocation errors pretending we're completely out of
2475 * memory. */
2476 bool volatile fErrInjHandyPages;
2477 /** Padding. */
2478 bool afReserved[7];
2479 /** @} */
2480
2481 /** @name Release Statistics
2482 * @{ */
2483 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2484 uint32_t cPrivatePages; /**< The number of private pages. */
2485 uint32_t cSharedPages; /**< The number of shared pages. */
2486 uint32_t cZeroPages; /**< The number of zero backed pages. */
2487
2488 /** The number of times we were forced to change the hypervisor region location. */
2489 STAMCOUNTER cRelocations;
2490 /** @} */
2491
2492#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2493 /* R3 only: */
2494 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2495 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2496
2497 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2498 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2499 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2500 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2501 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2502 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2503 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2504 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2505 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2506 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2507 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2508 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2509 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2510 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2511 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2512 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2513 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2514 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2515/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2516 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2517 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2518/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2519
2520 /* RC only: */
2521 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2522 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2523 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2524 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2525
2526 STAMCOUNTER StatRZPhysRead;
2527 STAMCOUNTER StatRZPhysReadBytes;
2528 STAMCOUNTER StatRZPhysWrite;
2529 STAMCOUNTER StatRZPhysWriteBytes;
2530 STAMCOUNTER StatR3PhysRead;
2531 STAMCOUNTER StatR3PhysReadBytes;
2532 STAMCOUNTER StatR3PhysWrite;
2533 STAMCOUNTER StatR3PhysWriteBytes;
2534 STAMCOUNTER StatRCPhysRead;
2535 STAMCOUNTER StatRCPhysReadBytes;
2536 STAMCOUNTER StatRCPhysWrite;
2537 STAMCOUNTER StatRCPhysWriteBytes;
2538
2539 STAMCOUNTER StatRZPhysSimpleRead;
2540 STAMCOUNTER StatRZPhysSimpleReadBytes;
2541 STAMCOUNTER StatRZPhysSimpleWrite;
2542 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2543 STAMCOUNTER StatR3PhysSimpleRead;
2544 STAMCOUNTER StatR3PhysSimpleReadBytes;
2545 STAMCOUNTER StatR3PhysSimpleWrite;
2546 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2547 STAMCOUNTER StatRCPhysSimpleRead;
2548 STAMCOUNTER StatRCPhysSimpleReadBytes;
2549 STAMCOUNTER StatRCPhysSimpleWrite;
2550 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2551
2552# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2553 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2554 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2555 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2556 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2557 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2558 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2559# endif
2560#endif
2561} PGM;
2562/** Pointer to the PGM instance data. */
2563typedef PGM *PPGM;
2564
2565
2566/**
2567 * Converts a PGMCPU pointer into a VM pointer.
2568 * @returns Pointer to the VM structure the PGM is part of.
2569 * @param pPGM Pointer to PGMCPU instance data.
2570 */
2571#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2572
2573/**
2574 * Converts a PGMCPU pointer into a PGM pointer.
2575 * @returns Pointer to the VM structure the PGM is part of.
2576 * @param pPGM Pointer to PGMCPU instance data.
2577 */
2578#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2579
2580/**
2581 * PGMCPU Data (part of VMCPU).
2582 */
2583typedef struct PGMCPU
2584{
2585 /** Offset to the VM structure. */
2586 RTINT offVM;
2587 /** Offset to the VMCPU structure. */
2588 RTINT offVCpu;
2589 /** Offset of the PGM structure relative to VMCPU. */
2590 RTINT offPGM;
2591 RTINT uPadding0; /**< structure size alignment. */
2592
2593#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2594 /** Automatically tracked physical memory mapping set.
2595 * Ring-0 and strict raw-mode builds. */
2596 PGMMAPSET AutoSet;
2597#endif
2598
2599 /** A20 gate mask.
2600 * Our current approach to A20 emulation is to let REM do it and don't bother
2601 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2602 * But whould need arrise, we'll subject physical addresses to this mask. */
2603 RTGCPHYS GCPhysA20Mask;
2604 /** A20 gate state - boolean! */
2605 bool fA20Enabled;
2606
2607 /** What needs syncing (PGM_SYNC_*).
2608 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2609 * PGMFlushTLB, and PGMR3Load. */
2610 RTUINT fSyncFlags;
2611
2612 /** The shadow paging mode. */
2613 PGMMODE enmShadowMode;
2614 /** The guest paging mode. */
2615 PGMMODE enmGuestMode;
2616
2617 /** The current physical address representing in the guest CR3 register. */
2618 RTGCPHYS GCPhysCR3;
2619
2620 /** @name 32-bit Guest Paging.
2621 * @{ */
2622 /** The guest's page directory, R3 pointer. */
2623 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2624#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2625 /** The guest's page directory, R0 pointer. */
2626 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2627#endif
2628 /** The guest's page directory, static RC mapping. */
2629 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2630 /** @} */
2631
2632 /** @name PAE Guest Paging.
2633 * @{ */
2634 /** The guest's page directory pointer table, static RC mapping. */
2635 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2636 /** The guest's page directory pointer table, R3 pointer. */
2637 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2638#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2639 /** The guest's page directory pointer table, R0 pointer. */
2640 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2641#endif
2642
2643 /** The guest's page directories, R3 pointers.
2644 * These are individual pointers and don't have to be adjecent.
2645 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2646 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2647 /** The guest's page directories, R0 pointers.
2648 * Same restrictions as apGstPaePDsR3. */
2649#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2650 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2651#endif
2652 /** The guest's page directories, static GC mapping.
2653 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2654 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2655 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2656 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2657 RTGCPHYS aGCPhysGstPaePDs[4];
2658 /** The physical addresses of the monitored guest page directories (PAE). */
2659 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2660 /** @} */
2661
2662 /** @name AMD64 Guest Paging.
2663 * @{ */
2664 /** The guest's page directory pointer table, R3 pointer. */
2665 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2666#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2667 /** The guest's page directory pointer table, R0 pointer. */
2668 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2669#endif
2670 /** @} */
2671
2672 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2673 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2674 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2675 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2676 /** Pointer to the page of the current active CR3 - RC Ptr. */
2677 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2678 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2679 uint32_t iShwUser;
2680 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2681 uint32_t iShwUserTable;
2682# if HC_ARCH_BITS == 64
2683 RTRCPTR alignment6; /**< structure size alignment. */
2684# endif
2685 /** @} */
2686
2687 /** @name Function pointers for Shadow paging.
2688 * @{
2689 */
2690 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2691 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2692 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2693 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2694
2695 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2696 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2697
2698 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2699 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2700
2701 /** @} */
2702
2703 /** @name Function pointers for Guest paging.
2704 * @{
2705 */
2706 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2707 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2708 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2709 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2710 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2711 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2712 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2713 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2714#if HC_ARCH_BITS == 64
2715 RTRCPTR alignment3; /**< structure size alignment. */
2716#endif
2717
2718 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2719 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2720 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2721 /** @} */
2722
2723 /** @name Function pointers for Both Shadow and Guest paging.
2724 * @{
2725 */
2726 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2727 /* no pfnR3BthTrap0eHandler */
2728 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2729 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2730 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2731 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2732 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2733 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2734 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2735 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2736
2737 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2738 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2739 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2740 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2741 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2742 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2743 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2744 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2745 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2746
2747 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2748 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2749 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2750 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2751 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2752 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2753 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2754 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2755 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2756#if HC_ARCH_BITS == 64
2757 RTRCPTR alignment2; /**< structure size alignment. */
2758#endif
2759 /** @} */
2760
2761 /** For saving stack space, the disassembler state is allocated here instead of
2762 * on the stack.
2763 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2764 union
2765 {
2766 /** The disassembler scratch space. */
2767 DISCPUSTATE DisState;
2768 /** Padding. */
2769 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2770 };
2771
2772 /* Count the number of pgm pool access handler calls. */
2773 uint64_t cPoolAccessHandler;
2774
2775 /** @name Release Statistics
2776 * @{ */
2777 /** The number of times the guest has switched mode since last reset or statistics reset. */
2778 STAMCOUNTER cGuestModeChanges;
2779 /** @} */
2780
2781#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2782 /** @name Statistics
2783 * @{ */
2784 /** RC: Which statistic this \#PF should be attributed to. */
2785 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2786 RTRCPTR padding0;
2787 /** R0: Which statistic this \#PF should be attributed to. */
2788 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2789 RTR0PTR padding1;
2790
2791 /* Common */
2792 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2793 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2794
2795 /* R0 only: */
2796 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2797 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2798 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2799 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2800 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2801 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2802 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2803 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2804 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2805 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2806 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2807 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2808 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2809 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2810 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2811 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2812 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2813 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2814 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2815 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2816 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2817 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2818 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2819 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2820 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2821 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2822
2823 /* RZ only: */
2824 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2825 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2826 STAMPROFILE StatRZTrap0eTimeSyncPT;
2827 STAMPROFILE StatRZTrap0eTimeMapping;
2828 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2829 STAMPROFILE StatRZTrap0eTimeHandlers;
2830 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2831 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2832 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2833 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2834 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2835 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2836 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2837 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2838 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2839 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2840 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2841 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2842 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2843 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2844 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2845 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2846 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2847 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2848 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2849 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2850 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2851 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2852 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2853 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2854 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2856 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2857 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2858 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2859 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2860 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2861 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2862 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2863 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2864 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2865 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2866 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2867 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2868 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2869 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2870 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2871 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2872 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2873
2874 /* HC - R3 and (maybe) R0: */
2875
2876 /* RZ & R3: */
2877 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2878 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2879 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2880 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2881 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2882 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2883 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2884 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2885 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2886 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2887 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2888 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2889 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2890 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2891 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2892 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2893 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2894 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2895 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2896 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2897 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2898 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2899 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
2900 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2901 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2902 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2903 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2904 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2905 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2906 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2907 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2908 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2909 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2910 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2911 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2912 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2913 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2914 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2915 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2916 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2917 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2918 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2919 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2920 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2921
2922 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2923 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2924 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2925 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2926 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2927 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2928 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2929 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2930 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2931 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2932 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2933 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2934 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2935 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2936 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2937 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2938 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2939 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2940 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2941 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2942 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2943 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2944 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2945 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2946 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2947 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2948 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2949 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2950 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2951 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2952 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2953 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2954 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2955 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2956 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2957 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2958 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2959 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2960 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2961 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2962 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2963 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2964 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2965 /** @} */
2966#endif /* VBOX_WITH_STATISTICS */
2967} PGMCPU;
2968/** Pointer to the per-cpu PGM data. */
2969typedef PGMCPU *PPGMCPU;
2970
2971
2972/** @name PGM::fSyncFlags Flags
2973 * @{
2974 */
2975/** Updates the virtual access handler state bit in PGMPAGE. */
2976#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2977/** Always sync CR3. */
2978#define PGM_SYNC_ALWAYS RT_BIT(1)
2979/** Check monitoring on next CR3 (re)load and invalidate page.
2980 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2981#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2982/** Check guest mapping in SyncCR3. */
2983#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2984/** Clear the page pool (a light weight flush). */
2985#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2986#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2987/** @} */
2988
2989
2990RT_C_DECLS_BEGIN
2991
2992int pgmLock(PVM pVM);
2993void pgmUnlock(PVM pVM);
2994
2995int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2996int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2997PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2998void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2999DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3000
3001void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3002bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3003void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3004int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3005DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3006#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3007void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3008#else
3009# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3010#endif
3011DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3012
3013
3014int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3015int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3016int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3017int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3018int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3019int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3020int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3021int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3022int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3023VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3024#ifdef IN_RING3
3025void pgmR3PhysRelinkRamRanges(PVM pVM);
3026int pgmR3PhysRamPreAllocate(PVM pVM);
3027int pgmR3PhysRamReset(PVM pVM);
3028int pgmR3PhysRomReset(PVM pVM);
3029int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3030
3031int pgmR3PoolInit(PVM pVM);
3032void pgmR3PoolRelocate(PVM pVM);
3033void pgmR3PoolReset(PVM pVM);
3034
3035#endif /* IN_RING3 */
3036#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3037int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3038#endif
3039int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3040
3041DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3042{
3043 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3044}
3045
3046void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3047void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3048int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3049void pgmPoolClearAll(PVM pVM);
3050PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3051int pgmPoolSyncCR3(PVMCPU pVCpu);
3052bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3053int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3054uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3055void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3056void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3057#ifdef PGMPOOL_WITH_MONITORING
3058void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3059int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3060void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3061#endif
3062
3063void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3064void pgmPoolResetDirtyPages(PVM pVM, bool fForceRemoval = false);
3065
3066int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3067int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3068
3069void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3070void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3071int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3072int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3073
3074int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3075#ifndef IN_RC
3076int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3077#endif
3078int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3079
3080PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3081PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3082PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3083PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3084
3085RT_C_DECLS_END
3086
3087
3088/**
3089 * Gets the PGMRAMRANGE structure for a guest page.
3090 *
3091 * @returns Pointer to the RAM range on success.
3092 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3093 *
3094 * @param pPGM PGM handle.
3095 * @param GCPhys The GC physical address.
3096 */
3097DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3098{
3099 /*
3100 * Optimize for the first range.
3101 */
3102 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3103 RTGCPHYS off = GCPhys - pRam->GCPhys;
3104 if (RT_UNLIKELY(off >= pRam->cb))
3105 {
3106 do
3107 {
3108 pRam = pRam->CTX_SUFF(pNext);
3109 if (RT_UNLIKELY(!pRam))
3110 break;
3111 off = GCPhys - pRam->GCPhys;
3112 } while (off >= pRam->cb);
3113 }
3114 return pRam;
3115}
3116
3117
3118/**
3119 * Gets the PGMPAGE structure for a guest page.
3120 *
3121 * @returns Pointer to the page on success.
3122 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3123 *
3124 * @param pPGM PGM handle.
3125 * @param GCPhys The GC physical address.
3126 */
3127DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3128{
3129 /*
3130 * Optimize for the first range.
3131 */
3132 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3133 RTGCPHYS off = GCPhys - pRam->GCPhys;
3134 if (RT_UNLIKELY(off >= pRam->cb))
3135 {
3136 do
3137 {
3138 pRam = pRam->CTX_SUFF(pNext);
3139 if (RT_UNLIKELY(!pRam))
3140 return NULL;
3141 off = GCPhys - pRam->GCPhys;
3142 } while (off >= pRam->cb);
3143 }
3144 return &pRam->aPages[off >> PAGE_SHIFT];
3145}
3146
3147
3148/**
3149 * Gets the PGMPAGE structure for a guest page.
3150 *
3151 * Old Phys code: Will make sure the page is present.
3152 *
3153 * @returns VBox status code.
3154 * @retval VINF_SUCCESS and a valid *ppPage on success.
3155 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3156 *
3157 * @param pPGM PGM handle.
3158 * @param GCPhys The GC physical address.
3159 * @param ppPage Where to store the page poitner on success.
3160 */
3161DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3162{
3163 /*
3164 * Optimize for the first range.
3165 */
3166 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3167 RTGCPHYS off = GCPhys - pRam->GCPhys;
3168 if (RT_UNLIKELY(off >= pRam->cb))
3169 {
3170 do
3171 {
3172 pRam = pRam->CTX_SUFF(pNext);
3173 if (RT_UNLIKELY(!pRam))
3174 {
3175 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3176 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3177 }
3178 off = GCPhys - pRam->GCPhys;
3179 } while (off >= pRam->cb);
3180 }
3181 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3182 return VINF_SUCCESS;
3183}
3184
3185
3186
3187
3188/**
3189 * Gets the PGMPAGE structure for a guest page.
3190 *
3191 * Old Phys code: Will make sure the page is present.
3192 *
3193 * @returns VBox status code.
3194 * @retval VINF_SUCCESS and a valid *ppPage on success.
3195 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3196 *
3197 * @param pPGM PGM handle.
3198 * @param GCPhys The GC physical address.
3199 * @param ppPage Where to store the page poitner on success.
3200 * @param ppRamHint Where to read and store the ram list hint.
3201 * The caller initializes this to NULL before the call.
3202 */
3203DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3204{
3205 RTGCPHYS off;
3206 PPGMRAMRANGE pRam = *ppRamHint;
3207 if ( !pRam
3208 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3209 {
3210 pRam = pPGM->CTX_SUFF(pRamRanges);
3211 off = GCPhys - pRam->GCPhys;
3212 if (RT_UNLIKELY(off >= pRam->cb))
3213 {
3214 do
3215 {
3216 pRam = pRam->CTX_SUFF(pNext);
3217 if (RT_UNLIKELY(!pRam))
3218 {
3219 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3220 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3221 }
3222 off = GCPhys - pRam->GCPhys;
3223 } while (off >= pRam->cb);
3224 }
3225 *ppRamHint = pRam;
3226 }
3227 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3228 return VINF_SUCCESS;
3229}
3230
3231
3232/**
3233 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3234 *
3235 * @returns Pointer to the page on success.
3236 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3237 *
3238 * @param pPGM PGM handle.
3239 * @param GCPhys The GC physical address.
3240 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3241 */
3242DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3243{
3244 /*
3245 * Optimize for the first range.
3246 */
3247 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3248 RTGCPHYS off = GCPhys - pRam->GCPhys;
3249 if (RT_UNLIKELY(off >= pRam->cb))
3250 {
3251 do
3252 {
3253 pRam = pRam->CTX_SUFF(pNext);
3254 if (RT_UNLIKELY(!pRam))
3255 return NULL;
3256 off = GCPhys - pRam->GCPhys;
3257 } while (off >= pRam->cb);
3258 }
3259 *ppRam = pRam;
3260 return &pRam->aPages[off >> PAGE_SHIFT];
3261}
3262
3263
3264/**
3265 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3266 *
3267 * @returns Pointer to the page on success.
3268 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3269 *
3270 * @param pPGM PGM handle.
3271 * @param GCPhys The GC physical address.
3272 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3273 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3274 */
3275DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3276{
3277 /*
3278 * Optimize for the first range.
3279 */
3280 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3281 RTGCPHYS off = GCPhys - pRam->GCPhys;
3282 if (RT_UNLIKELY(off >= pRam->cb))
3283 {
3284 do
3285 {
3286 pRam = pRam->CTX_SUFF(pNext);
3287 if (RT_UNLIKELY(!pRam))
3288 {
3289 *ppRam = NULL; /* Shut up silly GCC warnings. */
3290 *ppPage = NULL; /* ditto */
3291 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3292 }
3293 off = GCPhys - pRam->GCPhys;
3294 } while (off >= pRam->cb);
3295 }
3296 *ppRam = pRam;
3297 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3298 return VINF_SUCCESS;
3299}
3300
3301
3302/**
3303 * Convert GC Phys to HC Phys.
3304 *
3305 * @returns VBox status.
3306 * @param pPGM PGM handle.
3307 * @param GCPhys The GC physical address.
3308 * @param pHCPhys Where to store the corresponding HC physical address.
3309 *
3310 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3311 * Avoid when writing new code!
3312 */
3313DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3314{
3315 PPGMPAGE pPage;
3316 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3317 if (RT_FAILURE(rc))
3318 return rc;
3319 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3320 return VINF_SUCCESS;
3321}
3322
3323#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3324
3325/**
3326 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3327 * optimizes access to pages already in the set.
3328 *
3329 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3330 * @param pPGM Pointer to the PVM instance data.
3331 * @param HCPhys The physical address of the page.
3332 * @param ppv Where to store the mapping address.
3333 */
3334DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3335{
3336 PVM pVM = PGM2VM(pPGM);
3337 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3338 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3339
3340 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3341 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3342 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3343
3344 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3345 unsigned iEntry = pSet->aiHashTable[iHash];
3346 if ( iEntry < pSet->cEntries
3347 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3348 {
3349 *ppv = pSet->aEntries[iEntry].pvPage;
3350 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3351 }
3352 else
3353 {
3354 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3355 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3356 }
3357
3358 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3359 return VINF_SUCCESS;
3360}
3361
3362
3363/**
3364 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3365 * access to pages already in the set.
3366 *
3367 * @returns See PGMDynMapGCPage.
3368 * @param pPGM Pointer to the PVM instance data.
3369 * @param HCPhys The physical address of the page.
3370 * @param ppv Where to store the mapping address.
3371 */
3372DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3373{
3374 PVM pVM = PGM2VM(pPGM);
3375 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3376
3377 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3378 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3379
3380 /*
3381 * Get the ram range.
3382 */
3383 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3384 RTGCPHYS off = GCPhys - pRam->GCPhys;
3385 if (RT_UNLIKELY(off >= pRam->cb
3386 /** @todo || page state stuff */))
3387 {
3388 /* This case is not counted into StatR0DynMapGCPageInl. */
3389 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3390 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3391 }
3392
3393 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3394 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3395
3396 /*
3397 * pgmR0DynMapHCPageInlined with out stats.
3398 */
3399 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3400 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3401 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3402
3403 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3404 unsigned iEntry = pSet->aiHashTable[iHash];
3405 if ( iEntry < pSet->cEntries
3406 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3407 {
3408 *ppv = pSet->aEntries[iEntry].pvPage;
3409 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3410 }
3411 else
3412 {
3413 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3414 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3415 }
3416
3417 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3418 return VINF_SUCCESS;
3419}
3420
3421
3422/**
3423 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3424 * access to pages already in the set.
3425 *
3426 * @returns See PGMDynMapGCPage.
3427 * @param pPGM Pointer to the PVM instance data.
3428 * @param HCPhys The physical address of the page.
3429 * @param ppv Where to store the mapping address.
3430 */
3431DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3432{
3433 PVM pVM = PGM2VM(pPGM);
3434 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3435
3436 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3437
3438 /*
3439 * Get the ram range.
3440 */
3441 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3442 RTGCPHYS off = GCPhys - pRam->GCPhys;
3443 if (RT_UNLIKELY(off >= pRam->cb
3444 /** @todo || page state stuff */))
3445 {
3446 /* This case is not counted into StatR0DynMapGCPageInl. */
3447 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3448 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3449 }
3450
3451 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3452 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3453
3454 /*
3455 * pgmR0DynMapHCPageInlined with out stats.
3456 */
3457 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3458 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3459 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3460
3461 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3462 unsigned iEntry = pSet->aiHashTable[iHash];
3463 if ( iEntry < pSet->cEntries
3464 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3465 {
3466 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3467 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3468 }
3469 else
3470 {
3471 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3472 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3473 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3474 }
3475
3476 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3477 return VINF_SUCCESS;
3478}
3479
3480#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3481#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3482
3483/**
3484 * Maps the page into current context (RC and maybe R0).
3485 *
3486 * @returns pointer to the mapping.
3487 * @param pVM Pointer to the PGM instance data.
3488 * @param pPage The page.
3489 */
3490DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3491{
3492 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3493 {
3494 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3495 void *pv;
3496# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3497 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3498# else
3499 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3500# endif
3501 return pv;
3502 }
3503 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3504}
3505
3506/**
3507 * Temporarily maps one host page specified by HC physical address, returning
3508 * pointer within the page.
3509 *
3510 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3511 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3512 *
3513 * @returns The address corresponding to HCPhys.
3514 * @param pPGM Pointer to the PVM instance data.
3515 * @param HCPhys HC Physical address of the page.
3516 */
3517DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3518{
3519 void *pv;
3520# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3521 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3522# else
3523 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3524# endif
3525 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3526 return pv;
3527}
3528
3529#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3530#ifndef IN_RC
3531
3532/**
3533 * Queries the Physical TLB entry for a physical guest page,
3534 * attempting to load the TLB entry if necessary.
3535 *
3536 * @returns VBox status code.
3537 * @retval VINF_SUCCESS on success
3538 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3539 *
3540 * @param pPGM The PGM instance handle.
3541 * @param GCPhys The address of the guest page.
3542 * @param ppTlbe Where to store the pointer to the TLB entry.
3543 */
3544DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3545{
3546 int rc;
3547 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3548 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3549 {
3550 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3551 rc = VINF_SUCCESS;
3552 }
3553 else
3554 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3555 *ppTlbe = pTlbe;
3556 return rc;
3557}
3558
3559
3560/**
3561 * Queries the Physical TLB entry for a physical guest page,
3562 * attempting to load the TLB entry if necessary.
3563 *
3564 * @returns VBox status code.
3565 * @retval VINF_SUCCESS on success
3566 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3567 *
3568 * @param pPGM The PGM instance handle.
3569 * @param pPage Pointer to the PGMPAGE structure corresponding to
3570 * GCPhys.
3571 * @param GCPhys The address of the guest page.
3572 * @param ppTlbe Where to store the pointer to the TLB entry.
3573 */
3574DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3575{
3576 int rc;
3577 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3578 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3579 {
3580 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3581 rc = VINF_SUCCESS;
3582 }
3583 else
3584 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3585 *ppTlbe = pTlbe;
3586 return rc;
3587}
3588
3589#endif /* !IN_RC */
3590
3591/**
3592 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3593 * Takes PSE-36 into account.
3594 *
3595 * @returns guest physical address
3596 * @param pPGM Pointer to the PGM instance data.
3597 * @param Pde Guest Pde
3598 */
3599DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3600{
3601 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3602 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3603
3604 return GCPhys & pPGM->GCPhys4MBPSEMask;
3605}
3606
3607
3608/**
3609 * Gets the page directory entry for the specified address (32-bit paging).
3610 *
3611 * @returns The page directory entry in question.
3612 * @param pPGM Pointer to the PGM instance data.
3613 * @param GCPtr The address.
3614 */
3615DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3616{
3617#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3618 PCX86PD pGuestPD = NULL;
3619 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3620 if (RT_FAILURE(rc))
3621 {
3622 X86PDE ZeroPde = {0};
3623 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3624 }
3625#else
3626 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3627# ifdef IN_RING3
3628 if (!pGuestPD)
3629 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3630# endif
3631#endif
3632 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3633}
3634
3635
3636/**
3637 * Gets the address of a specific page directory entry (32-bit paging).
3638 *
3639 * @returns Pointer the page directory entry in question.
3640 * @param pPGM Pointer to the PGM instance data.
3641 * @param GCPtr The address.
3642 */
3643DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3644{
3645#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3646 PX86PD pGuestPD = NULL;
3647 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3648 AssertRCReturn(rc, NULL);
3649#else
3650 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3651# ifdef IN_RING3
3652 if (!pGuestPD)
3653 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3654# endif
3655#endif
3656 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3657}
3658
3659
3660/**
3661 * Gets the address the guest page directory (32-bit paging).
3662 *
3663 * @returns Pointer the page directory entry in question.
3664 * @param pPGM Pointer to the PGM instance data.
3665 */
3666DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3667{
3668#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3669 PX86PD pGuestPD = NULL;
3670 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3671 AssertRCReturn(rc, NULL);
3672#else
3673 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3674# ifdef IN_RING3
3675 if (!pGuestPD)
3676 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3677# endif
3678#endif
3679 return pGuestPD;
3680}
3681
3682
3683/**
3684 * Gets the guest page directory pointer table.
3685 *
3686 * @returns Pointer to the page directory in question.
3687 * @returns NULL if the page directory is not present or on an invalid page.
3688 * @param pPGM Pointer to the PGM instance data.
3689 */
3690DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3691{
3692#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3693 PX86PDPT pGuestPDPT = NULL;
3694 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3695 AssertRCReturn(rc, NULL);
3696#else
3697 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3698# ifdef IN_RING3
3699 if (!pGuestPDPT)
3700 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3701# endif
3702#endif
3703 return pGuestPDPT;
3704}
3705
3706
3707/**
3708 * Gets the guest page directory pointer table entry for the specified address.
3709 *
3710 * @returns Pointer to the page directory in question.
3711 * @returns NULL if the page directory is not present or on an invalid page.
3712 * @param pPGM Pointer to the PGM instance data.
3713 * @param GCPtr The address.
3714 */
3715DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3716{
3717 AssertGCPtr32(GCPtr);
3718
3719#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3720 PX86PDPT pGuestPDPT = 0;
3721 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3722 AssertRCReturn(rc, 0);
3723#else
3724 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3725# ifdef IN_RING3
3726 if (!pGuestPDPT)
3727 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3728# endif
3729#endif
3730 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3731}
3732
3733
3734/**
3735 * Gets the page directory for the specified address.
3736 *
3737 * @returns Pointer to the page directory in question.
3738 * @returns NULL if the page directory is not present or on an invalid page.
3739 * @param pPGM Pointer to the PGM instance data.
3740 * @param GCPtr The address.
3741 */
3742DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3743{
3744 AssertGCPtr32(GCPtr);
3745
3746 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3747 AssertReturn(pGuestPDPT, NULL);
3748 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3749 if (pGuestPDPT->a[iPdpt].n.u1Present)
3750 {
3751#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3752 PX86PDPAE pGuestPD = NULL;
3753 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3754 AssertRCReturn(rc, NULL);
3755#else
3756 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3757 if ( !pGuestPD
3758 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3759 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3760#endif
3761 return pGuestPD;
3762 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3763 }
3764 return NULL;
3765}
3766
3767
3768/**
3769 * Gets the page directory entry for the specified address.
3770 *
3771 * @returns Pointer to the page directory entry in question.
3772 * @returns NULL if the page directory is not present or on an invalid page.
3773 * @param pPGM Pointer to the PGM instance data.
3774 * @param GCPtr The address.
3775 */
3776DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3777{
3778 AssertGCPtr32(GCPtr);
3779
3780 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3781 AssertReturn(pGuestPDPT, NULL);
3782 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3783 if (pGuestPDPT->a[iPdpt].n.u1Present)
3784 {
3785 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3786#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3787 PX86PDPAE pGuestPD = NULL;
3788 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3789 AssertRCReturn(rc, NULL);
3790#else
3791 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3792 if ( !pGuestPD
3793 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3794 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3795#endif
3796 return &pGuestPD->a[iPD];
3797 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3798 }
3799 return NULL;
3800}
3801
3802
3803/**
3804 * Gets the page directory entry for the specified address.
3805 *
3806 * @returns The page directory entry in question.
3807 * @returns A non-present entry if the page directory is not present or on an invalid page.
3808 * @param pPGM Pointer to the PGM instance data.
3809 * @param GCPtr The address.
3810 */
3811DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3812{
3813 AssertGCPtr32(GCPtr);
3814 X86PDEPAE ZeroPde = {0};
3815 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3816 if (RT_LIKELY(pGuestPDPT))
3817 {
3818 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3819 if (pGuestPDPT->a[iPdpt].n.u1Present)
3820 {
3821 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3822#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3823 PX86PDPAE pGuestPD = NULL;
3824 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3825 AssertRCReturn(rc, ZeroPde);
3826#else
3827 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3828 if ( !pGuestPD
3829 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3830 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3831#endif
3832 return pGuestPD->a[iPD];
3833 }
3834 }
3835 return ZeroPde;
3836}
3837
3838
3839/**
3840 * Gets the page directory pointer table entry for the specified address
3841 * and returns the index into the page directory
3842 *
3843 * @returns Pointer to the page directory in question.
3844 * @returns NULL if the page directory is not present or on an invalid page.
3845 * @param pPGM Pointer to the PGM instance data.
3846 * @param GCPtr The address.
3847 * @param piPD Receives the index into the returned page directory
3848 * @param pPdpe Receives the page directory pointer entry. Optional.
3849 */
3850DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3851{
3852 AssertGCPtr32(GCPtr);
3853
3854 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3855 AssertReturn(pGuestPDPT, NULL);
3856 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3857 if (pPdpe)
3858 *pPdpe = pGuestPDPT->a[iPdpt];
3859 if (pGuestPDPT->a[iPdpt].n.u1Present)
3860 {
3861 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3862#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3863 PX86PDPAE pGuestPD = NULL;
3864 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3865 AssertRCReturn(rc, NULL);
3866#else
3867 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3868 if ( !pGuestPD
3869 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3870 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3871#endif
3872 *piPD = iPD;
3873 return pGuestPD;
3874 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3875 }
3876 return NULL;
3877}
3878
3879#ifndef IN_RC
3880
3881/**
3882 * Gets the page map level-4 pointer for the guest.
3883 *
3884 * @returns Pointer to the PML4 page.
3885 * @param pPGM Pointer to the PGM instance data.
3886 */
3887DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3888{
3889#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3890 PX86PML4 pGuestPml4;
3891 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3892 AssertRCReturn(rc, NULL);
3893#else
3894 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3895# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3896 if (!pGuestPml4)
3897 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3898# endif
3899 Assert(pGuestPml4);
3900#endif
3901 return pGuestPml4;
3902}
3903
3904
3905/**
3906 * Gets the pointer to a page map level-4 entry.
3907 *
3908 * @returns Pointer to the PML4 entry.
3909 * @param pPGM Pointer to the PGM instance data.
3910 * @param iPml4 The index.
3911 */
3912DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3913{
3914#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3915 PX86PML4 pGuestPml4;
3916 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3917 AssertRCReturn(rc, NULL);
3918#else
3919 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3920# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3921 if (!pGuestPml4)
3922 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3923# endif
3924 Assert(pGuestPml4);
3925#endif
3926 return &pGuestPml4->a[iPml4];
3927}
3928
3929
3930/**
3931 * Gets a page map level-4 entry.
3932 *
3933 * @returns The PML4 entry.
3934 * @param pPGM Pointer to the PGM instance data.
3935 * @param iPml4 The index.
3936 */
3937DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3938{
3939#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3940 PX86PML4 pGuestPml4;
3941 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3942 if (RT_FAILURE(rc))
3943 {
3944 X86PML4E ZeroPml4e = {0};
3945 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3946 }
3947#else
3948 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3949# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3950 if (!pGuestPml4)
3951 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3952# endif
3953 Assert(pGuestPml4);
3954#endif
3955 return pGuestPml4->a[iPml4];
3956}
3957
3958
3959/**
3960 * Gets the page directory pointer entry for the specified address.
3961 *
3962 * @returns Pointer to the page directory pointer entry in question.
3963 * @returns NULL if the page directory is not present or on an invalid page.
3964 * @param pPGM Pointer to the PGM instance data.
3965 * @param GCPtr The address.
3966 * @param ppPml4e Page Map Level-4 Entry (out)
3967 */
3968DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3969{
3970 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3971 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3972 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3973 if (pPml4e->n.u1Present)
3974 {
3975 PX86PDPT pPdpt;
3976 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3977 AssertRCReturn(rc, NULL);
3978
3979 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3980 return &pPdpt->a[iPdpt];
3981 }
3982 return NULL;
3983}
3984
3985
3986/**
3987 * Gets the page directory entry for the specified address.
3988 *
3989 * @returns The page directory entry in question.
3990 * @returns A non-present entry if the page directory is not present or on an invalid page.
3991 * @param pPGM Pointer to the PGM instance data.
3992 * @param GCPtr The address.
3993 * @param ppPml4e Page Map Level-4 Entry (out)
3994 * @param pPdpe Page directory pointer table entry (out)
3995 */
3996DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3997{
3998 X86PDEPAE ZeroPde = {0};
3999 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4000 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4001 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4002 if (pPml4e->n.u1Present)
4003 {
4004 PCX86PDPT pPdptTemp;
4005 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4006 AssertRCReturn(rc, ZeroPde);
4007
4008 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4009 *pPdpe = pPdptTemp->a[iPdpt];
4010 if (pPdptTemp->a[iPdpt].n.u1Present)
4011 {
4012 PCX86PDPAE pPD;
4013 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4014 AssertRCReturn(rc, ZeroPde);
4015
4016 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4017 return pPD->a[iPD];
4018 }
4019 }
4020
4021 return ZeroPde;
4022}
4023
4024
4025/**
4026 * Gets the page directory entry for the specified address.
4027 *
4028 * @returns The page directory entry in question.
4029 * @returns A non-present entry if the page directory is not present or on an invalid page.
4030 * @param pPGM Pointer to the PGM instance data.
4031 * @param GCPtr The address.
4032 */
4033DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4034{
4035 X86PDEPAE ZeroPde = {0};
4036 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4037 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4038 if (pGuestPml4->a[iPml4].n.u1Present)
4039 {
4040 PCX86PDPT pPdptTemp;
4041 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4042 AssertRCReturn(rc, ZeroPde);
4043
4044 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4045 if (pPdptTemp->a[iPdpt].n.u1Present)
4046 {
4047 PCX86PDPAE pPD;
4048 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4049 AssertRCReturn(rc, ZeroPde);
4050
4051 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4052 return pPD->a[iPD];
4053 }
4054 }
4055 return ZeroPde;
4056}
4057
4058
4059/**
4060 * Gets the page directory entry for the specified address.
4061 *
4062 * @returns Pointer to the page directory entry in question.
4063 * @returns NULL if the page directory is not present or on an invalid page.
4064 * @param pPGM Pointer to the PGM instance data.
4065 * @param GCPtr The address.
4066 */
4067DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4068{
4069 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4070 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4071 if (pGuestPml4->a[iPml4].n.u1Present)
4072 {
4073 PCX86PDPT pPdptTemp;
4074 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4075 AssertRCReturn(rc, NULL);
4076
4077 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4078 if (pPdptTemp->a[iPdpt].n.u1Present)
4079 {
4080 PX86PDPAE pPD;
4081 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4082 AssertRCReturn(rc, NULL);
4083
4084 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4085 return &pPD->a[iPD];
4086 }
4087 }
4088 return NULL;
4089}
4090
4091
4092/**
4093 * Gets the GUEST page directory pointer for the specified address.
4094 *
4095 * @returns The page directory in question.
4096 * @returns NULL if the page directory is not present or on an invalid page.
4097 * @param pPGM Pointer to the PGM instance data.
4098 * @param GCPtr The address.
4099 * @param ppPml4e Page Map Level-4 Entry (out)
4100 * @param pPdpe Page directory pointer table entry (out)
4101 * @param piPD Receives the index into the returned page directory
4102 */
4103DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4104{
4105 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4106 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4107 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4108 if (pPml4e->n.u1Present)
4109 {
4110 PCX86PDPT pPdptTemp;
4111 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4112 AssertRCReturn(rc, NULL);
4113
4114 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4115 *pPdpe = pPdptTemp->a[iPdpt];
4116 if (pPdptTemp->a[iPdpt].n.u1Present)
4117 {
4118 PX86PDPAE pPD;
4119 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4120 AssertRCReturn(rc, NULL);
4121
4122 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4123 return pPD;
4124 }
4125 }
4126 return 0;
4127}
4128
4129#endif /* !IN_RC */
4130
4131/**
4132 * Gets the shadow page directory, 32-bit.
4133 *
4134 * @returns Pointer to the shadow 32-bit PD.
4135 * @param pPGM Pointer to the PGM instance data.
4136 */
4137DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4138{
4139 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4140}
4141
4142
4143/**
4144 * Gets the shadow page directory entry for the specified address, 32-bit.
4145 *
4146 * @returns Shadow 32-bit PDE.
4147 * @param pPGM Pointer to the PGM instance data.
4148 * @param GCPtr The address.
4149 */
4150DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4151{
4152 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4153
4154 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4155 if (!pShwPde)
4156 {
4157 X86PDE ZeroPde = {0};
4158 return ZeroPde;
4159 }
4160 return pShwPde->a[iPd];
4161}
4162
4163
4164/**
4165 * Gets the pointer to the shadow page directory entry for the specified
4166 * address, 32-bit.
4167 *
4168 * @returns Pointer to the shadow 32-bit PDE.
4169 * @param pPGM Pointer to the PGM instance data.
4170 * @param GCPtr The address.
4171 */
4172DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4173{
4174 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4175
4176 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4177 AssertReturn(pPde, NULL);
4178 return &pPde->a[iPd];
4179}
4180
4181
4182/**
4183 * Gets the shadow page pointer table, PAE.
4184 *
4185 * @returns Pointer to the shadow PAE PDPT.
4186 * @param pPGM Pointer to the PGM instance data.
4187 */
4188DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4189{
4190 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4191}
4192
4193
4194/**
4195 * Gets the shadow page directory for the specified address, PAE.
4196 *
4197 * @returns Pointer to the shadow PD.
4198 * @param pPGM Pointer to the PGM instance data.
4199 * @param GCPtr The address.
4200 */
4201DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4202{
4203 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4204 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4205
4206 if (!pPdpt->a[iPdpt].n.u1Present)
4207 return NULL;
4208
4209 /* Fetch the pgm pool shadow descriptor. */
4210 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4211 AssertReturn(pShwPde, NULL);
4212
4213 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4214}
4215
4216
4217/**
4218 * Gets the shadow page directory for the specified address, PAE.
4219 *
4220 * @returns Pointer to the shadow PD.
4221 * @param pPGM Pointer to the PGM instance data.
4222 * @param GCPtr The address.
4223 */
4224DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4225{
4226 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4227
4228 if (!pPdpt->a[iPdpt].n.u1Present)
4229 return NULL;
4230
4231 /* Fetch the pgm pool shadow descriptor. */
4232 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4233 AssertReturn(pShwPde, NULL);
4234
4235 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4236}
4237
4238
4239/**
4240 * Gets the shadow page directory entry, PAE.
4241 *
4242 * @returns PDE.
4243 * @param pPGM Pointer to the PGM instance data.
4244 * @param GCPtr The address.
4245 */
4246DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4247{
4248 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4249
4250 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4251 if (!pShwPde)
4252 {
4253 X86PDEPAE ZeroPde = {0};
4254 return ZeroPde;
4255 }
4256 return pShwPde->a[iPd];
4257}
4258
4259
4260/**
4261 * Gets the pointer to the shadow page directory entry for an address, PAE.
4262 *
4263 * @returns Pointer to the PDE.
4264 * @param pPGM Pointer to the PGM instance data.
4265 * @param GCPtr The address.
4266 */
4267DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4268{
4269 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4270
4271 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4272 AssertReturn(pPde, NULL);
4273 return &pPde->a[iPd];
4274}
4275
4276#ifndef IN_RC
4277
4278/**
4279 * Gets the shadow page map level-4 pointer.
4280 *
4281 * @returns Pointer to the shadow PML4.
4282 * @param pPGM Pointer to the PGM instance data.
4283 */
4284DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4285{
4286 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4287}
4288
4289
4290/**
4291 * Gets the shadow page map level-4 entry for the specified address.
4292 *
4293 * @returns The entry.
4294 * @param pPGM Pointer to the PGM instance data.
4295 * @param GCPtr The address.
4296 */
4297DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4298{
4299 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4300 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4301
4302 if (!pShwPml4)
4303 {
4304 X86PML4E ZeroPml4e = {0};
4305 return ZeroPml4e;
4306 }
4307 return pShwPml4->a[iPml4];
4308}
4309
4310
4311/**
4312 * Gets the pointer to the specified shadow page map level-4 entry.
4313 *
4314 * @returns The entry.
4315 * @param pPGM Pointer to the PGM instance data.
4316 * @param iPml4 The PML4 index.
4317 */
4318DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4319{
4320 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4321 if (!pShwPml4)
4322 return NULL;
4323 return &pShwPml4->a[iPml4];
4324}
4325
4326
4327/**
4328 * Gets the GUEST page directory pointer for the specified address.
4329 *
4330 * @returns The page directory in question.
4331 * @returns NULL if the page directory is not present or on an invalid page.
4332 * @param pPGM Pointer to the PGM instance data.
4333 * @param GCPtr The address.
4334 * @param piPD Receives the index into the returned page directory
4335 */
4336DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4337{
4338 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4339 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4340 if (pGuestPml4->a[iPml4].n.u1Present)
4341 {
4342 PCX86PDPT pPdptTemp;
4343 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4344 AssertRCReturn(rc, NULL);
4345
4346 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4347 if (pPdptTemp->a[iPdpt].n.u1Present)
4348 {
4349 PX86PDPAE pPD;
4350 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4351 AssertRCReturn(rc, NULL);
4352
4353 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4354 return pPD;
4355 }
4356 }
4357 return NULL;
4358}
4359
4360#endif /* !IN_RC */
4361
4362/**
4363 * Gets the page state for a physical handler.
4364 *
4365 * @returns The physical handler page state.
4366 * @param pCur The physical handler in question.
4367 */
4368DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4369{
4370 switch (pCur->enmType)
4371 {
4372 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4373 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4374
4375 case PGMPHYSHANDLERTYPE_MMIO:
4376 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4377 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4378
4379 default:
4380 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4381 }
4382}
4383
4384
4385/**
4386 * Gets the page state for a virtual handler.
4387 *
4388 * @returns The virtual handler page state.
4389 * @param pCur The virtual handler in question.
4390 * @remarks This should never be used on a hypervisor access handler.
4391 */
4392DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4393{
4394 switch (pCur->enmType)
4395 {
4396 case PGMVIRTHANDLERTYPE_WRITE:
4397 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4398 case PGMVIRTHANDLERTYPE_ALL:
4399 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4400 default:
4401 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4402 }
4403}
4404
4405
4406/**
4407 * Clears one physical page of a virtual handler
4408 *
4409 * @param pPGM Pointer to the PGM instance.
4410 * @param pCur Virtual handler structure
4411 * @param iPage Physical page index
4412 *
4413 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4414 * need to care about other handlers in the same page.
4415 */
4416DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4417{
4418 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4419
4420 /*
4421 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4422 */
4423#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4424 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4425 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4426 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4427#endif
4428 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4429 {
4430 /* We're the head of the alias chain. */
4431 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4432#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4433 AssertReleaseMsg(pRemove != NULL,
4434 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4435 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4436 AssertReleaseMsg(pRemove == pPhys2Virt,
4437 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4438 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4439 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4440 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4441#endif
4442 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4443 {
4444 /* Insert the next list in the alias chain into the tree. */
4445 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4446#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4447 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4448 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4449 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4450#endif
4451 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4452 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4453 AssertRelease(fRc);
4454 }
4455 }
4456 else
4457 {
4458 /* Locate the previous node in the alias chain. */
4459 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4460#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4461 AssertReleaseMsg(pPrev != pPhys2Virt,
4462 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4463 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4464#endif
4465 for (;;)
4466 {
4467 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4468 if (pNext == pPhys2Virt)
4469 {
4470 /* unlink. */
4471 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4472 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4473 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4474 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4475 else
4476 {
4477 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4478 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4479 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4480 }
4481 break;
4482 }
4483
4484 /* next */
4485 if (pNext == pPrev)
4486 {
4487#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4488 AssertReleaseMsg(pNext != pPrev,
4489 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4490 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4491#endif
4492 break;
4493 }
4494 pPrev = pNext;
4495 }
4496 }
4497 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4498 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4499 pPhys2Virt->offNextAlias = 0;
4500 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4501
4502 /*
4503 * Clear the ram flags for this page.
4504 */
4505 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4506 AssertReturnVoid(pPage);
4507 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4508}
4509
4510
4511/**
4512 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4513 *
4514 * @returns Pointer to the shadow page structure.
4515 * @param pPool The pool.
4516 * @param idx The pool page index.
4517 */
4518DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4519{
4520 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4521 return &pPool->aPages[idx];
4522}
4523
4524
4525#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4526/**
4527 * Clear references to guest physical memory.
4528 *
4529 * @param pPool The pool.
4530 * @param pPoolPage The pool page.
4531 * @param pPhysPage The physical guest page tracking structure.
4532 */
4533DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4534{
4535 /*
4536 * Just deal with the simple case here.
4537 */
4538# ifdef LOG_ENABLED
4539 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4540# endif
4541 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4542 if (cRefs == 1)
4543 {
4544 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4545 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4546 }
4547 else
4548 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4549 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4550}
4551#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4552
4553
4554#ifdef PGMPOOL_WITH_CACHE
4555/**
4556 * Moves the page to the head of the age list.
4557 *
4558 * This is done when the cached page is used in one way or another.
4559 *
4560 * @param pPool The pool.
4561 * @param pPage The cached page.
4562 */
4563DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4564{
4565 PVM pVM = pPool->CTX_SUFF(pVM);
4566 pgmLock(pVM);
4567
4568 /*
4569 * Move to the head of the age list.
4570 */
4571 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4572 {
4573 /* unlink */
4574 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4575 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4576 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4577 else
4578 pPool->iAgeTail = pPage->iAgePrev;
4579
4580 /* insert at head */
4581 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4582 pPage->iAgeNext = pPool->iAgeHead;
4583 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4584 pPool->iAgeHead = pPage->idx;
4585 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4586 }
4587 pgmUnlock(pVM);
4588}
4589#endif /* PGMPOOL_WITH_CACHE */
4590
4591/**
4592 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4593 *
4594 * @param pVM VM Handle.
4595 * @param pPage PGM pool page
4596 */
4597DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4598{
4599 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4600 ASMAtomicIncU32(&pPage->cLocked);
4601}
4602
4603
4604/**
4605 * Unlocks a page to allow flushing again
4606 *
4607 * @param pVM VM Handle.
4608 * @param pPage PGM pool page
4609 */
4610DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4611{
4612 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4613 Assert(pPage->cLocked);
4614 ASMAtomicDecU32(&pPage->cLocked);
4615}
4616
4617
4618/**
4619 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4620 *
4621 * @returns VBox status code.
4622 * @param pPage PGM pool page
4623 */
4624DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4625{
4626 if (pPage->cLocked)
4627 {
4628 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4629 if (pPage->cModifications)
4630 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4631 return true;
4632 }
4633 return false;
4634}
4635
4636/**
4637 * Tells if mappings are to be put into the shadow page table or not
4638 *
4639 * @returns boolean result
4640 * @param pVM VM handle.
4641 */
4642DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4643{
4644#ifdef IN_RING0
4645 /* There are no mappings in VT-x and AMD-V mode. */
4646 Assert(pPGM->fDisableMappings);
4647 return false;
4648#else
4649 return !pPGM->fDisableMappings;
4650#endif
4651}
4652
4653/** @} */
4654
4655#endif
4656
4657
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