VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 23425

Last change on this file since 23425 was 23415, checked in by vboxsync, 15 years ago

PGM: Saved state hacking and some minor cleanups.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 198.6 KB
Line 
1/* $Id: PGMInternal.h 23415 2009-09-29 15:40:39Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#if 0 /* disabled again while debugging */
72#ifndef IN_RC
73# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
74#endif
75#endif
76
77/**
78 * Sync N pages instead of a whole page table
79 */
80#define PGM_SYNC_N_PAGES
81
82/**
83 * Number of pages to sync during a page fault
84 *
85 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
86 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
87 *
88 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
89 * world switch overhead, so let's sync more.
90 */
91# ifdef IN_RING0
92/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
93 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
94 * but ~5% fewer faults.
95 */
96# define PGM_SYNC_NR_PAGES 32
97#else
98# define PGM_SYNC_NR_PAGES 8
99#endif
100
101/**
102 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
103 */
104#define PGM_MAX_PHYSCACHE_ENTRIES 64
105#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
106
107/** @def PGMPOOL_WITH_CACHE
108 * Enable agressive caching using the page pool.
109 *
110 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
111 */
112#define PGMPOOL_WITH_CACHE
113
114/** @def PGMPOOL_WITH_MIXED_PT_CR3
115 * When defined, we'll deal with 'uncachable' pages.
116 */
117#ifdef PGMPOOL_WITH_CACHE
118# define PGMPOOL_WITH_MIXED_PT_CR3
119#endif
120
121/** @def PGMPOOL_WITH_MONITORING
122 * Monitor the guest pages which are shadowed.
123 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
124 * be enabled as well.
125 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
126 */
127#ifdef PGMPOOL_WITH_CACHE
128# define PGMPOOL_WITH_MONITORING
129#endif
130
131/** @def PGMPOOL_WITH_GCPHYS_TRACKING
132 * Tracking the of shadow pages mapping guest physical pages.
133 *
134 * This is very expensive, the current cache prototype is trying to figure out
135 * whether it will be acceptable with an agressive caching policy.
136 */
137#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
138# define PGMPOOL_WITH_GCPHYS_TRACKING
139#endif
140
141/** @def PGMPOOL_WITH_USER_TRACKING
142 * Tracking users of shadow pages. This is required for the linking of shadow page
143 * tables and physical guest addresses.
144 */
145#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
146# define PGMPOOL_WITH_USER_TRACKING
147#endif
148
149/** @def PGMPOOL_CFG_MAX_GROW
150 * The maximum number of pages to add to the pool in one go.
151 */
152#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
153
154/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
155 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
156 */
157#ifdef VBOX_STRICT
158# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
159#endif
160
161/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
162 * Enables the experimental lazy page allocation code. */
163/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED 6
213#define PGM_TYPE_EPT 7
214#define PGM_TYPE_MAX PGM_TYPE_EPT
215/** @} */
216
217/** Macro for checking if the guest is using paging.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_PAGING(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_32BIT \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227/** Macro for checking if the guest supports the NX bit.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_NX(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_PAE \
234 && (uShwType) != PGM_TYPE_NESTED \
235 && (uShwType) != PGM_TYPE_EPT)
236
237
238/** @def PGM_HCPHYS_2_PTR
239 * Maps a HC physical page pool address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM handle.
243 * @param HCPhys The HC physical address to map to a virtual one.
244 * @param ppv Where to store the virtual address. No need to cast this.
245 *
246 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
247 * small page window employeed by that function. Be careful.
248 * @remark There is no need to assert on the result.
249 */
250#ifdef IN_RC
251# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
252 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
253#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
258 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_HCPHYS_2_PTR_BY_PGM
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pPGM The PGM instance data.
266 * @param HCPhys The HC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
275 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
276#else
277# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
278 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
279#endif
280
281/** @def PGM_GCPHYS_2_PTR
282 * Maps a GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The VM handle.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290 * small page window employeed by that function. Be careful.
291 * @remark There is no need to assert on the result.
292 */
293#ifdef IN_RC
294# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
295 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
296#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
297# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
301 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pPGM Pointer to the PGM instance data.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
317# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
318 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
321 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
322#endif
323
324/** @def PGM_GCPHYS_2_PTR_EX
325 * Maps a unaligned GC physical page address to a virtual address.
326 *
327 * @returns VBox status code.
328 * @param pVM The VM handle.
329 * @param GCPhys The GC physical address to map to a virtual one.
330 * @param ppv Where to store the virtual address. No need to cast this.
331 *
332 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
333 * small page window employeed by that function. Be careful.
334 * @remark There is no need to assert on the result.
335 */
336#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
339#else
340# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
341 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
342#endif
343
344/** @def PGM_INVL_PG
345 * Invalidates a page.
346 *
347 * @param pVCpu The VMCPU handle.
348 * @param GCVirt The virtual address of the page to invalidate.
349 */
350#ifdef IN_RC
351# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
352#elif defined(IN_RING0)
353# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354#else
355# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356#endif
357
358/** @def PGM_INVL_PG_ALL_VCPU
359 * Invalidates a page on all VCPUs
360 *
361 * @param pVM The VM handle.
362 * @param GCVirt The virtual address of the page to invalidate.
363 */
364#ifdef IN_RC
365# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
366#elif defined(IN_RING0)
367# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368#else
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370#endif
371
372/** @def PGM_INVL_BIG_PG
373 * Invalidates a 4MB page directory entry.
374 *
375 * @param pVCpu The VMCPU handle.
376 * @param GCVirt The virtual address within the page directory to invalidate.
377 */
378#ifdef IN_RC
379# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_VCPU_TLBS()
387 * Invalidates the TLBs of the specified VCPU
388 *
389 * @param pVCpu The VMCPU handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_ALL_VCPU_TLBS()
400 * Invalidates the TLBs of all VCPUs
401 *
402 * @param pVM The VM handle.
403 */
404#ifdef IN_RC
405# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408#else
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410#endif
411
412/** Size of the GCPtrConflict array in PGMMAPPING.
413 * @remarks Must be a power of two. */
414#define PGMMAPPING_CONFLICT_MAX 8
415
416/**
417 * Structure for tracking GC Mappings.
418 *
419 * This structure is used by linked list in both GC and HC.
420 */
421typedef struct PGMMAPPING
422{
423 /** Pointer to next entry. */
424 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425 /** Pointer to next entry. */
426 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427 /** Pointer to next entry. */
428 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429 /** Indicate whether this entry is finalized. */
430 bool fFinalized;
431 /** Start Virtual address. */
432 RTGCPTR GCPtr;
433 /** Last Virtual address (inclusive). */
434 RTGCPTR GCPtrLast;
435 /** Range size (bytes). */
436 RTGCPTR cb;
437 /** Pointer to relocation callback function. */
438 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439 /** User argument to the callback. */
440 R3PTRTYPE(void *) pvUser;
441 /** Mapping description / name. For easing debugging. */
442 R3PTRTYPE(const char *) pszDesc;
443 /** Last 8 addresses that caused conflicts. */
444 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445 /** Number of conflicts for this hypervisor mapping. */
446 uint32_t cConflicts;
447 /** Number of page tables. */
448 uint32_t cPTs;
449
450 /** Array of page table mapping data. Each entry
451 * describes one page table. The array can be longer
452 * than the declared length.
453 */
454 struct
455 {
456 /** The HC physical address of the page table. */
457 RTHCPHYS HCPhysPT;
458 /** The HC physical address of the first PAE page table. */
459 RTHCPHYS HCPhysPaePT0;
460 /** The HC physical address of the second PAE page table. */
461 RTHCPHYS HCPhysPaePT1;
462 /** The HC virtual address of the 32-bit page table. */
463 R3PTRTYPE(PX86PT) pPTR3;
464 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466 /** The RC virtual address of the 32-bit page table. */
467 RCPTRTYPE(PX86PT) pPTRC;
468 /** The RC virtual address of the two PAE page table. */
469 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470 /** The R0 virtual address of the 32-bit page table. */
471 R0PTRTYPE(PX86PT) pPTR0;
472 /** The R0 virtual address of the two PAE page table. */
473 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474 } aPTs[1];
475} PGMMAPPING;
476/** Pointer to structure for tracking GC Mappings. */
477typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480/**
481 * Physical page access handler structure.
482 *
483 * This is used to keep track of physical address ranges
484 * which are being monitored in some kind of way.
485 */
486typedef struct PGMPHYSHANDLER
487{
488 AVLROGCPHYSNODECORE Core;
489 /** Access type. */
490 PGMPHYSHANDLERTYPE enmType;
491 /** Number of pages to update. */
492 uint32_t cPages;
493 /** Pointer to R3 callback function. */
494 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495 /** User argument for R3 handlers. */
496 R3PTRTYPE(void *) pvUserR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499 /** User argument for R0 handlers. */
500 R0PTRTYPE(void *) pvUserR0;
501 /** Pointer to RC callback function. */
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503 /** User argument for RC handlers. */
504 RCPTRTYPE(void *) pvUserRC;
505 /** Description / Name. For easing debugging. */
506 R3PTRTYPE(const char *) pszDesc;
507#ifdef VBOX_WITH_STATISTICS
508 /** Profiling of this handler. */
509 STAMPROFILE Stat;
510#endif
511} PGMPHYSHANDLER;
512/** Pointer to a physical page access handler structure. */
513typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516/**
517 * Cache node for the physical addresses covered by a virtual handler.
518 */
519typedef struct PGMPHYS2VIRTHANDLER
520{
521 /** Core node for the tree based on physical ranges. */
522 AVLROGCPHYSNODECORE Core;
523 /** Offset from this struct to the PGMVIRTHANDLER structure. */
524 int32_t offVirtHandler;
525 /** Offset of the next alias relative to this one.
526 * Bit 0 is used for indicating whether we're in the tree.
527 * Bit 1 is used for indicating that we're the head node.
528 */
529 int32_t offNextAlias;
530} PGMPHYS2VIRTHANDLER;
531/** Pointer to a phys to virtual handler structure. */
532typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535 * node is in the tree. */
536#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538 * node is in the head of an alias chain.
539 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545/**
546 * Virtual page access handler structure.
547 *
548 * This is used to keep track of virtual address ranges
549 * which are being monitored in some kind of way.
550 */
551typedef struct PGMVIRTHANDLER
552{
553 /** Core node for the tree based on virtual ranges. */
554 AVLROGCPTRNODECORE Core;
555 /** Size of the range (in bytes). */
556 RTGCPTR cb;
557 /** Number of cache pages. */
558 uint32_t cPages;
559 /** Access type. */
560 PGMVIRTHANDLERTYPE enmType;
561 /** Pointer to the RC callback function. */
562 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563#if HC_ARCH_BITS == 64
564 RTRCPTR padding;
565#endif
566 /** Pointer to the R3 callback function for invalidation. */
567 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568 /** Pointer to the R3 callback function. */
569 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570 /** Description / Name. For easing debugging. */
571 R3PTRTYPE(const char *) pszDesc;
572#ifdef VBOX_WITH_STATISTICS
573 /** Profiling of this handler. */
574 STAMPROFILE Stat;
575#endif
576 /** Array of cached physical addresses for the monitored ranged. */
577 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578} PGMVIRTHANDLER;
579/** Pointer to a virtual page access handler structure. */
580typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583/**
584 * Page type.
585 *
586 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587 * @remarks This is used in the saved state, so changes to it requires bumping
588 * the saved state version.
589 * @todo So, convert to \#defines!
590 */
591typedef enum PGMPAGETYPE
592{
593 /** The usual invalid zero entry. */
594 PGMPAGETYPE_INVALID = 0,
595 /** RAM page. (RWX) */
596 PGMPAGETYPE_RAM,
597 /** MMIO2 page. (RWX) */
598 PGMPAGETYPE_MMIO2,
599 /** MMIO2 page aliased over an MMIO page. (RWX)
600 * See PGMHandlerPhysicalPageAlias(). */
601 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602 /** Shadowed ROM. (RWX) */
603 PGMPAGETYPE_ROM_SHADOW,
604 /** ROM page. (R-X) */
605 PGMPAGETYPE_ROM,
606 /** MMIO page. (---) */
607 PGMPAGETYPE_MMIO,
608 /** End of valid entries. */
609 PGMPAGETYPE_END
610} PGMPAGETYPE;
611AssertCompile(PGMPAGETYPE_END <= 7);
612
613/** @name Page type predicates.
614 * @{ */
615#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620/** @} */
621
622
623/**
624 * A Physical Guest Page tracking structure.
625 *
626 * The format of this structure is complicated because we have to fit a lot
627 * of information into as few bits as possible. The format is also subject
628 * to change (there is one comming up soon). Which means that for we'll be
629 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
630 * accessess to the structure.
631 */
632typedef struct PGMPAGE
633{
634 /** The physical address and a whole lot of other stuff. All bits are used! */
635 RTHCPHYS HCPhysX;
636 /** The page state. */
637 uint32_t u2StateX : 2;
638 /** Flag indicating that a write monitored page was written to when set. */
639 uint32_t fWrittenToX : 1;
640 /** For later. */
641 uint32_t fSomethingElse : 1;
642 /** The Page ID.
643 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
644 * The HCPhysX will then be 100% static. */
645 uint32_t idPageX : 28;
646 /** The page type (PGMPAGETYPE). */
647 uint32_t u3Type : 3;
648 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
649 uint32_t u2HandlerPhysStateX : 2;
650 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
651 uint32_t u2HandlerVirtStateX : 2;
652 uint32_t u29B : 25;
653} PGMPAGE;
654AssertCompileSize(PGMPAGE, 16);
655/** Pointer to a physical guest page. */
656typedef PGMPAGE *PPGMPAGE;
657/** Pointer to a const physical guest page. */
658typedef const PGMPAGE *PCPGMPAGE;
659/** Pointer to a physical guest page pointer. */
660typedef PPGMPAGE *PPPGMPAGE;
661
662
663/**
664 * Clears the page structure.
665 * @param pPage Pointer to the physical guest page tracking structure.
666 */
667#define PGM_PAGE_CLEAR(pPage) \
668 do { \
669 (pPage)->HCPhysX = 0; \
670 (pPage)->u2StateX = 0; \
671 (pPage)->fWrittenToX = 0; \
672 (pPage)->fSomethingElse = 0; \
673 (pPage)->idPageX = 0; \
674 (pPage)->u3Type = 0; \
675 (pPage)->u29B = 0; \
676 } while (0)
677
678/**
679 * Initializes the page structure.
680 * @param pPage Pointer to the physical guest page tracking structure.
681 */
682#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
683 do { \
684 (pPage)->HCPhysX = (_HCPhys); \
685 (pPage)->u2StateX = (_uState); \
686 (pPage)->fWrittenToX = 0; \
687 (pPage)->fSomethingElse = 0; \
688 (pPage)->idPageX = (_idPage); \
689 (pPage)->u3Type = (_uType); \
690 (pPage)->u29B = 0; \
691 } while (0)
692
693/**
694 * Initializes the page structure of a ZERO page.
695 * @param pPage Pointer to the physical guest page tracking structure.
696 */
697#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
698 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
699
700
701/** @name The Page state, PGMPAGE::u2StateX.
702 * @{ */
703/** The zero page.
704 * This is a per-VM page that's never ever mapped writable. */
705#define PGM_PAGE_STATE_ZERO 0
706/** A allocated page.
707 * This is a per-VM page allocated from the page pool (or wherever
708 * we get MMIO2 pages from if the type is MMIO2).
709 */
710#define PGM_PAGE_STATE_ALLOCATED 1
711/** A allocated page that's being monitored for writes.
712 * The shadow page table mappings are read-only. When a write occurs, the
713 * fWrittenTo member is set, the page remapped as read-write and the state
714 * moved back to allocated. */
715#define PGM_PAGE_STATE_WRITE_MONITORED 2
716/** The page is shared, aka. copy-on-write.
717 * This is a page that's shared with other VMs. */
718#define PGM_PAGE_STATE_SHARED 3
719/** @} */
720
721
722/**
723 * Gets the page state.
724 * @returns page state (PGM_PAGE_STATE_*).
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
728
729/**
730 * Sets the page state.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 * @param _uState The new page state.
733 */
734#define PGM_PAGE_SET_STATE(pPage, _uState) \
735 do { (pPage)->u2StateX = (_uState); } while (0)
736
737
738/**
739 * Gets the host physical address of the guest page.
740 * @returns host physical address (RTHCPHYS).
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
744
745/**
746 * Sets the host physical address of the guest page.
747 * @param pPage Pointer to the physical guest page tracking structure.
748 * @param _HCPhys The new host physical address.
749 */
750#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
751 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
752 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
753
754/**
755 * Get the Page ID.
756 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
760/* later:
761#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
762 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
763*/
764/**
765 * Sets the Page ID.
766 * @param pPage Pointer to the physical guest page tracking structure.
767 */
768#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
769/* later:
770#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
771 | ((_idPage) & 0xfff) \
772 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
773*/
774
775/**
776 * Get the Chunk ID.
777 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 */
780#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
781/* later:
782#if GMM_CHUNKID_SHIFT == 12
783# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
784#elif GMM_CHUNKID_SHIFT > 12
785# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
786#elif GMM_CHUNKID_SHIFT < 12
787# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
788 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
789#else
790# error "GMM_CHUNKID_SHIFT isn't defined or something."
791#endif
792*/
793
794/**
795 * Get the index of the page within the allocaiton chunk.
796 * @returns The page index.
797 * @param pPage Pointer to the physical guest page tracking structure.
798 */
799#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
800/* later:
801#if GMM_CHUNKID_SHIFT <= 12
802# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
803#else
804# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
805 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
806#endif
807*/
808
809
810/**
811 * Gets the page type.
812 * @returns The page type.
813 * @param pPage Pointer to the physical guest page tracking structure.
814 */
815#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
816
817/**
818 * Sets the page type.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 * @param _enmType The new page type (PGMPAGETYPE).
821 */
822#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
823 do { (pPage)->u3Type = (_enmType); } while (0)
824
825/**
826 * Checks if the page is marked for MMIO.
827 * @returns true/false.
828 * @param pPage Pointer to the physical guest page tracking structure.
829 */
830#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
831
832/**
833 * Checks if the page is backed by the ZERO page.
834 * @returns true/false.
835 * @param pPage Pointer to the physical guest page tracking structure.
836 */
837#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
838
839/**
840 * Checks if the page is backed by a SHARED page.
841 * @returns true/false.
842 * @param pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
845
846
847/**
848 * Marks the paget as written to (for GMM change monitoring).
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
852
853/**
854 * Clears the written-to indicator.
855 * @param pPage Pointer to the physical guest page tracking structure.
856 */
857#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
858
859/**
860 * Checks if the page was marked as written-to.
861 * @returns true/false.
862 * @param pPage Pointer to the physical guest page tracking structure.
863 */
864#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
865
866
867/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
868 *
869 * @remarks The values are assigned in order of priority, so we can calculate
870 * the correct state for a page with different handlers installed.
871 * @{ */
872/** No handler installed. */
873#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
874/** Monitoring is temporarily disabled. */
875#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
876/** Write access is monitored. */
877#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
878/** All access is monitored. */
879#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
880/** @} */
881
882/**
883 * Gets the physical access handler state of a page.
884 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
885 * @param pPage Pointer to the physical guest page tracking structure.
886 */
887#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
888
889/**
890 * Sets the physical access handler state of a page.
891 * @param pPage Pointer to the physical guest page tracking structure.
892 * @param _uState The new state value.
893 */
894#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
895 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
896
897/**
898 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
899 * @returns true/false
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
903
904/**
905 * Checks if the page has any active physical access handlers.
906 * @returns true/false
907 * @param pPage Pointer to the physical guest page tracking structure.
908 */
909#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
910
911
912/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
913 *
914 * @remarks The values are assigned in order of priority, so we can calculate
915 * the correct state for a page with different handlers installed.
916 * @{ */
917/** No handler installed. */
918#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
919/* 1 is reserved so the lineup is identical with the physical ones. */
920/** Write access is monitored. */
921#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
922/** All access is monitored. */
923#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
924/** @} */
925
926/**
927 * Gets the virtual access handler state of a page.
928 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
929 * @param pPage Pointer to the physical guest page tracking structure.
930 */
931#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
932
933/**
934 * Sets the virtual access handler state of a page.
935 * @param pPage Pointer to the physical guest page tracking structure.
936 * @param _uState The new state value.
937 */
938#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
939 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
940
941/**
942 * Checks if the page has any virtual access handlers.
943 * @returns true/false
944 * @param pPage Pointer to the physical guest page tracking structure.
945 */
946#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
947
948/**
949 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
950 * virtual handlers.
951 * @returns true/false
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
955
956
957
958/**
959 * Checks if the page has any access handlers, including temporarily disabled ones.
960 * @returns true/false
961 * @param pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
964 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
965 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
966
967/**
968 * Checks if the page has any active access handlers.
969 * @returns true/false
970 * @param pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
973 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
974 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
975
976/**
977 * Checks if the page has any active access handlers catching all accesses.
978 * @returns true/false
979 * @param pPage Pointer to the physical guest page tracking structure.
980 */
981#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
982 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
983 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
984
985
986
987
988/** @def PGM_PAGE_GET_TRACKING
989 * Gets the packed shadow page pool tracking data associated with a guest page.
990 * @returns uint16_t containing the data.
991 * @param pPage Pointer to the physical guest page tracking structure.
992 */
993#define PGM_PAGE_GET_TRACKING(pPage) \
994 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
995
996/** @def PGM_PAGE_SET_TRACKING
997 * Sets the packed shadow page pool tracking data associated with a guest page.
998 * @param pPage Pointer to the physical guest page tracking structure.
999 * @param u16TrackingData The tracking data to store.
1000 */
1001#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1002 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
1003
1004/** @def PGM_PAGE_GET_TD_CREFS
1005 * Gets the @a cRefs tracking data member.
1006 * @returns cRefs.
1007 * @param pPage Pointer to the physical guest page tracking structure.
1008 */
1009#define PGM_PAGE_GET_TD_CREFS(pPage) \
1010 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1011
1012#define PGM_PAGE_GET_TD_IDX(pPage) \
1013 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1014
1015/**
1016 * Per page live save tracking data.
1017 */
1018typedef struct PGMLIVESAVEPAGE
1019{
1020 /** The pass number where this page was last saved. */
1021 uint32_t uPassSaved;
1022 /** Number of times it has been dirtied. */
1023 uint32_t cDirtied : 24;
1024 /** Whether it is currently dirty. */
1025 uint32_t fDirty : 1;
1026 /** Is or has been a MMIO/MMIO2 and is not worth saving. */
1027 uint32_t fMmio : 1;
1028 /** Was a ZERO page last time around. */
1029 uint32_t fZero : 1;
1030 /** Was a SHARED page last time around. */
1031 uint32_t fShared : 1;
1032 /** Whether the page is/was write monitored in a previous pass. */
1033 uint32_t fWriteMonitored : 1;
1034 /** Whether the page is/was write monitored earlier in this pass. */
1035 uint32_t fWriteMonitoredJustNow : 1;
1036 /** Bits reserved for future use. */
1037 uint32_t u2Reserved : 2;
1038} PGMLIVESAVEPAGE;
1039AssertCompileSize(PGMLIVESAVEPAGE, 8);
1040/** Pointer to the per page live save tracking data. */
1041typedef PGMLIVESAVEPAGE *PPGMLIVESAVEPAGE;
1042
1043/** The max value of PGMLIVESAVEPAGE::cDirtied. */
1044#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1045
1046
1047/**
1048 * Ram range for GC Phys to HC Phys conversion.
1049 *
1050 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1051 * conversions too, but we'll let MM handle that for now.
1052 *
1053 * This structure is used by linked lists in both GC and HC.
1054 */
1055typedef struct PGMRAMRANGE
1056{
1057 /** Start of the range. Page aligned. */
1058 RTGCPHYS GCPhys;
1059 /** Size of the range. (Page aligned of course). */
1060 RTGCPHYS cb;
1061 /** Pointer to the next RAM range - for R3. */
1062 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1063 /** Pointer to the next RAM range - for R0. */
1064 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1065 /** Pointer to the next RAM range - for RC. */
1066 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1067 /** PGM_RAM_RANGE_FLAGS_* flags. */
1068 uint32_t fFlags;
1069 /** Last address in the range (inclusive). Page aligned (-1). */
1070 RTGCPHYS GCPhysLast;
1071 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1072 R3PTRTYPE(void *) pvR3;
1073 /** Live save per page tracking data. */
1074 R3PTRTYPE(PPGMLIVESAVEPAGE) paLSPages;
1075 /** The range description. */
1076 R3PTRTYPE(const char *) pszDesc;
1077 /** Pointer to self - R0 pointer. */
1078 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1079 /** Pointer to self - RC pointer. */
1080 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1081 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1082 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1083 /** Array of physical guest page tracking structures. */
1084 PGMPAGE aPages[1];
1085} PGMRAMRANGE;
1086/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1087typedef PGMRAMRANGE *PPGMRAMRANGE;
1088
1089/** @name PGMRAMRANGE::fFlags
1090 * @{ */
1091/** The RAM range is floating around as an independent guest mapping. */
1092#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1093/** Ad hoc RAM range for an ROM mapping. */
1094#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1095/** Ad hoc RAM range for an MMIO mapping. */
1096#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1097/** Ad hoc RAM range for an MMIO2 mapping. */
1098#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1099/** @} */
1100
1101/** Tests if a RAM range is an ad hoc one or not.
1102 * @returns true/false.
1103 * @param pRam The RAM range.
1104 */
1105#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1106 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1107
1108
1109/**
1110 * Per page tracking structure for ROM image.
1111 *
1112 * A ROM image may have a shadow page, in which case we may have two pages
1113 * backing it. This structure contains the PGMPAGE for both while
1114 * PGMRAMRANGE have a copy of the active one. It is important that these
1115 * aren't out of sync in any regard other than page pool tracking data.
1116 */
1117typedef struct PGMROMPAGE
1118{
1119 /** The page structure for the virgin ROM page. */
1120 PGMPAGE Virgin;
1121 /** The page structure for the shadow RAM page. */
1122 PGMPAGE Shadow;
1123 /** The current protection setting. */
1124 PGMROMPROT enmProt;
1125 /** Live save status information. Makes use of unused alignment space. */
1126 struct
1127 {
1128 /** The previous protection value. */
1129 uint8_t u8Prot;
1130 /** Whether we've saved the virgin page already. */
1131 bool fSavedVirgin;
1132 /** Written to flag set by the handler. */
1133 bool fWrittenTo;
1134 /** Whether we're positively done, i.e. the ROM cannot be shadowed. */
1135 bool fDone;
1136 } LiveSave;
1137} PGMROMPAGE;
1138AssertCompileSizeAlignment(PGMROMPAGE, 8);
1139/** Pointer to a ROM page tracking structure. */
1140typedef PGMROMPAGE *PPGMROMPAGE;
1141
1142
1143/**
1144 * A registered ROM image.
1145 *
1146 * This is needed to keep track of ROM image since they generally intrude
1147 * into a PGMRAMRANGE. It also keeps track of additional info like the
1148 * two page sets (read-only virgin and read-write shadow), the current
1149 * state of each page.
1150 *
1151 * Because access handlers cannot easily be executed in a different
1152 * context, the ROM ranges needs to be accessible and in all contexts.
1153 */
1154typedef struct PGMROMRANGE
1155{
1156 /** Pointer to the next range - R3. */
1157 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1158 /** Pointer to the next range - R0. */
1159 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1160 /** Pointer to the next range - RC. */
1161 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1162 /** Pointer alignment */
1163 RTRCPTR GCPtrAlignment;
1164 /** Address of the range. */
1165 RTGCPHYS GCPhys;
1166 /** Address of the last byte in the range. */
1167 RTGCPHYS GCPhysLast;
1168 /** Size of the range. */
1169 RTGCPHYS cb;
1170 /** The flags (PGMPHYS_ROM_FLAG_*). */
1171 uint32_t fFlags;
1172 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1173 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1174 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1175 * This is used for strictness checks. */
1176 R3PTRTYPE(const void *) pvOriginal;
1177 /** The ROM description. */
1178 R3PTRTYPE(const char *) pszDesc;
1179 /** The per page tracking structures. */
1180 PGMROMPAGE aPages[1];
1181} PGMROMRANGE;
1182/** Pointer to a ROM range. */
1183typedef PGMROMRANGE *PPGMROMRANGE;
1184
1185
1186/**
1187 * A registered MMIO2 (= Device RAM) range.
1188 *
1189 * There are a few reason why we need to keep track of these
1190 * registrations. One of them is the deregistration & cleanup stuff,
1191 * while another is that the PGMRAMRANGE associated with such a region may
1192 * have to be removed from the ram range list.
1193 *
1194 * Overlapping with a RAM range has to be 100% or none at all. The pages
1195 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1196 * will be raised if a partial overlap or an overlap of ROM pages is
1197 * encountered. On an overlap we will free all the existing RAM pages and
1198 * put in the ram range pages instead.
1199 */
1200typedef struct PGMMMIO2RANGE
1201{
1202 /** The owner of the range. (a device) */
1203 PPDMDEVINSR3 pDevInsR3;
1204 /** Pointer to the ring-3 mapping of the allocation. */
1205 RTR3PTR pvR3;
1206 /** Pointer to the next range - R3. */
1207 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1208 /** Whether it's mapped or not. */
1209 bool fMapped;
1210 /** Whether it's overlapping or not. */
1211 bool fOverlapping;
1212 /** The PCI region number.
1213 * @remarks This ASSUMES that nobody will ever really need to have multiple
1214 * PCI devices with matching MMIO region numbers on a single device. */
1215 uint8_t iRegion;
1216 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1217 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1218 /** The associated RAM range. */
1219 PGMRAMRANGE RamRange;
1220} PGMMMIO2RANGE;
1221/** Pointer to a MMIO2 range. */
1222typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1223
1224
1225
1226
1227/**
1228 * PGMPhysRead/Write cache entry
1229 */
1230typedef struct PGMPHYSCACHEENTRY
1231{
1232 /** R3 pointer to physical page. */
1233 R3PTRTYPE(uint8_t *) pbR3;
1234 /** GC Physical address for cache entry */
1235 RTGCPHYS GCPhys;
1236#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1237 RTGCPHYS u32Padding0; /**< alignment padding. */
1238#endif
1239} PGMPHYSCACHEENTRY;
1240
1241/**
1242 * PGMPhysRead/Write cache to reduce REM memory access overhead
1243 */
1244typedef struct PGMPHYSCACHE
1245{
1246 /** Bitmap of valid cache entries */
1247 uint64_t aEntries;
1248 /** Cache entries */
1249 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1250} PGMPHYSCACHE;
1251
1252
1253/** Pointer to an allocation chunk ring-3 mapping. */
1254typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1255/** Pointer to an allocation chunk ring-3 mapping pointer. */
1256typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1257
1258/**
1259 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1260 *
1261 * The primary tree (Core) uses the chunk id as key.
1262 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1263 */
1264typedef struct PGMCHUNKR3MAP
1265{
1266 /** The key is the chunk id. */
1267 AVLU32NODECORE Core;
1268 /** The key is the ageing sequence number. */
1269 AVLLU32NODECORE AgeCore;
1270 /** The current age thingy. */
1271 uint32_t iAge;
1272 /** The current reference count. */
1273 uint32_t volatile cRefs;
1274 /** The current permanent reference count. */
1275 uint32_t volatile cPermRefs;
1276 /** The mapping address. */
1277 void *pv;
1278} PGMCHUNKR3MAP;
1279
1280/**
1281 * Allocation chunk ring-3 mapping TLB entry.
1282 */
1283typedef struct PGMCHUNKR3MAPTLBE
1284{
1285 /** The chunk id. */
1286 uint32_t volatile idChunk;
1287#if HC_ARCH_BITS == 64
1288 uint32_t u32Padding; /**< alignment padding. */
1289#endif
1290 /** The chunk map. */
1291#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1292 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1293#else
1294 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1295#endif
1296} PGMCHUNKR3MAPTLBE;
1297/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1298typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1299
1300/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1301 * @remark Must be a power of two value. */
1302#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1303
1304/**
1305 * Allocation chunk ring-3 mapping TLB.
1306 *
1307 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1308 * At first glance this might look kinda odd since AVL trees are
1309 * supposed to give the most optimial lookup times of all trees
1310 * due to their balancing. However, take a tree with 1023 nodes
1311 * in it, that's 10 levels, meaning that most searches has to go
1312 * down 9 levels before they find what they want. This isn't fast
1313 * compared to a TLB hit. There is the factor of cache misses,
1314 * and of course the problem with trees and branch prediction.
1315 * This is why we use TLBs in front of most of the trees.
1316 *
1317 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1318 * difficult when we switch to the new inlined AVL trees (from kStuff).
1319 */
1320typedef struct PGMCHUNKR3MAPTLB
1321{
1322 /** The TLB entries. */
1323 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1324} PGMCHUNKR3MAPTLB;
1325
1326/**
1327 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1328 * @returns Chunk TLB index.
1329 * @param idChunk The Chunk ID.
1330 */
1331#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1332
1333
1334/**
1335 * Ring-3 guest page mapping TLB entry.
1336 * @remarks used in ring-0 as well at the moment.
1337 */
1338typedef struct PGMPAGER3MAPTLBE
1339{
1340 /** Address of the page. */
1341 RTGCPHYS volatile GCPhys;
1342 /** The guest page. */
1343#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1344 R3PTRTYPE(PPGMPAGE) volatile pPage;
1345#else
1346 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1347#endif
1348 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1349#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1350 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1351#else
1352 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1353#endif
1354 /** The address */
1355#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1356 R3PTRTYPE(void *) volatile pv;
1357#else
1358 R3R0PTRTYPE(void *) volatile pv;
1359#endif
1360#if HC_ARCH_BITS == 32
1361 uint32_t u32Padding; /**< alignment padding. */
1362#endif
1363} PGMPAGER3MAPTLBE;
1364/** Pointer to an entry in the HC physical TLB. */
1365typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1366
1367
1368/** The number of entries in the ring-3 guest page mapping TLB.
1369 * @remarks The value must be a power of two. */
1370#define PGM_PAGER3MAPTLB_ENTRIES 64
1371
1372/**
1373 * Ring-3 guest page mapping TLB.
1374 * @remarks used in ring-0 as well at the moment.
1375 */
1376typedef struct PGMPAGER3MAPTLB
1377{
1378 /** The TLB entries. */
1379 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1380} PGMPAGER3MAPTLB;
1381/** Pointer to the ring-3 guest page mapping TLB. */
1382typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1383
1384/**
1385 * Calculates the index of the TLB entry for the specified guest page.
1386 * @returns Physical TLB index.
1387 * @param GCPhys The guest physical address.
1388 */
1389#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1390
1391
1392/**
1393 * Mapping cache usage set entry.
1394 *
1395 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1396 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1397 * cache. If it's extended to include ring-3, well, then something will
1398 * have be changed here...
1399 */
1400typedef struct PGMMAPSETENTRY
1401{
1402 /** The mapping cache index. */
1403 uint16_t iPage;
1404 /** The number of references.
1405 * The max is UINT16_MAX - 1. */
1406 uint16_t cRefs;
1407#if HC_ARCH_BITS == 64
1408 uint32_t alignment;
1409#endif
1410 /** Pointer to the page. */
1411 RTR0PTR pvPage;
1412 /** The physical address for this entry. */
1413 RTHCPHYS HCPhys;
1414} PGMMAPSETENTRY;
1415/** Pointer to a mapping cache usage set entry. */
1416typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1417
1418/**
1419 * Mapping cache usage set.
1420 *
1421 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1422 * done during exits / traps. The set is
1423 */
1424typedef struct PGMMAPSET
1425{
1426 /** The number of occupied entries.
1427 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1428 * dynamic mappings. */
1429 uint32_t cEntries;
1430 /** The start of the current subset.
1431 * This is UINT32_MAX if no subset is currently open. */
1432 uint32_t iSubset;
1433 /** The index of the current CPU, only valid if the set is open. */
1434 int32_t iCpu;
1435#if HC_ARCH_BITS == 64
1436 uint32_t alignment;
1437#endif
1438 /** The entries. */
1439 PGMMAPSETENTRY aEntries[64];
1440 /** HCPhys -> iEntry fast lookup table.
1441 * Use PGMMAPSET_HASH for hashing.
1442 * The entries may or may not be valid, check against cEntries. */
1443 uint8_t aiHashTable[128];
1444} PGMMAPSET;
1445/** Pointer to the mapping cache set. */
1446typedef PGMMAPSET *PPGMMAPSET;
1447
1448/** PGMMAPSET::cEntries value for a closed set. */
1449#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1450
1451/** Hash function for aiHashTable. */
1452#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1453
1454/** The max fill size (strict builds). */
1455#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1456
1457
1458/** @name Context neutrual page mapper TLB.
1459 *
1460 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1461 * code is writting in a kind of context neutrual way. Time will show whether
1462 * this actually makes sense or not...
1463 *
1464 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1465 * context ends up using a global mapping cache on some platforms
1466 * (darwin).
1467 *
1468 * @{ */
1469/** @typedef PPGMPAGEMAPTLB
1470 * The page mapper TLB pointer type for the current context. */
1471/** @typedef PPGMPAGEMAPTLB
1472 * The page mapper TLB entry pointer type for the current context. */
1473/** @typedef PPGMPAGEMAPTLB
1474 * The page mapper TLB entry pointer pointer type for the current context. */
1475/** @def PGM_PAGEMAPTLB_ENTRIES
1476 * The number of TLB entries in the page mapper TLB for the current context. */
1477/** @def PGM_PAGEMAPTLB_IDX
1478 * Calculate the TLB index for a guest physical address.
1479 * @returns The TLB index.
1480 * @param GCPhys The guest physical address. */
1481/** @typedef PPGMPAGEMAP
1482 * Pointer to a page mapper unit for current context. */
1483/** @typedef PPPGMPAGEMAP
1484 * Pointer to a page mapper unit pointer for current context. */
1485#ifdef IN_RC
1486// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1487// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1488// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1489# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1490# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1491 typedef void * PPGMPAGEMAP;
1492 typedef void ** PPPGMPAGEMAP;
1493//#elif IN_RING0
1494// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1495// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1496// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1497//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1498//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1499// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1500// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1501#else
1502 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1503 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1504 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1505# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1506# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1507 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1508 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1509#endif
1510/** @} */
1511
1512
1513/** @name PGM Pool Indexes.
1514 * Aka. the unique shadow page identifier.
1515 * @{ */
1516/** NIL page pool IDX. */
1517#define NIL_PGMPOOL_IDX 0
1518/** The first normal index. */
1519#define PGMPOOL_IDX_FIRST_SPECIAL 1
1520/** Page directory (32-bit root). */
1521#define PGMPOOL_IDX_PD 1
1522/** Page Directory Pointer Table (PAE root). */
1523#define PGMPOOL_IDX_PDPT 2
1524/** AMD64 CR3 level index.*/
1525#define PGMPOOL_IDX_AMD64_CR3 3
1526/** Nested paging root.*/
1527#define PGMPOOL_IDX_NESTED_ROOT 4
1528/** The first normal index. */
1529#define PGMPOOL_IDX_FIRST 5
1530/** The last valid index. (inclusive, 14 bits) */
1531#define PGMPOOL_IDX_LAST 0x3fff
1532/** @} */
1533
1534/** The NIL index for the parent chain. */
1535#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1536#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1537
1538/**
1539 * Node in the chain linking a shadowed page to it's parent (user).
1540 */
1541#pragma pack(1)
1542typedef struct PGMPOOLUSER
1543{
1544 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1545 uint16_t iNext;
1546 /** The user page index. */
1547 uint16_t iUser;
1548 /** Index into the user table. */
1549 uint32_t iUserTable;
1550} PGMPOOLUSER, *PPGMPOOLUSER;
1551typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1552#pragma pack()
1553
1554
1555/** The NIL index for the phys ext chain. */
1556#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1557
1558/**
1559 * Node in the chain of physical cross reference extents.
1560 * @todo Calling this an 'extent' is not quite right, find a better name.
1561 */
1562#pragma pack(1)
1563typedef struct PGMPOOLPHYSEXT
1564{
1565 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1566 uint16_t iNext;
1567 /** The user page index. */
1568 uint16_t aidx[3];
1569} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1570typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1571#pragma pack()
1572
1573
1574/**
1575 * The kind of page that's being shadowed.
1576 */
1577typedef enum PGMPOOLKIND
1578{
1579 /** The virtual invalid 0 entry. */
1580 PGMPOOLKIND_INVALID = 0,
1581 /** The entry is free (=unused). */
1582 PGMPOOLKIND_FREE,
1583
1584 /** Shw: 32-bit page table; Gst: no paging */
1585 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1586 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1587 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1588 /** Shw: 32-bit page table; Gst: 4MB page. */
1589 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1590 /** Shw: PAE page table; Gst: no paging */
1591 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1592 /** Shw: PAE page table; Gst: 32-bit page table. */
1593 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1594 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1595 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1596 /** Shw: PAE page table; Gst: PAE page table. */
1597 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1598 /** Shw: PAE page table; Gst: 2MB page. */
1599 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1600
1601 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1602 PGMPOOLKIND_32BIT_PD,
1603 /** Shw: 32-bit page directory. Gst: no paging. */
1604 PGMPOOLKIND_32BIT_PD_PHYS,
1605 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1606 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1607 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1608 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1609 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1610 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1611 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1612 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1613 /** Shw: PAE page directory; Gst: PAE page directory. */
1614 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1615 /** Shw: PAE page directory; Gst: no paging. */
1616 PGMPOOLKIND_PAE_PD_PHYS,
1617
1618 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1619 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1620 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1621 PGMPOOLKIND_PAE_PDPT,
1622 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1623 PGMPOOLKIND_PAE_PDPT_PHYS,
1624
1625 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1626 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1627 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1628 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1629 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1630 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1631 /** Shw: 64-bit page directory table; Gst: no paging */
1632 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1633
1634 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1635 PGMPOOLKIND_64BIT_PML4,
1636
1637 /** Shw: EPT page directory pointer table; Gst: no paging */
1638 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1639 /** Shw: EPT page directory table; Gst: no paging */
1640 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1641 /** Shw: EPT page table; Gst: no paging */
1642 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1643
1644 /** Shw: Root Nested paging table. */
1645 PGMPOOLKIND_ROOT_NESTED,
1646
1647 /** The last valid entry. */
1648 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1649} PGMPOOLKIND;
1650
1651/**
1652 * The access attributes of the page; only applies to big pages.
1653 */
1654typedef enum
1655{
1656 PGMPOOLACCESS_DONTCARE = 0,
1657 PGMPOOLACCESS_USER_RW,
1658 PGMPOOLACCESS_USER_R,
1659 PGMPOOLACCESS_USER_RW_NX,
1660 PGMPOOLACCESS_USER_R_NX,
1661 PGMPOOLACCESS_SUPERVISOR_RW,
1662 PGMPOOLACCESS_SUPERVISOR_R,
1663 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1664 PGMPOOLACCESS_SUPERVISOR_R_NX
1665} PGMPOOLACCESS;
1666
1667/**
1668 * The tracking data for a page in the pool.
1669 */
1670typedef struct PGMPOOLPAGE
1671{
1672 /** AVL node code with the (R3) physical address of this page. */
1673 AVLOHCPHYSNODECORE Core;
1674 /** Pointer to the R3 mapping of the page. */
1675#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1676 R3PTRTYPE(void *) pvPageR3;
1677#else
1678 R3R0PTRTYPE(void *) pvPageR3;
1679#endif
1680 /** The guest physical address. */
1681#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1682 uint32_t Alignment0;
1683#endif
1684 RTGCPHYS GCPhys;
1685
1686 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1687 RTGCPTR pvLastAccessHandlerRip;
1688 RTGCPTR pvLastAccessHandlerFault;
1689 uint64_t cLastAccessHandlerCount;
1690
1691 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1692 uint8_t enmKind;
1693 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1694 uint8_t enmAccess;
1695 /** The index of this page. */
1696 uint16_t idx;
1697 /** The next entry in the list this page currently resides in.
1698 * It's either in the free list or in the GCPhys hash. */
1699 uint16_t iNext;
1700#ifdef PGMPOOL_WITH_USER_TRACKING
1701 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1702 uint16_t iUserHead;
1703 /** The number of present entries. */
1704 uint16_t cPresent;
1705 /** The first entry in the table which is present. */
1706 uint16_t iFirstPresent;
1707#endif
1708#ifdef PGMPOOL_WITH_MONITORING
1709 /** The number of modifications to the monitored page. */
1710 uint16_t cModifications;
1711 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1712 uint16_t iModifiedNext;
1713 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1714 uint16_t iModifiedPrev;
1715 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1716 uint16_t iMonitoredNext;
1717 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1718 uint16_t iMonitoredPrev;
1719#endif
1720#ifdef PGMPOOL_WITH_CACHE
1721 /** The next page in the age list. */
1722 uint16_t iAgeNext;
1723 /** The previous page in the age list. */
1724 uint16_t iAgePrev;
1725#endif /* PGMPOOL_WITH_CACHE */
1726 /** Used to indicate that the page is zeroed. */
1727 bool fZeroed;
1728 /** Used to indicate that a PT has non-global entries. */
1729 bool fSeenNonGlobal;
1730 /** Used to indicate that we're monitoring writes to the guest page. */
1731 bool fMonitored;
1732 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1733 * (All pages are in the age list.) */
1734 bool fCached;
1735 /** This is used by the R3 access handlers when invoked by an async thread.
1736 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1737 bool volatile fReusedFlushPending;
1738 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1739 bool fDirty;
1740
1741 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1742 uint32_t cLocked;
1743 uint32_t idxDirty;
1744 RTGCPTR pvDirtyFault;
1745} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1746/** Pointer to a const pool page. */
1747typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1748
1749
1750#ifdef PGMPOOL_WITH_CACHE
1751/** The hash table size. */
1752# define PGMPOOL_HASH_SIZE 0x40
1753/** The hash function. */
1754# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1755#endif
1756
1757
1758/**
1759 * The shadow page pool instance data.
1760 *
1761 * It's all one big allocation made at init time, except for the
1762 * pages that is. The user nodes follows immediatly after the
1763 * page structures.
1764 */
1765typedef struct PGMPOOL
1766{
1767 /** The VM handle - R3 Ptr. */
1768 PVMR3 pVMR3;
1769 /** The VM handle - R0 Ptr. */
1770 PVMR0 pVMR0;
1771 /** The VM handle - RC Ptr. */
1772 PVMRC pVMRC;
1773 /** The max pool size. This includes the special IDs. */
1774 uint16_t cMaxPages;
1775 /** The current pool size. */
1776 uint16_t cCurPages;
1777 /** The head of the free page list. */
1778 uint16_t iFreeHead;
1779 /* Padding. */
1780 uint16_t u16Padding;
1781#ifdef PGMPOOL_WITH_USER_TRACKING
1782 /** Head of the chain of free user nodes. */
1783 uint16_t iUserFreeHead;
1784 /** The number of user nodes we've allocated. */
1785 uint16_t cMaxUsers;
1786 /** The number of present page table entries in the entire pool. */
1787 uint32_t cPresent;
1788 /** Pointer to the array of user nodes - RC pointer. */
1789 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1790 /** Pointer to the array of user nodes - R3 pointer. */
1791 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1792 /** Pointer to the array of user nodes - R0 pointer. */
1793 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1794#endif /* PGMPOOL_WITH_USER_TRACKING */
1795#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1796 /** Head of the chain of free phys ext nodes. */
1797 uint16_t iPhysExtFreeHead;
1798 /** The number of user nodes we've allocated. */
1799 uint16_t cMaxPhysExts;
1800 /** Pointer to the array of physical xref extent - RC pointer. */
1801 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1802 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1803 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1804 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1805 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1806#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1807#ifdef PGMPOOL_WITH_CACHE
1808 /** Hash table for GCPhys addresses. */
1809 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1810 /** The head of the age list. */
1811 uint16_t iAgeHead;
1812 /** The tail of the age list. */
1813 uint16_t iAgeTail;
1814 /** Set if the cache is enabled. */
1815 bool fCacheEnabled;
1816 /** Alignment padding. */
1817 bool afPadding1[3];
1818#endif /* PGMPOOL_WITH_CACHE */
1819#ifdef PGMPOOL_WITH_MONITORING
1820 /** Head of the list of modified pages. */
1821 uint16_t iModifiedHead;
1822 /** The current number of modified pages. */
1823 uint16_t cModifiedPages;
1824 /** Access handler, RC. */
1825 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1826 /** Access handler, R0. */
1827 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1828 /** Access handler, R3. */
1829 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1830 /** The access handler description (R3 ptr). */
1831 R3PTRTYPE(const char *) pszAccessHandler;
1832# if HC_ARCH_BITS == 32
1833 /** Alignment padding. */
1834 uint32_t u32Padding2;
1835# endif
1836 /* Next available slot. */
1837 uint32_t idxFreeDirtyPage;
1838 /* Number of active dirty pages. */
1839 uint32_t cDirtyPages;
1840 /* Array of current dirty pgm pool page indices. */
1841 uint16_t aIdxDirtyPages[16];
1842 uint64_t aDirtyPages[16][512];
1843#endif /* PGMPOOL_WITH_MONITORING */
1844 /** The number of pages currently in use. */
1845 uint16_t cUsedPages;
1846#ifdef VBOX_WITH_STATISTICS
1847 /** The high water mark for cUsedPages. */
1848 uint16_t cUsedPagesHigh;
1849 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1850 /** Profiling pgmPoolAlloc(). */
1851 STAMPROFILEADV StatAlloc;
1852 /** Profiling pgmR3PoolClearDoIt(). */
1853 STAMPROFILE StatClearAll;
1854 /** Profiling pgmR3PoolReset(). */
1855 STAMPROFILE StatR3Reset;
1856 /** Profiling pgmPoolFlushPage(). */
1857 STAMPROFILE StatFlushPage;
1858 /** Profiling pgmPoolFree(). */
1859 STAMPROFILE StatFree;
1860 /** Counting explicit flushes by PGMPoolFlushPage(). */
1861 STAMCOUNTER StatForceFlushPage;
1862 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1863 STAMCOUNTER StatForceFlushDirtyPage;
1864 /** Counting flushes for reused pages. */
1865 STAMCOUNTER StatForceFlushReused;
1866 /** Profiling time spent zeroing pages. */
1867 STAMPROFILE StatZeroPage;
1868# ifdef PGMPOOL_WITH_USER_TRACKING
1869 /** Profiling of pgmPoolTrackDeref. */
1870 STAMPROFILE StatTrackDeref;
1871 /** Profiling pgmTrackFlushGCPhysPT. */
1872 STAMPROFILE StatTrackFlushGCPhysPT;
1873 /** Profiling pgmTrackFlushGCPhysPTs. */
1874 STAMPROFILE StatTrackFlushGCPhysPTs;
1875 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1876 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1877 /** Number of times we've been out of user records. */
1878 STAMCOUNTER StatTrackFreeUpOneUser;
1879 /** Nr of flushed entries. */
1880 STAMCOUNTER StatTrackFlushEntry;
1881 /** Nr of updated entries. */
1882 STAMCOUNTER StatTrackFlushEntryKeep;
1883# endif
1884# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1885 /** Profiling deref activity related tracking GC physical pages. */
1886 STAMPROFILE StatTrackDerefGCPhys;
1887 /** Number of linear searches for a HCPhys in the ram ranges. */
1888 STAMCOUNTER StatTrackLinearRamSearches;
1889 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1890 STAMCOUNTER StamTrackPhysExtAllocFailures;
1891# endif
1892# ifdef PGMPOOL_WITH_MONITORING
1893 /** Profiling the RC/R0 access handler. */
1894 STAMPROFILE StatMonitorRZ;
1895 /** Times we've failed interpreting the instruction. */
1896 STAMCOUNTER StatMonitorRZEmulateInstr;
1897 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1898 STAMPROFILE StatMonitorRZFlushPage;
1899 /* Times we've detected a page table reinit. */
1900 STAMCOUNTER StatMonitorRZFlushReinit;
1901 /** Counting flushes for pages that are modified too often. */
1902 STAMCOUNTER StatMonitorRZFlushModOverflow;
1903 /** Times we've detected fork(). */
1904 STAMCOUNTER StatMonitorRZFork;
1905 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1906 STAMPROFILE StatMonitorRZHandled;
1907 /** Times we've failed interpreting a patch code instruction. */
1908 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1909 /** Times we've failed interpreting a patch code instruction during flushing. */
1910 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1911 /** The number of times we've seen rep prefixes we can't handle. */
1912 STAMCOUNTER StatMonitorRZRepPrefix;
1913 /** Profiling the REP STOSD cases we've handled. */
1914 STAMPROFILE StatMonitorRZRepStosd;
1915 /** Nr of handled PT faults. */
1916 STAMCOUNTER StatMonitorRZFaultPT;
1917 /** Nr of handled PD faults. */
1918 STAMCOUNTER StatMonitorRZFaultPD;
1919 /** Nr of handled PDPT faults. */
1920 STAMCOUNTER StatMonitorRZFaultPDPT;
1921 /** Nr of handled PML4 faults. */
1922 STAMCOUNTER StatMonitorRZFaultPML4;
1923
1924 /** Profiling the R3 access handler. */
1925 STAMPROFILE StatMonitorR3;
1926 /** Times we've failed interpreting the instruction. */
1927 STAMCOUNTER StatMonitorR3EmulateInstr;
1928 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1929 STAMPROFILE StatMonitorR3FlushPage;
1930 /* Times we've detected a page table reinit. */
1931 STAMCOUNTER StatMonitorR3FlushReinit;
1932 /** Counting flushes for pages that are modified too often. */
1933 STAMCOUNTER StatMonitorR3FlushModOverflow;
1934 /** Times we've detected fork(). */
1935 STAMCOUNTER StatMonitorR3Fork;
1936 /** Profiling the R3 access we've handled (except REP STOSD). */
1937 STAMPROFILE StatMonitorR3Handled;
1938 /** The number of times we've seen rep prefixes we can't handle. */
1939 STAMCOUNTER StatMonitorR3RepPrefix;
1940 /** Profiling the REP STOSD cases we've handled. */
1941 STAMPROFILE StatMonitorR3RepStosd;
1942 /** Nr of handled PT faults. */
1943 STAMCOUNTER StatMonitorR3FaultPT;
1944 /** Nr of handled PD faults. */
1945 STAMCOUNTER StatMonitorR3FaultPD;
1946 /** Nr of handled PDPT faults. */
1947 STAMCOUNTER StatMonitorR3FaultPDPT;
1948 /** Nr of handled PML4 faults. */
1949 STAMCOUNTER StatMonitorR3FaultPML4;
1950 /** The number of times we're called in an async thread an need to flush. */
1951 STAMCOUNTER StatMonitorR3Async;
1952 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
1953 STAMCOUNTER StatResetDirtyPages;
1954 /** Times we've called pgmPoolAddDirtyPage. */
1955 STAMCOUNTER StatDirtyPage;
1956 /** Times we've had to flush duplicates for dirty page management. */
1957 STAMCOUNTER StatDirtyPageDupFlush;
1958 /** Times we've had to flush because of overflow. */
1959 STAMCOUNTER StatDirtyPageOverFlowFlush;
1960
1961 /** The high wather mark for cModifiedPages. */
1962 uint16_t cModifiedPagesHigh;
1963 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1964# endif
1965# ifdef PGMPOOL_WITH_CACHE
1966 /** The number of cache hits. */
1967 STAMCOUNTER StatCacheHits;
1968 /** The number of cache misses. */
1969 STAMCOUNTER StatCacheMisses;
1970 /** The number of times we've got a conflict of 'kind' in the cache. */
1971 STAMCOUNTER StatCacheKindMismatches;
1972 /** Number of times we've been out of pages. */
1973 STAMCOUNTER StatCacheFreeUpOne;
1974 /** The number of cacheable allocations. */
1975 STAMCOUNTER StatCacheCacheable;
1976 /** The number of uncacheable allocations. */
1977 STAMCOUNTER StatCacheUncacheable;
1978# endif
1979#else
1980 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1981#endif
1982 /** The AVL tree for looking up a page by its HC physical address. */
1983 AVLOHCPHYSTREE HCPhysTree;
1984 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1985 /** Array of pages. (cMaxPages in length)
1986 * The Id is the index into thist array.
1987 */
1988 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1989} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1990#ifdef PGMPOOL_WITH_MONITORING
1991AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
1992AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
1993#endif
1994AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
1995#ifdef VBOX_WITH_STATISTICS
1996AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
1997#endif
1998AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
1999
2000
2001/** @def PGMPOOL_PAGE_2_PTR
2002 * Maps a pool page pool into the current context.
2003 *
2004 * @returns VBox status code.
2005 * @param pVM The VM handle.
2006 * @param pPage The pool page.
2007 *
2008 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2009 * small page window employeed by that function. Be careful.
2010 * @remark There is no need to assert on the result.
2011 */
2012#if defined(IN_RC)
2013# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2014#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2015# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2016#elif defined(VBOX_STRICT)
2017# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2018DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2019{
2020 Assert(pPage && pPage->pvPageR3);
2021 return pPage->pvPageR3;
2022}
2023#else
2024# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2025#endif
2026
2027/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2028 * Maps a pool page pool into the current context.
2029 *
2030 * @returns VBox status code.
2031 * @param pPGM Pointer to the PGM instance data.
2032 * @param pPage The pool page.
2033 *
2034 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2035 * small page window employeed by that function. Be careful.
2036 * @remark There is no need to assert on the result.
2037 */
2038#if defined(IN_RC)
2039# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2040#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2041# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2042#else
2043# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2044#endif
2045
2046/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2047 * Maps a pool page pool into the current context.
2048 *
2049 * @returns VBox status code.
2050 * @param pPGM Pointer to the PGMCPU instance data.
2051 * @param pPage The pool page.
2052 *
2053 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2054 * small page window employeed by that function. Be careful.
2055 * @remark There is no need to assert on the result.
2056 */
2057#if defined(IN_RC)
2058# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2059#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2060# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2061#else
2062# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2063#endif
2064
2065
2066/** @name Per guest page tracking data.
2067 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2068 * is to use more bits for it and split it up later on. But for now we'll play
2069 * safe and change as little as possible.
2070 *
2071 * The 16-bit word has two parts:
2072 *
2073 * The first 14-bit forms the @a idx field. It is either the index of a page in
2074 * the shadow page pool, or and index into the extent list.
2075 *
2076 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2077 * shadow page pool references to the page. If cRefs equals
2078 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2079 * (misnomer) table and not the shadow page pool.
2080 *
2081 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2082 * the 16-bit word.
2083 *
2084 * @{ */
2085/** The shift count for getting to the cRefs part. */
2086#define PGMPOOL_TD_CREFS_SHIFT 14
2087/** The mask applied after shifting the tracking data down by
2088 * PGMPOOL_TD_CREFS_SHIFT. */
2089#define PGMPOOL_TD_CREFS_MASK 0x3
2090/** The cRef value used to indiciate that the idx is the head of a
2091 * physical cross reference list. */
2092#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2093/** The shift used to get idx. */
2094#define PGMPOOL_TD_IDX_SHIFT 0
2095/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2096#define PGMPOOL_TD_IDX_MASK 0x3fff
2097/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2098 * simply too many mappings of this page. */
2099#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2100
2101/** @def PGMPOOL_TD_MAKE
2102 * Makes a 16-bit tracking data word.
2103 *
2104 * @returns tracking data.
2105 * @param cRefs The @a cRefs field. Must be within bounds!
2106 * @param idx The @a idx field. Must also be within bounds! */
2107#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2108
2109/** @def PGMPOOL_TD_GET_CREFS
2110 * Get the @a cRefs field from a tracking data word.
2111 *
2112 * @returns The @a cRefs field
2113 * @param u16 The tracking data word. */
2114#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2115
2116/** @def PGMPOOL_TD_GET_IDX
2117 * Get the @a idx field from a tracking data word.
2118 *
2119 * @returns The @a idx field
2120 * @param u16 The tracking data word. */
2121#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2122/** @} */
2123
2124
2125/**
2126 * Trees are using self relative offsets as pointers.
2127 * So, all its data, including the root pointer, must be in the heap for HC and GC
2128 * to have the same layout.
2129 */
2130typedef struct PGMTREES
2131{
2132 /** Physical access handlers (AVL range+offsetptr tree). */
2133 AVLROGCPHYSTREE PhysHandlers;
2134 /** Virtual access handlers (AVL range + GC ptr tree). */
2135 AVLROGCPTRTREE VirtHandlers;
2136 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2137 AVLROGCPHYSTREE PhysToVirtHandlers;
2138 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2139 AVLROGCPTRTREE HyperVirtHandlers;
2140} PGMTREES;
2141/** Pointer to PGM trees. */
2142typedef PGMTREES *PPGMTREES;
2143
2144
2145/** @name Paging mode macros
2146 * @{ */
2147#ifdef IN_RC
2148# define PGM_CTX(a,b) a##RC##b
2149# define PGM_CTX_STR(a,b) a "GC" b
2150# define PGM_CTX_DECL(type) VMMRCDECL(type)
2151#else
2152# ifdef IN_RING3
2153# define PGM_CTX(a,b) a##R3##b
2154# define PGM_CTX_STR(a,b) a "R3" b
2155# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2156# else
2157# define PGM_CTX(a,b) a##R0##b
2158# define PGM_CTX_STR(a,b) a "R0" b
2159# define PGM_CTX_DECL(type) VMMDECL(type)
2160# endif
2161#endif
2162
2163#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2164#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2165#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2166#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2167#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2168#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2169#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2170#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2171#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2172#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2173#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2174#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2175#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2176#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2177#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2178#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2179#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2180
2181#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2182#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2183#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2184#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2185#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2186#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2187#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2188#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2189#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2190#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2191#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2192#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2193#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2194#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2195#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2196#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2197#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2198
2199/* Shw_Gst */
2200#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2201#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2202#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2203#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2204#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2205#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2206#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2207#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2208#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2209#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2210#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2211#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2212#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2213#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2214#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2215#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2216#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2217#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2218#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2219
2220#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2221#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2222#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2223#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2224#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2225#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2226#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2227#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2228#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2229#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2230#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2231#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2232#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2233#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2234#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2235#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2236#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2237#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2238#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2239#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2240#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2241#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2242#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2243#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2244#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2245#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2246#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2247#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2248#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2249#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2250#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2251#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2252#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2253#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2254#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2255#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2256#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2257
2258#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2259#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2260/** @} */
2261
2262/**
2263 * Data for each paging mode.
2264 */
2265typedef struct PGMMODEDATA
2266{
2267 /** The guest mode type. */
2268 uint32_t uGstType;
2269 /** The shadow mode type. */
2270 uint32_t uShwType;
2271
2272 /** @name Function pointers for Shadow paging.
2273 * @{
2274 */
2275 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2276 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2277 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2278 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2279
2280 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2281 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2282
2283 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2284 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2285 /** @} */
2286
2287 /** @name Function pointers for Guest paging.
2288 * @{
2289 */
2290 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2291 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2292 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2293 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2294 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2295 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2296 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2297 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2298 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2299 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2300 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2301 /** @} */
2302
2303 /** @name Function pointers for Both Shadow and Guest paging.
2304 * @{
2305 */
2306 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2307 /* no pfnR3BthTrap0eHandler */
2308 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2309 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2310 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2311 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2312 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2313#ifdef VBOX_STRICT
2314 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2315#endif
2316 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2317 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2318
2319 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2320 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2321 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2322 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2323 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2324 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2325#ifdef VBOX_STRICT
2326 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2327#endif
2328 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2329 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2330
2331 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2332 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2333 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2334 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2335 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2336 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2337#ifdef VBOX_STRICT
2338 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2339#endif
2340 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2341 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2342 /** @} */
2343} PGMMODEDATA, *PPGMMODEDATA;
2344
2345
2346
2347/**
2348 * Converts a PGM pointer into a VM pointer.
2349 * @returns Pointer to the VM structure the PGM is part of.
2350 * @param pPGM Pointer to PGM instance data.
2351 */
2352#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2353
2354/**
2355 * PGM Data (part of VM)
2356 */
2357typedef struct PGM
2358{
2359 /** Offset to the VM structure. */
2360 RTINT offVM;
2361 /** Offset of the PGMCPU structure relative to VMCPU. */
2362 RTINT offVCpuPGM;
2363
2364 /** @cfgm{RamPreAlloc, boolean, false}
2365 * Indicates whether the base RAM should all be allocated before starting
2366 * the VM (default), or if it should be allocated when first written to.
2367 */
2368 bool fRamPreAlloc;
2369 /** Indicates whether write monitoring is currently in use.
2370 * This is used to prevent conflicts between live saving and page sharing
2371 * detection. */
2372 bool fPhysWriteMonitoringEngaged;
2373 /** Alignment padding. */
2374 bool afAlignment0[2];
2375
2376 /*
2377 * This will be redefined at least two more times before we're done, I'm sure.
2378 * The current code is only to get on with the coding.
2379 * - 2004-06-10: initial version, bird.
2380 * - 2004-07-02: 1st time, bird.
2381 * - 2004-10-18: 2nd time, bird.
2382 * - 2005-07-xx: 3rd time, bird.
2383 */
2384
2385 /** The host paging mode. (This is what SUPLib reports.) */
2386 SUPPAGINGMODE enmHostMode;
2387
2388 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2389 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2390 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2391 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2392
2393 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2394 RTGCPHYS GCPhys4MBPSEMask;
2395
2396 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2397 * This is sorted by physical address and contains no overlapping ranges. */
2398 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2399 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2400 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2401 /** RC pointer corresponding to PGM::pRamRangesR3. */
2402 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2403 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2404 * range is linked or unlinked. */
2405 uint32_t volatile idRamRangesGen;
2406
2407 /** Pointer to the list of ROM ranges - for R3.
2408 * This is sorted by physical address and contains no overlapping ranges. */
2409 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2410 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2411 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2412 /** RC pointer corresponding to PGM::pRomRangesR3. */
2413 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2414#if HC_ARCH_BITS == 64
2415 /** Alignment padding. */
2416 RTRCPTR GCPtrPadding2;
2417#endif
2418
2419 /** Pointer to the list of MMIO2 ranges - for R3.
2420 * Registration order. */
2421 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2422
2423 /** PGM offset based trees - R3 Ptr. */
2424 R3PTRTYPE(PPGMTREES) pTreesR3;
2425 /** PGM offset based trees - R0 Ptr. */
2426 R0PTRTYPE(PPGMTREES) pTreesR0;
2427 /** PGM offset based trees - RC Ptr. */
2428 RCPTRTYPE(PPGMTREES) pTreesRC;
2429
2430 /** Linked list of GC mappings - for RC.
2431 * The list is sorted ascending on address.
2432 */
2433 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2434 /** Linked list of GC mappings - for HC.
2435 * The list is sorted ascending on address.
2436 */
2437 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2438 /** Linked list of GC mappings - for R0.
2439 * The list is sorted ascending on address.
2440 */
2441 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2442
2443 /** Pointer to the 5 page CR3 content mapping.
2444 * The first page is always the CR3 (in some form) while the 4 other pages
2445 * are used of the PDs in PAE mode. */
2446 RTGCPTR GCPtrCR3Mapping;
2447#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2448 uint32_t u32Alignment1;
2449#endif
2450
2451 /** Indicates that PGMR3FinalizeMappings has been called and that further
2452 * PGMR3MapIntermediate calls will be rejected. */
2453 bool fFinalizedMappings;
2454 /** If set no conflict checks are required. (boolean) */
2455 bool fMappingsFixed;
2456 /** If set, then no mappings are put into the shadow page table. (boolean) */
2457 bool fDisableMappings;
2458 /** Size of fixed mapping */
2459 uint32_t cbMappingFixed;
2460 /** Base address (GC) of fixed mapping */
2461 RTGCPTR GCPtrMappingFixed;
2462 /** The address of the previous RAM range mapping. */
2463 RTGCPTR GCPtrPrevRamRangeMapping;
2464
2465 /** @name Intermediate Context
2466 * @{ */
2467 /** Pointer to the intermediate page directory - Normal. */
2468 R3PTRTYPE(PX86PD) pInterPD;
2469 /** Pointer to the intermedate page tables - Normal.
2470 * There are two page tables, one for the identity mapping and one for
2471 * the host context mapping (of the core code). */
2472 R3PTRTYPE(PX86PT) apInterPTs[2];
2473 /** Pointer to the intermedate page tables - PAE. */
2474 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2475 /** Pointer to the intermedate page directory - PAE. */
2476 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2477 /** Pointer to the intermedate page directory - PAE. */
2478 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2479 /** Pointer to the intermedate page-map level 4 - AMD64. */
2480 R3PTRTYPE(PX86PML4) pInterPaePML4;
2481 /** Pointer to the intermedate page directory - AMD64. */
2482 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2483 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2484 RTHCPHYS HCPhysInterPD;
2485 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2486 RTHCPHYS HCPhysInterPaePDPT;
2487 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2488 RTHCPHYS HCPhysInterPaePML4;
2489 /** @} */
2490
2491 /** Base address of the dynamic page mapping area.
2492 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2493 */
2494 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2495 /** The index of the last entry used in the dynamic page mapping area. */
2496 RTUINT iDynPageMapLast;
2497 /** Cache containing the last entries in the dynamic page mapping area.
2498 * The cache size is covering half of the mapping area. */
2499 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2500 /** Keep a lock counter for the full (!) mapping area. */
2501 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2502
2503 /** The address of the ring-0 mapping cache if we're making use of it. */
2504 RTR0PTR pvR0DynMapUsed;
2505#if HC_ARCH_BITS == 32
2506 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2507 uint32_t u32Alignment2;
2508#endif
2509
2510 /** PGM critical section.
2511 * This protects the physical & virtual access handlers, ram ranges,
2512 * and the page flag updating (some of it anyway).
2513 */
2514 PDMCRITSECT CritSect;
2515
2516 /** Pointer to SHW+GST mode data (function pointers).
2517 * The index into this table is made up from */
2518 R3PTRTYPE(PPGMMODEDATA) paModeData;
2519
2520 /** Shadow Page Pool - R3 Ptr. */
2521 R3PTRTYPE(PPGMPOOL) pPoolR3;
2522 /** Shadow Page Pool - R0 Ptr. */
2523 R0PTRTYPE(PPGMPOOL) pPoolR0;
2524 /** Shadow Page Pool - RC Ptr. */
2525 RCPTRTYPE(PPGMPOOL) pPoolRC;
2526
2527 /** We're not in a state which permits writes to guest memory.
2528 * (Only used in strict builds.) */
2529 bool fNoMorePhysWrites;
2530 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2531 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2532
2533 /**
2534 * Data associated with managing the ring-3 mappings of the allocation chunks.
2535 */
2536 struct
2537 {
2538 /** The chunk tree, ordered by chunk id. */
2539#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2540 R3PTRTYPE(PAVLU32NODECORE) pTree;
2541#else
2542 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2543#endif
2544 /** The chunk age tree, ordered by ageing sequence number. */
2545 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2546 /** The chunk mapping TLB. */
2547 PGMCHUNKR3MAPTLB Tlb;
2548 /** The number of mapped chunks. */
2549 uint32_t c;
2550 /** The maximum number of mapped chunks.
2551 * @cfgm PGM/MaxRing3Chunks */
2552 uint32_t cMax;
2553 /** The current time. */
2554 uint32_t iNow;
2555 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2556 uint32_t AgeingCountdown;
2557 } ChunkR3Map;
2558
2559 /**
2560 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2561 */
2562 PGMPAGER3MAPTLB PhysTlbHC;
2563
2564 /** @name The zero page.
2565 * @{ */
2566 /** The host physical address of the zero page. */
2567 RTHCPHYS HCPhysZeroPg;
2568 /** The ring-3 mapping of the zero page. */
2569 RTR3PTR pvZeroPgR3;
2570 /** The ring-0 mapping of the zero page. */
2571 RTR0PTR pvZeroPgR0;
2572 /** The GC mapping of the zero page. */
2573 RTGCPTR pvZeroPgRC;
2574#if GC_ARCH_BITS != 32
2575 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2576#endif
2577 /** @}*/
2578
2579 /** The number of handy pages. */
2580 uint32_t cHandyPages;
2581 /**
2582 * Array of handy pages.
2583 *
2584 * This array is used in a two way communication between pgmPhysAllocPage
2585 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2586 * an intermediary.
2587 *
2588 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2589 * (The current size of 32 pages, means 128 KB of handy memory.)
2590 */
2591 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2592
2593 /**
2594 * Live save data.
2595 */
2596 struct
2597 {
2598 /** The number of ready pages. */
2599 uint32_t cReadyPages;
2600 /** The number of dirty pages. (Not counting MMIO and MMIO2 pages.) */
2601 uint32_t cDirtyPages;
2602 /** The number of MMIO and MMIO2 pages. */
2603 uint32_t cMmioPages;
2604 /** The number of monitored pages. */
2605 uint32_t cMonitoredPages;
2606 /** Indicates that a live save operation is active. */
2607 bool fActive;
2608 /** Padding. */
2609 bool afReserved[7];
2610 } LiveSave;
2611
2612 /** @name Error injection.
2613 * @{ */
2614 /** Inject handy page allocation errors pretending we're completely out of
2615 * memory. */
2616 bool volatile fErrInjHandyPages;
2617 /** Padding. */
2618 bool afReserved[7];
2619 /** @} */
2620
2621 /** @name Release Statistics
2622 * @{ */
2623 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2624 uint32_t cPrivatePages; /**< The number of private pages. */
2625 uint32_t cSharedPages; /**< The number of shared pages. */
2626 uint32_t cZeroPages; /**< The number of zero backed pages. */
2627 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2628 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2629
2630 /** The number of times we were forced to change the hypervisor region location. */
2631 STAMCOUNTER cRelocations;
2632 /** @} */
2633
2634#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2635 /* R3 only: */
2636 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2637 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2638
2639 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2640 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2641 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2642 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2643 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2644 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2645 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2646 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2647 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2648 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2649 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2650 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2651 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2652 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2653 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2654 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2655 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2656 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2657/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2658 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2659 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2660/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2661
2662 /* RC only: */
2663 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2664 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2665 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2666 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2667
2668 STAMCOUNTER StatRZPhysRead;
2669 STAMCOUNTER StatRZPhysReadBytes;
2670 STAMCOUNTER StatRZPhysWrite;
2671 STAMCOUNTER StatRZPhysWriteBytes;
2672 STAMCOUNTER StatR3PhysRead;
2673 STAMCOUNTER StatR3PhysReadBytes;
2674 STAMCOUNTER StatR3PhysWrite;
2675 STAMCOUNTER StatR3PhysWriteBytes;
2676 STAMCOUNTER StatRCPhysRead;
2677 STAMCOUNTER StatRCPhysReadBytes;
2678 STAMCOUNTER StatRCPhysWrite;
2679 STAMCOUNTER StatRCPhysWriteBytes;
2680
2681 STAMCOUNTER StatRZPhysSimpleRead;
2682 STAMCOUNTER StatRZPhysSimpleReadBytes;
2683 STAMCOUNTER StatRZPhysSimpleWrite;
2684 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2685 STAMCOUNTER StatR3PhysSimpleRead;
2686 STAMCOUNTER StatR3PhysSimpleReadBytes;
2687 STAMCOUNTER StatR3PhysSimpleWrite;
2688 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2689 STAMCOUNTER StatRCPhysSimpleRead;
2690 STAMCOUNTER StatRCPhysSimpleReadBytes;
2691 STAMCOUNTER StatRCPhysSimpleWrite;
2692 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2693
2694# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2695 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2696 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2697 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2698 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2699 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2700 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2701# endif
2702#endif
2703} PGM;
2704#ifndef IN_TSTVMSTRUCTGC /* HACK */
2705AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2706AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2707AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2708AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2709AssertCompileMemberAlignment(PGM, CritSect, 8);
2710AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2711AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2712AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2713AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2714AssertCompileMemberAlignment(PGM, cRelocations, 8);
2715#endif /* !IN_TSTVMSTRUCTGC */
2716/** Pointer to the PGM instance data. */
2717typedef PGM *PPGM;
2718
2719
2720/**
2721 * Converts a PGMCPU pointer into a VM pointer.
2722 * @returns Pointer to the VM structure the PGM is part of.
2723 * @param pPGM Pointer to PGMCPU instance data.
2724 */
2725#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2726
2727/**
2728 * Converts a PGMCPU pointer into a PGM pointer.
2729 * @returns Pointer to the VM structure the PGM is part of.
2730 * @param pPGM Pointer to PGMCPU instance data.
2731 */
2732#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2733
2734/**
2735 * PGMCPU Data (part of VMCPU).
2736 */
2737typedef struct PGMCPU
2738{
2739 /** Offset to the VM structure. */
2740 RTINT offVM;
2741 /** Offset to the VMCPU structure. */
2742 RTINT offVCpu;
2743 /** Offset of the PGM structure relative to VMCPU. */
2744 RTINT offPGM;
2745 RTINT uPadding0; /**< structure size alignment. */
2746
2747#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2748 /** Automatically tracked physical memory mapping set.
2749 * Ring-0 and strict raw-mode builds. */
2750 PGMMAPSET AutoSet;
2751#endif
2752
2753 /** A20 gate mask.
2754 * Our current approach to A20 emulation is to let REM do it and don't bother
2755 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2756 * But whould need arrise, we'll subject physical addresses to this mask. */
2757 RTGCPHYS GCPhysA20Mask;
2758 /** A20 gate state - boolean! */
2759 bool fA20Enabled;
2760
2761 /** What needs syncing (PGM_SYNC_*).
2762 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2763 * PGMFlushTLB, and PGMR3Load. */
2764 RTUINT fSyncFlags;
2765
2766 /** The shadow paging mode. */
2767 PGMMODE enmShadowMode;
2768 /** The guest paging mode. */
2769 PGMMODE enmGuestMode;
2770
2771 /** The current physical address representing in the guest CR3 register. */
2772 RTGCPHYS GCPhysCR3;
2773
2774 /** @name 32-bit Guest Paging.
2775 * @{ */
2776 /** The guest's page directory, R3 pointer. */
2777 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2778#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2779 /** The guest's page directory, R0 pointer. */
2780 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2781#endif
2782 /** The guest's page directory, static RC mapping. */
2783 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2784 /** @} */
2785
2786 /** @name PAE Guest Paging.
2787 * @{ */
2788 /** The guest's page directory pointer table, static RC mapping. */
2789 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2790 /** The guest's page directory pointer table, R3 pointer. */
2791 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2792#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2793 /** The guest's page directory pointer table, R0 pointer. */
2794 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2795#endif
2796
2797 /** The guest's page directories, R3 pointers.
2798 * These are individual pointers and don't have to be adjecent.
2799 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2800 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2801 /** The guest's page directories, R0 pointers.
2802 * Same restrictions as apGstPaePDsR3. */
2803#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2804 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2805#endif
2806 /** The guest's page directories, static GC mapping.
2807 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2808 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2809 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2810 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2811 RTGCPHYS aGCPhysGstPaePDs[4];
2812 /** The physical addresses of the monitored guest page directories (PAE). */
2813 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2814 /** @} */
2815
2816 /** @name AMD64 Guest Paging.
2817 * @{ */
2818 /** The guest's page directory pointer table, R3 pointer. */
2819 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2820#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2821 /** The guest's page directory pointer table, R0 pointer. */
2822 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2823#endif
2824 /** @} */
2825
2826 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2827 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2828 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2829 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2830 /** Pointer to the page of the current active CR3 - RC Ptr. */
2831 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2832 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2833 uint32_t iShwUser;
2834 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2835 uint32_t iShwUserTable;
2836# if HC_ARCH_BITS == 64
2837 RTRCPTR alignment6; /**< structure size alignment. */
2838# endif
2839 /** @} */
2840
2841 /** @name Function pointers for Shadow paging.
2842 * @{
2843 */
2844 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2845 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2846 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2847 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2848
2849 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2850 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2851
2852 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2853 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2854
2855 /** @} */
2856
2857 /** @name Function pointers for Guest paging.
2858 * @{
2859 */
2860 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2861 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2862 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2863 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2864 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2865 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2866 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2867 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2868#if HC_ARCH_BITS == 64
2869 RTRCPTR alignment3; /**< structure size alignment. */
2870#endif
2871
2872 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2873 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2874 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2875 /** @} */
2876
2877 /** @name Function pointers for Both Shadow and Guest paging.
2878 * @{
2879 */
2880 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2881 /* no pfnR3BthTrap0eHandler */
2882 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2883 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2884 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2885 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2886 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2887 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2888 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2889 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2890
2891 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2892 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2893 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2894 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2895 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2896 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2897 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2898 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2899 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2900
2901 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2902 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2903 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2904 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2905 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2906 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2907 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2908 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2909 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2910 RTRCPTR alignment2; /**< structure size alignment. */
2911 /** @} */
2912
2913 /** For saving stack space, the disassembler state is allocated here instead of
2914 * on the stack.
2915 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2916 union
2917 {
2918 /** The disassembler scratch space. */
2919 DISCPUSTATE DisState;
2920 /** Padding. */
2921 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2922 };
2923
2924 /* Count the number of pgm pool access handler calls. */
2925 uint64_t cPoolAccessHandler;
2926
2927 /** @name Release Statistics
2928 * @{ */
2929 /** The number of times the guest has switched mode since last reset or statistics reset. */
2930 STAMCOUNTER cGuestModeChanges;
2931 /** @} */
2932
2933#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2934 /** @name Statistics
2935 * @{ */
2936 /** RC: Which statistic this \#PF should be attributed to. */
2937 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2938 RTRCPTR padding0;
2939 /** R0: Which statistic this \#PF should be attributed to. */
2940 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2941 RTR0PTR padding1;
2942
2943 /* Common */
2944 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2945 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2946
2947 /* R0 only: */
2948 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2949 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2950 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2951 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2952 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2953 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2954 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2955 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2956 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2957 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2958 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2959 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2960 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2961 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2962 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2963 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2964 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2965 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2966 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2967 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2968 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2969 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2970 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2971 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2972 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2973 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2974
2975 /* RZ only: */
2976 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2977 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2978 STAMPROFILE StatRZTrap0eTimeSyncPT;
2979 STAMPROFILE StatRZTrap0eTimeMapping;
2980 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2981 STAMPROFILE StatRZTrap0eTimeHandlers;
2982 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2983 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2984 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2985 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2986 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2987 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2988 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2989 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2990 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2991 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2992 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2993 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2994 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2995 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2996 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2997 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2998 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2999 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3000 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3001 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3002 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3003 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
3004 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
3005 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
3006 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
3007 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
3008 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
3009 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
3010 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
3011 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
3012 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
3013 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
3014 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
3015 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
3016 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
3017 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3018 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3019 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
3020 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3021 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3022 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3023 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3024 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3025
3026 /* HC - R3 and (maybe) R0: */
3027
3028 /* RZ & R3: */
3029 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3030 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3031 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3032 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3033 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3034 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3035 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3036 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3037 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3038 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3039 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3040 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3041 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3042 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3043 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3044 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3045 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3046 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3047 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3048 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3049 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3050 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3051 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3052 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3053 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3054 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3055 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3056 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3057 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3058 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3059 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3060 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3061 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3062 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3063 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3064 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3065 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3066 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in #PF. */
3067 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF. */
3068 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3069 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3070 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3071 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3072 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3073 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3074 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3075
3076 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3077 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3078 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3079 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3080 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3081 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3082 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3083 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3084 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3085 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3086 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3087 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3088 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3089 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3090 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3091 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3092 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3093 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3094 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3095 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3096 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3097 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3098 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3099 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3100 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3101 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3102 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3103 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3104 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3105 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3106 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3107 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3108 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3109 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3110 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3111 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3112 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in #PF. */
3113 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in #PF. */
3114 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3115 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3116 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3117 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3118 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3119 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3120 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3121 /** @} */
3122#endif /* VBOX_WITH_STATISTICS */
3123} PGMCPU;
3124/** Pointer to the per-cpu PGM data. */
3125typedef PGMCPU *PPGMCPU;
3126
3127
3128/** @name PGM::fSyncFlags Flags
3129 * @{
3130 */
3131/** Updates the virtual access handler state bit in PGMPAGE. */
3132#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3133/** Always sync CR3. */
3134#define PGM_SYNC_ALWAYS RT_BIT(1)
3135/** Check monitoring on next CR3 (re)load and invalidate page.
3136 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3137#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3138/** Check guest mapping in SyncCR3. */
3139#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3140/** Clear the page pool (a light weight flush). */
3141#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3142#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3143/** @} */
3144
3145
3146RT_C_DECLS_BEGIN
3147
3148int pgmLock(PVM pVM);
3149void pgmUnlock(PVM pVM);
3150
3151int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3152int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3153PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3154void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3155DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3156
3157void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3158bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3159void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3160int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3161DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3162#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3163void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3164#else
3165# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3166#endif
3167DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3168int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3169
3170int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3171int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3172int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3173int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3174int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3175int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3176int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3177int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3178int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3179VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3180#ifdef IN_RING3
3181void pgmR3PhysRelinkRamRanges(PVM pVM);
3182int pgmR3PhysRamPreAllocate(PVM pVM);
3183int pgmR3PhysRamReset(PVM pVM);
3184int pgmR3PhysRomReset(PVM pVM);
3185int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3186
3187int pgmR3PoolInit(PVM pVM);
3188void pgmR3PoolRelocate(PVM pVM);
3189void pgmR3PoolReset(PVM pVM);
3190void pgmR3PoolClearAll(PVM pVM);
3191
3192#endif /* IN_RING3 */
3193#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3194int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3195#endif
3196int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3197
3198DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3199{
3200 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3201}
3202
3203void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3204void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3205int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3206void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3207PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3208int pgmPoolSyncCR3(PVMCPU pVCpu);
3209bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3210int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3211DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3212{
3213 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3214}
3215
3216uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3217void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3218void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3219#ifdef PGMPOOL_WITH_MONITORING
3220void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3221int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3222void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3223#endif
3224
3225void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3226void pgmPoolResetDirtyPages(PVM pVM);
3227
3228int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3229int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3230
3231void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3232void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3233int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3234int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3235
3236int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3237#ifndef IN_RC
3238int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3239#endif
3240int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3241
3242PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3243PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3244PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3245PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3246
3247RT_C_DECLS_END
3248
3249
3250/**
3251 * Gets the PGMRAMRANGE structure for a guest page.
3252 *
3253 * @returns Pointer to the RAM range on success.
3254 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3255 *
3256 * @param pPGM PGM handle.
3257 * @param GCPhys The GC physical address.
3258 */
3259DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3260{
3261 /*
3262 * Optimize for the first range.
3263 */
3264 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3265 RTGCPHYS off = GCPhys - pRam->GCPhys;
3266 if (RT_UNLIKELY(off >= pRam->cb))
3267 {
3268 do
3269 {
3270 pRam = pRam->CTX_SUFF(pNext);
3271 if (RT_UNLIKELY(!pRam))
3272 break;
3273 off = GCPhys - pRam->GCPhys;
3274 } while (off >= pRam->cb);
3275 }
3276 return pRam;
3277}
3278
3279
3280/**
3281 * Gets the PGMPAGE structure for a guest page.
3282 *
3283 * @returns Pointer to the page on success.
3284 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3285 *
3286 * @param pPGM PGM handle.
3287 * @param GCPhys The GC physical address.
3288 */
3289DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3290{
3291 /*
3292 * Optimize for the first range.
3293 */
3294 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3295 RTGCPHYS off = GCPhys - pRam->GCPhys;
3296 if (RT_UNLIKELY(off >= pRam->cb))
3297 {
3298 do
3299 {
3300 pRam = pRam->CTX_SUFF(pNext);
3301 if (RT_UNLIKELY(!pRam))
3302 return NULL;
3303 off = GCPhys - pRam->GCPhys;
3304 } while (off >= pRam->cb);
3305 }
3306 return &pRam->aPages[off >> PAGE_SHIFT];
3307}
3308
3309
3310/**
3311 * Gets the PGMPAGE structure for a guest page.
3312 *
3313 * Old Phys code: Will make sure the page is present.
3314 *
3315 * @returns VBox status code.
3316 * @retval VINF_SUCCESS and a valid *ppPage on success.
3317 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3318 *
3319 * @param pPGM PGM handle.
3320 * @param GCPhys The GC physical address.
3321 * @param ppPage Where to store the page pointer on success.
3322 */
3323DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3324{
3325 /*
3326 * Optimize for the first range.
3327 */
3328 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3329 RTGCPHYS off = GCPhys - pRam->GCPhys;
3330 if (RT_UNLIKELY(off >= pRam->cb))
3331 {
3332 do
3333 {
3334 pRam = pRam->CTX_SUFF(pNext);
3335 if (RT_UNLIKELY(!pRam))
3336 {
3337 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3338 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3339 }
3340 off = GCPhys - pRam->GCPhys;
3341 } while (off >= pRam->cb);
3342 }
3343 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3344 return VINF_SUCCESS;
3345}
3346
3347
3348
3349
3350/**
3351 * Gets the PGMPAGE structure for a guest page.
3352 *
3353 * Old Phys code: Will make sure the page is present.
3354 *
3355 * @returns VBox status code.
3356 * @retval VINF_SUCCESS and a valid *ppPage on success.
3357 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3358 *
3359 * @param pPGM PGM handle.
3360 * @param GCPhys The GC physical address.
3361 * @param ppPage Where to store the page pointer on success.
3362 * @param ppRamHint Where to read and store the ram list hint.
3363 * The caller initializes this to NULL before the call.
3364 */
3365DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3366{
3367 RTGCPHYS off;
3368 PPGMRAMRANGE pRam = *ppRamHint;
3369 if ( !pRam
3370 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3371 {
3372 pRam = pPGM->CTX_SUFF(pRamRanges);
3373 off = GCPhys - pRam->GCPhys;
3374 if (RT_UNLIKELY(off >= pRam->cb))
3375 {
3376 do
3377 {
3378 pRam = pRam->CTX_SUFF(pNext);
3379 if (RT_UNLIKELY(!pRam))
3380 {
3381 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3382 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3383 }
3384 off = GCPhys - pRam->GCPhys;
3385 } while (off >= pRam->cb);
3386 }
3387 *ppRamHint = pRam;
3388 }
3389 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3390 return VINF_SUCCESS;
3391}
3392
3393
3394/**
3395 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3396 *
3397 * @returns Pointer to the page on success.
3398 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3399 *
3400 * @param pPGM PGM handle.
3401 * @param GCPhys The GC physical address.
3402 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3403 */
3404DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3405{
3406 /*
3407 * Optimize for the first range.
3408 */
3409 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3410 RTGCPHYS off = GCPhys - pRam->GCPhys;
3411 if (RT_UNLIKELY(off >= pRam->cb))
3412 {
3413 do
3414 {
3415 pRam = pRam->CTX_SUFF(pNext);
3416 if (RT_UNLIKELY(!pRam))
3417 return NULL;
3418 off = GCPhys - pRam->GCPhys;
3419 } while (off >= pRam->cb);
3420 }
3421 *ppRam = pRam;
3422 return &pRam->aPages[off >> PAGE_SHIFT];
3423}
3424
3425
3426/**
3427 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3428 *
3429 * @returns Pointer to the page on success.
3430 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3431 *
3432 * @param pPGM PGM handle.
3433 * @param GCPhys The GC physical address.
3434 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3435 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3436 */
3437DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3438{
3439 /*
3440 * Optimize for the first range.
3441 */
3442 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3443 RTGCPHYS off = GCPhys - pRam->GCPhys;
3444 if (RT_UNLIKELY(off >= pRam->cb))
3445 {
3446 do
3447 {
3448 pRam = pRam->CTX_SUFF(pNext);
3449 if (RT_UNLIKELY(!pRam))
3450 {
3451 *ppRam = NULL; /* Shut up silly GCC warnings. */
3452 *ppPage = NULL; /* ditto */
3453 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3454 }
3455 off = GCPhys - pRam->GCPhys;
3456 } while (off >= pRam->cb);
3457 }
3458 *ppRam = pRam;
3459 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3460 return VINF_SUCCESS;
3461}
3462
3463
3464/**
3465 * Convert GC Phys to HC Phys.
3466 *
3467 * @returns VBox status.
3468 * @param pPGM PGM handle.
3469 * @param GCPhys The GC physical address.
3470 * @param pHCPhys Where to store the corresponding HC physical address.
3471 *
3472 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3473 * Avoid when writing new code!
3474 */
3475DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3476{
3477 PPGMPAGE pPage;
3478 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3479 if (RT_FAILURE(rc))
3480 return rc;
3481 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3482 return VINF_SUCCESS;
3483}
3484
3485#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3486
3487/**
3488 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3489 * optimizes access to pages already in the set.
3490 *
3491 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3492 * @param pPGM Pointer to the PVM instance data.
3493 * @param HCPhys The physical address of the page.
3494 * @param ppv Where to store the mapping address.
3495 */
3496DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3497{
3498 PVM pVM = PGM2VM(pPGM);
3499 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3500 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3501
3502 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3503 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3504 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3505
3506 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3507 unsigned iEntry = pSet->aiHashTable[iHash];
3508 if ( iEntry < pSet->cEntries
3509 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3510 {
3511 *ppv = pSet->aEntries[iEntry].pvPage;
3512 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3513 }
3514 else
3515 {
3516 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3517 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3518 }
3519
3520 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3521 return VINF_SUCCESS;
3522}
3523
3524
3525/**
3526 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3527 * access to pages already in the set.
3528 *
3529 * @returns See PGMDynMapGCPage.
3530 * @param pPGM Pointer to the PVM instance data.
3531 * @param HCPhys The physical address of the page.
3532 * @param ppv Where to store the mapping address.
3533 */
3534DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3535{
3536 PVM pVM = PGM2VM(pPGM);
3537 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3538
3539 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3540 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3541
3542 /*
3543 * Get the ram range.
3544 */
3545 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3546 RTGCPHYS off = GCPhys - pRam->GCPhys;
3547 if (RT_UNLIKELY(off >= pRam->cb
3548 /** @todo || page state stuff */))
3549 {
3550 /* This case is not counted into StatR0DynMapGCPageInl. */
3551 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3552 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3553 }
3554
3555 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3556 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3557
3558 /*
3559 * pgmR0DynMapHCPageInlined with out stats.
3560 */
3561 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3562 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3563 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3564
3565 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3566 unsigned iEntry = pSet->aiHashTable[iHash];
3567 if ( iEntry < pSet->cEntries
3568 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3569 {
3570 *ppv = pSet->aEntries[iEntry].pvPage;
3571 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3572 }
3573 else
3574 {
3575 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3576 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3577 }
3578
3579 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3580 return VINF_SUCCESS;
3581}
3582
3583
3584/**
3585 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3586 * access to pages already in the set.
3587 *
3588 * @returns See PGMDynMapGCPage.
3589 * @param pPGM Pointer to the PVM instance data.
3590 * @param HCPhys The physical address of the page.
3591 * @param ppv Where to store the mapping address.
3592 */
3593DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3594{
3595 PVM pVM = PGM2VM(pPGM);
3596 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3597
3598 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3599
3600 /*
3601 * Get the ram range.
3602 */
3603 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3604 RTGCPHYS off = GCPhys - pRam->GCPhys;
3605 if (RT_UNLIKELY(off >= pRam->cb
3606 /** @todo || page state stuff */))
3607 {
3608 /* This case is not counted into StatR0DynMapGCPageInl. */
3609 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3610 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3611 }
3612
3613 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3614 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3615
3616 /*
3617 * pgmR0DynMapHCPageInlined with out stats.
3618 */
3619 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3620 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3621 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3622
3623 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3624 unsigned iEntry = pSet->aiHashTable[iHash];
3625 if ( iEntry < pSet->cEntries
3626 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3627 {
3628 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3629 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3630 }
3631 else
3632 {
3633 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3634 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3635 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3636 }
3637
3638 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3639 return VINF_SUCCESS;
3640}
3641
3642#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3643#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3644
3645/**
3646 * Maps the page into current context (RC and maybe R0).
3647 *
3648 * @returns pointer to the mapping.
3649 * @param pVM Pointer to the PGM instance data.
3650 * @param pPage The page.
3651 */
3652DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3653{
3654 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3655 {
3656 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3657 void *pv;
3658# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3659 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3660# else
3661 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3662# endif
3663 return pv;
3664 }
3665 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3666}
3667
3668/**
3669 * Temporarily maps one host page specified by HC physical address, returning
3670 * pointer within the page.
3671 *
3672 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3673 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3674 *
3675 * @returns The address corresponding to HCPhys.
3676 * @param pPGM Pointer to the PVM instance data.
3677 * @param HCPhys HC Physical address of the page.
3678 */
3679DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3680{
3681 void *pv;
3682# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3683 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3684# else
3685 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3686# endif
3687 pv = (void *)((uintptr_t)pv | ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3688 return pv;
3689}
3690
3691#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3692#ifndef IN_RC
3693
3694/**
3695 * Queries the Physical TLB entry for a physical guest page,
3696 * attempting to load the TLB entry if necessary.
3697 *
3698 * @returns VBox status code.
3699 * @retval VINF_SUCCESS on success
3700 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3701 *
3702 * @param pPGM The PGM instance handle.
3703 * @param GCPhys The address of the guest page.
3704 * @param ppTlbe Where to store the pointer to the TLB entry.
3705 */
3706DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3707{
3708 int rc;
3709 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3710 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3711 {
3712 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3713 rc = VINF_SUCCESS;
3714 }
3715 else
3716 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3717 *ppTlbe = pTlbe;
3718 return rc;
3719}
3720
3721
3722/**
3723 * Queries the Physical TLB entry for a physical guest page,
3724 * attempting to load the TLB entry if necessary.
3725 *
3726 * @returns VBox status code.
3727 * @retval VINF_SUCCESS on success
3728 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3729 *
3730 * @param pPGM The PGM instance handle.
3731 * @param pPage Pointer to the PGMPAGE structure corresponding to
3732 * GCPhys.
3733 * @param GCPhys The address of the guest page.
3734 * @param ppTlbe Where to store the pointer to the TLB entry.
3735 */
3736DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3737{
3738 int rc;
3739 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3740 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3741 {
3742 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3743 rc = VINF_SUCCESS;
3744 }
3745 else
3746 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3747 *ppTlbe = pTlbe;
3748 return rc;
3749}
3750
3751#endif /* !IN_RC */
3752
3753/**
3754 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3755 * Takes PSE-36 into account.
3756 *
3757 * @returns guest physical address
3758 * @param pPGM Pointer to the PGM instance data.
3759 * @param Pde Guest Pde
3760 */
3761DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3762{
3763 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3764 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3765
3766 return GCPhys & pPGM->GCPhys4MBPSEMask;
3767}
3768
3769
3770/**
3771 * Gets the page directory entry for the specified address (32-bit paging).
3772 *
3773 * @returns The page directory entry in question.
3774 * @param pPGM Pointer to the PGM instance data.
3775 * @param GCPtr The address.
3776 */
3777DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3778{
3779#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3780 PCX86PD pGuestPD = NULL;
3781 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3782 if (RT_FAILURE(rc))
3783 {
3784 X86PDE ZeroPde = {0};
3785 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3786 }
3787#else
3788 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3789# ifdef IN_RING3
3790 if (!pGuestPD)
3791 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3792# endif
3793#endif
3794 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3795}
3796
3797
3798/**
3799 * Gets the address of a specific page directory entry (32-bit paging).
3800 *
3801 * @returns Pointer the page directory entry in question.
3802 * @param pPGM Pointer to the PGM instance data.
3803 * @param GCPtr The address.
3804 */
3805DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3806{
3807#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3808 PX86PD pGuestPD = NULL;
3809 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3810 AssertRCReturn(rc, NULL);
3811#else
3812 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3813# ifdef IN_RING3
3814 if (!pGuestPD)
3815 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3816# endif
3817#endif
3818 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3819}
3820
3821
3822/**
3823 * Gets the address the guest page directory (32-bit paging).
3824 *
3825 * @returns Pointer the page directory entry in question.
3826 * @param pPGM Pointer to the PGM instance data.
3827 */
3828DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3829{
3830#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3831 PX86PD pGuestPD = NULL;
3832 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3833 AssertRCReturn(rc, NULL);
3834#else
3835 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3836# ifdef IN_RING3
3837 if (!pGuestPD)
3838 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3839# endif
3840#endif
3841 return pGuestPD;
3842}
3843
3844
3845/**
3846 * Gets the guest page directory pointer table.
3847 *
3848 * @returns Pointer to the page directory in question.
3849 * @returns NULL if the page directory is not present or on an invalid page.
3850 * @param pPGM Pointer to the PGM instance data.
3851 */
3852DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3853{
3854#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3855 PX86PDPT pGuestPDPT = NULL;
3856 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3857 AssertRCReturn(rc, NULL);
3858#else
3859 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3860# ifdef IN_RING3
3861 if (!pGuestPDPT)
3862 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3863# endif
3864#endif
3865 return pGuestPDPT;
3866}
3867
3868
3869/**
3870 * Gets the guest page directory pointer table entry for the specified address.
3871 *
3872 * @returns Pointer to the page directory in question.
3873 * @returns NULL if the page directory is not present or on an invalid page.
3874 * @param pPGM Pointer to the PGM instance data.
3875 * @param GCPtr The address.
3876 */
3877DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3878{
3879 AssertGCPtr32(GCPtr);
3880
3881#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3882 PX86PDPT pGuestPDPT = 0;
3883 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3884 AssertRCReturn(rc, 0);
3885#else
3886 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3887# ifdef IN_RING3
3888 if (!pGuestPDPT)
3889 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3890# endif
3891#endif
3892 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3893}
3894
3895
3896/**
3897 * Gets the page directory for the specified address.
3898 *
3899 * @returns Pointer to the page directory in question.
3900 * @returns NULL if the page directory is not present or on an invalid page.
3901 * @param pPGM Pointer to the PGM instance data.
3902 * @param GCPtr The address.
3903 */
3904DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3905{
3906 AssertGCPtr32(GCPtr);
3907
3908 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3909 AssertReturn(pGuestPDPT, NULL);
3910 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3911 if (pGuestPDPT->a[iPdpt].n.u1Present)
3912 {
3913#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3914 PX86PDPAE pGuestPD = NULL;
3915 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3916 AssertRCReturn(rc, NULL);
3917#else
3918 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3919 if ( !pGuestPD
3920 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3921 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3922#endif
3923 return pGuestPD;
3924 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3925 }
3926 return NULL;
3927}
3928
3929
3930/**
3931 * Gets the page directory entry for the specified address.
3932 *
3933 * @returns Pointer to the page directory entry in question.
3934 * @returns NULL if the page directory is not present or on an invalid page.
3935 * @param pPGM Pointer to the PGM instance data.
3936 * @param GCPtr The address.
3937 */
3938DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3939{
3940 AssertGCPtr32(GCPtr);
3941
3942 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3943 AssertReturn(pGuestPDPT, NULL);
3944 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3945 if (pGuestPDPT->a[iPdpt].n.u1Present)
3946 {
3947 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3948#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3949 PX86PDPAE pGuestPD = NULL;
3950 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3951 AssertRCReturn(rc, NULL);
3952#else
3953 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3954 if ( !pGuestPD
3955 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3956 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3957#endif
3958 return &pGuestPD->a[iPD];
3959 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3960 }
3961 return NULL;
3962}
3963
3964
3965/**
3966 * Gets the page directory entry for the specified address.
3967 *
3968 * @returns The page directory entry in question.
3969 * @returns A non-present entry if the page directory is not present or on an invalid page.
3970 * @param pPGM Pointer to the PGM instance data.
3971 * @param GCPtr The address.
3972 */
3973DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3974{
3975 AssertGCPtr32(GCPtr);
3976 X86PDEPAE ZeroPde = {0};
3977 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3978 if (RT_LIKELY(pGuestPDPT))
3979 {
3980 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3981 if (pGuestPDPT->a[iPdpt].n.u1Present)
3982 {
3983 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3984#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3985 PX86PDPAE pGuestPD = NULL;
3986 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3987 AssertRCReturn(rc, ZeroPde);
3988#else
3989 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3990 if ( !pGuestPD
3991 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3992 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3993#endif
3994 return pGuestPD->a[iPD];
3995 }
3996 }
3997 return ZeroPde;
3998}
3999
4000
4001/**
4002 * Gets the page directory pointer table entry for the specified address
4003 * and returns the index into the page directory
4004 *
4005 * @returns Pointer to the page directory in question.
4006 * @returns NULL if the page directory is not present or on an invalid page.
4007 * @param pPGM Pointer to the PGM instance data.
4008 * @param GCPtr The address.
4009 * @param piPD Receives the index into the returned page directory
4010 * @param pPdpe Receives the page directory pointer entry. Optional.
4011 */
4012DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4013{
4014 AssertGCPtr32(GCPtr);
4015
4016 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4017 AssertReturn(pGuestPDPT, NULL);
4018 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4019 if (pPdpe)
4020 *pPdpe = pGuestPDPT->a[iPdpt];
4021 if (pGuestPDPT->a[iPdpt].n.u1Present)
4022 {
4023 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4024#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4025 PX86PDPAE pGuestPD = NULL;
4026 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4027 AssertRCReturn(rc, NULL);
4028#else
4029 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4030 if ( !pGuestPD
4031 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4032 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4033#endif
4034 *piPD = iPD;
4035 return pGuestPD;
4036 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4037 }
4038 return NULL;
4039}
4040
4041#ifndef IN_RC
4042
4043/**
4044 * Gets the page map level-4 pointer for the guest.
4045 *
4046 * @returns Pointer to the PML4 page.
4047 * @param pPGM Pointer to the PGM instance data.
4048 */
4049DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4050{
4051#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4052 PX86PML4 pGuestPml4;
4053 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4054 AssertRCReturn(rc, NULL);
4055#else
4056 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4057# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4058 if (!pGuestPml4)
4059 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4060# endif
4061 Assert(pGuestPml4);
4062#endif
4063 return pGuestPml4;
4064}
4065
4066
4067/**
4068 * Gets the pointer to a page map level-4 entry.
4069 *
4070 * @returns Pointer to the PML4 entry.
4071 * @param pPGM Pointer to the PGM instance data.
4072 * @param iPml4 The index.
4073 */
4074DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4075{
4076#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4077 PX86PML4 pGuestPml4;
4078 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4079 AssertRCReturn(rc, NULL);
4080#else
4081 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4082# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4083 if (!pGuestPml4)
4084 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4085# endif
4086 Assert(pGuestPml4);
4087#endif
4088 return &pGuestPml4->a[iPml4];
4089}
4090
4091
4092/**
4093 * Gets a page map level-4 entry.
4094 *
4095 * @returns The PML4 entry.
4096 * @param pPGM Pointer to the PGM instance data.
4097 * @param iPml4 The index.
4098 */
4099DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4100{
4101#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4102 PX86PML4 pGuestPml4;
4103 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4104 if (RT_FAILURE(rc))
4105 {
4106 X86PML4E ZeroPml4e = {0};
4107 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4108 }
4109#else
4110 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4111# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4112 if (!pGuestPml4)
4113 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4114# endif
4115 Assert(pGuestPml4);
4116#endif
4117 return pGuestPml4->a[iPml4];
4118}
4119
4120
4121/**
4122 * Gets the page directory pointer entry for the specified address.
4123 *
4124 * @returns Pointer to the page directory pointer entry in question.
4125 * @returns NULL if the page directory is not present or on an invalid page.
4126 * @param pPGM Pointer to the PGM instance data.
4127 * @param GCPtr The address.
4128 * @param ppPml4e Page Map Level-4 Entry (out)
4129 */
4130DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4131{
4132 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4133 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4134 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4135 if (pPml4e->n.u1Present)
4136 {
4137 PX86PDPT pPdpt;
4138 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4139 AssertRCReturn(rc, NULL);
4140
4141 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4142 return &pPdpt->a[iPdpt];
4143 }
4144 return NULL;
4145}
4146
4147
4148/**
4149 * Gets the page directory entry for the specified address.
4150 *
4151 * @returns The page directory entry in question.
4152 * @returns A non-present entry if the page directory is not present or on an invalid page.
4153 * @param pPGM Pointer to the PGM instance data.
4154 * @param GCPtr The address.
4155 * @param ppPml4e Page Map Level-4 Entry (out)
4156 * @param pPdpe Page directory pointer table entry (out)
4157 */
4158DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4159{
4160 X86PDEPAE ZeroPde = {0};
4161 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4162 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4163 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4164 if (pPml4e->n.u1Present)
4165 {
4166 PCX86PDPT pPdptTemp;
4167 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4168 AssertRCReturn(rc, ZeroPde);
4169
4170 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4171 *pPdpe = pPdptTemp->a[iPdpt];
4172 if (pPdptTemp->a[iPdpt].n.u1Present)
4173 {
4174 PCX86PDPAE pPD;
4175 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4176 AssertRCReturn(rc, ZeroPde);
4177
4178 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4179 return pPD->a[iPD];
4180 }
4181 }
4182
4183 return ZeroPde;
4184}
4185
4186
4187/**
4188 * Gets the page directory entry for the specified address.
4189 *
4190 * @returns The page directory entry in question.
4191 * @returns A non-present entry if the page directory is not present or on an invalid page.
4192 * @param pPGM Pointer to the PGM instance data.
4193 * @param GCPtr The address.
4194 */
4195DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4196{
4197 X86PDEPAE ZeroPde = {0};
4198 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4199 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4200 if (pGuestPml4->a[iPml4].n.u1Present)
4201 {
4202 PCX86PDPT pPdptTemp;
4203 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4204 AssertRCReturn(rc, ZeroPde);
4205
4206 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4207 if (pPdptTemp->a[iPdpt].n.u1Present)
4208 {
4209 PCX86PDPAE pPD;
4210 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4211 AssertRCReturn(rc, ZeroPde);
4212
4213 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4214 return pPD->a[iPD];
4215 }
4216 }
4217 return ZeroPde;
4218}
4219
4220
4221/**
4222 * Gets the page directory entry for the specified address.
4223 *
4224 * @returns Pointer to the page directory entry in question.
4225 * @returns NULL if the page directory is not present or on an invalid page.
4226 * @param pPGM Pointer to the PGM instance data.
4227 * @param GCPtr The address.
4228 */
4229DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4230{
4231 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4232 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4233 if (pGuestPml4->a[iPml4].n.u1Present)
4234 {
4235 PCX86PDPT pPdptTemp;
4236 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4237 AssertRCReturn(rc, NULL);
4238
4239 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4240 if (pPdptTemp->a[iPdpt].n.u1Present)
4241 {
4242 PX86PDPAE pPD;
4243 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4244 AssertRCReturn(rc, NULL);
4245
4246 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4247 return &pPD->a[iPD];
4248 }
4249 }
4250 return NULL;
4251}
4252
4253
4254/**
4255 * Gets the GUEST page directory pointer for the specified address.
4256 *
4257 * @returns The page directory in question.
4258 * @returns NULL if the page directory is not present or on an invalid page.
4259 * @param pPGM Pointer to the PGM instance data.
4260 * @param GCPtr The address.
4261 * @param ppPml4e Page Map Level-4 Entry (out)
4262 * @param pPdpe Page directory pointer table entry (out)
4263 * @param piPD Receives the index into the returned page directory
4264 */
4265DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4266{
4267 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4268 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4269 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4270 if (pPml4e->n.u1Present)
4271 {
4272 PCX86PDPT pPdptTemp;
4273 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4274 AssertRCReturn(rc, NULL);
4275
4276 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4277 *pPdpe = pPdptTemp->a[iPdpt];
4278 if (pPdptTemp->a[iPdpt].n.u1Present)
4279 {
4280 PX86PDPAE pPD;
4281 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4282 AssertRCReturn(rc, NULL);
4283
4284 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4285 return pPD;
4286 }
4287 }
4288 return 0;
4289}
4290
4291#endif /* !IN_RC */
4292
4293/**
4294 * Gets the shadow page directory, 32-bit.
4295 *
4296 * @returns Pointer to the shadow 32-bit PD.
4297 * @param pPGM Pointer to the PGM instance data.
4298 */
4299DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4300{
4301 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4302}
4303
4304
4305/**
4306 * Gets the shadow page directory entry for the specified address, 32-bit.
4307 *
4308 * @returns Shadow 32-bit PDE.
4309 * @param pPGM Pointer to the PGM instance data.
4310 * @param GCPtr The address.
4311 */
4312DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4313{
4314 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4315
4316 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4317 if (!pShwPde)
4318 {
4319 X86PDE ZeroPde = {0};
4320 return ZeroPde;
4321 }
4322 return pShwPde->a[iPd];
4323}
4324
4325
4326/**
4327 * Gets the pointer to the shadow page directory entry for the specified
4328 * address, 32-bit.
4329 *
4330 * @returns Pointer to the shadow 32-bit PDE.
4331 * @param pPGM Pointer to the PGM instance data.
4332 * @param GCPtr The address.
4333 */
4334DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4335{
4336 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4337
4338 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4339 AssertReturn(pPde, NULL);
4340 return &pPde->a[iPd];
4341}
4342
4343
4344/**
4345 * Gets the shadow page pointer table, PAE.
4346 *
4347 * @returns Pointer to the shadow PAE PDPT.
4348 * @param pPGM Pointer to the PGM instance data.
4349 */
4350DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4351{
4352 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4353}
4354
4355
4356/**
4357 * Gets the shadow page directory for the specified address, PAE.
4358 *
4359 * @returns Pointer to the shadow PD.
4360 * @param pPGM Pointer to the PGM instance data.
4361 * @param GCPtr The address.
4362 */
4363DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4364{
4365 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4366 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4367
4368 if (!pPdpt->a[iPdpt].n.u1Present)
4369 return NULL;
4370
4371 /* Fetch the pgm pool shadow descriptor. */
4372 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4373 AssertReturn(pShwPde, NULL);
4374
4375 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4376}
4377
4378
4379/**
4380 * Gets the shadow page directory for the specified address, PAE.
4381 *
4382 * @returns Pointer to the shadow PD.
4383 * @param pPGM Pointer to the PGM instance data.
4384 * @param GCPtr The address.
4385 */
4386DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4387{
4388 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4389
4390 if (!pPdpt->a[iPdpt].n.u1Present)
4391 return NULL;
4392
4393 /* Fetch the pgm pool shadow descriptor. */
4394 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4395 AssertReturn(pShwPde, NULL);
4396
4397 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4398}
4399
4400
4401/**
4402 * Gets the shadow page directory entry, PAE.
4403 *
4404 * @returns PDE.
4405 * @param pPGM Pointer to the PGM instance data.
4406 * @param GCPtr The address.
4407 */
4408DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4409{
4410 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4411
4412 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4413 if (!pShwPde)
4414 {
4415 X86PDEPAE ZeroPde = {0};
4416 return ZeroPde;
4417 }
4418 return pShwPde->a[iPd];
4419}
4420
4421
4422/**
4423 * Gets the pointer to the shadow page directory entry for an address, PAE.
4424 *
4425 * @returns Pointer to the PDE.
4426 * @param pPGM Pointer to the PGM instance data.
4427 * @param GCPtr The address.
4428 */
4429DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4430{
4431 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4432
4433 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4434 AssertReturn(pPde, NULL);
4435 return &pPde->a[iPd];
4436}
4437
4438#ifndef IN_RC
4439
4440/**
4441 * Gets the shadow page map level-4 pointer.
4442 *
4443 * @returns Pointer to the shadow PML4.
4444 * @param pPGM Pointer to the PGM instance data.
4445 */
4446DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4447{
4448 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4449}
4450
4451
4452/**
4453 * Gets the shadow page map level-4 entry for the specified address.
4454 *
4455 * @returns The entry.
4456 * @param pPGM Pointer to the PGM instance data.
4457 * @param GCPtr The address.
4458 */
4459DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4460{
4461 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4462 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4463
4464 if (!pShwPml4)
4465 {
4466 X86PML4E ZeroPml4e = {0};
4467 return ZeroPml4e;
4468 }
4469 return pShwPml4->a[iPml4];
4470}
4471
4472
4473/**
4474 * Gets the pointer to the specified shadow page map level-4 entry.
4475 *
4476 * @returns The entry.
4477 * @param pPGM Pointer to the PGM instance data.
4478 * @param iPml4 The PML4 index.
4479 */
4480DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4481{
4482 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4483 if (!pShwPml4)
4484 return NULL;
4485 return &pShwPml4->a[iPml4];
4486}
4487
4488
4489/**
4490 * Gets the GUEST page directory pointer for the specified address.
4491 *
4492 * @returns The page directory in question.
4493 * @returns NULL if the page directory is not present or on an invalid page.
4494 * @param pPGM Pointer to the PGM instance data.
4495 * @param GCPtr The address.
4496 * @param piPD Receives the index into the returned page directory
4497 */
4498DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4499{
4500 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4501 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4502 if (pGuestPml4->a[iPml4].n.u1Present)
4503 {
4504 PCX86PDPT pPdptTemp;
4505 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4506 AssertRCReturn(rc, NULL);
4507
4508 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4509 if (pPdptTemp->a[iPdpt].n.u1Present)
4510 {
4511 PX86PDPAE pPD;
4512 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4513 AssertRCReturn(rc, NULL);
4514
4515 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4516 return pPD;
4517 }
4518 }
4519 return NULL;
4520}
4521
4522#endif /* !IN_RC */
4523
4524/**
4525 * Gets the page state for a physical handler.
4526 *
4527 * @returns The physical handler page state.
4528 * @param pCur The physical handler in question.
4529 */
4530DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4531{
4532 switch (pCur->enmType)
4533 {
4534 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4535 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4536
4537 case PGMPHYSHANDLERTYPE_MMIO:
4538 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4539 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4540
4541 default:
4542 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4543 }
4544}
4545
4546
4547/**
4548 * Gets the page state for a virtual handler.
4549 *
4550 * @returns The virtual handler page state.
4551 * @param pCur The virtual handler in question.
4552 * @remarks This should never be used on a hypervisor access handler.
4553 */
4554DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4555{
4556 switch (pCur->enmType)
4557 {
4558 case PGMVIRTHANDLERTYPE_WRITE:
4559 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4560 case PGMVIRTHANDLERTYPE_ALL:
4561 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4562 default:
4563 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4564 }
4565}
4566
4567
4568/**
4569 * Clears one physical page of a virtual handler
4570 *
4571 * @param pPGM Pointer to the PGM instance.
4572 * @param pCur Virtual handler structure
4573 * @param iPage Physical page index
4574 *
4575 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4576 * need to care about other handlers in the same page.
4577 */
4578DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4579{
4580 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4581
4582 /*
4583 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4584 */
4585#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4586 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4587 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4588 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4589#endif
4590 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4591 {
4592 /* We're the head of the alias chain. */
4593 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4594#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4595 AssertReleaseMsg(pRemove != NULL,
4596 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4597 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4598 AssertReleaseMsg(pRemove == pPhys2Virt,
4599 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4600 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4601 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4602 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4603#endif
4604 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4605 {
4606 /* Insert the next list in the alias chain into the tree. */
4607 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4608#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4609 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4610 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4611 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4612#endif
4613 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4614 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4615 AssertRelease(fRc);
4616 }
4617 }
4618 else
4619 {
4620 /* Locate the previous node in the alias chain. */
4621 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4622#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4623 AssertReleaseMsg(pPrev != pPhys2Virt,
4624 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4625 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4626#endif
4627 for (;;)
4628 {
4629 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4630 if (pNext == pPhys2Virt)
4631 {
4632 /* unlink. */
4633 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4634 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4635 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4636 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4637 else
4638 {
4639 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4640 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4641 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4642 }
4643 break;
4644 }
4645
4646 /* next */
4647 if (pNext == pPrev)
4648 {
4649#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4650 AssertReleaseMsg(pNext != pPrev,
4651 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4652 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4653#endif
4654 break;
4655 }
4656 pPrev = pNext;
4657 }
4658 }
4659 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4660 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4661 pPhys2Virt->offNextAlias = 0;
4662 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4663
4664 /*
4665 * Clear the ram flags for this page.
4666 */
4667 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4668 AssertReturnVoid(pPage);
4669 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4670}
4671
4672
4673/**
4674 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4675 *
4676 * @returns Pointer to the shadow page structure.
4677 * @param pPool The pool.
4678 * @param idx The pool page index.
4679 */
4680DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4681{
4682 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4683 return &pPool->aPages[idx];
4684}
4685
4686
4687#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4688/**
4689 * Clear references to guest physical memory.
4690 *
4691 * @param pPool The pool.
4692 * @param pPoolPage The pool page.
4693 * @param pPhysPage The physical guest page tracking structure.
4694 */
4695DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4696{
4697 /*
4698 * Just deal with the simple case here.
4699 */
4700# ifdef LOG_ENABLED
4701 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4702# endif
4703 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4704 if (cRefs == 1)
4705 {
4706 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4707 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4708 }
4709 else
4710 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4711 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4712}
4713#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4714
4715
4716#ifdef PGMPOOL_WITH_CACHE
4717/**
4718 * Moves the page to the head of the age list.
4719 *
4720 * This is done when the cached page is used in one way or another.
4721 *
4722 * @param pPool The pool.
4723 * @param pPage The cached page.
4724 */
4725DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4726{
4727 PVM pVM = pPool->CTX_SUFF(pVM);
4728 pgmLock(pVM);
4729
4730 /*
4731 * Move to the head of the age list.
4732 */
4733 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4734 {
4735 /* unlink */
4736 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4737 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4738 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4739 else
4740 pPool->iAgeTail = pPage->iAgePrev;
4741
4742 /* insert at head */
4743 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4744 pPage->iAgeNext = pPool->iAgeHead;
4745 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4746 pPool->iAgeHead = pPage->idx;
4747 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4748 }
4749 pgmUnlock(pVM);
4750}
4751#endif /* PGMPOOL_WITH_CACHE */
4752
4753/**
4754 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4755 *
4756 * @param pVM VM Handle.
4757 * @param pPage PGM pool page
4758 */
4759DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4760{
4761 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4762 ASMAtomicIncU32(&pPage->cLocked);
4763}
4764
4765
4766/**
4767 * Unlocks a page to allow flushing again
4768 *
4769 * @param pVM VM Handle.
4770 * @param pPage PGM pool page
4771 */
4772DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4773{
4774 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4775 Assert(pPage->cLocked);
4776 ASMAtomicDecU32(&pPage->cLocked);
4777}
4778
4779
4780/**
4781 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4782 *
4783 * @returns VBox status code.
4784 * @param pPage PGM pool page
4785 */
4786DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4787{
4788 if (pPage->cLocked)
4789 {
4790 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4791 if (pPage->cModifications)
4792 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4793 return true;
4794 }
4795 return false;
4796}
4797
4798/**
4799 * Tells if mappings are to be put into the shadow page table or not
4800 *
4801 * @returns boolean result
4802 * @param pVM VM handle.
4803 */
4804DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4805{
4806#ifdef IN_RING0
4807 /* There are no mappings in VT-x and AMD-V mode. */
4808 Assert(pPGM->fDisableMappings);
4809 return false;
4810#else
4811 return !pPGM->fDisableMappings;
4812#endif
4813}
4814
4815/** @} */
4816
4817#endif
4818
4819
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette