VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 23458

Last change on this file since 23458 was 23458, checked in by vboxsync, 16 years ago

PGMPAGE: HCPhys and idPage migration work, part 2.
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1/* $Id: PGMInternal.h 23458 2009-10-01 01:12:59Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#if 0 /* disabled again while debugging */
72#ifndef IN_RC
73# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
74#endif
75#endif
76
77/**
78 * Sync N pages instead of a whole page table
79 */
80#define PGM_SYNC_N_PAGES
81
82/**
83 * Number of pages to sync during a page fault
84 *
85 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
86 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
87 *
88 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
89 * world switch overhead, so let's sync more.
90 */
91# ifdef IN_RING0
92/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
93 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
94 * but ~5% fewer faults.
95 */
96# define PGM_SYNC_NR_PAGES 32
97#else
98# define PGM_SYNC_NR_PAGES 8
99#endif
100
101/**
102 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
103 */
104#define PGM_MAX_PHYSCACHE_ENTRIES 64
105#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
106
107/** @def PGMPOOL_WITH_CACHE
108 * Enable agressive caching using the page pool.
109 *
110 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
111 */
112#define PGMPOOL_WITH_CACHE
113
114/** @def PGMPOOL_WITH_MIXED_PT_CR3
115 * When defined, we'll deal with 'uncachable' pages.
116 */
117#ifdef PGMPOOL_WITH_CACHE
118# define PGMPOOL_WITH_MIXED_PT_CR3
119#endif
120
121/** @def PGMPOOL_WITH_MONITORING
122 * Monitor the guest pages which are shadowed.
123 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
124 * be enabled as well.
125 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
126 */
127#ifdef PGMPOOL_WITH_CACHE
128# define PGMPOOL_WITH_MONITORING
129#endif
130
131/** @def PGMPOOL_WITH_GCPHYS_TRACKING
132 * Tracking the of shadow pages mapping guest physical pages.
133 *
134 * This is very expensive, the current cache prototype is trying to figure out
135 * whether it will be acceptable with an agressive caching policy.
136 */
137#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
138# define PGMPOOL_WITH_GCPHYS_TRACKING
139#endif
140
141/** @def PGMPOOL_WITH_USER_TRACKING
142 * Tracking users of shadow pages. This is required for the linking of shadow page
143 * tables and physical guest addresses.
144 */
145#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
146# define PGMPOOL_WITH_USER_TRACKING
147#endif
148
149/** @def PGMPOOL_CFG_MAX_GROW
150 * The maximum number of pages to add to the pool in one go.
151 */
152#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
153
154/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
155 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
156 */
157#ifdef VBOX_STRICT
158# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
159#endif
160
161/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
162 * Enables the experimental lazy page allocation code. */
163/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED 6
213#define PGM_TYPE_EPT 7
214#define PGM_TYPE_MAX PGM_TYPE_EPT
215/** @} */
216
217/** Macro for checking if the guest is using paging.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_PAGING(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_32BIT \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227/** Macro for checking if the guest supports the NX bit.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_NX(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_PAE \
234 && (uShwType) != PGM_TYPE_NESTED \
235 && (uShwType) != PGM_TYPE_EPT)
236
237
238/** @def PGM_HCPHYS_2_PTR
239 * Maps a HC physical page pool address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM handle.
243 * @param HCPhys The HC physical address to map to a virtual one.
244 * @param ppv Where to store the virtual address. No need to cast this.
245 *
246 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
247 * small page window employeed by that function. Be careful.
248 * @remark There is no need to assert on the result.
249 */
250#ifdef IN_RC
251# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
252 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
253#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
258 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_HCPHYS_2_PTR_BY_PGM
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pPGM The PGM instance data.
266 * @param HCPhys The HC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
275 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
276#else
277# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
278 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
279#endif
280
281/** @def PGM_GCPHYS_2_PTR
282 * Maps a GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The VM handle.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290 * small page window employeed by that function. Be careful.
291 * @remark There is no need to assert on the result.
292 */
293#ifdef IN_RC
294# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
295 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
296#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
297# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
301 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pPGM Pointer to the PGM instance data.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
317# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
318 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
321 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
322#endif
323
324/** @def PGM_GCPHYS_2_PTR_EX
325 * Maps a unaligned GC physical page address to a virtual address.
326 *
327 * @returns VBox status code.
328 * @param pVM The VM handle.
329 * @param GCPhys The GC physical address to map to a virtual one.
330 * @param ppv Where to store the virtual address. No need to cast this.
331 *
332 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
333 * small page window employeed by that function. Be careful.
334 * @remark There is no need to assert on the result.
335 */
336#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
339#else
340# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
341 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
342#endif
343
344/** @def PGM_INVL_PG
345 * Invalidates a page.
346 *
347 * @param pVCpu The VMCPU handle.
348 * @param GCVirt The virtual address of the page to invalidate.
349 */
350#ifdef IN_RC
351# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
352#elif defined(IN_RING0)
353# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354#else
355# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356#endif
357
358/** @def PGM_INVL_PG_ALL_VCPU
359 * Invalidates a page on all VCPUs
360 *
361 * @param pVM The VM handle.
362 * @param GCVirt The virtual address of the page to invalidate.
363 */
364#ifdef IN_RC
365# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
366#elif defined(IN_RING0)
367# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368#else
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370#endif
371
372/** @def PGM_INVL_BIG_PG
373 * Invalidates a 4MB page directory entry.
374 *
375 * @param pVCpu The VMCPU handle.
376 * @param GCVirt The virtual address within the page directory to invalidate.
377 */
378#ifdef IN_RC
379# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_VCPU_TLBS()
387 * Invalidates the TLBs of the specified VCPU
388 *
389 * @param pVCpu The VMCPU handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_ALL_VCPU_TLBS()
400 * Invalidates the TLBs of all VCPUs
401 *
402 * @param pVM The VM handle.
403 */
404#ifdef IN_RC
405# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408#else
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410#endif
411
412/** Size of the GCPtrConflict array in PGMMAPPING.
413 * @remarks Must be a power of two. */
414#define PGMMAPPING_CONFLICT_MAX 8
415
416/**
417 * Structure for tracking GC Mappings.
418 *
419 * This structure is used by linked list in both GC and HC.
420 */
421typedef struct PGMMAPPING
422{
423 /** Pointer to next entry. */
424 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425 /** Pointer to next entry. */
426 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427 /** Pointer to next entry. */
428 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429 /** Indicate whether this entry is finalized. */
430 bool fFinalized;
431 /** Start Virtual address. */
432 RTGCPTR GCPtr;
433 /** Last Virtual address (inclusive). */
434 RTGCPTR GCPtrLast;
435 /** Range size (bytes). */
436 RTGCPTR cb;
437 /** Pointer to relocation callback function. */
438 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439 /** User argument to the callback. */
440 R3PTRTYPE(void *) pvUser;
441 /** Mapping description / name. For easing debugging. */
442 R3PTRTYPE(const char *) pszDesc;
443 /** Last 8 addresses that caused conflicts. */
444 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445 /** Number of conflicts for this hypervisor mapping. */
446 uint32_t cConflicts;
447 /** Number of page tables. */
448 uint32_t cPTs;
449
450 /** Array of page table mapping data. Each entry
451 * describes one page table. The array can be longer
452 * than the declared length.
453 */
454 struct
455 {
456 /** The HC physical address of the page table. */
457 RTHCPHYS HCPhysPT;
458 /** The HC physical address of the first PAE page table. */
459 RTHCPHYS HCPhysPaePT0;
460 /** The HC physical address of the second PAE page table. */
461 RTHCPHYS HCPhysPaePT1;
462 /** The HC virtual address of the 32-bit page table. */
463 R3PTRTYPE(PX86PT) pPTR3;
464 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466 /** The RC virtual address of the 32-bit page table. */
467 RCPTRTYPE(PX86PT) pPTRC;
468 /** The RC virtual address of the two PAE page table. */
469 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470 /** The R0 virtual address of the 32-bit page table. */
471 R0PTRTYPE(PX86PT) pPTR0;
472 /** The R0 virtual address of the two PAE page table. */
473 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474 } aPTs[1];
475} PGMMAPPING;
476/** Pointer to structure for tracking GC Mappings. */
477typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480/**
481 * Physical page access handler structure.
482 *
483 * This is used to keep track of physical address ranges
484 * which are being monitored in some kind of way.
485 */
486typedef struct PGMPHYSHANDLER
487{
488 AVLROGCPHYSNODECORE Core;
489 /** Access type. */
490 PGMPHYSHANDLERTYPE enmType;
491 /** Number of pages to update. */
492 uint32_t cPages;
493 /** Pointer to R3 callback function. */
494 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495 /** User argument for R3 handlers. */
496 R3PTRTYPE(void *) pvUserR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499 /** User argument for R0 handlers. */
500 R0PTRTYPE(void *) pvUserR0;
501 /** Pointer to RC callback function. */
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503 /** User argument for RC handlers. */
504 RCPTRTYPE(void *) pvUserRC;
505 /** Description / Name. For easing debugging. */
506 R3PTRTYPE(const char *) pszDesc;
507#ifdef VBOX_WITH_STATISTICS
508 /** Profiling of this handler. */
509 STAMPROFILE Stat;
510#endif
511} PGMPHYSHANDLER;
512/** Pointer to a physical page access handler structure. */
513typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516/**
517 * Cache node for the physical addresses covered by a virtual handler.
518 */
519typedef struct PGMPHYS2VIRTHANDLER
520{
521 /** Core node for the tree based on physical ranges. */
522 AVLROGCPHYSNODECORE Core;
523 /** Offset from this struct to the PGMVIRTHANDLER structure. */
524 int32_t offVirtHandler;
525 /** Offset of the next alias relative to this one.
526 * Bit 0 is used for indicating whether we're in the tree.
527 * Bit 1 is used for indicating that we're the head node.
528 */
529 int32_t offNextAlias;
530} PGMPHYS2VIRTHANDLER;
531/** Pointer to a phys to virtual handler structure. */
532typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535 * node is in the tree. */
536#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538 * node is in the head of an alias chain.
539 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545/**
546 * Virtual page access handler structure.
547 *
548 * This is used to keep track of virtual address ranges
549 * which are being monitored in some kind of way.
550 */
551typedef struct PGMVIRTHANDLER
552{
553 /** Core node for the tree based on virtual ranges. */
554 AVLROGCPTRNODECORE Core;
555 /** Size of the range (in bytes). */
556 RTGCPTR cb;
557 /** Number of cache pages. */
558 uint32_t cPages;
559 /** Access type. */
560 PGMVIRTHANDLERTYPE enmType;
561 /** Pointer to the RC callback function. */
562 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563#if HC_ARCH_BITS == 64
564 RTRCPTR padding;
565#endif
566 /** Pointer to the R3 callback function for invalidation. */
567 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568 /** Pointer to the R3 callback function. */
569 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570 /** Description / Name. For easing debugging. */
571 R3PTRTYPE(const char *) pszDesc;
572#ifdef VBOX_WITH_STATISTICS
573 /** Profiling of this handler. */
574 STAMPROFILE Stat;
575#endif
576 /** Array of cached physical addresses for the monitored ranged. */
577 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578} PGMVIRTHANDLER;
579/** Pointer to a virtual page access handler structure. */
580typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583/**
584 * Page type.
585 *
586 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587 * @remarks This is used in the saved state, so changes to it requires bumping
588 * the saved state version.
589 * @todo So, convert to \#defines!
590 */
591typedef enum PGMPAGETYPE
592{
593 /** The usual invalid zero entry. */
594 PGMPAGETYPE_INVALID = 0,
595 /** RAM page. (RWX) */
596 PGMPAGETYPE_RAM,
597 /** MMIO2 page. (RWX) */
598 PGMPAGETYPE_MMIO2,
599 /** MMIO2 page aliased over an MMIO page. (RWX)
600 * See PGMHandlerPhysicalPageAlias(). */
601 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602 /** Shadowed ROM. (RWX) */
603 PGMPAGETYPE_ROM_SHADOW,
604 /** ROM page. (R-X) */
605 PGMPAGETYPE_ROM,
606 /** MMIO page. (---) */
607 PGMPAGETYPE_MMIO,
608 /** End of valid entries. */
609 PGMPAGETYPE_END
610} PGMPAGETYPE;
611AssertCompile(PGMPAGETYPE_END <= 7);
612
613/** @name Page type predicates.
614 * @{ */
615#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620/** @} */
621
622#if 0 /* disabled temporarily */
623/** Enables the new structure layout.
624 * Some bits are better others are not. */
625#define PGM_PAGE_WITH_PAGEID_IN_HCPHYS
626
627/** When non-zero, PGMPAGE is packed. When zero some of the important fields
628 * are expaned to 8-bit size to allow the compiler to use byte access. */
629#define PGM_PAGE_PACKED 0
630#endif
631
632
633/**
634 * A Physical Guest Page tracking structure.
635 *
636 * The format of this structure is complicated because we have to fit a lot
637 * of information into as few bits as possible. The format is also subject
638 * to change (there is one comming up soon). Which means that for we'll be
639 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
640 * accesses to the structure.
641 */
642typedef struct PGMPAGE
643{
644#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
645 /** The physical address and the Page ID. */
646 RTHCPHYS HCPhysAndPageID;
647 /** The page state. */
648 uint32_t u2StateY : (PGM_PAGE_PACKED ? 2 : 8);
649 /** The page type (PGMPAGETYPE). */
650 uint32_t u3TypeY : (PGM_PAGE_PACKED ? 3 : 8);
651 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
652 uint32_t u2HandlerPhysStateY : (PGM_PAGE_PACKED ? 2 : 8);
653 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
654 uint32_t u2HandlerVirtStateY : 2;
655 /** Flag indicating that a write monitored page was written to when set. */
656 uint32_t fWrittenToY : 1;
657 /** For later. */
658 uint32_t afSomethingElse0 : (PGM_PAGE_PACKED ? 17+5 : 5);
659 /** Usage tracking (page pool). */
660 uint16_t u16TrackingY;
661 /** The number of read locks on this page. */
662 uint8_t cReadLocksY;
663 /** The number of write locks on this page. */
664 uint8_t cWriteLocksY;
665#else
666 /** The physical address.
667 * This will later contain the page id in the unused bits. */
668 RTHCPHYS HCPhysY;
669 /** The page state. */
670 uint32_t u2StateY : 2;
671 /** Flag indicating that a write monitored page was written to when set. */
672 uint32_t fWrittenToY : 1;
673 /** For later. */
674 uint32_t fSomethingElse0 : 1;
675 /** The Page ID. */
676 uint32_t idPageY : 28;
677 /** The page type (PGMPAGETYPE). */
678 uint32_t u3TypeY : 3;
679 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
680 uint32_t u2HandlerPhysStateY : 2;
681 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
682 uint32_t u2HandlerVirtStateY : 2;
683 /** For later. */
684 uint32_t fSomethingElse1 : 1;
685 /** The number of read locks on this page. */
686 uint32_t cReadLocksY : 4;
687 /** The number of write locks on this page. */
688 uint32_t cWriteLocksY : 4;
689 /** Usage tracking (page pool). */
690 uint32_t u16TrackingY : 16;
691#endif
692} PGMPAGE;
693AssertCompileSize(PGMPAGE, 16);
694/** Pointer to a physical guest page. */
695typedef PGMPAGE *PPGMPAGE;
696/** Pointer to a const physical guest page. */
697typedef const PGMPAGE *PCPGMPAGE;
698/** Pointer to a physical guest page pointer. */
699typedef PPGMPAGE *PPPGMPAGE;
700
701
702/**
703 * Clears the page structure.
704 * @param pPage Pointer to the physical guest page tracking structure.
705 */
706#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
707# define PGM_PAGE_CLEAR(pPage) \
708 do { \
709 (pPage)->HCPhysAndPageID = 0; \
710 (pPage)->u2StateY = 0; \
711 (pPage)->fWrittenToY = 0; \
712 (pPage)->afSomethingElse0 = 0; \
713 (pPage)->u3TypeY = 0; \
714 (pPage)->u2HandlerPhysStateY = 0; \
715 (pPage)->u2HandlerVirtStateY = 0; \
716 (pPage)->u16TrackingY = 0; \
717 (pPage)->cReadLocksY = 0; \
718 (pPage)->cWriteLocksY = 0; \
719 } while (0)
720#else
721# define PGM_PAGE_CLEAR(pPage) \
722 do { \
723 (pPage)->HCPhysY = 0; \
724 (pPage)->u2StateY = 0; \
725 (pPage)->fWrittenToY = 0; \
726 (pPage)->fSomethingElse0 = 0; \
727 (pPage)->idPageY = 0; \
728 (pPage)->u3TypeY = 0; \
729 (pPage)->u2HandlerPhysStateY = 0; \
730 (pPage)->u2HandlerVirtStateY = 0; \
731 (pPage)->fSomethingElse1 = 0; \
732 (pPage)->cReadLocksY = 0; \
733 (pPage)->cWriteLocksY = 0; \
734 (pPage)->u16TrackingY = 0; \
735 } while (0)
736#endif
737
738/**
739 * Initializes the page structure.
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
743# define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
744 do { \
745 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
746 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
747 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
748 (pPage)->u2StateY = (_uState); \
749 (pPage)->fWrittenToY = 0; \
750 (pPage)->afSomethingElse0 = 0; \
751 (pPage)->u3TypeY = (_uType); \
752 (pPage)->u2HandlerPhysStateY = 0; \
753 (pPage)->u2HandlerVirtStateY = 0; \
754 (pPage)->u16TrackingY = 0; \
755 (pPage)->cReadLocksY = 0; \
756 (pPage)->cWriteLocksY = 0; \
757 } while (0)
758#else
759# define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760 do { \
761 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763 (pPage)->HCPhysY = SetHCPhysTmp; \
764 (pPage)->u2StateY = (_uState); \
765 (pPage)->fWrittenToY = 0; \
766 (pPage)->fSomethingElse0 = 0; \
767 (pPage)->idPageY = (_idPage); \
768 (pPage)->u3TypeY = (_uType); \
769 (pPage)->u2HandlerPhysStateY = 0; \
770 (pPage)->u2HandlerVirtStateY = 0; \
771 (pPage)->fSomethingElse1 = 0; \
772 (pPage)->cReadLocksY = 0; \
773 (pPage)->cWriteLocksY = 0; \
774 (pPage)->u16TrackingY = 0; \
775 } while (0)
776#endif
777
778/**
779 * Initializes the page structure of a ZERO page.
780 * @param pPage Pointer to the physical guest page tracking structure.
781 * @param pVM The VM handle (for getting the zero page address).
782 * @param uType The page type (PGMPAGETYPE).
783 */
784#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
785 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
786
787
788/** @name The Page state, PGMPAGE::u2StateY.
789 * @{ */
790/** The zero page.
791 * This is a per-VM page that's never ever mapped writable. */
792#define PGM_PAGE_STATE_ZERO 0
793/** A allocated page.
794 * This is a per-VM page allocated from the page pool (or wherever
795 * we get MMIO2 pages from if the type is MMIO2).
796 */
797#define PGM_PAGE_STATE_ALLOCATED 1
798/** A allocated page that's being monitored for writes.
799 * The shadow page table mappings are read-only. When a write occurs, the
800 * fWrittenTo member is set, the page remapped as read-write and the state
801 * moved back to allocated. */
802#define PGM_PAGE_STATE_WRITE_MONITORED 2
803/** The page is shared, aka. copy-on-write.
804 * This is a page that's shared with other VMs. */
805#define PGM_PAGE_STATE_SHARED 3
806/** @} */
807
808
809/**
810 * Gets the page state.
811 * @returns page state (PGM_PAGE_STATE_*).
812 * @param pPage Pointer to the physical guest page tracking structure.
813 */
814#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateY )
815
816/**
817 * Sets the page state.
818 * @param pPage Pointer to the physical guest page tracking structure.
819 * @param _uState The new page state.
820 */
821#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->u2StateY = (_uState); } while (0)
822
823
824/**
825 * Gets the host physical address of the guest page.
826 * @returns host physical address (RTHCPHYS).
827 * @param pPage Pointer to the physical guest page tracking structure.
828 */
829#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
830# define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
831#else
832# define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysY )
833#endif
834
835/**
836 * Sets the host physical address of the guest page.
837 * @param pPage Pointer to the physical guest page tracking structure.
838 * @param _HCPhys The new host physical address.
839 */
840#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
841#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
842 do { \
843 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
844 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
845 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
846 | (SetHCPhysTmp << (28-12)); \
847 } while (0)
848#else
849# define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
850 do { \
851 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
852 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
853 (pPage)->HCPhysY = SetHCPhysTmp; \
854 } while (0)
855#endif
856
857/**
858 * Get the Page ID.
859 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
860 * @param pPage Pointer to the physical guest page tracking structure.
861 */
862#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
863# define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
864#else
865# define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageY )
866#endif
867
868/**
869 * Sets the Page ID.
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
873# define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
874 do { \
875 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
876 | ((_idPage) & UINT32_C(0x0fffffff)); \
877 } while (0)
878#else
879# define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
880 do { \
881 (pPage)->idPageY = (_idPage); \
882 } while (0)
883#endif
884
885/**
886 * Get the Chunk ID.
887 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
888 * @param pPage Pointer to the physical guest page tracking structure.
889 */
890#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
891# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) >> GMM_CHUNKID_SHIFT )
892#else
893# define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageY >> GMM_CHUNKID_SHIFT )
894#endif
895
896/**
897 * Get the index of the page within the allocation chunk.
898 * @returns The page index.
899 * @param pPage Pointer to the physical guest page tracking structure.
900 */
901#ifdef PGM_PAGE_WITH_PAGEID_IN_HCPHYS
902# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
903#else
904# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageY & GMM_PAGEID_IDX_MASK )
905#endif
906
907
908/**
909 * Gets the page type.
910 * @returns The page type.
911 * @param pPage Pointer to the physical guest page tracking structure.
912 */
913#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3TypeY
914
915/**
916 * Sets the page type.
917 * @param pPage Pointer to the physical guest page tracking structure.
918 * @param _enmType The new page type (PGMPAGETYPE).
919 */
920#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->u3TypeY = (_enmType); } while (0)
921
922/**
923 * Checks if the page is marked for MMIO.
924 * @returns true/false.
925 * @param pPage Pointer to the physical guest page tracking structure.
926 */
927#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3TypeY == PGMPAGETYPE_MMIO )
928
929/**
930 * Checks if the page is backed by the ZERO page.
931 * @returns true/false.
932 * @param pPage Pointer to the physical guest page tracking structure.
933 */
934#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateY == PGM_PAGE_STATE_ZERO )
935
936/**
937 * Checks if the page is backed by a SHARED page.
938 * @returns true/false.
939 * @param pPage Pointer to the physical guest page tracking structure.
940 */
941#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateY == PGM_PAGE_STATE_SHARED )
942
943
944/**
945 * Marks the paget as written to (for GMM change monitoring).
946 * @param pPage Pointer to the physical guest page tracking structure.
947 */
948#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToY = 1; } while (0)
949
950/**
951 * Clears the written-to indicator.
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToY = 0; } while (0)
955
956/**
957 * Checks if the page was marked as written-to.
958 * @returns true/false.
959 * @param pPage Pointer to the physical guest page tracking structure.
960 */
961#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToY )
962
963
964/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
965 *
966 * @remarks The values are assigned in order of priority, so we can calculate
967 * the correct state for a page with different handlers installed.
968 * @{ */
969/** No handler installed. */
970#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
971/** Monitoring is temporarily disabled. */
972#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
973/** Write access is monitored. */
974#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
975/** All access is monitored. */
976#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
977/** @} */
978
979/**
980 * Gets the physical access handler state of a page.
981 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 */
984#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
985 ( (pPage)->u2HandlerPhysStateY )
986
987/**
988 * Sets the physical access handler state of a page.
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param _uState The new state value.
991 */
992#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
993 do { (pPage)->u2HandlerPhysStateY = (_uState); } while (0)
994
995/**
996 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
997 * @returns true/false
998 * @param pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1001 ( (pPage)->u2HandlerPhysStateY != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1002
1003/**
1004 * Checks if the page has any active physical access handlers.
1005 * @returns true/false
1006 * @param pPage Pointer to the physical guest page tracking structure.
1007 */
1008#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1009 ( (pPage)->u2HandlerPhysStateY >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1010
1011
1012/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1013 *
1014 * @remarks The values are assigned in order of priority, so we can calculate
1015 * the correct state for a page with different handlers installed.
1016 * @{ */
1017/** No handler installed. */
1018#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1019/* 1 is reserved so the lineup is identical with the physical ones. */
1020/** Write access is monitored. */
1021#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1022/** All access is monitored. */
1023#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1024/** @} */
1025
1026/**
1027 * Gets the virtual access handler state of a page.
1028 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1029 * @param pPage Pointer to the physical guest page tracking structure.
1030 */
1031#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) \
1032 ( (pPage)->u2HandlerVirtStateY )
1033
1034/**
1035 * Sets the virtual access handler state of a page.
1036 * @param pPage Pointer to the physical guest page tracking structure.
1037 * @param _uState The new state value.
1038 */
1039#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1040 do { (pPage)->u2HandlerVirtStateY = (_uState); } while (0)
1041
1042/**
1043 * Checks if the page has any virtual access handlers.
1044 * @returns true/false
1045 * @param pPage Pointer to the physical guest page tracking structure.
1046 */
1047#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1048 ( (pPage)->u2HandlerVirtStateY != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1049
1050/**
1051 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1052 * virtual handlers.
1053 * @returns true/false
1054 * @param pPage Pointer to the physical guest page tracking structure.
1055 */
1056#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1057 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1058
1059
1060
1061/**
1062 * Checks if the page has any access handlers, including temporarily disabled ones.
1063 * @returns true/false
1064 * @param pPage Pointer to the physical guest page tracking structure.
1065 */
1066#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1067 ( (pPage)->u2HandlerPhysStateY != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1068 || (pPage)->u2HandlerVirtStateY != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1069
1070/**
1071 * Checks if the page has any active access handlers.
1072 * @returns true/false
1073 * @param pPage Pointer to the physical guest page tracking structure.
1074 */
1075#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1076 ( (pPage)->u2HandlerPhysStateY >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1077 || (pPage)->u2HandlerVirtStateY >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1078
1079/**
1080 * Checks if the page has any active access handlers catching all accesses.
1081 * @returns true/false
1082 * @param pPage Pointer to the physical guest page tracking structure.
1083 */
1084#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1085 ( (pPage)->u2HandlerPhysStateY == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1086 || (pPage)->u2HandlerVirtStateY == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1087
1088
1089/** @def PGM_PAGE_GET_TRACKING
1090 * Gets the packed shadow page pool tracking data associated with a guest page.
1091 * @returns uint16_t containing the data.
1092 * @param pPage Pointer to the physical guest page tracking structure.
1093 */
1094#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1095
1096/** @def PGM_PAGE_SET_TRACKING
1097 * Sets the packed shadow page pool tracking data associated with a guest page.
1098 * @param pPage Pointer to the physical guest page tracking structure.
1099 * @param u16TrackingData The tracking data to store.
1100 */
1101#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1102 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1103
1104/** @def PGM_PAGE_GET_TD_CREFS
1105 * Gets the @a cRefs tracking data member.
1106 * @returns cRefs.
1107 * @param pPage Pointer to the physical guest page tracking structure.
1108 */
1109#define PGM_PAGE_GET_TD_CREFS(pPage) \
1110 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1111
1112/** @def PGM_PAGE_GET_TD_IDX
1113 * Gets the @a idx tracking data member.
1114 * @returns idx.
1115 * @param pPage Pointer to the physical guest page tracking structure.
1116 */
1117#define PGM_PAGE_GET_TD_IDX(pPage) \
1118 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1119
1120
1121
1122/**
1123 * Per page live save tracking data.
1124 */
1125typedef struct PGMLIVESAVEPAGE
1126{
1127 /** The pass number where this page was last saved. */
1128 uint32_t uPassSaved;
1129 /** Number of times it has been dirtied. */
1130 uint32_t cDirtied : 24;
1131 /** Whether it is currently dirty. */
1132 uint32_t fDirty : 1;
1133 /** Ignore the page.
1134 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1135 * deal with these after pausing the VM and DevPCI have said it bit about
1136 * remappings. */
1137 uint32_t fIgnore : 1;
1138 /** Was a ZERO page last time around. */
1139 uint32_t fZero : 1;
1140 /** Was a SHARED page last time around. */
1141 uint32_t fShared : 1;
1142 /** Whether the page is/was write monitored in a previous pass. */
1143 uint32_t fWriteMonitored : 1;
1144 /** Whether the page is/was write monitored earlier in this pass. */
1145 uint32_t fWriteMonitoredJustNow : 1;
1146 /** Bits reserved for future use. */
1147 uint32_t u2Reserved : 2;
1148} PGMLIVESAVEPAGE;
1149AssertCompileSize(PGMLIVESAVEPAGE, 8);
1150/** Pointer to the per page live save tracking data. */
1151typedef PGMLIVESAVEPAGE *PPGMLIVESAVEPAGE;
1152
1153/** The max value of PGMLIVESAVEPAGE::cDirtied. */
1154#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1155
1156
1157/**
1158 * Ram range for GC Phys to HC Phys conversion.
1159 *
1160 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1161 * conversions too, but we'll let MM handle that for now.
1162 *
1163 * This structure is used by linked lists in both GC and HC.
1164 */
1165typedef struct PGMRAMRANGE
1166{
1167 /** Start of the range. Page aligned. */
1168 RTGCPHYS GCPhys;
1169 /** Size of the range. (Page aligned of course). */
1170 RTGCPHYS cb;
1171 /** Pointer to the next RAM range - for R3. */
1172 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1173 /** Pointer to the next RAM range - for R0. */
1174 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1175 /** Pointer to the next RAM range - for RC. */
1176 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1177 /** PGM_RAM_RANGE_FLAGS_* flags. */
1178 uint32_t fFlags;
1179 /** Last address in the range (inclusive). Page aligned (-1). */
1180 RTGCPHYS GCPhysLast;
1181 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1182 R3PTRTYPE(void *) pvR3;
1183 /** Live save per page tracking data. */
1184 R3PTRTYPE(PPGMLIVESAVEPAGE) paLSPages;
1185 /** The range description. */
1186 R3PTRTYPE(const char *) pszDesc;
1187 /** Pointer to self - R0 pointer. */
1188 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1189 /** Pointer to self - RC pointer. */
1190 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1191 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1192 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1193 /** Array of physical guest page tracking structures. */
1194 PGMPAGE aPages[1];
1195} PGMRAMRANGE;
1196/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1197typedef PGMRAMRANGE *PPGMRAMRANGE;
1198
1199/** @name PGMRAMRANGE::fFlags
1200 * @{ */
1201/** The RAM range is floating around as an independent guest mapping. */
1202#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1203/** Ad hoc RAM range for an ROM mapping. */
1204#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1205/** Ad hoc RAM range for an MMIO mapping. */
1206#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1207/** Ad hoc RAM range for an MMIO2 mapping. */
1208#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1209/** @} */
1210
1211/** Tests if a RAM range is an ad hoc one or not.
1212 * @returns true/false.
1213 * @param pRam The RAM range.
1214 */
1215#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1216 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1217
1218
1219/**
1220 * Per page tracking structure for ROM image.
1221 *
1222 * A ROM image may have a shadow page, in which case we may have two pages
1223 * backing it. This structure contains the PGMPAGE for both while
1224 * PGMRAMRANGE have a copy of the active one. It is important that these
1225 * aren't out of sync in any regard other than page pool tracking data.
1226 */
1227typedef struct PGMROMPAGE
1228{
1229 /** The page structure for the virgin ROM page. */
1230 PGMPAGE Virgin;
1231 /** The page structure for the shadow RAM page. */
1232 PGMPAGE Shadow;
1233 /** The current protection setting. */
1234 PGMROMPROT enmProt;
1235 /** Live save status information. Makes use of unused alignment space. */
1236 struct
1237 {
1238 /** The previous protection value. */
1239 uint8_t u8Prot;
1240 /** Written to flag set by the handler. */
1241 bool fWrittenTo;
1242 /** Whether the shadow page is dirty or not. */
1243 bool fDirty;
1244 /** Whether it was dirtied in the recently. */
1245 bool fDirtiedRecently;
1246 } LiveSave;
1247} PGMROMPAGE;
1248AssertCompileSizeAlignment(PGMROMPAGE, 8);
1249/** Pointer to a ROM page tracking structure. */
1250typedef PGMROMPAGE *PPGMROMPAGE;
1251
1252
1253/**
1254 * A registered ROM image.
1255 *
1256 * This is needed to keep track of ROM image since they generally intrude
1257 * into a PGMRAMRANGE. It also keeps track of additional info like the
1258 * two page sets (read-only virgin and read-write shadow), the current
1259 * state of each page.
1260 *
1261 * Because access handlers cannot easily be executed in a different
1262 * context, the ROM ranges needs to be accessible and in all contexts.
1263 */
1264typedef struct PGMROMRANGE
1265{
1266 /** Pointer to the next range - R3. */
1267 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1268 /** Pointer to the next range - R0. */
1269 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1270 /** Pointer to the next range - RC. */
1271 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1272 /** Pointer alignment */
1273 RTRCPTR RCPtrAlignment;
1274 /** Address of the range. */
1275 RTGCPHYS GCPhys;
1276 /** Address of the last byte in the range. */
1277 RTGCPHYS GCPhysLast;
1278 /** Size of the range. */
1279 RTGCPHYS cb;
1280 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1281 uint32_t fFlags;
1282 /** The saved state range ID. */
1283 uint8_t idSavedState;
1284 /** Alignment padding. */
1285 uint8_t au8Alignment[3];
1286 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1287 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1288 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1289 * This is used for strictness checks. */
1290 R3PTRTYPE(const void *) pvOriginal;
1291 /** The ROM description. */
1292 R3PTRTYPE(const char *) pszDesc;
1293 /** The per page tracking structures. */
1294 PGMROMPAGE aPages[1];
1295} PGMROMRANGE;
1296/** Pointer to a ROM range. */
1297typedef PGMROMRANGE *PPGMROMRANGE;
1298
1299
1300/**
1301 * A registered MMIO2 (= Device RAM) range.
1302 *
1303 * There are a few reason why we need to keep track of these
1304 * registrations. One of them is the deregistration & cleanup stuff,
1305 * while another is that the PGMRAMRANGE associated with such a region may
1306 * have to be removed from the ram range list.
1307 *
1308 * Overlapping with a RAM range has to be 100% or none at all. The pages
1309 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1310 * will be raised if a partial overlap or an overlap of ROM pages is
1311 * encountered. On an overlap we will free all the existing RAM pages and
1312 * put in the ram range pages instead.
1313 */
1314typedef struct PGMMMIO2RANGE
1315{
1316 /** The owner of the range. (a device) */
1317 PPDMDEVINSR3 pDevInsR3;
1318 /** Pointer to the ring-3 mapping of the allocation. */
1319 RTR3PTR pvR3;
1320 /** Pointer to the next range - R3. */
1321 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1322 /** Whether it's mapped or not. */
1323 bool fMapped;
1324 /** Whether it's overlapping or not. */
1325 bool fOverlapping;
1326 /** The PCI region number.
1327 * @remarks This ASSUMES that nobody will ever really need to have multiple
1328 * PCI devices with matching MMIO region numbers on a single device. */
1329 uint8_t iRegion;
1330 /** The saved state range ID. */
1331 uint8_t idSavedState;
1332#if HC_ARCH_BITS != 32
1333 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1334 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 0 : 4];
1335#endif
1336 /** The associated RAM range. */
1337 PGMRAMRANGE RamRange;
1338} PGMMMIO2RANGE;
1339/** Pointer to a MMIO2 range. */
1340typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1341
1342
1343
1344
1345/**
1346 * PGMPhysRead/Write cache entry
1347 */
1348typedef struct PGMPHYSCACHEENTRY
1349{
1350 /** R3 pointer to physical page. */
1351 R3PTRTYPE(uint8_t *) pbR3;
1352 /** GC Physical address for cache entry */
1353 RTGCPHYS GCPhys;
1354#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1355 RTGCPHYS u32Padding0; /**< alignment padding. */
1356#endif
1357} PGMPHYSCACHEENTRY;
1358
1359/**
1360 * PGMPhysRead/Write cache to reduce REM memory access overhead
1361 */
1362typedef struct PGMPHYSCACHE
1363{
1364 /** Bitmap of valid cache entries */
1365 uint64_t aEntries;
1366 /** Cache entries */
1367 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1368} PGMPHYSCACHE;
1369
1370
1371/** Pointer to an allocation chunk ring-3 mapping. */
1372typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1373/** Pointer to an allocation chunk ring-3 mapping pointer. */
1374typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1375
1376/**
1377 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1378 *
1379 * The primary tree (Core) uses the chunk id as key.
1380 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1381 */
1382typedef struct PGMCHUNKR3MAP
1383{
1384 /** The key is the chunk id. */
1385 AVLU32NODECORE Core;
1386 /** The key is the ageing sequence number. */
1387 AVLLU32NODECORE AgeCore;
1388 /** The current age thingy. */
1389 uint32_t iAge;
1390 /** The current reference count. */
1391 uint32_t volatile cRefs;
1392 /** The current permanent reference count. */
1393 uint32_t volatile cPermRefs;
1394 /** The mapping address. */
1395 void *pv;
1396} PGMCHUNKR3MAP;
1397
1398/**
1399 * Allocation chunk ring-3 mapping TLB entry.
1400 */
1401typedef struct PGMCHUNKR3MAPTLBE
1402{
1403 /** The chunk id. */
1404 uint32_t volatile idChunk;
1405#if HC_ARCH_BITS == 64
1406 uint32_t u32Padding; /**< alignment padding. */
1407#endif
1408 /** The chunk map. */
1409#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1410 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1411#else
1412 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1413#endif
1414} PGMCHUNKR3MAPTLBE;
1415/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1416typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1417
1418/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1419 * @remark Must be a power of two value. */
1420#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1421
1422/**
1423 * Allocation chunk ring-3 mapping TLB.
1424 *
1425 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1426 * At first glance this might look kinda odd since AVL trees are
1427 * supposed to give the most optimial lookup times of all trees
1428 * due to their balancing. However, take a tree with 1023 nodes
1429 * in it, that's 10 levels, meaning that most searches has to go
1430 * down 9 levels before they find what they want. This isn't fast
1431 * compared to a TLB hit. There is the factor of cache misses,
1432 * and of course the problem with trees and branch prediction.
1433 * This is why we use TLBs in front of most of the trees.
1434 *
1435 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1436 * difficult when we switch to the new inlined AVL trees (from kStuff).
1437 */
1438typedef struct PGMCHUNKR3MAPTLB
1439{
1440 /** The TLB entries. */
1441 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1442} PGMCHUNKR3MAPTLB;
1443
1444/**
1445 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1446 * @returns Chunk TLB index.
1447 * @param idChunk The Chunk ID.
1448 */
1449#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1450
1451
1452/**
1453 * Ring-3 guest page mapping TLB entry.
1454 * @remarks used in ring-0 as well at the moment.
1455 */
1456typedef struct PGMPAGER3MAPTLBE
1457{
1458 /** Address of the page. */
1459 RTGCPHYS volatile GCPhys;
1460 /** The guest page. */
1461#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1462 R3PTRTYPE(PPGMPAGE) volatile pPage;
1463#else
1464 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1465#endif
1466 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1467#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1468 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1469#else
1470 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1471#endif
1472 /** The address */
1473#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1474 R3PTRTYPE(void *) volatile pv;
1475#else
1476 R3R0PTRTYPE(void *) volatile pv;
1477#endif
1478#if HC_ARCH_BITS == 32
1479 uint32_t u32Padding; /**< alignment padding. */
1480#endif
1481} PGMPAGER3MAPTLBE;
1482/** Pointer to an entry in the HC physical TLB. */
1483typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1484
1485
1486/** The number of entries in the ring-3 guest page mapping TLB.
1487 * @remarks The value must be a power of two. */
1488#define PGM_PAGER3MAPTLB_ENTRIES 64
1489
1490/**
1491 * Ring-3 guest page mapping TLB.
1492 * @remarks used in ring-0 as well at the moment.
1493 */
1494typedef struct PGMPAGER3MAPTLB
1495{
1496 /** The TLB entries. */
1497 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1498} PGMPAGER3MAPTLB;
1499/** Pointer to the ring-3 guest page mapping TLB. */
1500typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1501
1502/**
1503 * Calculates the index of the TLB entry for the specified guest page.
1504 * @returns Physical TLB index.
1505 * @param GCPhys The guest physical address.
1506 */
1507#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1508
1509
1510/**
1511 * Mapping cache usage set entry.
1512 *
1513 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1514 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1515 * cache. If it's extended to include ring-3, well, then something will
1516 * have be changed here...
1517 */
1518typedef struct PGMMAPSETENTRY
1519{
1520 /** The mapping cache index. */
1521 uint16_t iPage;
1522 /** The number of references.
1523 * The max is UINT16_MAX - 1. */
1524 uint16_t cRefs;
1525#if HC_ARCH_BITS == 64
1526 uint32_t alignment;
1527#endif
1528 /** Pointer to the page. */
1529 RTR0PTR pvPage;
1530 /** The physical address for this entry. */
1531 RTHCPHYS HCPhys;
1532} PGMMAPSETENTRY;
1533/** Pointer to a mapping cache usage set entry. */
1534typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1535
1536/**
1537 * Mapping cache usage set.
1538 *
1539 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1540 * done during exits / traps. The set is
1541 */
1542typedef struct PGMMAPSET
1543{
1544 /** The number of occupied entries.
1545 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1546 * dynamic mappings. */
1547 uint32_t cEntries;
1548 /** The start of the current subset.
1549 * This is UINT32_MAX if no subset is currently open. */
1550 uint32_t iSubset;
1551 /** The index of the current CPU, only valid if the set is open. */
1552 int32_t iCpu;
1553#if HC_ARCH_BITS == 64
1554 uint32_t alignment;
1555#endif
1556 /** The entries. */
1557 PGMMAPSETENTRY aEntries[64];
1558 /** HCPhys -> iEntry fast lookup table.
1559 * Use PGMMAPSET_HASH for hashing.
1560 * The entries may or may not be valid, check against cEntries. */
1561 uint8_t aiHashTable[128];
1562} PGMMAPSET;
1563/** Pointer to the mapping cache set. */
1564typedef PGMMAPSET *PPGMMAPSET;
1565
1566/** PGMMAPSET::cEntries value for a closed set. */
1567#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1568
1569/** Hash function for aiHashTable. */
1570#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1571
1572/** The max fill size (strict builds). */
1573#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1574
1575
1576/** @name Context neutrual page mapper TLB.
1577 *
1578 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1579 * code is writting in a kind of context neutrual way. Time will show whether
1580 * this actually makes sense or not...
1581 *
1582 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1583 * context ends up using a global mapping cache on some platforms
1584 * (darwin).
1585 *
1586 * @{ */
1587/** @typedef PPGMPAGEMAPTLB
1588 * The page mapper TLB pointer type for the current context. */
1589/** @typedef PPGMPAGEMAPTLB
1590 * The page mapper TLB entry pointer type for the current context. */
1591/** @typedef PPGMPAGEMAPTLB
1592 * The page mapper TLB entry pointer pointer type for the current context. */
1593/** @def PGM_PAGEMAPTLB_ENTRIES
1594 * The number of TLB entries in the page mapper TLB for the current context. */
1595/** @def PGM_PAGEMAPTLB_IDX
1596 * Calculate the TLB index for a guest physical address.
1597 * @returns The TLB index.
1598 * @param GCPhys The guest physical address. */
1599/** @typedef PPGMPAGEMAP
1600 * Pointer to a page mapper unit for current context. */
1601/** @typedef PPPGMPAGEMAP
1602 * Pointer to a page mapper unit pointer for current context. */
1603#ifdef IN_RC
1604// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1605// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1606// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1607# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1608# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1609 typedef void * PPGMPAGEMAP;
1610 typedef void ** PPPGMPAGEMAP;
1611//#elif IN_RING0
1612// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1613// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1614// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1615//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1616//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1617// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1618// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1619#else
1620 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1621 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1622 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1623# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1624# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1625 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1626 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1627#endif
1628/** @} */
1629
1630
1631/** @name PGM Pool Indexes.
1632 * Aka. the unique shadow page identifier.
1633 * @{ */
1634/** NIL page pool IDX. */
1635#define NIL_PGMPOOL_IDX 0
1636/** The first normal index. */
1637#define PGMPOOL_IDX_FIRST_SPECIAL 1
1638/** Page directory (32-bit root). */
1639#define PGMPOOL_IDX_PD 1
1640/** Page Directory Pointer Table (PAE root). */
1641#define PGMPOOL_IDX_PDPT 2
1642/** AMD64 CR3 level index.*/
1643#define PGMPOOL_IDX_AMD64_CR3 3
1644/** Nested paging root.*/
1645#define PGMPOOL_IDX_NESTED_ROOT 4
1646/** The first normal index. */
1647#define PGMPOOL_IDX_FIRST 5
1648/** The last valid index. (inclusive, 14 bits) */
1649#define PGMPOOL_IDX_LAST 0x3fff
1650/** @} */
1651
1652/** The NIL index for the parent chain. */
1653#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1654#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1655
1656/**
1657 * Node in the chain linking a shadowed page to it's parent (user).
1658 */
1659#pragma pack(1)
1660typedef struct PGMPOOLUSER
1661{
1662 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1663 uint16_t iNext;
1664 /** The user page index. */
1665 uint16_t iUser;
1666 /** Index into the user table. */
1667 uint32_t iUserTable;
1668} PGMPOOLUSER, *PPGMPOOLUSER;
1669typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1670#pragma pack()
1671
1672
1673/** The NIL index for the phys ext chain. */
1674#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1675
1676/**
1677 * Node in the chain of physical cross reference extents.
1678 * @todo Calling this an 'extent' is not quite right, find a better name.
1679 */
1680#pragma pack(1)
1681typedef struct PGMPOOLPHYSEXT
1682{
1683 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1684 uint16_t iNext;
1685 /** The user page index. */
1686 uint16_t aidx[3];
1687} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1688typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1689#pragma pack()
1690
1691
1692/**
1693 * The kind of page that's being shadowed.
1694 */
1695typedef enum PGMPOOLKIND
1696{
1697 /** The virtual invalid 0 entry. */
1698 PGMPOOLKIND_INVALID = 0,
1699 /** The entry is free (=unused). */
1700 PGMPOOLKIND_FREE,
1701
1702 /** Shw: 32-bit page table; Gst: no paging */
1703 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1704 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1705 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1706 /** Shw: 32-bit page table; Gst: 4MB page. */
1707 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1708 /** Shw: PAE page table; Gst: no paging */
1709 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1710 /** Shw: PAE page table; Gst: 32-bit page table. */
1711 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1712 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1713 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1714 /** Shw: PAE page table; Gst: PAE page table. */
1715 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1716 /** Shw: PAE page table; Gst: 2MB page. */
1717 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1718
1719 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1720 PGMPOOLKIND_32BIT_PD,
1721 /** Shw: 32-bit page directory. Gst: no paging. */
1722 PGMPOOLKIND_32BIT_PD_PHYS,
1723 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1724 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1725 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1726 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1727 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1728 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1729 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1730 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1731 /** Shw: PAE page directory; Gst: PAE page directory. */
1732 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1733 /** Shw: PAE page directory; Gst: no paging. */
1734 PGMPOOLKIND_PAE_PD_PHYS,
1735
1736 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1737 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1738 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1739 PGMPOOLKIND_PAE_PDPT,
1740 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1741 PGMPOOLKIND_PAE_PDPT_PHYS,
1742
1743 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1744 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1745 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1746 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1747 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1748 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1749 /** Shw: 64-bit page directory table; Gst: no paging */
1750 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1751
1752 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1753 PGMPOOLKIND_64BIT_PML4,
1754
1755 /** Shw: EPT page directory pointer table; Gst: no paging */
1756 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1757 /** Shw: EPT page directory table; Gst: no paging */
1758 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1759 /** Shw: EPT page table; Gst: no paging */
1760 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1761
1762 /** Shw: Root Nested paging table. */
1763 PGMPOOLKIND_ROOT_NESTED,
1764
1765 /** The last valid entry. */
1766 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1767} PGMPOOLKIND;
1768
1769/**
1770 * The access attributes of the page; only applies to big pages.
1771 */
1772typedef enum
1773{
1774 PGMPOOLACCESS_DONTCARE = 0,
1775 PGMPOOLACCESS_USER_RW,
1776 PGMPOOLACCESS_USER_R,
1777 PGMPOOLACCESS_USER_RW_NX,
1778 PGMPOOLACCESS_USER_R_NX,
1779 PGMPOOLACCESS_SUPERVISOR_RW,
1780 PGMPOOLACCESS_SUPERVISOR_R,
1781 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1782 PGMPOOLACCESS_SUPERVISOR_R_NX
1783} PGMPOOLACCESS;
1784
1785/**
1786 * The tracking data for a page in the pool.
1787 */
1788typedef struct PGMPOOLPAGE
1789{
1790 /** AVL node code with the (R3) physical address of this page. */
1791 AVLOHCPHYSNODECORE Core;
1792 /** Pointer to the R3 mapping of the page. */
1793#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1794 R3PTRTYPE(void *) pvPageR3;
1795#else
1796 R3R0PTRTYPE(void *) pvPageR3;
1797#endif
1798 /** The guest physical address. */
1799#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1800 uint32_t Alignment0;
1801#endif
1802 RTGCPHYS GCPhys;
1803
1804 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1805 RTGCPTR pvLastAccessHandlerRip;
1806 RTGCPTR pvLastAccessHandlerFault;
1807 uint64_t cLastAccessHandlerCount;
1808
1809 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1810 uint8_t enmKind;
1811 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1812 uint8_t enmAccess;
1813 /** The index of this page. */
1814 uint16_t idx;
1815 /** The next entry in the list this page currently resides in.
1816 * It's either in the free list or in the GCPhys hash. */
1817 uint16_t iNext;
1818#ifdef PGMPOOL_WITH_USER_TRACKING
1819 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1820 uint16_t iUserHead;
1821 /** The number of present entries. */
1822 uint16_t cPresent;
1823 /** The first entry in the table which is present. */
1824 uint16_t iFirstPresent;
1825#endif
1826#ifdef PGMPOOL_WITH_MONITORING
1827 /** The number of modifications to the monitored page. */
1828 uint16_t cModifications;
1829 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1830 uint16_t iModifiedNext;
1831 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1832 uint16_t iModifiedPrev;
1833 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1834 uint16_t iMonitoredNext;
1835 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1836 uint16_t iMonitoredPrev;
1837#endif
1838#ifdef PGMPOOL_WITH_CACHE
1839 /** The next page in the age list. */
1840 uint16_t iAgeNext;
1841 /** The previous page in the age list. */
1842 uint16_t iAgePrev;
1843#endif /* PGMPOOL_WITH_CACHE */
1844 /** Used to indicate that the page is zeroed. */
1845 bool fZeroed;
1846 /** Used to indicate that a PT has non-global entries. */
1847 bool fSeenNonGlobal;
1848 /** Used to indicate that we're monitoring writes to the guest page. */
1849 bool fMonitored;
1850 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1851 * (All pages are in the age list.) */
1852 bool fCached;
1853 /** This is used by the R3 access handlers when invoked by an async thread.
1854 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1855 bool volatile fReusedFlushPending;
1856 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1857 bool fDirty;
1858
1859 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1860 uint32_t cLocked;
1861 uint32_t idxDirty;
1862 RTGCPTR pvDirtyFault;
1863} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1864/** Pointer to a const pool page. */
1865typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1866
1867
1868#ifdef PGMPOOL_WITH_CACHE
1869/** The hash table size. */
1870# define PGMPOOL_HASH_SIZE 0x40
1871/** The hash function. */
1872# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1873#endif
1874
1875
1876/**
1877 * The shadow page pool instance data.
1878 *
1879 * It's all one big allocation made at init time, except for the
1880 * pages that is. The user nodes follows immediatly after the
1881 * page structures.
1882 */
1883typedef struct PGMPOOL
1884{
1885 /** The VM handle - R3 Ptr. */
1886 PVMR3 pVMR3;
1887 /** The VM handle - R0 Ptr. */
1888 PVMR0 pVMR0;
1889 /** The VM handle - RC Ptr. */
1890 PVMRC pVMRC;
1891 /** The max pool size. This includes the special IDs. */
1892 uint16_t cMaxPages;
1893 /** The current pool size. */
1894 uint16_t cCurPages;
1895 /** The head of the free page list. */
1896 uint16_t iFreeHead;
1897 /* Padding. */
1898 uint16_t u16Padding;
1899#ifdef PGMPOOL_WITH_USER_TRACKING
1900 /** Head of the chain of free user nodes. */
1901 uint16_t iUserFreeHead;
1902 /** The number of user nodes we've allocated. */
1903 uint16_t cMaxUsers;
1904 /** The number of present page table entries in the entire pool. */
1905 uint32_t cPresent;
1906 /** Pointer to the array of user nodes - RC pointer. */
1907 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1908 /** Pointer to the array of user nodes - R3 pointer. */
1909 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1910 /** Pointer to the array of user nodes - R0 pointer. */
1911 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1912#endif /* PGMPOOL_WITH_USER_TRACKING */
1913#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1914 /** Head of the chain of free phys ext nodes. */
1915 uint16_t iPhysExtFreeHead;
1916 /** The number of user nodes we've allocated. */
1917 uint16_t cMaxPhysExts;
1918 /** Pointer to the array of physical xref extent - RC pointer. */
1919 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1920 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1921 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1922 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1923 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1924#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1925#ifdef PGMPOOL_WITH_CACHE
1926 /** Hash table for GCPhys addresses. */
1927 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1928 /** The head of the age list. */
1929 uint16_t iAgeHead;
1930 /** The tail of the age list. */
1931 uint16_t iAgeTail;
1932 /** Set if the cache is enabled. */
1933 bool fCacheEnabled;
1934 /** Alignment padding. */
1935 bool afPadding1[3];
1936#endif /* PGMPOOL_WITH_CACHE */
1937#ifdef PGMPOOL_WITH_MONITORING
1938 /** Head of the list of modified pages. */
1939 uint16_t iModifiedHead;
1940 /** The current number of modified pages. */
1941 uint16_t cModifiedPages;
1942 /** Access handler, RC. */
1943 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1944 /** Access handler, R0. */
1945 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1946 /** Access handler, R3. */
1947 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1948 /** The access handler description (R3 ptr). */
1949 R3PTRTYPE(const char *) pszAccessHandler;
1950# if HC_ARCH_BITS == 32
1951 /** Alignment padding. */
1952 uint32_t u32Padding2;
1953# endif
1954 /* Next available slot. */
1955 uint32_t idxFreeDirtyPage;
1956 /* Number of active dirty pages. */
1957 uint32_t cDirtyPages;
1958 /* Array of current dirty pgm pool page indices. */
1959 uint16_t aIdxDirtyPages[16];
1960 uint64_t aDirtyPages[16][512];
1961#endif /* PGMPOOL_WITH_MONITORING */
1962 /** The number of pages currently in use. */
1963 uint16_t cUsedPages;
1964#ifdef VBOX_WITH_STATISTICS
1965 /** The high water mark for cUsedPages. */
1966 uint16_t cUsedPagesHigh;
1967 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1968 /** Profiling pgmPoolAlloc(). */
1969 STAMPROFILEADV StatAlloc;
1970 /** Profiling pgmR3PoolClearDoIt(). */
1971 STAMPROFILE StatClearAll;
1972 /** Profiling pgmR3PoolReset(). */
1973 STAMPROFILE StatR3Reset;
1974 /** Profiling pgmPoolFlushPage(). */
1975 STAMPROFILE StatFlushPage;
1976 /** Profiling pgmPoolFree(). */
1977 STAMPROFILE StatFree;
1978 /** Counting explicit flushes by PGMPoolFlushPage(). */
1979 STAMCOUNTER StatForceFlushPage;
1980 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1981 STAMCOUNTER StatForceFlushDirtyPage;
1982 /** Counting flushes for reused pages. */
1983 STAMCOUNTER StatForceFlushReused;
1984 /** Profiling time spent zeroing pages. */
1985 STAMPROFILE StatZeroPage;
1986# ifdef PGMPOOL_WITH_USER_TRACKING
1987 /** Profiling of pgmPoolTrackDeref. */
1988 STAMPROFILE StatTrackDeref;
1989 /** Profiling pgmTrackFlushGCPhysPT. */
1990 STAMPROFILE StatTrackFlushGCPhysPT;
1991 /** Profiling pgmTrackFlushGCPhysPTs. */
1992 STAMPROFILE StatTrackFlushGCPhysPTs;
1993 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1994 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1995 /** Number of times we've been out of user records. */
1996 STAMCOUNTER StatTrackFreeUpOneUser;
1997 /** Nr of flushed entries. */
1998 STAMCOUNTER StatTrackFlushEntry;
1999 /** Nr of updated entries. */
2000 STAMCOUNTER StatTrackFlushEntryKeep;
2001# endif
2002# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2003 /** Profiling deref activity related tracking GC physical pages. */
2004 STAMPROFILE StatTrackDerefGCPhys;
2005 /** Number of linear searches for a HCPhys in the ram ranges. */
2006 STAMCOUNTER StatTrackLinearRamSearches;
2007 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2008 STAMCOUNTER StamTrackPhysExtAllocFailures;
2009# endif
2010# ifdef PGMPOOL_WITH_MONITORING
2011 /** Profiling the RC/R0 access handler. */
2012 STAMPROFILE StatMonitorRZ;
2013 /** Times we've failed interpreting the instruction. */
2014 STAMCOUNTER StatMonitorRZEmulateInstr;
2015 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2016 STAMPROFILE StatMonitorRZFlushPage;
2017 /* Times we've detected a page table reinit. */
2018 STAMCOUNTER StatMonitorRZFlushReinit;
2019 /** Counting flushes for pages that are modified too often. */
2020 STAMCOUNTER StatMonitorRZFlushModOverflow;
2021 /** Times we've detected fork(). */
2022 STAMCOUNTER StatMonitorRZFork;
2023 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2024 STAMPROFILE StatMonitorRZHandled;
2025 /** Times we've failed interpreting a patch code instruction. */
2026 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2027 /** Times we've failed interpreting a patch code instruction during flushing. */
2028 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2029 /** The number of times we've seen rep prefixes we can't handle. */
2030 STAMCOUNTER StatMonitorRZRepPrefix;
2031 /** Profiling the REP STOSD cases we've handled. */
2032 STAMPROFILE StatMonitorRZRepStosd;
2033 /** Nr of handled PT faults. */
2034 STAMCOUNTER StatMonitorRZFaultPT;
2035 /** Nr of handled PD faults. */
2036 STAMCOUNTER StatMonitorRZFaultPD;
2037 /** Nr of handled PDPT faults. */
2038 STAMCOUNTER StatMonitorRZFaultPDPT;
2039 /** Nr of handled PML4 faults. */
2040 STAMCOUNTER StatMonitorRZFaultPML4;
2041
2042 /** Profiling the R3 access handler. */
2043 STAMPROFILE StatMonitorR3;
2044 /** Times we've failed interpreting the instruction. */
2045 STAMCOUNTER StatMonitorR3EmulateInstr;
2046 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2047 STAMPROFILE StatMonitorR3FlushPage;
2048 /* Times we've detected a page table reinit. */
2049 STAMCOUNTER StatMonitorR3FlushReinit;
2050 /** Counting flushes for pages that are modified too often. */
2051 STAMCOUNTER StatMonitorR3FlushModOverflow;
2052 /** Times we've detected fork(). */
2053 STAMCOUNTER StatMonitorR3Fork;
2054 /** Profiling the R3 access we've handled (except REP STOSD). */
2055 STAMPROFILE StatMonitorR3Handled;
2056 /** The number of times we've seen rep prefixes we can't handle. */
2057 STAMCOUNTER StatMonitorR3RepPrefix;
2058 /** Profiling the REP STOSD cases we've handled. */
2059 STAMPROFILE StatMonitorR3RepStosd;
2060 /** Nr of handled PT faults. */
2061 STAMCOUNTER StatMonitorR3FaultPT;
2062 /** Nr of handled PD faults. */
2063 STAMCOUNTER StatMonitorR3FaultPD;
2064 /** Nr of handled PDPT faults. */
2065 STAMCOUNTER StatMonitorR3FaultPDPT;
2066 /** Nr of handled PML4 faults. */
2067 STAMCOUNTER StatMonitorR3FaultPML4;
2068 /** The number of times we're called in an async thread an need to flush. */
2069 STAMCOUNTER StatMonitorR3Async;
2070 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2071 STAMCOUNTER StatResetDirtyPages;
2072 /** Times we've called pgmPoolAddDirtyPage. */
2073 STAMCOUNTER StatDirtyPage;
2074 /** Times we've had to flush duplicates for dirty page management. */
2075 STAMCOUNTER StatDirtyPageDupFlush;
2076 /** Times we've had to flush because of overflow. */
2077 STAMCOUNTER StatDirtyPageOverFlowFlush;
2078
2079 /** The high wather mark for cModifiedPages. */
2080 uint16_t cModifiedPagesHigh;
2081 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2082# endif
2083# ifdef PGMPOOL_WITH_CACHE
2084 /** The number of cache hits. */
2085 STAMCOUNTER StatCacheHits;
2086 /** The number of cache misses. */
2087 STAMCOUNTER StatCacheMisses;
2088 /** The number of times we've got a conflict of 'kind' in the cache. */
2089 STAMCOUNTER StatCacheKindMismatches;
2090 /** Number of times we've been out of pages. */
2091 STAMCOUNTER StatCacheFreeUpOne;
2092 /** The number of cacheable allocations. */
2093 STAMCOUNTER StatCacheCacheable;
2094 /** The number of uncacheable allocations. */
2095 STAMCOUNTER StatCacheUncacheable;
2096# endif
2097#else
2098 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2099#endif
2100 /** The AVL tree for looking up a page by its HC physical address. */
2101 AVLOHCPHYSTREE HCPhysTree;
2102 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2103 /** Array of pages. (cMaxPages in length)
2104 * The Id is the index into thist array.
2105 */
2106 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2107} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2108#ifdef PGMPOOL_WITH_MONITORING
2109AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2110AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2111#endif
2112AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2113#ifdef VBOX_WITH_STATISTICS
2114AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2115#endif
2116AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2117
2118
2119/** @def PGMPOOL_PAGE_2_PTR
2120 * Maps a pool page pool into the current context.
2121 *
2122 * @returns VBox status code.
2123 * @param pVM The VM handle.
2124 * @param pPage The pool page.
2125 *
2126 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2127 * small page window employeed by that function. Be careful.
2128 * @remark There is no need to assert on the result.
2129 */
2130#if defined(IN_RC)
2131# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2132#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2133# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2134#elif defined(VBOX_STRICT)
2135# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2136DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2137{
2138 Assert(pPage && pPage->pvPageR3);
2139 return pPage->pvPageR3;
2140}
2141#else
2142# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2143#endif
2144
2145/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2146 * Maps a pool page pool into the current context.
2147 *
2148 * @returns VBox status code.
2149 * @param pPGM Pointer to the PGM instance data.
2150 * @param pPage The pool page.
2151 *
2152 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2153 * small page window employeed by that function. Be careful.
2154 * @remark There is no need to assert on the result.
2155 */
2156#if defined(IN_RC)
2157# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2158#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2159# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2160#else
2161# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2162#endif
2163
2164/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2165 * Maps a pool page pool into the current context.
2166 *
2167 * @returns VBox status code.
2168 * @param pPGM Pointer to the PGMCPU instance data.
2169 * @param pPage The pool page.
2170 *
2171 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2172 * small page window employeed by that function. Be careful.
2173 * @remark There is no need to assert on the result.
2174 */
2175#if defined(IN_RC)
2176# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2177#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2178# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2179#else
2180# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2181#endif
2182
2183
2184/** @name Per guest page tracking data.
2185 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2186 * is to use more bits for it and split it up later on. But for now we'll play
2187 * safe and change as little as possible.
2188 *
2189 * The 16-bit word has two parts:
2190 *
2191 * The first 14-bit forms the @a idx field. It is either the index of a page in
2192 * the shadow page pool, or and index into the extent list.
2193 *
2194 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2195 * shadow page pool references to the page. If cRefs equals
2196 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2197 * (misnomer) table and not the shadow page pool.
2198 *
2199 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2200 * the 16-bit word.
2201 *
2202 * @{ */
2203/** The shift count for getting to the cRefs part. */
2204#define PGMPOOL_TD_CREFS_SHIFT 14
2205/** The mask applied after shifting the tracking data down by
2206 * PGMPOOL_TD_CREFS_SHIFT. */
2207#define PGMPOOL_TD_CREFS_MASK 0x3
2208/** The cRef value used to indiciate that the idx is the head of a
2209 * physical cross reference list. */
2210#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2211/** The shift used to get idx. */
2212#define PGMPOOL_TD_IDX_SHIFT 0
2213/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2214#define PGMPOOL_TD_IDX_MASK 0x3fff
2215/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2216 * simply too many mappings of this page. */
2217#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2218
2219/** @def PGMPOOL_TD_MAKE
2220 * Makes a 16-bit tracking data word.
2221 *
2222 * @returns tracking data.
2223 * @param cRefs The @a cRefs field. Must be within bounds!
2224 * @param idx The @a idx field. Must also be within bounds! */
2225#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2226
2227/** @def PGMPOOL_TD_GET_CREFS
2228 * Get the @a cRefs field from a tracking data word.
2229 *
2230 * @returns The @a cRefs field
2231 * @param u16 The tracking data word. */
2232#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2233
2234/** @def PGMPOOL_TD_GET_IDX
2235 * Get the @a idx field from a tracking data word.
2236 *
2237 * @returns The @a idx field
2238 * @param u16 The tracking data word. */
2239#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2240/** @} */
2241
2242
2243/**
2244 * Trees are using self relative offsets as pointers.
2245 * So, all its data, including the root pointer, must be in the heap for HC and GC
2246 * to have the same layout.
2247 */
2248typedef struct PGMTREES
2249{
2250 /** Physical access handlers (AVL range+offsetptr tree). */
2251 AVLROGCPHYSTREE PhysHandlers;
2252 /** Virtual access handlers (AVL range + GC ptr tree). */
2253 AVLROGCPTRTREE VirtHandlers;
2254 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2255 AVLROGCPHYSTREE PhysToVirtHandlers;
2256 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2257 AVLROGCPTRTREE HyperVirtHandlers;
2258} PGMTREES;
2259/** Pointer to PGM trees. */
2260typedef PGMTREES *PPGMTREES;
2261
2262
2263/** @name Paging mode macros
2264 * @{ */
2265#ifdef IN_RC
2266# define PGM_CTX(a,b) a##RC##b
2267# define PGM_CTX_STR(a,b) a "GC" b
2268# define PGM_CTX_DECL(type) VMMRCDECL(type)
2269#else
2270# ifdef IN_RING3
2271# define PGM_CTX(a,b) a##R3##b
2272# define PGM_CTX_STR(a,b) a "R3" b
2273# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2274# else
2275# define PGM_CTX(a,b) a##R0##b
2276# define PGM_CTX_STR(a,b) a "R0" b
2277# define PGM_CTX_DECL(type) VMMDECL(type)
2278# endif
2279#endif
2280
2281#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2282#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2283#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2284#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2285#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2286#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2287#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2288#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2289#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2290#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2291#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2292#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2293#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2294#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2295#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2296#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2297#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2298
2299#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2300#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2301#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2302#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2303#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2304#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2305#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2306#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2307#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2308#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2309#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2310#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2311#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2312#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2313#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2314#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2315#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2316
2317/* Shw_Gst */
2318#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2319#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2320#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2321#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2322#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2323#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2324#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2325#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2326#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2327#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2328#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2329#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2330#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2331#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2332#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2333#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2334#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2335#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2336#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2337
2338#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2339#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2340#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2341#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2342#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2343#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2344#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2345#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2346#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2347#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2348#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2349#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2350#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2351#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2352#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2353#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2354#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2355#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2356#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2357#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2358#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2359#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2360#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2361#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2362#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2363#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2364#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2365#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2366#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2367#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2368#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2369#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2370#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2371#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2372#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2373#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2374#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2375
2376#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2377#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2378/** @} */
2379
2380/**
2381 * Data for each paging mode.
2382 */
2383typedef struct PGMMODEDATA
2384{
2385 /** The guest mode type. */
2386 uint32_t uGstType;
2387 /** The shadow mode type. */
2388 uint32_t uShwType;
2389
2390 /** @name Function pointers for Shadow paging.
2391 * @{
2392 */
2393 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2394 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2395 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2396 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2397
2398 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2399 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2400
2401 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2402 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2403 /** @} */
2404
2405 /** @name Function pointers for Guest paging.
2406 * @{
2407 */
2408 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2409 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2410 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2411 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2412 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2413 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2414 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2415 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2416 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2417 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2418 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2419 /** @} */
2420
2421 /** @name Function pointers for Both Shadow and Guest paging.
2422 * @{
2423 */
2424 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2425 /* no pfnR3BthTrap0eHandler */
2426 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2427 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2428 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2429 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2430 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2431#ifdef VBOX_STRICT
2432 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2433#endif
2434 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2435 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2436
2437 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2438 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2439 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2440 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2441 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2442 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2443#ifdef VBOX_STRICT
2444 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2445#endif
2446 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2447 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2448
2449 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2450 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2451 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2452 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2453 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2454 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2455#ifdef VBOX_STRICT
2456 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2457#endif
2458 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2459 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2460 /** @} */
2461} PGMMODEDATA, *PPGMMODEDATA;
2462
2463
2464
2465/**
2466 * Converts a PGM pointer into a VM pointer.
2467 * @returns Pointer to the VM structure the PGM is part of.
2468 * @param pPGM Pointer to PGM instance data.
2469 */
2470#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2471
2472/**
2473 * PGM Data (part of VM)
2474 */
2475typedef struct PGM
2476{
2477 /** Offset to the VM structure. */
2478 RTINT offVM;
2479 /** Offset of the PGMCPU structure relative to VMCPU. */
2480 RTINT offVCpuPGM;
2481
2482 /** @cfgm{RamPreAlloc, boolean, false}
2483 * Indicates whether the base RAM should all be allocated before starting
2484 * the VM (default), or if it should be allocated when first written to.
2485 */
2486 bool fRamPreAlloc;
2487 /** Indicates whether write monitoring is currently in use.
2488 * This is used to prevent conflicts between live saving and page sharing
2489 * detection. */
2490 bool fPhysWriteMonitoringEngaged;
2491 /** Alignment padding. */
2492 bool afAlignment0[2];
2493
2494 /*
2495 * This will be redefined at least two more times before we're done, I'm sure.
2496 * The current code is only to get on with the coding.
2497 * - 2004-06-10: initial version, bird.
2498 * - 2004-07-02: 1st time, bird.
2499 * - 2004-10-18: 2nd time, bird.
2500 * - 2005-07-xx: 3rd time, bird.
2501 */
2502
2503 /** The host paging mode. (This is what SUPLib reports.) */
2504 SUPPAGINGMODE enmHostMode;
2505
2506 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2507 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2508 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2509 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2510
2511 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2512 RTGCPHYS GCPhys4MBPSEMask;
2513
2514 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2515 * This is sorted by physical address and contains no overlapping ranges. */
2516 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2517 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2518 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2519 /** RC pointer corresponding to PGM::pRamRangesR3. */
2520 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2521 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2522 * range is linked or unlinked. */
2523 uint32_t volatile idRamRangesGen;
2524
2525 /** Pointer to the list of ROM ranges - for R3.
2526 * This is sorted by physical address and contains no overlapping ranges. */
2527 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2528 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2529 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2530 /** RC pointer corresponding to PGM::pRomRangesR3. */
2531 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2532#if HC_ARCH_BITS == 64
2533 /** Alignment padding. */
2534 RTRCPTR GCPtrPadding2;
2535#endif
2536
2537 /** Pointer to the list of MMIO2 ranges - for R3.
2538 * Registration order. */
2539 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2540
2541 /** PGM offset based trees - R3 Ptr. */
2542 R3PTRTYPE(PPGMTREES) pTreesR3;
2543 /** PGM offset based trees - R0 Ptr. */
2544 R0PTRTYPE(PPGMTREES) pTreesR0;
2545 /** PGM offset based trees - RC Ptr. */
2546 RCPTRTYPE(PPGMTREES) pTreesRC;
2547
2548 /** Linked list of GC mappings - for RC.
2549 * The list is sorted ascending on address.
2550 */
2551 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2552 /** Linked list of GC mappings - for HC.
2553 * The list is sorted ascending on address.
2554 */
2555 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2556 /** Linked list of GC mappings - for R0.
2557 * The list is sorted ascending on address.
2558 */
2559 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2560
2561 /** Pointer to the 5 page CR3 content mapping.
2562 * The first page is always the CR3 (in some form) while the 4 other pages
2563 * are used of the PDs in PAE mode. */
2564 RTGCPTR GCPtrCR3Mapping;
2565#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2566 uint32_t u32Alignment1;
2567#endif
2568
2569 /** Indicates that PGMR3FinalizeMappings has been called and that further
2570 * PGMR3MapIntermediate calls will be rejected. */
2571 bool fFinalizedMappings;
2572 /** If set no conflict checks are required. (boolean) */
2573 bool fMappingsFixed;
2574 /** If set, then no mappings are put into the shadow page table. (boolean) */
2575 bool fDisableMappings;
2576 /** Size of fixed mapping */
2577 uint32_t cbMappingFixed;
2578 /** Base address (GC) of fixed mapping */
2579 RTGCPTR GCPtrMappingFixed;
2580 /** The address of the previous RAM range mapping. */
2581 RTGCPTR GCPtrPrevRamRangeMapping;
2582
2583 /** @name Intermediate Context
2584 * @{ */
2585 /** Pointer to the intermediate page directory - Normal. */
2586 R3PTRTYPE(PX86PD) pInterPD;
2587 /** Pointer to the intermedate page tables - Normal.
2588 * There are two page tables, one for the identity mapping and one for
2589 * the host context mapping (of the core code). */
2590 R3PTRTYPE(PX86PT) apInterPTs[2];
2591 /** Pointer to the intermedate page tables - PAE. */
2592 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2593 /** Pointer to the intermedate page directory - PAE. */
2594 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2595 /** Pointer to the intermedate page directory - PAE. */
2596 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2597 /** Pointer to the intermedate page-map level 4 - AMD64. */
2598 R3PTRTYPE(PX86PML4) pInterPaePML4;
2599 /** Pointer to the intermedate page directory - AMD64. */
2600 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2601 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2602 RTHCPHYS HCPhysInterPD;
2603 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2604 RTHCPHYS HCPhysInterPaePDPT;
2605 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2606 RTHCPHYS HCPhysInterPaePML4;
2607 /** @} */
2608
2609 /** Base address of the dynamic page mapping area.
2610 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2611 */
2612 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2613 /** The index of the last entry used in the dynamic page mapping area. */
2614 RTUINT iDynPageMapLast;
2615 /** Cache containing the last entries in the dynamic page mapping area.
2616 * The cache size is covering half of the mapping area. */
2617 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2618 /** Keep a lock counter for the full (!) mapping area. */
2619 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2620
2621 /** The address of the ring-0 mapping cache if we're making use of it. */
2622 RTR0PTR pvR0DynMapUsed;
2623#if HC_ARCH_BITS == 32
2624 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2625 uint32_t u32Alignment2;
2626#endif
2627
2628 /** PGM critical section.
2629 * This protects the physical & virtual access handlers, ram ranges,
2630 * and the page flag updating (some of it anyway).
2631 */
2632 PDMCRITSECT CritSect;
2633
2634 /** Pointer to SHW+GST mode data (function pointers).
2635 * The index into this table is made up from */
2636 R3PTRTYPE(PPGMMODEDATA) paModeData;
2637
2638 /** Shadow Page Pool - R3 Ptr. */
2639 R3PTRTYPE(PPGMPOOL) pPoolR3;
2640 /** Shadow Page Pool - R0 Ptr. */
2641 R0PTRTYPE(PPGMPOOL) pPoolR0;
2642 /** Shadow Page Pool - RC Ptr. */
2643 RCPTRTYPE(PPGMPOOL) pPoolRC;
2644
2645 /** We're not in a state which permits writes to guest memory.
2646 * (Only used in strict builds.) */
2647 bool fNoMorePhysWrites;
2648 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2649 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2650
2651 /**
2652 * Data associated with managing the ring-3 mappings of the allocation chunks.
2653 */
2654 struct
2655 {
2656 /** The chunk tree, ordered by chunk id. */
2657#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2658 R3PTRTYPE(PAVLU32NODECORE) pTree;
2659#else
2660 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2661#endif
2662 /** The chunk age tree, ordered by ageing sequence number. */
2663 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2664 /** The chunk mapping TLB. */
2665 PGMCHUNKR3MAPTLB Tlb;
2666 /** The number of mapped chunks. */
2667 uint32_t c;
2668 /** The maximum number of mapped chunks.
2669 * @cfgm PGM/MaxRing3Chunks */
2670 uint32_t cMax;
2671 /** The current time. */
2672 uint32_t iNow;
2673 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2674 uint32_t AgeingCountdown;
2675 } ChunkR3Map;
2676
2677 /**
2678 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2679 */
2680 PGMPAGER3MAPTLB PhysTlbHC;
2681
2682 /** @name The zero page.
2683 * @{ */
2684 /** The host physical address of the zero page. */
2685 RTHCPHYS HCPhysZeroPg;
2686 /** The ring-3 mapping of the zero page. */
2687 RTR3PTR pvZeroPgR3;
2688 /** The ring-0 mapping of the zero page. */
2689 RTR0PTR pvZeroPgR0;
2690 /** The GC mapping of the zero page. */
2691 RTGCPTR pvZeroPgRC;
2692#if GC_ARCH_BITS != 32
2693 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2694#endif
2695 /** @}*/
2696
2697 /** The number of handy pages. */
2698 uint32_t cHandyPages;
2699 /**
2700 * Array of handy pages.
2701 *
2702 * This array is used in a two way communication between pgmPhysAllocPage
2703 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2704 * an intermediary.
2705 *
2706 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2707 * (The current size of 32 pages, means 128 KB of handy memory.)
2708 */
2709 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2710
2711 /**
2712 * Live save data.
2713 */
2714 struct
2715 {
2716 /** The number of ready pages. */
2717 uint32_t cReadyPages;
2718 /** The number of dirty pages. */
2719 uint32_t cDirtyPages;
2720 /** The number of monitored pages. */
2721 uint32_t cMonitoredPages;
2722 /** The number of ignored pages. */
2723 uint32_t cIgnoredPages;
2724 /** The number of MMIO2 pages. */
2725 uint32_t cMmio2Pages;
2726 /** Indicates that a live save operation is active. */
2727 bool fActive;
2728 /** Padding. */
2729 bool afReserved[3];
2730 } LiveSave;
2731
2732 /** @name Error injection.
2733 * @{ */
2734 /** Inject handy page allocation errors pretending we're completely out of
2735 * memory. */
2736 bool volatile fErrInjHandyPages;
2737 /** Padding. */
2738 bool afReserved[7];
2739 /** @} */
2740
2741 /** @name Release Statistics
2742 * @{ */
2743 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2744 uint32_t cPrivatePages; /**< The number of private pages. */
2745 uint32_t cSharedPages; /**< The number of shared pages. */
2746 uint32_t cZeroPages; /**< The number of zero backed pages. */
2747 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2748 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2749
2750 /** The number of times we were forced to change the hypervisor region location. */
2751 STAMCOUNTER cRelocations;
2752 /** @} */
2753
2754#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2755 /* R3 only: */
2756 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2757 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2758
2759 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2760 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2761 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2762 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2763 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2764 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2765 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2766 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2767 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2768 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2769 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2770 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2771 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2772 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2773 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2774 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2775 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2776 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2777/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2778 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2779 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2780/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2781
2782 /* RC only: */
2783 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2784 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2785 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2786 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2787
2788 STAMCOUNTER StatRZPhysRead;
2789 STAMCOUNTER StatRZPhysReadBytes;
2790 STAMCOUNTER StatRZPhysWrite;
2791 STAMCOUNTER StatRZPhysWriteBytes;
2792 STAMCOUNTER StatR3PhysRead;
2793 STAMCOUNTER StatR3PhysReadBytes;
2794 STAMCOUNTER StatR3PhysWrite;
2795 STAMCOUNTER StatR3PhysWriteBytes;
2796 STAMCOUNTER StatRCPhysRead;
2797 STAMCOUNTER StatRCPhysReadBytes;
2798 STAMCOUNTER StatRCPhysWrite;
2799 STAMCOUNTER StatRCPhysWriteBytes;
2800
2801 STAMCOUNTER StatRZPhysSimpleRead;
2802 STAMCOUNTER StatRZPhysSimpleReadBytes;
2803 STAMCOUNTER StatRZPhysSimpleWrite;
2804 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2805 STAMCOUNTER StatR3PhysSimpleRead;
2806 STAMCOUNTER StatR3PhysSimpleReadBytes;
2807 STAMCOUNTER StatR3PhysSimpleWrite;
2808 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2809 STAMCOUNTER StatRCPhysSimpleRead;
2810 STAMCOUNTER StatRCPhysSimpleReadBytes;
2811 STAMCOUNTER StatRCPhysSimpleWrite;
2812 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2813
2814# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2815 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2816 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2817 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2818 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2819 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2820 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2821# endif
2822#endif
2823} PGM;
2824#ifndef IN_TSTVMSTRUCTGC /* HACK */
2825AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2826AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2827AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2828AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2829AssertCompileMemberAlignment(PGM, CritSect, 8);
2830AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2831AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2832AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2833AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2834AssertCompileMemberAlignment(PGM, cRelocations, 8);
2835#endif /* !IN_TSTVMSTRUCTGC */
2836/** Pointer to the PGM instance data. */
2837typedef PGM *PPGM;
2838
2839
2840/**
2841 * Converts a PGMCPU pointer into a VM pointer.
2842 * @returns Pointer to the VM structure the PGM is part of.
2843 * @param pPGM Pointer to PGMCPU instance data.
2844 */
2845#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2846
2847/**
2848 * Converts a PGMCPU pointer into a PGM pointer.
2849 * @returns Pointer to the VM structure the PGM is part of.
2850 * @param pPGM Pointer to PGMCPU instance data.
2851 */
2852#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2853
2854/**
2855 * PGMCPU Data (part of VMCPU).
2856 */
2857typedef struct PGMCPU
2858{
2859 /** Offset to the VM structure. */
2860 RTINT offVM;
2861 /** Offset to the VMCPU structure. */
2862 RTINT offVCpu;
2863 /** Offset of the PGM structure relative to VMCPU. */
2864 RTINT offPGM;
2865 RTINT uPadding0; /**< structure size alignment. */
2866
2867#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2868 /** Automatically tracked physical memory mapping set.
2869 * Ring-0 and strict raw-mode builds. */
2870 PGMMAPSET AutoSet;
2871#endif
2872
2873 /** A20 gate mask.
2874 * Our current approach to A20 emulation is to let REM do it and don't bother
2875 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2876 * But whould need arrise, we'll subject physical addresses to this mask. */
2877 RTGCPHYS GCPhysA20Mask;
2878 /** A20 gate state - boolean! */
2879 bool fA20Enabled;
2880
2881 /** What needs syncing (PGM_SYNC_*).
2882 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2883 * PGMFlushTLB, and PGMR3Load. */
2884 RTUINT fSyncFlags;
2885
2886 /** The shadow paging mode. */
2887 PGMMODE enmShadowMode;
2888 /** The guest paging mode. */
2889 PGMMODE enmGuestMode;
2890
2891 /** The current physical address representing in the guest CR3 register. */
2892 RTGCPHYS GCPhysCR3;
2893
2894 /** @name 32-bit Guest Paging.
2895 * @{ */
2896 /** The guest's page directory, R3 pointer. */
2897 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2898#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2899 /** The guest's page directory, R0 pointer. */
2900 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2901#endif
2902 /** The guest's page directory, static RC mapping. */
2903 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2904 /** @} */
2905
2906 /** @name PAE Guest Paging.
2907 * @{ */
2908 /** The guest's page directory pointer table, static RC mapping. */
2909 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2910 /** The guest's page directory pointer table, R3 pointer. */
2911 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2912#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2913 /** The guest's page directory pointer table, R0 pointer. */
2914 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2915#endif
2916
2917 /** The guest's page directories, R3 pointers.
2918 * These are individual pointers and don't have to be adjecent.
2919 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2920 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2921 /** The guest's page directories, R0 pointers.
2922 * Same restrictions as apGstPaePDsR3. */
2923#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2924 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2925#endif
2926 /** The guest's page directories, static GC mapping.
2927 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2928 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2929 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2930 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2931 RTGCPHYS aGCPhysGstPaePDs[4];
2932 /** The physical addresses of the monitored guest page directories (PAE). */
2933 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2934 /** @} */
2935
2936 /** @name AMD64 Guest Paging.
2937 * @{ */
2938 /** The guest's page directory pointer table, R3 pointer. */
2939 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2940#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2941 /** The guest's page directory pointer table, R0 pointer. */
2942 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2943#endif
2944 /** @} */
2945
2946 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2947 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2948 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2949 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2950 /** Pointer to the page of the current active CR3 - RC Ptr. */
2951 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2952 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2953 uint32_t iShwUser;
2954 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2955 uint32_t iShwUserTable;
2956# if HC_ARCH_BITS == 64
2957 RTRCPTR alignment6; /**< structure size alignment. */
2958# endif
2959 /** @} */
2960
2961 /** @name Function pointers for Shadow paging.
2962 * @{
2963 */
2964 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2965 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2966 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2967 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2968
2969 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2970 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2971
2972 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2973 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2974
2975 /** @} */
2976
2977 /** @name Function pointers for Guest paging.
2978 * @{
2979 */
2980 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2981 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2982 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2983 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2984 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2985 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2986 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2987 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2988#if HC_ARCH_BITS == 64
2989 RTRCPTR alignment3; /**< structure size alignment. */
2990#endif
2991
2992 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2993 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2994 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2995 /** @} */
2996
2997 /** @name Function pointers for Both Shadow and Guest paging.
2998 * @{
2999 */
3000 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3001 /* no pfnR3BthTrap0eHandler */
3002 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3003 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3004 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3005 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3006 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3007 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3008 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3009 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3010
3011 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
3012 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3013 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3014 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3015 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3016 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3017 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3018 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3019 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3020
3021 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
3022 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3023 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3024 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3025 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3026 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3027 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3028 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3029 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3030 RTRCPTR alignment2; /**< structure size alignment. */
3031 /** @} */
3032
3033 /** For saving stack space, the disassembler state is allocated here instead of
3034 * on the stack.
3035 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3036 union
3037 {
3038 /** The disassembler scratch space. */
3039 DISCPUSTATE DisState;
3040 /** Padding. */
3041 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3042 };
3043
3044 /* Count the number of pgm pool access handler calls. */
3045 uint64_t cPoolAccessHandler;
3046
3047 /** @name Release Statistics
3048 * @{ */
3049 /** The number of times the guest has switched mode since last reset or statistics reset. */
3050 STAMCOUNTER cGuestModeChanges;
3051 /** @} */
3052
3053#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3054 /** @name Statistics
3055 * @{ */
3056 /** RC: Which statistic this \#PF should be attributed to. */
3057 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3058 RTRCPTR padding0;
3059 /** R0: Which statistic this \#PF should be attributed to. */
3060 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3061 RTR0PTR padding1;
3062
3063 /* Common */
3064 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3065 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3066
3067 /* R0 only: */
3068 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3069 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3070 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3071 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3072 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3073 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3074 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3075 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3076 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3077 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3078 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3079 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3080 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3081 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3082 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3083 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3084 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3085 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3086 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3087 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3088 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3089 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3090 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3091 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3092 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3093 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3094
3095 /* RZ only: */
3096 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3097 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3098 STAMPROFILE StatRZTrap0eTimeSyncPT;
3099 STAMPROFILE StatRZTrap0eTimeMapping;
3100 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3101 STAMPROFILE StatRZTrap0eTimeHandlers;
3102 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3103 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3104 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3105 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3106 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3107 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3108 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3109 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3110 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3111 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3112 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3113 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3114 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3115 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3116 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3117 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3118 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3119 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3120 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3121 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3122 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3123 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
3124 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
3125 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
3126 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
3127 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
3128 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
3129 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
3130 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
3131 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
3132 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
3133 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
3134 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
3135 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
3136 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
3137 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3138 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3139 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
3140 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3141 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3142 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3143 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3144 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3145
3146 /* HC - R3 and (maybe) R0: */
3147
3148 /* RZ & R3: */
3149 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3150 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3151 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3152 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3153 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3154 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3155 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3156 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3157 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3158 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3159 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3160 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3161 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3162 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3163 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3164 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3165 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3166 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3167 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3168 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3169 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3170 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3171 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3172 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3173 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3174 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3175 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3176 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3177 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3178 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3179 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3180 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3181 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3182 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3183 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3184 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3185 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3186 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in #PF. */
3187 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF. */
3188 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3189 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3190 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3191 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3192 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3193 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3194 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3195
3196 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3197 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3198 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3199 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3200 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3201 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3202 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3203 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3204 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3205 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3206 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3207 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3208 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3209 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3210 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3211 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3212 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3213 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3214 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3215 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3216 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3217 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3218 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3219 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3220 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3221 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3222 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3223 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3224 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3225 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3226 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3227 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3228 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3229 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3230 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3231 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3232 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in #PF. */
3233 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in #PF. */
3234 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3235 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3236 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3237 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3238 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3239 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3240 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3241 /** @} */
3242#endif /* VBOX_WITH_STATISTICS */
3243} PGMCPU;
3244/** Pointer to the per-cpu PGM data. */
3245typedef PGMCPU *PPGMCPU;
3246
3247
3248/** @name PGM::fSyncFlags Flags
3249 * @{
3250 */
3251/** Updates the virtual access handler state bit in PGMPAGE. */
3252#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3253/** Always sync CR3. */
3254#define PGM_SYNC_ALWAYS RT_BIT(1)
3255/** Check monitoring on next CR3 (re)load and invalidate page.
3256 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3257#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3258/** Check guest mapping in SyncCR3. */
3259#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3260/** Clear the page pool (a light weight flush). */
3261#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3262#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3263/** @} */
3264
3265
3266RT_C_DECLS_BEGIN
3267
3268int pgmLock(PVM pVM);
3269void pgmUnlock(PVM pVM);
3270
3271int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3272int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3273PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3274void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3275DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3276
3277void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3278bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3279void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3280int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3281DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3282#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3283void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3284#else
3285# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3286#endif
3287DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3288int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3289
3290int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3291int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3292int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3293int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3294int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3295int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3296int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3297int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3298int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3299int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3300int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3301VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3302#ifdef IN_RING3
3303void pgmR3PhysRelinkRamRanges(PVM pVM);
3304int pgmR3PhysRamPreAllocate(PVM pVM);
3305int pgmR3PhysRamReset(PVM pVM);
3306int pgmR3PhysRomReset(PVM pVM);
3307int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3308
3309int pgmR3PoolInit(PVM pVM);
3310void pgmR3PoolRelocate(PVM pVM);
3311void pgmR3PoolReset(PVM pVM);
3312void pgmR3PoolClearAll(PVM pVM);
3313
3314#endif /* IN_RING3 */
3315#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3316int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3317#endif
3318int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3319
3320DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3321{
3322 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3323}
3324
3325void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3326void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3327int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3328void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3329PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3330int pgmPoolSyncCR3(PVMCPU pVCpu);
3331bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3332int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3333DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3334{
3335 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3336}
3337
3338uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3339void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3340void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3341#ifdef PGMPOOL_WITH_MONITORING
3342void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3343int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3344void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3345#endif
3346
3347void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3348void pgmPoolResetDirtyPages(PVM pVM);
3349
3350int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3351int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3352
3353void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3354void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3355int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3356int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3357
3358int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3359#ifndef IN_RC
3360int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3361#endif
3362int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3363
3364PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3365PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3366PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3367PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3368
3369RT_C_DECLS_END
3370
3371
3372/**
3373 * Gets the PGMRAMRANGE structure for a guest page.
3374 *
3375 * @returns Pointer to the RAM range on success.
3376 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3377 *
3378 * @param pPGM PGM handle.
3379 * @param GCPhys The GC physical address.
3380 */
3381DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3382{
3383 /*
3384 * Optimize for the first range.
3385 */
3386 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3387 RTGCPHYS off = GCPhys - pRam->GCPhys;
3388 if (RT_UNLIKELY(off >= pRam->cb))
3389 {
3390 do
3391 {
3392 pRam = pRam->CTX_SUFF(pNext);
3393 if (RT_UNLIKELY(!pRam))
3394 break;
3395 off = GCPhys - pRam->GCPhys;
3396 } while (off >= pRam->cb);
3397 }
3398 return pRam;
3399}
3400
3401
3402/**
3403 * Gets the PGMPAGE structure for a guest page.
3404 *
3405 * @returns Pointer to the page on success.
3406 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3407 *
3408 * @param pPGM PGM handle.
3409 * @param GCPhys The GC physical address.
3410 */
3411DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3412{
3413 /*
3414 * Optimize for the first range.
3415 */
3416 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3417 RTGCPHYS off = GCPhys - pRam->GCPhys;
3418 if (RT_UNLIKELY(off >= pRam->cb))
3419 {
3420 do
3421 {
3422 pRam = pRam->CTX_SUFF(pNext);
3423 if (RT_UNLIKELY(!pRam))
3424 return NULL;
3425 off = GCPhys - pRam->GCPhys;
3426 } while (off >= pRam->cb);
3427 }
3428 return &pRam->aPages[off >> PAGE_SHIFT];
3429}
3430
3431
3432/**
3433 * Gets the PGMPAGE structure for a guest page.
3434 *
3435 * Old Phys code: Will make sure the page is present.
3436 *
3437 * @returns VBox status code.
3438 * @retval VINF_SUCCESS and a valid *ppPage on success.
3439 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3440 *
3441 * @param pPGM PGM handle.
3442 * @param GCPhys The GC physical address.
3443 * @param ppPage Where to store the page pointer on success.
3444 */
3445DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3446{
3447 /*
3448 * Optimize for the first range.
3449 */
3450 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3451 RTGCPHYS off = GCPhys - pRam->GCPhys;
3452 if (RT_UNLIKELY(off >= pRam->cb))
3453 {
3454 do
3455 {
3456 pRam = pRam->CTX_SUFF(pNext);
3457 if (RT_UNLIKELY(!pRam))
3458 {
3459 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3460 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3461 }
3462 off = GCPhys - pRam->GCPhys;
3463 } while (off >= pRam->cb);
3464 }
3465 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3466 return VINF_SUCCESS;
3467}
3468
3469
3470
3471
3472/**
3473 * Gets the PGMPAGE structure for a guest page.
3474 *
3475 * Old Phys code: Will make sure the page is present.
3476 *
3477 * @returns VBox status code.
3478 * @retval VINF_SUCCESS and a valid *ppPage on success.
3479 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3480 *
3481 * @param pPGM PGM handle.
3482 * @param GCPhys The GC physical address.
3483 * @param ppPage Where to store the page pointer on success.
3484 * @param ppRamHint Where to read and store the ram list hint.
3485 * The caller initializes this to NULL before the call.
3486 */
3487DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3488{
3489 RTGCPHYS off;
3490 PPGMRAMRANGE pRam = *ppRamHint;
3491 if ( !pRam
3492 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3493 {
3494 pRam = pPGM->CTX_SUFF(pRamRanges);
3495 off = GCPhys - pRam->GCPhys;
3496 if (RT_UNLIKELY(off >= pRam->cb))
3497 {
3498 do
3499 {
3500 pRam = pRam->CTX_SUFF(pNext);
3501 if (RT_UNLIKELY(!pRam))
3502 {
3503 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3504 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3505 }
3506 off = GCPhys - pRam->GCPhys;
3507 } while (off >= pRam->cb);
3508 }
3509 *ppRamHint = pRam;
3510 }
3511 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3512 return VINF_SUCCESS;
3513}
3514
3515
3516/**
3517 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3518 *
3519 * @returns Pointer to the page on success.
3520 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3521 *
3522 * @param pPGM PGM handle.
3523 * @param GCPhys The GC physical address.
3524 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3525 */
3526DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3527{
3528 /*
3529 * Optimize for the first range.
3530 */
3531 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3532 RTGCPHYS off = GCPhys - pRam->GCPhys;
3533 if (RT_UNLIKELY(off >= pRam->cb))
3534 {
3535 do
3536 {
3537 pRam = pRam->CTX_SUFF(pNext);
3538 if (RT_UNLIKELY(!pRam))
3539 return NULL;
3540 off = GCPhys - pRam->GCPhys;
3541 } while (off >= pRam->cb);
3542 }
3543 *ppRam = pRam;
3544 return &pRam->aPages[off >> PAGE_SHIFT];
3545}
3546
3547
3548/**
3549 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3550 *
3551 * @returns Pointer to the page on success.
3552 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3553 *
3554 * @param pPGM PGM handle.
3555 * @param GCPhys The GC physical address.
3556 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3557 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3558 */
3559DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3560{
3561 /*
3562 * Optimize for the first range.
3563 */
3564 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3565 RTGCPHYS off = GCPhys - pRam->GCPhys;
3566 if (RT_UNLIKELY(off >= pRam->cb))
3567 {
3568 do
3569 {
3570 pRam = pRam->CTX_SUFF(pNext);
3571 if (RT_UNLIKELY(!pRam))
3572 {
3573 *ppRam = NULL; /* Shut up silly GCC warnings. */
3574 *ppPage = NULL; /* ditto */
3575 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3576 }
3577 off = GCPhys - pRam->GCPhys;
3578 } while (off >= pRam->cb);
3579 }
3580 *ppRam = pRam;
3581 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3582 return VINF_SUCCESS;
3583}
3584
3585
3586/**
3587 * Convert GC Phys to HC Phys.
3588 *
3589 * @returns VBox status.
3590 * @param pPGM PGM handle.
3591 * @param GCPhys The GC physical address.
3592 * @param pHCPhys Where to store the corresponding HC physical address.
3593 *
3594 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3595 * Avoid when writing new code!
3596 */
3597DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3598{
3599 PPGMPAGE pPage;
3600 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3601 if (RT_FAILURE(rc))
3602 return rc;
3603 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3604 return VINF_SUCCESS;
3605}
3606
3607#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3608
3609/**
3610 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3611 * optimizes access to pages already in the set.
3612 *
3613 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3614 * @param pPGM Pointer to the PVM instance data.
3615 * @param HCPhys The physical address of the page.
3616 * @param ppv Where to store the mapping address.
3617 */
3618DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3619{
3620 PVM pVM = PGM2VM(pPGM);
3621 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3622 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3623
3624 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3625 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3626 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3627
3628 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3629 unsigned iEntry = pSet->aiHashTable[iHash];
3630 if ( iEntry < pSet->cEntries
3631 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3632 {
3633 *ppv = pSet->aEntries[iEntry].pvPage;
3634 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3635 }
3636 else
3637 {
3638 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3639 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3640 }
3641
3642 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3643 return VINF_SUCCESS;
3644}
3645
3646
3647/**
3648 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3649 * access to pages already in the set.
3650 *
3651 * @returns See PGMDynMapGCPage.
3652 * @param pPGM Pointer to the PVM instance data.
3653 * @param HCPhys The physical address of the page.
3654 * @param ppv Where to store the mapping address.
3655 */
3656DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3657{
3658 PVM pVM = PGM2VM(pPGM);
3659 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3660
3661 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3662 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3663
3664 /*
3665 * Get the ram range.
3666 */
3667 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3668 RTGCPHYS off = GCPhys - pRam->GCPhys;
3669 if (RT_UNLIKELY(off >= pRam->cb
3670 /** @todo || page state stuff */))
3671 {
3672 /* This case is not counted into StatR0DynMapGCPageInl. */
3673 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3674 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3675 }
3676
3677 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3678 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3679
3680 /*
3681 * pgmR0DynMapHCPageInlined with out stats.
3682 */
3683 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3684 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3685 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3686
3687 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3688 unsigned iEntry = pSet->aiHashTable[iHash];
3689 if ( iEntry < pSet->cEntries
3690 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3691 {
3692 *ppv = pSet->aEntries[iEntry].pvPage;
3693 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3694 }
3695 else
3696 {
3697 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3698 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3699 }
3700
3701 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3702 return VINF_SUCCESS;
3703}
3704
3705
3706/**
3707 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3708 * access to pages already in the set.
3709 *
3710 * @returns See PGMDynMapGCPage.
3711 * @param pPGM Pointer to the PVM instance data.
3712 * @param HCPhys The physical address of the page.
3713 * @param ppv Where to store the mapping address.
3714 */
3715DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3716{
3717 PVM pVM = PGM2VM(pPGM);
3718 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3719
3720 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3721
3722 /*
3723 * Get the ram range.
3724 */
3725 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3726 RTGCPHYS off = GCPhys - pRam->GCPhys;
3727 if (RT_UNLIKELY(off >= pRam->cb
3728 /** @todo || page state stuff */))
3729 {
3730 /* This case is not counted into StatR0DynMapGCPageInl. */
3731 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3732 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3733 }
3734
3735 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3736 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3737
3738 /*
3739 * pgmR0DynMapHCPageInlined with out stats.
3740 */
3741 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3742 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3743 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3744
3745 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3746 unsigned iEntry = pSet->aiHashTable[iHash];
3747 if ( iEntry < pSet->cEntries
3748 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3749 {
3750 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3751 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3752 }
3753 else
3754 {
3755 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3756 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3757 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3758 }
3759
3760 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3761 return VINF_SUCCESS;
3762}
3763
3764#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3765#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3766
3767/**
3768 * Maps the page into current context (RC and maybe R0).
3769 *
3770 * @returns pointer to the mapping.
3771 * @param pVM Pointer to the PGM instance data.
3772 * @param pPage The page.
3773 */
3774DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3775{
3776 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3777 {
3778 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3779 void *pv;
3780# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3781 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3782# else
3783 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3784# endif
3785 return pv;
3786 }
3787 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3788}
3789
3790/**
3791 * Temporarily maps one host page specified by HC physical address, returning
3792 * pointer within the page.
3793 *
3794 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3795 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3796 *
3797 * @returns The address corresponding to HCPhys.
3798 * @param pPGM Pointer to the PVM instance data.
3799 * @param HCPhys HC Physical address of the page.
3800 */
3801DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3802{
3803 void *pv;
3804# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3805 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3806# else
3807 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3808# endif
3809 pv = (void *)((uintptr_t)pv | ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3810 return pv;
3811}
3812
3813#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3814#ifndef IN_RC
3815
3816/**
3817 * Queries the Physical TLB entry for a physical guest page,
3818 * attempting to load the TLB entry if necessary.
3819 *
3820 * @returns VBox status code.
3821 * @retval VINF_SUCCESS on success
3822 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3823 *
3824 * @param pPGM The PGM instance handle.
3825 * @param GCPhys The address of the guest page.
3826 * @param ppTlbe Where to store the pointer to the TLB entry.
3827 */
3828DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3829{
3830 int rc;
3831 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3832 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3833 {
3834 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3835 rc = VINF_SUCCESS;
3836 }
3837 else
3838 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3839 *ppTlbe = pTlbe;
3840 return rc;
3841}
3842
3843
3844/**
3845 * Queries the Physical TLB entry for a physical guest page,
3846 * attempting to load the TLB entry if necessary.
3847 *
3848 * @returns VBox status code.
3849 * @retval VINF_SUCCESS on success
3850 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3851 *
3852 * @param pPGM The PGM instance handle.
3853 * @param pPage Pointer to the PGMPAGE structure corresponding to
3854 * GCPhys.
3855 * @param GCPhys The address of the guest page.
3856 * @param ppTlbe Where to store the pointer to the TLB entry.
3857 */
3858DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3859{
3860 int rc;
3861 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3862 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3863 {
3864 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3865 rc = VINF_SUCCESS;
3866 }
3867 else
3868 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3869 *ppTlbe = pTlbe;
3870 return rc;
3871}
3872
3873#endif /* !IN_RC */
3874
3875/**
3876 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3877 * Takes PSE-36 into account.
3878 *
3879 * @returns guest physical address
3880 * @param pPGM Pointer to the PGM instance data.
3881 * @param Pde Guest Pde
3882 */
3883DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3884{
3885 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3886 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3887
3888 return GCPhys & pPGM->GCPhys4MBPSEMask;
3889}
3890
3891
3892/**
3893 * Gets the page directory entry for the specified address (32-bit paging).
3894 *
3895 * @returns The page directory entry in question.
3896 * @param pPGM Pointer to the PGM instance data.
3897 * @param GCPtr The address.
3898 */
3899DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3900{
3901#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3902 PCX86PD pGuestPD = NULL;
3903 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3904 if (RT_FAILURE(rc))
3905 {
3906 X86PDE ZeroPde = {0};
3907 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3908 }
3909#else
3910 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3911# ifdef IN_RING3
3912 if (!pGuestPD)
3913 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3914# endif
3915#endif
3916 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3917}
3918
3919
3920/**
3921 * Gets the address of a specific page directory entry (32-bit paging).
3922 *
3923 * @returns Pointer the page directory entry in question.
3924 * @param pPGM Pointer to the PGM instance data.
3925 * @param GCPtr The address.
3926 */
3927DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3928{
3929#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3930 PX86PD pGuestPD = NULL;
3931 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3932 AssertRCReturn(rc, NULL);
3933#else
3934 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3935# ifdef IN_RING3
3936 if (!pGuestPD)
3937 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3938# endif
3939#endif
3940 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3941}
3942
3943
3944/**
3945 * Gets the address the guest page directory (32-bit paging).
3946 *
3947 * @returns Pointer the page directory entry in question.
3948 * @param pPGM Pointer to the PGM instance data.
3949 */
3950DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3951{
3952#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3953 PX86PD pGuestPD = NULL;
3954 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3955 AssertRCReturn(rc, NULL);
3956#else
3957 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3958# ifdef IN_RING3
3959 if (!pGuestPD)
3960 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3961# endif
3962#endif
3963 return pGuestPD;
3964}
3965
3966
3967/**
3968 * Gets the guest page directory pointer table.
3969 *
3970 * @returns Pointer to the page directory in question.
3971 * @returns NULL if the page directory is not present or on an invalid page.
3972 * @param pPGM Pointer to the PGM instance data.
3973 */
3974DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3975{
3976#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3977 PX86PDPT pGuestPDPT = NULL;
3978 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3979 AssertRCReturn(rc, NULL);
3980#else
3981 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3982# ifdef IN_RING3
3983 if (!pGuestPDPT)
3984 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3985# endif
3986#endif
3987 return pGuestPDPT;
3988}
3989
3990
3991/**
3992 * Gets the guest page directory pointer table entry for the specified address.
3993 *
3994 * @returns Pointer to the page directory in question.
3995 * @returns NULL if the page directory is not present or on an invalid page.
3996 * @param pPGM Pointer to the PGM instance data.
3997 * @param GCPtr The address.
3998 */
3999DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4000{
4001 AssertGCPtr32(GCPtr);
4002
4003#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4004 PX86PDPT pGuestPDPT = 0;
4005 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
4006 AssertRCReturn(rc, 0);
4007#else
4008 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
4009# ifdef IN_RING3
4010 if (!pGuestPDPT)
4011 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
4012# endif
4013#endif
4014 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
4015}
4016
4017
4018/**
4019 * Gets the page directory for the specified address.
4020 *
4021 * @returns Pointer to the page directory in question.
4022 * @returns NULL if the page directory is not present or on an invalid page.
4023 * @param pPGM Pointer to the PGM instance data.
4024 * @param GCPtr The address.
4025 */
4026DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
4027{
4028 AssertGCPtr32(GCPtr);
4029
4030 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4031 AssertReturn(pGuestPDPT, NULL);
4032 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4033 if (pGuestPDPT->a[iPdpt].n.u1Present)
4034 {
4035#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4036 PX86PDPAE pGuestPD = NULL;
4037 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4038 AssertRCReturn(rc, NULL);
4039#else
4040 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4041 if ( !pGuestPD
4042 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4043 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4044#endif
4045 return pGuestPD;
4046 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
4047 }
4048 return NULL;
4049}
4050
4051
4052/**
4053 * Gets the page directory entry for the specified address.
4054 *
4055 * @returns Pointer to the page directory entry in question.
4056 * @returns NULL if the page directory is not present or on an invalid page.
4057 * @param pPGM Pointer to the PGM instance data.
4058 * @param GCPtr The address.
4059 */
4060DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4061{
4062 AssertGCPtr32(GCPtr);
4063
4064 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4065 AssertReturn(pGuestPDPT, NULL);
4066 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4067 if (pGuestPDPT->a[iPdpt].n.u1Present)
4068 {
4069 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4070#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4071 PX86PDPAE pGuestPD = NULL;
4072 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4073 AssertRCReturn(rc, NULL);
4074#else
4075 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4076 if ( !pGuestPD
4077 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4078 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4079#endif
4080 return &pGuestPD->a[iPD];
4081 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
4082 }
4083 return NULL;
4084}
4085
4086
4087/**
4088 * Gets the page directory entry for the specified address.
4089 *
4090 * @returns The page directory entry in question.
4091 * @returns A non-present entry if the page directory is not present or on an invalid page.
4092 * @param pPGM Pointer to the PGM instance data.
4093 * @param GCPtr The address.
4094 */
4095DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4096{
4097 AssertGCPtr32(GCPtr);
4098 X86PDEPAE ZeroPde = {0};
4099 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4100 if (RT_LIKELY(pGuestPDPT))
4101 {
4102 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4103 if (pGuestPDPT->a[iPdpt].n.u1Present)
4104 {
4105 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4106#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4107 PX86PDPAE pGuestPD = NULL;
4108 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4109 AssertRCReturn(rc, ZeroPde);
4110#else
4111 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4112 if ( !pGuestPD
4113 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4114 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4115#endif
4116 return pGuestPD->a[iPD];
4117 }
4118 }
4119 return ZeroPde;
4120}
4121
4122
4123/**
4124 * Gets the page directory pointer table entry for the specified address
4125 * and returns the index into the page directory
4126 *
4127 * @returns Pointer to the page directory in question.
4128 * @returns NULL if the page directory is not present or on an invalid page.
4129 * @param pPGM Pointer to the PGM instance data.
4130 * @param GCPtr The address.
4131 * @param piPD Receives the index into the returned page directory
4132 * @param pPdpe Receives the page directory pointer entry. Optional.
4133 */
4134DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4135{
4136 AssertGCPtr32(GCPtr);
4137
4138 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4139 AssertReturn(pGuestPDPT, NULL);
4140 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4141 if (pPdpe)
4142 *pPdpe = pGuestPDPT->a[iPdpt];
4143 if (pGuestPDPT->a[iPdpt].n.u1Present)
4144 {
4145 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4146#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4147 PX86PDPAE pGuestPD = NULL;
4148 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4149 AssertRCReturn(rc, NULL);
4150#else
4151 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4152 if ( !pGuestPD
4153 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4154 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4155#endif
4156 *piPD = iPD;
4157 return pGuestPD;
4158 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4159 }
4160 return NULL;
4161}
4162
4163#ifndef IN_RC
4164
4165/**
4166 * Gets the page map level-4 pointer for the guest.
4167 *
4168 * @returns Pointer to the PML4 page.
4169 * @param pPGM Pointer to the PGM instance data.
4170 */
4171DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4172{
4173#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4174 PX86PML4 pGuestPml4;
4175 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4176 AssertRCReturn(rc, NULL);
4177#else
4178 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4179# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4180 if (!pGuestPml4)
4181 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4182# endif
4183 Assert(pGuestPml4);
4184#endif
4185 return pGuestPml4;
4186}
4187
4188
4189/**
4190 * Gets the pointer to a page map level-4 entry.
4191 *
4192 * @returns Pointer to the PML4 entry.
4193 * @param pPGM Pointer to the PGM instance data.
4194 * @param iPml4 The index.
4195 */
4196DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4197{
4198#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4199 PX86PML4 pGuestPml4;
4200 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4201 AssertRCReturn(rc, NULL);
4202#else
4203 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4204# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4205 if (!pGuestPml4)
4206 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4207# endif
4208 Assert(pGuestPml4);
4209#endif
4210 return &pGuestPml4->a[iPml4];
4211}
4212
4213
4214/**
4215 * Gets a page map level-4 entry.
4216 *
4217 * @returns The PML4 entry.
4218 * @param pPGM Pointer to the PGM instance data.
4219 * @param iPml4 The index.
4220 */
4221DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4222{
4223#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4224 PX86PML4 pGuestPml4;
4225 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4226 if (RT_FAILURE(rc))
4227 {
4228 X86PML4E ZeroPml4e = {0};
4229 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4230 }
4231#else
4232 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4233# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4234 if (!pGuestPml4)
4235 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4236# endif
4237 Assert(pGuestPml4);
4238#endif
4239 return pGuestPml4->a[iPml4];
4240}
4241
4242
4243/**
4244 * Gets the page directory pointer entry for the specified address.
4245 *
4246 * @returns Pointer to the page directory pointer entry in question.
4247 * @returns NULL if the page directory is not present or on an invalid page.
4248 * @param pPGM Pointer to the PGM instance data.
4249 * @param GCPtr The address.
4250 * @param ppPml4e Page Map Level-4 Entry (out)
4251 */
4252DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4253{
4254 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4255 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4256 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4257 if (pPml4e->n.u1Present)
4258 {
4259 PX86PDPT pPdpt;
4260 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4261 AssertRCReturn(rc, NULL);
4262
4263 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4264 return &pPdpt->a[iPdpt];
4265 }
4266 return NULL;
4267}
4268
4269
4270/**
4271 * Gets the page directory entry for the specified address.
4272 *
4273 * @returns The page directory entry in question.
4274 * @returns A non-present entry if the page directory is not present or on an invalid page.
4275 * @param pPGM Pointer to the PGM instance data.
4276 * @param GCPtr The address.
4277 * @param ppPml4e Page Map Level-4 Entry (out)
4278 * @param pPdpe Page directory pointer table entry (out)
4279 */
4280DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4281{
4282 X86PDEPAE ZeroPde = {0};
4283 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4284 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4285 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4286 if (pPml4e->n.u1Present)
4287 {
4288 PCX86PDPT pPdptTemp;
4289 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4290 AssertRCReturn(rc, ZeroPde);
4291
4292 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4293 *pPdpe = pPdptTemp->a[iPdpt];
4294 if (pPdptTemp->a[iPdpt].n.u1Present)
4295 {
4296 PCX86PDPAE pPD;
4297 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4298 AssertRCReturn(rc, ZeroPde);
4299
4300 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4301 return pPD->a[iPD];
4302 }
4303 }
4304
4305 return ZeroPde;
4306}
4307
4308
4309/**
4310 * Gets the page directory entry for the specified address.
4311 *
4312 * @returns The page directory entry in question.
4313 * @returns A non-present entry if the page directory is not present or on an invalid page.
4314 * @param pPGM Pointer to the PGM instance data.
4315 * @param GCPtr The address.
4316 */
4317DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4318{
4319 X86PDEPAE ZeroPde = {0};
4320 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4321 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4322 if (pGuestPml4->a[iPml4].n.u1Present)
4323 {
4324 PCX86PDPT pPdptTemp;
4325 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4326 AssertRCReturn(rc, ZeroPde);
4327
4328 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4329 if (pPdptTemp->a[iPdpt].n.u1Present)
4330 {
4331 PCX86PDPAE pPD;
4332 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4333 AssertRCReturn(rc, ZeroPde);
4334
4335 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4336 return pPD->a[iPD];
4337 }
4338 }
4339 return ZeroPde;
4340}
4341
4342
4343/**
4344 * Gets the page directory entry for the specified address.
4345 *
4346 * @returns Pointer to the page directory entry in question.
4347 * @returns NULL if the page directory is not present or on an invalid page.
4348 * @param pPGM Pointer to the PGM instance data.
4349 * @param GCPtr The address.
4350 */
4351DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4352{
4353 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4354 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4355 if (pGuestPml4->a[iPml4].n.u1Present)
4356 {
4357 PCX86PDPT pPdptTemp;
4358 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4359 AssertRCReturn(rc, NULL);
4360
4361 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4362 if (pPdptTemp->a[iPdpt].n.u1Present)
4363 {
4364 PX86PDPAE pPD;
4365 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4366 AssertRCReturn(rc, NULL);
4367
4368 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4369 return &pPD->a[iPD];
4370 }
4371 }
4372 return NULL;
4373}
4374
4375
4376/**
4377 * Gets the GUEST page directory pointer for the specified address.
4378 *
4379 * @returns The page directory in question.
4380 * @returns NULL if the page directory is not present or on an invalid page.
4381 * @param pPGM Pointer to the PGM instance data.
4382 * @param GCPtr The address.
4383 * @param ppPml4e Page Map Level-4 Entry (out)
4384 * @param pPdpe Page directory pointer table entry (out)
4385 * @param piPD Receives the index into the returned page directory
4386 */
4387DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4388{
4389 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4390 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4391 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4392 if (pPml4e->n.u1Present)
4393 {
4394 PCX86PDPT pPdptTemp;
4395 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4396 AssertRCReturn(rc, NULL);
4397
4398 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4399 *pPdpe = pPdptTemp->a[iPdpt];
4400 if (pPdptTemp->a[iPdpt].n.u1Present)
4401 {
4402 PX86PDPAE pPD;
4403 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4404 AssertRCReturn(rc, NULL);
4405
4406 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4407 return pPD;
4408 }
4409 }
4410 return 0;
4411}
4412
4413#endif /* !IN_RC */
4414
4415/**
4416 * Gets the shadow page directory, 32-bit.
4417 *
4418 * @returns Pointer to the shadow 32-bit PD.
4419 * @param pPGM Pointer to the PGM instance data.
4420 */
4421DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4422{
4423 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4424}
4425
4426
4427/**
4428 * Gets the shadow page directory entry for the specified address, 32-bit.
4429 *
4430 * @returns Shadow 32-bit PDE.
4431 * @param pPGM Pointer to the PGM instance data.
4432 * @param GCPtr The address.
4433 */
4434DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4435{
4436 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4437
4438 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4439 if (!pShwPde)
4440 {
4441 X86PDE ZeroPde = {0};
4442 return ZeroPde;
4443 }
4444 return pShwPde->a[iPd];
4445}
4446
4447
4448/**
4449 * Gets the pointer to the shadow page directory entry for the specified
4450 * address, 32-bit.
4451 *
4452 * @returns Pointer to the shadow 32-bit PDE.
4453 * @param pPGM Pointer to the PGM instance data.
4454 * @param GCPtr The address.
4455 */
4456DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4457{
4458 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4459
4460 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4461 AssertReturn(pPde, NULL);
4462 return &pPde->a[iPd];
4463}
4464
4465
4466/**
4467 * Gets the shadow page pointer table, PAE.
4468 *
4469 * @returns Pointer to the shadow PAE PDPT.
4470 * @param pPGM Pointer to the PGM instance data.
4471 */
4472DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4473{
4474 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4475}
4476
4477
4478/**
4479 * Gets the shadow page directory for the specified address, PAE.
4480 *
4481 * @returns Pointer to the shadow PD.
4482 * @param pPGM Pointer to the PGM instance data.
4483 * @param GCPtr The address.
4484 */
4485DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4486{
4487 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4488 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4489
4490 if (!pPdpt->a[iPdpt].n.u1Present)
4491 return NULL;
4492
4493 /* Fetch the pgm pool shadow descriptor. */
4494 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4495 AssertReturn(pShwPde, NULL);
4496
4497 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4498}
4499
4500
4501/**
4502 * Gets the shadow page directory for the specified address, PAE.
4503 *
4504 * @returns Pointer to the shadow PD.
4505 * @param pPGM Pointer to the PGM instance data.
4506 * @param GCPtr The address.
4507 */
4508DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4509{
4510 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4511
4512 if (!pPdpt->a[iPdpt].n.u1Present)
4513 return NULL;
4514
4515 /* Fetch the pgm pool shadow descriptor. */
4516 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4517 AssertReturn(pShwPde, NULL);
4518
4519 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4520}
4521
4522
4523/**
4524 * Gets the shadow page directory entry, PAE.
4525 *
4526 * @returns PDE.
4527 * @param pPGM Pointer to the PGM instance data.
4528 * @param GCPtr The address.
4529 */
4530DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4531{
4532 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4533
4534 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4535 if (!pShwPde)
4536 {
4537 X86PDEPAE ZeroPde = {0};
4538 return ZeroPde;
4539 }
4540 return pShwPde->a[iPd];
4541}
4542
4543
4544/**
4545 * Gets the pointer to the shadow page directory entry for an address, PAE.
4546 *
4547 * @returns Pointer to the PDE.
4548 * @param pPGM Pointer to the PGM instance data.
4549 * @param GCPtr The address.
4550 */
4551DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4552{
4553 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4554
4555 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4556 AssertReturn(pPde, NULL);
4557 return &pPde->a[iPd];
4558}
4559
4560#ifndef IN_RC
4561
4562/**
4563 * Gets the shadow page map level-4 pointer.
4564 *
4565 * @returns Pointer to the shadow PML4.
4566 * @param pPGM Pointer to the PGM instance data.
4567 */
4568DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4569{
4570 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4571}
4572
4573
4574/**
4575 * Gets the shadow page map level-4 entry for the specified address.
4576 *
4577 * @returns The entry.
4578 * @param pPGM Pointer to the PGM instance data.
4579 * @param GCPtr The address.
4580 */
4581DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4582{
4583 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4584 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4585
4586 if (!pShwPml4)
4587 {
4588 X86PML4E ZeroPml4e = {0};
4589 return ZeroPml4e;
4590 }
4591 return pShwPml4->a[iPml4];
4592}
4593
4594
4595/**
4596 * Gets the pointer to the specified shadow page map level-4 entry.
4597 *
4598 * @returns The entry.
4599 * @param pPGM Pointer to the PGM instance data.
4600 * @param iPml4 The PML4 index.
4601 */
4602DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4603{
4604 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4605 if (!pShwPml4)
4606 return NULL;
4607 return &pShwPml4->a[iPml4];
4608}
4609
4610
4611/**
4612 * Gets the GUEST page directory pointer for the specified address.
4613 *
4614 * @returns The page directory in question.
4615 * @returns NULL if the page directory is not present or on an invalid page.
4616 * @param pPGM Pointer to the PGM instance data.
4617 * @param GCPtr The address.
4618 * @param piPD Receives the index into the returned page directory
4619 */
4620DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4621{
4622 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4623 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4624 if (pGuestPml4->a[iPml4].n.u1Present)
4625 {
4626 PCX86PDPT pPdptTemp;
4627 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4628 AssertRCReturn(rc, NULL);
4629
4630 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4631 if (pPdptTemp->a[iPdpt].n.u1Present)
4632 {
4633 PX86PDPAE pPD;
4634 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4635 AssertRCReturn(rc, NULL);
4636
4637 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4638 return pPD;
4639 }
4640 }
4641 return NULL;
4642}
4643
4644#endif /* !IN_RC */
4645
4646/**
4647 * Gets the page state for a physical handler.
4648 *
4649 * @returns The physical handler page state.
4650 * @param pCur The physical handler in question.
4651 */
4652DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4653{
4654 switch (pCur->enmType)
4655 {
4656 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4657 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4658
4659 case PGMPHYSHANDLERTYPE_MMIO:
4660 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4661 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4662
4663 default:
4664 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4665 }
4666}
4667
4668
4669/**
4670 * Gets the page state for a virtual handler.
4671 *
4672 * @returns The virtual handler page state.
4673 * @param pCur The virtual handler in question.
4674 * @remarks This should never be used on a hypervisor access handler.
4675 */
4676DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4677{
4678 switch (pCur->enmType)
4679 {
4680 case PGMVIRTHANDLERTYPE_WRITE:
4681 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4682 case PGMVIRTHANDLERTYPE_ALL:
4683 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4684 default:
4685 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4686 }
4687}
4688
4689
4690/**
4691 * Clears one physical page of a virtual handler
4692 *
4693 * @param pPGM Pointer to the PGM instance.
4694 * @param pCur Virtual handler structure
4695 * @param iPage Physical page index
4696 *
4697 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4698 * need to care about other handlers in the same page.
4699 */
4700DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4701{
4702 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4703
4704 /*
4705 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4706 */
4707#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4708 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4709 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4710 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4711#endif
4712 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4713 {
4714 /* We're the head of the alias chain. */
4715 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4716#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4717 AssertReleaseMsg(pRemove != NULL,
4718 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4719 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4720 AssertReleaseMsg(pRemove == pPhys2Virt,
4721 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4722 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4723 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4724 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4725#endif
4726 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4727 {
4728 /* Insert the next list in the alias chain into the tree. */
4729 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4730#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4731 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4732 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4733 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4734#endif
4735 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4736 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4737 AssertRelease(fRc);
4738 }
4739 }
4740 else
4741 {
4742 /* Locate the previous node in the alias chain. */
4743 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4744#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4745 AssertReleaseMsg(pPrev != pPhys2Virt,
4746 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4747 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4748#endif
4749 for (;;)
4750 {
4751 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4752 if (pNext == pPhys2Virt)
4753 {
4754 /* unlink. */
4755 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4756 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4757 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4758 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4759 else
4760 {
4761 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4762 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4763 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4764 }
4765 break;
4766 }
4767
4768 /* next */
4769 if (pNext == pPrev)
4770 {
4771#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4772 AssertReleaseMsg(pNext != pPrev,
4773 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4774 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4775#endif
4776 break;
4777 }
4778 pPrev = pNext;
4779 }
4780 }
4781 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4782 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4783 pPhys2Virt->offNextAlias = 0;
4784 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4785
4786 /*
4787 * Clear the ram flags for this page.
4788 */
4789 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4790 AssertReturnVoid(pPage);
4791 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4792}
4793
4794
4795/**
4796 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4797 *
4798 * @returns Pointer to the shadow page structure.
4799 * @param pPool The pool.
4800 * @param idx The pool page index.
4801 */
4802DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4803{
4804 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4805 return &pPool->aPages[idx];
4806}
4807
4808
4809#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4810/**
4811 * Clear references to guest physical memory.
4812 *
4813 * @param pPool The pool.
4814 * @param pPoolPage The pool page.
4815 * @param pPhysPage The physical guest page tracking structure.
4816 */
4817DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4818{
4819 /*
4820 * Just deal with the simple case here.
4821 */
4822# ifdef LOG_ENABLED
4823 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4824# endif
4825 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4826 if (cRefs == 1)
4827 {
4828 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4829 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4830 }
4831 else
4832 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4833 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4834}
4835#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4836
4837
4838#ifdef PGMPOOL_WITH_CACHE
4839/**
4840 * Moves the page to the head of the age list.
4841 *
4842 * This is done when the cached page is used in one way or another.
4843 *
4844 * @param pPool The pool.
4845 * @param pPage The cached page.
4846 */
4847DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4848{
4849 PVM pVM = pPool->CTX_SUFF(pVM);
4850 pgmLock(pVM);
4851
4852 /*
4853 * Move to the head of the age list.
4854 */
4855 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4856 {
4857 /* unlink */
4858 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4859 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4860 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4861 else
4862 pPool->iAgeTail = pPage->iAgePrev;
4863
4864 /* insert at head */
4865 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4866 pPage->iAgeNext = pPool->iAgeHead;
4867 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4868 pPool->iAgeHead = pPage->idx;
4869 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4870 }
4871 pgmUnlock(pVM);
4872}
4873#endif /* PGMPOOL_WITH_CACHE */
4874
4875/**
4876 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4877 *
4878 * @param pVM VM Handle.
4879 * @param pPage PGM pool page
4880 */
4881DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4882{
4883 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4884 ASMAtomicIncU32(&pPage->cLocked);
4885}
4886
4887
4888/**
4889 * Unlocks a page to allow flushing again
4890 *
4891 * @param pVM VM Handle.
4892 * @param pPage PGM pool page
4893 */
4894DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4895{
4896 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4897 Assert(pPage->cLocked);
4898 ASMAtomicDecU32(&pPage->cLocked);
4899}
4900
4901
4902/**
4903 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4904 *
4905 * @returns VBox status code.
4906 * @param pPage PGM pool page
4907 */
4908DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4909{
4910 if (pPage->cLocked)
4911 {
4912 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4913 if (pPage->cModifications)
4914 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4915 return true;
4916 }
4917 return false;
4918}
4919
4920/**
4921 * Tells if mappings are to be put into the shadow page table or not
4922 *
4923 * @returns boolean result
4924 * @param pVM VM handle.
4925 */
4926DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4927{
4928#ifdef IN_RING0
4929 /* There are no mappings in VT-x and AMD-V mode. */
4930 Assert(pPGM->fDisableMappings);
4931 return false;
4932#else
4933 return !pPGM->fDisableMappings;
4934#endif
4935}
4936
4937/** @} */
4938
4939#endif
4940
4941
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