PGMInternal.h@ 23483

Last change on this file since 23483 was 23483, checked in by vboxsync, 16 years ago
PGMPAGE: Merging u2HandlerPhysStateY into the misc field.
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File size: 202.9 KB

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1	/* $Id: PGMInternal.h 23483 2009-10-01 13:40:25Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/avl.h>
42	#include <iprt/critsect.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59	* Comment it if it will break something.
60	*/
61	#define PGM_OUT_OF_SYNC_IN_GC
62
63	/**
64	* Check and skip global PDEs for non-global flushes
65	*/
66	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68	/**
69	* Optimization for PAE page tables that are modified often
70	*/
71	#if 0 /* disabled again while debugging */
72	#ifndef IN_RC
73	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
74	#endif
75	#endif
76
77	/**
78	* Sync N pages instead of a whole page table
79	*/
80	#define PGM_SYNC_N_PAGES
81
82	/**
83	* Number of pages to sync during a page fault
84	*
85	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
86	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
87	*
88	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
89	* world switch overhead, so let's sync more.
90	*/
91	# ifdef IN_RING0
92	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
93	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
94	* but ~5% fewer faults.
95	*/
96	# define PGM_SYNC_NR_PAGES 32
97	#else
98	# define PGM_SYNC_NR_PAGES 8
99	#endif
100
101	/**
102	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
103	*/
104	#define PGM_MAX_PHYSCACHE_ENTRIES 64
105	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
106
107	/** @def PGMPOOL_WITH_CACHE
108	* Enable agressive caching using the page pool.
109	*
110	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
111	*/
112	#define PGMPOOL_WITH_CACHE
113
114	/** @def PGMPOOL_WITH_MIXED_PT_CR3
115	* When defined, we'll deal with 'uncachable' pages.
116	*/
117	#ifdef PGMPOOL_WITH_CACHE
118	# define PGMPOOL_WITH_MIXED_PT_CR3
119	#endif
120
121	/** @def PGMPOOL_WITH_MONITORING
122	* Monitor the guest pages which are shadowed.
123	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
124	* be enabled as well.
125	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
126	*/
127	#ifdef PGMPOOL_WITH_CACHE
128	# define PGMPOOL_WITH_MONITORING
129	#endif
130
131	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
132	* Tracking the of shadow pages mapping guest physical pages.
133	*
134	* This is very expensive, the current cache prototype is trying to figure out
135	* whether it will be acceptable with an agressive caching policy.
136	*/
137	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
138	# define PGMPOOL_WITH_GCPHYS_TRACKING
139	#endif
140
141	/** @def PGMPOOL_WITH_USER_TRACKING
142	* Tracking users of shadow pages. This is required for the linking of shadow page
143	* tables and physical guest addresses.
144	*/
145	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
146	# define PGMPOOL_WITH_USER_TRACKING
147	#endif
148
149	/** @def PGMPOOL_CFG_MAX_GROW
150	* The maximum number of pages to add to the pool in one go.
151	*/
152	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
153
154	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
155	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
156	*/
157	#ifdef VBOX_STRICT
158	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
159	#endif
160
161	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
162	* Enables the experimental lazy page allocation code. */
163	/# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
164
165	/** @} */
166
167
168	/** @name PDPT and PML4 flags.
169	* These are placed in the three bits available for system programs in
170	* the PDPT and PML4 entries.
171	* @{ */
172	/** The entry is a permanent one and it's must always be present.
173	* Never free such an entry. */
174	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175	/** Mapping (hypervisor allocated pagetable). */
176	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED 6
213	#define PGM_TYPE_EPT 7
214	#define PGM_TYPE_MAX PGM_TYPE_EPT
215	/** @} */
216
217	/** Macro for checking if the guest is using paging.
218	* @param uGstType PGM_TYPE_*
219	* @param uShwType PGM_TYPE_*
220	* @remark ASSUMES certain order of the PGM_TYPE_* values.
221	*/
222	#define PGM_WITH_PAGING(uGstType, uShwType) \
223	( (uGstType) >= PGM_TYPE_32BIT \
224	&& (uShwType) != PGM_TYPE_NESTED \
225	&& (uShwType) != PGM_TYPE_EPT)
226
227	/** Macro for checking if the guest supports the NX bit.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_NX(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_PAE \
234	&& (uShwType) != PGM_TYPE_NESTED \
235	&& (uShwType) != PGM_TYPE_EPT)
236
237
238	/** @def PGM_HCPHYS_2_PTR
239	* Maps a HC physical page pool address to a virtual address.
240	*
241	* @returns VBox status code.
242	* @param pVM The VM handle.
243	* @param HCPhys The HC physical address to map to a virtual one.
244	* @param ppv Where to store the virtual address. No need to cast this.
245	*
246	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
247	* small page window employeed by that function. Be careful.
248	* @remark There is no need to assert on the result.
249	*/
250	#ifdef IN_RC
251	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
252	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
253	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
255	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
256	#else
257	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
258	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
259	#endif
260
261	/** @def PGM_HCPHYS_2_PTR_BY_PGM
262	* Maps a HC physical page pool address to a virtual address.
263	*
264	* @returns VBox status code.
265	* @param pPGM The PGM instance data.
266	* @param HCPhys The HC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
270	* small page window employeed by that function. Be careful.
271	* @remark There is no need to assert on the result.
272	*/
273	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
275	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
276	#else
277	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
278	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
279	#endif
280
281	/** @def PGM_GCPHYS_2_PTR
282	* Maps a GC physical page address to a virtual address.
283	*
284	* @returns VBox status code.
285	* @param pVM The VM handle.
286	* @param GCPhys The GC physical address to map to a virtual one.
287	* @param ppv Where to store the virtual address. No need to cast this.
288	*
289	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290	* small page window employeed by that function. Be careful.
291	* @remark There is no need to assert on the result.
292	*/
293	#ifdef IN_RC
294	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
295	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
296	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
297	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
298	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
299	#else
300	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
301	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
302	#endif
303
304	/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
305	* Maps a GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pPGM Pointer to the PGM instance data.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313	* small page window employeed by that function. Be careful.
314	* @remark There is no need to assert on the result.
315	*/
316	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
317	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
318	pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
319	#else
320	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
321	PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
322	#endif
323
324	/** @def PGM_GCPHYS_2_PTR_EX
325	* Maps a unaligned GC physical page address to a virtual address.
326	*
327	* @returns VBox status code.
328	* @param pVM The VM handle.
329	* @param GCPhys The GC physical address to map to a virtual one.
330	* @param ppv Where to store the virtual address. No need to cast this.
331	*
332	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
333	* small page window employeed by that function. Be careful.
334	* @remark There is no need to assert on the result.
335	*/
336	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
339	#else
340	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
341	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
342	#endif
343
344	/** @def PGM_INVL_PG
345	* Invalidates a page.
346	*
347	* @param pVCpu The VMCPU handle.
348	* @param GCVirt The virtual address of the page to invalidate.
349	*/
350	#ifdef IN_RC
351	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
352	#elif defined(IN_RING0)
353	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354	#else
355	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356	#endif
357
358	/** @def PGM_INVL_PG_ALL_VCPU
359	* Invalidates a page on all VCPUs
360	*
361	* @param pVM The VM handle.
362	* @param GCVirt The virtual address of the page to invalidate.
363	*/
364	#ifdef IN_RC
365	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
366	#elif defined(IN_RING0)
367	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368	#else
369	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370	#endif
371
372	/** @def PGM_INVL_BIG_PG
373	* Invalidates a 4MB page directory entry.
374	*
375	* @param pVCpu The VMCPU handle.
376	* @param GCVirt The virtual address within the page directory to invalidate.
377	*/
378	#ifdef IN_RC
379	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380	#elif defined(IN_RING0)
381	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382	#else
383	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384	#endif
385
386	/** @def PGM_INVL_VCPU_TLBS()
387	* Invalidates the TLBs of the specified VCPU
388	*
389	* @param pVCpu The VMCPU handle.
390	*/
391	#ifdef IN_RC
392	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393	#elif defined(IN_RING0)
394	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395	#else
396	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397	#endif
398
399	/** @def PGM_INVL_ALL_VCPU_TLBS()
400	* Invalidates the TLBs of all VCPUs
401	*
402	* @param pVM The VM handle.
403	*/
404	#ifdef IN_RC
405	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406	#elif defined(IN_RING0)
407	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408	#else
409	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410	#endif
411
412	/** Size of the GCPtrConflict array in PGMMAPPING.
413	* @remarks Must be a power of two. */
414	#define PGMMAPPING_CONFLICT_MAX 8
415
416	/**
417	* Structure for tracking GC Mappings.
418	*
419	* This structure is used by linked list in both GC and HC.
420	*/
421	typedef struct PGMMAPPING
422	{
423	/** Pointer to next entry. */
424	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425	/** Pointer to next entry. */
426	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427	/** Pointer to next entry. */
428	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429	/** Indicate whether this entry is finalized. */
430	bool fFinalized;
431	/** Start Virtual address. */
432	RTGCPTR GCPtr;
433	/** Last Virtual address (inclusive). */
434	RTGCPTR GCPtrLast;
435	/** Range size (bytes). */
436	RTGCPTR cb;
437	/** Pointer to relocation callback function. */
438	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439	/** User argument to the callback. */
440	R3PTRTYPE(void *) pvUser;
441	/** Mapping description / name. For easing debugging. */
442	R3PTRTYPE(const char *) pszDesc;
443	/** Last 8 addresses that caused conflicts. */
444	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445	/** Number of conflicts for this hypervisor mapping. */
446	uint32_t cConflicts;
447	/** Number of page tables. */
448	uint32_t cPTs;
449
450	/** Array of page table mapping data. Each entry
451	* describes one page table. The array can be longer
452	* than the declared length.
453	*/
454	struct
455	{
456	/** The HC physical address of the page table. */
457	RTHCPHYS HCPhysPT;
458	/** The HC physical address of the first PAE page table. */
459	RTHCPHYS HCPhysPaePT0;
460	/** The HC physical address of the second PAE page table. */
461	RTHCPHYS HCPhysPaePT1;
462	/** The HC virtual address of the 32-bit page table. */
463	R3PTRTYPE(PX86PT) pPTR3;
464	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466	/** The RC virtual address of the 32-bit page table. */
467	RCPTRTYPE(PX86PT) pPTRC;
468	/** The RC virtual address of the two PAE page table. */
469	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470	/** The R0 virtual address of the 32-bit page table. */
471	R0PTRTYPE(PX86PT) pPTR0;
472	/** The R0 virtual address of the two PAE page table. */
473	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474	} aPTs[1];
475	} PGMMAPPING;
476	/** Pointer to structure for tracking GC Mappings. */
477	typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480	/**
481	* Physical page access handler structure.
482	*
483	* This is used to keep track of physical address ranges
484	* which are being monitored in some kind of way.
485	*/
486	typedef struct PGMPHYSHANDLER
487	{
488	AVLROGCPHYSNODECORE Core;
489	/** Access type. */
490	PGMPHYSHANDLERTYPE enmType;
491	/** Number of pages to update. */
492	uint32_t cPages;
493	/** Pointer to R3 callback function. */
494	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495	/** User argument for R3 handlers. */
496	R3PTRTYPE(void *) pvUserR3;
497	/** Pointer to R0 callback function. */
498	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499	/** User argument for R0 handlers. */
500	R0PTRTYPE(void *) pvUserR0;
501	/** Pointer to RC callback function. */
502	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503	/** User argument for RC handlers. */
504	RCPTRTYPE(void *) pvUserRC;
505	/** Description / Name. For easing debugging. */
506	R3PTRTYPE(const char *) pszDesc;
507	#ifdef VBOX_WITH_STATISTICS
508	/** Profiling of this handler. */
509	STAMPROFILE Stat;
510	#endif
511	} PGMPHYSHANDLER;
512	/** Pointer to a physical page access handler structure. */
513	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516	/**
517	* Cache node for the physical addresses covered by a virtual handler.
518	*/
519	typedef struct PGMPHYS2VIRTHANDLER
520	{
521	/** Core node for the tree based on physical ranges. */
522	AVLROGCPHYSNODECORE Core;
523	/** Offset from this struct to the PGMVIRTHANDLER structure. */
524	int32_t offVirtHandler;
525	/** Offset of the next alias relative to this one.
526	* Bit 0 is used for indicating whether we're in the tree.
527	* Bit 1 is used for indicating that we're the head node.
528	*/
529	int32_t offNextAlias;
530	} PGMPHYS2VIRTHANDLER;
531	/** Pointer to a phys to virtual handler structure. */
532	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535	* node is in the tree. */
536	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538	* node is in the head of an alias chain.
539	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545	/**
546	* Virtual page access handler structure.
547	*
548	* This is used to keep track of virtual address ranges
549	* which are being monitored in some kind of way.
550	*/
551	typedef struct PGMVIRTHANDLER
552	{
553	/** Core node for the tree based on virtual ranges. */
554	AVLROGCPTRNODECORE Core;
555	/** Size of the range (in bytes). */
556	RTGCPTR cb;
557	/** Number of cache pages. */
558	uint32_t cPages;
559	/** Access type. */
560	PGMVIRTHANDLERTYPE enmType;
561	/** Pointer to the RC callback function. */
562	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563	#if HC_ARCH_BITS == 64
564	RTRCPTR padding;
565	#endif
566	/** Pointer to the R3 callback function for invalidation. */
567	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568	/** Pointer to the R3 callback function. */
569	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570	/** Description / Name. For easing debugging. */
571	R3PTRTYPE(const char *) pszDesc;
572	#ifdef VBOX_WITH_STATISTICS
573	/** Profiling of this handler. */
574	STAMPROFILE Stat;
575	#endif
576	/** Array of cached physical addresses for the monitored ranged. */
577	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578	} PGMVIRTHANDLER;
579	/** Pointer to a virtual page access handler structure. */
580	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583	/**
584	* Page type.
585	*
586	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587	* @remarks This is used in the saved state, so changes to it requires bumping
588	* the saved state version.
589	* @todo So, convert to \#defines!
590	*/
591	typedef enum PGMPAGETYPE
592	{
593	/** The usual invalid zero entry. */
594	PGMPAGETYPE_INVALID = 0,
595	/** RAM page. (RWX) */
596	PGMPAGETYPE_RAM,
597	/** MMIO2 page. (RWX) */
598	PGMPAGETYPE_MMIO2,
599	/** MMIO2 page aliased over an MMIO page. (RWX)
600	* See PGMHandlerPhysicalPageAlias(). */
601	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602	/** Shadowed ROM. (RWX) */
603	PGMPAGETYPE_ROM_SHADOW,
604	/** ROM page. (R-X) */
605	PGMPAGETYPE_ROM,
606	/** MMIO page. (---) */
607	PGMPAGETYPE_MMIO,
608	/** End of valid entries. */
609	PGMPAGETYPE_END
610	} PGMPAGETYPE;
611	AssertCompile(PGMPAGETYPE_END <= 7);
612
613	/** @name Page type predicates.
614	* @{ */
615	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620	/** @} */
621
622
623	/**
624	* A Physical Guest Page tracking structure.
625	*
626	* The format of this structure is complicated because we have to fit a lot
627	* of information into as few bits as possible. The format is also subject
628	* to change (there is one comming up soon). Which means that for we'll be
629	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
630	* accesses to the structure.
631	*/
632	typedef struct PGMPAGE
633	{
634	/** The physical address and the Page ID. */
635	RTHCPHYS HCPhysAndPageID;
636	/** The page state.
637	* Only 2 bits are really needed for this. */
638	uint8_t uStateY;
639	/** The page type (PGMPAGETYPE).
640	* Only 3 bits are really needed for this. */
641	uint8_t uTypeY;
642
643	#define PGM_PAGE_WITH_U16MISCY 1
644	#ifdef PGM_PAGE_WITH_U16MISCY
645	/** Combination of:
646	* - [0-7]: u2HandlerPhysStateY - the physical handler state
647	* (PGM_PAGE_HNDL_PHYS_STATE_*).
648	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
649	* (PGM_PAGE_HNDL_VIRT_STATE_*).
650	* - [15]: fWrittenToY - flag indicating that a write monitored page was
651	* written to when set.
652	* - [10-14]: 5 unused bits.
653	* @remarks Warning! All accesses to the bits are hardcoded.
654	*/
655	RTUINT16U u16MiscY;
656	#else
657	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*).
658	* Only 2 bits are really needed for this. */
659	uint8_t uHandlerPhysStateY;
660	/** Combination of:
661	* - u2HandlerVirtStateY - the virtual handler state
662	* (PGM_PAGE_HNDL_VIRT_STATE_*).
663	* - fWrittenToY - flag indicating that a write monitored page was written to
664	* when set.
665	* - 5 unused bits. */
666	uint8_t f8MiscY;
667	#endif
668
669	/** Usage tracking (page pool). */
670	uint16_t u16TrackingY;
671	/** The number of read locks on this page. */
672	uint8_t cReadLocksY;
673	/** The number of write locks on this page. */
674	uint8_t cWriteLocksY;
675	} PGMPAGE;
676	AssertCompileSize(PGMPAGE, 16);
677	/** Pointer to a physical guest page. */
678	typedef PGMPAGE *PPGMPAGE;
679	/** Pointer to a const physical guest page. */
680	typedef const PGMPAGE *PCPGMPAGE;
681	/** Pointer to a physical guest page pointer. */
682	typedef PPGMPAGE *PPPGMPAGE;
683
684
685	/**
686	* Clears the page structure.
687	* @param pPage Pointer to the physical guest page tracking structure.
688	*/
689	#ifdef PGM_PAGE_WITH_U16MISCY
690	#define PGM_PAGE_CLEAR(pPage) \
691	do { \
692	(pPage)->HCPhysAndPageID = 0; \
693	(pPage)->uStateY = 0; \
694	(pPage)->uTypeY = 0; \
695	(pPage)->u16MiscY.u = 0; \
696	(pPage)->u16TrackingY = 0; \
697	(pPage)->cReadLocksY = 0; \
698	(pPage)->cWriteLocksY = 0; \
699	} while (0)
700	#else
701	#define PGM_PAGE_CLEAR(pPage) \
702	do { \
703	(pPage)->HCPhysAndPageID = 0; \
704	(pPage)->uStateY = 0; \
705	(pPage)->uTypeY = 0; \
706	(pPage)->uHandlerPhysStateY = 0; \
707	(pPage)->f8MiscY = 0; \
708	(pPage)->u16TrackingY = 0; \
709	(pPage)->cReadLocksY = 0; \
710	(pPage)->cWriteLocksY = 0; \
711	} while (0)
712	#endif
713
714	/**
715	* Initializes the page structure.
716	* @param pPage Pointer to the physical guest page tracking structure.
717	*/
718	#ifdef PGM_PAGE_WITH_U16MISCY
719	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
720	do { \
721	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
722	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
723	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
724	(pPage)->uStateY = (_uState); \
725	(pPage)->uTypeY = (_uType); \
726	(pPage)->u16MiscY.u = 0; \
727	(pPage)->u16TrackingY = 0; \
728	(pPage)->cReadLocksY = 0; \
729	(pPage)->cWriteLocksY = 0; \
730	} while (0)
731	#else
732	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
733	do { \
734	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
735	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
736	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
737	(pPage)->uStateY = (_uState); \
738	(pPage)->uTypeY = (_uType); \
739	(pPage)->uHandlerPhysStateY = 0; \
740	(pPage)->f8MiscY = 0; \
741	(pPage)->u16TrackingY = 0; \
742	(pPage)->cReadLocksY = 0; \
743	(pPage)->cWriteLocksY = 0; \
744	} while (0)
745	#endif
746
747	/**
748	* Initializes the page structure of a ZERO page.
749	* @param pPage Pointer to the physical guest page tracking structure.
750	* @param pVM The VM handle (for getting the zero page address).
751	* @param uType The page type (PGMPAGETYPE).
752	*/
753	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
754	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
755
756
757	/** @name The Page state, PGMPAGE::uStateY.
758	* @{ */
759	/** The zero page.
760	* This is a per-VM page that's never ever mapped writable. */
761	#define PGM_PAGE_STATE_ZERO 0
762	/** A allocated page.
763	* This is a per-VM page allocated from the page pool (or wherever
764	* we get MMIO2 pages from if the type is MMIO2).
765	*/
766	#define PGM_PAGE_STATE_ALLOCATED 1
767	/** A allocated page that's being monitored for writes.
768	* The shadow page table mappings are read-only. When a write occurs, the
769	* fWrittenTo member is set, the page remapped as read-write and the state
770	* moved back to allocated. */
771	#define PGM_PAGE_STATE_WRITE_MONITORED 2
772	/** The page is shared, aka. copy-on-write.
773	* This is a page that's shared with other VMs. */
774	#define PGM_PAGE_STATE_SHARED 3
775	/** @} */
776
777
778	/**
779	* Gets the page state.
780	* @returns page state (PGM_PAGE_STATE_*).
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
784
785	/**
786	* Sets the page state.
787	* @param pPage Pointer to the physical guest page tracking structure.
788	* @param _uState The new page state.
789	*/
790	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
791
792
793	/**
794	* Gets the host physical address of the guest page.
795	* @returns host physical address (RTHCPHYS).
796	* @param pPage Pointer to the physical guest page tracking structure.
797	*/
798	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
799
800	/**
801	* Sets the host physical address of the guest page.
802	* @param pPage Pointer to the physical guest page tracking structure.
803	* @param _HCPhys The new host physical address.
804	*/
805	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
806	do { \
807	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
808	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
809	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
810	\| (SetHCPhysTmp << (28-12)); \
811	} while (0)
812
813	/**
814	* Get the Page ID.
815	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
816	* @param pPage Pointer to the physical guest page tracking structure.
817	*/
818	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
819
820	/**
821	* Sets the Page ID.
822	* @param pPage Pointer to the physical guest page tracking structure.
823	*/
824	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
825	do { \
826	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
827	\| ((_idPage) & UINT32_C(0x0fffffff)); \
828	} while (0)
829
830	/**
831	* Get the Chunk ID.
832	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
833	* @param pPage Pointer to the physical guest page tracking structure.
834	*/
835	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
836
837	/**
838	* Get the index of the page within the allocation chunk.
839	* @returns The page index.
840	* @param pPage Pointer to the physical guest page tracking structure.
841	*/
842	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
843
844	/**
845	* Gets the page type.
846	* @returns The page type.
847	* @param pPage Pointer to the physical guest page tracking structure.
848	*/
849	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
850
851	/**
852	* Sets the page type.
853	* @param pPage Pointer to the physical guest page tracking structure.
854	* @param _enmType The new page type (PGMPAGETYPE).
855	*/
856	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
857
858	/**
859	* Checks if the page is marked for MMIO.
860	* @returns true/false.
861	* @param pPage Pointer to the physical guest page tracking structure.
862	*/
863	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
864
865	/**
866	* Checks if the page is backed by the ZERO page.
867	* @returns true/false.
868	* @param pPage Pointer to the physical guest page tracking structure.
869	*/
870	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
871
872	/**
873	* Checks if the page is backed by a SHARED page.
874	* @returns true/false.
875	* @param pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
878
879
880	/**
881	* Marks the paget as written to (for GMM change monitoring).
882	* @param pPage Pointer to the physical guest page tracking structure.
883	*/
884	#ifdef PGM_PAGE_WITH_U16MISCY
885	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
886	#else
887	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->f8MiscY \|= UINT8_C(0x80); } while (0)
888	#endif
889
890	/**
891	* Clears the written-to indicator.
892	* @param pPage Pointer to the physical guest page tracking structure.
893	*/
894	#ifdef PGM_PAGE_WITH_U16MISCY
895	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
896	#else
897	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->f8MiscY &= UINT8_C(0x7f); } while (0)
898	#endif
899
900	/**
901	* Checks if the page was marked as written-to.
902	* @returns true/false.
903	* @param pPage Pointer to the physical guest page tracking structure.
904	*/
905	#ifdef PGM_PAGE_WITH_U16MISCY
906	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
907	#else
908	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->f8MiscY & UINT8_C(0x80)) )
909	#endif
910
911
912	/** @name Physical Access Handler State values (PGMPAGE::uHandlerPhysStateY).
913	*
914	* @remarks The values are assigned in order of priority, so we can calculate
915	* the correct state for a page with different handlers installed.
916	* @{ */
917	/** No handler installed. */
918	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
919	/** Monitoring is temporarily disabled. */
920	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
921	/** Write access is monitored. */
922	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
923	/** All access is monitored. */
924	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
925	/** @} */
926
927	/**
928	* Gets the physical access handler state of a page.
929	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
930	* @param pPage Pointer to the physical guest page tracking structure.
931	*/
932	#ifdef PGM_PAGE_WITH_U16MISCY
933	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
934	( (pPage)->u16MiscY.au8[0] )
935	#else
936	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
937	( (pPage)->uHandlerPhysStateY )
938	#endif
939
940	/**
941	* Sets the physical access handler state of a page.
942	* @param pPage Pointer to the physical guest page tracking structure.
943	* @param _uState The new state value.
944	*/
945	#ifdef PGM_PAGE_WITH_U16MISCY
946	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
947	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
948	#else
949	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
950	do { (pPage)->uHandlerPhysStateY = (_uState); } while (0)
951	#endif
952
953	/**
954	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
955	* @returns true/false
956	* @param pPage Pointer to the physical guest page tracking structure.
957	*/
958	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
959	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
960
961	/**
962	* Checks if the page has any active physical access handlers.
963	* @returns true/false
964	* @param pPage Pointer to the physical guest page tracking structure.
965	*/
966	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
967	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
968
969
970	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
971	*
972	* @remarks The values are assigned in order of priority, so we can calculate
973	* the correct state for a page with different handlers installed.
974	* @{ */
975	/** No handler installed. */
976	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
977	/* 1 is reserved so the lineup is identical with the physical ones. */
978	/** Write access is monitored. */
979	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
980	/** All access is monitored. */
981	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
982	/** @} */
983
984	/**
985	* Gets the virtual access handler state of a page.
986	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
987	* @param pPage Pointer to the physical guest page tracking structure.
988	*/
989	#ifdef PGM_PAGE_WITH_U16MISCY
990	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) )
991	#else
992	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->f8MiscY & UINT8_C(0x03) )
993	#endif
994
995	/**
996	* Sets the virtual access handler state of a page.
997	* @param pPage Pointer to the physical guest page tracking structure.
998	* @param _uState The new state value.
999	*/
1000	#ifdef PGM_PAGE_WITH_U16MISCY
1001	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1002	do { \
1003	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1004	\| ((_uState) & UINT8_C(0x03)); \
1005	} while (0)
1006	#else
1007	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1008	do { \
1009	(pPage)->f8MiscY = ((pPage)->f8MiscY & UINT8_C(0xfc)) \
1010	\| ((_uState) & UINT8_C(0x03)); \
1011	} while (0)
1012	#endif
1013
1014	/**
1015	* Checks if the page has any virtual access handlers.
1016	* @returns true/false
1017	* @param pPage Pointer to the physical guest page tracking structure.
1018	*/
1019	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1020	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1021
1022	/**
1023	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1024	* virtual handlers.
1025	* @returns true/false
1026	* @param pPage Pointer to the physical guest page tracking structure.
1027	*/
1028	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1029	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1030
1031
1032
1033	/**
1034	* Checks if the page has any access handlers, including temporarily disabled ones.
1035	* @returns true/false
1036	* @param pPage Pointer to the physical guest page tracking structure.
1037	*/
1038	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1039	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1040	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1041
1042	/**
1043	* Checks if the page has any active access handlers.
1044	* @returns true/false
1045	* @param pPage Pointer to the physical guest page tracking structure.
1046	*/
1047	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1048	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1049	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1050
1051	/**
1052	* Checks if the page has any active access handlers catching all accesses.
1053	* @returns true/false
1054	* @param pPage Pointer to the physical guest page tracking structure.
1055	*/
1056	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1057	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1058	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1059
1060
1061	/** @def PGM_PAGE_GET_TRACKING
1062	* Gets the packed shadow page pool tracking data associated with a guest page.
1063	* @returns uint16_t containing the data.
1064	* @param pPage Pointer to the physical guest page tracking structure.
1065	*/
1066	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1067
1068	/** @def PGM_PAGE_SET_TRACKING
1069	* Sets the packed shadow page pool tracking data associated with a guest page.
1070	* @param pPage Pointer to the physical guest page tracking structure.
1071	* @param u16TrackingData The tracking data to store.
1072	*/
1073	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1074	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1075
1076	/** @def PGM_PAGE_GET_TD_CREFS
1077	* Gets the @a cRefs tracking data member.
1078	* @returns cRefs.
1079	* @param pPage Pointer to the physical guest page tracking structure.
1080	*/
1081	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1082	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1083
1084	/** @def PGM_PAGE_GET_TD_IDX
1085	* Gets the @a idx tracking data member.
1086	* @returns idx.
1087	* @param pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_GET_TD_IDX(pPage) \
1090	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1091
1092
1093	/** Max number of locks on a page. */
1094	#define PGM_PAGE_MAX_LOCKS 254
1095
1096	/** Get the read lock count.
1097	* @returns count.
1098	* @param pPage Pointer to the physical guest page tracking structure.
1099	*/
1100	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1101
1102	/** Get the write lock count.
1103	* @returns count.
1104	* @param pPage Pointer to the physical guest page tracking structure.
1105	*/
1106	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1107
1108	/** Decrement the read lock counter.
1109	* @param pPage Pointer to the physical guest page tracking structure.
1110	*/
1111	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1112
1113	/** Decrement the write lock counter.
1114	* @param pPage Pointer to the physical guest page tracking structure.
1115	*/
1116	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1117
1118	/** Increment the read lock counter.
1119	* @param pPage Pointer to the physical guest page tracking structure.
1120	*/
1121	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1122
1123	/** Increment the write lock counter.
1124	* @param pPage Pointer to the physical guest page tracking structure.
1125	*/
1126	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1127
1128
1129
1130	/**
1131	* Per page live save tracking data.
1132	*/
1133	typedef struct PGMLIVESAVEPAGE
1134	{
1135	/** The pass number where this page was last saved. */
1136	uint32_t uPassSaved;
1137	/** Number of times it has been dirtied. */
1138	uint32_t cDirtied : 24;
1139	/** Whether it is currently dirty. */
1140	uint32_t fDirty : 1;
1141	/** Ignore the page.
1142	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1143	* deal with these after pausing the VM and DevPCI have said it bit about
1144	* remappings. */
1145	uint32_t fIgnore : 1;
1146	/** Was a ZERO page last time around. */
1147	uint32_t fZero : 1;
1148	/** Was a SHARED page last time around. */
1149	uint32_t fShared : 1;
1150	/** Whether the page is/was write monitored in a previous pass. */
1151	uint32_t fWriteMonitored : 1;
1152	/** Whether the page is/was write monitored earlier in this pass. */
1153	uint32_t fWriteMonitoredJustNow : 1;
1154	/** Bits reserved for future use. */
1155	uint32_t u2Reserved : 2;
1156	} PGMLIVESAVEPAGE;
1157	AssertCompileSize(PGMLIVESAVEPAGE, 8);
1158	/** Pointer to the per page live save tracking data. */
1159	typedef PGMLIVESAVEPAGE *PPGMLIVESAVEPAGE;
1160
1161	/** The max value of PGMLIVESAVEPAGE::cDirtied. */
1162	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1163
1164
1165	/**
1166	* Ram range for GC Phys to HC Phys conversion.
1167	*
1168	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1169	* conversions too, but we'll let MM handle that for now.
1170	*
1171	* This structure is used by linked lists in both GC and HC.
1172	*/
1173	typedef struct PGMRAMRANGE
1174	{
1175	/** Start of the range. Page aligned. */
1176	RTGCPHYS GCPhys;
1177	/** Size of the range. (Page aligned of course). */
1178	RTGCPHYS cb;
1179	/** Pointer to the next RAM range - for R3. */
1180	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1181	/** Pointer to the next RAM range - for R0. */
1182	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1183	/** Pointer to the next RAM range - for RC. */
1184	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1185	/** PGM_RAM_RANGE_FLAGS_* flags. */
1186	uint32_t fFlags;
1187	/** Last address in the range (inclusive). Page aligned (-1). */
1188	RTGCPHYS GCPhysLast;
1189	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1190	R3PTRTYPE(void *) pvR3;
1191	/** Live save per page tracking data. */
1192	R3PTRTYPE(PPGMLIVESAVEPAGE) paLSPages;
1193	/** The range description. */
1194	R3PTRTYPE(const char *) pszDesc;
1195	/** Pointer to self - R0 pointer. */
1196	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1197	/** Pointer to self - RC pointer. */
1198	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1199	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1200	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1201	/** Array of physical guest page tracking structures. */
1202	PGMPAGE aPages[1];
1203	} PGMRAMRANGE;
1204	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1205	typedef PGMRAMRANGE *PPGMRAMRANGE;
1206
1207	/** @name PGMRAMRANGE::fFlags
1208	* @{ */
1209	/** The RAM range is floating around as an independent guest mapping. */
1210	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1211	/** Ad hoc RAM range for an ROM mapping. */
1212	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1213	/** Ad hoc RAM range for an MMIO mapping. */
1214	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1215	/** Ad hoc RAM range for an MMIO2 mapping. */
1216	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1217	/** @} */
1218
1219	/** Tests if a RAM range is an ad hoc one or not.
1220	* @returns true/false.
1221	* @param pRam The RAM range.
1222	*/
1223	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1224	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1225
1226
1227	/**
1228	* Per page tracking structure for ROM image.
1229	*
1230	* A ROM image may have a shadow page, in which case we may have two pages
1231	* backing it. This structure contains the PGMPAGE for both while
1232	* PGMRAMRANGE have a copy of the active one. It is important that these
1233	* aren't out of sync in any regard other than page pool tracking data.
1234	*/
1235	typedef struct PGMROMPAGE
1236	{
1237	/** The page structure for the virgin ROM page. */
1238	PGMPAGE Virgin;
1239	/** The page structure for the shadow RAM page. */
1240	PGMPAGE Shadow;
1241	/** The current protection setting. */
1242	PGMROMPROT enmProt;
1243	/** Live save status information. Makes use of unused alignment space. */
1244	struct
1245	{
1246	/** The previous protection value. */
1247	uint8_t u8Prot;
1248	/** Written to flag set by the handler. */
1249	bool fWrittenTo;
1250	/** Whether the shadow page is dirty or not. */
1251	bool fDirty;
1252	/** Whether it was dirtied in the recently. */
1253	bool fDirtiedRecently;
1254	} LiveSave;
1255	} PGMROMPAGE;
1256	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1257	/** Pointer to a ROM page tracking structure. */
1258	typedef PGMROMPAGE *PPGMROMPAGE;
1259
1260
1261	/**
1262	* A registered ROM image.
1263	*
1264	* This is needed to keep track of ROM image since they generally intrude
1265	* into a PGMRAMRANGE. It also keeps track of additional info like the
1266	* two page sets (read-only virgin and read-write shadow), the current
1267	* state of each page.
1268	*
1269	* Because access handlers cannot easily be executed in a different
1270	* context, the ROM ranges needs to be accessible and in all contexts.
1271	*/
1272	typedef struct PGMROMRANGE
1273	{
1274	/** Pointer to the next range - R3. */
1275	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1276	/** Pointer to the next range - R0. */
1277	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1278	/** Pointer to the next range - RC. */
1279	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1280	/** Pointer alignment */
1281	RTRCPTR RCPtrAlignment;
1282	/** Address of the range. */
1283	RTGCPHYS GCPhys;
1284	/** Address of the last byte in the range. */
1285	RTGCPHYS GCPhysLast;
1286	/** Size of the range. */
1287	RTGCPHYS cb;
1288	/** The flags (PGMPHYS_ROM_FLAGS_). /
1289	uint32_t fFlags;
1290	/** The saved state range ID. */
1291	uint8_t idSavedState;
1292	/** Alignment padding. */
1293	uint8_t au8Alignment[3];
1294	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1295	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1296	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1297	* This is used for strictness checks. */
1298	R3PTRTYPE(const void *) pvOriginal;
1299	/** The ROM description. */
1300	R3PTRTYPE(const char *) pszDesc;
1301	/** The per page tracking structures. */
1302	PGMROMPAGE aPages[1];
1303	} PGMROMRANGE;
1304	/** Pointer to a ROM range. */
1305	typedef PGMROMRANGE *PPGMROMRANGE;
1306
1307
1308	/**
1309	* A registered MMIO2 (= Device RAM) range.
1310	*
1311	* There are a few reason why we need to keep track of these
1312	* registrations. One of them is the deregistration & cleanup stuff,
1313	* while another is that the PGMRAMRANGE associated with such a region may
1314	* have to be removed from the ram range list.
1315	*
1316	* Overlapping with a RAM range has to be 100% or none at all. The pages
1317	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1318	* will be raised if a partial overlap or an overlap of ROM pages is
1319	* encountered. On an overlap we will free all the existing RAM pages and
1320	* put in the ram range pages instead.
1321	*/
1322	typedef struct PGMMMIO2RANGE
1323	{
1324	/** The owner of the range. (a device) */
1325	PPDMDEVINSR3 pDevInsR3;
1326	/** Pointer to the ring-3 mapping of the allocation. */
1327	RTR3PTR pvR3;
1328	/** Pointer to the next range - R3. */
1329	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1330	/** Whether it's mapped or not. */
1331	bool fMapped;
1332	/** Whether it's overlapping or not. */
1333	bool fOverlapping;
1334	/** The PCI region number.
1335	* @remarks This ASSUMES that nobody will ever really need to have multiple
1336	* PCI devices with matching MMIO region numbers on a single device. */
1337	uint8_t iRegion;
1338	/** The saved state range ID. */
1339	uint8_t idSavedState;
1340	#if HC_ARCH_BITS != 32
1341	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1342	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 0 : 4];
1343	#endif
1344	/** The associated RAM range. */
1345	PGMRAMRANGE RamRange;
1346	} PGMMMIO2RANGE;
1347	/** Pointer to a MMIO2 range. */
1348	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1349
1350
1351
1352
1353	/**
1354	* PGMPhysRead/Write cache entry
1355	*/
1356	typedef struct PGMPHYSCACHEENTRY
1357	{
1358	/** R3 pointer to physical page. */
1359	R3PTRTYPE(uint8_t *) pbR3;
1360	/** GC Physical address for cache entry */
1361	RTGCPHYS GCPhys;
1362	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1363	RTGCPHYS u32Padding0; /*< alignment padding. /
1364	#endif
1365	} PGMPHYSCACHEENTRY;
1366
1367	/**
1368	* PGMPhysRead/Write cache to reduce REM memory access overhead
1369	*/
1370	typedef struct PGMPHYSCACHE
1371	{
1372	/** Bitmap of valid cache entries */
1373	uint64_t aEntries;
1374	/** Cache entries */
1375	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1376	} PGMPHYSCACHE;
1377
1378
1379	/** Pointer to an allocation chunk ring-3 mapping. */
1380	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1381	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1382	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1383
1384	/**
1385	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1386	*
1387	* The primary tree (Core) uses the chunk id as key.
1388	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1389	*/
1390	typedef struct PGMCHUNKR3MAP
1391	{
1392	/** The key is the chunk id. */
1393	AVLU32NODECORE Core;
1394	/** The key is the ageing sequence number. */
1395	AVLLU32NODECORE AgeCore;
1396	/** The current age thingy. */
1397	uint32_t iAge;
1398	/** The current reference count. */
1399	uint32_t volatile cRefs;
1400	/** The current permanent reference count. */
1401	uint32_t volatile cPermRefs;
1402	/** The mapping address. */
1403	void *pv;
1404	} PGMCHUNKR3MAP;
1405
1406	/**
1407	* Allocation chunk ring-3 mapping TLB entry.
1408	*/
1409	typedef struct PGMCHUNKR3MAPTLBE
1410	{
1411	/** The chunk id. */
1412	uint32_t volatile idChunk;
1413	#if HC_ARCH_BITS == 64
1414	uint32_t u32Padding; /*< alignment padding. /
1415	#endif
1416	/** The chunk map. */
1417	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1418	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1419	#else
1420	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1421	#endif
1422	} PGMCHUNKR3MAPTLBE;
1423	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1424	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1425
1426	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1427	* @remark Must be a power of two value. */
1428	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1429
1430	/**
1431	* Allocation chunk ring-3 mapping TLB.
1432	*
1433	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1434	* At first glance this might look kinda odd since AVL trees are
1435	* supposed to give the most optimial lookup times of all trees
1436	* due to their balancing. However, take a tree with 1023 nodes
1437	* in it, that's 10 levels, meaning that most searches has to go
1438	* down 9 levels before they find what they want. This isn't fast
1439	* compared to a TLB hit. There is the factor of cache misses,
1440	* and of course the problem with trees and branch prediction.
1441	* This is why we use TLBs in front of most of the trees.
1442	*
1443	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1444	* difficult when we switch to the new inlined AVL trees (from kStuff).
1445	*/
1446	typedef struct PGMCHUNKR3MAPTLB
1447	{
1448	/** The TLB entries. */
1449	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1450	} PGMCHUNKR3MAPTLB;
1451
1452	/**
1453	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1454	* @returns Chunk TLB index.
1455	* @param idChunk The Chunk ID.
1456	*/
1457	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1458
1459
1460	/**
1461	* Ring-3 guest page mapping TLB entry.
1462	* @remarks used in ring-0 as well at the moment.
1463	*/
1464	typedef struct PGMPAGER3MAPTLBE
1465	{
1466	/** Address of the page. */
1467	RTGCPHYS volatile GCPhys;
1468	/** The guest page. */
1469	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1470	R3PTRTYPE(PPGMPAGE) volatile pPage;
1471	#else
1472	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1473	#endif
1474	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1475	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1476	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1477	#else
1478	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1479	#endif
1480	/** The address */
1481	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1482	R3PTRTYPE(void *) volatile pv;
1483	#else
1484	R3R0PTRTYPE(void *) volatile pv;
1485	#endif
1486	#if HC_ARCH_BITS == 32
1487	uint32_t u32Padding; /*< alignment padding. /
1488	#endif
1489	} PGMPAGER3MAPTLBE;
1490	/** Pointer to an entry in the HC physical TLB. */
1491	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1492
1493
1494	/** The number of entries in the ring-3 guest page mapping TLB.
1495	* @remarks The value must be a power of two. */
1496	#define PGM_PAGER3MAPTLB_ENTRIES 64
1497
1498	/**
1499	* Ring-3 guest page mapping TLB.
1500	* @remarks used in ring-0 as well at the moment.
1501	*/
1502	typedef struct PGMPAGER3MAPTLB
1503	{
1504	/** The TLB entries. */
1505	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1506	} PGMPAGER3MAPTLB;
1507	/** Pointer to the ring-3 guest page mapping TLB. */
1508	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1509
1510	/**
1511	* Calculates the index of the TLB entry for the specified guest page.
1512	* @returns Physical TLB index.
1513	* @param GCPhys The guest physical address.
1514	*/
1515	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1516
1517
1518	/**
1519	* Mapping cache usage set entry.
1520	*
1521	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1522	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1523	* cache. If it's extended to include ring-3, well, then something will
1524	* have be changed here...
1525	*/
1526	typedef struct PGMMAPSETENTRY
1527	{
1528	/** The mapping cache index. */
1529	uint16_t iPage;
1530	/** The number of references.
1531	* The max is UINT16_MAX - 1. */
1532	uint16_t cRefs;
1533	#if HC_ARCH_BITS == 64
1534	uint32_t alignment;
1535	#endif
1536	/** Pointer to the page. */
1537	RTR0PTR pvPage;
1538	/** The physical address for this entry. */
1539	RTHCPHYS HCPhys;
1540	} PGMMAPSETENTRY;
1541	/** Pointer to a mapping cache usage set entry. */
1542	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1543
1544	/**
1545	* Mapping cache usage set.
1546	*
1547	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1548	* done during exits / traps. The set is
1549	*/
1550	typedef struct PGMMAPSET
1551	{
1552	/** The number of occupied entries.
1553	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1554	* dynamic mappings. */
1555	uint32_t cEntries;
1556	/** The start of the current subset.
1557	* This is UINT32_MAX if no subset is currently open. */
1558	uint32_t iSubset;
1559	/** The index of the current CPU, only valid if the set is open. */
1560	int32_t iCpu;
1561	#if HC_ARCH_BITS == 64
1562	uint32_t alignment;
1563	#endif
1564	/** The entries. */
1565	PGMMAPSETENTRY aEntries[64];
1566	/** HCPhys -> iEntry fast lookup table.
1567	* Use PGMMAPSET_HASH for hashing.
1568	* The entries may or may not be valid, check against cEntries. */
1569	uint8_t aiHashTable[128];
1570	} PGMMAPSET;
1571	/** Pointer to the mapping cache set. */
1572	typedef PGMMAPSET *PPGMMAPSET;
1573
1574	/** PGMMAPSET::cEntries value for a closed set. */
1575	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1576
1577	/** Hash function for aiHashTable. */
1578	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1579
1580	/** The max fill size (strict builds). */
1581	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1582
1583
1584	/** @name Context neutrual page mapper TLB.
1585	*
1586	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1587	* code is writting in a kind of context neutrual way. Time will show whether
1588	* this actually makes sense or not...
1589	*
1590	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1591	* context ends up using a global mapping cache on some platforms
1592	* (darwin).
1593	*
1594	* @{ */
1595	/** @typedef PPGMPAGEMAPTLB
1596	* The page mapper TLB pointer type for the current context. */
1597	/** @typedef PPGMPAGEMAPTLB
1598	* The page mapper TLB entry pointer type for the current context. */
1599	/** @typedef PPGMPAGEMAPTLB
1600	* The page mapper TLB entry pointer pointer type for the current context. */
1601	/** @def PGM_PAGEMAPTLB_ENTRIES
1602	* The number of TLB entries in the page mapper TLB for the current context. */
1603	/** @def PGM_PAGEMAPTLB_IDX
1604	* Calculate the TLB index for a guest physical address.
1605	* @returns The TLB index.
1606	* @param GCPhys The guest physical address. */
1607	/** @typedef PPGMPAGEMAP
1608	* Pointer to a page mapper unit for current context. */
1609	/** @typedef PPPGMPAGEMAP
1610	* Pointer to a page mapper unit pointer for current context. */
1611	#ifdef IN_RC
1612	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1613	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1614	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1615	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1616	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1617	typedef void * PPGMPAGEMAP;
1618	typedef void ** PPPGMPAGEMAP;
1619	//#elif IN_RING0
1620	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1621	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1622	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1623	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1624	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1625	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1626	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1627	#else
1628	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1629	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1630	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1631	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1632	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1633	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1634	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1635	#endif
1636	/** @} */
1637
1638
1639	/** @name PGM Pool Indexes.
1640	* Aka. the unique shadow page identifier.
1641	* @{ */
1642	/** NIL page pool IDX. */
1643	#define NIL_PGMPOOL_IDX 0
1644	/** The first normal index. */
1645	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1646	/** Page directory (32-bit root). */
1647	#define PGMPOOL_IDX_PD 1
1648	/** Page Directory Pointer Table (PAE root). */
1649	#define PGMPOOL_IDX_PDPT 2
1650	/** AMD64 CR3 level index.*/
1651	#define PGMPOOL_IDX_AMD64_CR3 3
1652	/** Nested paging root.*/
1653	#define PGMPOOL_IDX_NESTED_ROOT 4
1654	/** The first normal index. */
1655	#define PGMPOOL_IDX_FIRST 5
1656	/** The last valid index. (inclusive, 14 bits) */
1657	#define PGMPOOL_IDX_LAST 0x3fff
1658	/** @} */
1659
1660	/** The NIL index for the parent chain. */
1661	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1662	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1663
1664	/**
1665	* Node in the chain linking a shadowed page to it's parent (user).
1666	*/
1667	#pragma pack(1)
1668	typedef struct PGMPOOLUSER
1669	{
1670	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1671	uint16_t iNext;
1672	/** The user page index. */
1673	uint16_t iUser;
1674	/** Index into the user table. */
1675	uint32_t iUserTable;
1676	} PGMPOOLUSER, *PPGMPOOLUSER;
1677	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1678	#pragma pack()
1679
1680
1681	/** The NIL index for the phys ext chain. */
1682	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1683
1684	/**
1685	* Node in the chain of physical cross reference extents.
1686	* @todo Calling this an 'extent' is not quite right, find a better name.
1687	*/
1688	#pragma pack(1)
1689	typedef struct PGMPOOLPHYSEXT
1690	{
1691	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1692	uint16_t iNext;
1693	/** The user page index. */
1694	uint16_t aidx[3];
1695	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1696	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1697	#pragma pack()
1698
1699
1700	/**
1701	* The kind of page that's being shadowed.
1702	*/
1703	typedef enum PGMPOOLKIND
1704	{
1705	/** The virtual invalid 0 entry. */
1706	PGMPOOLKIND_INVALID = 0,
1707	/** The entry is free (=unused). */
1708	PGMPOOLKIND_FREE,
1709
1710	/** Shw: 32-bit page table; Gst: no paging */
1711	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1712	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1713	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1714	/** Shw: 32-bit page table; Gst: 4MB page. */
1715	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1716	/** Shw: PAE page table; Gst: no paging */
1717	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1718	/** Shw: PAE page table; Gst: 32-bit page table. */
1719	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1720	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1721	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1722	/** Shw: PAE page table; Gst: PAE page table. */
1723	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1724	/** Shw: PAE page table; Gst: 2MB page. */
1725	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1726
1727	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1728	PGMPOOLKIND_32BIT_PD,
1729	/** Shw: 32-bit page directory. Gst: no paging. */
1730	PGMPOOLKIND_32BIT_PD_PHYS,
1731	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1732	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1733	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1734	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1735	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1736	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1737	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1738	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1739	/** Shw: PAE page directory; Gst: PAE page directory. */
1740	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1741	/** Shw: PAE page directory; Gst: no paging. */
1742	PGMPOOLKIND_PAE_PD_PHYS,
1743
1744	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1745	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1746	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1747	PGMPOOLKIND_PAE_PDPT,
1748	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1749	PGMPOOLKIND_PAE_PDPT_PHYS,
1750
1751	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1752	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1753	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1754	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1755	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1756	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1757	/** Shw: 64-bit page directory table; Gst: no paging */
1758	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1759
1760	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1761	PGMPOOLKIND_64BIT_PML4,
1762
1763	/** Shw: EPT page directory pointer table; Gst: no paging */
1764	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1765	/** Shw: EPT page directory table; Gst: no paging */
1766	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1767	/** Shw: EPT page table; Gst: no paging */
1768	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1769
1770	/** Shw: Root Nested paging table. */
1771	PGMPOOLKIND_ROOT_NESTED,
1772
1773	/** The last valid entry. */
1774	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1775	} PGMPOOLKIND;
1776
1777	/**
1778	* The access attributes of the page; only applies to big pages.
1779	*/
1780	typedef enum
1781	{
1782	PGMPOOLACCESS_DONTCARE = 0,
1783	PGMPOOLACCESS_USER_RW,
1784	PGMPOOLACCESS_USER_R,
1785	PGMPOOLACCESS_USER_RW_NX,
1786	PGMPOOLACCESS_USER_R_NX,
1787	PGMPOOLACCESS_SUPERVISOR_RW,
1788	PGMPOOLACCESS_SUPERVISOR_R,
1789	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1790	PGMPOOLACCESS_SUPERVISOR_R_NX
1791	} PGMPOOLACCESS;
1792
1793	/**
1794	* The tracking data for a page in the pool.
1795	*/
1796	typedef struct PGMPOOLPAGE
1797	{
1798	/** AVL node code with the (R3) physical address of this page. */
1799	AVLOHCPHYSNODECORE Core;
1800	/** Pointer to the R3 mapping of the page. */
1801	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1802	R3PTRTYPE(void *) pvPageR3;
1803	#else
1804	R3R0PTRTYPE(void *) pvPageR3;
1805	#endif
1806	/** The guest physical address. */
1807	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1808	uint32_t Alignment0;
1809	#endif
1810	RTGCPHYS GCPhys;
1811
1812	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1813	RTGCPTR pvLastAccessHandlerRip;
1814	RTGCPTR pvLastAccessHandlerFault;
1815	uint64_t cLastAccessHandlerCount;
1816
1817	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1818	uint8_t enmKind;
1819	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1820	uint8_t enmAccess;
1821	/** The index of this page. */
1822	uint16_t idx;
1823	/** The next entry in the list this page currently resides in.
1824	* It's either in the free list or in the GCPhys hash. */
1825	uint16_t iNext;
1826	#ifdef PGMPOOL_WITH_USER_TRACKING
1827	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1828	uint16_t iUserHead;
1829	/** The number of present entries. */
1830	uint16_t cPresent;
1831	/** The first entry in the table which is present. */
1832	uint16_t iFirstPresent;
1833	#endif
1834	#ifdef PGMPOOL_WITH_MONITORING
1835	/** The number of modifications to the monitored page. */
1836	uint16_t cModifications;
1837	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1838	uint16_t iModifiedNext;
1839	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1840	uint16_t iModifiedPrev;
1841	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1842	uint16_t iMonitoredNext;
1843	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1844	uint16_t iMonitoredPrev;
1845	#endif
1846	#ifdef PGMPOOL_WITH_CACHE
1847	/** The next page in the age list. */
1848	uint16_t iAgeNext;
1849	/** The previous page in the age list. */
1850	uint16_t iAgePrev;
1851	#endif /* PGMPOOL_WITH_CACHE */
1852	/** Used to indicate that the page is zeroed. */
1853	bool fZeroed;
1854	/** Used to indicate that a PT has non-global entries. */
1855	bool fSeenNonGlobal;
1856	/** Used to indicate that we're monitoring writes to the guest page. */
1857	bool fMonitored;
1858	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1859	* (All pages are in the age list.) */
1860	bool fCached;
1861	/** This is used by the R3 access handlers when invoked by an async thread.
1862	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1863	bool volatile fReusedFlushPending;
1864	/** Used to mark the page as dirty (write monitoring if temporarily off. */
1865	bool fDirty;
1866
1867	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1868	uint32_t cLocked;
1869	uint32_t idxDirty;
1870	RTGCPTR pvDirtyFault;
1871	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1872	/** Pointer to a const pool page. */
1873	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1874
1875
1876	#ifdef PGMPOOL_WITH_CACHE
1877	/** The hash table size. */
1878	# define PGMPOOL_HASH_SIZE 0x40
1879	/** The hash function. */
1880	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1881	#endif
1882
1883
1884	/**
1885	* The shadow page pool instance data.
1886	*
1887	* It's all one big allocation made at init time, except for the
1888	* pages that is. The user nodes follows immediatly after the
1889	* page structures.
1890	*/
1891	typedef struct PGMPOOL
1892	{
1893	/** The VM handle - R3 Ptr. */
1894	PVMR3 pVMR3;
1895	/** The VM handle - R0 Ptr. */
1896	PVMR0 pVMR0;
1897	/** The VM handle - RC Ptr. */
1898	PVMRC pVMRC;
1899	/** The max pool size. This includes the special IDs. */
1900	uint16_t cMaxPages;
1901	/** The current pool size. */
1902	uint16_t cCurPages;
1903	/** The head of the free page list. */
1904	uint16_t iFreeHead;
1905	/* Padding. */
1906	uint16_t u16Padding;
1907	#ifdef PGMPOOL_WITH_USER_TRACKING
1908	/** Head of the chain of free user nodes. */
1909	uint16_t iUserFreeHead;
1910	/** The number of user nodes we've allocated. */
1911	uint16_t cMaxUsers;
1912	/** The number of present page table entries in the entire pool. */
1913	uint32_t cPresent;
1914	/** Pointer to the array of user nodes - RC pointer. */
1915	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1916	/** Pointer to the array of user nodes - R3 pointer. */
1917	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1918	/** Pointer to the array of user nodes - R0 pointer. */
1919	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1920	#endif /* PGMPOOL_WITH_USER_TRACKING */
1921	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1922	/** Head of the chain of free phys ext nodes. */
1923	uint16_t iPhysExtFreeHead;
1924	/** The number of user nodes we've allocated. */
1925	uint16_t cMaxPhysExts;
1926	/** Pointer to the array of physical xref extent - RC pointer. */
1927	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1928	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1929	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1930	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1931	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1932	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1933	#ifdef PGMPOOL_WITH_CACHE
1934	/** Hash table for GCPhys addresses. */
1935	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1936	/** The head of the age list. */
1937	uint16_t iAgeHead;
1938	/** The tail of the age list. */
1939	uint16_t iAgeTail;
1940	/** Set if the cache is enabled. */
1941	bool fCacheEnabled;
1942	/** Alignment padding. */
1943	bool afPadding1[3];
1944	#endif /* PGMPOOL_WITH_CACHE */
1945	#ifdef PGMPOOL_WITH_MONITORING
1946	/** Head of the list of modified pages. */
1947	uint16_t iModifiedHead;
1948	/** The current number of modified pages. */
1949	uint16_t cModifiedPages;
1950	/** Access handler, RC. */
1951	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1952	/** Access handler, R0. */
1953	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1954	/** Access handler, R3. */
1955	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1956	/** The access handler description (R3 ptr). */
1957	R3PTRTYPE(const char *) pszAccessHandler;
1958	# if HC_ARCH_BITS == 32
1959	/** Alignment padding. */
1960	uint32_t u32Padding2;
1961	# endif
1962	/* Next available slot. */
1963	uint32_t idxFreeDirtyPage;
1964	/* Number of active dirty pages. */
1965	uint32_t cDirtyPages;
1966	/* Array of current dirty pgm pool page indices. */
1967	uint16_t aIdxDirtyPages[16];
1968	uint64_t aDirtyPages[16][512];
1969	#endif /* PGMPOOL_WITH_MONITORING */
1970	/** The number of pages currently in use. */
1971	uint16_t cUsedPages;
1972	#ifdef VBOX_WITH_STATISTICS
1973	/** The high water mark for cUsedPages. */
1974	uint16_t cUsedPagesHigh;
1975	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1976	/** Profiling pgmPoolAlloc(). */
1977	STAMPROFILEADV StatAlloc;
1978	/** Profiling pgmR3PoolClearDoIt(). */
1979	STAMPROFILE StatClearAll;
1980	/** Profiling pgmR3PoolReset(). */
1981	STAMPROFILE StatR3Reset;
1982	/** Profiling pgmPoolFlushPage(). */
1983	STAMPROFILE StatFlushPage;
1984	/** Profiling pgmPoolFree(). */
1985	STAMPROFILE StatFree;
1986	/** Counting explicit flushes by PGMPoolFlushPage(). */
1987	STAMCOUNTER StatForceFlushPage;
1988	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1989	STAMCOUNTER StatForceFlushDirtyPage;
1990	/** Counting flushes for reused pages. */
1991	STAMCOUNTER StatForceFlushReused;
1992	/** Profiling time spent zeroing pages. */
1993	STAMPROFILE StatZeroPage;
1994	# ifdef PGMPOOL_WITH_USER_TRACKING
1995	/** Profiling of pgmPoolTrackDeref. */
1996	STAMPROFILE StatTrackDeref;
1997	/** Profiling pgmTrackFlushGCPhysPT. */
1998	STAMPROFILE StatTrackFlushGCPhysPT;
1999	/** Profiling pgmTrackFlushGCPhysPTs. */
2000	STAMPROFILE StatTrackFlushGCPhysPTs;
2001	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2002	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2003	/** Number of times we've been out of user records. */
2004	STAMCOUNTER StatTrackFreeUpOneUser;
2005	/** Nr of flushed entries. */
2006	STAMCOUNTER StatTrackFlushEntry;
2007	/** Nr of updated entries. */
2008	STAMCOUNTER StatTrackFlushEntryKeep;
2009	# endif
2010	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2011	/** Profiling deref activity related tracking GC physical pages. */
2012	STAMPROFILE StatTrackDerefGCPhys;
2013	/** Number of linear searches for a HCPhys in the ram ranges. */
2014	STAMCOUNTER StatTrackLinearRamSearches;
2015	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2016	STAMCOUNTER StamTrackPhysExtAllocFailures;
2017	# endif
2018	# ifdef PGMPOOL_WITH_MONITORING
2019	/** Profiling the RC/R0 access handler. */
2020	STAMPROFILE StatMonitorRZ;
2021	/** Times we've failed interpreting the instruction. */
2022	STAMCOUNTER StatMonitorRZEmulateInstr;
2023	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2024	STAMPROFILE StatMonitorRZFlushPage;
2025	/* Times we've detected a page table reinit. */
2026	STAMCOUNTER StatMonitorRZFlushReinit;
2027	/** Counting flushes for pages that are modified too often. */
2028	STAMCOUNTER StatMonitorRZFlushModOverflow;
2029	/** Times we've detected fork(). */
2030	STAMCOUNTER StatMonitorRZFork;
2031	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2032	STAMPROFILE StatMonitorRZHandled;
2033	/** Times we've failed interpreting a patch code instruction. */
2034	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2035	/** Times we've failed interpreting a patch code instruction during flushing. */
2036	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2037	/** The number of times we've seen rep prefixes we can't handle. */
2038	STAMCOUNTER StatMonitorRZRepPrefix;
2039	/** Profiling the REP STOSD cases we've handled. */
2040	STAMPROFILE StatMonitorRZRepStosd;
2041	/** Nr of handled PT faults. */
2042	STAMCOUNTER StatMonitorRZFaultPT;
2043	/** Nr of handled PD faults. */
2044	STAMCOUNTER StatMonitorRZFaultPD;
2045	/** Nr of handled PDPT faults. */
2046	STAMCOUNTER StatMonitorRZFaultPDPT;
2047	/** Nr of handled PML4 faults. */
2048	STAMCOUNTER StatMonitorRZFaultPML4;
2049
2050	/** Profiling the R3 access handler. */
2051	STAMPROFILE StatMonitorR3;
2052	/** Times we've failed interpreting the instruction. */
2053	STAMCOUNTER StatMonitorR3EmulateInstr;
2054	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2055	STAMPROFILE StatMonitorR3FlushPage;
2056	/* Times we've detected a page table reinit. */
2057	STAMCOUNTER StatMonitorR3FlushReinit;
2058	/** Counting flushes for pages that are modified too often. */
2059	STAMCOUNTER StatMonitorR3FlushModOverflow;
2060	/** Times we've detected fork(). */
2061	STAMCOUNTER StatMonitorR3Fork;
2062	/** Profiling the R3 access we've handled (except REP STOSD). */
2063	STAMPROFILE StatMonitorR3Handled;
2064	/** The number of times we've seen rep prefixes we can't handle. */
2065	STAMCOUNTER StatMonitorR3RepPrefix;
2066	/** Profiling the REP STOSD cases we've handled. */
2067	STAMPROFILE StatMonitorR3RepStosd;
2068	/** Nr of handled PT faults. */
2069	STAMCOUNTER StatMonitorR3FaultPT;
2070	/** Nr of handled PD faults. */
2071	STAMCOUNTER StatMonitorR3FaultPD;
2072	/** Nr of handled PDPT faults. */
2073	STAMCOUNTER StatMonitorR3FaultPDPT;
2074	/** Nr of handled PML4 faults. */
2075	STAMCOUNTER StatMonitorR3FaultPML4;
2076	/** The number of times we're called in an async thread an need to flush. */
2077	STAMCOUNTER StatMonitorR3Async;
2078	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2079	STAMCOUNTER StatResetDirtyPages;
2080	/** Times we've called pgmPoolAddDirtyPage. */
2081	STAMCOUNTER StatDirtyPage;
2082	/** Times we've had to flush duplicates for dirty page management. */
2083	STAMCOUNTER StatDirtyPageDupFlush;
2084	/** Times we've had to flush because of overflow. */
2085	STAMCOUNTER StatDirtyPageOverFlowFlush;
2086
2087	/** The high wather mark for cModifiedPages. */
2088	uint16_t cModifiedPagesHigh;
2089	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
2090	# endif
2091	# ifdef PGMPOOL_WITH_CACHE
2092	/** The number of cache hits. */
2093	STAMCOUNTER StatCacheHits;
2094	/** The number of cache misses. */
2095	STAMCOUNTER StatCacheMisses;
2096	/** The number of times we've got a conflict of 'kind' in the cache. */
2097	STAMCOUNTER StatCacheKindMismatches;
2098	/** Number of times we've been out of pages. */
2099	STAMCOUNTER StatCacheFreeUpOne;
2100	/** The number of cacheable allocations. */
2101	STAMCOUNTER StatCacheCacheable;
2102	/** The number of uncacheable allocations. */
2103	STAMCOUNTER StatCacheUncacheable;
2104	# endif
2105	#else
2106	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
2107	#endif
2108	/** The AVL tree for looking up a page by its HC physical address. */
2109	AVLOHCPHYSTREE HCPhysTree;
2110	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
2111	/** Array of pages. (cMaxPages in length)
2112	* The Id is the index into thist array.
2113	*/
2114	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2115	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2116	#ifdef PGMPOOL_WITH_MONITORING
2117	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2118	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2119	#endif
2120	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2121	#ifdef VBOX_WITH_STATISTICS
2122	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2123	#endif
2124	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2125
2126
2127	/** @def PGMPOOL_PAGE_2_PTR
2128	* Maps a pool page pool into the current context.
2129	*
2130	* @returns VBox status code.
2131	* @param pVM The VM handle.
2132	* @param pPage The pool page.
2133	*
2134	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2135	* small page window employeed by that function. Be careful.
2136	* @remark There is no need to assert on the result.
2137	*/
2138	#if defined(IN_RC)
2139	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2140	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2141	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2142	#elif defined(VBOX_STRICT)
2143	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2144	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2145	{
2146	Assert(pPage && pPage->pvPageR3);
2147	return pPage->pvPageR3;
2148	}
2149	#else
2150	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2151	#endif
2152
2153	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2154	* Maps a pool page pool into the current context.
2155	*
2156	* @returns VBox status code.
2157	* @param pPGM Pointer to the PGM instance data.
2158	* @param pPage The pool page.
2159	*
2160	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2161	* small page window employeed by that function. Be careful.
2162	* @remark There is no need to assert on the result.
2163	*/
2164	#if defined(IN_RC)
2165	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2166	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2167	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2168	#else
2169	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2170	#endif
2171
2172	/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2173	* Maps a pool page pool into the current context.
2174	*
2175	* @returns VBox status code.
2176	* @param pPGM Pointer to the PGMCPU instance data.
2177	* @param pPage The pool page.
2178	*
2179	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2180	* small page window employeed by that function. Be careful.
2181	* @remark There is no need to assert on the result.
2182	*/
2183	#if defined(IN_RC)
2184	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2185	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2186	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2187	#else
2188	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2189	#endif
2190
2191
2192	/** @name Per guest page tracking data.
2193	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2194	* is to use more bits for it and split it up later on. But for now we'll play
2195	* safe and change as little as possible.
2196	*
2197	* The 16-bit word has two parts:
2198	*
2199	* The first 14-bit forms the @a idx field. It is either the index of a page in
2200	* the shadow page pool, or and index into the extent list.
2201	*
2202	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2203	* shadow page pool references to the page. If cRefs equals
2204	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2205	* (misnomer) table and not the shadow page pool.
2206	*
2207	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2208	* the 16-bit word.
2209	*
2210	* @{ */
2211	/** The shift count for getting to the cRefs part. */
2212	#define PGMPOOL_TD_CREFS_SHIFT 14
2213	/** The mask applied after shifting the tracking data down by
2214	* PGMPOOL_TD_CREFS_SHIFT. */
2215	#define PGMPOOL_TD_CREFS_MASK 0x3
2216	/** The cRef value used to indiciate that the idx is the head of a
2217	* physical cross reference list. */
2218	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2219	/** The shift used to get idx. */
2220	#define PGMPOOL_TD_IDX_SHIFT 0
2221	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2222	#define PGMPOOL_TD_IDX_MASK 0x3fff
2223	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2224	* simply too many mappings of this page. */
2225	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2226
2227	/** @def PGMPOOL_TD_MAKE
2228	* Makes a 16-bit tracking data word.
2229	*
2230	* @returns tracking data.
2231	* @param cRefs The @a cRefs field. Must be within bounds!
2232	* @param idx The @a idx field. Must also be within bounds! */
2233	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2234
2235	/** @def PGMPOOL_TD_GET_CREFS
2236	* Get the @a cRefs field from a tracking data word.
2237	*
2238	* @returns The @a cRefs field
2239	* @param u16 The tracking data word. */
2240	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2241
2242	/** @def PGMPOOL_TD_GET_IDX
2243	* Get the @a idx field from a tracking data word.
2244	*
2245	* @returns The @a idx field
2246	* @param u16 The tracking data word. */
2247	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2248	/** @} */
2249
2250
2251	/**
2252	* Trees are using self relative offsets as pointers.
2253	* So, all its data, including the root pointer, must be in the heap for HC and GC
2254	* to have the same layout.
2255	*/
2256	typedef struct PGMTREES
2257	{
2258	/** Physical access handlers (AVL range+offsetptr tree). */
2259	AVLROGCPHYSTREE PhysHandlers;
2260	/** Virtual access handlers (AVL range + GC ptr tree). */
2261	AVLROGCPTRTREE VirtHandlers;
2262	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2263	AVLROGCPHYSTREE PhysToVirtHandlers;
2264	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2265	AVLROGCPTRTREE HyperVirtHandlers;
2266	} PGMTREES;
2267	/** Pointer to PGM trees. */
2268	typedef PGMTREES *PPGMTREES;
2269
2270
2271	/** @name Paging mode macros
2272	* @{ */
2273	#ifdef IN_RC
2274	# define PGM_CTX(a,b) a##RC##b
2275	# define PGM_CTX_STR(a,b) a "GC" b
2276	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2277	#else
2278	# ifdef IN_RING3
2279	# define PGM_CTX(a,b) a##R3##b
2280	# define PGM_CTX_STR(a,b) a "R3" b
2281	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2282	# else
2283	# define PGM_CTX(a,b) a##R0##b
2284	# define PGM_CTX_STR(a,b) a "R0" b
2285	# define PGM_CTX_DECL(type) VMMDECL(type)
2286	# endif
2287	#endif
2288
2289	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2290	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2291	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2292	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2293	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2294	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2295	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2296	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2297	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2298	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2299	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2300	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2301	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2302	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2303	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2304	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2305	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2306
2307	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2308	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2309	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2310	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2311	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2312	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2313	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2314	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2315	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2316	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2317	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2318	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2319	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2320	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2321	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2322	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2323	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2324
2325	/* Shw_Gst */
2326	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2327	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2328	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2329	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2330	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2331	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2332	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2333	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2334	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2335	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2336	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2337	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2338	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2339	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2340	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2341	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2342	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2343	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2344	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2345
2346	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2347	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2348	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2349	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2350	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2351	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2352	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2353	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2354	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2355	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2356	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2357	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2358	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2359	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2360	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2361	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2362	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2363	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2364	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2365	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2366	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2367	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2368	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2369	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2370	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2371	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2372	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2373	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2374	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2375	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2376	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2377	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2378	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2379	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2380	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2381	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2382	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2383
2384	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2385	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2386	/** @} */
2387
2388	/**
2389	* Data for each paging mode.
2390	*/
2391	typedef struct PGMMODEDATA
2392	{
2393	/** The guest mode type. */
2394	uint32_t uGstType;
2395	/** The shadow mode type. */
2396	uint32_t uShwType;
2397
2398	/** @name Function pointers for Shadow paging.
2399	* @{
2400	*/
2401	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2402	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2403	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2404	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2405
2406	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2407	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2408
2409	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2410	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2411	/** @} */
2412
2413	/** @name Function pointers for Guest paging.
2414	* @{
2415	*/
2416	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2417	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2418	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2419	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2420	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2421	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2422	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2423	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2424	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2425	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2426	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2427	/** @} */
2428
2429	/** @name Function pointers for Both Shadow and Guest paging.
2430	* @{
2431	*/
2432	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2433	/* no pfnR3BthTrap0eHandler */
2434	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2435	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2436	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2437	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2438	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2439	#ifdef VBOX_STRICT
2440	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2441	#endif
2442	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2443	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2444
2445	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2446	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2447	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2448	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2449	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2450	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2451	#ifdef VBOX_STRICT
2452	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2453	#endif
2454	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2455	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2456
2457	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2458	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2459	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2460	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2461	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2462	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2463	#ifdef VBOX_STRICT
2464	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2465	#endif
2466	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2467	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2468	/** @} */
2469	} PGMMODEDATA, *PPGMMODEDATA;
2470
2471
2472
2473	/**
2474	* Converts a PGM pointer into a VM pointer.
2475	* @returns Pointer to the VM structure the PGM is part of.
2476	* @param pPGM Pointer to PGM instance data.
2477	*/
2478	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2479
2480	/**
2481	* PGM Data (part of VM)
2482	*/
2483	typedef struct PGM
2484	{
2485	/** Offset to the VM structure. */
2486	RTINT offVM;
2487	/** Offset of the PGMCPU structure relative to VMCPU. */
2488	RTINT offVCpuPGM;
2489
2490	/** @cfgm{RamPreAlloc, boolean, false}
2491	* Indicates whether the base RAM should all be allocated before starting
2492	* the VM (default), or if it should be allocated when first written to.
2493	*/
2494	bool fRamPreAlloc;
2495	/** Indicates whether write monitoring is currently in use.
2496	* This is used to prevent conflicts between live saving and page sharing
2497	* detection. */
2498	bool fPhysWriteMonitoringEngaged;
2499	/** Alignment padding. */
2500	bool afAlignment0[2];
2501
2502	/*
2503	* This will be redefined at least two more times before we're done, I'm sure.
2504	* The current code is only to get on with the coding.
2505	* - 2004-06-10: initial version, bird.
2506	* - 2004-07-02: 1st time, bird.
2507	* - 2004-10-18: 2nd time, bird.
2508	* - 2005-07-xx: 3rd time, bird.
2509	*/
2510
2511	/** The host paging mode. (This is what SUPLib reports.) */
2512	SUPPAGINGMODE enmHostMode;
2513
2514	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2515	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2516	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2517	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2518
2519	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2520	RTGCPHYS GCPhys4MBPSEMask;
2521
2522	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2523	* This is sorted by physical address and contains no overlapping ranges. */
2524	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2525	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2526	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2527	/** RC pointer corresponding to PGM::pRamRangesR3. */
2528	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2529	/** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2530	* range is linked or unlinked. */
2531	uint32_t volatile idRamRangesGen;
2532
2533	/** Pointer to the list of ROM ranges - for R3.
2534	* This is sorted by physical address and contains no overlapping ranges. */
2535	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2536	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2537	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2538	/** RC pointer corresponding to PGM::pRomRangesR3. */
2539	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2540	#if HC_ARCH_BITS == 64
2541	/** Alignment padding. */
2542	RTRCPTR GCPtrPadding2;
2543	#endif
2544
2545	/** Pointer to the list of MMIO2 ranges - for R3.
2546	* Registration order. */
2547	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2548
2549	/** PGM offset based trees - R3 Ptr. */
2550	R3PTRTYPE(PPGMTREES) pTreesR3;
2551	/** PGM offset based trees - R0 Ptr. */
2552	R0PTRTYPE(PPGMTREES) pTreesR0;
2553	/** PGM offset based trees - RC Ptr. */
2554	RCPTRTYPE(PPGMTREES) pTreesRC;
2555
2556	/** Linked list of GC mappings - for RC.
2557	* The list is sorted ascending on address.
2558	*/
2559	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2560	/** Linked list of GC mappings - for HC.
2561	* The list is sorted ascending on address.
2562	*/
2563	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2564	/** Linked list of GC mappings - for R0.
2565	* The list is sorted ascending on address.
2566	*/
2567	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2568
2569	/** Pointer to the 5 page CR3 content mapping.
2570	* The first page is always the CR3 (in some form) while the 4 other pages
2571	* are used of the PDs in PAE mode. */
2572	RTGCPTR GCPtrCR3Mapping;
2573	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2574	uint32_t u32Alignment1;
2575	#endif
2576
2577	/** Indicates that PGMR3FinalizeMappings has been called and that further
2578	* PGMR3MapIntermediate calls will be rejected. */
2579	bool fFinalizedMappings;
2580	/** If set no conflict checks are required. (boolean) */
2581	bool fMappingsFixed;
2582	/** If set, then no mappings are put into the shadow page table. (boolean) */
2583	bool fDisableMappings;
2584	/** Size of fixed mapping */
2585	uint32_t cbMappingFixed;
2586	/** Base address (GC) of fixed mapping */
2587	RTGCPTR GCPtrMappingFixed;
2588	/** The address of the previous RAM range mapping. */
2589	RTGCPTR GCPtrPrevRamRangeMapping;
2590
2591	/** @name Intermediate Context
2592	* @{ */
2593	/** Pointer to the intermediate page directory - Normal. */
2594	R3PTRTYPE(PX86PD) pInterPD;
2595	/** Pointer to the intermedate page tables - Normal.
2596	* There are two page tables, one for the identity mapping and one for
2597	* the host context mapping (of the core code). */
2598	R3PTRTYPE(PX86PT) apInterPTs[2];
2599	/** Pointer to the intermedate page tables - PAE. */
2600	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2601	/** Pointer to the intermedate page directory - PAE. */
2602	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2603	/** Pointer to the intermedate page directory - PAE. */
2604	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2605	/** Pointer to the intermedate page-map level 4 - AMD64. */
2606	R3PTRTYPE(PX86PML4) pInterPaePML4;
2607	/** Pointer to the intermedate page directory - AMD64. */
2608	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2609	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2610	RTHCPHYS HCPhysInterPD;
2611	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2612	RTHCPHYS HCPhysInterPaePDPT;
2613	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2614	RTHCPHYS HCPhysInterPaePML4;
2615	/** @} */
2616
2617	/** Base address of the dynamic page mapping area.
2618	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2619	*/
2620	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2621	/** The index of the last entry used in the dynamic page mapping area. */
2622	RTUINT iDynPageMapLast;
2623	/** Cache containing the last entries in the dynamic page mapping area.
2624	* The cache size is covering half of the mapping area. */
2625	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2626	/** Keep a lock counter for the full (!) mapping area. */
2627	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2628
2629	/** The address of the ring-0 mapping cache if we're making use of it. */
2630	RTR0PTR pvR0DynMapUsed;
2631	#if HC_ARCH_BITS == 32
2632	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2633	uint32_t u32Alignment2;
2634	#endif
2635
2636	/** PGM critical section.
2637	* This protects the physical & virtual access handlers, ram ranges,
2638	* and the page flag updating (some of it anyway).
2639	*/
2640	PDMCRITSECT CritSect;
2641
2642	/** Pointer to SHW+GST mode data (function pointers).
2643	* The index into this table is made up from */
2644	R3PTRTYPE(PPGMMODEDATA) paModeData;
2645
2646	/** Shadow Page Pool - R3 Ptr. */
2647	R3PTRTYPE(PPGMPOOL) pPoolR3;
2648	/** Shadow Page Pool - R0 Ptr. */
2649	R0PTRTYPE(PPGMPOOL) pPoolR0;
2650	/** Shadow Page Pool - RC Ptr. */
2651	RCPTRTYPE(PPGMPOOL) pPoolRC;
2652
2653	/** We're not in a state which permits writes to guest memory.
2654	* (Only used in strict builds.) */
2655	bool fNoMorePhysWrites;
2656	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2657	bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2658
2659	/**
2660	* Data associated with managing the ring-3 mappings of the allocation chunks.
2661	*/
2662	struct
2663	{
2664	/** The chunk tree, ordered by chunk id. */
2665	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2666	R3PTRTYPE(PAVLU32NODECORE) pTree;
2667	#else
2668	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2669	#endif
2670	/** The chunk age tree, ordered by ageing sequence number. */
2671	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2672	/** The chunk mapping TLB. */
2673	PGMCHUNKR3MAPTLB Tlb;
2674	/** The number of mapped chunks. */
2675	uint32_t c;
2676	/** The maximum number of mapped chunks.
2677	* @cfgm PGM/MaxRing3Chunks */
2678	uint32_t cMax;
2679	/** The current time. */
2680	uint32_t iNow;
2681	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2682	uint32_t AgeingCountdown;
2683	} ChunkR3Map;
2684
2685	/**
2686	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2687	*/
2688	PGMPAGER3MAPTLB PhysTlbHC;
2689
2690	/** @name The zero page.
2691	* @{ */
2692	/** The host physical address of the zero page. */
2693	RTHCPHYS HCPhysZeroPg;
2694	/** The ring-3 mapping of the zero page. */
2695	RTR3PTR pvZeroPgR3;
2696	/** The ring-0 mapping of the zero page. */
2697	RTR0PTR pvZeroPgR0;
2698	/** The GC mapping of the zero page. */
2699	RTGCPTR pvZeroPgRC;
2700	#if GC_ARCH_BITS != 32
2701	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2702	#endif
2703	/** @}*/
2704
2705	/** The number of handy pages. */
2706	uint32_t cHandyPages;
2707	/**
2708	* Array of handy pages.
2709	*
2710	* This array is used in a two way communication between pgmPhysAllocPage
2711	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2712	* an intermediary.
2713	*
2714	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2715	* (The current size of 32 pages, means 128 KB of handy memory.)
2716	*/
2717	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2718
2719	/**
2720	* Live save data.
2721	*/
2722	struct
2723	{
2724	/** The number of ready pages. */
2725	uint32_t cReadyPages;
2726	/** The number of dirty pages. */
2727	uint32_t cDirtyPages;
2728	/** The number of monitored pages. */
2729	uint32_t cMonitoredPages;
2730	/** The number of ignored pages. */
2731	uint32_t cIgnoredPages;
2732	/** The number of MMIO2 pages. */
2733	uint32_t cMmio2Pages;
2734	/** Indicates that a live save operation is active. */
2735	bool fActive;
2736	/** Padding. */
2737	bool afReserved[3];
2738	} LiveSave;
2739
2740	/** @name Error injection.
2741	* @{ */
2742	/** Inject handy page allocation errors pretending we're completely out of
2743	* memory. */
2744	bool volatile fErrInjHandyPages;
2745	/** Padding. */
2746	bool afReserved[7];
2747	/** @} */
2748
2749	/** @name Release Statistics
2750	* @{ */
2751	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2752	uint32_t cPrivatePages; /*< The number of private pages. /
2753	uint32_t cSharedPages; /*< The number of shared pages. /
2754	uint32_t cZeroPages; /*< The number of zero backed pages. /
2755	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
2756	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
2757
2758	/** The number of times we were forced to change the hypervisor region location. */
2759	STAMCOUNTER cRelocations;
2760	/** @} */
2761
2762	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2763	/* R3 only: */
2764	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2765	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2766
2767	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2768	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2769	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2770	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2771	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2772	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2773	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2774	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2775	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2776	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2777	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2778	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2779	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2780	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2781	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2782	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2783	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2784	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2785	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2786	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2787	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2788	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2789
2790	/* RC only: */
2791	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache misses /
2792	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache hits /
2793	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2794	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2795
2796	STAMCOUNTER StatRZPhysRead;
2797	STAMCOUNTER StatRZPhysReadBytes;
2798	STAMCOUNTER StatRZPhysWrite;
2799	STAMCOUNTER StatRZPhysWriteBytes;
2800	STAMCOUNTER StatR3PhysRead;
2801	STAMCOUNTER StatR3PhysReadBytes;
2802	STAMCOUNTER StatR3PhysWrite;
2803	STAMCOUNTER StatR3PhysWriteBytes;
2804	STAMCOUNTER StatRCPhysRead;
2805	STAMCOUNTER StatRCPhysReadBytes;
2806	STAMCOUNTER StatRCPhysWrite;
2807	STAMCOUNTER StatRCPhysWriteBytes;
2808
2809	STAMCOUNTER StatRZPhysSimpleRead;
2810	STAMCOUNTER StatRZPhysSimpleReadBytes;
2811	STAMCOUNTER StatRZPhysSimpleWrite;
2812	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2813	STAMCOUNTER StatR3PhysSimpleRead;
2814	STAMCOUNTER StatR3PhysSimpleReadBytes;
2815	STAMCOUNTER StatR3PhysSimpleWrite;
2816	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2817	STAMCOUNTER StatRCPhysSimpleRead;
2818	STAMCOUNTER StatRCPhysSimpleReadBytes;
2819	STAMCOUNTER StatRCPhysSimpleWrite;
2820	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2821
2822	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2823	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2824	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2825	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2826	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2827	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2828	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2829	# endif
2830	#endif
2831	} PGM;
2832	#ifndef IN_TSTVMSTRUCTGC /* HACK */
2833	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2834	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2835	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2836	AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2837	AssertCompileMemberAlignment(PGM, CritSect, 8);
2838	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2839	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2840	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2841	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2842	AssertCompileMemberAlignment(PGM, cRelocations, 8);
2843	#endif /* !IN_TSTVMSTRUCTGC */
2844	/** Pointer to the PGM instance data. */
2845	typedef PGM *PPGM;
2846
2847
2848	/**
2849	* Converts a PGMCPU pointer into a VM pointer.
2850	* @returns Pointer to the VM structure the PGM is part of.
2851	* @param pPGM Pointer to PGMCPU instance data.
2852	*/
2853	#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2854
2855	/**
2856	* Converts a PGMCPU pointer into a PGM pointer.
2857	* @returns Pointer to the VM structure the PGM is part of.
2858	* @param pPGM Pointer to PGMCPU instance data.
2859	*/
2860	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2861
2862	/**
2863	* PGMCPU Data (part of VMCPU).
2864	*/
2865	typedef struct PGMCPU
2866	{
2867	/** Offset to the VM structure. */
2868	RTINT offVM;
2869	/** Offset to the VMCPU structure. */
2870	RTINT offVCpu;
2871	/** Offset of the PGM structure relative to VMCPU. */
2872	RTINT offPGM;
2873	RTINT uPadding0; /*< structure size alignment. /
2874
2875	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2876	/** Automatically tracked physical memory mapping set.
2877	* Ring-0 and strict raw-mode builds. */
2878	PGMMAPSET AutoSet;
2879	#endif
2880
2881	/** A20 gate mask.
2882	* Our current approach to A20 emulation is to let REM do it and don't bother
2883	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2884	* But whould need arrise, we'll subject physical addresses to this mask. */
2885	RTGCPHYS GCPhysA20Mask;
2886	/** A20 gate state - boolean! */
2887	bool fA20Enabled;
2888
2889	/** What needs syncing (PGM_SYNC_*).
2890	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2891	* PGMFlushTLB, and PGMR3Load. */
2892	RTUINT fSyncFlags;
2893
2894	/** The shadow paging mode. */
2895	PGMMODE enmShadowMode;
2896	/** The guest paging mode. */
2897	PGMMODE enmGuestMode;
2898
2899	/** The current physical address representing in the guest CR3 register. */
2900	RTGCPHYS GCPhysCR3;
2901
2902	/** @name 32-bit Guest Paging.
2903	* @{ */
2904	/** The guest's page directory, R3 pointer. */
2905	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2906	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2907	/** The guest's page directory, R0 pointer. */
2908	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2909	#endif
2910	/** The guest's page directory, static RC mapping. */
2911	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2912	/** @} */
2913
2914	/** @name PAE Guest Paging.
2915	* @{ */
2916	/** The guest's page directory pointer table, static RC mapping. */
2917	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2918	/** The guest's page directory pointer table, R3 pointer. */
2919	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2920	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2921	/** The guest's page directory pointer table, R0 pointer. */
2922	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2923	#endif
2924
2925	/** The guest's page directories, R3 pointers.
2926	* These are individual pointers and don't have to be adjecent.
2927	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2928	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2929	/** The guest's page directories, R0 pointers.
2930	* Same restrictions as apGstPaePDsR3. */
2931	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2932	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2933	#endif
2934	/** The guest's page directories, static GC mapping.
2935	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2936	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2937	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2938	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2939	RTGCPHYS aGCPhysGstPaePDs[4];
2940	/** The physical addresses of the monitored guest page directories (PAE). */
2941	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2942	/** @} */
2943
2944	/** @name AMD64 Guest Paging.
2945	* @{ */
2946	/** The guest's page directory pointer table, R3 pointer. */
2947	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2948	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2949	/** The guest's page directory pointer table, R0 pointer. */
2950	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2951	#endif
2952	/** @} */
2953
2954	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2955	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2956	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2957	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2958	/** Pointer to the page of the current active CR3 - RC Ptr. */
2959	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2960	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2961	uint32_t iShwUser;
2962	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2963	uint32_t iShwUserTable;
2964	# if HC_ARCH_BITS == 64
2965	RTRCPTR alignment6; /*< structure size alignment. /
2966	# endif
2967	/** @} */
2968
2969	/** @name Function pointers for Shadow paging.
2970	* @{
2971	*/
2972	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2973	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2974	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2975	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2976
2977	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2978	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2979
2980	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2981	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2982
2983	/** @} */
2984
2985	/** @name Function pointers for Guest paging.
2986	* @{
2987	*/
2988	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2989	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2990	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2991	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2992	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2993	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2994	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2995	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2996	#if HC_ARCH_BITS == 64
2997	RTRCPTR alignment3; /*< structure size alignment. /
2998	#endif
2999
3000	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3001	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3002	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3003	/** @} */
3004
3005	/** @name Function pointers for Both Shadow and Guest paging.
3006	* @{
3007	*/
3008	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3009	/* no pfnR3BthTrap0eHandler */
3010	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3011	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3012	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3013	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3014	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3015	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3016	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3017	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3018
3019	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
3020	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3021	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3022	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3023	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3024	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3025	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3026	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3027	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3028
3029	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
3030	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3031	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3032	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3033	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3034	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3035	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3036	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3037	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3038	RTRCPTR alignment2; /*< structure size alignment. /
3039	/** @} */
3040
3041	/** For saving stack space, the disassembler state is allocated here instead of
3042	* on the stack.
3043	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3044	union
3045	{
3046	/** The disassembler scratch space. */
3047	DISCPUSTATE DisState;
3048	/** Padding. */
3049	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3050	};
3051
3052	/* Count the number of pgm pool access handler calls. */
3053	uint64_t cPoolAccessHandler;
3054
3055	/** @name Release Statistics
3056	* @{ */
3057	/** The number of times the guest has switched mode since last reset or statistics reset. */
3058	STAMCOUNTER cGuestModeChanges;
3059	/** @} */
3060
3061	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3062	/** @name Statistics
3063	* @{ */
3064	/** RC: Which statistic this \#PF should be attributed to. */
3065	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3066	RTRCPTR padding0;
3067	/** R0: Which statistic this \#PF should be attributed to. */
3068	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3069	RTR0PTR padding1;
3070
3071	/* Common */
3072	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3073	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3074
3075	/* R0 only: */
3076	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
3077	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
3078	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
3079	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3080	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
3081	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
3082	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
3083	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
3084	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3085	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
3086	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
3087	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
3088	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
3089	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
3090	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
3091	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
3092	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
3093	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
3094	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
3095	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
3096	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
3097	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
3098	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
3099	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
3100	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
3101	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
3102
3103	/* RZ only: */
3104	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3105	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3106	STAMPROFILE StatRZTrap0eTimeSyncPT;
3107	STAMPROFILE StatRZTrap0eTimeMapping;
3108	STAMPROFILE StatRZTrap0eTimeOutOfSync;
3109	STAMPROFILE StatRZTrap0eTimeHandlers;
3110	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3111	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3112	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3113	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3114	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3115	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3116	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3117	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3118	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3119	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3120	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3121	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3122	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3123	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3124	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3125	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
3126	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3127	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3128	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3129	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3130	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3131	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
3132	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
3133	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
3134	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
3135	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
3136	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
3137	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
3138	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
3139	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
3140	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
3141	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
3142	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
3143	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
3144	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
3145	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3146	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3147	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
3148	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3149	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3150	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3151	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3152	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3153
3154	/* HC - R3 and (maybe) R0: */
3155
3156	/* RZ & R3: */
3157	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3158	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3159	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3160	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3161	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3162	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3163	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3164	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3165	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3166	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3167	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3168	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3169	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3170	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3171	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3172	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3173	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3174	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3175	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3176	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3177	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3178	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3179	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3180	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3181	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3182	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3183	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3184	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3185	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3186	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3187	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3188	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3189	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3190	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3191	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3192	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
3193	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
3194	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in #PF. /
3195	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF. /
3196	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3197	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3198	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3199	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3200	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3201	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3202	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3203
3204	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3205	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3206	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3207	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3208	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3209	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3210	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3211	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3212	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3213	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3214	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3215	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3216	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3217	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3218	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3219	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3220	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3221	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3222	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3223	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3224	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3225	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3226	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3227	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3228	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3229	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3230	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3231	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3232	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3233	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3234	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3235	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3236	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3237	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3238	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
3239	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
3240	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in #PF. /
3241	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in #PF. /
3242	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3243	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3244	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3245	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3246	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3247	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3248	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3249	/** @} */
3250	#endif /* VBOX_WITH_STATISTICS */
3251	} PGMCPU;
3252	/** Pointer to the per-cpu PGM data. */
3253	typedef PGMCPU *PPGMCPU;
3254
3255
3256	/** @name PGM::fSyncFlags Flags
3257	* @{
3258	*/
3259	/** Updates the virtual access handler state bit in PGMPAGE. */
3260	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3261	/** Always sync CR3. */
3262	#define PGM_SYNC_ALWAYS RT_BIT(1)
3263	/** Check monitoring on next CR3 (re)load and invalidate page.
3264	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3265	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3266	/** Check guest mapping in SyncCR3. */
3267	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3268	/** Clear the page pool (a light weight flush). */
3269	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3270	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3271	/** @} */
3272
3273
3274	RT_C_DECLS_BEGIN
3275
3276	int pgmLock(PVM pVM);
3277	void pgmUnlock(PVM pVM);
3278
3279	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3280	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3281	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3282	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3283	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3284
3285	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3286	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3287	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3288	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3289	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3290	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3291	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3292	#else
3293	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3294	#endif
3295	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3296	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3297
3298	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3299	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3300	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3301	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3302	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3303	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3304	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3305	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3306	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3307	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3308	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3309	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3310	#ifdef IN_RING3
3311	void pgmR3PhysRelinkRamRanges(PVM pVM);
3312	int pgmR3PhysRamPreAllocate(PVM pVM);
3313	int pgmR3PhysRamReset(PVM pVM);
3314	int pgmR3PhysRomReset(PVM pVM);
3315	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3316
3317	int pgmR3PoolInit(PVM pVM);
3318	void pgmR3PoolRelocate(PVM pVM);
3319	void pgmR3PoolReset(PVM pVM);
3320	void pgmR3PoolClearAll(PVM pVM);
3321
3322	#endif /* IN_RING3 */
3323	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3324	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3325	#endif
3326	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3327
3328	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3329	{
3330	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3331	}
3332
3333	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3334	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3335	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3336	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3337	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3338	int pgmPoolSyncCR3(PVMCPU pVCpu);
3339	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3340	int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3341	DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3342	{
3343	return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3344	}
3345
3346	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3347	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3348	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3349	#ifdef PGMPOOL_WITH_MONITORING
3350	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3351	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3352	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3353	#endif
3354
3355	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3356	void pgmPoolResetDirtyPages(PVM pVM);
3357
3358	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3359	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3360
3361	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3362	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3363	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3364	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3365
3366	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3367	#ifndef IN_RC
3368	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3369	#endif
3370	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3371
3372	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3373	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3374	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3375	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3376
3377	RT_C_DECLS_END
3378
3379
3380	/**
3381	* Gets the PGMRAMRANGE structure for a guest page.
3382	*
3383	* @returns Pointer to the RAM range on success.
3384	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3385	*
3386	* @param pPGM PGM handle.
3387	* @param GCPhys The GC physical address.
3388	*/
3389	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3390	{
3391	/*
3392	* Optimize for the first range.
3393	*/
3394	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3395	RTGCPHYS off = GCPhys - pRam->GCPhys;
3396	if (RT_UNLIKELY(off >= pRam->cb))
3397	{
3398	do
3399	{
3400	pRam = pRam->CTX_SUFF(pNext);
3401	if (RT_UNLIKELY(!pRam))
3402	break;
3403	off = GCPhys - pRam->GCPhys;
3404	} while (off >= pRam->cb);
3405	}
3406	return pRam;
3407	}
3408
3409
3410	/**
3411	* Gets the PGMPAGE structure for a guest page.
3412	*
3413	* @returns Pointer to the page on success.
3414	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3415	*
3416	* @param pPGM PGM handle.
3417	* @param GCPhys The GC physical address.
3418	*/
3419	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3420	{
3421	/*
3422	* Optimize for the first range.
3423	*/
3424	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3425	RTGCPHYS off = GCPhys - pRam->GCPhys;
3426	if (RT_UNLIKELY(off >= pRam->cb))
3427	{
3428	do
3429	{
3430	pRam = pRam->CTX_SUFF(pNext);
3431	if (RT_UNLIKELY(!pRam))
3432	return NULL;
3433	off = GCPhys - pRam->GCPhys;
3434	} while (off >= pRam->cb);
3435	}
3436	return &pRam->aPages[off >> PAGE_SHIFT];
3437	}
3438
3439
3440	/**
3441	* Gets the PGMPAGE structure for a guest page.
3442	*
3443	* Old Phys code: Will make sure the page is present.
3444	*
3445	* @returns VBox status code.
3446	* @retval VINF_SUCCESS and a valid *ppPage on success.
3447	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3448	*
3449	* @param pPGM PGM handle.
3450	* @param GCPhys The GC physical address.
3451	* @param ppPage Where to store the page pointer on success.
3452	*/
3453	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3454	{
3455	/*
3456	* Optimize for the first range.
3457	*/
3458	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3459	RTGCPHYS off = GCPhys - pRam->GCPhys;
3460	if (RT_UNLIKELY(off >= pRam->cb))
3461	{
3462	do
3463	{
3464	pRam = pRam->CTX_SUFF(pNext);
3465	if (RT_UNLIKELY(!pRam))
3466	{
3467	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3468	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3469	}
3470	off = GCPhys - pRam->GCPhys;
3471	} while (off >= pRam->cb);
3472	}
3473	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3474	return VINF_SUCCESS;
3475	}
3476
3477
3478
3479
3480	/**
3481	* Gets the PGMPAGE structure for a guest page.
3482	*
3483	* Old Phys code: Will make sure the page is present.
3484	*
3485	* @returns VBox status code.
3486	* @retval VINF_SUCCESS and a valid *ppPage on success.
3487	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3488	*
3489	* @param pPGM PGM handle.
3490	* @param GCPhys The GC physical address.
3491	* @param ppPage Where to store the page pointer on success.
3492	* @param ppRamHint Where to read and store the ram list hint.
3493	* The caller initializes this to NULL before the call.
3494	*/
3495	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3496	{
3497	RTGCPHYS off;
3498	PPGMRAMRANGE pRam = *ppRamHint;
3499	if ( !pRam
3500	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3501	{
3502	pRam = pPGM->CTX_SUFF(pRamRanges);
3503	off = GCPhys - pRam->GCPhys;
3504	if (RT_UNLIKELY(off >= pRam->cb))
3505	{
3506	do
3507	{
3508	pRam = pRam->CTX_SUFF(pNext);
3509	if (RT_UNLIKELY(!pRam))
3510	{
3511	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3512	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3513	}
3514	off = GCPhys - pRam->GCPhys;
3515	} while (off >= pRam->cb);
3516	}
3517	*ppRamHint = pRam;
3518	}
3519	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3520	return VINF_SUCCESS;
3521	}
3522
3523
3524	/**
3525	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3526	*
3527	* @returns Pointer to the page on success.
3528	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3529	*
3530	* @param pPGM PGM handle.
3531	* @param GCPhys The GC physical address.
3532	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3533	*/
3534	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3535	{
3536	/*
3537	* Optimize for the first range.
3538	*/
3539	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3540	RTGCPHYS off = GCPhys - pRam->GCPhys;
3541	if (RT_UNLIKELY(off >= pRam->cb))
3542	{
3543	do
3544	{
3545	pRam = pRam->CTX_SUFF(pNext);
3546	if (RT_UNLIKELY(!pRam))
3547	return NULL;
3548	off = GCPhys - pRam->GCPhys;
3549	} while (off >= pRam->cb);
3550	}
3551	*ppRam = pRam;
3552	return &pRam->aPages[off >> PAGE_SHIFT];
3553	}
3554
3555
3556	/**
3557	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3558	*
3559	* @returns Pointer to the page on success.
3560	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3561	*
3562	* @param pPGM PGM handle.
3563	* @param GCPhys The GC physical address.
3564	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3565	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3566	*/
3567	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3568	{
3569	/*
3570	* Optimize for the first range.
3571	*/
3572	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3573	RTGCPHYS off = GCPhys - pRam->GCPhys;
3574	if (RT_UNLIKELY(off >= pRam->cb))
3575	{
3576	do
3577	{
3578	pRam = pRam->CTX_SUFF(pNext);
3579	if (RT_UNLIKELY(!pRam))
3580	{
3581	ppRam = NULL; / Shut up silly GCC warnings. */
3582	ppPage = NULL; / ditto */
3583	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3584	}
3585	off = GCPhys - pRam->GCPhys;
3586	} while (off >= pRam->cb);
3587	}
3588	*ppRam = pRam;
3589	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3590	return VINF_SUCCESS;
3591	}
3592
3593
3594	/**
3595	* Convert GC Phys to HC Phys.
3596	*
3597	* @returns VBox status.
3598	* @param pPGM PGM handle.
3599	* @param GCPhys The GC physical address.
3600	* @param pHCPhys Where to store the corresponding HC physical address.
3601	*
3602	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3603	* Avoid when writing new code!
3604	*/
3605	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3606	{
3607	PPGMPAGE pPage;
3608	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3609	if (RT_FAILURE(rc))
3610	return rc;
3611	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3612	return VINF_SUCCESS;
3613	}
3614
3615	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3616
3617	/**
3618	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3619	* optimizes access to pages already in the set.
3620	*
3621	* @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3622	* @param pPGM Pointer to the PVM instance data.
3623	* @param HCPhys The physical address of the page.
3624	* @param ppv Where to store the mapping address.
3625	*/
3626	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3627	{
3628	PVM pVM = PGM2VM(pPGM);
3629	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3630	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3631
3632	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3633	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3634	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3635
3636	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3637	unsigned iEntry = pSet->aiHashTable[iHash];
3638	if ( iEntry < pSet->cEntries
3639	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3640	{
3641	*ppv = pSet->aEntries[iEntry].pvPage;
3642	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3643	}
3644	else
3645	{
3646	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3647	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3648	}
3649
3650	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3651	return VINF_SUCCESS;
3652	}
3653
3654
3655	/**
3656	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3657	* access to pages already in the set.
3658	*
3659	* @returns See PGMDynMapGCPage.
3660	* @param pPGM Pointer to the PVM instance data.
3661	* @param HCPhys The physical address of the page.
3662	* @param ppv Where to store the mapping address.
3663	*/
3664	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3665	{
3666	PVM pVM = PGM2VM(pPGM);
3667	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3668
3669	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3670	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3671
3672	/*
3673	* Get the ram range.
3674	*/
3675	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3676	RTGCPHYS off = GCPhys - pRam->GCPhys;
3677	if (RT_UNLIKELY(off >= pRam->cb
3678	/** @todo \|\| page state stuff */))
3679	{
3680	/* This case is not counted into StatR0DynMapGCPageInl. */
3681	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3682	return PGMDynMapGCPage(pVM, GCPhys, ppv);
3683	}
3684
3685	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3686	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3687
3688	/*
3689	* pgmR0DynMapHCPageInlined with out stats.
3690	*/
3691	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3692	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3693	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3694
3695	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3696	unsigned iEntry = pSet->aiHashTable[iHash];
3697	if ( iEntry < pSet->cEntries
3698	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3699	{
3700	*ppv = pSet->aEntries[iEntry].pvPage;
3701	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3702	}
3703	else
3704	{
3705	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3706	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3707	}
3708
3709	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3710	return VINF_SUCCESS;
3711	}
3712
3713
3714	/**
3715	* Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3716	* access to pages already in the set.
3717	*
3718	* @returns See PGMDynMapGCPage.
3719	* @param pPGM Pointer to the PVM instance data.
3720	* @param HCPhys The physical address of the page.
3721	* @param ppv Where to store the mapping address.
3722	*/
3723	DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3724	{
3725	PVM pVM = PGM2VM(pPGM);
3726	PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t )VMMGetCpu(pVM) + pPGM->offVCpuPGM); / very pretty ;-) */
3727
3728	STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3729
3730	/*
3731	* Get the ram range.
3732	*/
3733	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3734	RTGCPHYS off = GCPhys - pRam->GCPhys;
3735	if (RT_UNLIKELY(off >= pRam->cb
3736	/** @todo \|\| page state stuff */))
3737	{
3738	/* This case is not counted into StatR0DynMapGCPageInl. */
3739	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3740	return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3741	}
3742
3743	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3744	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3745
3746	/*
3747	* pgmR0DynMapHCPageInlined with out stats.
3748	*/
3749	PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3750	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3751	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3752
3753	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3754	unsigned iEntry = pSet->aiHashTable[iHash];
3755	if ( iEntry < pSet->cEntries
3756	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3757	{
3758	ppv = (void )((uintptr_t)pSet->aEntries[iEntry].pvPage \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3759	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3760	}
3761	else
3762	{
3763	STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3764	pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3765	ppv = (void )((uintptr_t)*ppv \| (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3766	}
3767
3768	STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3769	return VINF_SUCCESS;
3770	}
3771
3772	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3773	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3774
3775	/**
3776	* Maps the page into current context (RC and maybe R0).
3777	*
3778	* @returns pointer to the mapping.
3779	* @param pVM Pointer to the PGM instance data.
3780	* @param pPage The page.
3781	*/
3782	DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3783	{
3784	if (pPage->idx >= PGMPOOL_IDX_FIRST)
3785	{
3786	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3787	void *pv;
3788	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3789	pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3790	# else
3791	PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3792	# endif
3793	return pv;
3794	}
3795	AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3796	}
3797
3798	/**
3799	* Temporarily maps one host page specified by HC physical address, returning
3800	* pointer within the page.
3801	*
3802	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3803	* reused after 8 mappings (or perhaps a few more if you score with the cache).
3804	*
3805	* @returns The address corresponding to HCPhys.
3806	* @param pPGM Pointer to the PVM instance data.
3807	* @param HCPhys HC Physical address of the page.
3808	*/
3809	DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3810	{
3811	void *pv;
3812	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3813	pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3814	# else
3815	PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3816	# endif
3817	pv = (void *)((uintptr_t)pv \| ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3818	return pv;
3819	}
3820
3821	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 \|\| IN_RC */
3822	#ifndef IN_RC
3823
3824	/**
3825	* Queries the Physical TLB entry for a physical guest page,
3826	* attempting to load the TLB entry if necessary.
3827	*
3828	* @returns VBox status code.
3829	* @retval VINF_SUCCESS on success
3830	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3831	*
3832	* @param pPGM The PGM instance handle.
3833	* @param GCPhys The address of the guest page.
3834	* @param ppTlbe Where to store the pointer to the TLB entry.
3835	*/
3836	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3837	{
3838	int rc;
3839	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3840	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3841	{
3842	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3843	rc = VINF_SUCCESS;
3844	}
3845	else
3846	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3847	*ppTlbe = pTlbe;
3848	return rc;
3849	}
3850
3851
3852	/**
3853	* Queries the Physical TLB entry for a physical guest page,
3854	* attempting to load the TLB entry if necessary.
3855	*
3856	* @returns VBox status code.
3857	* @retval VINF_SUCCESS on success
3858	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3859	*
3860	* @param pPGM The PGM instance handle.
3861	* @param pPage Pointer to the PGMPAGE structure corresponding to
3862	* GCPhys.
3863	* @param GCPhys The address of the guest page.
3864	* @param ppTlbe Where to store the pointer to the TLB entry.
3865	*/
3866	DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3867	{
3868	int rc;
3869	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3870	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3871	{
3872	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3873	rc = VINF_SUCCESS;
3874	}
3875	else
3876	rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3877	*ppTlbe = pTlbe;
3878	return rc;
3879	}
3880
3881	#endif /* !IN_RC */
3882
3883	/**
3884	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3885	* Takes PSE-36 into account.
3886	*
3887	* @returns guest physical address
3888	* @param pPGM Pointer to the PGM instance data.
3889	* @param Pde Guest Pde
3890	*/
3891	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3892	{
3893	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3894	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3895
3896	return GCPhys & pPGM->GCPhys4MBPSEMask;
3897	}
3898
3899
3900	/**
3901	* Gets the page directory entry for the specified address (32-bit paging).
3902	*
3903	* @returns The page directory entry in question.
3904	* @param pPGM Pointer to the PGM instance data.
3905	* @param GCPtr The address.
3906	*/
3907	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3908	{
3909	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3910	PCX86PD pGuestPD = NULL;
3911	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3912	if (RT_FAILURE(rc))
3913	{
3914	X86PDE ZeroPde = {0};
3915	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3916	}
3917	#else
3918	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3919	# ifdef IN_RING3
3920	if (!pGuestPD)
3921	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3922	# endif
3923	#endif
3924	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3925	}
3926
3927
3928	/**
3929	* Gets the address of a specific page directory entry (32-bit paging).
3930	*
3931	* @returns Pointer the page directory entry in question.
3932	* @param pPGM Pointer to the PGM instance data.
3933	* @param GCPtr The address.
3934	*/
3935	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3936	{
3937	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3938	PX86PD pGuestPD = NULL;
3939	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3940	AssertRCReturn(rc, NULL);
3941	#else
3942	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3943	# ifdef IN_RING3
3944	if (!pGuestPD)
3945	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3946	# endif
3947	#endif
3948	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3949	}
3950
3951
3952	/**
3953	* Gets the address the guest page directory (32-bit paging).
3954	*
3955	* @returns Pointer the page directory entry in question.
3956	* @param pPGM Pointer to the PGM instance data.
3957	*/
3958	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3959	{
3960	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3961	PX86PD pGuestPD = NULL;
3962	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3963	AssertRCReturn(rc, NULL);
3964	#else
3965	PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3966	# ifdef IN_RING3
3967	if (!pGuestPD)
3968	pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3969	# endif
3970	#endif
3971	return pGuestPD;
3972	}
3973
3974
3975	/**
3976	* Gets the guest page directory pointer table.
3977	*
3978	* @returns Pointer to the page directory in question.
3979	* @returns NULL if the page directory is not present or on an invalid page.
3980	* @param pPGM Pointer to the PGM instance data.
3981	*/
3982	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3983	{
3984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3985	PX86PDPT pGuestPDPT = NULL;
3986	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3987	AssertRCReturn(rc, NULL);
3988	#else
3989	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3990	# ifdef IN_RING3
3991	if (!pGuestPDPT)
3992	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3993	# endif
3994	#endif
3995	return pGuestPDPT;
3996	}
3997
3998
3999	/**
4000	* Gets the guest page directory pointer table entry for the specified address.
4001	*
4002	* @returns Pointer to the page directory in question.
4003	* @returns NULL if the page directory is not present or on an invalid page.
4004	* @param pPGM Pointer to the PGM instance data.
4005	* @param GCPtr The address.
4006	*/
4007	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4008	{
4009	AssertGCPtr32(GCPtr);
4010
4011	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4012	PX86PDPT pGuestPDPT = 0;
4013	int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
4014	AssertRCReturn(rc, 0);
4015	#else
4016	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
4017	# ifdef IN_RING3
4018	if (!pGuestPDPT)
4019	pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
4020	# endif
4021	#endif
4022	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
4023	}
4024
4025
4026	/**
4027	* Gets the page directory for the specified address.
4028	*
4029	* @returns Pointer to the page directory in question.
4030	* @returns NULL if the page directory is not present or on an invalid page.
4031	* @param pPGM Pointer to the PGM instance data.
4032	* @param GCPtr The address.
4033	*/
4034	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
4035	{
4036	AssertGCPtr32(GCPtr);
4037
4038	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4039	AssertReturn(pGuestPDPT, NULL);
4040	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4041	if (pGuestPDPT->a[iPdpt].n.u1Present)
4042	{
4043	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4044	PX86PDPAE pGuestPD = NULL;
4045	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4046	AssertRCReturn(rc, NULL);
4047	#else
4048	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4049	if ( !pGuestPD
4050	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4051	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4052	#endif
4053	return pGuestPD;
4054	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
4055	}
4056	return NULL;
4057	}
4058
4059
4060	/**
4061	* Gets the page directory entry for the specified address.
4062	*
4063	* @returns Pointer to the page directory entry in question.
4064	* @returns NULL if the page directory is not present or on an invalid page.
4065	* @param pPGM Pointer to the PGM instance data.
4066	* @param GCPtr The address.
4067	*/
4068	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4069	{
4070	AssertGCPtr32(GCPtr);
4071
4072	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4073	AssertReturn(pGuestPDPT, NULL);
4074	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4075	if (pGuestPDPT->a[iPdpt].n.u1Present)
4076	{
4077	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4078	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4079	PX86PDPAE pGuestPD = NULL;
4080	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4081	AssertRCReturn(rc, NULL);
4082	#else
4083	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4084	if ( !pGuestPD
4085	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4086	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4087	#endif
4088	return &pGuestPD->a[iPD];
4089	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
4090	}
4091	return NULL;
4092	}
4093
4094
4095	/**
4096	* Gets the page directory entry for the specified address.
4097	*
4098	* @returns The page directory entry in question.
4099	* @returns A non-present entry if the page directory is not present or on an invalid page.
4100	* @param pPGM Pointer to the PGM instance data.
4101	* @param GCPtr The address.
4102	*/
4103	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4104	{
4105	AssertGCPtr32(GCPtr);
4106	X86PDEPAE ZeroPde = {0};
4107	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4108	if (RT_LIKELY(pGuestPDPT))
4109	{
4110	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4111	if (pGuestPDPT->a[iPdpt].n.u1Present)
4112	{
4113	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4114	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4115	PX86PDPAE pGuestPD = NULL;
4116	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4117	AssertRCReturn(rc, ZeroPde);
4118	#else
4119	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4120	if ( !pGuestPD
4121	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4122	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4123	#endif
4124	return pGuestPD->a[iPD];
4125	}
4126	}
4127	return ZeroPde;
4128	}
4129
4130
4131	/**
4132	* Gets the page directory pointer table entry for the specified address
4133	* and returns the index into the page directory
4134	*
4135	* @returns Pointer to the page directory in question.
4136	* @returns NULL if the page directory is not present or on an invalid page.
4137	* @param pPGM Pointer to the PGM instance data.
4138	* @param GCPtr The address.
4139	* @param piPD Receives the index into the returned page directory
4140	* @param pPdpe Receives the page directory pointer entry. Optional.
4141	*/
4142	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4143	{
4144	AssertGCPtr32(GCPtr);
4145
4146	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4147	AssertReturn(pGuestPDPT, NULL);
4148	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4149	if (pPdpe)
4150	*pPdpe = pGuestPDPT->a[iPdpt];
4151	if (pGuestPDPT->a[iPdpt].n.u1Present)
4152	{
4153	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4154	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4155	PX86PDPAE pGuestPD = NULL;
4156	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4157	AssertRCReturn(rc, NULL);
4158	#else
4159	PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4160	if ( !pGuestPD
4161	\|\| (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4162	pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4163	#endif
4164	*piPD = iPD;
4165	return pGuestPD;
4166	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4167	}
4168	return NULL;
4169	}
4170
4171	#ifndef IN_RC
4172
4173	/**
4174	* Gets the page map level-4 pointer for the guest.
4175	*
4176	* @returns Pointer to the PML4 page.
4177	* @param pPGM Pointer to the PGM instance data.
4178	*/
4179	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4180	{
4181	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4182	PX86PML4 pGuestPml4;
4183	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4184	AssertRCReturn(rc, NULL);
4185	#else
4186	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4187	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4188	if (!pGuestPml4)
4189	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4190	# endif
4191	Assert(pGuestPml4);
4192	#endif
4193	return pGuestPml4;
4194	}
4195
4196
4197	/**
4198	* Gets the pointer to a page map level-4 entry.
4199	*
4200	* @returns Pointer to the PML4 entry.
4201	* @param pPGM Pointer to the PGM instance data.
4202	* @param iPml4 The index.
4203	*/
4204	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4205	{
4206	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4207	PX86PML4 pGuestPml4;
4208	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4209	AssertRCReturn(rc, NULL);
4210	#else
4211	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4212	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4213	if (!pGuestPml4)
4214	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4215	# endif
4216	Assert(pGuestPml4);
4217	#endif
4218	return &pGuestPml4->a[iPml4];
4219	}
4220
4221
4222	/**
4223	* Gets a page map level-4 entry.
4224	*
4225	* @returns The PML4 entry.
4226	* @param pPGM Pointer to the PGM instance data.
4227	* @param iPml4 The index.
4228	*/
4229	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4230	{
4231	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4232	PX86PML4 pGuestPml4;
4233	int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4234	if (RT_FAILURE(rc))
4235	{
4236	X86PML4E ZeroPml4e = {0};
4237	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4238	}
4239	#else
4240	PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4241	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4242	if (!pGuestPml4)
4243	pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4244	# endif
4245	Assert(pGuestPml4);
4246	#endif
4247	return pGuestPml4->a[iPml4];
4248	}
4249
4250
4251	/**
4252	* Gets the page directory pointer entry for the specified address.
4253	*
4254	* @returns Pointer to the page directory pointer entry in question.
4255	* @returns NULL if the page directory is not present or on an invalid page.
4256	* @param pPGM Pointer to the PGM instance data.
4257	* @param GCPtr The address.
4258	* @param ppPml4e Page Map Level-4 Entry (out)
4259	*/
4260	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4261	{
4262	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4263	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4264	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4265	if (pPml4e->n.u1Present)
4266	{
4267	PX86PDPT pPdpt;
4268	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4269	AssertRCReturn(rc, NULL);
4270
4271	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4272	return &pPdpt->a[iPdpt];
4273	}
4274	return NULL;
4275	}
4276
4277
4278	/**
4279	* Gets the page directory entry for the specified address.
4280	*
4281	* @returns The page directory entry in question.
4282	* @returns A non-present entry if the page directory is not present or on an invalid page.
4283	* @param pPGM Pointer to the PGM instance data.
4284	* @param GCPtr The address.
4285	* @param ppPml4e Page Map Level-4 Entry (out)
4286	* @param pPdpe Page directory pointer table entry (out)
4287	*/
4288	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4289	{
4290	X86PDEPAE ZeroPde = {0};
4291	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4292	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4293	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4294	if (pPml4e->n.u1Present)
4295	{
4296	PCX86PDPT pPdptTemp;
4297	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4298	AssertRCReturn(rc, ZeroPde);
4299
4300	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4301	*pPdpe = pPdptTemp->a[iPdpt];
4302	if (pPdptTemp->a[iPdpt].n.u1Present)
4303	{
4304	PCX86PDPAE pPD;
4305	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4306	AssertRCReturn(rc, ZeroPde);
4307
4308	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4309	return pPD->a[iPD];
4310	}
4311	}
4312
4313	return ZeroPde;
4314	}
4315
4316
4317	/**
4318	* Gets the page directory entry for the specified address.
4319	*
4320	* @returns The page directory entry in question.
4321	* @returns A non-present entry if the page directory is not present or on an invalid page.
4322	* @param pPGM Pointer to the PGM instance data.
4323	* @param GCPtr The address.
4324	*/
4325	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4326	{
4327	X86PDEPAE ZeroPde = {0};
4328	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4329	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4330	if (pGuestPml4->a[iPml4].n.u1Present)
4331	{
4332	PCX86PDPT pPdptTemp;
4333	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4334	AssertRCReturn(rc, ZeroPde);
4335
4336	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4337	if (pPdptTemp->a[iPdpt].n.u1Present)
4338	{
4339	PCX86PDPAE pPD;
4340	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4341	AssertRCReturn(rc, ZeroPde);
4342
4343	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4344	return pPD->a[iPD];
4345	}
4346	}
4347	return ZeroPde;
4348	}
4349
4350
4351	/**
4352	* Gets the page directory entry for the specified address.
4353	*
4354	* @returns Pointer to the page directory entry in question.
4355	* @returns NULL if the page directory is not present or on an invalid page.
4356	* @param pPGM Pointer to the PGM instance data.
4357	* @param GCPtr The address.
4358	*/
4359	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4360	{
4361	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4362	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4363	if (pGuestPml4->a[iPml4].n.u1Present)
4364	{
4365	PCX86PDPT pPdptTemp;
4366	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4367	AssertRCReturn(rc, NULL);
4368
4369	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4370	if (pPdptTemp->a[iPdpt].n.u1Present)
4371	{
4372	PX86PDPAE pPD;
4373	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4374	AssertRCReturn(rc, NULL);
4375
4376	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4377	return &pPD->a[iPD];
4378	}
4379	}
4380	return NULL;
4381	}
4382
4383
4384	/**
4385	* Gets the GUEST page directory pointer for the specified address.
4386	*
4387	* @returns The page directory in question.
4388	* @returns NULL if the page directory is not present or on an invalid page.
4389	* @param pPGM Pointer to the PGM instance data.
4390	* @param GCPtr The address.
4391	* @param ppPml4e Page Map Level-4 Entry (out)
4392	* @param pPdpe Page directory pointer table entry (out)
4393	* @param piPD Receives the index into the returned page directory
4394	*/
4395	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4396	{
4397	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4398	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4399	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4400	if (pPml4e->n.u1Present)
4401	{
4402	PCX86PDPT pPdptTemp;
4403	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4404	AssertRCReturn(rc, NULL);
4405
4406	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4407	*pPdpe = pPdptTemp->a[iPdpt];
4408	if (pPdptTemp->a[iPdpt].n.u1Present)
4409	{
4410	PX86PDPAE pPD;
4411	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4412	AssertRCReturn(rc, NULL);
4413
4414	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4415	return pPD;
4416	}
4417	}
4418	return 0;
4419	}
4420
4421	#endif /* !IN_RC */
4422
4423	/**
4424	* Gets the shadow page directory, 32-bit.
4425	*
4426	* @returns Pointer to the shadow 32-bit PD.
4427	* @param pPGM Pointer to the PGM instance data.
4428	*/
4429	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4430	{
4431	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4432	}
4433
4434
4435	/**
4436	* Gets the shadow page directory entry for the specified address, 32-bit.
4437	*
4438	* @returns Shadow 32-bit PDE.
4439	* @param pPGM Pointer to the PGM instance data.
4440	* @param GCPtr The address.
4441	*/
4442	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4443	{
4444	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4445
4446	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4447	if (!pShwPde)
4448	{
4449	X86PDE ZeroPde = {0};
4450	return ZeroPde;
4451	}
4452	return pShwPde->a[iPd];
4453	}
4454
4455
4456	/**
4457	* Gets the pointer to the shadow page directory entry for the specified
4458	* address, 32-bit.
4459	*
4460	* @returns Pointer to the shadow 32-bit PDE.
4461	* @param pPGM Pointer to the PGM instance data.
4462	* @param GCPtr The address.
4463	*/
4464	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4465	{
4466	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4467
4468	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4469	AssertReturn(pPde, NULL);
4470	return &pPde->a[iPd];
4471	}
4472
4473
4474	/**
4475	* Gets the shadow page pointer table, PAE.
4476	*
4477	* @returns Pointer to the shadow PAE PDPT.
4478	* @param pPGM Pointer to the PGM instance data.
4479	*/
4480	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4481	{
4482	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4483	}
4484
4485
4486	/**
4487	* Gets the shadow page directory for the specified address, PAE.
4488	*
4489	* @returns Pointer to the shadow PD.
4490	* @param pPGM Pointer to the PGM instance data.
4491	* @param GCPtr The address.
4492	*/
4493	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4494	{
4495	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4496	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4497
4498	if (!pPdpt->a[iPdpt].n.u1Present)
4499	return NULL;
4500
4501	/* Fetch the pgm pool shadow descriptor. */
4502	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4503	AssertReturn(pShwPde, NULL);
4504
4505	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4506	}
4507
4508
4509	/**
4510	* Gets the shadow page directory for the specified address, PAE.
4511	*
4512	* @returns Pointer to the shadow PD.
4513	* @param pPGM Pointer to the PGM instance data.
4514	* @param GCPtr The address.
4515	*/
4516	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4517	{
4518	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4519
4520	if (!pPdpt->a[iPdpt].n.u1Present)
4521	return NULL;
4522
4523	/* Fetch the pgm pool shadow descriptor. */
4524	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4525	AssertReturn(pShwPde, NULL);
4526
4527	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4528	}
4529
4530
4531	/**
4532	* Gets the shadow page directory entry, PAE.
4533	*
4534	* @returns PDE.
4535	* @param pPGM Pointer to the PGM instance data.
4536	* @param GCPtr The address.
4537	*/
4538	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4539	{
4540	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4541
4542	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4543	if (!pShwPde)
4544	{
4545	X86PDEPAE ZeroPde = {0};
4546	return ZeroPde;
4547	}
4548	return pShwPde->a[iPd];
4549	}
4550
4551
4552	/**
4553	* Gets the pointer to the shadow page directory entry for an address, PAE.
4554	*
4555	* @returns Pointer to the PDE.
4556	* @param pPGM Pointer to the PGM instance data.
4557	* @param GCPtr The address.
4558	*/
4559	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4560	{
4561	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4562
4563	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4564	AssertReturn(pPde, NULL);
4565	return &pPde->a[iPd];
4566	}
4567
4568	#ifndef IN_RC
4569
4570	/**
4571	* Gets the shadow page map level-4 pointer.
4572	*
4573	* @returns Pointer to the shadow PML4.
4574	* @param pPGM Pointer to the PGM instance data.
4575	*/
4576	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4577	{
4578	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4579	}
4580
4581
4582	/**
4583	* Gets the shadow page map level-4 entry for the specified address.
4584	*
4585	* @returns The entry.
4586	* @param pPGM Pointer to the PGM instance data.
4587	* @param GCPtr The address.
4588	*/
4589	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4590	{
4591	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4592	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4593
4594	if (!pShwPml4)
4595	{
4596	X86PML4E ZeroPml4e = {0};
4597	return ZeroPml4e;
4598	}
4599	return pShwPml4->a[iPml4];
4600	}
4601
4602
4603	/**
4604	* Gets the pointer to the specified shadow page map level-4 entry.
4605	*
4606	* @returns The entry.
4607	* @param pPGM Pointer to the PGM instance data.
4608	* @param iPml4 The PML4 index.
4609	*/
4610	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4611	{
4612	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4613	if (!pShwPml4)
4614	return NULL;
4615	return &pShwPml4->a[iPml4];
4616	}
4617
4618
4619	/**
4620	* Gets the GUEST page directory pointer for the specified address.
4621	*
4622	* @returns The page directory in question.
4623	* @returns NULL if the page directory is not present or on an invalid page.
4624	* @param pPGM Pointer to the PGM instance data.
4625	* @param GCPtr The address.
4626	* @param piPD Receives the index into the returned page directory
4627	*/
4628	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4629	{
4630	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4631	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4632	if (pGuestPml4->a[iPml4].n.u1Present)
4633	{
4634	PCX86PDPT pPdptTemp;
4635	int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4636	AssertRCReturn(rc, NULL);
4637
4638	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4639	if (pPdptTemp->a[iPdpt].n.u1Present)
4640	{
4641	PX86PDPAE pPD;
4642	rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4643	AssertRCReturn(rc, NULL);
4644
4645	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4646	return pPD;
4647	}
4648	}
4649	return NULL;
4650	}
4651
4652	#endif /* !IN_RC */
4653
4654	/**
4655	* Gets the page state for a physical handler.
4656	*
4657	* @returns The physical handler page state.
4658	* @param pCur The physical handler in question.
4659	*/
4660	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4661	{
4662	switch (pCur->enmType)
4663	{
4664	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4665	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4666
4667	case PGMPHYSHANDLERTYPE_MMIO:
4668	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4669	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4670
4671	default:
4672	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4673	}
4674	}
4675
4676
4677	/**
4678	* Gets the page state for a virtual handler.
4679	*
4680	* @returns The virtual handler page state.
4681	* @param pCur The virtual handler in question.
4682	* @remarks This should never be used on a hypervisor access handler.
4683	*/
4684	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4685	{
4686	switch (pCur->enmType)
4687	{
4688	case PGMVIRTHANDLERTYPE_WRITE:
4689	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4690	case PGMVIRTHANDLERTYPE_ALL:
4691	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4692	default:
4693	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4694	}
4695	}
4696
4697
4698	/**
4699	* Clears one physical page of a virtual handler
4700	*
4701	* @param pPGM Pointer to the PGM instance.
4702	* @param pCur Virtual handler structure
4703	* @param iPage Physical page index
4704	*
4705	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4706	* need to care about other handlers in the same page.
4707	*/
4708	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4709	{
4710	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4711
4712	/*
4713	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4714	*/
4715	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4716	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4717	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4718	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4719	#endif
4720	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4721	{
4722	/* We're the head of the alias chain. */
4723	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4724	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4725	AssertReleaseMsg(pRemove != NULL,
4726	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4727	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4728	AssertReleaseMsg(pRemove == pPhys2Virt,
4729	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4730	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4731	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4732	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4733	#endif
4734	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4735	{
4736	/* Insert the next list in the alias chain into the tree. */
4737	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4738	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4739	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4740	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4741	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4742	#endif
4743	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4744	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4745	AssertRelease(fRc);
4746	}
4747	}
4748	else
4749	{
4750	/* Locate the previous node in the alias chain. */
4751	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4752	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4753	AssertReleaseMsg(pPrev != pPhys2Virt,
4754	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4755	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4756	#endif
4757	for (;;)
4758	{
4759	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4760	if (pNext == pPhys2Virt)
4761	{
4762	/* unlink. */
4763	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4764	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4765	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4766	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4767	else
4768	{
4769	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4770	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4771	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4772	}
4773	break;
4774	}
4775
4776	/* next */
4777	if (pNext == pPrev)
4778	{
4779	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4780	AssertReleaseMsg(pNext != pPrev,
4781	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4782	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4783	#endif
4784	break;
4785	}
4786	pPrev = pNext;
4787	}
4788	}
4789	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4790	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4791	pPhys2Virt->offNextAlias = 0;
4792	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4793
4794	/*
4795	* Clear the ram flags for this page.
4796	*/
4797	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4798	AssertReturnVoid(pPage);
4799	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4800	}
4801
4802
4803	/**
4804	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4805	*
4806	* @returns Pointer to the shadow page structure.
4807	* @param pPool The pool.
4808	* @param idx The pool page index.
4809	*/
4810	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4811	{
4812	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4813	return &pPool->aPages[idx];
4814	}
4815
4816
4817	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4818	/**
4819	* Clear references to guest physical memory.
4820	*
4821	* @param pPool The pool.
4822	* @param pPoolPage The pool page.
4823	* @param pPhysPage The physical guest page tracking structure.
4824	*/
4825	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4826	{
4827	/*
4828	* Just deal with the simple case here.
4829	*/
4830	# ifdef LOG_ENABLED
4831	const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4832	# endif
4833	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4834	if (cRefs == 1)
4835	{
4836	Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4837	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4838	}
4839	else
4840	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4841	Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4842	}
4843	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4844
4845
4846	#ifdef PGMPOOL_WITH_CACHE
4847	/**
4848	* Moves the page to the head of the age list.
4849	*
4850	* This is done when the cached page is used in one way or another.
4851	*
4852	* @param pPool The pool.
4853	* @param pPage The cached page.
4854	*/
4855	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4856	{
4857	PVM pVM = pPool->CTX_SUFF(pVM);
4858	pgmLock(pVM);
4859
4860	/*
4861	* Move to the head of the age list.
4862	*/
4863	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4864	{
4865	/* unlink */
4866	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4867	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4868	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4869	else
4870	pPool->iAgeTail = pPage->iAgePrev;
4871
4872	/* insert at head */
4873	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4874	pPage->iAgeNext = pPool->iAgeHead;
4875	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4876	pPool->iAgeHead = pPage->idx;
4877	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4878	}
4879	pgmUnlock(pVM);
4880	}
4881	#endif /* PGMPOOL_WITH_CACHE */
4882
4883	/**
4884	* Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4885	*
4886	* @param pVM VM Handle.
4887	* @param pPage PGM pool page
4888	*/
4889	DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4890	{
4891	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4892	ASMAtomicIncU32(&pPage->cLocked);
4893	}
4894
4895
4896	/**
4897	* Unlocks a page to allow flushing again
4898	*
4899	* @param pVM VM Handle.
4900	* @param pPage PGM pool page
4901	*/
4902	DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4903	{
4904	Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4905	Assert(pPage->cLocked);
4906	ASMAtomicDecU32(&pPage->cLocked);
4907	}
4908
4909
4910	/**
4911	* Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4912	*
4913	* @returns VBox status code.
4914	* @param pPage PGM pool page
4915	*/
4916	DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4917	{
4918	if (pPage->cLocked)
4919	{
4920	LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4921	if (pPage->cModifications)
4922	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4923	return true;
4924	}
4925	return false;
4926	}
4927
4928	/**
4929	* Tells if mappings are to be put into the shadow page table or not
4930	*
4931	* @returns boolean result
4932	* @param pVM VM handle.
4933	*/
4934	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4935	{
4936	#ifdef IN_RING0
4937	/* There are no mappings in VT-x and AMD-V mode. */
4938	Assert(pPGM->fDisableMappings);
4939	return false;
4940	#else
4941	return !pPGM->fDisableMappings;
4942	#endif
4943	}
4944
4945	/** @} */
4946
4947	#endif
4948
4949

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 23483

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