VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 23488

Last change on this file since 23488 was 23488, checked in by vboxsync, 15 years ago

PGM: Lock stats and check for write locks on monitored pages during live save.
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1/* $Id: PGMInternal.h 23488 2009-10-01 15:38:06Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#if 0 /* disabled again while debugging */
72#ifndef IN_RC
73# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
74#endif
75#endif
76
77/**
78 * Sync N pages instead of a whole page table
79 */
80#define PGM_SYNC_N_PAGES
81
82/**
83 * Number of pages to sync during a page fault
84 *
85 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
86 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
87 *
88 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
89 * world switch overhead, so let's sync more.
90 */
91# ifdef IN_RING0
92/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
93 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
94 * but ~5% fewer faults.
95 */
96# define PGM_SYNC_NR_PAGES 32
97#else
98# define PGM_SYNC_NR_PAGES 8
99#endif
100
101/**
102 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
103 */
104#define PGM_MAX_PHYSCACHE_ENTRIES 64
105#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
106
107/** @def PGMPOOL_WITH_CACHE
108 * Enable agressive caching using the page pool.
109 *
110 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
111 */
112#define PGMPOOL_WITH_CACHE
113
114/** @def PGMPOOL_WITH_MIXED_PT_CR3
115 * When defined, we'll deal with 'uncachable' pages.
116 */
117#ifdef PGMPOOL_WITH_CACHE
118# define PGMPOOL_WITH_MIXED_PT_CR3
119#endif
120
121/** @def PGMPOOL_WITH_MONITORING
122 * Monitor the guest pages which are shadowed.
123 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
124 * be enabled as well.
125 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
126 */
127#ifdef PGMPOOL_WITH_CACHE
128# define PGMPOOL_WITH_MONITORING
129#endif
130
131/** @def PGMPOOL_WITH_GCPHYS_TRACKING
132 * Tracking the of shadow pages mapping guest physical pages.
133 *
134 * This is very expensive, the current cache prototype is trying to figure out
135 * whether it will be acceptable with an agressive caching policy.
136 */
137#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
138# define PGMPOOL_WITH_GCPHYS_TRACKING
139#endif
140
141/** @def PGMPOOL_WITH_USER_TRACKING
142 * Tracking users of shadow pages. This is required for the linking of shadow page
143 * tables and physical guest addresses.
144 */
145#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
146# define PGMPOOL_WITH_USER_TRACKING
147#endif
148
149/** @def PGMPOOL_CFG_MAX_GROW
150 * The maximum number of pages to add to the pool in one go.
151 */
152#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
153
154/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
155 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
156 */
157#ifdef VBOX_STRICT
158# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
159#endif
160
161/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
162 * Enables the experimental lazy page allocation code. */
163/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED 6
213#define PGM_TYPE_EPT 7
214#define PGM_TYPE_MAX PGM_TYPE_EPT
215/** @} */
216
217/** Macro for checking if the guest is using paging.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_PAGING(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_32BIT \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227/** Macro for checking if the guest supports the NX bit.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_NX(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_PAE \
234 && (uShwType) != PGM_TYPE_NESTED \
235 && (uShwType) != PGM_TYPE_EPT)
236
237
238/** @def PGM_HCPHYS_2_PTR
239 * Maps a HC physical page pool address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM handle.
243 * @param HCPhys The HC physical address to map to a virtual one.
244 * @param ppv Where to store the virtual address. No need to cast this.
245 *
246 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
247 * small page window employeed by that function. Be careful.
248 * @remark There is no need to assert on the result.
249 */
250#ifdef IN_RC
251# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
252 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
253#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
258 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_HCPHYS_2_PTR_BY_PGM
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pPGM The PGM instance data.
266 * @param HCPhys The HC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
275 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
276#else
277# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
278 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
279#endif
280
281/** @def PGM_GCPHYS_2_PTR
282 * Maps a GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The VM handle.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290 * small page window employeed by that function. Be careful.
291 * @remark There is no need to assert on the result.
292 */
293#ifdef IN_RC
294# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
295 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
296#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
297# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
301 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pPGM Pointer to the PGM instance data.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
317# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
318 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
321 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
322#endif
323
324/** @def PGM_GCPHYS_2_PTR_EX
325 * Maps a unaligned GC physical page address to a virtual address.
326 *
327 * @returns VBox status code.
328 * @param pVM The VM handle.
329 * @param GCPhys The GC physical address to map to a virtual one.
330 * @param ppv Where to store the virtual address. No need to cast this.
331 *
332 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
333 * small page window employeed by that function. Be careful.
334 * @remark There is no need to assert on the result.
335 */
336#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
339#else
340# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
341 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
342#endif
343
344/** @def PGM_INVL_PG
345 * Invalidates a page.
346 *
347 * @param pVCpu The VMCPU handle.
348 * @param GCVirt The virtual address of the page to invalidate.
349 */
350#ifdef IN_RC
351# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
352#elif defined(IN_RING0)
353# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354#else
355# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356#endif
357
358/** @def PGM_INVL_PG_ALL_VCPU
359 * Invalidates a page on all VCPUs
360 *
361 * @param pVM The VM handle.
362 * @param GCVirt The virtual address of the page to invalidate.
363 */
364#ifdef IN_RC
365# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
366#elif defined(IN_RING0)
367# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368#else
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370#endif
371
372/** @def PGM_INVL_BIG_PG
373 * Invalidates a 4MB page directory entry.
374 *
375 * @param pVCpu The VMCPU handle.
376 * @param GCVirt The virtual address within the page directory to invalidate.
377 */
378#ifdef IN_RC
379# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_VCPU_TLBS()
387 * Invalidates the TLBs of the specified VCPU
388 *
389 * @param pVCpu The VMCPU handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_ALL_VCPU_TLBS()
400 * Invalidates the TLBs of all VCPUs
401 *
402 * @param pVM The VM handle.
403 */
404#ifdef IN_RC
405# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408#else
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410#endif
411
412/** Size of the GCPtrConflict array in PGMMAPPING.
413 * @remarks Must be a power of two. */
414#define PGMMAPPING_CONFLICT_MAX 8
415
416/**
417 * Structure for tracking GC Mappings.
418 *
419 * This structure is used by linked list in both GC and HC.
420 */
421typedef struct PGMMAPPING
422{
423 /** Pointer to next entry. */
424 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425 /** Pointer to next entry. */
426 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427 /** Pointer to next entry. */
428 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429 /** Indicate whether this entry is finalized. */
430 bool fFinalized;
431 /** Start Virtual address. */
432 RTGCPTR GCPtr;
433 /** Last Virtual address (inclusive). */
434 RTGCPTR GCPtrLast;
435 /** Range size (bytes). */
436 RTGCPTR cb;
437 /** Pointer to relocation callback function. */
438 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439 /** User argument to the callback. */
440 R3PTRTYPE(void *) pvUser;
441 /** Mapping description / name. For easing debugging. */
442 R3PTRTYPE(const char *) pszDesc;
443 /** Last 8 addresses that caused conflicts. */
444 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445 /** Number of conflicts for this hypervisor mapping. */
446 uint32_t cConflicts;
447 /** Number of page tables. */
448 uint32_t cPTs;
449
450 /** Array of page table mapping data. Each entry
451 * describes one page table. The array can be longer
452 * than the declared length.
453 */
454 struct
455 {
456 /** The HC physical address of the page table. */
457 RTHCPHYS HCPhysPT;
458 /** The HC physical address of the first PAE page table. */
459 RTHCPHYS HCPhysPaePT0;
460 /** The HC physical address of the second PAE page table. */
461 RTHCPHYS HCPhysPaePT1;
462 /** The HC virtual address of the 32-bit page table. */
463 R3PTRTYPE(PX86PT) pPTR3;
464 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466 /** The RC virtual address of the 32-bit page table. */
467 RCPTRTYPE(PX86PT) pPTRC;
468 /** The RC virtual address of the two PAE page table. */
469 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470 /** The R0 virtual address of the 32-bit page table. */
471 R0PTRTYPE(PX86PT) pPTR0;
472 /** The R0 virtual address of the two PAE page table. */
473 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474 } aPTs[1];
475} PGMMAPPING;
476/** Pointer to structure for tracking GC Mappings. */
477typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480/**
481 * Physical page access handler structure.
482 *
483 * This is used to keep track of physical address ranges
484 * which are being monitored in some kind of way.
485 */
486typedef struct PGMPHYSHANDLER
487{
488 AVLROGCPHYSNODECORE Core;
489 /** Access type. */
490 PGMPHYSHANDLERTYPE enmType;
491 /** Number of pages to update. */
492 uint32_t cPages;
493 /** Pointer to R3 callback function. */
494 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495 /** User argument for R3 handlers. */
496 R3PTRTYPE(void *) pvUserR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499 /** User argument for R0 handlers. */
500 R0PTRTYPE(void *) pvUserR0;
501 /** Pointer to RC callback function. */
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503 /** User argument for RC handlers. */
504 RCPTRTYPE(void *) pvUserRC;
505 /** Description / Name. For easing debugging. */
506 R3PTRTYPE(const char *) pszDesc;
507#ifdef VBOX_WITH_STATISTICS
508 /** Profiling of this handler. */
509 STAMPROFILE Stat;
510#endif
511} PGMPHYSHANDLER;
512/** Pointer to a physical page access handler structure. */
513typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516/**
517 * Cache node for the physical addresses covered by a virtual handler.
518 */
519typedef struct PGMPHYS2VIRTHANDLER
520{
521 /** Core node for the tree based on physical ranges. */
522 AVLROGCPHYSNODECORE Core;
523 /** Offset from this struct to the PGMVIRTHANDLER structure. */
524 int32_t offVirtHandler;
525 /** Offset of the next alias relative to this one.
526 * Bit 0 is used for indicating whether we're in the tree.
527 * Bit 1 is used for indicating that we're the head node.
528 */
529 int32_t offNextAlias;
530} PGMPHYS2VIRTHANDLER;
531/** Pointer to a phys to virtual handler structure. */
532typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535 * node is in the tree. */
536#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538 * node is in the head of an alias chain.
539 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545/**
546 * Virtual page access handler structure.
547 *
548 * This is used to keep track of virtual address ranges
549 * which are being monitored in some kind of way.
550 */
551typedef struct PGMVIRTHANDLER
552{
553 /** Core node for the tree based on virtual ranges. */
554 AVLROGCPTRNODECORE Core;
555 /** Size of the range (in bytes). */
556 RTGCPTR cb;
557 /** Number of cache pages. */
558 uint32_t cPages;
559 /** Access type. */
560 PGMVIRTHANDLERTYPE enmType;
561 /** Pointer to the RC callback function. */
562 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563#if HC_ARCH_BITS == 64
564 RTRCPTR padding;
565#endif
566 /** Pointer to the R3 callback function for invalidation. */
567 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568 /** Pointer to the R3 callback function. */
569 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570 /** Description / Name. For easing debugging. */
571 R3PTRTYPE(const char *) pszDesc;
572#ifdef VBOX_WITH_STATISTICS
573 /** Profiling of this handler. */
574 STAMPROFILE Stat;
575#endif
576 /** Array of cached physical addresses for the monitored ranged. */
577 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578} PGMVIRTHANDLER;
579/** Pointer to a virtual page access handler structure. */
580typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583/**
584 * Page type.
585 *
586 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587 * @remarks This is used in the saved state, so changes to it requires bumping
588 * the saved state version.
589 * @todo So, convert to \#defines!
590 */
591typedef enum PGMPAGETYPE
592{
593 /** The usual invalid zero entry. */
594 PGMPAGETYPE_INVALID = 0,
595 /** RAM page. (RWX) */
596 PGMPAGETYPE_RAM,
597 /** MMIO2 page. (RWX) */
598 PGMPAGETYPE_MMIO2,
599 /** MMIO2 page aliased over an MMIO page. (RWX)
600 * See PGMHandlerPhysicalPageAlias(). */
601 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602 /** Shadowed ROM. (RWX) */
603 PGMPAGETYPE_ROM_SHADOW,
604 /** ROM page. (R-X) */
605 PGMPAGETYPE_ROM,
606 /** MMIO page. (---) */
607 PGMPAGETYPE_MMIO,
608 /** End of valid entries. */
609 PGMPAGETYPE_END
610} PGMPAGETYPE;
611AssertCompile(PGMPAGETYPE_END <= 7);
612
613/** @name Page type predicates.
614 * @{ */
615#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620/** @} */
621
622
623/**
624 * A Physical Guest Page tracking structure.
625 *
626 * The format of this structure is complicated because we have to fit a lot
627 * of information into as few bits as possible. The format is also subject
628 * to change (there is one comming up soon). Which means that for we'll be
629 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
630 * accesses to the structure.
631 */
632typedef struct PGMPAGE
633{
634 /** The physical address and the Page ID. */
635 RTHCPHYS HCPhysAndPageID;
636 /** Combination of:
637 * - [0-7]: u2HandlerPhysStateY - the physical handler state
638 * (PGM_PAGE_HNDL_PHYS_STATE_*).
639 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
640 * (PGM_PAGE_HNDL_VIRT_STATE_*).
641 * - [15]: fWrittenToY - flag indicating that a write monitored page was
642 * written to when set.
643 * - [10-14]: 5 unused bits.
644 * @remarks Warning! All accesses to the bits are hardcoded.
645 *
646 * @todo Change this to a union with both bitfields, u8 and u accessors.
647 * That'll help deal with some of the hardcoded accesses.
648 *
649 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
650 * will make it possible to turn some of the 16-bit accesses into
651 * 32-bit ones, which may be efficient (stalls).
652 */
653 RTUINT16U u16MiscY;
654 /** The page state.
655 * Only 2 bits are really needed for this. */
656 uint8_t uStateY;
657 /** The page type (PGMPAGETYPE).
658 * Only 3 bits are really needed for this. */
659 uint8_t uTypeY;
660 /** Usage tracking (page pool). */
661 uint16_t u16TrackingY;
662 /** The number of read locks on this page. */
663 uint8_t cReadLocksY;
664 /** The number of write locks on this page. */
665 uint8_t cWriteLocksY;
666} PGMPAGE;
667AssertCompileSize(PGMPAGE, 16);
668/** Pointer to a physical guest page. */
669typedef PGMPAGE *PPGMPAGE;
670/** Pointer to a const physical guest page. */
671typedef const PGMPAGE *PCPGMPAGE;
672/** Pointer to a physical guest page pointer. */
673typedef PPGMPAGE *PPPGMPAGE;
674
675
676/**
677 * Clears the page structure.
678 * @param pPage Pointer to the physical guest page tracking structure.
679 */
680#define PGM_PAGE_CLEAR(pPage) \
681 do { \
682 (pPage)->HCPhysAndPageID = 0; \
683 (pPage)->uStateY = 0; \
684 (pPage)->uTypeY = 0; \
685 (pPage)->u16MiscY.u = 0; \
686 (pPage)->u16TrackingY = 0; \
687 (pPage)->cReadLocksY = 0; \
688 (pPage)->cWriteLocksY = 0; \
689 } while (0)
690
691/**
692 * Initializes the page structure.
693 * @param pPage Pointer to the physical guest page tracking structure.
694 */
695#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
696 do { \
697 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
698 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
699 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
700 (pPage)->uStateY = (_uState); \
701 (pPage)->uTypeY = (_uType); \
702 (pPage)->u16MiscY.u = 0; \
703 (pPage)->u16TrackingY = 0; \
704 (pPage)->cReadLocksY = 0; \
705 (pPage)->cWriteLocksY = 0; \
706 } while (0)
707
708/**
709 * Initializes the page structure of a ZERO page.
710 * @param pPage Pointer to the physical guest page tracking structure.
711 * @param pVM The VM handle (for getting the zero page address).
712 * @param uType The page type (PGMPAGETYPE).
713 */
714#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
715 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
716
717
718/** @name The Page state, PGMPAGE::uStateY.
719 * @{ */
720/** The zero page.
721 * This is a per-VM page that's never ever mapped writable. */
722#define PGM_PAGE_STATE_ZERO 0
723/** A allocated page.
724 * This is a per-VM page allocated from the page pool (or wherever
725 * we get MMIO2 pages from if the type is MMIO2).
726 */
727#define PGM_PAGE_STATE_ALLOCATED 1
728/** A allocated page that's being monitored for writes.
729 * The shadow page table mappings are read-only. When a write occurs, the
730 * fWrittenTo member is set, the page remapped as read-write and the state
731 * moved back to allocated. */
732#define PGM_PAGE_STATE_WRITE_MONITORED 2
733/** The page is shared, aka. copy-on-write.
734 * This is a page that's shared with other VMs. */
735#define PGM_PAGE_STATE_SHARED 3
736/** @} */
737
738
739/**
740 * Gets the page state.
741 * @returns page state (PGM_PAGE_STATE_*).
742 * @param pPage Pointer to the physical guest page tracking structure.
743 */
744#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
745
746/**
747 * Sets the page state.
748 * @param pPage Pointer to the physical guest page tracking structure.
749 * @param _uState The new page state.
750 */
751#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
752
753
754/**
755 * Gets the host physical address of the guest page.
756 * @returns host physical address (RTHCPHYS).
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
760
761/**
762 * Sets the host physical address of the guest page.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 * @param _HCPhys The new host physical address.
765 */
766#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
767 do { \
768 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
769 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
770 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
771 | (SetHCPhysTmp << (28-12)); \
772 } while (0)
773
774/**
775 * Get the Page ID.
776 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
777 * @param pPage Pointer to the physical guest page tracking structure.
778 */
779#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
780
781/**
782 * Sets the Page ID.
783 * @param pPage Pointer to the physical guest page tracking structure.
784 */
785#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
786 do { \
787 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
788 | ((_idPage) & UINT32_C(0x0fffffff)); \
789 } while (0)
790
791/**
792 * Get the Chunk ID.
793 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
797
798/**
799 * Get the index of the page within the allocation chunk.
800 * @returns The page index.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
804
805/**
806 * Gets the page type.
807 * @returns The page type.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
811
812/**
813 * Sets the page type.
814 * @param pPage Pointer to the physical guest page tracking structure.
815 * @param _enmType The new page type (PGMPAGETYPE).
816 */
817#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
818
819/**
820 * Checks if the page is marked for MMIO.
821 * @returns true/false.
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
825
826/**
827 * Checks if the page is backed by the ZERO page.
828 * @returns true/false.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
832
833/**
834 * Checks if the page is backed by a SHARED page.
835 * @returns true/false.
836 * @param pPage Pointer to the physical guest page tracking structure.
837 */
838#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
839
840
841/**
842 * Marks the paget as written to (for GMM change monitoring).
843 * @param pPage Pointer to the physical guest page tracking structure.
844 */
845#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
846
847/**
848 * Clears the written-to indicator.
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
852
853/**
854 * Checks if the page was marked as written-to.
855 * @returns true/false.
856 * @param pPage Pointer to the physical guest page tracking structure.
857 */
858#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
859
860
861/** Enabled optimized access handler tests.
862 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
863 * layout. When enabled, the compiler should normally generate more compact
864 * code.
865 */
866#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
867
868/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
869 *
870 * @remarks The values are assigned in order of priority, so we can calculate
871 * the correct state for a page with different handlers installed.
872 * @{ */
873/** No handler installed. */
874#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
875/** Monitoring is temporarily disabled. */
876#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
877/** Write access is monitored. */
878#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
879/** All access is monitored. */
880#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
881/** @} */
882
883/**
884 * Gets the physical access handler state of a page.
885 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
886 * @param pPage Pointer to the physical guest page tracking structure.
887 */
888#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
889 ( (pPage)->u16MiscY.au8[0] )
890
891/**
892 * Sets the physical access handler state of a page.
893 * @param pPage Pointer to the physical guest page tracking structure.
894 * @param _uState The new state value.
895 */
896#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
897 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
898
899/**
900 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
901 * @returns true/false
902 * @param pPage Pointer to the physical guest page tracking structure.
903 */
904#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
905 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
906
907/**
908 * Checks if the page has any active physical access handlers.
909 * @returns true/false
910 * @param pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
913 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
914
915
916/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
917 *
918 * @remarks The values are assigned in order of priority, so we can calculate
919 * the correct state for a page with different handlers installed.
920 * @{ */
921/** No handler installed. */
922#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
923/* 1 is reserved so the lineup is identical with the physical ones. */
924/** Write access is monitored. */
925#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
926/** All access is monitored. */
927#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
928/** @} */
929
930/**
931 * Gets the virtual access handler state of a page.
932 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
933 * @param pPage Pointer to the physical guest page tracking structure.
934 */
935#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) )
936
937/**
938 * Sets the virtual access handler state of a page.
939 * @param pPage Pointer to the physical guest page tracking structure.
940 * @param _uState The new state value.
941 */
942#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
943 do { \
944 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
945 | ((_uState) & UINT8_C(0x03)); \
946 } while (0)
947
948/**
949 * Checks if the page has any virtual access handlers.
950 * @returns true/false
951 * @param pPage Pointer to the physical guest page tracking structure.
952 */
953#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
954 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
955
956/**
957 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
958 * virtual handlers.
959 * @returns true/false
960 * @param pPage Pointer to the physical guest page tracking structure.
961 */
962#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
963 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
964
965
966/**
967 * Checks if the page has any access handlers, including temporarily disabled ones.
968 * @returns true/false
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
972# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
973 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
974#else
975# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
976 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
977 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
978#endif
979
980/**
981 * Checks if the page has any active access handlers.
982 * @returns true/false
983 * @param pPage Pointer to the physical guest page tracking structure.
984 */
985#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
986# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
987 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
988#else
989# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
990 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
991 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
992#endif
993
994/**
995 * Checks if the page has any active access handlers catching all accesses.
996 * @returns true/false
997 * @param pPage Pointer to the physical guest page tracking structure.
998 */
999#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1000# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1001 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1002 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1003#else
1004# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1005 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1006 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1007#endif
1008
1009
1010/** @def PGM_PAGE_GET_TRACKING
1011 * Gets the packed shadow page pool tracking data associated with a guest page.
1012 * @returns uint16_t containing the data.
1013 * @param pPage Pointer to the physical guest page tracking structure.
1014 */
1015#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1016
1017/** @def PGM_PAGE_SET_TRACKING
1018 * Sets the packed shadow page pool tracking data associated with a guest page.
1019 * @param pPage Pointer to the physical guest page tracking structure.
1020 * @param u16TrackingData The tracking data to store.
1021 */
1022#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1023 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1024
1025/** @def PGM_PAGE_GET_TD_CREFS
1026 * Gets the @a cRefs tracking data member.
1027 * @returns cRefs.
1028 * @param pPage Pointer to the physical guest page tracking structure.
1029 */
1030#define PGM_PAGE_GET_TD_CREFS(pPage) \
1031 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1032
1033/** @def PGM_PAGE_GET_TD_IDX
1034 * Gets the @a idx tracking data member.
1035 * @returns idx.
1036 * @param pPage Pointer to the physical guest page tracking structure.
1037 */
1038#define PGM_PAGE_GET_TD_IDX(pPage) \
1039 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1040
1041
1042/** Max number of locks on a page. */
1043#define PGM_PAGE_MAX_LOCKS 254
1044
1045/** Get the read lock count.
1046 * @returns count.
1047 * @param pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1050
1051/** Get the write lock count.
1052 * @returns count.
1053 * @param pPage Pointer to the physical guest page tracking structure.
1054 */
1055#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1056
1057/** Decrement the read lock counter.
1058 * @param pPage Pointer to the physical guest page tracking structure.
1059 */
1060#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1061
1062/** Decrement the write lock counter.
1063 * @param pPage Pointer to the physical guest page tracking structure.
1064 */
1065#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1066
1067/** Increment the read lock counter.
1068 * @param pPage Pointer to the physical guest page tracking structure.
1069 */
1070#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1071
1072/** Increment the write lock counter.
1073 * @param pPage Pointer to the physical guest page tracking structure.
1074 */
1075#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1076
1077
1078
1079/**
1080 * Per page live save tracking data.
1081 */
1082typedef struct PGMLIVESAVEPAGE
1083{
1084 /** The pass number where this page was last saved. */
1085 uint32_t uPassSaved;
1086 /** Number of times it has been dirtied. */
1087 uint32_t cDirtied : 24;
1088 /** Whether it is currently dirty. */
1089 uint32_t fDirty : 1;
1090 /** Ignore the page.
1091 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1092 * deal with these after pausing the VM and DevPCI have said it bit about
1093 * remappings. */
1094 uint32_t fIgnore : 1;
1095 /** Was a ZERO page last time around. */
1096 uint32_t fZero : 1;
1097 /** Was a SHARED page last time around. */
1098 uint32_t fShared : 1;
1099 /** Whether the page is/was write monitored in a previous pass. */
1100 uint32_t fWriteMonitored : 1;
1101 /** Whether the page is/was write monitored earlier in this pass. */
1102 uint32_t fWriteMonitoredJustNow : 1;
1103 /** Bits reserved for future use. */
1104 uint32_t u2Reserved : 2;
1105} PGMLIVESAVEPAGE;
1106AssertCompileSize(PGMLIVESAVEPAGE, 8);
1107/** Pointer to the per page live save tracking data. */
1108typedef PGMLIVESAVEPAGE *PPGMLIVESAVEPAGE;
1109
1110/** The max value of PGMLIVESAVEPAGE::cDirtied. */
1111#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1112
1113
1114/**
1115 * Ram range for GC Phys to HC Phys conversion.
1116 *
1117 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1118 * conversions too, but we'll let MM handle that for now.
1119 *
1120 * This structure is used by linked lists in both GC and HC.
1121 */
1122typedef struct PGMRAMRANGE
1123{
1124 /** Start of the range. Page aligned. */
1125 RTGCPHYS GCPhys;
1126 /** Size of the range. (Page aligned of course). */
1127 RTGCPHYS cb;
1128 /** Pointer to the next RAM range - for R3. */
1129 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1130 /** Pointer to the next RAM range - for R0. */
1131 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1132 /** Pointer to the next RAM range - for RC. */
1133 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1134 /** PGM_RAM_RANGE_FLAGS_* flags. */
1135 uint32_t fFlags;
1136 /** Last address in the range (inclusive). Page aligned (-1). */
1137 RTGCPHYS GCPhysLast;
1138 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1139 R3PTRTYPE(void *) pvR3;
1140 /** Live save per page tracking data. */
1141 R3PTRTYPE(PPGMLIVESAVEPAGE) paLSPages;
1142 /** The range description. */
1143 R3PTRTYPE(const char *) pszDesc;
1144 /** Pointer to self - R0 pointer. */
1145 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1146 /** Pointer to self - RC pointer. */
1147 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1148 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1149 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1150 /** Array of physical guest page tracking structures. */
1151 PGMPAGE aPages[1];
1152} PGMRAMRANGE;
1153/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1154typedef PGMRAMRANGE *PPGMRAMRANGE;
1155
1156/** @name PGMRAMRANGE::fFlags
1157 * @{ */
1158/** The RAM range is floating around as an independent guest mapping. */
1159#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1160/** Ad hoc RAM range for an ROM mapping. */
1161#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1162/** Ad hoc RAM range for an MMIO mapping. */
1163#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1164/** Ad hoc RAM range for an MMIO2 mapping. */
1165#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1166/** @} */
1167
1168/** Tests if a RAM range is an ad hoc one or not.
1169 * @returns true/false.
1170 * @param pRam The RAM range.
1171 */
1172#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1173 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1174
1175
1176/**
1177 * Per page tracking structure for ROM image.
1178 *
1179 * A ROM image may have a shadow page, in which case we may have two pages
1180 * backing it. This structure contains the PGMPAGE for both while
1181 * PGMRAMRANGE have a copy of the active one. It is important that these
1182 * aren't out of sync in any regard other than page pool tracking data.
1183 */
1184typedef struct PGMROMPAGE
1185{
1186 /** The page structure for the virgin ROM page. */
1187 PGMPAGE Virgin;
1188 /** The page structure for the shadow RAM page. */
1189 PGMPAGE Shadow;
1190 /** The current protection setting. */
1191 PGMROMPROT enmProt;
1192 /** Live save status information. Makes use of unused alignment space. */
1193 struct
1194 {
1195 /** The previous protection value. */
1196 uint8_t u8Prot;
1197 /** Written to flag set by the handler. */
1198 bool fWrittenTo;
1199 /** Whether the shadow page is dirty or not. */
1200 bool fDirty;
1201 /** Whether it was dirtied in the recently. */
1202 bool fDirtiedRecently;
1203 } LiveSave;
1204} PGMROMPAGE;
1205AssertCompileSizeAlignment(PGMROMPAGE, 8);
1206/** Pointer to a ROM page tracking structure. */
1207typedef PGMROMPAGE *PPGMROMPAGE;
1208
1209
1210/**
1211 * A registered ROM image.
1212 *
1213 * This is needed to keep track of ROM image since they generally intrude
1214 * into a PGMRAMRANGE. It also keeps track of additional info like the
1215 * two page sets (read-only virgin and read-write shadow), the current
1216 * state of each page.
1217 *
1218 * Because access handlers cannot easily be executed in a different
1219 * context, the ROM ranges needs to be accessible and in all contexts.
1220 */
1221typedef struct PGMROMRANGE
1222{
1223 /** Pointer to the next range - R3. */
1224 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1225 /** Pointer to the next range - R0. */
1226 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1227 /** Pointer to the next range - RC. */
1228 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1229 /** Pointer alignment */
1230 RTRCPTR RCPtrAlignment;
1231 /** Address of the range. */
1232 RTGCPHYS GCPhys;
1233 /** Address of the last byte in the range. */
1234 RTGCPHYS GCPhysLast;
1235 /** Size of the range. */
1236 RTGCPHYS cb;
1237 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1238 uint32_t fFlags;
1239 /** The saved state range ID. */
1240 uint8_t idSavedState;
1241 /** Alignment padding. */
1242 uint8_t au8Alignment[3];
1243 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1244 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1245 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1246 * This is used for strictness checks. */
1247 R3PTRTYPE(const void *) pvOriginal;
1248 /** The ROM description. */
1249 R3PTRTYPE(const char *) pszDesc;
1250 /** The per page tracking structures. */
1251 PGMROMPAGE aPages[1];
1252} PGMROMRANGE;
1253/** Pointer to a ROM range. */
1254typedef PGMROMRANGE *PPGMROMRANGE;
1255
1256
1257/**
1258 * A registered MMIO2 (= Device RAM) range.
1259 *
1260 * There are a few reason why we need to keep track of these
1261 * registrations. One of them is the deregistration & cleanup stuff,
1262 * while another is that the PGMRAMRANGE associated with such a region may
1263 * have to be removed from the ram range list.
1264 *
1265 * Overlapping with a RAM range has to be 100% or none at all. The pages
1266 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1267 * will be raised if a partial overlap or an overlap of ROM pages is
1268 * encountered. On an overlap we will free all the existing RAM pages and
1269 * put in the ram range pages instead.
1270 */
1271typedef struct PGMMMIO2RANGE
1272{
1273 /** The owner of the range. (a device) */
1274 PPDMDEVINSR3 pDevInsR3;
1275 /** Pointer to the ring-3 mapping of the allocation. */
1276 RTR3PTR pvR3;
1277 /** Pointer to the next range - R3. */
1278 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1279 /** Whether it's mapped or not. */
1280 bool fMapped;
1281 /** Whether it's overlapping or not. */
1282 bool fOverlapping;
1283 /** The PCI region number.
1284 * @remarks This ASSUMES that nobody will ever really need to have multiple
1285 * PCI devices with matching MMIO region numbers on a single device. */
1286 uint8_t iRegion;
1287 /** The saved state range ID. */
1288 uint8_t idSavedState;
1289#if HC_ARCH_BITS != 32
1290 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1291 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 0 : 4];
1292#endif
1293 /** The associated RAM range. */
1294 PGMRAMRANGE RamRange;
1295} PGMMMIO2RANGE;
1296/** Pointer to a MMIO2 range. */
1297typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1298
1299
1300
1301
1302/**
1303 * PGMPhysRead/Write cache entry
1304 */
1305typedef struct PGMPHYSCACHEENTRY
1306{
1307 /** R3 pointer to physical page. */
1308 R3PTRTYPE(uint8_t *) pbR3;
1309 /** GC Physical address for cache entry */
1310 RTGCPHYS GCPhys;
1311#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1312 RTGCPHYS u32Padding0; /**< alignment padding. */
1313#endif
1314} PGMPHYSCACHEENTRY;
1315
1316/**
1317 * PGMPhysRead/Write cache to reduce REM memory access overhead
1318 */
1319typedef struct PGMPHYSCACHE
1320{
1321 /** Bitmap of valid cache entries */
1322 uint64_t aEntries;
1323 /** Cache entries */
1324 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1325} PGMPHYSCACHE;
1326
1327
1328/** Pointer to an allocation chunk ring-3 mapping. */
1329typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1330/** Pointer to an allocation chunk ring-3 mapping pointer. */
1331typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1332
1333/**
1334 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1335 *
1336 * The primary tree (Core) uses the chunk id as key.
1337 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1338 */
1339typedef struct PGMCHUNKR3MAP
1340{
1341 /** The key is the chunk id. */
1342 AVLU32NODECORE Core;
1343 /** The key is the ageing sequence number. */
1344 AVLLU32NODECORE AgeCore;
1345 /** The current age thingy. */
1346 uint32_t iAge;
1347 /** The current reference count. */
1348 uint32_t volatile cRefs;
1349 /** The current permanent reference count. */
1350 uint32_t volatile cPermRefs;
1351 /** The mapping address. */
1352 void *pv;
1353} PGMCHUNKR3MAP;
1354
1355/**
1356 * Allocation chunk ring-3 mapping TLB entry.
1357 */
1358typedef struct PGMCHUNKR3MAPTLBE
1359{
1360 /** The chunk id. */
1361 uint32_t volatile idChunk;
1362#if HC_ARCH_BITS == 64
1363 uint32_t u32Padding; /**< alignment padding. */
1364#endif
1365 /** The chunk map. */
1366#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1367 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1368#else
1369 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1370#endif
1371} PGMCHUNKR3MAPTLBE;
1372/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1373typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1374
1375/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1376 * @remark Must be a power of two value. */
1377#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1378
1379/**
1380 * Allocation chunk ring-3 mapping TLB.
1381 *
1382 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1383 * At first glance this might look kinda odd since AVL trees are
1384 * supposed to give the most optimial lookup times of all trees
1385 * due to their balancing. However, take a tree with 1023 nodes
1386 * in it, that's 10 levels, meaning that most searches has to go
1387 * down 9 levels before they find what they want. This isn't fast
1388 * compared to a TLB hit. There is the factor of cache misses,
1389 * and of course the problem with trees and branch prediction.
1390 * This is why we use TLBs in front of most of the trees.
1391 *
1392 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1393 * difficult when we switch to the new inlined AVL trees (from kStuff).
1394 */
1395typedef struct PGMCHUNKR3MAPTLB
1396{
1397 /** The TLB entries. */
1398 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1399} PGMCHUNKR3MAPTLB;
1400
1401/**
1402 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1403 * @returns Chunk TLB index.
1404 * @param idChunk The Chunk ID.
1405 */
1406#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1407
1408
1409/**
1410 * Ring-3 guest page mapping TLB entry.
1411 * @remarks used in ring-0 as well at the moment.
1412 */
1413typedef struct PGMPAGER3MAPTLBE
1414{
1415 /** Address of the page. */
1416 RTGCPHYS volatile GCPhys;
1417 /** The guest page. */
1418#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1419 R3PTRTYPE(PPGMPAGE) volatile pPage;
1420#else
1421 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1422#endif
1423 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1424#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1425 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1426#else
1427 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1428#endif
1429 /** The address */
1430#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1431 R3PTRTYPE(void *) volatile pv;
1432#else
1433 R3R0PTRTYPE(void *) volatile pv;
1434#endif
1435#if HC_ARCH_BITS == 32
1436 uint32_t u32Padding; /**< alignment padding. */
1437#endif
1438} PGMPAGER3MAPTLBE;
1439/** Pointer to an entry in the HC physical TLB. */
1440typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1441
1442
1443/** The number of entries in the ring-3 guest page mapping TLB.
1444 * @remarks The value must be a power of two. */
1445#define PGM_PAGER3MAPTLB_ENTRIES 64
1446
1447/**
1448 * Ring-3 guest page mapping TLB.
1449 * @remarks used in ring-0 as well at the moment.
1450 */
1451typedef struct PGMPAGER3MAPTLB
1452{
1453 /** The TLB entries. */
1454 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1455} PGMPAGER3MAPTLB;
1456/** Pointer to the ring-3 guest page mapping TLB. */
1457typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1458
1459/**
1460 * Calculates the index of the TLB entry for the specified guest page.
1461 * @returns Physical TLB index.
1462 * @param GCPhys The guest physical address.
1463 */
1464#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1465
1466
1467/**
1468 * Mapping cache usage set entry.
1469 *
1470 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1471 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1472 * cache. If it's extended to include ring-3, well, then something will
1473 * have be changed here...
1474 */
1475typedef struct PGMMAPSETENTRY
1476{
1477 /** The mapping cache index. */
1478 uint16_t iPage;
1479 /** The number of references.
1480 * The max is UINT16_MAX - 1. */
1481 uint16_t cRefs;
1482#if HC_ARCH_BITS == 64
1483 uint32_t alignment;
1484#endif
1485 /** Pointer to the page. */
1486 RTR0PTR pvPage;
1487 /** The physical address for this entry. */
1488 RTHCPHYS HCPhys;
1489} PGMMAPSETENTRY;
1490/** Pointer to a mapping cache usage set entry. */
1491typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1492
1493/**
1494 * Mapping cache usage set.
1495 *
1496 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1497 * done during exits / traps. The set is
1498 */
1499typedef struct PGMMAPSET
1500{
1501 /** The number of occupied entries.
1502 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1503 * dynamic mappings. */
1504 uint32_t cEntries;
1505 /** The start of the current subset.
1506 * This is UINT32_MAX if no subset is currently open. */
1507 uint32_t iSubset;
1508 /** The index of the current CPU, only valid if the set is open. */
1509 int32_t iCpu;
1510#if HC_ARCH_BITS == 64
1511 uint32_t alignment;
1512#endif
1513 /** The entries. */
1514 PGMMAPSETENTRY aEntries[64];
1515 /** HCPhys -> iEntry fast lookup table.
1516 * Use PGMMAPSET_HASH for hashing.
1517 * The entries may or may not be valid, check against cEntries. */
1518 uint8_t aiHashTable[128];
1519} PGMMAPSET;
1520/** Pointer to the mapping cache set. */
1521typedef PGMMAPSET *PPGMMAPSET;
1522
1523/** PGMMAPSET::cEntries value for a closed set. */
1524#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1525
1526/** Hash function for aiHashTable. */
1527#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1528
1529/** The max fill size (strict builds). */
1530#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1531
1532
1533/** @name Context neutrual page mapper TLB.
1534 *
1535 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1536 * code is writting in a kind of context neutrual way. Time will show whether
1537 * this actually makes sense or not...
1538 *
1539 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1540 * context ends up using a global mapping cache on some platforms
1541 * (darwin).
1542 *
1543 * @{ */
1544/** @typedef PPGMPAGEMAPTLB
1545 * The page mapper TLB pointer type for the current context. */
1546/** @typedef PPGMPAGEMAPTLB
1547 * The page mapper TLB entry pointer type for the current context. */
1548/** @typedef PPGMPAGEMAPTLB
1549 * The page mapper TLB entry pointer pointer type for the current context. */
1550/** @def PGM_PAGEMAPTLB_ENTRIES
1551 * The number of TLB entries in the page mapper TLB for the current context. */
1552/** @def PGM_PAGEMAPTLB_IDX
1553 * Calculate the TLB index for a guest physical address.
1554 * @returns The TLB index.
1555 * @param GCPhys The guest physical address. */
1556/** @typedef PPGMPAGEMAP
1557 * Pointer to a page mapper unit for current context. */
1558/** @typedef PPPGMPAGEMAP
1559 * Pointer to a page mapper unit pointer for current context. */
1560#ifdef IN_RC
1561// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1562// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1563// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1564# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1565# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1566 typedef void * PPGMPAGEMAP;
1567 typedef void ** PPPGMPAGEMAP;
1568//#elif IN_RING0
1569// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1570// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1571// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1572//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1573//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1574// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1575// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1576#else
1577 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1578 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1579 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1580# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1581# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1582 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1583 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1584#endif
1585/** @} */
1586
1587
1588/** @name PGM Pool Indexes.
1589 * Aka. the unique shadow page identifier.
1590 * @{ */
1591/** NIL page pool IDX. */
1592#define NIL_PGMPOOL_IDX 0
1593/** The first normal index. */
1594#define PGMPOOL_IDX_FIRST_SPECIAL 1
1595/** Page directory (32-bit root). */
1596#define PGMPOOL_IDX_PD 1
1597/** Page Directory Pointer Table (PAE root). */
1598#define PGMPOOL_IDX_PDPT 2
1599/** AMD64 CR3 level index.*/
1600#define PGMPOOL_IDX_AMD64_CR3 3
1601/** Nested paging root.*/
1602#define PGMPOOL_IDX_NESTED_ROOT 4
1603/** The first normal index. */
1604#define PGMPOOL_IDX_FIRST 5
1605/** The last valid index. (inclusive, 14 bits) */
1606#define PGMPOOL_IDX_LAST 0x3fff
1607/** @} */
1608
1609/** The NIL index for the parent chain. */
1610#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1611#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1612
1613/**
1614 * Node in the chain linking a shadowed page to it's parent (user).
1615 */
1616#pragma pack(1)
1617typedef struct PGMPOOLUSER
1618{
1619 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1620 uint16_t iNext;
1621 /** The user page index. */
1622 uint16_t iUser;
1623 /** Index into the user table. */
1624 uint32_t iUserTable;
1625} PGMPOOLUSER, *PPGMPOOLUSER;
1626typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1627#pragma pack()
1628
1629
1630/** The NIL index for the phys ext chain. */
1631#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1632
1633/**
1634 * Node in the chain of physical cross reference extents.
1635 * @todo Calling this an 'extent' is not quite right, find a better name.
1636 */
1637#pragma pack(1)
1638typedef struct PGMPOOLPHYSEXT
1639{
1640 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1641 uint16_t iNext;
1642 /** The user page index. */
1643 uint16_t aidx[3];
1644} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1645typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1646#pragma pack()
1647
1648
1649/**
1650 * The kind of page that's being shadowed.
1651 */
1652typedef enum PGMPOOLKIND
1653{
1654 /** The virtual invalid 0 entry. */
1655 PGMPOOLKIND_INVALID = 0,
1656 /** The entry is free (=unused). */
1657 PGMPOOLKIND_FREE,
1658
1659 /** Shw: 32-bit page table; Gst: no paging */
1660 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1661 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1662 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1663 /** Shw: 32-bit page table; Gst: 4MB page. */
1664 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1665 /** Shw: PAE page table; Gst: no paging */
1666 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1667 /** Shw: PAE page table; Gst: 32-bit page table. */
1668 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1669 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1670 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1671 /** Shw: PAE page table; Gst: PAE page table. */
1672 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1673 /** Shw: PAE page table; Gst: 2MB page. */
1674 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1675
1676 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1677 PGMPOOLKIND_32BIT_PD,
1678 /** Shw: 32-bit page directory. Gst: no paging. */
1679 PGMPOOLKIND_32BIT_PD_PHYS,
1680 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1681 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1682 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1683 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1684 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1685 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1686 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1687 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1688 /** Shw: PAE page directory; Gst: PAE page directory. */
1689 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1690 /** Shw: PAE page directory; Gst: no paging. */
1691 PGMPOOLKIND_PAE_PD_PHYS,
1692
1693 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1694 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1695 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1696 PGMPOOLKIND_PAE_PDPT,
1697 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1698 PGMPOOLKIND_PAE_PDPT_PHYS,
1699
1700 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1701 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1702 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1703 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1704 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1705 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1706 /** Shw: 64-bit page directory table; Gst: no paging */
1707 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1708
1709 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1710 PGMPOOLKIND_64BIT_PML4,
1711
1712 /** Shw: EPT page directory pointer table; Gst: no paging */
1713 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1714 /** Shw: EPT page directory table; Gst: no paging */
1715 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1716 /** Shw: EPT page table; Gst: no paging */
1717 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1718
1719 /** Shw: Root Nested paging table. */
1720 PGMPOOLKIND_ROOT_NESTED,
1721
1722 /** The last valid entry. */
1723 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1724} PGMPOOLKIND;
1725
1726/**
1727 * The access attributes of the page; only applies to big pages.
1728 */
1729typedef enum
1730{
1731 PGMPOOLACCESS_DONTCARE = 0,
1732 PGMPOOLACCESS_USER_RW,
1733 PGMPOOLACCESS_USER_R,
1734 PGMPOOLACCESS_USER_RW_NX,
1735 PGMPOOLACCESS_USER_R_NX,
1736 PGMPOOLACCESS_SUPERVISOR_RW,
1737 PGMPOOLACCESS_SUPERVISOR_R,
1738 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1739 PGMPOOLACCESS_SUPERVISOR_R_NX
1740} PGMPOOLACCESS;
1741
1742/**
1743 * The tracking data for a page in the pool.
1744 */
1745typedef struct PGMPOOLPAGE
1746{
1747 /** AVL node code with the (R3) physical address of this page. */
1748 AVLOHCPHYSNODECORE Core;
1749 /** Pointer to the R3 mapping of the page. */
1750#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1751 R3PTRTYPE(void *) pvPageR3;
1752#else
1753 R3R0PTRTYPE(void *) pvPageR3;
1754#endif
1755 /** The guest physical address. */
1756#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1757 uint32_t Alignment0;
1758#endif
1759 RTGCPHYS GCPhys;
1760
1761 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1762 RTGCPTR pvLastAccessHandlerRip;
1763 RTGCPTR pvLastAccessHandlerFault;
1764 uint64_t cLastAccessHandlerCount;
1765
1766 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1767 uint8_t enmKind;
1768 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1769 uint8_t enmAccess;
1770 /** The index of this page. */
1771 uint16_t idx;
1772 /** The next entry in the list this page currently resides in.
1773 * It's either in the free list or in the GCPhys hash. */
1774 uint16_t iNext;
1775#ifdef PGMPOOL_WITH_USER_TRACKING
1776 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1777 uint16_t iUserHead;
1778 /** The number of present entries. */
1779 uint16_t cPresent;
1780 /** The first entry in the table which is present. */
1781 uint16_t iFirstPresent;
1782#endif
1783#ifdef PGMPOOL_WITH_MONITORING
1784 /** The number of modifications to the monitored page. */
1785 uint16_t cModifications;
1786 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1787 uint16_t iModifiedNext;
1788 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1789 uint16_t iModifiedPrev;
1790 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1791 uint16_t iMonitoredNext;
1792 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1793 uint16_t iMonitoredPrev;
1794#endif
1795#ifdef PGMPOOL_WITH_CACHE
1796 /** The next page in the age list. */
1797 uint16_t iAgeNext;
1798 /** The previous page in the age list. */
1799 uint16_t iAgePrev;
1800#endif /* PGMPOOL_WITH_CACHE */
1801 /** Used to indicate that the page is zeroed. */
1802 bool fZeroed;
1803 /** Used to indicate that a PT has non-global entries. */
1804 bool fSeenNonGlobal;
1805 /** Used to indicate that we're monitoring writes to the guest page. */
1806 bool fMonitored;
1807 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1808 * (All pages are in the age list.) */
1809 bool fCached;
1810 /** This is used by the R3 access handlers when invoked by an async thread.
1811 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1812 bool volatile fReusedFlushPending;
1813 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1814 bool fDirty;
1815
1816 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1817 uint32_t cLocked;
1818 uint32_t idxDirty;
1819 RTGCPTR pvDirtyFault;
1820} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1821/** Pointer to a const pool page. */
1822typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1823
1824
1825#ifdef PGMPOOL_WITH_CACHE
1826/** The hash table size. */
1827# define PGMPOOL_HASH_SIZE 0x40
1828/** The hash function. */
1829# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1830#endif
1831
1832
1833/**
1834 * The shadow page pool instance data.
1835 *
1836 * It's all one big allocation made at init time, except for the
1837 * pages that is. The user nodes follows immediatly after the
1838 * page structures.
1839 */
1840typedef struct PGMPOOL
1841{
1842 /** The VM handle - R3 Ptr. */
1843 PVMR3 pVMR3;
1844 /** The VM handle - R0 Ptr. */
1845 PVMR0 pVMR0;
1846 /** The VM handle - RC Ptr. */
1847 PVMRC pVMRC;
1848 /** The max pool size. This includes the special IDs. */
1849 uint16_t cMaxPages;
1850 /** The current pool size. */
1851 uint16_t cCurPages;
1852 /** The head of the free page list. */
1853 uint16_t iFreeHead;
1854 /* Padding. */
1855 uint16_t u16Padding;
1856#ifdef PGMPOOL_WITH_USER_TRACKING
1857 /** Head of the chain of free user nodes. */
1858 uint16_t iUserFreeHead;
1859 /** The number of user nodes we've allocated. */
1860 uint16_t cMaxUsers;
1861 /** The number of present page table entries in the entire pool. */
1862 uint32_t cPresent;
1863 /** Pointer to the array of user nodes - RC pointer. */
1864 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1865 /** Pointer to the array of user nodes - R3 pointer. */
1866 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1867 /** Pointer to the array of user nodes - R0 pointer. */
1868 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1869#endif /* PGMPOOL_WITH_USER_TRACKING */
1870#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1871 /** Head of the chain of free phys ext nodes. */
1872 uint16_t iPhysExtFreeHead;
1873 /** The number of user nodes we've allocated. */
1874 uint16_t cMaxPhysExts;
1875 /** Pointer to the array of physical xref extent - RC pointer. */
1876 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1877 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1878 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1879 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1880 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1881#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1882#ifdef PGMPOOL_WITH_CACHE
1883 /** Hash table for GCPhys addresses. */
1884 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1885 /** The head of the age list. */
1886 uint16_t iAgeHead;
1887 /** The tail of the age list. */
1888 uint16_t iAgeTail;
1889 /** Set if the cache is enabled. */
1890 bool fCacheEnabled;
1891 /** Alignment padding. */
1892 bool afPadding1[3];
1893#endif /* PGMPOOL_WITH_CACHE */
1894#ifdef PGMPOOL_WITH_MONITORING
1895 /** Head of the list of modified pages. */
1896 uint16_t iModifiedHead;
1897 /** The current number of modified pages. */
1898 uint16_t cModifiedPages;
1899 /** Access handler, RC. */
1900 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1901 /** Access handler, R0. */
1902 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1903 /** Access handler, R3. */
1904 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1905 /** The access handler description (R3 ptr). */
1906 R3PTRTYPE(const char *) pszAccessHandler;
1907# if HC_ARCH_BITS == 32
1908 /** Alignment padding. */
1909 uint32_t u32Padding2;
1910# endif
1911 /* Next available slot. */
1912 uint32_t idxFreeDirtyPage;
1913 /* Number of active dirty pages. */
1914 uint32_t cDirtyPages;
1915 /* Array of current dirty pgm pool page indices. */
1916 uint16_t aIdxDirtyPages[16];
1917 uint64_t aDirtyPages[16][512];
1918#endif /* PGMPOOL_WITH_MONITORING */
1919 /** The number of pages currently in use. */
1920 uint16_t cUsedPages;
1921#ifdef VBOX_WITH_STATISTICS
1922 /** The high water mark for cUsedPages. */
1923 uint16_t cUsedPagesHigh;
1924 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1925 /** Profiling pgmPoolAlloc(). */
1926 STAMPROFILEADV StatAlloc;
1927 /** Profiling pgmR3PoolClearDoIt(). */
1928 STAMPROFILE StatClearAll;
1929 /** Profiling pgmR3PoolReset(). */
1930 STAMPROFILE StatR3Reset;
1931 /** Profiling pgmPoolFlushPage(). */
1932 STAMPROFILE StatFlushPage;
1933 /** Profiling pgmPoolFree(). */
1934 STAMPROFILE StatFree;
1935 /** Counting explicit flushes by PGMPoolFlushPage(). */
1936 STAMCOUNTER StatForceFlushPage;
1937 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1938 STAMCOUNTER StatForceFlushDirtyPage;
1939 /** Counting flushes for reused pages. */
1940 STAMCOUNTER StatForceFlushReused;
1941 /** Profiling time spent zeroing pages. */
1942 STAMPROFILE StatZeroPage;
1943# ifdef PGMPOOL_WITH_USER_TRACKING
1944 /** Profiling of pgmPoolTrackDeref. */
1945 STAMPROFILE StatTrackDeref;
1946 /** Profiling pgmTrackFlushGCPhysPT. */
1947 STAMPROFILE StatTrackFlushGCPhysPT;
1948 /** Profiling pgmTrackFlushGCPhysPTs. */
1949 STAMPROFILE StatTrackFlushGCPhysPTs;
1950 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1951 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1952 /** Number of times we've been out of user records. */
1953 STAMCOUNTER StatTrackFreeUpOneUser;
1954 /** Nr of flushed entries. */
1955 STAMCOUNTER StatTrackFlushEntry;
1956 /** Nr of updated entries. */
1957 STAMCOUNTER StatTrackFlushEntryKeep;
1958# endif
1959# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1960 /** Profiling deref activity related tracking GC physical pages. */
1961 STAMPROFILE StatTrackDerefGCPhys;
1962 /** Number of linear searches for a HCPhys in the ram ranges. */
1963 STAMCOUNTER StatTrackLinearRamSearches;
1964 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1965 STAMCOUNTER StamTrackPhysExtAllocFailures;
1966# endif
1967# ifdef PGMPOOL_WITH_MONITORING
1968 /** Profiling the RC/R0 access handler. */
1969 STAMPROFILE StatMonitorRZ;
1970 /** Times we've failed interpreting the instruction. */
1971 STAMCOUNTER StatMonitorRZEmulateInstr;
1972 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1973 STAMPROFILE StatMonitorRZFlushPage;
1974 /* Times we've detected a page table reinit. */
1975 STAMCOUNTER StatMonitorRZFlushReinit;
1976 /** Counting flushes for pages that are modified too often. */
1977 STAMCOUNTER StatMonitorRZFlushModOverflow;
1978 /** Times we've detected fork(). */
1979 STAMCOUNTER StatMonitorRZFork;
1980 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1981 STAMPROFILE StatMonitorRZHandled;
1982 /** Times we've failed interpreting a patch code instruction. */
1983 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1984 /** Times we've failed interpreting a patch code instruction during flushing. */
1985 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1986 /** The number of times we've seen rep prefixes we can't handle. */
1987 STAMCOUNTER StatMonitorRZRepPrefix;
1988 /** Profiling the REP STOSD cases we've handled. */
1989 STAMPROFILE StatMonitorRZRepStosd;
1990 /** Nr of handled PT faults. */
1991 STAMCOUNTER StatMonitorRZFaultPT;
1992 /** Nr of handled PD faults. */
1993 STAMCOUNTER StatMonitorRZFaultPD;
1994 /** Nr of handled PDPT faults. */
1995 STAMCOUNTER StatMonitorRZFaultPDPT;
1996 /** Nr of handled PML4 faults. */
1997 STAMCOUNTER StatMonitorRZFaultPML4;
1998
1999 /** Profiling the R3 access handler. */
2000 STAMPROFILE StatMonitorR3;
2001 /** Times we've failed interpreting the instruction. */
2002 STAMCOUNTER StatMonitorR3EmulateInstr;
2003 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2004 STAMPROFILE StatMonitorR3FlushPage;
2005 /* Times we've detected a page table reinit. */
2006 STAMCOUNTER StatMonitorR3FlushReinit;
2007 /** Counting flushes for pages that are modified too often. */
2008 STAMCOUNTER StatMonitorR3FlushModOverflow;
2009 /** Times we've detected fork(). */
2010 STAMCOUNTER StatMonitorR3Fork;
2011 /** Profiling the R3 access we've handled (except REP STOSD). */
2012 STAMPROFILE StatMonitorR3Handled;
2013 /** The number of times we've seen rep prefixes we can't handle. */
2014 STAMCOUNTER StatMonitorR3RepPrefix;
2015 /** Profiling the REP STOSD cases we've handled. */
2016 STAMPROFILE StatMonitorR3RepStosd;
2017 /** Nr of handled PT faults. */
2018 STAMCOUNTER StatMonitorR3FaultPT;
2019 /** Nr of handled PD faults. */
2020 STAMCOUNTER StatMonitorR3FaultPD;
2021 /** Nr of handled PDPT faults. */
2022 STAMCOUNTER StatMonitorR3FaultPDPT;
2023 /** Nr of handled PML4 faults. */
2024 STAMCOUNTER StatMonitorR3FaultPML4;
2025 /** The number of times we're called in an async thread an need to flush. */
2026 STAMCOUNTER StatMonitorR3Async;
2027 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2028 STAMCOUNTER StatResetDirtyPages;
2029 /** Times we've called pgmPoolAddDirtyPage. */
2030 STAMCOUNTER StatDirtyPage;
2031 /** Times we've had to flush duplicates for dirty page management. */
2032 STAMCOUNTER StatDirtyPageDupFlush;
2033 /** Times we've had to flush because of overflow. */
2034 STAMCOUNTER StatDirtyPageOverFlowFlush;
2035
2036 /** The high wather mark for cModifiedPages. */
2037 uint16_t cModifiedPagesHigh;
2038 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2039# endif
2040# ifdef PGMPOOL_WITH_CACHE
2041 /** The number of cache hits. */
2042 STAMCOUNTER StatCacheHits;
2043 /** The number of cache misses. */
2044 STAMCOUNTER StatCacheMisses;
2045 /** The number of times we've got a conflict of 'kind' in the cache. */
2046 STAMCOUNTER StatCacheKindMismatches;
2047 /** Number of times we've been out of pages. */
2048 STAMCOUNTER StatCacheFreeUpOne;
2049 /** The number of cacheable allocations. */
2050 STAMCOUNTER StatCacheCacheable;
2051 /** The number of uncacheable allocations. */
2052 STAMCOUNTER StatCacheUncacheable;
2053# endif
2054#else
2055 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2056#endif
2057 /** The AVL tree for looking up a page by its HC physical address. */
2058 AVLOHCPHYSTREE HCPhysTree;
2059 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2060 /** Array of pages. (cMaxPages in length)
2061 * The Id is the index into thist array.
2062 */
2063 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2064} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2065#ifdef PGMPOOL_WITH_MONITORING
2066AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2067AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2068#endif
2069AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2070#ifdef VBOX_WITH_STATISTICS
2071AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2072#endif
2073AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2074
2075
2076/** @def PGMPOOL_PAGE_2_PTR
2077 * Maps a pool page pool into the current context.
2078 *
2079 * @returns VBox status code.
2080 * @param pVM The VM handle.
2081 * @param pPage The pool page.
2082 *
2083 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2084 * small page window employeed by that function. Be careful.
2085 * @remark There is no need to assert on the result.
2086 */
2087#if defined(IN_RC)
2088# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2089#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2090# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2091#elif defined(VBOX_STRICT)
2092# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2093DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2094{
2095 Assert(pPage && pPage->pvPageR3);
2096 return pPage->pvPageR3;
2097}
2098#else
2099# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2100#endif
2101
2102/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2103 * Maps a pool page pool into the current context.
2104 *
2105 * @returns VBox status code.
2106 * @param pPGM Pointer to the PGM instance data.
2107 * @param pPage The pool page.
2108 *
2109 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2110 * small page window employeed by that function. Be careful.
2111 * @remark There is no need to assert on the result.
2112 */
2113#if defined(IN_RC)
2114# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2115#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2116# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2117#else
2118# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2119#endif
2120
2121/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2122 * Maps a pool page pool into the current context.
2123 *
2124 * @returns VBox status code.
2125 * @param pPGM Pointer to the PGMCPU instance data.
2126 * @param pPage The pool page.
2127 *
2128 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2129 * small page window employeed by that function. Be careful.
2130 * @remark There is no need to assert on the result.
2131 */
2132#if defined(IN_RC)
2133# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2134#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2135# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2136#else
2137# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2138#endif
2139
2140
2141/** @name Per guest page tracking data.
2142 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2143 * is to use more bits for it and split it up later on. But for now we'll play
2144 * safe and change as little as possible.
2145 *
2146 * The 16-bit word has two parts:
2147 *
2148 * The first 14-bit forms the @a idx field. It is either the index of a page in
2149 * the shadow page pool, or and index into the extent list.
2150 *
2151 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2152 * shadow page pool references to the page. If cRefs equals
2153 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2154 * (misnomer) table and not the shadow page pool.
2155 *
2156 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2157 * the 16-bit word.
2158 *
2159 * @{ */
2160/** The shift count for getting to the cRefs part. */
2161#define PGMPOOL_TD_CREFS_SHIFT 14
2162/** The mask applied after shifting the tracking data down by
2163 * PGMPOOL_TD_CREFS_SHIFT. */
2164#define PGMPOOL_TD_CREFS_MASK 0x3
2165/** The cRef value used to indiciate that the idx is the head of a
2166 * physical cross reference list. */
2167#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2168/** The shift used to get idx. */
2169#define PGMPOOL_TD_IDX_SHIFT 0
2170/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2171#define PGMPOOL_TD_IDX_MASK 0x3fff
2172/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2173 * simply too many mappings of this page. */
2174#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2175
2176/** @def PGMPOOL_TD_MAKE
2177 * Makes a 16-bit tracking data word.
2178 *
2179 * @returns tracking data.
2180 * @param cRefs The @a cRefs field. Must be within bounds!
2181 * @param idx The @a idx field. Must also be within bounds! */
2182#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2183
2184/** @def PGMPOOL_TD_GET_CREFS
2185 * Get the @a cRefs field from a tracking data word.
2186 *
2187 * @returns The @a cRefs field
2188 * @param u16 The tracking data word. */
2189#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2190
2191/** @def PGMPOOL_TD_GET_IDX
2192 * Get the @a idx field from a tracking data word.
2193 *
2194 * @returns The @a idx field
2195 * @param u16 The tracking data word. */
2196#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2197/** @} */
2198
2199
2200/**
2201 * Trees are using self relative offsets as pointers.
2202 * So, all its data, including the root pointer, must be in the heap for HC and GC
2203 * to have the same layout.
2204 */
2205typedef struct PGMTREES
2206{
2207 /** Physical access handlers (AVL range+offsetptr tree). */
2208 AVLROGCPHYSTREE PhysHandlers;
2209 /** Virtual access handlers (AVL range + GC ptr tree). */
2210 AVLROGCPTRTREE VirtHandlers;
2211 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2212 AVLROGCPHYSTREE PhysToVirtHandlers;
2213 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2214 AVLROGCPTRTREE HyperVirtHandlers;
2215} PGMTREES;
2216/** Pointer to PGM trees. */
2217typedef PGMTREES *PPGMTREES;
2218
2219
2220/** @name Paging mode macros
2221 * @{ */
2222#ifdef IN_RC
2223# define PGM_CTX(a,b) a##RC##b
2224# define PGM_CTX_STR(a,b) a "GC" b
2225# define PGM_CTX_DECL(type) VMMRCDECL(type)
2226#else
2227# ifdef IN_RING3
2228# define PGM_CTX(a,b) a##R3##b
2229# define PGM_CTX_STR(a,b) a "R3" b
2230# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2231# else
2232# define PGM_CTX(a,b) a##R0##b
2233# define PGM_CTX_STR(a,b) a "R0" b
2234# define PGM_CTX_DECL(type) VMMDECL(type)
2235# endif
2236#endif
2237
2238#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2239#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2240#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2241#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2242#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2243#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2244#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2245#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2246#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2247#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2248#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2249#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2250#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2251#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2252#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2253#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2254#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2255
2256#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2257#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2258#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2259#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2260#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2261#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2262#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2263#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2264#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2265#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2266#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2267#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2268#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2269#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2270#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2271#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2272#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2273
2274/* Shw_Gst */
2275#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2276#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2277#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2278#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2279#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2280#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2281#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2282#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2283#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2284#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2285#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2286#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2287#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2288#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2289#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2290#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2291#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2292#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2293#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2294
2295#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2296#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2297#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2298#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2299#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2300#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2301#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2302#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2303#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2304#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2305#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2306#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2307#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2308#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2309#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2310#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2311#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2312#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2313#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2314#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2315#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2316#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2317#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2318#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2319#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2320#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2321#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2322#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2323#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2324#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2325#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2326#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2327#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2328#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2329#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2330#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2331#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2332
2333#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2334#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2335/** @} */
2336
2337/**
2338 * Data for each paging mode.
2339 */
2340typedef struct PGMMODEDATA
2341{
2342 /** The guest mode type. */
2343 uint32_t uGstType;
2344 /** The shadow mode type. */
2345 uint32_t uShwType;
2346
2347 /** @name Function pointers for Shadow paging.
2348 * @{
2349 */
2350 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2351 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2352 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2353 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2354
2355 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2356 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2357
2358 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2359 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2360 /** @} */
2361
2362 /** @name Function pointers for Guest paging.
2363 * @{
2364 */
2365 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2366 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2367 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2368 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2369 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2370 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2371 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2372 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2373 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2374 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2375 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2376 /** @} */
2377
2378 /** @name Function pointers for Both Shadow and Guest paging.
2379 * @{
2380 */
2381 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2382 /* no pfnR3BthTrap0eHandler */
2383 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2384 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2385 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2386 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2387 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2388#ifdef VBOX_STRICT
2389 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2390#endif
2391 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2392 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2393
2394 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2395 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2396 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2397 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2398 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2399 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2400#ifdef VBOX_STRICT
2401 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2402#endif
2403 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2404 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2405
2406 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2407 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2408 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2409 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2410 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2411 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2412#ifdef VBOX_STRICT
2413 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2414#endif
2415 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2416 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2417 /** @} */
2418} PGMMODEDATA, *PPGMMODEDATA;
2419
2420
2421
2422/**
2423 * Converts a PGM pointer into a VM pointer.
2424 * @returns Pointer to the VM structure the PGM is part of.
2425 * @param pPGM Pointer to PGM instance data.
2426 */
2427#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2428
2429/**
2430 * PGM Data (part of VM)
2431 */
2432typedef struct PGM
2433{
2434 /** Offset to the VM structure. */
2435 RTINT offVM;
2436 /** Offset of the PGMCPU structure relative to VMCPU. */
2437 RTINT offVCpuPGM;
2438
2439 /** @cfgm{RamPreAlloc, boolean, false}
2440 * Indicates whether the base RAM should all be allocated before starting
2441 * the VM (default), or if it should be allocated when first written to.
2442 */
2443 bool fRamPreAlloc;
2444 /** Indicates whether write monitoring is currently in use.
2445 * This is used to prevent conflicts between live saving and page sharing
2446 * detection. */
2447 bool fPhysWriteMonitoringEngaged;
2448 /** Alignment padding. */
2449 bool afAlignment0[2];
2450
2451 /*
2452 * This will be redefined at least two more times before we're done, I'm sure.
2453 * The current code is only to get on with the coding.
2454 * - 2004-06-10: initial version, bird.
2455 * - 2004-07-02: 1st time, bird.
2456 * - 2004-10-18: 2nd time, bird.
2457 * - 2005-07-xx: 3rd time, bird.
2458 */
2459
2460 /** The host paging mode. (This is what SUPLib reports.) */
2461 SUPPAGINGMODE enmHostMode;
2462
2463 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2464 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2465 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2466 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2467
2468 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2469 RTGCPHYS GCPhys4MBPSEMask;
2470
2471 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2472 * This is sorted by physical address and contains no overlapping ranges. */
2473 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2474 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2475 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2476 /** RC pointer corresponding to PGM::pRamRangesR3. */
2477 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2478 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2479 * range is linked or unlinked. */
2480 uint32_t volatile idRamRangesGen;
2481
2482 /** Pointer to the list of ROM ranges - for R3.
2483 * This is sorted by physical address and contains no overlapping ranges. */
2484 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2485 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2486 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2487 /** RC pointer corresponding to PGM::pRomRangesR3. */
2488 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2489#if HC_ARCH_BITS == 64
2490 /** Alignment padding. */
2491 RTRCPTR GCPtrPadding2;
2492#endif
2493
2494 /** Pointer to the list of MMIO2 ranges - for R3.
2495 * Registration order. */
2496 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2497
2498 /** PGM offset based trees - R3 Ptr. */
2499 R3PTRTYPE(PPGMTREES) pTreesR3;
2500 /** PGM offset based trees - R0 Ptr. */
2501 R0PTRTYPE(PPGMTREES) pTreesR0;
2502 /** PGM offset based trees - RC Ptr. */
2503 RCPTRTYPE(PPGMTREES) pTreesRC;
2504
2505 /** Linked list of GC mappings - for RC.
2506 * The list is sorted ascending on address.
2507 */
2508 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2509 /** Linked list of GC mappings - for HC.
2510 * The list is sorted ascending on address.
2511 */
2512 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2513 /** Linked list of GC mappings - for R0.
2514 * The list is sorted ascending on address.
2515 */
2516 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2517
2518 /** Pointer to the 5 page CR3 content mapping.
2519 * The first page is always the CR3 (in some form) while the 4 other pages
2520 * are used of the PDs in PAE mode. */
2521 RTGCPTR GCPtrCR3Mapping;
2522#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2523 uint32_t u32Alignment1;
2524#endif
2525
2526 /** Indicates that PGMR3FinalizeMappings has been called and that further
2527 * PGMR3MapIntermediate calls will be rejected. */
2528 bool fFinalizedMappings;
2529 /** If set no conflict checks are required. (boolean) */
2530 bool fMappingsFixed;
2531 /** If set, then no mappings are put into the shadow page table. (boolean) */
2532 bool fDisableMappings;
2533 /** Size of fixed mapping */
2534 uint32_t cbMappingFixed;
2535 /** Base address (GC) of fixed mapping */
2536 RTGCPTR GCPtrMappingFixed;
2537 /** The address of the previous RAM range mapping. */
2538 RTGCPTR GCPtrPrevRamRangeMapping;
2539
2540 /** @name Intermediate Context
2541 * @{ */
2542 /** Pointer to the intermediate page directory - Normal. */
2543 R3PTRTYPE(PX86PD) pInterPD;
2544 /** Pointer to the intermedate page tables - Normal.
2545 * There are two page tables, one for the identity mapping and one for
2546 * the host context mapping (of the core code). */
2547 R3PTRTYPE(PX86PT) apInterPTs[2];
2548 /** Pointer to the intermedate page tables - PAE. */
2549 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2550 /** Pointer to the intermedate page directory - PAE. */
2551 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2552 /** Pointer to the intermedate page directory - PAE. */
2553 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2554 /** Pointer to the intermedate page-map level 4 - AMD64. */
2555 R3PTRTYPE(PX86PML4) pInterPaePML4;
2556 /** Pointer to the intermedate page directory - AMD64. */
2557 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2558 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2559 RTHCPHYS HCPhysInterPD;
2560 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2561 RTHCPHYS HCPhysInterPaePDPT;
2562 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2563 RTHCPHYS HCPhysInterPaePML4;
2564 /** @} */
2565
2566 /** Base address of the dynamic page mapping area.
2567 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2568 */
2569 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2570 /** The index of the last entry used in the dynamic page mapping area. */
2571 RTUINT iDynPageMapLast;
2572 /** Cache containing the last entries in the dynamic page mapping area.
2573 * The cache size is covering half of the mapping area. */
2574 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2575 /** Keep a lock counter for the full (!) mapping area. */
2576 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2577
2578 /** The address of the ring-0 mapping cache if we're making use of it. */
2579 RTR0PTR pvR0DynMapUsed;
2580#if HC_ARCH_BITS == 32
2581 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2582 uint32_t u32Alignment2;
2583#endif
2584
2585 /** PGM critical section.
2586 * This protects the physical & virtual access handlers, ram ranges,
2587 * and the page flag updating (some of it anyway).
2588 */
2589 PDMCRITSECT CritSect;
2590
2591 /** Pointer to SHW+GST mode data (function pointers).
2592 * The index into this table is made up from */
2593 R3PTRTYPE(PPGMMODEDATA) paModeData;
2594
2595 /** Shadow Page Pool - R3 Ptr. */
2596 R3PTRTYPE(PPGMPOOL) pPoolR3;
2597 /** Shadow Page Pool - R0 Ptr. */
2598 R0PTRTYPE(PPGMPOOL) pPoolR0;
2599 /** Shadow Page Pool - RC Ptr. */
2600 RCPTRTYPE(PPGMPOOL) pPoolRC;
2601
2602 /** We're not in a state which permits writes to guest memory.
2603 * (Only used in strict builds.) */
2604 bool fNoMorePhysWrites;
2605 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2606 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2607
2608 /**
2609 * Data associated with managing the ring-3 mappings of the allocation chunks.
2610 */
2611 struct
2612 {
2613 /** The chunk tree, ordered by chunk id. */
2614#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2615 R3PTRTYPE(PAVLU32NODECORE) pTree;
2616#else
2617 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2618#endif
2619 /** The chunk age tree, ordered by ageing sequence number. */
2620 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2621 /** The chunk mapping TLB. */
2622 PGMCHUNKR3MAPTLB Tlb;
2623 /** The number of mapped chunks. */
2624 uint32_t c;
2625 /** The maximum number of mapped chunks.
2626 * @cfgm PGM/MaxRing3Chunks */
2627 uint32_t cMax;
2628 /** The current time. */
2629 uint32_t iNow;
2630 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2631 uint32_t AgeingCountdown;
2632 } ChunkR3Map;
2633
2634 /**
2635 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2636 */
2637 PGMPAGER3MAPTLB PhysTlbHC;
2638
2639 /** @name The zero page.
2640 * @{ */
2641 /** The host physical address of the zero page. */
2642 RTHCPHYS HCPhysZeroPg;
2643 /** The ring-3 mapping of the zero page. */
2644 RTR3PTR pvZeroPgR3;
2645 /** The ring-0 mapping of the zero page. */
2646 RTR0PTR pvZeroPgR0;
2647 /** The GC mapping of the zero page. */
2648 RTGCPTR pvZeroPgRC;
2649#if GC_ARCH_BITS != 32
2650 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2651#endif
2652 /** @}*/
2653
2654 /** The number of handy pages. */
2655 uint32_t cHandyPages;
2656 /**
2657 * Array of handy pages.
2658 *
2659 * This array is used in a two way communication between pgmPhysAllocPage
2660 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2661 * an intermediary.
2662 *
2663 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2664 * (The current size of 32 pages, means 128 KB of handy memory.)
2665 */
2666 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2667
2668 /**
2669 * Live save data.
2670 */
2671 struct
2672 {
2673 /** The number of ready pages. */
2674 uint32_t cReadyPages;
2675 /** The number of dirty pages. */
2676 uint32_t cDirtyPages;
2677 /** The number of monitored pages. */
2678 uint32_t cMonitoredPages;
2679 /** The number of ignored pages. */
2680 uint32_t cIgnoredPages;
2681 /** The number of MMIO2 pages. */
2682 uint32_t cMmio2Pages;
2683 /** Indicates that a live save operation is active. */
2684 bool fActive;
2685 /** Padding. */
2686 bool afReserved[3];
2687 } LiveSave;
2688
2689 /** @name Error injection.
2690 * @{ */
2691 /** Inject handy page allocation errors pretending we're completely out of
2692 * memory. */
2693 bool volatile fErrInjHandyPages;
2694 /** Padding. */
2695 bool afReserved[7];
2696 /** @} */
2697
2698 /** @name Release Statistics
2699 * @{ */
2700 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2701 uint32_t cPrivatePages; /**< The number of private pages. */
2702 uint32_t cSharedPages; /**< The number of shared pages. */
2703 uint32_t cZeroPages; /**< The number of zero backed pages. */
2704 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2705 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2706 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2707 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2708
2709 /** The number of times we were forced to change the hypervisor region location. */
2710 STAMCOUNTER cRelocations;
2711 /** @} */
2712
2713#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2714 /* R3 only: */
2715 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2716 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2717
2718 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2719 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2720 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2721 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2722 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2723 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2724 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2725 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2726 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2727 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2728 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2729 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2730 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2731 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2732 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2733 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2734 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2735 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2736/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2737 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2738 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2739/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2740
2741 /* RC only: */
2742 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2743 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2744 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2745 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2746
2747 STAMCOUNTER StatRZPhysRead;
2748 STAMCOUNTER StatRZPhysReadBytes;
2749 STAMCOUNTER StatRZPhysWrite;
2750 STAMCOUNTER StatRZPhysWriteBytes;
2751 STAMCOUNTER StatR3PhysRead;
2752 STAMCOUNTER StatR3PhysReadBytes;
2753 STAMCOUNTER StatR3PhysWrite;
2754 STAMCOUNTER StatR3PhysWriteBytes;
2755 STAMCOUNTER StatRCPhysRead;
2756 STAMCOUNTER StatRCPhysReadBytes;
2757 STAMCOUNTER StatRCPhysWrite;
2758 STAMCOUNTER StatRCPhysWriteBytes;
2759
2760 STAMCOUNTER StatRZPhysSimpleRead;
2761 STAMCOUNTER StatRZPhysSimpleReadBytes;
2762 STAMCOUNTER StatRZPhysSimpleWrite;
2763 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2764 STAMCOUNTER StatR3PhysSimpleRead;
2765 STAMCOUNTER StatR3PhysSimpleReadBytes;
2766 STAMCOUNTER StatR3PhysSimpleWrite;
2767 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2768 STAMCOUNTER StatRCPhysSimpleRead;
2769 STAMCOUNTER StatRCPhysSimpleReadBytes;
2770 STAMCOUNTER StatRCPhysSimpleWrite;
2771 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2772
2773# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2774 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2775 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2776 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2777 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2778 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2779 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2780# endif
2781#endif
2782} PGM;
2783#ifndef IN_TSTVMSTRUCTGC /* HACK */
2784AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2785AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2786AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2787AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2788AssertCompileMemberAlignment(PGM, CritSect, 8);
2789AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2790AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2791AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2792AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2793AssertCompileMemberAlignment(PGM, cRelocations, 8);
2794#endif /* !IN_TSTVMSTRUCTGC */
2795/** Pointer to the PGM instance data. */
2796typedef PGM *PPGM;
2797
2798
2799/**
2800 * Converts a PGMCPU pointer into a VM pointer.
2801 * @returns Pointer to the VM structure the PGM is part of.
2802 * @param pPGM Pointer to PGMCPU instance data.
2803 */
2804#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2805
2806/**
2807 * Converts a PGMCPU pointer into a PGM pointer.
2808 * @returns Pointer to the VM structure the PGM is part of.
2809 * @param pPGM Pointer to PGMCPU instance data.
2810 */
2811#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2812
2813/**
2814 * PGMCPU Data (part of VMCPU).
2815 */
2816typedef struct PGMCPU
2817{
2818 /** Offset to the VM structure. */
2819 RTINT offVM;
2820 /** Offset to the VMCPU structure. */
2821 RTINT offVCpu;
2822 /** Offset of the PGM structure relative to VMCPU. */
2823 RTINT offPGM;
2824 RTINT uPadding0; /**< structure size alignment. */
2825
2826#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2827 /** Automatically tracked physical memory mapping set.
2828 * Ring-0 and strict raw-mode builds. */
2829 PGMMAPSET AutoSet;
2830#endif
2831
2832 /** A20 gate mask.
2833 * Our current approach to A20 emulation is to let REM do it and don't bother
2834 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2835 * But whould need arrise, we'll subject physical addresses to this mask. */
2836 RTGCPHYS GCPhysA20Mask;
2837 /** A20 gate state - boolean! */
2838 bool fA20Enabled;
2839
2840 /** What needs syncing (PGM_SYNC_*).
2841 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2842 * PGMFlushTLB, and PGMR3Load. */
2843 RTUINT fSyncFlags;
2844
2845 /** The shadow paging mode. */
2846 PGMMODE enmShadowMode;
2847 /** The guest paging mode. */
2848 PGMMODE enmGuestMode;
2849
2850 /** The current physical address representing in the guest CR3 register. */
2851 RTGCPHYS GCPhysCR3;
2852
2853 /** @name 32-bit Guest Paging.
2854 * @{ */
2855 /** The guest's page directory, R3 pointer. */
2856 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2857#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2858 /** The guest's page directory, R0 pointer. */
2859 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2860#endif
2861 /** The guest's page directory, static RC mapping. */
2862 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2863 /** @} */
2864
2865 /** @name PAE Guest Paging.
2866 * @{ */
2867 /** The guest's page directory pointer table, static RC mapping. */
2868 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2869 /** The guest's page directory pointer table, R3 pointer. */
2870 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2871#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2872 /** The guest's page directory pointer table, R0 pointer. */
2873 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2874#endif
2875
2876 /** The guest's page directories, R3 pointers.
2877 * These are individual pointers and don't have to be adjecent.
2878 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2879 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2880 /** The guest's page directories, R0 pointers.
2881 * Same restrictions as apGstPaePDsR3. */
2882#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2883 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2884#endif
2885 /** The guest's page directories, static GC mapping.
2886 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2887 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2888 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2889 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2890 RTGCPHYS aGCPhysGstPaePDs[4];
2891 /** The physical addresses of the monitored guest page directories (PAE). */
2892 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2893 /** @} */
2894
2895 /** @name AMD64 Guest Paging.
2896 * @{ */
2897 /** The guest's page directory pointer table, R3 pointer. */
2898 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2899#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2900 /** The guest's page directory pointer table, R0 pointer. */
2901 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2902#endif
2903 /** @} */
2904
2905 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2906 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2907 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2908 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2909 /** Pointer to the page of the current active CR3 - RC Ptr. */
2910 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2911 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2912 uint32_t iShwUser;
2913 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2914 uint32_t iShwUserTable;
2915# if HC_ARCH_BITS == 64
2916 RTRCPTR alignment6; /**< structure size alignment. */
2917# endif
2918 /** @} */
2919
2920 /** @name Function pointers for Shadow paging.
2921 * @{
2922 */
2923 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2924 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2925 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2926 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2927
2928 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2929 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2930
2931 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2932 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2933
2934 /** @} */
2935
2936 /** @name Function pointers for Guest paging.
2937 * @{
2938 */
2939 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2940 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2941 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2942 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2943 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2944 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2945 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2946 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2947#if HC_ARCH_BITS == 64
2948 RTRCPTR alignment3; /**< structure size alignment. */
2949#endif
2950
2951 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2952 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2953 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2954 /** @} */
2955
2956 /** @name Function pointers for Both Shadow and Guest paging.
2957 * @{
2958 */
2959 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2960 /* no pfnR3BthTrap0eHandler */
2961 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2962 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2963 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2964 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2965 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2966 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2967 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2968 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2969
2970 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2971 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2972 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2973 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2974 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2975 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2976 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2977 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2978 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2979
2980 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2981 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2982 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2983 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2984 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2985 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2986 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2987 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2988 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2989 RTRCPTR alignment2; /**< structure size alignment. */
2990 /** @} */
2991
2992 /** For saving stack space, the disassembler state is allocated here instead of
2993 * on the stack.
2994 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2995 union
2996 {
2997 /** The disassembler scratch space. */
2998 DISCPUSTATE DisState;
2999 /** Padding. */
3000 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3001 };
3002
3003 /* Count the number of pgm pool access handler calls. */
3004 uint64_t cPoolAccessHandler;
3005
3006 /** @name Release Statistics
3007 * @{ */
3008 /** The number of times the guest has switched mode since last reset or statistics reset. */
3009 STAMCOUNTER cGuestModeChanges;
3010 /** @} */
3011
3012#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3013 /** @name Statistics
3014 * @{ */
3015 /** RC: Which statistic this \#PF should be attributed to. */
3016 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3017 RTRCPTR padding0;
3018 /** R0: Which statistic this \#PF should be attributed to. */
3019 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3020 RTR0PTR padding1;
3021
3022 /* Common */
3023 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3024 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3025
3026 /* R0 only: */
3027 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3028 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3029 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3030 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3031 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3032 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3033 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3034 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3035 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3036 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3037 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3038 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3039 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3040 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3041 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3042 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3043 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3044 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3045 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3046 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3047 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3048 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3049 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3050 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3051 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3052 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3053
3054 /* RZ only: */
3055 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3056 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3057 STAMPROFILE StatRZTrap0eTimeSyncPT;
3058 STAMPROFILE StatRZTrap0eTimeMapping;
3059 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3060 STAMPROFILE StatRZTrap0eTimeHandlers;
3061 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3062 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3063 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3064 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3065 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3066 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3067 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3068 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3069 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3070 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3071 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3072 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3073 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3074 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3075 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3076 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3077 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3078 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3079 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3080 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3081 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3082 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
3083 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
3084 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
3085 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
3086 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
3087 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
3088 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
3089 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
3090 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
3091 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
3092 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
3093 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
3094 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
3095 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
3096 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3097 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3098 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
3099 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3100 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3101 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3102 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3103 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3104
3105 /* HC - R3 and (maybe) R0: */
3106
3107 /* RZ & R3: */
3108 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3109 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3110 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3111 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3112 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3113 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3114 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3115 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3116 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3117 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3118 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3119 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3120 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3121 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3122 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3123 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3124 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3125 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3126 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3127 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3128 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3129 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3130 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3131 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3132 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3133 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3134 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3135 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3136 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3137 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3138 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3139 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3140 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3141 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3142 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3143 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3144 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3145 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in #PF. */
3146 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF. */
3147 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3148 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3149 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3150 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3151 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3152 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3153 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3154
3155 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3156 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3157 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3158 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3159 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3160 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3161 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3162 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3163 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3164 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3165 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3166 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3167 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3168 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3169 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3170 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3171 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3172 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3173 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3174 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3175 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3176 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3177 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3178 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3179 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3180 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3181 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3182 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3183 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3184 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3185 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3186 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3187 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3188 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3189 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
3190 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
3191 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in #PF. */
3192 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in #PF. */
3193 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3194 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3195 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3196 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3197 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3198 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3199 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3200 /** @} */
3201#endif /* VBOX_WITH_STATISTICS */
3202} PGMCPU;
3203/** Pointer to the per-cpu PGM data. */
3204typedef PGMCPU *PPGMCPU;
3205
3206
3207/** @name PGM::fSyncFlags Flags
3208 * @{
3209 */
3210/** Updates the virtual access handler state bit in PGMPAGE. */
3211#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3212/** Always sync CR3. */
3213#define PGM_SYNC_ALWAYS RT_BIT(1)
3214/** Check monitoring on next CR3 (re)load and invalidate page.
3215 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3216#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3217/** Check guest mapping in SyncCR3. */
3218#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3219/** Clear the page pool (a light weight flush). */
3220#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3221#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3222/** @} */
3223
3224
3225RT_C_DECLS_BEGIN
3226
3227int pgmLock(PVM pVM);
3228void pgmUnlock(PVM pVM);
3229
3230int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3231int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3232PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3233void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3234DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3235
3236void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3237bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3238void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3239int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3240DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3241#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3242void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3243#else
3244# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3245#endif
3246DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3247int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3248
3249int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3250int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3251int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3252int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3253int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3254int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3255int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3256int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3257int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3258int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3259int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3260VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3261#ifdef IN_RING3
3262void pgmR3PhysRelinkRamRanges(PVM pVM);
3263int pgmR3PhysRamPreAllocate(PVM pVM);
3264int pgmR3PhysRamReset(PVM pVM);
3265int pgmR3PhysRomReset(PVM pVM);
3266int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3267
3268int pgmR3PoolInit(PVM pVM);
3269void pgmR3PoolRelocate(PVM pVM);
3270void pgmR3PoolReset(PVM pVM);
3271void pgmR3PoolClearAll(PVM pVM);
3272
3273#endif /* IN_RING3 */
3274#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3275int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3276#endif
3277int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3278
3279DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3280{
3281 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3282}
3283
3284void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3285void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3286int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3287void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3288PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3289int pgmPoolSyncCR3(PVMCPU pVCpu);
3290bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3291int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3292DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3293{
3294 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3295}
3296
3297uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3298void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3299void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3300#ifdef PGMPOOL_WITH_MONITORING
3301void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3302int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3303void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3304#endif
3305
3306void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3307void pgmPoolResetDirtyPages(PVM pVM);
3308
3309int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3310int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3311
3312void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3313void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3314int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3315int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3316
3317int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3318#ifndef IN_RC
3319int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3320#endif
3321int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3322
3323PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3324PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3325PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3326PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3327
3328RT_C_DECLS_END
3329
3330
3331/**
3332 * Gets the PGMRAMRANGE structure for a guest page.
3333 *
3334 * @returns Pointer to the RAM range on success.
3335 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3336 *
3337 * @param pPGM PGM handle.
3338 * @param GCPhys The GC physical address.
3339 */
3340DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3341{
3342 /*
3343 * Optimize for the first range.
3344 */
3345 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3346 RTGCPHYS off = GCPhys - pRam->GCPhys;
3347 if (RT_UNLIKELY(off >= pRam->cb))
3348 {
3349 do
3350 {
3351 pRam = pRam->CTX_SUFF(pNext);
3352 if (RT_UNLIKELY(!pRam))
3353 break;
3354 off = GCPhys - pRam->GCPhys;
3355 } while (off >= pRam->cb);
3356 }
3357 return pRam;
3358}
3359
3360
3361/**
3362 * Gets the PGMPAGE structure for a guest page.
3363 *
3364 * @returns Pointer to the page on success.
3365 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3366 *
3367 * @param pPGM PGM handle.
3368 * @param GCPhys The GC physical address.
3369 */
3370DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3371{
3372 /*
3373 * Optimize for the first range.
3374 */
3375 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3376 RTGCPHYS off = GCPhys - pRam->GCPhys;
3377 if (RT_UNLIKELY(off >= pRam->cb))
3378 {
3379 do
3380 {
3381 pRam = pRam->CTX_SUFF(pNext);
3382 if (RT_UNLIKELY(!pRam))
3383 return NULL;
3384 off = GCPhys - pRam->GCPhys;
3385 } while (off >= pRam->cb);
3386 }
3387 return &pRam->aPages[off >> PAGE_SHIFT];
3388}
3389
3390
3391/**
3392 * Gets the PGMPAGE structure for a guest page.
3393 *
3394 * Old Phys code: Will make sure the page is present.
3395 *
3396 * @returns VBox status code.
3397 * @retval VINF_SUCCESS and a valid *ppPage on success.
3398 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3399 *
3400 * @param pPGM PGM handle.
3401 * @param GCPhys The GC physical address.
3402 * @param ppPage Where to store the page pointer on success.
3403 */
3404DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3405{
3406 /*
3407 * Optimize for the first range.
3408 */
3409 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3410 RTGCPHYS off = GCPhys - pRam->GCPhys;
3411 if (RT_UNLIKELY(off >= pRam->cb))
3412 {
3413 do
3414 {
3415 pRam = pRam->CTX_SUFF(pNext);
3416 if (RT_UNLIKELY(!pRam))
3417 {
3418 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3419 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3420 }
3421 off = GCPhys - pRam->GCPhys;
3422 } while (off >= pRam->cb);
3423 }
3424 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3425 return VINF_SUCCESS;
3426}
3427
3428
3429
3430
3431/**
3432 * Gets the PGMPAGE structure for a guest page.
3433 *
3434 * Old Phys code: Will make sure the page is present.
3435 *
3436 * @returns VBox status code.
3437 * @retval VINF_SUCCESS and a valid *ppPage on success.
3438 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3439 *
3440 * @param pPGM PGM handle.
3441 * @param GCPhys The GC physical address.
3442 * @param ppPage Where to store the page pointer on success.
3443 * @param ppRamHint Where to read and store the ram list hint.
3444 * The caller initializes this to NULL before the call.
3445 */
3446DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3447{
3448 RTGCPHYS off;
3449 PPGMRAMRANGE pRam = *ppRamHint;
3450 if ( !pRam
3451 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3452 {
3453 pRam = pPGM->CTX_SUFF(pRamRanges);
3454 off = GCPhys - pRam->GCPhys;
3455 if (RT_UNLIKELY(off >= pRam->cb))
3456 {
3457 do
3458 {
3459 pRam = pRam->CTX_SUFF(pNext);
3460 if (RT_UNLIKELY(!pRam))
3461 {
3462 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3463 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3464 }
3465 off = GCPhys - pRam->GCPhys;
3466 } while (off >= pRam->cb);
3467 }
3468 *ppRamHint = pRam;
3469 }
3470 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3471 return VINF_SUCCESS;
3472}
3473
3474
3475/**
3476 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3477 *
3478 * @returns Pointer to the page on success.
3479 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3480 *
3481 * @param pPGM PGM handle.
3482 * @param GCPhys The GC physical address.
3483 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3484 */
3485DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3486{
3487 /*
3488 * Optimize for the first range.
3489 */
3490 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3491 RTGCPHYS off = GCPhys - pRam->GCPhys;
3492 if (RT_UNLIKELY(off >= pRam->cb))
3493 {
3494 do
3495 {
3496 pRam = pRam->CTX_SUFF(pNext);
3497 if (RT_UNLIKELY(!pRam))
3498 return NULL;
3499 off = GCPhys - pRam->GCPhys;
3500 } while (off >= pRam->cb);
3501 }
3502 *ppRam = pRam;
3503 return &pRam->aPages[off >> PAGE_SHIFT];
3504}
3505
3506
3507/**
3508 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3509 *
3510 * @returns Pointer to the page on success.
3511 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3512 *
3513 * @param pPGM PGM handle.
3514 * @param GCPhys The GC physical address.
3515 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3516 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3517 */
3518DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3519{
3520 /*
3521 * Optimize for the first range.
3522 */
3523 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3524 RTGCPHYS off = GCPhys - pRam->GCPhys;
3525 if (RT_UNLIKELY(off >= pRam->cb))
3526 {
3527 do
3528 {
3529 pRam = pRam->CTX_SUFF(pNext);
3530 if (RT_UNLIKELY(!pRam))
3531 {
3532 *ppRam = NULL; /* Shut up silly GCC warnings. */
3533 *ppPage = NULL; /* ditto */
3534 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3535 }
3536 off = GCPhys - pRam->GCPhys;
3537 } while (off >= pRam->cb);
3538 }
3539 *ppRam = pRam;
3540 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3541 return VINF_SUCCESS;
3542}
3543
3544
3545/**
3546 * Convert GC Phys to HC Phys.
3547 *
3548 * @returns VBox status.
3549 * @param pPGM PGM handle.
3550 * @param GCPhys The GC physical address.
3551 * @param pHCPhys Where to store the corresponding HC physical address.
3552 *
3553 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3554 * Avoid when writing new code!
3555 */
3556DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3557{
3558 PPGMPAGE pPage;
3559 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3560 if (RT_FAILURE(rc))
3561 return rc;
3562 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3563 return VINF_SUCCESS;
3564}
3565
3566#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3567
3568/**
3569 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3570 * optimizes access to pages already in the set.
3571 *
3572 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3573 * @param pPGM Pointer to the PVM instance data.
3574 * @param HCPhys The physical address of the page.
3575 * @param ppv Where to store the mapping address.
3576 */
3577DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3578{
3579 PVM pVM = PGM2VM(pPGM);
3580 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3581 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3582
3583 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3584 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3585 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3586
3587 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3588 unsigned iEntry = pSet->aiHashTable[iHash];
3589 if ( iEntry < pSet->cEntries
3590 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3591 {
3592 *ppv = pSet->aEntries[iEntry].pvPage;
3593 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3594 }
3595 else
3596 {
3597 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3598 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3599 }
3600
3601 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3602 return VINF_SUCCESS;
3603}
3604
3605
3606/**
3607 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3608 * access to pages already in the set.
3609 *
3610 * @returns See PGMDynMapGCPage.
3611 * @param pPGM Pointer to the PVM instance data.
3612 * @param HCPhys The physical address of the page.
3613 * @param ppv Where to store the mapping address.
3614 */
3615DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3616{
3617 PVM pVM = PGM2VM(pPGM);
3618 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3619
3620 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3621 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3622
3623 /*
3624 * Get the ram range.
3625 */
3626 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3627 RTGCPHYS off = GCPhys - pRam->GCPhys;
3628 if (RT_UNLIKELY(off >= pRam->cb
3629 /** @todo || page state stuff */))
3630 {
3631 /* This case is not counted into StatR0DynMapGCPageInl. */
3632 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3633 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3634 }
3635
3636 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3637 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3638
3639 /*
3640 * pgmR0DynMapHCPageInlined with out stats.
3641 */
3642 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3643 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3644 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3645
3646 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3647 unsigned iEntry = pSet->aiHashTable[iHash];
3648 if ( iEntry < pSet->cEntries
3649 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3650 {
3651 *ppv = pSet->aEntries[iEntry].pvPage;
3652 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3653 }
3654 else
3655 {
3656 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3657 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3658 }
3659
3660 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3661 return VINF_SUCCESS;
3662}
3663
3664
3665/**
3666 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3667 * access to pages already in the set.
3668 *
3669 * @returns See PGMDynMapGCPage.
3670 * @param pPGM Pointer to the PVM instance data.
3671 * @param HCPhys The physical address of the page.
3672 * @param ppv Where to store the mapping address.
3673 */
3674DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3675{
3676 PVM pVM = PGM2VM(pPGM);
3677 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3678
3679 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3680
3681 /*
3682 * Get the ram range.
3683 */
3684 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3685 RTGCPHYS off = GCPhys - pRam->GCPhys;
3686 if (RT_UNLIKELY(off >= pRam->cb
3687 /** @todo || page state stuff */))
3688 {
3689 /* This case is not counted into StatR0DynMapGCPageInl. */
3690 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3691 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3692 }
3693
3694 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3695 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3696
3697 /*
3698 * pgmR0DynMapHCPageInlined with out stats.
3699 */
3700 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3701 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3702 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3703
3704 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3705 unsigned iEntry = pSet->aiHashTable[iHash];
3706 if ( iEntry < pSet->cEntries
3707 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3708 {
3709 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3710 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3711 }
3712 else
3713 {
3714 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3715 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3716 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3717 }
3718
3719 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3720 return VINF_SUCCESS;
3721}
3722
3723#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3724#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3725
3726/**
3727 * Maps the page into current context (RC and maybe R0).
3728 *
3729 * @returns pointer to the mapping.
3730 * @param pVM Pointer to the PGM instance data.
3731 * @param pPage The page.
3732 */
3733DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3734{
3735 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3736 {
3737 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3738 void *pv;
3739# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3740 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3741# else
3742 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3743# endif
3744 return pv;
3745 }
3746 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3747}
3748
3749/**
3750 * Temporarily maps one host page specified by HC physical address, returning
3751 * pointer within the page.
3752 *
3753 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3754 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3755 *
3756 * @returns The address corresponding to HCPhys.
3757 * @param pPGM Pointer to the PVM instance data.
3758 * @param HCPhys HC Physical address of the page.
3759 */
3760DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3761{
3762 void *pv;
3763# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3764 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3765# else
3766 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3767# endif
3768 pv = (void *)((uintptr_t)pv | ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3769 return pv;
3770}
3771
3772#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3773#ifndef IN_RC
3774
3775/**
3776 * Queries the Physical TLB entry for a physical guest page,
3777 * attempting to load the TLB entry if necessary.
3778 *
3779 * @returns VBox status code.
3780 * @retval VINF_SUCCESS on success
3781 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3782 *
3783 * @param pPGM The PGM instance handle.
3784 * @param GCPhys The address of the guest page.
3785 * @param ppTlbe Where to store the pointer to the TLB entry.
3786 */
3787DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3788{
3789 int rc;
3790 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3791 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3792 {
3793 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3794 rc = VINF_SUCCESS;
3795 }
3796 else
3797 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3798 *ppTlbe = pTlbe;
3799 return rc;
3800}
3801
3802
3803/**
3804 * Queries the Physical TLB entry for a physical guest page,
3805 * attempting to load the TLB entry if necessary.
3806 *
3807 * @returns VBox status code.
3808 * @retval VINF_SUCCESS on success
3809 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3810 *
3811 * @param pPGM The PGM instance handle.
3812 * @param pPage Pointer to the PGMPAGE structure corresponding to
3813 * GCPhys.
3814 * @param GCPhys The address of the guest page.
3815 * @param ppTlbe Where to store the pointer to the TLB entry.
3816 */
3817DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3818{
3819 int rc;
3820 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3821 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3822 {
3823 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3824 rc = VINF_SUCCESS;
3825 }
3826 else
3827 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3828 *ppTlbe = pTlbe;
3829 return rc;
3830}
3831
3832#endif /* !IN_RC */
3833
3834/**
3835 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3836 * Takes PSE-36 into account.
3837 *
3838 * @returns guest physical address
3839 * @param pPGM Pointer to the PGM instance data.
3840 * @param Pde Guest Pde
3841 */
3842DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3843{
3844 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3845 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3846
3847 return GCPhys & pPGM->GCPhys4MBPSEMask;
3848}
3849
3850
3851/**
3852 * Gets the page directory entry for the specified address (32-bit paging).
3853 *
3854 * @returns The page directory entry in question.
3855 * @param pPGM Pointer to the PGM instance data.
3856 * @param GCPtr The address.
3857 */
3858DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3859{
3860#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3861 PCX86PD pGuestPD = NULL;
3862 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3863 if (RT_FAILURE(rc))
3864 {
3865 X86PDE ZeroPde = {0};
3866 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3867 }
3868#else
3869 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3870# ifdef IN_RING3
3871 if (!pGuestPD)
3872 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3873# endif
3874#endif
3875 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3876}
3877
3878
3879/**
3880 * Gets the address of a specific page directory entry (32-bit paging).
3881 *
3882 * @returns Pointer the page directory entry in question.
3883 * @param pPGM Pointer to the PGM instance data.
3884 * @param GCPtr The address.
3885 */
3886DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3887{
3888#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3889 PX86PD pGuestPD = NULL;
3890 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3891 AssertRCReturn(rc, NULL);
3892#else
3893 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3894# ifdef IN_RING3
3895 if (!pGuestPD)
3896 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3897# endif
3898#endif
3899 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3900}
3901
3902
3903/**
3904 * Gets the address the guest page directory (32-bit paging).
3905 *
3906 * @returns Pointer the page directory entry in question.
3907 * @param pPGM Pointer to the PGM instance data.
3908 */
3909DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3910{
3911#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3912 PX86PD pGuestPD = NULL;
3913 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3914 AssertRCReturn(rc, NULL);
3915#else
3916 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3917# ifdef IN_RING3
3918 if (!pGuestPD)
3919 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3920# endif
3921#endif
3922 return pGuestPD;
3923}
3924
3925
3926/**
3927 * Gets the guest page directory pointer table.
3928 *
3929 * @returns Pointer to the page directory in question.
3930 * @returns NULL if the page directory is not present or on an invalid page.
3931 * @param pPGM Pointer to the PGM instance data.
3932 */
3933DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3934{
3935#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3936 PX86PDPT pGuestPDPT = NULL;
3937 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3938 AssertRCReturn(rc, NULL);
3939#else
3940 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3941# ifdef IN_RING3
3942 if (!pGuestPDPT)
3943 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3944# endif
3945#endif
3946 return pGuestPDPT;
3947}
3948
3949
3950/**
3951 * Gets the guest page directory pointer table entry for the specified address.
3952 *
3953 * @returns Pointer to the page directory in question.
3954 * @returns NULL if the page directory is not present or on an invalid page.
3955 * @param pPGM Pointer to the PGM instance data.
3956 * @param GCPtr The address.
3957 */
3958DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3959{
3960 AssertGCPtr32(GCPtr);
3961
3962#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3963 PX86PDPT pGuestPDPT = 0;
3964 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3965 AssertRCReturn(rc, 0);
3966#else
3967 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3968# ifdef IN_RING3
3969 if (!pGuestPDPT)
3970 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3971# endif
3972#endif
3973 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3974}
3975
3976
3977/**
3978 * Gets the page directory for the specified address.
3979 *
3980 * @returns Pointer to the page directory in question.
3981 * @returns NULL if the page directory is not present or on an invalid page.
3982 * @param pPGM Pointer to the PGM instance data.
3983 * @param GCPtr The address.
3984 */
3985DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3986{
3987 AssertGCPtr32(GCPtr);
3988
3989 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3990 AssertReturn(pGuestPDPT, NULL);
3991 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3992 if (pGuestPDPT->a[iPdpt].n.u1Present)
3993 {
3994#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3995 PX86PDPAE pGuestPD = NULL;
3996 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3997 AssertRCReturn(rc, NULL);
3998#else
3999 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4000 if ( !pGuestPD
4001 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4002 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4003#endif
4004 return pGuestPD;
4005 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
4006 }
4007 return NULL;
4008}
4009
4010
4011/**
4012 * Gets the page directory entry for the specified address.
4013 *
4014 * @returns Pointer to the page directory entry in question.
4015 * @returns NULL if the page directory is not present or on an invalid page.
4016 * @param pPGM Pointer to the PGM instance data.
4017 * @param GCPtr The address.
4018 */
4019DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4020{
4021 AssertGCPtr32(GCPtr);
4022
4023 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4024 AssertReturn(pGuestPDPT, NULL);
4025 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4026 if (pGuestPDPT->a[iPdpt].n.u1Present)
4027 {
4028 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4029#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4030 PX86PDPAE pGuestPD = NULL;
4031 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4032 AssertRCReturn(rc, NULL);
4033#else
4034 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4035 if ( !pGuestPD
4036 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4037 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4038#endif
4039 return &pGuestPD->a[iPD];
4040 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
4041 }
4042 return NULL;
4043}
4044
4045
4046/**
4047 * Gets the page directory entry for the specified address.
4048 *
4049 * @returns The page directory entry in question.
4050 * @returns A non-present entry if the page directory is not present or on an invalid page.
4051 * @param pPGM Pointer to the PGM instance data.
4052 * @param GCPtr The address.
4053 */
4054DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4055{
4056 AssertGCPtr32(GCPtr);
4057 X86PDEPAE ZeroPde = {0};
4058 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4059 if (RT_LIKELY(pGuestPDPT))
4060 {
4061 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4062 if (pGuestPDPT->a[iPdpt].n.u1Present)
4063 {
4064 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4065#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4066 PX86PDPAE pGuestPD = NULL;
4067 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4068 AssertRCReturn(rc, ZeroPde);
4069#else
4070 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4071 if ( !pGuestPD
4072 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4073 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4074#endif
4075 return pGuestPD->a[iPD];
4076 }
4077 }
4078 return ZeroPde;
4079}
4080
4081
4082/**
4083 * Gets the page directory pointer table entry for the specified address
4084 * and returns the index into the page directory
4085 *
4086 * @returns Pointer to the page directory in question.
4087 * @returns NULL if the page directory is not present or on an invalid page.
4088 * @param pPGM Pointer to the PGM instance data.
4089 * @param GCPtr The address.
4090 * @param piPD Receives the index into the returned page directory
4091 * @param pPdpe Receives the page directory pointer entry. Optional.
4092 */
4093DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4094{
4095 AssertGCPtr32(GCPtr);
4096
4097 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4098 AssertReturn(pGuestPDPT, NULL);
4099 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4100 if (pPdpe)
4101 *pPdpe = pGuestPDPT->a[iPdpt];
4102 if (pGuestPDPT->a[iPdpt].n.u1Present)
4103 {
4104 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4105#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4106 PX86PDPAE pGuestPD = NULL;
4107 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4108 AssertRCReturn(rc, NULL);
4109#else
4110 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4111 if ( !pGuestPD
4112 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4113 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4114#endif
4115 *piPD = iPD;
4116 return pGuestPD;
4117 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4118 }
4119 return NULL;
4120}
4121
4122#ifndef IN_RC
4123
4124/**
4125 * Gets the page map level-4 pointer for the guest.
4126 *
4127 * @returns Pointer to the PML4 page.
4128 * @param pPGM Pointer to the PGM instance data.
4129 */
4130DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4131{
4132#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4133 PX86PML4 pGuestPml4;
4134 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4135 AssertRCReturn(rc, NULL);
4136#else
4137 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4138# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4139 if (!pGuestPml4)
4140 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4141# endif
4142 Assert(pGuestPml4);
4143#endif
4144 return pGuestPml4;
4145}
4146
4147
4148/**
4149 * Gets the pointer to a page map level-4 entry.
4150 *
4151 * @returns Pointer to the PML4 entry.
4152 * @param pPGM Pointer to the PGM instance data.
4153 * @param iPml4 The index.
4154 */
4155DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4156{
4157#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4158 PX86PML4 pGuestPml4;
4159 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4160 AssertRCReturn(rc, NULL);
4161#else
4162 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4163# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4164 if (!pGuestPml4)
4165 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4166# endif
4167 Assert(pGuestPml4);
4168#endif
4169 return &pGuestPml4->a[iPml4];
4170}
4171
4172
4173/**
4174 * Gets a page map level-4 entry.
4175 *
4176 * @returns The PML4 entry.
4177 * @param pPGM Pointer to the PGM instance data.
4178 * @param iPml4 The index.
4179 */
4180DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4181{
4182#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4183 PX86PML4 pGuestPml4;
4184 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4185 if (RT_FAILURE(rc))
4186 {
4187 X86PML4E ZeroPml4e = {0};
4188 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4189 }
4190#else
4191 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4192# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4193 if (!pGuestPml4)
4194 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4195# endif
4196 Assert(pGuestPml4);
4197#endif
4198 return pGuestPml4->a[iPml4];
4199}
4200
4201
4202/**
4203 * Gets the page directory pointer entry for the specified address.
4204 *
4205 * @returns Pointer to the page directory pointer entry in question.
4206 * @returns NULL if the page directory is not present or on an invalid page.
4207 * @param pPGM Pointer to the PGM instance data.
4208 * @param GCPtr The address.
4209 * @param ppPml4e Page Map Level-4 Entry (out)
4210 */
4211DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4212{
4213 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4214 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4215 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4216 if (pPml4e->n.u1Present)
4217 {
4218 PX86PDPT pPdpt;
4219 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4220 AssertRCReturn(rc, NULL);
4221
4222 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4223 return &pPdpt->a[iPdpt];
4224 }
4225 return NULL;
4226}
4227
4228
4229/**
4230 * Gets the page directory entry for the specified address.
4231 *
4232 * @returns The page directory entry in question.
4233 * @returns A non-present entry if the page directory is not present or on an invalid page.
4234 * @param pPGM Pointer to the PGM instance data.
4235 * @param GCPtr The address.
4236 * @param ppPml4e Page Map Level-4 Entry (out)
4237 * @param pPdpe Page directory pointer table entry (out)
4238 */
4239DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4240{
4241 X86PDEPAE ZeroPde = {0};
4242 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4243 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4244 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4245 if (pPml4e->n.u1Present)
4246 {
4247 PCX86PDPT pPdptTemp;
4248 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4249 AssertRCReturn(rc, ZeroPde);
4250
4251 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4252 *pPdpe = pPdptTemp->a[iPdpt];
4253 if (pPdptTemp->a[iPdpt].n.u1Present)
4254 {
4255 PCX86PDPAE pPD;
4256 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4257 AssertRCReturn(rc, ZeroPde);
4258
4259 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4260 return pPD->a[iPD];
4261 }
4262 }
4263
4264 return ZeroPde;
4265}
4266
4267
4268/**
4269 * Gets the page directory entry for the specified address.
4270 *
4271 * @returns The page directory entry in question.
4272 * @returns A non-present entry if the page directory is not present or on an invalid page.
4273 * @param pPGM Pointer to the PGM instance data.
4274 * @param GCPtr The address.
4275 */
4276DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4277{
4278 X86PDEPAE ZeroPde = {0};
4279 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4280 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4281 if (pGuestPml4->a[iPml4].n.u1Present)
4282 {
4283 PCX86PDPT pPdptTemp;
4284 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4285 AssertRCReturn(rc, ZeroPde);
4286
4287 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4288 if (pPdptTemp->a[iPdpt].n.u1Present)
4289 {
4290 PCX86PDPAE pPD;
4291 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4292 AssertRCReturn(rc, ZeroPde);
4293
4294 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4295 return pPD->a[iPD];
4296 }
4297 }
4298 return ZeroPde;
4299}
4300
4301
4302/**
4303 * Gets the page directory entry for the specified address.
4304 *
4305 * @returns Pointer to the page directory entry in question.
4306 * @returns NULL if the page directory is not present or on an invalid page.
4307 * @param pPGM Pointer to the PGM instance data.
4308 * @param GCPtr The address.
4309 */
4310DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4311{
4312 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4313 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4314 if (pGuestPml4->a[iPml4].n.u1Present)
4315 {
4316 PCX86PDPT pPdptTemp;
4317 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4318 AssertRCReturn(rc, NULL);
4319
4320 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4321 if (pPdptTemp->a[iPdpt].n.u1Present)
4322 {
4323 PX86PDPAE pPD;
4324 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4325 AssertRCReturn(rc, NULL);
4326
4327 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4328 return &pPD->a[iPD];
4329 }
4330 }
4331 return NULL;
4332}
4333
4334
4335/**
4336 * Gets the GUEST page directory pointer for the specified address.
4337 *
4338 * @returns The page directory in question.
4339 * @returns NULL if the page directory is not present or on an invalid page.
4340 * @param pPGM Pointer to the PGM instance data.
4341 * @param GCPtr The address.
4342 * @param ppPml4e Page Map Level-4 Entry (out)
4343 * @param pPdpe Page directory pointer table entry (out)
4344 * @param piPD Receives the index into the returned page directory
4345 */
4346DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4347{
4348 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4349 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4350 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4351 if (pPml4e->n.u1Present)
4352 {
4353 PCX86PDPT pPdptTemp;
4354 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4355 AssertRCReturn(rc, NULL);
4356
4357 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4358 *pPdpe = pPdptTemp->a[iPdpt];
4359 if (pPdptTemp->a[iPdpt].n.u1Present)
4360 {
4361 PX86PDPAE pPD;
4362 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4363 AssertRCReturn(rc, NULL);
4364
4365 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4366 return pPD;
4367 }
4368 }
4369 return 0;
4370}
4371
4372#endif /* !IN_RC */
4373
4374/**
4375 * Gets the shadow page directory, 32-bit.
4376 *
4377 * @returns Pointer to the shadow 32-bit PD.
4378 * @param pPGM Pointer to the PGM instance data.
4379 */
4380DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4381{
4382 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4383}
4384
4385
4386/**
4387 * Gets the shadow page directory entry for the specified address, 32-bit.
4388 *
4389 * @returns Shadow 32-bit PDE.
4390 * @param pPGM Pointer to the PGM instance data.
4391 * @param GCPtr The address.
4392 */
4393DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4394{
4395 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4396
4397 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4398 if (!pShwPde)
4399 {
4400 X86PDE ZeroPde = {0};
4401 return ZeroPde;
4402 }
4403 return pShwPde->a[iPd];
4404}
4405
4406
4407/**
4408 * Gets the pointer to the shadow page directory entry for the specified
4409 * address, 32-bit.
4410 *
4411 * @returns Pointer to the shadow 32-bit PDE.
4412 * @param pPGM Pointer to the PGM instance data.
4413 * @param GCPtr The address.
4414 */
4415DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4416{
4417 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4418
4419 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4420 AssertReturn(pPde, NULL);
4421 return &pPde->a[iPd];
4422}
4423
4424
4425/**
4426 * Gets the shadow page pointer table, PAE.
4427 *
4428 * @returns Pointer to the shadow PAE PDPT.
4429 * @param pPGM Pointer to the PGM instance data.
4430 */
4431DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4432{
4433 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4434}
4435
4436
4437/**
4438 * Gets the shadow page directory for the specified address, PAE.
4439 *
4440 * @returns Pointer to the shadow PD.
4441 * @param pPGM Pointer to the PGM instance data.
4442 * @param GCPtr The address.
4443 */
4444DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4445{
4446 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4447 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4448
4449 if (!pPdpt->a[iPdpt].n.u1Present)
4450 return NULL;
4451
4452 /* Fetch the pgm pool shadow descriptor. */
4453 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4454 AssertReturn(pShwPde, NULL);
4455
4456 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4457}
4458
4459
4460/**
4461 * Gets the shadow page directory for the specified address, PAE.
4462 *
4463 * @returns Pointer to the shadow PD.
4464 * @param pPGM Pointer to the PGM instance data.
4465 * @param GCPtr The address.
4466 */
4467DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4468{
4469 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4470
4471 if (!pPdpt->a[iPdpt].n.u1Present)
4472 return NULL;
4473
4474 /* Fetch the pgm pool shadow descriptor. */
4475 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4476 AssertReturn(pShwPde, NULL);
4477
4478 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4479}
4480
4481
4482/**
4483 * Gets the shadow page directory entry, PAE.
4484 *
4485 * @returns PDE.
4486 * @param pPGM Pointer to the PGM instance data.
4487 * @param GCPtr The address.
4488 */
4489DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4490{
4491 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4492
4493 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4494 if (!pShwPde)
4495 {
4496 X86PDEPAE ZeroPde = {0};
4497 return ZeroPde;
4498 }
4499 return pShwPde->a[iPd];
4500}
4501
4502
4503/**
4504 * Gets the pointer to the shadow page directory entry for an address, PAE.
4505 *
4506 * @returns Pointer to the PDE.
4507 * @param pPGM Pointer to the PGM instance data.
4508 * @param GCPtr The address.
4509 */
4510DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4511{
4512 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4513
4514 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4515 AssertReturn(pPde, NULL);
4516 return &pPde->a[iPd];
4517}
4518
4519#ifndef IN_RC
4520
4521/**
4522 * Gets the shadow page map level-4 pointer.
4523 *
4524 * @returns Pointer to the shadow PML4.
4525 * @param pPGM Pointer to the PGM instance data.
4526 */
4527DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4528{
4529 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4530}
4531
4532
4533/**
4534 * Gets the shadow page map level-4 entry for the specified address.
4535 *
4536 * @returns The entry.
4537 * @param pPGM Pointer to the PGM instance data.
4538 * @param GCPtr The address.
4539 */
4540DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4541{
4542 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4543 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4544
4545 if (!pShwPml4)
4546 {
4547 X86PML4E ZeroPml4e = {0};
4548 return ZeroPml4e;
4549 }
4550 return pShwPml4->a[iPml4];
4551}
4552
4553
4554/**
4555 * Gets the pointer to the specified shadow page map level-4 entry.
4556 *
4557 * @returns The entry.
4558 * @param pPGM Pointer to the PGM instance data.
4559 * @param iPml4 The PML4 index.
4560 */
4561DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4562{
4563 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4564 if (!pShwPml4)
4565 return NULL;
4566 return &pShwPml4->a[iPml4];
4567}
4568
4569
4570/**
4571 * Gets the GUEST page directory pointer for the specified address.
4572 *
4573 * @returns The page directory in question.
4574 * @returns NULL if the page directory is not present or on an invalid page.
4575 * @param pPGM Pointer to the PGM instance data.
4576 * @param GCPtr The address.
4577 * @param piPD Receives the index into the returned page directory
4578 */
4579DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4580{
4581 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4582 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4583 if (pGuestPml4->a[iPml4].n.u1Present)
4584 {
4585 PCX86PDPT pPdptTemp;
4586 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4587 AssertRCReturn(rc, NULL);
4588
4589 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4590 if (pPdptTemp->a[iPdpt].n.u1Present)
4591 {
4592 PX86PDPAE pPD;
4593 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4594 AssertRCReturn(rc, NULL);
4595
4596 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4597 return pPD;
4598 }
4599 }
4600 return NULL;
4601}
4602
4603#endif /* !IN_RC */
4604
4605/**
4606 * Gets the page state for a physical handler.
4607 *
4608 * @returns The physical handler page state.
4609 * @param pCur The physical handler in question.
4610 */
4611DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4612{
4613 switch (pCur->enmType)
4614 {
4615 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4616 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4617
4618 case PGMPHYSHANDLERTYPE_MMIO:
4619 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4620 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4621
4622 default:
4623 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4624 }
4625}
4626
4627
4628/**
4629 * Gets the page state for a virtual handler.
4630 *
4631 * @returns The virtual handler page state.
4632 * @param pCur The virtual handler in question.
4633 * @remarks This should never be used on a hypervisor access handler.
4634 */
4635DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4636{
4637 switch (pCur->enmType)
4638 {
4639 case PGMVIRTHANDLERTYPE_WRITE:
4640 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4641 case PGMVIRTHANDLERTYPE_ALL:
4642 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4643 default:
4644 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4645 }
4646}
4647
4648
4649/**
4650 * Clears one physical page of a virtual handler
4651 *
4652 * @param pPGM Pointer to the PGM instance.
4653 * @param pCur Virtual handler structure
4654 * @param iPage Physical page index
4655 *
4656 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4657 * need to care about other handlers in the same page.
4658 */
4659DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4660{
4661 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4662
4663 /*
4664 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4665 */
4666#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4667 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4668 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4669 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4670#endif
4671 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4672 {
4673 /* We're the head of the alias chain. */
4674 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4675#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4676 AssertReleaseMsg(pRemove != NULL,
4677 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4678 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4679 AssertReleaseMsg(pRemove == pPhys2Virt,
4680 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4681 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4682 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4683 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4684#endif
4685 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4686 {
4687 /* Insert the next list in the alias chain into the tree. */
4688 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4689#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4690 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4691 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4692 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4693#endif
4694 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4695 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4696 AssertRelease(fRc);
4697 }
4698 }
4699 else
4700 {
4701 /* Locate the previous node in the alias chain. */
4702 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4703#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4704 AssertReleaseMsg(pPrev != pPhys2Virt,
4705 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4706 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4707#endif
4708 for (;;)
4709 {
4710 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4711 if (pNext == pPhys2Virt)
4712 {
4713 /* unlink. */
4714 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4715 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4716 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4717 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4718 else
4719 {
4720 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4721 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4722 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4723 }
4724 break;
4725 }
4726
4727 /* next */
4728 if (pNext == pPrev)
4729 {
4730#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4731 AssertReleaseMsg(pNext != pPrev,
4732 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4733 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4734#endif
4735 break;
4736 }
4737 pPrev = pNext;
4738 }
4739 }
4740 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4741 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4742 pPhys2Virt->offNextAlias = 0;
4743 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4744
4745 /*
4746 * Clear the ram flags for this page.
4747 */
4748 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4749 AssertReturnVoid(pPage);
4750 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4751}
4752
4753
4754/**
4755 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4756 *
4757 * @returns Pointer to the shadow page structure.
4758 * @param pPool The pool.
4759 * @param idx The pool page index.
4760 */
4761DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4762{
4763 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4764 return &pPool->aPages[idx];
4765}
4766
4767
4768#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4769/**
4770 * Clear references to guest physical memory.
4771 *
4772 * @param pPool The pool.
4773 * @param pPoolPage The pool page.
4774 * @param pPhysPage The physical guest page tracking structure.
4775 */
4776DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4777{
4778 /*
4779 * Just deal with the simple case here.
4780 */
4781# ifdef LOG_ENABLED
4782 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4783# endif
4784 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4785 if (cRefs == 1)
4786 {
4787 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4788 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4789 }
4790 else
4791 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4792 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4793}
4794#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4795
4796
4797#ifdef PGMPOOL_WITH_CACHE
4798/**
4799 * Moves the page to the head of the age list.
4800 *
4801 * This is done when the cached page is used in one way or another.
4802 *
4803 * @param pPool The pool.
4804 * @param pPage The cached page.
4805 */
4806DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4807{
4808 PVM pVM = pPool->CTX_SUFF(pVM);
4809 pgmLock(pVM);
4810
4811 /*
4812 * Move to the head of the age list.
4813 */
4814 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4815 {
4816 /* unlink */
4817 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4818 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4819 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4820 else
4821 pPool->iAgeTail = pPage->iAgePrev;
4822
4823 /* insert at head */
4824 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4825 pPage->iAgeNext = pPool->iAgeHead;
4826 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4827 pPool->iAgeHead = pPage->idx;
4828 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4829 }
4830 pgmUnlock(pVM);
4831}
4832#endif /* PGMPOOL_WITH_CACHE */
4833
4834/**
4835 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4836 *
4837 * @param pVM VM Handle.
4838 * @param pPage PGM pool page
4839 */
4840DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4841{
4842 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4843 ASMAtomicIncU32(&pPage->cLocked);
4844}
4845
4846
4847/**
4848 * Unlocks a page to allow flushing again
4849 *
4850 * @param pVM VM Handle.
4851 * @param pPage PGM pool page
4852 */
4853DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4854{
4855 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4856 Assert(pPage->cLocked);
4857 ASMAtomicDecU32(&pPage->cLocked);
4858}
4859
4860
4861/**
4862 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4863 *
4864 * @returns VBox status code.
4865 * @param pPage PGM pool page
4866 */
4867DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4868{
4869 if (pPage->cLocked)
4870 {
4871 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4872 if (pPage->cModifications)
4873 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4874 return true;
4875 }
4876 return false;
4877}
4878
4879/**
4880 * Tells if mappings are to be put into the shadow page table or not
4881 *
4882 * @returns boolean result
4883 * @param pVM VM handle.
4884 */
4885DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4886{
4887#ifdef IN_RING0
4888 /* There are no mappings in VT-x and AMD-V mode. */
4889 Assert(pPGM->fDisableMappings);
4890 return false;
4891#else
4892 return !pPGM->fDisableMappings;
4893#endif
4894}
4895
4896/** @} */
4897
4898#endif
4899
4900
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