VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 25816

Last change on this file since 25816 was 25816, checked in by vboxsync, 15 years ago

CPU hotplug: Merge the first patch. Resets a CPU state if a CPU was removed from the VM
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1/* $Id: PGMInternal.h 25816 2010-01-13 21:05:35Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43#include <iprt/sha.h>
44
45
46
47/** @defgroup grp_pgm_int Internals
48 * @ingroup grp_pgm
49 * @internal
50 * @{
51 */
52
53
54/** @name PGM Compile Time Config
55 * @{
56 */
57
58/**
59 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
60 * Comment it if it will break something.
61 */
62#define PGM_OUT_OF_SYNC_IN_GC
63
64/**
65 * Check and skip global PDEs for non-global flushes
66 */
67#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
68
69/**
70 * Optimization for PAE page tables that are modified often
71 */
72//#if 0 /* disabled again while debugging */
73#ifndef IN_RC
74# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
75#endif
76//#endif
77
78/**
79 * Sync N pages instead of a whole page table
80 */
81#define PGM_SYNC_N_PAGES
82
83/**
84 * Number of pages to sync during a page fault
85 *
86 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
87 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
88 *
89 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
90 * world switch overhead, so let's sync more.
91 */
92# ifdef IN_RING0
93/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
94 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
95 * but ~5% fewer faults.
96 */
97# define PGM_SYNC_NR_PAGES 32
98#else
99# define PGM_SYNC_NR_PAGES 8
100#endif
101
102/**
103 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
104 */
105#define PGM_MAX_PHYSCACHE_ENTRIES 64
106#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
107
108
109/** @def PGMPOOL_CFG_MAX_GROW
110 * The maximum number of pages to add to the pool in one go.
111 */
112#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
113
114/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
115 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
116 */
117#ifdef VBOX_STRICT
118# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
119#endif
120
121/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
122 * Enables the experimental lazy page allocation code. */
123/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
124
125/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
126 * Enables real write monitoring of pages, i.e. mapping them read-only and
127 * only making them writable when getting a write access #PF. */
128#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
129
130/** @} */
131
132
133/** @name PDPT and PML4 flags.
134 * These are placed in the three bits available for system programs in
135 * the PDPT and PML4 entries.
136 * @{ */
137/** The entry is a permanent one and it's must always be present.
138 * Never free such an entry. */
139#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
140/** Mapping (hypervisor allocated pagetable). */
141#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
142/** @} */
143
144/** @name Page directory flags.
145 * These are placed in the three bits available for system programs in
146 * the page directory entries.
147 * @{ */
148/** Mapping (hypervisor allocated pagetable). */
149#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
150/** Made read-only to facilitate dirty bit tracking. */
151#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
152/** @} */
153
154/** @name Page flags.
155 * These are placed in the three bits available for system programs in
156 * the page entries.
157 * @{ */
158/** Made read-only to facilitate dirty bit tracking. */
159#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
160
161#ifndef PGM_PTFLAGS_CSAM_VALIDATED
162/** Scanned and approved by CSAM (tm).
163 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
164 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
165#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
166#endif
167
168/** @} */
169
170/** @name Defines used to indicate the shadow and guest paging in the templates.
171 * @{ */
172#define PGM_TYPE_REAL 1
173#define PGM_TYPE_PROT 2
174#define PGM_TYPE_32BIT 3
175#define PGM_TYPE_PAE 4
176#define PGM_TYPE_AMD64 5
177#define PGM_TYPE_NESTED 6
178#define PGM_TYPE_EPT 7
179#define PGM_TYPE_MAX PGM_TYPE_EPT
180/** @} */
181
182/** Macro for checking if the guest is using paging.
183 * @param uGstType PGM_TYPE_*
184 * @param uShwType PGM_TYPE_*
185 * @remark ASSUMES certain order of the PGM_TYPE_* values.
186 */
187#define PGM_WITH_PAGING(uGstType, uShwType) \
188 ( (uGstType) >= PGM_TYPE_32BIT \
189 && (uShwType) != PGM_TYPE_NESTED \
190 && (uShwType) != PGM_TYPE_EPT)
191
192/** Macro for checking if the guest supports the NX bit.
193 * @param uGstType PGM_TYPE_*
194 * @param uShwType PGM_TYPE_*
195 * @remark ASSUMES certain order of the PGM_TYPE_* values.
196 */
197#define PGM_WITH_NX(uGstType, uShwType) \
198 ( (uGstType) >= PGM_TYPE_PAE \
199 && (uShwType) != PGM_TYPE_NESTED \
200 && (uShwType) != PGM_TYPE_EPT)
201
202
203/** @def PGM_HCPHYS_2_PTR
204 * Maps a HC physical page pool address to a virtual address.
205 *
206 * @returns VBox status code.
207 * @param pVM The VM handle.
208 * @param HCPhys The HC physical address to map to a virtual one.
209 * @param ppv Where to store the virtual address. No need to cast this.
210 *
211 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
212 * small page window employeed by that function. Be careful.
213 * @remark There is no need to assert on the result.
214 */
215#ifdef IN_RC
216# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
217 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
218#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
219# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
220 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
221#else
222# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
223 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
224#endif
225
226/** @def PGM_HCPHYS_2_PTR_BY_PGM
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pPGM The PGM instance data.
231 * @param HCPhys The HC physical address to map to a virtual one.
232 * @param ppv Where to store the virtual address. No need to cast this.
233 *
234 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
235 * small page window employeed by that function. Be careful.
236 * @remark There is no need to assert on the result.
237 */
238#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
239# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
240 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
241#else
242# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
243 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
244#endif
245
246/** @def PGM_GCPHYS_2_PTR
247 * Maps a GC physical page address to a virtual address.
248 *
249 * @returns VBox status code.
250 * @param pVM The VM handle.
251 * @param GCPhys The GC physical address to map to a virtual one.
252 * @param ppv Where to store the virtual address. No need to cast this.
253 *
254 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
255 * small page window employeed by that function. Be careful.
256 * @remark There is no need to assert on the result.
257 */
258#ifdef IN_RC
259# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
260 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
261#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
262# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
263 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
264#else
265# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pPGM Pointer to the PGM instance data.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
278 * small page window employeed by that function. Be careful.
279 * @remark There is no need to assert on the result.
280 */
281#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
282# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
283 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
284#else
285# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
286 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
287#endif
288
289/** @def PGM_GCPHYS_2_PTR_EX
290 * Maps a unaligned GC physical page address to a virtual address.
291 *
292 * @returns VBox status code.
293 * @param pVM The VM handle.
294 * @param GCPhys The GC physical address to map to a virtual one.
295 * @param ppv Where to store the virtual address. No need to cast this.
296 *
297 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
298 * small page window employeed by that function. Be careful.
299 * @remark There is no need to assert on the result.
300 */
301#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
302# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
303 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
304#else
305# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
306 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
307#endif
308
309/** @def PGM_INVL_PG
310 * Invalidates a page.
311 *
312 * @param pVCpu The VMCPU handle.
313 * @param GCVirt The virtual address of the page to invalidate.
314 */
315#ifdef IN_RC
316# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
317#elif defined(IN_RING0)
318# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
319#else
320# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
321#endif
322
323/** @def PGM_INVL_PG_ALL_VCPU
324 * Invalidates a page on all VCPUs
325 *
326 * @param pVM The VM handle.
327 * @param GCVirt The virtual address of the page to invalidate.
328 */
329#ifdef IN_RC
330# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
331#elif defined(IN_RING0)
332# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
333#else
334# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
335#endif
336
337/** @def PGM_INVL_BIG_PG
338 * Invalidates a 4MB page directory entry.
339 *
340 * @param pVCpu The VMCPU handle.
341 * @param GCVirt The virtual address within the page directory to invalidate.
342 */
343#ifdef IN_RC
344# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
345#elif defined(IN_RING0)
346# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
347#else
348# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
349#endif
350
351/** @def PGM_INVL_VCPU_TLBS()
352 * Invalidates the TLBs of the specified VCPU
353 *
354 * @param pVCpu The VMCPU handle.
355 */
356#ifdef IN_RC
357# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
358#elif defined(IN_RING0)
359# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
360#else
361# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
362#endif
363
364/** @def PGM_INVL_ALL_VCPU_TLBS()
365 * Invalidates the TLBs of all VCPUs
366 *
367 * @param pVM The VM handle.
368 */
369#ifdef IN_RC
370# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
371#elif defined(IN_RING0)
372# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
373#else
374# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
375#endif
376
377/** Size of the GCPtrConflict array in PGMMAPPING.
378 * @remarks Must be a power of two. */
379#define PGMMAPPING_CONFLICT_MAX 8
380
381/**
382 * Structure for tracking GC Mappings.
383 *
384 * This structure is used by linked list in both GC and HC.
385 */
386typedef struct PGMMAPPING
387{
388 /** Pointer to next entry. */
389 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
390 /** Pointer to next entry. */
391 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
392 /** Pointer to next entry. */
393 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
394 /** Indicate whether this entry is finalized. */
395 bool fFinalized;
396 /** Start Virtual address. */
397 RTGCPTR GCPtr;
398 /** Last Virtual address (inclusive). */
399 RTGCPTR GCPtrLast;
400 /** Range size (bytes). */
401 RTGCPTR cb;
402 /** Pointer to relocation callback function. */
403 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
404 /** User argument to the callback. */
405 R3PTRTYPE(void *) pvUser;
406 /** Mapping description / name. For easing debugging. */
407 R3PTRTYPE(const char *) pszDesc;
408 /** Last 8 addresses that caused conflicts. */
409 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
410 /** Number of conflicts for this hypervisor mapping. */
411 uint32_t cConflicts;
412 /** Number of page tables. */
413 uint32_t cPTs;
414
415 /** Array of page table mapping data. Each entry
416 * describes one page table. The array can be longer
417 * than the declared length.
418 */
419 struct
420 {
421 /** The HC physical address of the page table. */
422 RTHCPHYS HCPhysPT;
423 /** The HC physical address of the first PAE page table. */
424 RTHCPHYS HCPhysPaePT0;
425 /** The HC physical address of the second PAE page table. */
426 RTHCPHYS HCPhysPaePT1;
427 /** The HC virtual address of the 32-bit page table. */
428 R3PTRTYPE(PX86PT) pPTR3;
429 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
430 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
431 /** The RC virtual address of the 32-bit page table. */
432 RCPTRTYPE(PX86PT) pPTRC;
433 /** The RC virtual address of the two PAE page table. */
434 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
435 /** The R0 virtual address of the 32-bit page table. */
436 R0PTRTYPE(PX86PT) pPTR0;
437 /** The R0 virtual address of the two PAE page table. */
438 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
439 } aPTs[1];
440} PGMMAPPING;
441/** Pointer to structure for tracking GC Mappings. */
442typedef struct PGMMAPPING *PPGMMAPPING;
443
444
445/**
446 * Physical page access handler structure.
447 *
448 * This is used to keep track of physical address ranges
449 * which are being monitored in some kind of way.
450 */
451typedef struct PGMPHYSHANDLER
452{
453 AVLROGCPHYSNODECORE Core;
454 /** Access type. */
455 PGMPHYSHANDLERTYPE enmType;
456 /** Number of pages to update. */
457 uint32_t cPages;
458 /** Pointer to R3 callback function. */
459 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
460 /** User argument for R3 handlers. */
461 R3PTRTYPE(void *) pvUserR3;
462 /** Pointer to R0 callback function. */
463 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
464 /** User argument for R0 handlers. */
465 R0PTRTYPE(void *) pvUserR0;
466 /** Pointer to RC callback function. */
467 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
468 /** User argument for RC handlers. */
469 RCPTRTYPE(void *) pvUserRC;
470 /** Description / Name. For easing debugging. */
471 R3PTRTYPE(const char *) pszDesc;
472#ifdef VBOX_WITH_STATISTICS
473 /** Profiling of this handler. */
474 STAMPROFILE Stat;
475#endif
476} PGMPHYSHANDLER;
477/** Pointer to a physical page access handler structure. */
478typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
479
480
481/**
482 * Cache node for the physical addresses covered by a virtual handler.
483 */
484typedef struct PGMPHYS2VIRTHANDLER
485{
486 /** Core node for the tree based on physical ranges. */
487 AVLROGCPHYSNODECORE Core;
488 /** Offset from this struct to the PGMVIRTHANDLER structure. */
489 int32_t offVirtHandler;
490 /** Offset of the next alias relative to this one.
491 * Bit 0 is used for indicating whether we're in the tree.
492 * Bit 1 is used for indicating that we're the head node.
493 */
494 int32_t offNextAlias;
495} PGMPHYS2VIRTHANDLER;
496/** Pointer to a phys to virtual handler structure. */
497typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
498
499/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
500 * node is in the tree. */
501#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
502/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
503 * node is in the head of an alias chain.
504 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
505#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
506/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
507#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
508
509
510/**
511 * Virtual page access handler structure.
512 *
513 * This is used to keep track of virtual address ranges
514 * which are being monitored in some kind of way.
515 */
516typedef struct PGMVIRTHANDLER
517{
518 /** Core node for the tree based on virtual ranges. */
519 AVLROGCPTRNODECORE Core;
520 /** Size of the range (in bytes). */
521 RTGCPTR cb;
522 /** Number of cache pages. */
523 uint32_t cPages;
524 /** Access type. */
525 PGMVIRTHANDLERTYPE enmType;
526 /** Pointer to the RC callback function. */
527 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
528#if HC_ARCH_BITS == 64
529 RTRCPTR padding;
530#endif
531 /** Pointer to the R3 callback function for invalidation. */
532 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
533 /** Pointer to the R3 callback function. */
534 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
535 /** Description / Name. For easing debugging. */
536 R3PTRTYPE(const char *) pszDesc;
537#ifdef VBOX_WITH_STATISTICS
538 /** Profiling of this handler. */
539 STAMPROFILE Stat;
540#endif
541 /** Array of cached physical addresses for the monitored ranged. */
542 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
543} PGMVIRTHANDLER;
544/** Pointer to a virtual page access handler structure. */
545typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
546
547
548/**
549 * Page type.
550 *
551 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
552 * @remarks This is used in the saved state, so changes to it requires bumping
553 * the saved state version.
554 * @todo So, convert to \#defines!
555 */
556typedef enum PGMPAGETYPE
557{
558 /** The usual invalid zero entry. */
559 PGMPAGETYPE_INVALID = 0,
560 /** RAM page. (RWX) */
561 PGMPAGETYPE_RAM,
562 /** MMIO2 page. (RWX) */
563 PGMPAGETYPE_MMIO2,
564 /** MMIO2 page aliased over an MMIO page. (RWX)
565 * See PGMHandlerPhysicalPageAlias(). */
566 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
567 /** Shadowed ROM. (RWX) */
568 PGMPAGETYPE_ROM_SHADOW,
569 /** ROM page. (R-X) */
570 PGMPAGETYPE_ROM,
571 /** MMIO page. (---) */
572 PGMPAGETYPE_MMIO,
573 /** End of valid entries. */
574 PGMPAGETYPE_END
575} PGMPAGETYPE;
576AssertCompile(PGMPAGETYPE_END <= 7);
577
578/** @name Page type predicates.
579 * @{ */
580#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
581#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
582#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
583#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
584#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
585/** @} */
586
587
588/**
589 * A Physical Guest Page tracking structure.
590 *
591 * The format of this structure is complicated because we have to fit a lot
592 * of information into as few bits as possible. The format is also subject
593 * to change (there is one comming up soon). Which means that for we'll be
594 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
595 * accesses to the structure.
596 */
597typedef struct PGMPAGE
598{
599 /** The physical address and the Page ID. */
600 RTHCPHYS HCPhysAndPageID;
601 /** Combination of:
602 * - [0-7]: u2HandlerPhysStateY - the physical handler state
603 * (PGM_PAGE_HNDL_PHYS_STATE_*).
604 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
605 * (PGM_PAGE_HNDL_VIRT_STATE_*).
606 * - [15]: fWrittenToY - flag indicating that a write monitored page was
607 * written to when set.
608 * - [10-14]: 5 unused bits.
609 * @remarks Warning! All accesses to the bits are hardcoded.
610 *
611 * @todo Change this to a union with both bitfields, u8 and u accessors.
612 * That'll help deal with some of the hardcoded accesses.
613 *
614 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
615 * will make it possible to turn some of the 16-bit accesses into
616 * 32-bit ones, which may be efficient (stalls).
617 */
618 RTUINT16U u16MiscY;
619 /** The page state.
620 * Only 2 bits are really needed for this. */
621 uint8_t uStateY;
622 /** The page type (PGMPAGETYPE).
623 * Only 3 bits are really needed for this. */
624 uint8_t uTypeY;
625 /** Usage tracking (page pool). */
626 uint16_t u16TrackingY;
627 /** The number of read locks on this page. */
628 uint8_t cReadLocksY;
629 /** The number of write locks on this page. */
630 uint8_t cWriteLocksY;
631} PGMPAGE;
632AssertCompileSize(PGMPAGE, 16);
633/** Pointer to a physical guest page. */
634typedef PGMPAGE *PPGMPAGE;
635/** Pointer to a const physical guest page. */
636typedef const PGMPAGE *PCPGMPAGE;
637/** Pointer to a physical guest page pointer. */
638typedef PPGMPAGE *PPPGMPAGE;
639
640
641/**
642 * Clears the page structure.
643 * @param pPage Pointer to the physical guest page tracking structure.
644 */
645#define PGM_PAGE_CLEAR(pPage) \
646 do { \
647 (pPage)->HCPhysAndPageID = 0; \
648 (pPage)->uStateY = 0; \
649 (pPage)->uTypeY = 0; \
650 (pPage)->u16MiscY.u = 0; \
651 (pPage)->u16TrackingY = 0; \
652 (pPage)->cReadLocksY = 0; \
653 (pPage)->cWriteLocksY = 0; \
654 } while (0)
655
656/**
657 * Initializes the page structure.
658 * @param pPage Pointer to the physical guest page tracking structure.
659 */
660#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
661 do { \
662 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
663 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
664 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
665 (pPage)->uStateY = (_uState); \
666 (pPage)->uTypeY = (_uType); \
667 (pPage)->u16MiscY.u = 0; \
668 (pPage)->u16TrackingY = 0; \
669 (pPage)->cReadLocksY = 0; \
670 (pPage)->cWriteLocksY = 0; \
671 } while (0)
672
673/**
674 * Initializes the page structure of a ZERO page.
675 * @param pPage Pointer to the physical guest page tracking structure.
676 * @param pVM The VM handle (for getting the zero page address).
677 * @param uType The page type (PGMPAGETYPE).
678 */
679#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
680 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
681
682
683/** @name The Page state, PGMPAGE::uStateY.
684 * @{ */
685/** The zero page.
686 * This is a per-VM page that's never ever mapped writable. */
687#define PGM_PAGE_STATE_ZERO 0
688/** A allocated page.
689 * This is a per-VM page allocated from the page pool (or wherever
690 * we get MMIO2 pages from if the type is MMIO2).
691 */
692#define PGM_PAGE_STATE_ALLOCATED 1
693/** A allocated page that's being monitored for writes.
694 * The shadow page table mappings are read-only. When a write occurs, the
695 * fWrittenTo member is set, the page remapped as read-write and the state
696 * moved back to allocated. */
697#define PGM_PAGE_STATE_WRITE_MONITORED 2
698/** The page is shared, aka. copy-on-write.
699 * This is a page that's shared with other VMs. */
700#define PGM_PAGE_STATE_SHARED 3
701/** @} */
702
703
704/**
705 * Gets the page state.
706 * @returns page state (PGM_PAGE_STATE_*).
707 * @param pPage Pointer to the physical guest page tracking structure.
708 */
709#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
710
711/**
712 * Sets the page state.
713 * @param pPage Pointer to the physical guest page tracking structure.
714 * @param _uState The new page state.
715 */
716#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
717
718
719/**
720 * Gets the host physical address of the guest page.
721 * @returns host physical address (RTHCPHYS).
722 * @param pPage Pointer to the physical guest page tracking structure.
723 */
724#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
725
726/**
727 * Sets the host physical address of the guest page.
728 * @param pPage Pointer to the physical guest page tracking structure.
729 * @param _HCPhys The new host physical address.
730 */
731#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
732 do { \
733 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
734 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
735 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
736 | (SetHCPhysTmp << (28-12)); \
737 } while (0)
738
739/**
740 * Get the Page ID.
741 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
742 * @param pPage Pointer to the physical guest page tracking structure.
743 */
744#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
745
746/**
747 * Sets the Page ID.
748 * @param pPage Pointer to the physical guest page tracking structure.
749 */
750#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
751 do { \
752 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
753 | ((_idPage) & UINT32_C(0x0fffffff)); \
754 } while (0)
755
756/**
757 * Get the Chunk ID.
758 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
762
763/**
764 * Get the index of the page within the allocation chunk.
765 * @returns The page index.
766 * @param pPage Pointer to the physical guest page tracking structure.
767 */
768#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
769
770/**
771 * Gets the page type.
772 * @returns The page type.
773 * @param pPage Pointer to the physical guest page tracking structure.
774 */
775#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
776
777/**
778 * Sets the page type.
779 * @param pPage Pointer to the physical guest page tracking structure.
780 * @param _enmType The new page type (PGMPAGETYPE).
781 */
782#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
783
784/**
785 * Checks if the page is marked for MMIO.
786 * @returns true/false.
787 * @param pPage Pointer to the physical guest page tracking structure.
788 */
789#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
790
791/**
792 * Checks if the page is backed by the ZERO page.
793 * @returns true/false.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
797
798/**
799 * Checks if the page is backed by a SHARED page.
800 * @returns true/false.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
804
805
806/**
807 * Marks the paget as written to (for GMM change monitoring).
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
811
812/**
813 * Clears the written-to indicator.
814 * @param pPage Pointer to the physical guest page tracking structure.
815 */
816#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
817
818/**
819 * Checks if the page was marked as written-to.
820 * @returns true/false.
821 * @param pPage Pointer to the physical guest page tracking structure.
822 */
823#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
824
825
826/** Enabled optimized access handler tests.
827 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
828 * layout. When enabled, the compiler should normally generate more compact
829 * code.
830 */
831#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
832
833/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
834 *
835 * @remarks The values are assigned in order of priority, so we can calculate
836 * the correct state for a page with different handlers installed.
837 * @{ */
838/** No handler installed. */
839#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
840/** Monitoring is temporarily disabled. */
841#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
842/** Write access is monitored. */
843#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
844/** All access is monitored. */
845#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
846/** @} */
847
848/**
849 * Gets the physical access handler state of a page.
850 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
851 * @param pPage Pointer to the physical guest page tracking structure.
852 */
853#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
854 ( (pPage)->u16MiscY.au8[0] )
855
856/**
857 * Sets the physical access handler state of a page.
858 * @param pPage Pointer to the physical guest page tracking structure.
859 * @param _uState The new state value.
860 */
861#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
862 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
863
864/**
865 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
866 * @returns true/false
867 * @param pPage Pointer to the physical guest page tracking structure.
868 */
869#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
870 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
871
872/**
873 * Checks if the page has any active physical access handlers.
874 * @returns true/false
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
878 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
879
880
881/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
882 *
883 * @remarks The values are assigned in order of priority, so we can calculate
884 * the correct state for a page with different handlers installed.
885 * @{ */
886/** No handler installed. */
887#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
888/* 1 is reserved so the lineup is identical with the physical ones. */
889/** Write access is monitored. */
890#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
891/** All access is monitored. */
892#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
893/** @} */
894
895/**
896 * Gets the virtual access handler state of a page.
897 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
898 * @param pPage Pointer to the physical guest page tracking structure.
899 */
900#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) )
901
902/**
903 * Sets the virtual access handler state of a page.
904 * @param pPage Pointer to the physical guest page tracking structure.
905 * @param _uState The new state value.
906 */
907#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
908 do { \
909 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
910 | ((_uState) & UINT8_C(0x03)); \
911 } while (0)
912
913/**
914 * Checks if the page has any virtual access handlers.
915 * @returns true/false
916 * @param pPage Pointer to the physical guest page tracking structure.
917 */
918#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
919 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
920
921/**
922 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
923 * virtual handlers.
924 * @returns true/false
925 * @param pPage Pointer to the physical guest page tracking structure.
926 */
927#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
928 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
929
930
931/**
932 * Checks if the page has any access handlers, including temporarily disabled ones.
933 * @returns true/false
934 * @param pPage Pointer to the physical guest page tracking structure.
935 */
936#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
937# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
938 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
939#else
940# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
941 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
942 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
943#endif
944
945/**
946 * Checks if the page has any active access handlers.
947 * @returns true/false
948 * @param pPage Pointer to the physical guest page tracking structure.
949 */
950#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
951# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
952 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
953#else
954# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
955 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
956 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
957#endif
958
959/**
960 * Checks if the page has any active access handlers catching all accesses.
961 * @returns true/false
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
965# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
967 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
968#else
969# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
970 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
971 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
972#endif
973
974
975/** @def PGM_PAGE_GET_TRACKING
976 * Gets the packed shadow page pool tracking data associated with a guest page.
977 * @returns uint16_t containing the data.
978 * @param pPage Pointer to the physical guest page tracking structure.
979 */
980#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
981
982/** @def PGM_PAGE_SET_TRACKING
983 * Sets the packed shadow page pool tracking data associated with a guest page.
984 * @param pPage Pointer to the physical guest page tracking structure.
985 * @param u16TrackingData The tracking data to store.
986 */
987#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
988 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
989
990/** @def PGM_PAGE_GET_TD_CREFS
991 * Gets the @a cRefs tracking data member.
992 * @returns cRefs.
993 * @param pPage Pointer to the physical guest page tracking structure.
994 */
995#define PGM_PAGE_GET_TD_CREFS(pPage) \
996 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
997
998/** @def PGM_PAGE_GET_TD_IDX
999 * Gets the @a idx tracking data member.
1000 * @returns idx.
1001 * @param pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_GET_TD_IDX(pPage) \
1004 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1005
1006
1007/** Max number of locks on a page. */
1008#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1009
1010/** Get the read lock count.
1011 * @returns count.
1012 * @param pPage Pointer to the physical guest page tracking structure.
1013 */
1014#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1015
1016/** Get the write lock count.
1017 * @returns count.
1018 * @param pPage Pointer to the physical guest page tracking structure.
1019 */
1020#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1021
1022/** Decrement the read lock counter.
1023 * @param pPage Pointer to the physical guest page tracking structure.
1024 */
1025#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1026
1027/** Decrement the write lock counter.
1028 * @param pPage Pointer to the physical guest page tracking structure.
1029 */
1030#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1031
1032/** Increment the read lock counter.
1033 * @param pPage Pointer to the physical guest page tracking structure.
1034 */
1035#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1036
1037/** Increment the write lock counter.
1038 * @param pPage Pointer to the physical guest page tracking structure.
1039 */
1040#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1041
1042
1043#if 0
1044/** Enables sanity checking of write monitoring using CRC-32. */
1045# define PGMLIVESAVERAMPAGE_WITH_CRC32
1046#endif
1047
1048/**
1049 * Per page live save tracking data.
1050 */
1051typedef struct PGMLIVESAVERAMPAGE
1052{
1053 /** Number of times it has been dirtied. */
1054 uint32_t cDirtied : 24;
1055 /** Whether it is currently dirty. */
1056 uint32_t fDirty : 1;
1057 /** Ignore the page.
1058 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1059 * deal with these after pausing the VM and DevPCI have said it bit about
1060 * remappings. */
1061 uint32_t fIgnore : 1;
1062 /** Was a ZERO page last time around. */
1063 uint32_t fZero : 1;
1064 /** Was a SHARED page last time around. */
1065 uint32_t fShared : 1;
1066 /** Whether the page is/was write monitored in a previous pass. */
1067 uint32_t fWriteMonitored : 1;
1068 /** Whether the page is/was write monitored earlier in this pass. */
1069 uint32_t fWriteMonitoredJustNow : 1;
1070 /** Bits reserved for future use. */
1071 uint32_t u2Reserved : 2;
1072#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1073 /** CRC-32 for the page. This is for internal consistency checks. */
1074 uint32_t u32Crc;
1075#endif
1076} PGMLIVESAVERAMPAGE;
1077#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1078AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1079#else
1080AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1081#endif
1082/** Pointer to the per page live save tracking data. */
1083typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1084
1085/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1086#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1087
1088
1089/**
1090 * Ram range for GC Phys to HC Phys conversion.
1091 *
1092 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1093 * conversions too, but we'll let MM handle that for now.
1094 *
1095 * This structure is used by linked lists in both GC and HC.
1096 */
1097typedef struct PGMRAMRANGE
1098{
1099 /** Start of the range. Page aligned. */
1100 RTGCPHYS GCPhys;
1101 /** Size of the range. (Page aligned of course). */
1102 RTGCPHYS cb;
1103 /** Pointer to the next RAM range - for R3. */
1104 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1105 /** Pointer to the next RAM range - for R0. */
1106 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1107 /** Pointer to the next RAM range - for RC. */
1108 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1109 /** PGM_RAM_RANGE_FLAGS_* flags. */
1110 uint32_t fFlags;
1111 /** Last address in the range (inclusive). Page aligned (-1). */
1112 RTGCPHYS GCPhysLast;
1113 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1114 R3PTRTYPE(void *) pvR3;
1115 /** Live save per page tracking data. */
1116 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1117 /** The range description. */
1118 R3PTRTYPE(const char *) pszDesc;
1119 /** Pointer to self - R0 pointer. */
1120 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1121 /** Pointer to self - RC pointer. */
1122 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1123 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1124 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1125 /** Array of physical guest page tracking structures. */
1126 PGMPAGE aPages[1];
1127} PGMRAMRANGE;
1128/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1129typedef PGMRAMRANGE *PPGMRAMRANGE;
1130
1131/** @name PGMRAMRANGE::fFlags
1132 * @{ */
1133/** The RAM range is floating around as an independent guest mapping. */
1134#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1135/** Ad hoc RAM range for an ROM mapping. */
1136#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1137/** Ad hoc RAM range for an MMIO mapping. */
1138#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1139/** Ad hoc RAM range for an MMIO2 mapping. */
1140#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1141/** @} */
1142
1143/** Tests if a RAM range is an ad hoc one or not.
1144 * @returns true/false.
1145 * @param pRam The RAM range.
1146 */
1147#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1148 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1149
1150
1151/**
1152 * Per page tracking structure for ROM image.
1153 *
1154 * A ROM image may have a shadow page, in which case we may have two pages
1155 * backing it. This structure contains the PGMPAGE for both while
1156 * PGMRAMRANGE have a copy of the active one. It is important that these
1157 * aren't out of sync in any regard other than page pool tracking data.
1158 */
1159typedef struct PGMROMPAGE
1160{
1161 /** The page structure for the virgin ROM page. */
1162 PGMPAGE Virgin;
1163 /** The page structure for the shadow RAM page. */
1164 PGMPAGE Shadow;
1165 /** The current protection setting. */
1166 PGMROMPROT enmProt;
1167 /** Live save status information. Makes use of unused alignment space. */
1168 struct
1169 {
1170 /** The previous protection value. */
1171 uint8_t u8Prot;
1172 /** Written to flag set by the handler. */
1173 bool fWrittenTo;
1174 /** Whether the shadow page is dirty or not. */
1175 bool fDirty;
1176 /** Whether it was dirtied in the recently. */
1177 bool fDirtiedRecently;
1178 } LiveSave;
1179} PGMROMPAGE;
1180AssertCompileSizeAlignment(PGMROMPAGE, 8);
1181/** Pointer to a ROM page tracking structure. */
1182typedef PGMROMPAGE *PPGMROMPAGE;
1183
1184
1185/**
1186 * A registered ROM image.
1187 *
1188 * This is needed to keep track of ROM image since they generally intrude
1189 * into a PGMRAMRANGE. It also keeps track of additional info like the
1190 * two page sets (read-only virgin and read-write shadow), the current
1191 * state of each page.
1192 *
1193 * Because access handlers cannot easily be executed in a different
1194 * context, the ROM ranges needs to be accessible and in all contexts.
1195 */
1196typedef struct PGMROMRANGE
1197{
1198 /** Pointer to the next range - R3. */
1199 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1200 /** Pointer to the next range - R0. */
1201 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1202 /** Pointer to the next range - RC. */
1203 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1204 /** Pointer alignment */
1205 RTRCPTR RCPtrAlignment;
1206 /** Address of the range. */
1207 RTGCPHYS GCPhys;
1208 /** Address of the last byte in the range. */
1209 RTGCPHYS GCPhysLast;
1210 /** Size of the range. */
1211 RTGCPHYS cb;
1212 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1213 uint32_t fFlags;
1214 /** The saved state range ID. */
1215 uint8_t idSavedState;
1216 /** Alignment padding. */
1217 uint8_t au8Alignment[3];
1218 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1219 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1220 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1221 * This is used for strictness checks. */
1222 R3PTRTYPE(const void *) pvOriginal;
1223 /** The ROM description. */
1224 R3PTRTYPE(const char *) pszDesc;
1225 /** The per page tracking structures. */
1226 PGMROMPAGE aPages[1];
1227} PGMROMRANGE;
1228/** Pointer to a ROM range. */
1229typedef PGMROMRANGE *PPGMROMRANGE;
1230
1231
1232/**
1233 * Live save per page data for an MMIO2 page.
1234 *
1235 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1236 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1237 * CRC-32 for detecting changes as well as special handling of zero pages. This
1238 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1239 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1240 * because of speed (2.5x and 6x slower).)
1241 *
1242 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1243 * save but normally is disabled. Since we can write monitore guest
1244 * accesses on our own, we only need this for host accesses. Shouldn't be
1245 * too difficult for DevVGA, VMMDev might be doable, the planned
1246 * networking fun will be fun since it involves ring-0.
1247 */
1248typedef struct PGMLIVESAVEMMIO2PAGE
1249{
1250 /** Set if the page is considered dirty. */
1251 bool fDirty;
1252 /** The number of scans this page has remained unchanged for.
1253 * Only updated for dirty pages. */
1254 uint8_t cUnchangedScans;
1255 /** Whether this page was zero at the last scan. */
1256 bool fZero;
1257 /** Alignment padding. */
1258 bool fReserved;
1259 /** CRC-32 for the first half of the page.
1260 * This is used together with u32CrcH2 to quickly detect changes in the page
1261 * during the non-final passes. */
1262 uint32_t u32CrcH1;
1263 /** CRC-32 for the second half of the page. */
1264 uint32_t u32CrcH2;
1265 /** SHA-1 for the saved page.
1266 * This is used in the final pass to skip pages without changes. */
1267 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1268} PGMLIVESAVEMMIO2PAGE;
1269/** Pointer to a live save status data for an MMIO2 page. */
1270typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1271
1272/**
1273 * A registered MMIO2 (= Device RAM) range.
1274 *
1275 * There are a few reason why we need to keep track of these
1276 * registrations. One of them is the deregistration & cleanup stuff,
1277 * while another is that the PGMRAMRANGE associated with such a region may
1278 * have to be removed from the ram range list.
1279 *
1280 * Overlapping with a RAM range has to be 100% or none at all. The pages
1281 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1282 * will be raised if a partial overlap or an overlap of ROM pages is
1283 * encountered. On an overlap we will free all the existing RAM pages and
1284 * put in the ram range pages instead.
1285 */
1286typedef struct PGMMMIO2RANGE
1287{
1288 /** The owner of the range. (a device) */
1289 PPDMDEVINSR3 pDevInsR3;
1290 /** Pointer to the ring-3 mapping of the allocation. */
1291 RTR3PTR pvR3;
1292 /** Pointer to the next range - R3. */
1293 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1294 /** Whether it's mapped or not. */
1295 bool fMapped;
1296 /** Whether it's overlapping or not. */
1297 bool fOverlapping;
1298 /** The PCI region number.
1299 * @remarks This ASSUMES that nobody will ever really need to have multiple
1300 * PCI devices with matching MMIO region numbers on a single device. */
1301 uint8_t iRegion;
1302 /** The saved state range ID. */
1303 uint8_t idSavedState;
1304 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1305 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1306 /** Live save per page tracking data. */
1307 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1308 /** The associated RAM range. */
1309 PGMRAMRANGE RamRange;
1310} PGMMMIO2RANGE;
1311/** Pointer to a MMIO2 range. */
1312typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1313
1314
1315
1316
1317/**
1318 * PGMPhysRead/Write cache entry
1319 */
1320typedef struct PGMPHYSCACHEENTRY
1321{
1322 /** R3 pointer to physical page. */
1323 R3PTRTYPE(uint8_t *) pbR3;
1324 /** GC Physical address for cache entry */
1325 RTGCPHYS GCPhys;
1326#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1327 RTGCPHYS u32Padding0; /**< alignment padding. */
1328#endif
1329} PGMPHYSCACHEENTRY;
1330
1331/**
1332 * PGMPhysRead/Write cache to reduce REM memory access overhead
1333 */
1334typedef struct PGMPHYSCACHE
1335{
1336 /** Bitmap of valid cache entries */
1337 uint64_t aEntries;
1338 /** Cache entries */
1339 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1340} PGMPHYSCACHE;
1341
1342
1343/** Pointer to an allocation chunk ring-3 mapping. */
1344typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1345/** Pointer to an allocation chunk ring-3 mapping pointer. */
1346typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1347
1348/**
1349 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1350 *
1351 * The primary tree (Core) uses the chunk id as key.
1352 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1353 */
1354typedef struct PGMCHUNKR3MAP
1355{
1356 /** The key is the chunk id. */
1357 AVLU32NODECORE Core;
1358 /** The key is the ageing sequence number. */
1359 AVLLU32NODECORE AgeCore;
1360 /** The current age thingy. */
1361 uint32_t iAge;
1362 /** The current reference count. */
1363 uint32_t volatile cRefs;
1364 /** The current permanent reference count. */
1365 uint32_t volatile cPermRefs;
1366 /** The mapping address. */
1367 void *pv;
1368} PGMCHUNKR3MAP;
1369
1370/**
1371 * Allocation chunk ring-3 mapping TLB entry.
1372 */
1373typedef struct PGMCHUNKR3MAPTLBE
1374{
1375 /** The chunk id. */
1376 uint32_t volatile idChunk;
1377#if HC_ARCH_BITS == 64
1378 uint32_t u32Padding; /**< alignment padding. */
1379#endif
1380 /** The chunk map. */
1381#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1382 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1383#else
1384 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1385#endif
1386} PGMCHUNKR3MAPTLBE;
1387/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1388typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1389
1390/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1391 * @remark Must be a power of two value. */
1392#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1393
1394/**
1395 * Allocation chunk ring-3 mapping TLB.
1396 *
1397 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1398 * At first glance this might look kinda odd since AVL trees are
1399 * supposed to give the most optimial lookup times of all trees
1400 * due to their balancing. However, take a tree with 1023 nodes
1401 * in it, that's 10 levels, meaning that most searches has to go
1402 * down 9 levels before they find what they want. This isn't fast
1403 * compared to a TLB hit. There is the factor of cache misses,
1404 * and of course the problem with trees and branch prediction.
1405 * This is why we use TLBs in front of most of the trees.
1406 *
1407 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1408 * difficult when we switch to the new inlined AVL trees (from kStuff).
1409 */
1410typedef struct PGMCHUNKR3MAPTLB
1411{
1412 /** The TLB entries. */
1413 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1414} PGMCHUNKR3MAPTLB;
1415
1416/**
1417 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1418 * @returns Chunk TLB index.
1419 * @param idChunk The Chunk ID.
1420 */
1421#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1422
1423
1424/**
1425 * Ring-3 guest page mapping TLB entry.
1426 * @remarks used in ring-0 as well at the moment.
1427 */
1428typedef struct PGMPAGER3MAPTLBE
1429{
1430 /** Address of the page. */
1431 RTGCPHYS volatile GCPhys;
1432 /** The guest page. */
1433#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1434 R3PTRTYPE(PPGMPAGE) volatile pPage;
1435#else
1436 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1437#endif
1438 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1439#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1440 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1441#else
1442 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1443#endif
1444 /** The address */
1445#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1446 R3PTRTYPE(void *) volatile pv;
1447#else
1448 R3R0PTRTYPE(void *) volatile pv;
1449#endif
1450#if HC_ARCH_BITS == 32
1451 uint32_t u32Padding; /**< alignment padding. */
1452#endif
1453} PGMPAGER3MAPTLBE;
1454/** Pointer to an entry in the HC physical TLB. */
1455typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1456
1457
1458/** The number of entries in the ring-3 guest page mapping TLB.
1459 * @remarks The value must be a power of two. */
1460#define PGM_PAGER3MAPTLB_ENTRIES 256
1461
1462/**
1463 * Ring-3 guest page mapping TLB.
1464 * @remarks used in ring-0 as well at the moment.
1465 */
1466typedef struct PGMPAGER3MAPTLB
1467{
1468 /** The TLB entries. */
1469 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1470} PGMPAGER3MAPTLB;
1471/** Pointer to the ring-3 guest page mapping TLB. */
1472typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1473
1474/**
1475 * Calculates the index of the TLB entry for the specified guest page.
1476 * @returns Physical TLB index.
1477 * @param GCPhys The guest physical address.
1478 */
1479#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1480
1481
1482/**
1483 * Mapping cache usage set entry.
1484 *
1485 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1486 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1487 * cache. If it's extended to include ring-3, well, then something will
1488 * have be changed here...
1489 */
1490typedef struct PGMMAPSETENTRY
1491{
1492 /** The mapping cache index. */
1493 uint16_t iPage;
1494 /** The number of references.
1495 * The max is UINT16_MAX - 1. */
1496 uint16_t cRefs;
1497#if HC_ARCH_BITS == 64
1498 uint32_t alignment;
1499#endif
1500 /** Pointer to the page. */
1501 RTR0PTR pvPage;
1502 /** The physical address for this entry. */
1503 RTHCPHYS HCPhys;
1504} PGMMAPSETENTRY;
1505/** Pointer to a mapping cache usage set entry. */
1506typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1507
1508/**
1509 * Mapping cache usage set.
1510 *
1511 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1512 * done during exits / traps. The set is
1513 */
1514typedef struct PGMMAPSET
1515{
1516 /** The number of occupied entries.
1517 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1518 * dynamic mappings. */
1519 uint32_t cEntries;
1520 /** The start of the current subset.
1521 * This is UINT32_MAX if no subset is currently open. */
1522 uint32_t iSubset;
1523 /** The index of the current CPU, only valid if the set is open. */
1524 int32_t iCpu;
1525 uint32_t alignment;
1526 /** The entries. */
1527 PGMMAPSETENTRY aEntries[64];
1528 /** HCPhys -> iEntry fast lookup table.
1529 * Use PGMMAPSET_HASH for hashing.
1530 * The entries may or may not be valid, check against cEntries. */
1531 uint8_t aiHashTable[128];
1532} PGMMAPSET;
1533AssertCompileSizeAlignment(PGMMAPSET, 8);
1534/** Pointer to the mapping cache set. */
1535typedef PGMMAPSET *PPGMMAPSET;
1536
1537/** PGMMAPSET::cEntries value for a closed set. */
1538#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1539
1540/** Hash function for aiHashTable. */
1541#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1542
1543/** The max fill size (strict builds). */
1544#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1545
1546
1547/** @name Context neutrual page mapper TLB.
1548 *
1549 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1550 * code is writting in a kind of context neutrual way. Time will show whether
1551 * this actually makes sense or not...
1552 *
1553 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1554 * context ends up using a global mapping cache on some platforms
1555 * (darwin).
1556 *
1557 * @{ */
1558/** @typedef PPGMPAGEMAPTLB
1559 * The page mapper TLB pointer type for the current context. */
1560/** @typedef PPGMPAGEMAPTLB
1561 * The page mapper TLB entry pointer type for the current context. */
1562/** @typedef PPGMPAGEMAPTLB
1563 * The page mapper TLB entry pointer pointer type for the current context. */
1564/** @def PGM_PAGEMAPTLB_ENTRIES
1565 * The number of TLB entries in the page mapper TLB for the current context. */
1566/** @def PGM_PAGEMAPTLB_IDX
1567 * Calculate the TLB index for a guest physical address.
1568 * @returns The TLB index.
1569 * @param GCPhys The guest physical address. */
1570/** @typedef PPGMPAGEMAP
1571 * Pointer to a page mapper unit for current context. */
1572/** @typedef PPPGMPAGEMAP
1573 * Pointer to a page mapper unit pointer for current context. */
1574#ifdef IN_RC
1575// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1576// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1577// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1578# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1579# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1580 typedef void * PPGMPAGEMAP;
1581 typedef void ** PPPGMPAGEMAP;
1582//#elif IN_RING0
1583// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1584// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1585// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1586//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1587//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1588// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1589// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1590#else
1591 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1592 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1593 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1594# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1595# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1596 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1597 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1598#endif
1599/** @} */
1600
1601
1602/** @name PGM Pool Indexes.
1603 * Aka. the unique shadow page identifier.
1604 * @{ */
1605/** NIL page pool IDX. */
1606#define NIL_PGMPOOL_IDX 0
1607/** The first normal index. */
1608#define PGMPOOL_IDX_FIRST_SPECIAL 1
1609/** Page directory (32-bit root). */
1610#define PGMPOOL_IDX_PD 1
1611/** Page Directory Pointer Table (PAE root). */
1612#define PGMPOOL_IDX_PDPT 2
1613/** AMD64 CR3 level index.*/
1614#define PGMPOOL_IDX_AMD64_CR3 3
1615/** Nested paging root.*/
1616#define PGMPOOL_IDX_NESTED_ROOT 4
1617/** The first normal index. */
1618#define PGMPOOL_IDX_FIRST 5
1619/** The last valid index. (inclusive, 14 bits) */
1620#define PGMPOOL_IDX_LAST 0x3fff
1621/** @} */
1622
1623/** The NIL index for the parent chain. */
1624#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1625#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1626
1627/**
1628 * Node in the chain linking a shadowed page to it's parent (user).
1629 */
1630#pragma pack(1)
1631typedef struct PGMPOOLUSER
1632{
1633 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1634 uint16_t iNext;
1635 /** The user page index. */
1636 uint16_t iUser;
1637 /** Index into the user table. */
1638 uint32_t iUserTable;
1639} PGMPOOLUSER, *PPGMPOOLUSER;
1640typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1641#pragma pack()
1642
1643
1644/** The NIL index for the phys ext chain. */
1645#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1646
1647/**
1648 * Node in the chain of physical cross reference extents.
1649 * @todo Calling this an 'extent' is not quite right, find a better name.
1650 */
1651#pragma pack(1)
1652typedef struct PGMPOOLPHYSEXT
1653{
1654 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1655 uint16_t iNext;
1656 /** The user page index. */
1657 uint16_t aidx[3];
1658} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1659typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1660#pragma pack()
1661
1662
1663/**
1664 * The kind of page that's being shadowed.
1665 */
1666typedef enum PGMPOOLKIND
1667{
1668 /** The virtual invalid 0 entry. */
1669 PGMPOOLKIND_INVALID = 0,
1670 /** The entry is free (=unused). */
1671 PGMPOOLKIND_FREE,
1672
1673 /** Shw: 32-bit page table; Gst: no paging */
1674 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1675 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1676 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1677 /** Shw: 32-bit page table; Gst: 4MB page. */
1678 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1679 /** Shw: PAE page table; Gst: no paging */
1680 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1681 /** Shw: PAE page table; Gst: 32-bit page table. */
1682 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1683 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1684 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1685 /** Shw: PAE page table; Gst: PAE page table. */
1686 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1687 /** Shw: PAE page table; Gst: 2MB page. */
1688 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1689
1690 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1691 PGMPOOLKIND_32BIT_PD,
1692 /** Shw: 32-bit page directory. Gst: no paging. */
1693 PGMPOOLKIND_32BIT_PD_PHYS,
1694 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1695 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1696 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1697 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1698 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1699 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1700 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1701 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1702 /** Shw: PAE page directory; Gst: PAE page directory. */
1703 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1704 /** Shw: PAE page directory; Gst: no paging. */
1705 PGMPOOLKIND_PAE_PD_PHYS,
1706
1707 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1708 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1709 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1710 PGMPOOLKIND_PAE_PDPT,
1711 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1712 PGMPOOLKIND_PAE_PDPT_PHYS,
1713
1714 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1715 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1716 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1717 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1718 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1719 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1720 /** Shw: 64-bit page directory table; Gst: no paging */
1721 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1722
1723 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1724 PGMPOOLKIND_64BIT_PML4,
1725
1726 /** Shw: EPT page directory pointer table; Gst: no paging */
1727 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1728 /** Shw: EPT page directory table; Gst: no paging */
1729 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1730 /** Shw: EPT page table; Gst: no paging */
1731 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1732
1733 /** Shw: Root Nested paging table. */
1734 PGMPOOLKIND_ROOT_NESTED,
1735
1736 /** The last valid entry. */
1737 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1738} PGMPOOLKIND;
1739
1740/**
1741 * The access attributes of the page; only applies to big pages.
1742 */
1743typedef enum
1744{
1745 PGMPOOLACCESS_DONTCARE = 0,
1746 PGMPOOLACCESS_USER_RW,
1747 PGMPOOLACCESS_USER_R,
1748 PGMPOOLACCESS_USER_RW_NX,
1749 PGMPOOLACCESS_USER_R_NX,
1750 PGMPOOLACCESS_SUPERVISOR_RW,
1751 PGMPOOLACCESS_SUPERVISOR_R,
1752 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1753 PGMPOOLACCESS_SUPERVISOR_R_NX
1754} PGMPOOLACCESS;
1755
1756/**
1757 * The tracking data for a page in the pool.
1758 */
1759typedef struct PGMPOOLPAGE
1760{
1761 /** AVL node code with the (R3) physical address of this page. */
1762 AVLOHCPHYSNODECORE Core;
1763 /** Pointer to the R3 mapping of the page. */
1764#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1765 R3PTRTYPE(void *) pvPageR3;
1766#else
1767 R3R0PTRTYPE(void *) pvPageR3;
1768#endif
1769 /** The guest physical address. */
1770#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1771 uint32_t Alignment0;
1772#endif
1773 RTGCPHYS GCPhys;
1774
1775 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1776 RTGCPTR pvLastAccessHandlerRip;
1777 RTGCPTR pvLastAccessHandlerFault;
1778 uint64_t cLastAccessHandlerCount;
1779
1780 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1781 uint8_t enmKind;
1782 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1783 uint8_t enmAccess;
1784 /** The index of this page. */
1785 uint16_t idx;
1786 /** The next entry in the list this page currently resides in.
1787 * It's either in the free list or in the GCPhys hash. */
1788 uint16_t iNext;
1789 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1790 uint16_t iUserHead;
1791 /** The number of present entries. */
1792 uint16_t cPresent;
1793 /** The first entry in the table which is present. */
1794 uint16_t iFirstPresent;
1795 /** The number of modifications to the monitored page. */
1796 uint16_t cModifications;
1797 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1798 uint16_t iModifiedNext;
1799 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1800 uint16_t iModifiedPrev;
1801 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1802 uint16_t iMonitoredNext;
1803 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1804 uint16_t iMonitoredPrev;
1805 /** The next page in the age list. */
1806 uint16_t iAgeNext;
1807 /** The previous page in the age list. */
1808 uint16_t iAgePrev;
1809 /** Used to indicate that the page is zeroed. */
1810 bool fZeroed;
1811 /** Used to indicate that a PT has non-global entries. */
1812 bool fSeenNonGlobal;
1813 /** Used to indicate that we're monitoring writes to the guest page. */
1814 bool fMonitored;
1815 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1816 * (All pages are in the age list.) */
1817 bool fCached;
1818 /** This is used by the R3 access handlers when invoked by an async thread.
1819 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1820 bool volatile fReusedFlushPending;
1821 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1822 bool fDirty;
1823
1824 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1825 uint32_t cLocked;
1826 uint32_t idxDirty;
1827 RTGCPTR pvDirtyFault;
1828} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1829/** Pointer to a const pool page. */
1830typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1831
1832
1833/** The hash table size. */
1834# define PGMPOOL_HASH_SIZE 0x40
1835/** The hash function. */
1836# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1837
1838
1839/**
1840 * The shadow page pool instance data.
1841 *
1842 * It's all one big allocation made at init time, except for the
1843 * pages that is. The user nodes follows immediatly after the
1844 * page structures.
1845 */
1846typedef struct PGMPOOL
1847{
1848 /** The VM handle - R3 Ptr. */
1849 PVMR3 pVMR3;
1850 /** The VM handle - R0 Ptr. */
1851 PVMR0 pVMR0;
1852 /** The VM handle - RC Ptr. */
1853 PVMRC pVMRC;
1854 /** The max pool size. This includes the special IDs. */
1855 uint16_t cMaxPages;
1856 /** The current pool size. */
1857 uint16_t cCurPages;
1858 /** The head of the free page list. */
1859 uint16_t iFreeHead;
1860 /* Padding. */
1861 uint16_t u16Padding;
1862 /** Head of the chain of free user nodes. */
1863 uint16_t iUserFreeHead;
1864 /** The number of user nodes we've allocated. */
1865 uint16_t cMaxUsers;
1866 /** The number of present page table entries in the entire pool. */
1867 uint32_t cPresent;
1868 /** Pointer to the array of user nodes - RC pointer. */
1869 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1870 /** Pointer to the array of user nodes - R3 pointer. */
1871 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1872 /** Pointer to the array of user nodes - R0 pointer. */
1873 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1874 /** Head of the chain of free phys ext nodes. */
1875 uint16_t iPhysExtFreeHead;
1876 /** The number of user nodes we've allocated. */
1877 uint16_t cMaxPhysExts;
1878 /** Pointer to the array of physical xref extent - RC pointer. */
1879 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1880 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1881 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1882 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1883 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1884 /** Hash table for GCPhys addresses. */
1885 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1886 /** The head of the age list. */
1887 uint16_t iAgeHead;
1888 /** The tail of the age list. */
1889 uint16_t iAgeTail;
1890 /** Set if the cache is enabled. */
1891 bool fCacheEnabled;
1892 /** Alignment padding. */
1893 bool afPadding1[3];
1894 /** Head of the list of modified pages. */
1895 uint16_t iModifiedHead;
1896 /** The current number of modified pages. */
1897 uint16_t cModifiedPages;
1898 /** Access handler, RC. */
1899 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1900 /** Access handler, R0. */
1901 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1902 /** Access handler, R3. */
1903 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1904 /** The access handler description (R3 ptr). */
1905 R3PTRTYPE(const char *) pszAccessHandler;
1906# if HC_ARCH_BITS == 32
1907 /** Alignment padding. */
1908 uint32_t u32Padding2;
1909# endif
1910 /* Next available slot. */
1911 uint32_t idxFreeDirtyPage;
1912 /* Number of active dirty pages. */
1913 uint32_t cDirtyPages;
1914 /* Array of current dirty pgm pool page indices. */
1915 uint16_t aIdxDirtyPages[16];
1916 uint64_t aDirtyPages[16][512];
1917 /** The number of pages currently in use. */
1918 uint16_t cUsedPages;
1919#ifdef VBOX_WITH_STATISTICS
1920 /** The high water mark for cUsedPages. */
1921 uint16_t cUsedPagesHigh;
1922 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1923 /** Profiling pgmPoolAlloc(). */
1924 STAMPROFILEADV StatAlloc;
1925 /** Profiling pgmR3PoolClearDoIt(). */
1926 STAMPROFILE StatClearAll;
1927 /** Profiling pgmR3PoolReset(). */
1928 STAMPROFILE StatR3Reset;
1929 /** Profiling pgmPoolFlushPage(). */
1930 STAMPROFILE StatFlushPage;
1931 /** Profiling pgmPoolFree(). */
1932 STAMPROFILE StatFree;
1933 /** Counting explicit flushes by PGMPoolFlushPage(). */
1934 STAMCOUNTER StatForceFlushPage;
1935 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1936 STAMCOUNTER StatForceFlushDirtyPage;
1937 /** Counting flushes for reused pages. */
1938 STAMCOUNTER StatForceFlushReused;
1939 /** Profiling time spent zeroing pages. */
1940 STAMPROFILE StatZeroPage;
1941 /** Profiling of pgmPoolTrackDeref. */
1942 STAMPROFILE StatTrackDeref;
1943 /** Profiling pgmTrackFlushGCPhysPT. */
1944 STAMPROFILE StatTrackFlushGCPhysPT;
1945 /** Profiling pgmTrackFlushGCPhysPTs. */
1946 STAMPROFILE StatTrackFlushGCPhysPTs;
1947 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1948 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1949 /** Number of times we've been out of user records. */
1950 STAMCOUNTER StatTrackFreeUpOneUser;
1951 /** Nr of flushed entries. */
1952 STAMCOUNTER StatTrackFlushEntry;
1953 /** Nr of updated entries. */
1954 STAMCOUNTER StatTrackFlushEntryKeep;
1955 /** Profiling deref activity related tracking GC physical pages. */
1956 STAMPROFILE StatTrackDerefGCPhys;
1957 /** Number of linear searches for a HCPhys in the ram ranges. */
1958 STAMCOUNTER StatTrackLinearRamSearches;
1959 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1960 STAMCOUNTER StamTrackPhysExtAllocFailures;
1961 /** Profiling the RC/R0 access handler. */
1962 STAMPROFILE StatMonitorRZ;
1963 /** Times we've failed interpreting the instruction. */
1964 STAMCOUNTER StatMonitorRZEmulateInstr;
1965 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1966 STAMPROFILE StatMonitorRZFlushPage;
1967 /* Times we've detected a page table reinit. */
1968 STAMCOUNTER StatMonitorRZFlushReinit;
1969 /** Counting flushes for pages that are modified too often. */
1970 STAMCOUNTER StatMonitorRZFlushModOverflow;
1971 /** Times we've detected fork(). */
1972 STAMCOUNTER StatMonitorRZFork;
1973 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1974 STAMPROFILE StatMonitorRZHandled;
1975 /** Times we've failed interpreting a patch code instruction. */
1976 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1977 /** Times we've failed interpreting a patch code instruction during flushing. */
1978 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1979 /** The number of times we've seen rep prefixes we can't handle. */
1980 STAMCOUNTER StatMonitorRZRepPrefix;
1981 /** Profiling the REP STOSD cases we've handled. */
1982 STAMPROFILE StatMonitorRZRepStosd;
1983 /** Nr of handled PT faults. */
1984 STAMCOUNTER StatMonitorRZFaultPT;
1985 /** Nr of handled PD faults. */
1986 STAMCOUNTER StatMonitorRZFaultPD;
1987 /** Nr of handled PDPT faults. */
1988 STAMCOUNTER StatMonitorRZFaultPDPT;
1989 /** Nr of handled PML4 faults. */
1990 STAMCOUNTER StatMonitorRZFaultPML4;
1991
1992 /** Profiling the R3 access handler. */
1993 STAMPROFILE StatMonitorR3;
1994 /** Times we've failed interpreting the instruction. */
1995 STAMCOUNTER StatMonitorR3EmulateInstr;
1996 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1997 STAMPROFILE StatMonitorR3FlushPage;
1998 /* Times we've detected a page table reinit. */
1999 STAMCOUNTER StatMonitorR3FlushReinit;
2000 /** Counting flushes for pages that are modified too often. */
2001 STAMCOUNTER StatMonitorR3FlushModOverflow;
2002 /** Times we've detected fork(). */
2003 STAMCOUNTER StatMonitorR3Fork;
2004 /** Profiling the R3 access we've handled (except REP STOSD). */
2005 STAMPROFILE StatMonitorR3Handled;
2006 /** The number of times we've seen rep prefixes we can't handle. */
2007 STAMCOUNTER StatMonitorR3RepPrefix;
2008 /** Profiling the REP STOSD cases we've handled. */
2009 STAMPROFILE StatMonitorR3RepStosd;
2010 /** Nr of handled PT faults. */
2011 STAMCOUNTER StatMonitorR3FaultPT;
2012 /** Nr of handled PD faults. */
2013 STAMCOUNTER StatMonitorR3FaultPD;
2014 /** Nr of handled PDPT faults. */
2015 STAMCOUNTER StatMonitorR3FaultPDPT;
2016 /** Nr of handled PML4 faults. */
2017 STAMCOUNTER StatMonitorR3FaultPML4;
2018 /** The number of times we're called in an async thread an need to flush. */
2019 STAMCOUNTER StatMonitorR3Async;
2020 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2021 STAMCOUNTER StatResetDirtyPages;
2022 /** Times we've called pgmPoolAddDirtyPage. */
2023 STAMCOUNTER StatDirtyPage;
2024 /** Times we've had to flush duplicates for dirty page management. */
2025 STAMCOUNTER StatDirtyPageDupFlush;
2026 /** Times we've had to flush because of overflow. */
2027 STAMCOUNTER StatDirtyPageOverFlowFlush;
2028
2029 /** The high wather mark for cModifiedPages. */
2030 uint16_t cModifiedPagesHigh;
2031 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2032
2033 /** The number of cache hits. */
2034 STAMCOUNTER StatCacheHits;
2035 /** The number of cache misses. */
2036 STAMCOUNTER StatCacheMisses;
2037 /** The number of times we've got a conflict of 'kind' in the cache. */
2038 STAMCOUNTER StatCacheKindMismatches;
2039 /** Number of times we've been out of pages. */
2040 STAMCOUNTER StatCacheFreeUpOne;
2041 /** The number of cacheable allocations. */
2042 STAMCOUNTER StatCacheCacheable;
2043 /** The number of uncacheable allocations. */
2044 STAMCOUNTER StatCacheUncacheable;
2045#else
2046 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2047#endif
2048 /** The AVL tree for looking up a page by its HC physical address. */
2049 AVLOHCPHYSTREE HCPhysTree;
2050 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2051 /** Array of pages. (cMaxPages in length)
2052 * The Id is the index into thist array.
2053 */
2054 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2055} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2056AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2057AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2058AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2059#ifdef VBOX_WITH_STATISTICS
2060AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2061#endif
2062AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2063
2064
2065/** @def PGMPOOL_PAGE_2_PTR
2066 * Maps a pool page pool into the current context.
2067 *
2068 * @returns VBox status code.
2069 * @param pVM The VM handle.
2070 * @param pPage The pool page.
2071 *
2072 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2073 * small page window employeed by that function. Be careful.
2074 * @remark There is no need to assert on the result.
2075 */
2076#if defined(IN_RC)
2077# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2078#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2079# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2080#elif defined(VBOX_STRICT)
2081# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2082DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2083{
2084 Assert(pPage && pPage->pvPageR3);
2085 return pPage->pvPageR3;
2086}
2087#else
2088# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2089#endif
2090
2091/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2092 * Maps a pool page pool into the current context.
2093 *
2094 * @returns VBox status code.
2095 * @param pPGM Pointer to the PGM instance data.
2096 * @param pPage The pool page.
2097 *
2098 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2099 * small page window employeed by that function. Be careful.
2100 * @remark There is no need to assert on the result.
2101 */
2102#if defined(IN_RC)
2103# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2104#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2105# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2106#else
2107# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2108#endif
2109
2110/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2111 * Maps a pool page pool into the current context.
2112 *
2113 * @returns VBox status code.
2114 * @param pPGM Pointer to the PGMCPU instance data.
2115 * @param pPage The pool page.
2116 *
2117 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2118 * small page window employeed by that function. Be careful.
2119 * @remark There is no need to assert on the result.
2120 */
2121#if defined(IN_RC)
2122# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2123#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2124# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2125#else
2126# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2127#endif
2128
2129
2130/** @name Per guest page tracking data.
2131 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2132 * is to use more bits for it and split it up later on. But for now we'll play
2133 * safe and change as little as possible.
2134 *
2135 * The 16-bit word has two parts:
2136 *
2137 * The first 14-bit forms the @a idx field. It is either the index of a page in
2138 * the shadow page pool, or and index into the extent list.
2139 *
2140 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2141 * shadow page pool references to the page. If cRefs equals
2142 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2143 * (misnomer) table and not the shadow page pool.
2144 *
2145 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2146 * the 16-bit word.
2147 *
2148 * @{ */
2149/** The shift count for getting to the cRefs part. */
2150#define PGMPOOL_TD_CREFS_SHIFT 14
2151/** The mask applied after shifting the tracking data down by
2152 * PGMPOOL_TD_CREFS_SHIFT. */
2153#define PGMPOOL_TD_CREFS_MASK 0x3
2154/** The cRef value used to indiciate that the idx is the head of a
2155 * physical cross reference list. */
2156#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2157/** The shift used to get idx. */
2158#define PGMPOOL_TD_IDX_SHIFT 0
2159/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2160#define PGMPOOL_TD_IDX_MASK 0x3fff
2161/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2162 * simply too many mappings of this page. */
2163#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2164
2165/** @def PGMPOOL_TD_MAKE
2166 * Makes a 16-bit tracking data word.
2167 *
2168 * @returns tracking data.
2169 * @param cRefs The @a cRefs field. Must be within bounds!
2170 * @param idx The @a idx field. Must also be within bounds! */
2171#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2172
2173/** @def PGMPOOL_TD_GET_CREFS
2174 * Get the @a cRefs field from a tracking data word.
2175 *
2176 * @returns The @a cRefs field
2177 * @param u16 The tracking data word. */
2178#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2179
2180/** @def PGMPOOL_TD_GET_IDX
2181 * Get the @a idx field from a tracking data word.
2182 *
2183 * @returns The @a idx field
2184 * @param u16 The tracking data word. */
2185#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2186/** @} */
2187
2188
2189/**
2190 * Trees are using self relative offsets as pointers.
2191 * So, all its data, including the root pointer, must be in the heap for HC and GC
2192 * to have the same layout.
2193 */
2194typedef struct PGMTREES
2195{
2196 /** Physical access handlers (AVL range+offsetptr tree). */
2197 AVLROGCPHYSTREE PhysHandlers;
2198 /** Virtual access handlers (AVL range + GC ptr tree). */
2199 AVLROGCPTRTREE VirtHandlers;
2200 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2201 AVLROGCPHYSTREE PhysToVirtHandlers;
2202 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2203 AVLROGCPTRTREE HyperVirtHandlers;
2204} PGMTREES;
2205/** Pointer to PGM trees. */
2206typedef PGMTREES *PPGMTREES;
2207
2208
2209/** @name Paging mode macros
2210 * @{ */
2211#ifdef IN_RC
2212# define PGM_CTX(a,b) a##RC##b
2213# define PGM_CTX_STR(a,b) a "GC" b
2214# define PGM_CTX_DECL(type) VMMRCDECL(type)
2215#else
2216# ifdef IN_RING3
2217# define PGM_CTX(a,b) a##R3##b
2218# define PGM_CTX_STR(a,b) a "R3" b
2219# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2220# else
2221# define PGM_CTX(a,b) a##R0##b
2222# define PGM_CTX_STR(a,b) a "R0" b
2223# define PGM_CTX_DECL(type) VMMDECL(type)
2224# endif
2225#endif
2226
2227#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2228#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2229#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2230#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2231#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2232#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2233#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2234#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2235#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2236#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2237#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2238#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2239#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2240#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2241#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2242#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2243#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2244
2245#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2246#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2247#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2248#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2249#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2250#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2251#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2252#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2253#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2254#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2255#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2256#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2257#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2258#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2259#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2260#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2261#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2262
2263/* Shw_Gst */
2264#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2265#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2266#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2267#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2268#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2269#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2270#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2271#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2272#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2273#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2274#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2275#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2276#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2277#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2278#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2279#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2280#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2281#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2282#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2283
2284#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2285#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2286#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2287#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2288#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2289#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2290#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2291#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2292#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2293#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2294#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2295#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2296#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2297#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2298#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2299#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2300#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2301#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2302#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2303#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2304#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2305#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2306#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2307#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2308#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2309#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2310#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2311#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2312#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2313#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2314#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2315#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2316#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2317#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2318#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2319#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2320#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2321
2322#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2323#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2324/** @} */
2325
2326/**
2327 * Data for each paging mode.
2328 */
2329typedef struct PGMMODEDATA
2330{
2331 /** The guest mode type. */
2332 uint32_t uGstType;
2333 /** The shadow mode type. */
2334 uint32_t uShwType;
2335
2336 /** @name Function pointers for Shadow paging.
2337 * @{
2338 */
2339 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2340 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2341 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2342 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2343
2344 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2345 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2346
2347 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2348 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2349 /** @} */
2350
2351 /** @name Function pointers for Guest paging.
2352 * @{
2353 */
2354 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2355 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2356 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2357 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2358 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2359 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2360 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2361 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2362 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2363 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2364 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2365 /** @} */
2366
2367 /** @name Function pointers for Both Shadow and Guest paging.
2368 * @{
2369 */
2370 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2371 /* no pfnR3BthTrap0eHandler */
2372 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2373 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2374 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2375 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2376 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2377#ifdef VBOX_STRICT
2378 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2379#endif
2380 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2381 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2382
2383 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2384 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2385 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2386 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2387 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2388 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2389#ifdef VBOX_STRICT
2390 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2391#endif
2392 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2393 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2394
2395 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2396 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2397 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2398 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2399 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2400 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2401#ifdef VBOX_STRICT
2402 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2403#endif
2404 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2405 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2406 /** @} */
2407} PGMMODEDATA, *PPGMMODEDATA;
2408
2409
2410
2411/**
2412 * Converts a PGM pointer into a VM pointer.
2413 * @returns Pointer to the VM structure the PGM is part of.
2414 * @param pPGM Pointer to PGM instance data.
2415 */
2416#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2417
2418/**
2419 * PGM Data (part of VM)
2420 */
2421typedef struct PGM
2422{
2423 /** Offset to the VM structure. */
2424 RTINT offVM;
2425 /** Offset of the PGMCPU structure relative to VMCPU. */
2426 RTINT offVCpuPGM;
2427
2428 /** @cfgm{RamPreAlloc, boolean, false}
2429 * Indicates whether the base RAM should all be allocated before starting
2430 * the VM (default), or if it should be allocated when first written to.
2431 */
2432 bool fRamPreAlloc;
2433 /** Indicates whether write monitoring is currently in use.
2434 * This is used to prevent conflicts between live saving and page sharing
2435 * detection. */
2436 bool fPhysWriteMonitoringEngaged;
2437 /** Alignment padding. */
2438 bool afAlignment0[2];
2439
2440 /*
2441 * This will be redefined at least two more times before we're done, I'm sure.
2442 * The current code is only to get on with the coding.
2443 * - 2004-06-10: initial version, bird.
2444 * - 2004-07-02: 1st time, bird.
2445 * - 2004-10-18: 2nd time, bird.
2446 * - 2005-07-xx: 3rd time, bird.
2447 */
2448
2449 /** The host paging mode. (This is what SUPLib reports.) */
2450 SUPPAGINGMODE enmHostMode;
2451
2452 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2453 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2454 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2455 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2456
2457 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2458 RTGCPHYS GCPhys4MBPSEMask;
2459
2460 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2461 * This is sorted by physical address and contains no overlapping ranges. */
2462 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2463 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2464 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2465 /** RC pointer corresponding to PGM::pRamRangesR3. */
2466 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2467 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2468 * range is linked or unlinked. */
2469 uint32_t volatile idRamRangesGen;
2470
2471 /** Pointer to the list of ROM ranges - for R3.
2472 * This is sorted by physical address and contains no overlapping ranges. */
2473 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2474 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2475 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2476 /** RC pointer corresponding to PGM::pRomRangesR3. */
2477 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2478#if HC_ARCH_BITS == 64
2479 /** Alignment padding. */
2480 RTRCPTR GCPtrPadding2;
2481#endif
2482
2483 /** Pointer to the list of MMIO2 ranges - for R3.
2484 * Registration order. */
2485 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2486
2487 /** PGM offset based trees - R3 Ptr. */
2488 R3PTRTYPE(PPGMTREES) pTreesR3;
2489 /** PGM offset based trees - R0 Ptr. */
2490 R0PTRTYPE(PPGMTREES) pTreesR0;
2491 /** PGM offset based trees - RC Ptr. */
2492 RCPTRTYPE(PPGMTREES) pTreesRC;
2493
2494 /** Linked list of GC mappings - for RC.
2495 * The list is sorted ascending on address.
2496 */
2497 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2498 /** Linked list of GC mappings - for HC.
2499 * The list is sorted ascending on address.
2500 */
2501 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2502 /** Linked list of GC mappings - for R0.
2503 * The list is sorted ascending on address.
2504 */
2505 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2506
2507 /** Pointer to the 5 page CR3 content mapping.
2508 * The first page is always the CR3 (in some form) while the 4 other pages
2509 * are used of the PDs in PAE mode. */
2510 RTGCPTR GCPtrCR3Mapping;
2511#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2512 uint32_t u32Alignment1;
2513#endif
2514
2515 /** Indicates that PGMR3FinalizeMappings has been called and that further
2516 * PGMR3MapIntermediate calls will be rejected. */
2517 bool fFinalizedMappings;
2518 /** If set no conflict checks are required. (boolean) */
2519 bool fMappingsFixed;
2520 /** If set, then no mappings are put into the shadow page table. (boolean) */
2521 bool fDisableMappings;
2522 /** Size of fixed mapping */
2523 uint32_t cbMappingFixed;
2524 /** Base address (GC) of fixed mapping */
2525 RTGCPTR GCPtrMappingFixed;
2526 /** The address of the previous RAM range mapping. */
2527 RTGCPTR GCPtrPrevRamRangeMapping;
2528
2529 /** @name Intermediate Context
2530 * @{ */
2531 /** Pointer to the intermediate page directory - Normal. */
2532 R3PTRTYPE(PX86PD) pInterPD;
2533 /** Pointer to the intermedate page tables - Normal.
2534 * There are two page tables, one for the identity mapping and one for
2535 * the host context mapping (of the core code). */
2536 R3PTRTYPE(PX86PT) apInterPTs[2];
2537 /** Pointer to the intermedate page tables - PAE. */
2538 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2539 /** Pointer to the intermedate page directory - PAE. */
2540 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2541 /** Pointer to the intermedate page directory - PAE. */
2542 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2543 /** Pointer to the intermedate page-map level 4 - AMD64. */
2544 R3PTRTYPE(PX86PML4) pInterPaePML4;
2545 /** Pointer to the intermedate page directory - AMD64. */
2546 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2547 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2548 RTHCPHYS HCPhysInterPD;
2549 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2550 RTHCPHYS HCPhysInterPaePDPT;
2551 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2552 RTHCPHYS HCPhysInterPaePML4;
2553 /** @} */
2554
2555 /** Base address of the dynamic page mapping area.
2556 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2557 */
2558 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2559 /** The index of the last entry used in the dynamic page mapping area. */
2560 RTUINT iDynPageMapLast;
2561 /** Cache containing the last entries in the dynamic page mapping area.
2562 * The cache size is covering half of the mapping area. */
2563 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2564 /** Keep a lock counter for the full (!) mapping area. */
2565 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2566
2567 /** The address of the ring-0 mapping cache if we're making use of it. */
2568 RTR0PTR pvR0DynMapUsed;
2569#if HC_ARCH_BITS == 32
2570 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2571 uint32_t u32Alignment2;
2572#endif
2573
2574 /** PGM critical section.
2575 * This protects the physical & virtual access handlers, ram ranges,
2576 * and the page flag updating (some of it anyway).
2577 */
2578 PDMCRITSECT CritSect;
2579
2580 /** Pointer to SHW+GST mode data (function pointers).
2581 * The index into this table is made up from */
2582 R3PTRTYPE(PPGMMODEDATA) paModeData;
2583
2584 /** Shadow Page Pool - R3 Ptr. */
2585 R3PTRTYPE(PPGMPOOL) pPoolR3;
2586 /** Shadow Page Pool - R0 Ptr. */
2587 R0PTRTYPE(PPGMPOOL) pPoolR0;
2588 /** Shadow Page Pool - RC Ptr. */
2589 RCPTRTYPE(PPGMPOOL) pPoolRC;
2590
2591 /** We're not in a state which permits writes to guest memory.
2592 * (Only used in strict builds.) */
2593 bool fNoMorePhysWrites;
2594 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2595 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2596
2597 /**
2598 * Data associated with managing the ring-3 mappings of the allocation chunks.
2599 */
2600 struct
2601 {
2602 /** The chunk tree, ordered by chunk id. */
2603#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2604 R3PTRTYPE(PAVLU32NODECORE) pTree;
2605#else
2606 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2607#endif
2608 /** The chunk age tree, ordered by ageing sequence number. */
2609 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2610 /** The chunk mapping TLB. */
2611 PGMCHUNKR3MAPTLB Tlb;
2612 /** The number of mapped chunks. */
2613 uint32_t c;
2614 /** The maximum number of mapped chunks.
2615 * @cfgm PGM/MaxRing3Chunks */
2616 uint32_t cMax;
2617 /** The current time. */
2618 uint32_t iNow;
2619 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2620 uint32_t AgeingCountdown;
2621 } ChunkR3Map;
2622
2623 /**
2624 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2625 */
2626 PGMPAGER3MAPTLB PhysTlbHC;
2627
2628 /** @name The zero page.
2629 * @{ */
2630 /** The host physical address of the zero page. */
2631 RTHCPHYS HCPhysZeroPg;
2632 /** The ring-3 mapping of the zero page. */
2633 RTR3PTR pvZeroPgR3;
2634 /** The ring-0 mapping of the zero page. */
2635 RTR0PTR pvZeroPgR0;
2636 /** The GC mapping of the zero page. */
2637 RTGCPTR pvZeroPgRC;
2638#if GC_ARCH_BITS != 32
2639 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2640#endif
2641 /** @}*/
2642
2643 /** The number of handy pages. */
2644 uint32_t cHandyPages;
2645 /**
2646 * Array of handy pages.
2647 *
2648 * This array is used in a two way communication between pgmPhysAllocPage
2649 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2650 * an intermediary.
2651 *
2652 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2653 * (The current size of 32 pages, means 128 KB of handy memory.)
2654 */
2655 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2656
2657 /**
2658 * Live save data.
2659 */
2660 struct
2661 {
2662 /** Per type statistics. */
2663 struct
2664 {
2665 /** The number of ready pages. */
2666 uint32_t cReadyPages;
2667 /** The number of dirty pages. */
2668 uint32_t cDirtyPages;
2669 /** The number of ready zero pages. */
2670 uint32_t cZeroPages;
2671 /** The number of write monitored pages. */
2672 uint32_t cMonitoredPages;
2673 } Rom,
2674 Mmio2,
2675 Ram;
2676 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2677 uint32_t cIgnoredPages;
2678 /** Indicates that a live save operation is active. */
2679 bool fActive;
2680 /** Padding. */
2681 bool afReserved[2];
2682 /** The next history index. */
2683 uint8_t iDirtyPagesHistory;
2684 /** History of the total amount of dirty pages. */
2685 uint32_t acDirtyPagesHistory[64];
2686 /** Short term dirty page average. */
2687 uint32_t cDirtyPagesShort;
2688 /** Long term dirty page average. */
2689 uint32_t cDirtyPagesLong;
2690 /** The number of saved pages. This is used to get some kind of estimate of the
2691 * link speed so we can decide when we're done. It is reset after the first
2692 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2693 * zero pages. */
2694 uint64_t cSavedPages;
2695 /** The nanosecond timestamp when cSavedPages was 0. */
2696 uint64_t uSaveStartNS;
2697 /** Pages per second (for statistics). */
2698 uint32_t cPagesPerSecond;
2699 uint32_t cAlignment;
2700 } LiveSave;
2701
2702 /** @name Error injection.
2703 * @{ */
2704 /** Inject handy page allocation errors pretending we're completely out of
2705 * memory. */
2706 bool volatile fErrInjHandyPages;
2707 /** Padding. */
2708 bool afReserved[7];
2709 /** @} */
2710
2711 /** @name Release Statistics
2712 * @{ */
2713 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2714 uint32_t cPrivatePages; /**< The number of private pages. */
2715 uint32_t cSharedPages; /**< The number of shared pages. */
2716 uint32_t cZeroPages; /**< The number of zero backed pages. */
2717 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2718 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2719 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2720 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2721
2722 /** The number of times we were forced to change the hypervisor region location. */
2723 STAMCOUNTER cRelocations;
2724 /** @} */
2725
2726#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2727 /* R3 only: */
2728 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2729 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2730
2731 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2732 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2733 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2734 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2735 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2736 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2737 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2738 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2739 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2740 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2741 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2742 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2743 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2744 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2745 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2746 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2747 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2748 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2749 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2750 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2751/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2752 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2753 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2754/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2755
2756 /* RC only: */
2757 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2758 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2759 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2760 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2761
2762 STAMCOUNTER StatRZPhysRead;
2763 STAMCOUNTER StatRZPhysReadBytes;
2764 STAMCOUNTER StatRZPhysWrite;
2765 STAMCOUNTER StatRZPhysWriteBytes;
2766 STAMCOUNTER StatR3PhysRead;
2767 STAMCOUNTER StatR3PhysReadBytes;
2768 STAMCOUNTER StatR3PhysWrite;
2769 STAMCOUNTER StatR3PhysWriteBytes;
2770 STAMCOUNTER StatRCPhysRead;
2771 STAMCOUNTER StatRCPhysReadBytes;
2772 STAMCOUNTER StatRCPhysWrite;
2773 STAMCOUNTER StatRCPhysWriteBytes;
2774
2775 STAMCOUNTER StatRZPhysSimpleRead;
2776 STAMCOUNTER StatRZPhysSimpleReadBytes;
2777 STAMCOUNTER StatRZPhysSimpleWrite;
2778 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2779 STAMCOUNTER StatR3PhysSimpleRead;
2780 STAMCOUNTER StatR3PhysSimpleReadBytes;
2781 STAMCOUNTER StatR3PhysSimpleWrite;
2782 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2783 STAMCOUNTER StatRCPhysSimpleRead;
2784 STAMCOUNTER StatRCPhysSimpleReadBytes;
2785 STAMCOUNTER StatRCPhysSimpleWrite;
2786 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2787
2788 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2789 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2790 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2791 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2792 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2793 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2794#endif
2795} PGM;
2796#ifndef IN_TSTVMSTRUCTGC /* HACK */
2797AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2798AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2799AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2800AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2801AssertCompileMemberAlignment(PGM, CritSect, 8);
2802AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2803AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2804AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2805AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2806AssertCompileMemberAlignment(PGM, cRelocations, 8);
2807#endif /* !IN_TSTVMSTRUCTGC */
2808/** Pointer to the PGM instance data. */
2809typedef PGM *PPGM;
2810
2811
2812/**
2813 * Converts a PGMCPU pointer into a VM pointer.
2814 * @returns Pointer to the VM structure the PGM is part of.
2815 * @param pPGM Pointer to PGMCPU instance data.
2816 */
2817#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2818
2819/**
2820 * Converts a PGMCPU pointer into a PGM pointer.
2821 * @returns Pointer to the VM structure the PGM is part of.
2822 * @param pPGM Pointer to PGMCPU instance data.
2823 */
2824#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2825
2826/**
2827 * PGMCPU Data (part of VMCPU).
2828 */
2829typedef struct PGMCPU
2830{
2831 /** Offset to the VM structure. */
2832 RTINT offVM;
2833 /** Offset to the VMCPU structure. */
2834 RTINT offVCpu;
2835 /** Offset of the PGM structure relative to VMCPU. */
2836 RTINT offPGM;
2837 RTINT uPadding0; /**< structure size alignment. */
2838
2839#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2840 /** Automatically tracked physical memory mapping set.
2841 * Ring-0 and strict raw-mode builds. */
2842 PGMMAPSET AutoSet;
2843#endif
2844
2845 /** A20 gate mask.
2846 * Our current approach to A20 emulation is to let REM do it and don't bother
2847 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2848 * But whould need arrise, we'll subject physical addresses to this mask. */
2849 RTGCPHYS GCPhysA20Mask;
2850 /** A20 gate state - boolean! */
2851 bool fA20Enabled;
2852
2853 /** What needs syncing (PGM_SYNC_*).
2854 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2855 * PGMFlushTLB, and PGMR3Load. */
2856 RTUINT fSyncFlags;
2857
2858 /** The shadow paging mode. */
2859 PGMMODE enmShadowMode;
2860 /** The guest paging mode. */
2861 PGMMODE enmGuestMode;
2862
2863 /** The current physical address representing in the guest CR3 register. */
2864 RTGCPHYS GCPhysCR3;
2865
2866 /** @name 32-bit Guest Paging.
2867 * @{ */
2868 /** The guest's page directory, R3 pointer. */
2869 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2870#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2871 /** The guest's page directory, R0 pointer. */
2872 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2873#endif
2874 /** The guest's page directory, static RC mapping. */
2875 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2876 /** @} */
2877
2878 /** @name PAE Guest Paging.
2879 * @{ */
2880 /** The guest's page directory pointer table, static RC mapping. */
2881 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2882 /** The guest's page directory pointer table, R3 pointer. */
2883 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2884#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2885 /** The guest's page directory pointer table, R0 pointer. */
2886 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2887#endif
2888
2889 /** The guest's page directories, R3 pointers.
2890 * These are individual pointers and don't have to be adjecent.
2891 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2892 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2893 /** The guest's page directories, R0 pointers.
2894 * Same restrictions as apGstPaePDsR3. */
2895#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2896 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2897#endif
2898 /** The guest's page directories, static GC mapping.
2899 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2900 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2901 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2902 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2903 RTGCPHYS aGCPhysGstPaePDs[4];
2904 /** The physical addresses of the monitored guest page directories (PAE). */
2905 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2906 /** @} */
2907
2908 /** @name AMD64 Guest Paging.
2909 * @{ */
2910 /** The guest's page directory pointer table, R3 pointer. */
2911 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2912#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2913 /** The guest's page directory pointer table, R0 pointer. */
2914 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2915#else
2916 RTR0PTR alignment6b; /**< alignment equalizer. */
2917#endif
2918 /** @} */
2919
2920 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2921 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2922 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2923 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2924 /** Pointer to the page of the current active CR3 - RC Ptr. */
2925 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2926 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2927 uint32_t iShwUser;
2928 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2929 uint32_t iShwUserTable;
2930# if HC_ARCH_BITS == 64
2931 RTRCPTR alignment6; /**< structure size alignment. */
2932# endif
2933 /** @} */
2934
2935 /** @name Function pointers for Shadow paging.
2936 * @{
2937 */
2938 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2939 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2940 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2941 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2942
2943 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2944 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2945
2946 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2947 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2948
2949 /** @} */
2950
2951 /** @name Function pointers for Guest paging.
2952 * @{
2953 */
2954 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2955 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2956 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2957 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2958 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2959 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2960 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2961 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2962#if HC_ARCH_BITS == 64
2963 RTRCPTR alignment3; /**< structure size alignment. */
2964#endif
2965
2966 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2967 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2968 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2969 /** @} */
2970
2971 /** @name Function pointers for Both Shadow and Guest paging.
2972 * @{
2973 */
2974 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2975 /* no pfnR3BthTrap0eHandler */
2976 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2977 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2978 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2979 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2980 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2981 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2982 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2983 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2984
2985 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2986 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2987 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2988 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2989 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2990 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2991 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2992 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2993 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2994
2995 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2996 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2997 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2998 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2999 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3000 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3001 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3002 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3003 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3004 RTRCPTR alignment2; /**< structure size alignment. */
3005 /** @} */
3006
3007 /** For saving stack space, the disassembler state is allocated here instead of
3008 * on the stack.
3009 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3010 union
3011 {
3012 /** The disassembler scratch space. */
3013 DISCPUSTATE DisState;
3014 /** Padding. */
3015 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3016 };
3017
3018 /* Count the number of pgm pool access handler calls. */
3019 uint64_t cPoolAccessHandler;
3020
3021 /** @name Release Statistics
3022 * @{ */
3023 /** The number of times the guest has switched mode since last reset or statistics reset. */
3024 STAMCOUNTER cGuestModeChanges;
3025 /** @} */
3026
3027#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3028 /** @name Statistics
3029 * @{ */
3030 /** RC: Which statistic this \#PF should be attributed to. */
3031 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3032 RTRCPTR padding0;
3033 /** R0: Which statistic this \#PF should be attributed to. */
3034 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3035 RTR0PTR padding1;
3036
3037 /* Common */
3038 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3039 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3040
3041 /* R0 only: */
3042 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3043 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3044 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3045 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3046 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3047 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3048 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3049 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3050 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3051 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3052 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3053 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3054 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3055 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3056 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3057 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3058 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3059 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3060 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3061 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3062 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3063 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3064 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3065 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3066 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3067 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3068
3069 /* RZ only: */
3070 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3071 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3072 STAMPROFILE StatRZTrap0eTimeSyncPT;
3073 STAMPROFILE StatRZTrap0eTimeMapping;
3074 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3075 STAMPROFILE StatRZTrap0eTimeHandlers;
3076 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3077 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3078 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3079 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3080 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3081 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3082 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3083 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3084 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3085 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3086 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3087 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3088 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3089 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3090 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3091 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3092 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3093 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3094 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3095 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3096 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3097 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3098 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3099 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3100 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3101 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3102 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3103 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3104 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3105 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3106 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3107 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3108 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3109 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3110 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3111 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3112 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3113 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3114 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3115 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3116 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3117 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3118 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3119
3120 /* HC - R3 and (maybe) R0: */
3121
3122 /* RZ & R3: */
3123 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3124 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3125 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3126 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3127 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3128 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3129 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3130 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3131 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3132 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3133 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3134 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3135 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3136 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3137 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3138 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3139 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3140 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3141 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3142 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3143 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3144 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3145 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3146 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3147 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3148 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3149 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3150 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3151 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3152 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3153 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3154 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3155 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3156 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3157 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3158 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3159 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3160 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3161 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3162 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3163 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3164 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3165 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3166 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3167 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3168 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3169
3170 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3171 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3172 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3173 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3174 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3175 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3176 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3177 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3178 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3179 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3180 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3181 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3182 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3183 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3184 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3185 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3186 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3187 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3188 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3189 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3190 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3191 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3192 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3193 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3194 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3195 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3196 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3197 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3198 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3199 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3200 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3201 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3202 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3203 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3204 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3205 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3206 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3207 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3208 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3209 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3210 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3211 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3212 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3213 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3214 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3215 /** @} */
3216#endif /* VBOX_WITH_STATISTICS */
3217} PGMCPU;
3218/** Pointer to the per-cpu PGM data. */
3219typedef PGMCPU *PPGMCPU;
3220
3221
3222/** @name PGM::fSyncFlags Flags
3223 * @{
3224 */
3225/** Updates the virtual access handler state bit in PGMPAGE. */
3226#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3227/** Always sync CR3. */
3228#define PGM_SYNC_ALWAYS RT_BIT(1)
3229/** Check monitoring on next CR3 (re)load and invalidate page.
3230 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3231#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3232/** Check guest mapping in SyncCR3. */
3233#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3234/** Clear the page pool (a light weight flush). */
3235#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3236#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3237/** @} */
3238
3239
3240RT_C_DECLS_BEGIN
3241
3242int pgmLock(PVM pVM);
3243void pgmUnlock(PVM pVM);
3244
3245int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3246int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3247PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3248void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3249DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3250
3251void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3252bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3253void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3254int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3255DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3256#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3257void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3258#else
3259# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3260#endif
3261DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3262int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3263
3264int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3265int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3266int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3267void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3268int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3269int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3270int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3271int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3272int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3273int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3274int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3275int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3276VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3277#ifdef IN_RING3
3278void pgmR3PhysRelinkRamRanges(PVM pVM);
3279int pgmR3PhysRamPreAllocate(PVM pVM);
3280int pgmR3PhysRamReset(PVM pVM);
3281int pgmR3PhysRomReset(PVM pVM);
3282int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3283
3284int pgmR3PoolInit(PVM pVM);
3285void pgmR3PoolRelocate(PVM pVM);
3286void pgmR3PoolReset(PVM pVM);
3287void pgmR3PoolResetCpu(PVM pVM, PVMCPU pVCpu);
3288void pgmR3PoolClearAll(PVM pVM);
3289
3290#endif /* IN_RING3 */
3291#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3292int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3293#endif
3294int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3295
3296DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3297{
3298 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3299}
3300
3301void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3302void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3303int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3304void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3305PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3306int pgmPoolSyncCR3(PVMCPU pVCpu);
3307bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3308int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3309void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3310DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3311{
3312 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3313}
3314
3315uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3316void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3317void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3318void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3319int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3320void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3321
3322void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3323void pgmPoolResetDirtyPages(PVM pVM);
3324
3325int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3326int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3327
3328void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3329void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3330int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3331int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3332
3333int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3334#ifndef IN_RC
3335int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3336#endif
3337int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3338
3339PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3340PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3341PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3342PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3343
3344RT_C_DECLS_END
3345
3346
3347/**
3348 * Gets the PGMRAMRANGE structure for a guest page.
3349 *
3350 * @returns Pointer to the RAM range on success.
3351 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3352 *
3353 * @param pPGM PGM handle.
3354 * @param GCPhys The GC physical address.
3355 */
3356DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3357{
3358 /*
3359 * Optimize for the first range.
3360 */
3361 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3362 RTGCPHYS off = GCPhys - pRam->GCPhys;
3363 if (RT_UNLIKELY(off >= pRam->cb))
3364 {
3365 do
3366 {
3367 pRam = pRam->CTX_SUFF(pNext);
3368 if (RT_UNLIKELY(!pRam))
3369 break;
3370 off = GCPhys - pRam->GCPhys;
3371 } while (off >= pRam->cb);
3372 }
3373 return pRam;
3374}
3375
3376
3377/**
3378 * Gets the PGMPAGE structure for a guest page.
3379 *
3380 * @returns Pointer to the page on success.
3381 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3382 *
3383 * @param pPGM PGM handle.
3384 * @param GCPhys The GC physical address.
3385 */
3386DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3387{
3388 /*
3389 * Optimize for the first range.
3390 */
3391 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3392 RTGCPHYS off = GCPhys - pRam->GCPhys;
3393 if (RT_UNLIKELY(off >= pRam->cb))
3394 {
3395 do
3396 {
3397 pRam = pRam->CTX_SUFF(pNext);
3398 if (RT_UNLIKELY(!pRam))
3399 return NULL;
3400 off = GCPhys - pRam->GCPhys;
3401 } while (off >= pRam->cb);
3402 }
3403 return &pRam->aPages[off >> PAGE_SHIFT];
3404}
3405
3406
3407/**
3408 * Gets the PGMPAGE structure for a guest page.
3409 *
3410 * Old Phys code: Will make sure the page is present.
3411 *
3412 * @returns VBox status code.
3413 * @retval VINF_SUCCESS and a valid *ppPage on success.
3414 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3415 *
3416 * @param pPGM PGM handle.
3417 * @param GCPhys The GC physical address.
3418 * @param ppPage Where to store the page pointer on success.
3419 */
3420DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3421{
3422 /*
3423 * Optimize for the first range.
3424 */
3425 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3426 RTGCPHYS off = GCPhys - pRam->GCPhys;
3427 if (RT_UNLIKELY(off >= pRam->cb))
3428 {
3429 do
3430 {
3431 pRam = pRam->CTX_SUFF(pNext);
3432 if (RT_UNLIKELY(!pRam))
3433 {
3434 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3435 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3436 }
3437 off = GCPhys - pRam->GCPhys;
3438 } while (off >= pRam->cb);
3439 }
3440 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3441 return VINF_SUCCESS;
3442}
3443
3444
3445
3446
3447/**
3448 * Gets the PGMPAGE structure for a guest page.
3449 *
3450 * Old Phys code: Will make sure the page is present.
3451 *
3452 * @returns VBox status code.
3453 * @retval VINF_SUCCESS and a valid *ppPage on success.
3454 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3455 *
3456 * @param pPGM PGM handle.
3457 * @param GCPhys The GC physical address.
3458 * @param ppPage Where to store the page pointer on success.
3459 * @param ppRamHint Where to read and store the ram list hint.
3460 * The caller initializes this to NULL before the call.
3461 */
3462DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3463{
3464 RTGCPHYS off;
3465 PPGMRAMRANGE pRam = *ppRamHint;
3466 if ( !pRam
3467 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3468 {
3469 pRam = pPGM->CTX_SUFF(pRamRanges);
3470 off = GCPhys - pRam->GCPhys;
3471 if (RT_UNLIKELY(off >= pRam->cb))
3472 {
3473 do
3474 {
3475 pRam = pRam->CTX_SUFF(pNext);
3476 if (RT_UNLIKELY(!pRam))
3477 {
3478 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3479 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3480 }
3481 off = GCPhys - pRam->GCPhys;
3482 } while (off >= pRam->cb);
3483 }
3484 *ppRamHint = pRam;
3485 }
3486 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3487 return VINF_SUCCESS;
3488}
3489
3490
3491/**
3492 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3493 *
3494 * @returns Pointer to the page on success.
3495 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3496 *
3497 * @param pPGM PGM handle.
3498 * @param GCPhys The GC physical address.
3499 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3500 */
3501DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3502{
3503 /*
3504 * Optimize for the first range.
3505 */
3506 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3507 RTGCPHYS off = GCPhys - pRam->GCPhys;
3508 if (RT_UNLIKELY(off >= pRam->cb))
3509 {
3510 do
3511 {
3512 pRam = pRam->CTX_SUFF(pNext);
3513 if (RT_UNLIKELY(!pRam))
3514 return NULL;
3515 off = GCPhys - pRam->GCPhys;
3516 } while (off >= pRam->cb);
3517 }
3518 *ppRam = pRam;
3519 return &pRam->aPages[off >> PAGE_SHIFT];
3520}
3521
3522
3523/**
3524 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3525 *
3526 * @returns Pointer to the page on success.
3527 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3528 *
3529 * @param pPGM PGM handle.
3530 * @param GCPhys The GC physical address.
3531 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3532 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3533 */
3534DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3535{
3536 /*
3537 * Optimize for the first range.
3538 */
3539 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3540 RTGCPHYS off = GCPhys - pRam->GCPhys;
3541 if (RT_UNLIKELY(off >= pRam->cb))
3542 {
3543 do
3544 {
3545 pRam = pRam->CTX_SUFF(pNext);
3546 if (RT_UNLIKELY(!pRam))
3547 {
3548 *ppRam = NULL; /* Shut up silly GCC warnings. */
3549 *ppPage = NULL; /* ditto */
3550 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3551 }
3552 off = GCPhys - pRam->GCPhys;
3553 } while (off >= pRam->cb);
3554 }
3555 *ppRam = pRam;
3556 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3557 return VINF_SUCCESS;
3558}
3559
3560
3561/**
3562 * Convert GC Phys to HC Phys.
3563 *
3564 * @returns VBox status.
3565 * @param pPGM PGM handle.
3566 * @param GCPhys The GC physical address.
3567 * @param pHCPhys Where to store the corresponding HC physical address.
3568 *
3569 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3570 * Avoid when writing new code!
3571 */
3572DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3573{
3574 PPGMPAGE pPage;
3575 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3576 if (RT_FAILURE(rc))
3577 return rc;
3578 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3579 return VINF_SUCCESS;
3580}
3581
3582#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3583
3584/**
3585 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3586 * optimizes access to pages already in the set.
3587 *
3588 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3589 * @param pPGM Pointer to the PVM instance data.
3590 * @param HCPhys The physical address of the page.
3591 * @param ppv Where to store the mapping address.
3592 */
3593DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3594{
3595 PVM pVM = PGM2VM(pPGM);
3596 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3597 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3598
3599 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3600 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3601 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3602
3603 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3604 unsigned iEntry = pSet->aiHashTable[iHash];
3605 if ( iEntry < pSet->cEntries
3606 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3607 {
3608 *ppv = pSet->aEntries[iEntry].pvPage;
3609 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3610 }
3611 else
3612 {
3613 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3614 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3615 }
3616
3617 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3618 return VINF_SUCCESS;
3619}
3620
3621
3622/**
3623 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3624 * access to pages already in the set.
3625 *
3626 * @returns See PGMDynMapGCPage.
3627 * @param pPGM Pointer to the PVM instance data.
3628 * @param GCPhys The guest physical address of the page.
3629 * @param ppv Where to store the mapping address.
3630 */
3631DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3632{
3633 PVM pVM = PGM2VM(pPGM);
3634 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3635
3636 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3637 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3638
3639 /*
3640 * Get the ram range.
3641 */
3642 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3643 RTGCPHYS off = GCPhys - pRam->GCPhys;
3644 if (RT_UNLIKELY(off >= pRam->cb
3645 /** @todo || page state stuff */))
3646 {
3647 /* This case is not counted into StatR0DynMapGCPageInl. */
3648 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3649 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3650 }
3651
3652 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3653 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3654
3655 /*
3656 * pgmR0DynMapHCPageInlined with out stats.
3657 */
3658 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3659 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3660 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3661
3662 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3663 unsigned iEntry = pSet->aiHashTable[iHash];
3664 if ( iEntry < pSet->cEntries
3665 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3666 {
3667 *ppv = pSet->aEntries[iEntry].pvPage;
3668 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3669 }
3670 else
3671 {
3672 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3673 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3674 }
3675
3676 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3677 return VINF_SUCCESS;
3678}
3679
3680
3681/**
3682 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3683 * access to pages already in the set.
3684 *
3685 * @returns See PGMDynMapGCPage.
3686 * @param pPGM Pointer to the PVM instance data.
3687 * @param HCPhys The physical address of the page.
3688 * @param ppv Where to store the mapping address.
3689 */
3690DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3691{
3692 PVM pVM = PGM2VM(pPGM);
3693 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3694
3695 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3696
3697 /*
3698 * Get the ram range.
3699 */
3700 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3701 RTGCPHYS off = GCPhys - pRam->GCPhys;
3702 if (RT_UNLIKELY(off >= pRam->cb
3703 /** @todo || page state stuff */))
3704 {
3705 /* This case is not counted into StatR0DynMapGCPageInl. */
3706 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3707 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3708 }
3709
3710 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3711 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3712
3713 /*
3714 * pgmR0DynMapHCPageInlined with out stats.
3715 */
3716 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3717 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3718 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3719
3720 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3721 unsigned iEntry = pSet->aiHashTable[iHash];
3722 if ( iEntry < pSet->cEntries
3723 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3724 {
3725 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3726 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3727 }
3728 else
3729 {
3730 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3731 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3732 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3733 }
3734
3735 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3736 return VINF_SUCCESS;
3737}
3738
3739#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3740#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3741
3742/**
3743 * Maps the page into current context (RC and maybe R0).
3744 *
3745 * @returns pointer to the mapping.
3746 * @param pVM Pointer to the PGM instance data.
3747 * @param pPage The page.
3748 */
3749DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3750{
3751 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3752 {
3753 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3754 void *pv;
3755# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3756 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3757# else
3758 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3759# endif
3760 return pv;
3761 }
3762 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3763}
3764
3765/**
3766 * Temporarily maps one host page specified by HC physical address, returning
3767 * pointer within the page.
3768 *
3769 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3770 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3771 *
3772 * @returns The address corresponding to HCPhys.
3773 * @param pPGM Pointer to the PVM instance data.
3774 * @param HCPhys HC Physical address of the page.
3775 */
3776DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3777{
3778 void *pv;
3779# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3780 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3781# else
3782 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3783# endif
3784 pv = (void *)((uintptr_t)pv | ((uintptr_t)HCPhys & PAGE_OFFSET_MASK));
3785 return pv;
3786}
3787
3788#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3789#ifndef IN_RC
3790
3791/**
3792 * Queries the Physical TLB entry for a physical guest page,
3793 * attempting to load the TLB entry if necessary.
3794 *
3795 * @returns VBox status code.
3796 * @retval VINF_SUCCESS on success
3797 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3798 *
3799 * @param pPGM The PGM instance handle.
3800 * @param GCPhys The address of the guest page.
3801 * @param ppTlbe Where to store the pointer to the TLB entry.
3802 */
3803DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3804{
3805 int rc;
3806 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3807 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3808 {
3809 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3810 rc = VINF_SUCCESS;
3811 }
3812 else
3813 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3814 *ppTlbe = pTlbe;
3815 return rc;
3816}
3817
3818
3819/**
3820 * Queries the Physical TLB entry for a physical guest page,
3821 * attempting to load the TLB entry if necessary.
3822 *
3823 * @returns VBox status code.
3824 * @retval VINF_SUCCESS on success
3825 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3826 *
3827 * @param pPGM The PGM instance handle.
3828 * @param pPage Pointer to the PGMPAGE structure corresponding to
3829 * GCPhys.
3830 * @param GCPhys The address of the guest page.
3831 * @param ppTlbe Where to store the pointer to the TLB entry.
3832 */
3833DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3834{
3835 int rc;
3836 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3837 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3838 {
3839 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3840 rc = VINF_SUCCESS;
3841 }
3842 else
3843 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3844 *ppTlbe = pTlbe;
3845 return rc;
3846}
3847
3848#endif /* !IN_RC */
3849
3850/**
3851 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3852 * Takes PSE-36 into account.
3853 *
3854 * @returns guest physical address
3855 * @param pPGM Pointer to the PGM instance data.
3856 * @param Pde Guest Pde
3857 */
3858DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3859{
3860 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3861 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3862
3863 return GCPhys & pPGM->GCPhys4MBPSEMask;
3864}
3865
3866
3867/**
3868 * Gets the page directory entry for the specified address (32-bit paging).
3869 *
3870 * @returns The page directory entry in question.
3871 * @param pPGM Pointer to the PGM instance data.
3872 * @param GCPtr The address.
3873 */
3874DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3875{
3876#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3877 PCX86PD pGuestPD = NULL;
3878 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3879 if (RT_FAILURE(rc))
3880 {
3881 X86PDE ZeroPde = {0};
3882 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3883 }
3884#else
3885 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3886# ifdef IN_RING3
3887 if (!pGuestPD)
3888 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3889# endif
3890#endif
3891 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3892}
3893
3894
3895/**
3896 * Gets the address of a specific page directory entry (32-bit paging).
3897 *
3898 * @returns Pointer the page directory entry in question.
3899 * @param pPGM Pointer to the PGM instance data.
3900 * @param GCPtr The address.
3901 */
3902DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3903{
3904#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3905 PX86PD pGuestPD = NULL;
3906 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3907 AssertRCReturn(rc, NULL);
3908#else
3909 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3910# ifdef IN_RING3
3911 if (!pGuestPD)
3912 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3913# endif
3914#endif
3915 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3916}
3917
3918
3919/**
3920 * Gets the address the guest page directory (32-bit paging).
3921 *
3922 * @returns Pointer the page directory entry in question.
3923 * @param pPGM Pointer to the PGM instance data.
3924 */
3925DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3926{
3927#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3928 PX86PD pGuestPD = NULL;
3929 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3930 AssertRCReturn(rc, NULL);
3931#else
3932 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3933# ifdef IN_RING3
3934 if (!pGuestPD)
3935 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3936# endif
3937#endif
3938 return pGuestPD;
3939}
3940
3941
3942/**
3943 * Gets the guest page directory pointer table.
3944 *
3945 * @returns Pointer to the page directory in question.
3946 * @returns NULL if the page directory is not present or on an invalid page.
3947 * @param pPGM Pointer to the PGM instance data.
3948 */
3949DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3950{
3951#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3952 PX86PDPT pGuestPDPT = NULL;
3953 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3954 AssertRCReturn(rc, NULL);
3955#else
3956 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3957# ifdef IN_RING3
3958 if (!pGuestPDPT)
3959 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3960# endif
3961#endif
3962 return pGuestPDPT;
3963}
3964
3965
3966/**
3967 * Gets the guest page directory pointer table entry for the specified address.
3968 *
3969 * @returns Pointer to the page directory in question.
3970 * @returns NULL if the page directory is not present or on an invalid page.
3971 * @param pPGM Pointer to the PGM instance data.
3972 * @param GCPtr The address.
3973 */
3974DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3975{
3976 AssertGCPtr32(GCPtr);
3977
3978#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3979 PX86PDPT pGuestPDPT = 0;
3980 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3981 AssertRCReturn(rc, 0);
3982#else
3983 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3984# ifdef IN_RING3
3985 if (!pGuestPDPT)
3986 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3987# endif
3988#endif
3989 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3990}
3991
3992
3993/**
3994 * Gets the page directory for the specified address.
3995 *
3996 * @returns Pointer to the page directory in question.
3997 * @returns NULL if the page directory is not present or on an invalid page.
3998 * @param pPGM Pointer to the PGM instance data.
3999 * @param GCPtr The address.
4000 */
4001DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
4002{
4003 AssertGCPtr32(GCPtr);
4004
4005 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4006 AssertReturn(pGuestPDPT, NULL);
4007 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4008 if (pGuestPDPT->a[iPdpt].n.u1Present)
4009 {
4010#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4011 PX86PDPAE pGuestPD = NULL;
4012 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4013 AssertRCReturn(rc, NULL);
4014#else
4015 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4016 if ( !pGuestPD
4017 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4018 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4019#endif
4020 return pGuestPD;
4021 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
4022 }
4023 return NULL;
4024}
4025
4026
4027/**
4028 * Gets the page directory entry for the specified address.
4029 *
4030 * @returns Pointer to the page directory entry in question.
4031 * @returns NULL if the page directory is not present or on an invalid page.
4032 * @param pPGM Pointer to the PGM instance data.
4033 * @param GCPtr The address.
4034 */
4035DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4036{
4037 AssertGCPtr32(GCPtr);
4038
4039 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4040 AssertReturn(pGuestPDPT, NULL);
4041 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4042 if (pGuestPDPT->a[iPdpt].n.u1Present)
4043 {
4044 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4045#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4046 PX86PDPAE pGuestPD = NULL;
4047 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4048 AssertRCReturn(rc, NULL);
4049#else
4050 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4051 if ( !pGuestPD
4052 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4053 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4054#endif
4055 return &pGuestPD->a[iPD];
4056 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
4057 }
4058 return NULL;
4059}
4060
4061
4062/**
4063 * Gets the page directory entry for the specified address.
4064 *
4065 * @returns The page directory entry in question.
4066 * @returns A non-present entry if the page directory is not present or on an invalid page.
4067 * @param pPGM Pointer to the PGM instance data.
4068 * @param GCPtr The address.
4069 */
4070DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4071{
4072 AssertGCPtr32(GCPtr);
4073 X86PDEPAE ZeroPde = {0};
4074 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4075 if (RT_LIKELY(pGuestPDPT))
4076 {
4077 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4078 if (pGuestPDPT->a[iPdpt].n.u1Present)
4079 {
4080 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4081#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4082 PX86PDPAE pGuestPD = NULL;
4083 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4084 AssertRCReturn(rc, ZeroPde);
4085#else
4086 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4087 if ( !pGuestPD
4088 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4089 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4090#endif
4091 return pGuestPD->a[iPD];
4092 }
4093 }
4094 return ZeroPde;
4095}
4096
4097
4098/**
4099 * Gets the page directory pointer table entry for the specified address
4100 * and returns the index into the page directory
4101 *
4102 * @returns Pointer to the page directory in question.
4103 * @returns NULL if the page directory is not present or on an invalid page.
4104 * @param pPGM Pointer to the PGM instance data.
4105 * @param GCPtr The address.
4106 * @param piPD Receives the index into the returned page directory
4107 * @param pPdpe Receives the page directory pointer entry. Optional.
4108 */
4109DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
4110{
4111 AssertGCPtr32(GCPtr);
4112
4113 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
4114 AssertReturn(pGuestPDPT, NULL);
4115 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4116 if (pPdpe)
4117 *pPdpe = pGuestPDPT->a[iPdpt];
4118 if (pGuestPDPT->a[iPdpt].n.u1Present)
4119 {
4120 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4121#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4122 PX86PDPAE pGuestPD = NULL;
4123 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
4124 AssertRCReturn(rc, NULL);
4125#else
4126 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
4127 if ( !pGuestPD
4128 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
4129 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
4130#endif
4131 *piPD = iPD;
4132 return pGuestPD;
4133 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
4134 }
4135 return NULL;
4136}
4137
4138#ifndef IN_RC
4139
4140/**
4141 * Gets the page map level-4 pointer for the guest.
4142 *
4143 * @returns Pointer to the PML4 page.
4144 * @param pPGM Pointer to the PGM instance data.
4145 */
4146DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
4147{
4148#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4149 PX86PML4 pGuestPml4;
4150 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4151 AssertRCReturn(rc, NULL);
4152#else
4153 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4154# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4155 if (!pGuestPml4)
4156 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4157# endif
4158 Assert(pGuestPml4);
4159#endif
4160 return pGuestPml4;
4161}
4162
4163
4164/**
4165 * Gets the pointer to a page map level-4 entry.
4166 *
4167 * @returns Pointer to the PML4 entry.
4168 * @param pPGM Pointer to the PGM instance data.
4169 * @param iPml4 The index.
4170 */
4171DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4172{
4173#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4174 PX86PML4 pGuestPml4;
4175 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4176 AssertRCReturn(rc, NULL);
4177#else
4178 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4179# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4180 if (!pGuestPml4)
4181 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4182# endif
4183 Assert(pGuestPml4);
4184#endif
4185 return &pGuestPml4->a[iPml4];
4186}
4187
4188
4189/**
4190 * Gets a page map level-4 entry.
4191 *
4192 * @returns The PML4 entry.
4193 * @param pPGM Pointer to the PGM instance data.
4194 * @param iPml4 The index.
4195 */
4196DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
4197{
4198#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4199 PX86PML4 pGuestPml4;
4200 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
4201 if (RT_FAILURE(rc))
4202 {
4203 X86PML4E ZeroPml4e = {0};
4204 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4205 }
4206#else
4207 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
4208# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
4209 if (!pGuestPml4)
4210 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
4211# endif
4212 Assert(pGuestPml4);
4213#endif
4214 return pGuestPml4->a[iPml4];
4215}
4216
4217
4218/**
4219 * Gets the page directory pointer entry for the specified address.
4220 *
4221 * @returns Pointer to the page directory pointer entry in question.
4222 * @returns NULL if the page directory is not present or on an invalid page.
4223 * @param pPGM Pointer to the PGM instance data.
4224 * @param GCPtr The address.
4225 * @param ppPml4e Page Map Level-4 Entry (out)
4226 */
4227DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4228{
4229 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4230 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4231 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4232 if (pPml4e->n.u1Present)
4233 {
4234 PX86PDPT pPdpt;
4235 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4236 AssertRCReturn(rc, NULL);
4237
4238 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4239 return &pPdpt->a[iPdpt];
4240 }
4241 return NULL;
4242}
4243
4244
4245/**
4246 * Gets the page directory entry for the specified address.
4247 *
4248 * @returns The page directory entry in question.
4249 * @returns A non-present entry if the page directory is not present or on an invalid page.
4250 * @param pPGM Pointer to the PGM instance data.
4251 * @param GCPtr The address.
4252 * @param ppPml4e Page Map Level-4 Entry (out)
4253 * @param pPdpe Page directory pointer table entry (out)
4254 */
4255DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4256{
4257 X86PDEPAE ZeroPde = {0};
4258 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4259 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4260 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4261 if (pPml4e->n.u1Present)
4262 {
4263 PCX86PDPT pPdptTemp;
4264 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4265 AssertRCReturn(rc, ZeroPde);
4266
4267 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4268 *pPdpe = pPdptTemp->a[iPdpt];
4269 if (pPdptTemp->a[iPdpt].n.u1Present)
4270 {
4271 PCX86PDPAE pPD;
4272 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4273 AssertRCReturn(rc, ZeroPde);
4274
4275 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4276 return pPD->a[iPD];
4277 }
4278 }
4279
4280 return ZeroPde;
4281}
4282
4283
4284/**
4285 * Gets the page directory entry for the specified address.
4286 *
4287 * @returns The page directory entry in question.
4288 * @returns A non-present entry if the page directory is not present or on an invalid page.
4289 * @param pPGM Pointer to the PGM instance data.
4290 * @param GCPtr The address.
4291 */
4292DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4293{
4294 X86PDEPAE ZeroPde = {0};
4295 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4296 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4297 if (pGuestPml4->a[iPml4].n.u1Present)
4298 {
4299 PCX86PDPT pPdptTemp;
4300 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4301 AssertRCReturn(rc, ZeroPde);
4302
4303 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4304 if (pPdptTemp->a[iPdpt].n.u1Present)
4305 {
4306 PCX86PDPAE pPD;
4307 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4308 AssertRCReturn(rc, ZeroPde);
4309
4310 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4311 return pPD->a[iPD];
4312 }
4313 }
4314 return ZeroPde;
4315}
4316
4317
4318/**
4319 * Gets the page directory entry for the specified address.
4320 *
4321 * @returns Pointer to the page directory entry in question.
4322 * @returns NULL if the page directory is not present or on an invalid page.
4323 * @param pPGM Pointer to the PGM instance data.
4324 * @param GCPtr The address.
4325 */
4326DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4327{
4328 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4329 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4330 if (pGuestPml4->a[iPml4].n.u1Present)
4331 {
4332 PCX86PDPT pPdptTemp;
4333 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4334 AssertRCReturn(rc, NULL);
4335
4336 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4337 if (pPdptTemp->a[iPdpt].n.u1Present)
4338 {
4339 PX86PDPAE pPD;
4340 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4341 AssertRCReturn(rc, NULL);
4342
4343 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4344 return &pPD->a[iPD];
4345 }
4346 }
4347 return NULL;
4348}
4349
4350
4351/**
4352 * Gets the GUEST page directory pointer for the specified address.
4353 *
4354 * @returns The page directory in question.
4355 * @returns NULL if the page directory is not present or on an invalid page.
4356 * @param pPGM Pointer to the PGM instance data.
4357 * @param GCPtr The address.
4358 * @param ppPml4e Page Map Level-4 Entry (out)
4359 * @param pPdpe Page directory pointer table entry (out)
4360 * @param piPD Receives the index into the returned page directory
4361 */
4362DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4363{
4364 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4365 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4366 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4367 if (pPml4e->n.u1Present)
4368 {
4369 PCX86PDPT pPdptTemp;
4370 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4371 AssertRCReturn(rc, NULL);
4372
4373 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4374 *pPdpe = pPdptTemp->a[iPdpt];
4375 if (pPdptTemp->a[iPdpt].n.u1Present)
4376 {
4377 PX86PDPAE pPD;
4378 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4379 AssertRCReturn(rc, NULL);
4380
4381 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4382 return pPD;
4383 }
4384 }
4385 return 0;
4386}
4387
4388#endif /* !IN_RC */
4389
4390/**
4391 * Gets the shadow page directory, 32-bit.
4392 *
4393 * @returns Pointer to the shadow 32-bit PD.
4394 * @param pPGM Pointer to the PGM instance data.
4395 */
4396DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4397{
4398 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4399}
4400
4401
4402/**
4403 * Gets the shadow page directory entry for the specified address, 32-bit.
4404 *
4405 * @returns Shadow 32-bit PDE.
4406 * @param pPGM Pointer to the PGM instance data.
4407 * @param GCPtr The address.
4408 */
4409DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4410{
4411 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4412
4413 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4414 if (!pShwPde)
4415 {
4416 X86PDE ZeroPde = {0};
4417 return ZeroPde;
4418 }
4419 return pShwPde->a[iPd];
4420}
4421
4422
4423/**
4424 * Gets the pointer to the shadow page directory entry for the specified
4425 * address, 32-bit.
4426 *
4427 * @returns Pointer to the shadow 32-bit PDE.
4428 * @param pPGM Pointer to the PGM instance data.
4429 * @param GCPtr The address.
4430 */
4431DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4432{
4433 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4434
4435 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4436 AssertReturn(pPde, NULL);
4437 return &pPde->a[iPd];
4438}
4439
4440
4441/**
4442 * Gets the shadow page pointer table, PAE.
4443 *
4444 * @returns Pointer to the shadow PAE PDPT.
4445 * @param pPGM Pointer to the PGM instance data.
4446 */
4447DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4448{
4449 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4450}
4451
4452
4453/**
4454 * Gets the shadow page directory for the specified address, PAE.
4455 *
4456 * @returns Pointer to the shadow PD.
4457 * @param pPGM Pointer to the PGM instance data.
4458 * @param GCPtr The address.
4459 */
4460DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4461{
4462 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4463 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4464
4465 if (!pPdpt->a[iPdpt].n.u1Present)
4466 return NULL;
4467
4468 /* Fetch the pgm pool shadow descriptor. */
4469 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4470 AssertReturn(pShwPde, NULL);
4471
4472 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4473}
4474
4475
4476/**
4477 * Gets the shadow page directory for the specified address, PAE.
4478 *
4479 * @returns Pointer to the shadow PD.
4480 * @param pPGM Pointer to the PGM instance data.
4481 * @param GCPtr The address.
4482 */
4483DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4484{
4485 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4486
4487 if (!pPdpt->a[iPdpt].n.u1Present)
4488 return NULL;
4489
4490 /* Fetch the pgm pool shadow descriptor. */
4491 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4492 AssertReturn(pShwPde, NULL);
4493
4494 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4495}
4496
4497
4498/**
4499 * Gets the shadow page directory entry, PAE.
4500 *
4501 * @returns PDE.
4502 * @param pPGM Pointer to the PGM instance data.
4503 * @param GCPtr The address.
4504 */
4505DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4506{
4507 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4508
4509 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4510 if (!pShwPde)
4511 {
4512 X86PDEPAE ZeroPde = {0};
4513 return ZeroPde;
4514 }
4515 return pShwPde->a[iPd];
4516}
4517
4518
4519/**
4520 * Gets the pointer to the shadow page directory entry for an address, PAE.
4521 *
4522 * @returns Pointer to the PDE.
4523 * @param pPGM Pointer to the PGM instance data.
4524 * @param GCPtr The address.
4525 */
4526DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4527{
4528 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4529
4530 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4531 AssertReturn(pPde, NULL);
4532 return &pPde->a[iPd];
4533}
4534
4535#ifndef IN_RC
4536
4537/**
4538 * Gets the shadow page map level-4 pointer.
4539 *
4540 * @returns Pointer to the shadow PML4.
4541 * @param pPGM Pointer to the PGM instance data.
4542 */
4543DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4544{
4545 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4546}
4547
4548
4549/**
4550 * Gets the shadow page map level-4 entry for the specified address.
4551 *
4552 * @returns The entry.
4553 * @param pPGM Pointer to the PGM instance data.
4554 * @param GCPtr The address.
4555 */
4556DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4557{
4558 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4559 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4560
4561 if (!pShwPml4)
4562 {
4563 X86PML4E ZeroPml4e = {0};
4564 return ZeroPml4e;
4565 }
4566 return pShwPml4->a[iPml4];
4567}
4568
4569
4570/**
4571 * Gets the pointer to the specified shadow page map level-4 entry.
4572 *
4573 * @returns The entry.
4574 * @param pPGM Pointer to the PGM instance data.
4575 * @param iPml4 The PML4 index.
4576 */
4577DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4578{
4579 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4580 if (!pShwPml4)
4581 return NULL;
4582 return &pShwPml4->a[iPml4];
4583}
4584
4585
4586/**
4587 * Gets the GUEST page directory pointer for the specified address.
4588 *
4589 * @returns The page directory in question.
4590 * @returns NULL if the page directory is not present or on an invalid page.
4591 * @param pPGM Pointer to the PGM instance data.
4592 * @param GCPtr The address.
4593 * @param piPD Receives the index into the returned page directory
4594 */
4595DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4596{
4597 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4598 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4599 if (pGuestPml4->a[iPml4].n.u1Present)
4600 {
4601 PCX86PDPT pPdptTemp;
4602 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4603 AssertRCReturn(rc, NULL);
4604
4605 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4606 if (pPdptTemp->a[iPdpt].n.u1Present)
4607 {
4608 PX86PDPAE pPD;
4609 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4610 AssertRCReturn(rc, NULL);
4611
4612 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4613 return pPD;
4614 }
4615 }
4616 return NULL;
4617}
4618
4619#endif /* !IN_RC */
4620
4621/**
4622 * Gets the page state for a physical handler.
4623 *
4624 * @returns The physical handler page state.
4625 * @param pCur The physical handler in question.
4626 */
4627DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4628{
4629 switch (pCur->enmType)
4630 {
4631 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4632 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4633
4634 case PGMPHYSHANDLERTYPE_MMIO:
4635 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4636 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4637
4638 default:
4639 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4640 }
4641}
4642
4643
4644/**
4645 * Gets the page state for a virtual handler.
4646 *
4647 * @returns The virtual handler page state.
4648 * @param pCur The virtual handler in question.
4649 * @remarks This should never be used on a hypervisor access handler.
4650 */
4651DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4652{
4653 switch (pCur->enmType)
4654 {
4655 case PGMVIRTHANDLERTYPE_WRITE:
4656 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4657 case PGMVIRTHANDLERTYPE_ALL:
4658 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4659 default:
4660 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4661 }
4662}
4663
4664
4665/**
4666 * Clears one physical page of a virtual handler
4667 *
4668 * @param pPGM Pointer to the PGM instance.
4669 * @param pCur Virtual handler structure
4670 * @param iPage Physical page index
4671 *
4672 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4673 * need to care about other handlers in the same page.
4674 */
4675DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4676{
4677 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4678
4679 /*
4680 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4681 */
4682#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4683 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4684 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4685 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4686#endif
4687 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4688 {
4689 /* We're the head of the alias chain. */
4690 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4691#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4692 AssertReleaseMsg(pRemove != NULL,
4693 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4694 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4695 AssertReleaseMsg(pRemove == pPhys2Virt,
4696 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4697 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4698 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4699 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4700#endif
4701 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4702 {
4703 /* Insert the next list in the alias chain into the tree. */
4704 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4705#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4706 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4707 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4708 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4709#endif
4710 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4711 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4712 AssertRelease(fRc);
4713 }
4714 }
4715 else
4716 {
4717 /* Locate the previous node in the alias chain. */
4718 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4719#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4720 AssertReleaseMsg(pPrev != pPhys2Virt,
4721 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4722 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4723#endif
4724 for (;;)
4725 {
4726 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4727 if (pNext == pPhys2Virt)
4728 {
4729 /* unlink. */
4730 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4731 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4732 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4733 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4734 else
4735 {
4736 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4737 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4738 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4739 }
4740 break;
4741 }
4742
4743 /* next */
4744 if (pNext == pPrev)
4745 {
4746#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4747 AssertReleaseMsg(pNext != pPrev,
4748 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4749 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4750#endif
4751 break;
4752 }
4753 pPrev = pNext;
4754 }
4755 }
4756 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4757 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4758 pPhys2Virt->offNextAlias = 0;
4759 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4760
4761 /*
4762 * Clear the ram flags for this page.
4763 */
4764 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4765 AssertReturnVoid(pPage);
4766 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4767}
4768
4769
4770/**
4771 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4772 *
4773 * @returns Pointer to the shadow page structure.
4774 * @param pPool The pool.
4775 * @param idx The pool page index.
4776 */
4777DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4778{
4779 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4780 return &pPool->aPages[idx];
4781}
4782
4783
4784/**
4785 * Clear references to guest physical memory.
4786 *
4787 * @param pPool The pool.
4788 * @param pPoolPage The pool page.
4789 * @param pPhysPage The physical guest page tracking structure.
4790 */
4791DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4792{
4793 /*
4794 * Just deal with the simple case here.
4795 */
4796# ifdef LOG_ENABLED
4797 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4798# endif
4799 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4800 if (cRefs == 1)
4801 {
4802 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4803 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4804 }
4805 else
4806 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4807 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4808}
4809
4810
4811/**
4812 * Moves the page to the head of the age list.
4813 *
4814 * This is done when the cached page is used in one way or another.
4815 *
4816 * @param pPool The pool.
4817 * @param pPage The cached page.
4818 */
4819DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4820{
4821 PVM pVM = pPool->CTX_SUFF(pVM);
4822 pgmLock(pVM);
4823
4824 /*
4825 * Move to the head of the age list.
4826 */
4827 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4828 {
4829 /* unlink */
4830 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4831 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4832 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4833 else
4834 pPool->iAgeTail = pPage->iAgePrev;
4835
4836 /* insert at head */
4837 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4838 pPage->iAgeNext = pPool->iAgeHead;
4839 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4840 pPool->iAgeHead = pPage->idx;
4841 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4842 }
4843 pgmUnlock(pVM);
4844}
4845
4846/**
4847 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4848 *
4849 * @param pVM VM Handle.
4850 * @param pPage PGM pool page
4851 */
4852DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4853{
4854 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4855 ASMAtomicIncU32(&pPage->cLocked);
4856}
4857
4858
4859/**
4860 * Unlocks a page to allow flushing again
4861 *
4862 * @param pVM VM Handle.
4863 * @param pPage PGM pool page
4864 */
4865DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4866{
4867 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4868 Assert(pPage->cLocked);
4869 ASMAtomicDecU32(&pPage->cLocked);
4870}
4871
4872
4873/**
4874 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4875 *
4876 * @returns VBox status code.
4877 * @param pPage PGM pool page
4878 */
4879DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4880{
4881 if (pPage->cLocked)
4882 {
4883 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4884 if (pPage->cModifications)
4885 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4886 return true;
4887 }
4888 return false;
4889}
4890
4891/**
4892 * Tells if mappings are to be put into the shadow page table or not
4893 *
4894 * @returns boolean result
4895 * @param pVM VM handle.
4896 */
4897DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4898{
4899#ifdef IN_RING0
4900 /* There are no mappings in VT-x and AMD-V mode. */
4901 Assert(pPGM->fDisableMappings);
4902 return false;
4903#else
4904 return !pPGM->fDisableMappings;
4905#endif
4906}
4907
4908/** @} */
4909
4910#endif
4911
4912
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