PGMInternal.h@ 26606

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1	/* $Id: PGMInternal.h 26606 2010-02-17 12:40:42Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/avl.h>
42	#include <iprt/critsect.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings to care about.
60	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
61	*/
62	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
63	# define PGM_WITHOUT_MAPPINGS
64	#endif
65
66	/**
67	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
68	* Comment it if it will break something.
69	*/
70	#define PGM_OUT_OF_SYNC_IN_GC
71
72	/**
73	* Check and skip global PDEs for non-global flushes
74	*/
75	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
76
77	/**
78	* Optimization for PAE page tables that are modified often
79	*/
80	//#if 0 /* disabled again while debugging */
81	#ifndef IN_RC
82	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
83	#endif
84	//#endif
85
86	/**
87	* Sync N pages instead of a whole page table
88	*/
89	#define PGM_SYNC_N_PAGES
90
91	/**
92	* Number of pages to sync during a page fault
93	*
94	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
95	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
96	*
97	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
98	* world switch overhead, so let's sync more.
99	*/
100	# ifdef IN_RING0
101	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
102	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
103	* but ~5% fewer faults.
104	*/
105	# define PGM_SYNC_NR_PAGES 32
106	#else
107	# define PGM_SYNC_NR_PAGES 8
108	#endif
109
110	/**
111	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
112	*/
113	#define PGM_MAX_PHYSCACHE_ENTRIES 64
114	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
115
116
117	/** @def PGMPOOL_CFG_MAX_GROW
118	* The maximum number of pages to add to the pool in one go.
119	*/
120	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
121
122	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
123	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
124	*/
125	#ifdef VBOX_STRICT
126	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
127	#endif
128
129	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130	* Enables the experimental lazy page allocation code. */
131	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
132
133	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
134	* Enables real write monitoring of pages, i.e. mapping them read-only and
135	* only making them writable when getting a write access #PF. */
136	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
137
138	/** @} */
139
140
141	/** @name PDPT and PML4 flags.
142	* These are placed in the three bits available for system programs in
143	* the PDPT and PML4 entries.
144	* @{ */
145	/** The entry is a permanent one and it's must always be present.
146	* Never free such an entry. */
147	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
148	/** Mapping (hypervisor allocated pagetable). */
149	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
150	/** @} */
151
152	/** @name Page directory flags.
153	* These are placed in the three bits available for system programs in
154	* the page directory entries.
155	* @{ */
156	/** Mapping (hypervisor allocated pagetable). */
157	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
158	/** Made read-only to facilitate dirty bit tracking. */
159	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
160	/** @} */
161
162	/** @name Page flags.
163	* These are placed in the three bits available for system programs in
164	* the page entries.
165	* @{ */
166	/** Made read-only to facilitate dirty bit tracking. */
167	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
168
169	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
170	/** Scanned and approved by CSAM (tm).
171	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
172	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
173	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
174	#endif
175
176	/** @} */
177
178	/** @name Defines used to indicate the shadow and guest paging in the templates.
179	* @{ */
180	#define PGM_TYPE_REAL 1
181	#define PGM_TYPE_PROT 2
182	#define PGM_TYPE_32BIT 3
183	#define PGM_TYPE_PAE 4
184	#define PGM_TYPE_AMD64 5
185	#define PGM_TYPE_NESTED 6
186	#define PGM_TYPE_EPT 7
187	#define PGM_TYPE_MAX PGM_TYPE_EPT
188	/** @} */
189
190	/** Macro for checking if the guest is using paging.
191	* @param uGstType PGM_TYPE_*
192	* @param uShwType PGM_TYPE_*
193	* @remark ASSUMES certain order of the PGM_TYPE_* values.
194	*/
195	#define PGM_WITH_PAGING(uGstType, uShwType) \
196	( (uGstType) >= PGM_TYPE_32BIT \
197	&& (uShwType) != PGM_TYPE_NESTED \
198	&& (uShwType) != PGM_TYPE_EPT)
199
200	/** Macro for checking if the guest supports the NX bit.
201	* @param uGstType PGM_TYPE_*
202	* @param uShwType PGM_TYPE_*
203	* @remark ASSUMES certain order of the PGM_TYPE_* values.
204	*/
205	#define PGM_WITH_NX(uGstType, uShwType) \
206	( (uGstType) >= PGM_TYPE_PAE \
207	&& (uShwType) != PGM_TYPE_NESTED \
208	&& (uShwType) != PGM_TYPE_EPT)
209
210
211	/** @def PGM_HCPHYS_2_PTR
212	* Maps a HC physical page pool address to a virtual address.
213	*
214	* @returns VBox status code.
215	* @param pVM The VM handle.
216	* @param HCPhys The HC physical address to map to a virtual one.
217	* @param ppv Where to store the virtual address. No need to cast this.
218	*
219	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
220	* small page window employeed by that function. Be careful.
221	* @remark There is no need to assert on the result.
222	*/
223	#ifdef IN_RC
224	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
225	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
226	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
227	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
228	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
229	#else
230	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
231	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
232	#endif
233
234	/** @def PGM_HCPHYS_2_PTR_BY_PGM
235	* Maps a HC physical page pool address to a virtual address.
236	*
237	* @returns VBox status code.
238	* @param pPGM The PGM instance data.
239	* @param HCPhys The HC physical address to map to a virtual one.
240	* @param ppv Where to store the virtual address. No need to cast this.
241	*
242	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
243	* small page window employeed by that function. Be careful.
244	* @remark There is no need to assert on the result.
245	*/
246	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
247	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
248	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
249	#else
250	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
251	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
252	#endif
253
254	/** @def PGM_GCPHYS_2_PTR
255	* Maps a GC physical page address to a virtual address.
256	*
257	* @returns VBox status code.
258	* @param pVM The VM handle.
259	* @param GCPhys The GC physical address to map to a virtual one.
260	* @param ppv Where to store the virtual address. No need to cast this.
261	*
262	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
263	* small page window employeed by that function. Be careful.
264	* @remark There is no need to assert on the result.
265	*/
266	#ifdef IN_RC
267	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
268	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
269	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
270	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
271	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
272	#else
273	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
274	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
275	#endif
276
277	/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
278	* Maps a GC physical page address to a virtual address.
279	*
280	* @returns VBox status code.
281	* @param pPGM Pointer to the PGM instance data.
282	* @param GCPhys The GC physical address to map to a virtual one.
283	* @param ppv Where to store the virtual address. No need to cast this.
284	*
285	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
286	* small page window employeed by that function. Be careful.
287	* @remark There is no need to assert on the result.
288	*/
289	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
290	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
291	pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
292	#else
293	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
294	PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
295	#endif
296
297	/** @def PGM_GCPHYS_2_PTR_EX
298	* Maps a unaligned GC physical page address to a virtual address.
299	*
300	* @returns VBox status code.
301	* @param pVM The VM handle.
302	* @param GCPhys The GC physical address to map to a virtual one.
303	* @param ppv Where to store the virtual address. No need to cast this.
304	*
305	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
306	* small page window employeed by that function. Be careful.
307	* @remark There is no need to assert on the result.
308	*/
309	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
312	#else
313	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315	#endif
316
317	/** @def PGM_INVL_PG
318	* Invalidates a page.
319	*
320	* @param pVCpu The VMCPU handle.
321	* @param GCVirt The virtual address of the page to invalidate.
322	*/
323	#ifdef IN_RC
324	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
325	#elif defined(IN_RING0)
326	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
327	#else
328	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
329	#endif
330
331	/** @def PGM_INVL_PG_ALL_VCPU
332	* Invalidates a page on all VCPUs
333	*
334	* @param pVM The VM handle.
335	* @param GCVirt The virtual address of the page to invalidate.
336	*/
337	#ifdef IN_RC
338	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
339	#elif defined(IN_RING0)
340	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
341	#else
342	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
343	#endif
344
345	/** @def PGM_INVL_BIG_PG
346	* Invalidates a 4MB page directory entry.
347	*
348	* @param pVCpu The VMCPU handle.
349	* @param GCVirt The virtual address within the page directory to invalidate.
350	*/
351	#ifdef IN_RC
352	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
353	#elif defined(IN_RING0)
354	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
355	#else
356	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
357	#endif
358
359	/** @def PGM_INVL_VCPU_TLBS()
360	* Invalidates the TLBs of the specified VCPU
361	*
362	* @param pVCpu The VMCPU handle.
363	*/
364	#ifdef IN_RC
365	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
366	#elif defined(IN_RING0)
367	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
368	#else
369	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
370	#endif
371
372	/** @def PGM_INVL_ALL_VCPU_TLBS()
373	* Invalidates the TLBs of all VCPUs
374	*
375	* @param pVM The VM handle.
376	*/
377	#ifdef IN_RC
378	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
379	#elif defined(IN_RING0)
380	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
381	#else
382	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
383	#endif
384
385	/** Size of the GCPtrConflict array in PGMMAPPING.
386	* @remarks Must be a power of two. */
387	#define PGMMAPPING_CONFLICT_MAX 8
388
389	/**
390	* Structure for tracking GC Mappings.
391	*
392	* This structure is used by linked list in both GC and HC.
393	*/
394	typedef struct PGMMAPPING
395	{
396	/** Pointer to next entry. */
397	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
398	/** Pointer to next entry. */
399	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
400	/** Pointer to next entry. */
401	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
402	/** Indicate whether this entry is finalized. */
403	bool fFinalized;
404	/** Start Virtual address. */
405	RTGCPTR GCPtr;
406	/** Last Virtual address (inclusive). */
407	RTGCPTR GCPtrLast;
408	/** Range size (bytes). */
409	RTGCPTR cb;
410	/** Pointer to relocation callback function. */
411	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
412	/** User argument to the callback. */
413	R3PTRTYPE(void *) pvUser;
414	/** Mapping description / name. For easing debugging. */
415	R3PTRTYPE(const char *) pszDesc;
416	/** Last 8 addresses that caused conflicts. */
417	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
418	/** Number of conflicts for this hypervisor mapping. */
419	uint32_t cConflicts;
420	/** Number of page tables. */
421	uint32_t cPTs;
422
423	/** Array of page table mapping data. Each entry
424	* describes one page table. The array can be longer
425	* than the declared length.
426	*/
427	struct
428	{
429	/** The HC physical address of the page table. */
430	RTHCPHYS HCPhysPT;
431	/** The HC physical address of the first PAE page table. */
432	RTHCPHYS HCPhysPaePT0;
433	/** The HC physical address of the second PAE page table. */
434	RTHCPHYS HCPhysPaePT1;
435	/** The HC virtual address of the 32-bit page table. */
436	R3PTRTYPE(PX86PT) pPTR3;
437	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
438	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
439	/** The RC virtual address of the 32-bit page table. */
440	RCPTRTYPE(PX86PT) pPTRC;
441	/** The RC virtual address of the two PAE page table. */
442	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
443	/** The R0 virtual address of the 32-bit page table. */
444	R0PTRTYPE(PX86PT) pPTR0;
445	/** The R0 virtual address of the two PAE page table. */
446	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
447	} aPTs[1];
448	} PGMMAPPING;
449	/** Pointer to structure for tracking GC Mappings. */
450	typedef struct PGMMAPPING *PPGMMAPPING;
451
452
453	/**
454	* Physical page access handler structure.
455	*
456	* This is used to keep track of physical address ranges
457	* which are being monitored in some kind of way.
458	*/
459	typedef struct PGMPHYSHANDLER
460	{
461	AVLROGCPHYSNODECORE Core;
462	/** Access type. */
463	PGMPHYSHANDLERTYPE enmType;
464	/** Number of pages to update. */
465	uint32_t cPages;
466	/** Pointer to R3 callback function. */
467	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
468	/** User argument for R3 handlers. */
469	R3PTRTYPE(void *) pvUserR3;
470	/** Pointer to R0 callback function. */
471	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
472	/** User argument for R0 handlers. */
473	R0PTRTYPE(void *) pvUserR0;
474	/** Pointer to RC callback function. */
475	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
476	/** User argument for RC handlers. */
477	RCPTRTYPE(void *) pvUserRC;
478	/** Description / Name. For easing debugging. */
479	R3PTRTYPE(const char *) pszDesc;
480	#ifdef VBOX_WITH_STATISTICS
481	/** Profiling of this handler. */
482	STAMPROFILE Stat;
483	#endif
484	} PGMPHYSHANDLER;
485	/** Pointer to a physical page access handler structure. */
486	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
487
488
489	/**
490	* Cache node for the physical addresses covered by a virtual handler.
491	*/
492	typedef struct PGMPHYS2VIRTHANDLER
493	{
494	/** Core node for the tree based on physical ranges. */
495	AVLROGCPHYSNODECORE Core;
496	/** Offset from this struct to the PGMVIRTHANDLER structure. */
497	int32_t offVirtHandler;
498	/** Offset of the next alias relative to this one.
499	* Bit 0 is used for indicating whether we're in the tree.
500	* Bit 1 is used for indicating that we're the head node.
501	*/
502	int32_t offNextAlias;
503	} PGMPHYS2VIRTHANDLER;
504	/** Pointer to a phys to virtual handler structure. */
505	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
506
507	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
508	* node is in the tree. */
509	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
510	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
511	* node is in the head of an alias chain.
512	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
513	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
514	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
515	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
516
517
518	/**
519	* Virtual page access handler structure.
520	*
521	* This is used to keep track of virtual address ranges
522	* which are being monitored in some kind of way.
523	*/
524	typedef struct PGMVIRTHANDLER
525	{
526	/** Core node for the tree based on virtual ranges. */
527	AVLROGCPTRNODECORE Core;
528	/** Size of the range (in bytes). */
529	RTGCPTR cb;
530	/** Number of cache pages. */
531	uint32_t cPages;
532	/** Access type. */
533	PGMVIRTHANDLERTYPE enmType;
534	/** Pointer to the RC callback function. */
535	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
536	#if HC_ARCH_BITS == 64
537	RTRCPTR padding;
538	#endif
539	/** Pointer to the R3 callback function for invalidation. */
540	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
541	/** Pointer to the R3 callback function. */
542	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
543	/** Description / Name. For easing debugging. */
544	R3PTRTYPE(const char *) pszDesc;
545	#ifdef VBOX_WITH_STATISTICS
546	/** Profiling of this handler. */
547	STAMPROFILE Stat;
548	#endif
549	/** Array of cached physical addresses for the monitored ranged. */
550	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
551	} PGMVIRTHANDLER;
552	/** Pointer to a virtual page access handler structure. */
553	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
554
555
556	/**
557	* Page type.
558	*
559	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
560	* @remarks This is used in the saved state, so changes to it requires bumping
561	* the saved state version.
562	* @todo So, convert to \#defines!
563	*/
564	typedef enum PGMPAGETYPE
565	{
566	/** The usual invalid zero entry. */
567	PGMPAGETYPE_INVALID = 0,
568	/** RAM page. (RWX) */
569	PGMPAGETYPE_RAM,
570	/** MMIO2 page. (RWX) */
571	PGMPAGETYPE_MMIO2,
572	/** MMIO2 page aliased over an MMIO page. (RWX)
573	* See PGMHandlerPhysicalPageAlias(). */
574	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
575	/** Shadowed ROM. (RWX) */
576	PGMPAGETYPE_ROM_SHADOW,
577	/** ROM page. (R-X) */
578	PGMPAGETYPE_ROM,
579	/** MMIO page. (---) */
580	PGMPAGETYPE_MMIO,
581	/** End of valid entries. */
582	PGMPAGETYPE_END
583	} PGMPAGETYPE;
584	AssertCompile(PGMPAGETYPE_END <= 7);
585
586	/** @name Page type predicates.
587	* @{ */
588	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
589	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
590	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
591	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
592	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
593	/** @} */
594
595
596	/**
597	* A Physical Guest Page tracking structure.
598	*
599	* The format of this structure is complicated because we have to fit a lot
600	* of information into as few bits as possible. The format is also subject
601	* to change (there is one comming up soon). Which means that for we'll be
602	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
603	* accesses to the structure.
604	*/
605	typedef struct PGMPAGE
606	{
607	/** The physical address and the Page ID. */
608	RTHCPHYS HCPhysAndPageID;
609	/** Combination of:
610	* - [0-7]: u2HandlerPhysStateY - the physical handler state
611	* (PGM_PAGE_HNDL_PHYS_STATE_*).
612	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
613	* (PGM_PAGE_HNDL_VIRT_STATE_*).
614	* - [14]: u1LargePage - flag indicating that it's part of a large (2 MB) page
615	* - [15]: fWrittenToY - flag indicating that a write monitored page was
616	* written to when set.
617	* - [10-13]: 4 unused bits.
618	* @remarks Warning! All accesses to the bits are hardcoded.
619	*
620	* @todo Change this to a union with both bitfields, u8 and u accessors.
621	* That'll help deal with some of the hardcoded accesses.
622	*
623	* @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
624	* will make it possible to turn some of the 16-bit accesses into
625	* 32-bit ones, which may be efficient (stalls).
626	*/
627	RTUINT16U u16MiscY;
628	/** The page state.
629	* Only 2 bits are really needed for this. */
630	uint8_t uStateY;
631	/** The page type (PGMPAGETYPE).
632	* Only 3 bits are really needed for this. */
633	uint8_t uTypeY;
634	/** Usage tracking (page pool). */
635	uint16_t u16TrackingY;
636	/** The number of read locks on this page. */
637	uint8_t cReadLocksY;
638	/** The number of write locks on this page. */
639	uint8_t cWriteLocksY;
640	} PGMPAGE;
641	AssertCompileSize(PGMPAGE, 16);
642	/** Pointer to a physical guest page. */
643	typedef PGMPAGE *PPGMPAGE;
644	/** Pointer to a const physical guest page. */
645	typedef const PGMPAGE *PCPGMPAGE;
646	/** Pointer to a physical guest page pointer. */
647	typedef PPGMPAGE *PPPGMPAGE;
648
649
650	/**
651	* Clears the page structure.
652	* @param pPage Pointer to the physical guest page tracking structure.
653	*/
654	#define PGM_PAGE_CLEAR(pPage) \
655	do { \
656	(pPage)->HCPhysAndPageID = 0; \
657	(pPage)->uStateY = 0; \
658	(pPage)->uTypeY = 0; \
659	(pPage)->u16MiscY.u = 0; \
660	(pPage)->u16TrackingY = 0; \
661	(pPage)->cReadLocksY = 0; \
662	(pPage)->cWriteLocksY = 0; \
663	} while (0)
664
665	/**
666	* Initializes the page structure.
667	* @param pPage Pointer to the physical guest page tracking structure.
668	*/
669	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670	do { \
671	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
672	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
673	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
674	(pPage)->uStateY = (_uState); \
675	(pPage)->uTypeY = (_uType); \
676	(pPage)->u16MiscY.u = 0; \
677	(pPage)->u16TrackingY = 0; \
678	(pPage)->cReadLocksY = 0; \
679	(pPage)->cWriteLocksY = 0; \
680	} while (0)
681
682	/**
683	* Initializes the page structure of a ZERO page.
684	* @param pPage Pointer to the physical guest page tracking structure.
685	* @param pVM The VM handle (for getting the zero page address).
686	* @param uType The page type (PGMPAGETYPE).
687	*/
688	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
689	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
690
691
692	/** @name The Page state, PGMPAGE::uStateY.
693	* @{ */
694	/** The zero page.
695	* This is a per-VM page that's never ever mapped writable. */
696	#define PGM_PAGE_STATE_ZERO 0
697	/** A allocated page.
698	* This is a per-VM page allocated from the page pool (or wherever
699	* we get MMIO2 pages from if the type is MMIO2).
700	*/
701	#define PGM_PAGE_STATE_ALLOCATED 1
702	/** A allocated page that's being monitored for writes.
703	* The shadow page table mappings are read-only. When a write occurs, the
704	* fWrittenTo member is set, the page remapped as read-write and the state
705	* moved back to allocated. */
706	#define PGM_PAGE_STATE_WRITE_MONITORED 2
707	/** The page is shared, aka. copy-on-write.
708	* This is a page that's shared with other VMs. */
709	#define PGM_PAGE_STATE_SHARED 3
710	/** @} */
711
712
713	/**
714	* Gets the page state.
715	* @returns page state (PGM_PAGE_STATE_*).
716	* @param pPage Pointer to the physical guest page tracking structure.
717	*/
718	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
719
720	/**
721	* Sets the page state.
722	* @param pPage Pointer to the physical guest page tracking structure.
723	* @param _uState The new page state.
724	*/
725	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
726
727
728	/**
729	* Gets the host physical address of the guest page.
730	* @returns host physical address (RTHCPHYS).
731	* @param pPage Pointer to the physical guest page tracking structure.
732	*/
733	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
734
735	/**
736	* Sets the host physical address of the guest page.
737	* @param pPage Pointer to the physical guest page tracking structure.
738	* @param _HCPhys The new host physical address.
739	*/
740	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
741	do { \
742	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
743	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
744	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
745	\| (SetHCPhysTmp << (28-12)); \
746	} while (0)
747
748	/**
749	* Get the Page ID.
750	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
751	* @param pPage Pointer to the physical guest page tracking structure.
752	*/
753	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
754
755	/**
756	* Sets the Page ID.
757	* @param pPage Pointer to the physical guest page tracking structure.
758	*/
759	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
760	do { \
761	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
762	\| ((_idPage) & UINT32_C(0x0fffffff)); \
763	} while (0)
764
765	/**
766	* Get the Chunk ID.
767	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
768	* @param pPage Pointer to the physical guest page tracking structure.
769	*/
770	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
771
772	/**
773	* Get the index of the page within the allocation chunk.
774	* @returns The page index.
775	* @param pPage Pointer to the physical guest page tracking structure.
776	*/
777	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
778
779	/**
780	* Gets the page type.
781	* @returns The page type.
782	* @param pPage Pointer to the physical guest page tracking structure.
783	*/
784	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
785
786	/**
787	* Sets the page type.
788	* @param pPage Pointer to the physical guest page tracking structure.
789	* @param _enmType The new page type (PGMPAGETYPE).
790	*/
791	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
792
793	/**
794	* Checks if the page is marked for MMIO.
795	* @returns true/false.
796	* @param pPage Pointer to the physical guest page tracking structure.
797	*/
798	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
799
800	/**
801	* Checks if the page is backed by the ZERO page.
802	* @returns true/false.
803	* @param pPage Pointer to the physical guest page tracking structure.
804	*/
805	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
806
807	/**
808	* Checks if the page is backed by a SHARED page.
809	* @returns true/false.
810	* @param pPage Pointer to the physical guest page tracking structure.
811	*/
812	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
813
814
815	/**
816	* Marks the page as written to (for GMM change monitoring).
817	* @param pPage Pointer to the physical guest page tracking structure.
818	*/
819	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
820
821	/**
822	* Clears the written-to indicator.
823	* @param pPage Pointer to the physical guest page tracking structure.
824	*/
825	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
826
827	/**
828	* Checks if the page was marked as written-to.
829	* @returns true/false.
830	* @param pPage Pointer to the physical guest page tracking structure.
831	*/
832	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
833
834	/**
835	* Marks the page as part of a large continuous page
836	* @param pPage Pointer to the physical guest page tracking structure.
837	*/
838	#define PGM_PAGE_SET_LARGE_PAGE(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x40); } while (0)
839
840	/**
841	* Clears the page as part of a large continuous page indicator.
842	* @param pPage Pointer to the physical guest page tracking structure.
843	*/
844	#define PGM_PAGE_CLEAR_LARGE_PAGE(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xbf); } while (0)
845
846	/**
847	* Checks if the page was marked being part of a large page
848	* @returns true/false.
849	* @param pPage Pointer to the physical guest page tracking structure.
850	*/
851	#define PGM_PAGE_IS_LARGE_PAGE(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x40)) )
852
853	/** Enabled optimized access handler tests.
854	* These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
855	* layout. When enabled, the compiler should normally generate more compact
856	* code.
857	*/
858	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
859
860	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
861	*
862	* @remarks The values are assigned in order of priority, so we can calculate
863	* the correct state for a page with different handlers installed.
864	* @{ */
865	/** No handler installed. */
866	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
867	/** Monitoring is temporarily disabled. */
868	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
869	/** Write access is monitored. */
870	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
871	/** All access is monitored. */
872	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
873	/** @} */
874
875	/**
876	* Gets the physical access handler state of a page.
877	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
878	* @param pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
881	( (pPage)->u16MiscY.au8[0] )
882
883	/**
884	* Sets the physical access handler state of a page.
885	* @param pPage Pointer to the physical guest page tracking structure.
886	* @param _uState The new state value.
887	*/
888	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
889	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
890
891	/**
892	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
893	* @returns true/false
894	* @param pPage Pointer to the physical guest page tracking structure.
895	*/
896	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
897	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
898
899	/**
900	* Checks if the page has any active physical access handlers.
901	* @returns true/false
902	* @param pPage Pointer to the physical guest page tracking structure.
903	*/
904	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
905	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
906
907
908	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
909	*
910	* @remarks The values are assigned in order of priority, so we can calculate
911	* the correct state for a page with different handlers installed.
912	* @{ */
913	/** No handler installed. */
914	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
915	/* 1 is reserved so the lineup is identical with the physical ones. */
916	/** Write access is monitored. */
917	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
918	/** All access is monitored. */
919	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
920	/** @} */
921
922	/**
923	* Gets the virtual access handler state of a page.
924	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
925	* @param pPage Pointer to the physical guest page tracking structure.
926	*/
927	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
928
929	/**
930	* Sets the virtual access handler state of a page.
931	* @param pPage Pointer to the physical guest page tracking structure.
932	* @param _uState The new state value.
933	*/
934	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
935	do { \
936	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
937	\| ((_uState) & UINT8_C(0x03)); \
938	} while (0)
939
940	/**
941	* Checks if the page has any virtual access handlers.
942	* @returns true/false
943	* @param pPage Pointer to the physical guest page tracking structure.
944	*/
945	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
946	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
947
948	/**
949	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
950	* virtual handlers.
951	* @returns true/false
952	* @param pPage Pointer to the physical guest page tracking structure.
953	*/
954	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
955	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
956
957
958	/**
959	* Checks if the page has any access handlers, including temporarily disabled ones.
960	* @returns true/false
961	* @param pPage Pointer to the physical guest page tracking structure.
962	*/
963	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
964	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
965	( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
966	#else
967	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
968	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
969	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
970	#endif
971
972	/**
973	* Checks if the page has any active access handlers.
974	* @returns true/false
975	* @param pPage Pointer to the physical guest page tracking structure.
976	*/
977	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
978	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
979	( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
980	#else
981	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
982	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
983	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
984	#endif
985
986	/**
987	* Checks if the page has any active access handlers catching all accesses.
988	* @returns true/false
989	* @param pPage Pointer to the physical guest page tracking structure.
990	*/
991	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
992	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
993	( ( ((pPage)->u16MiscY.au8[0] \| (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
994	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
995	#else
996	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
997	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
998	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
999	#endif
1000
1001
1002	/** @def PGM_PAGE_GET_TRACKING
1003	* Gets the packed shadow page pool tracking data associated with a guest page.
1004	* @returns uint16_t containing the data.
1005	* @param pPage Pointer to the physical guest page tracking structure.
1006	*/
1007	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1008
1009	/** @def PGM_PAGE_SET_TRACKING
1010	* Sets the packed shadow page pool tracking data associated with a guest page.
1011	* @param pPage Pointer to the physical guest page tracking structure.
1012	* @param u16TrackingData The tracking data to store.
1013	*/
1014	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1015	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1016
1017	/** @def PGM_PAGE_GET_TD_CREFS
1018	* Gets the @a cRefs tracking data member.
1019	* @returns cRefs.
1020	* @param pPage Pointer to the physical guest page tracking structure.
1021	*/
1022	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1023	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1024
1025	/** @def PGM_PAGE_GET_TD_IDX
1026	* Gets the @a idx tracking data member.
1027	* @returns idx.
1028	* @param pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_GET_TD_IDX(pPage) \
1031	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1032
1033
1034	/** Max number of locks on a page. */
1035	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1036
1037	/** Get the read lock count.
1038	* @returns count.
1039	* @param pPage Pointer to the physical guest page tracking structure.
1040	*/
1041	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1042
1043	/** Get the write lock count.
1044	* @returns count.
1045	* @param pPage Pointer to the physical guest page tracking structure.
1046	*/
1047	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1048
1049	/** Decrement the read lock counter.
1050	* @param pPage Pointer to the physical guest page tracking structure.
1051	*/
1052	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1053
1054	/** Decrement the write lock counter.
1055	* @param pPage Pointer to the physical guest page tracking structure.
1056	*/
1057	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1058
1059	/** Increment the read lock counter.
1060	* @param pPage Pointer to the physical guest page tracking structure.
1061	*/
1062	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1063
1064	/** Increment the write lock counter.
1065	* @param pPage Pointer to the physical guest page tracking structure.
1066	*/
1067	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1068
1069
1070	#if 0
1071	/** Enables sanity checking of write monitoring using CRC-32. */
1072	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1073	#endif
1074
1075	/**
1076	* Per page live save tracking data.
1077	*/
1078	typedef struct PGMLIVESAVERAMPAGE
1079	{
1080	/** Number of times it has been dirtied. */
1081	uint32_t cDirtied : 24;
1082	/** Whether it is currently dirty. */
1083	uint32_t fDirty : 1;
1084	/** Ignore the page.
1085	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1086	* deal with these after pausing the VM and DevPCI have said it bit about
1087	* remappings. */
1088	uint32_t fIgnore : 1;
1089	/** Was a ZERO page last time around. */
1090	uint32_t fZero : 1;
1091	/** Was a SHARED page last time around. */
1092	uint32_t fShared : 1;
1093	/** Whether the page is/was write monitored in a previous pass. */
1094	uint32_t fWriteMonitored : 1;
1095	/** Whether the page is/was write monitored earlier in this pass. */
1096	uint32_t fWriteMonitoredJustNow : 1;
1097	/** Bits reserved for future use. */
1098	uint32_t u2Reserved : 2;
1099	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1100	/** CRC-32 for the page. This is for internal consistency checks. */
1101	uint32_t u32Crc;
1102	#endif
1103	} PGMLIVESAVERAMPAGE;
1104	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1105	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1106	#else
1107	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1108	#endif
1109	/** Pointer to the per page live save tracking data. */
1110	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1111
1112	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1113	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1114
1115
1116	/**
1117	* Ram range for GC Phys to HC Phys conversion.
1118	*
1119	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1120	* conversions too, but we'll let MM handle that for now.
1121	*
1122	* This structure is used by linked lists in both GC and HC.
1123	*/
1124	typedef struct PGMRAMRANGE
1125	{
1126	/** Start of the range. Page aligned. */
1127	RTGCPHYS GCPhys;
1128	/** Size of the range. (Page aligned of course). */
1129	RTGCPHYS cb;
1130	/** Pointer to the next RAM range - for R3. */
1131	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1132	/** Pointer to the next RAM range - for R0. */
1133	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1134	/** Pointer to the next RAM range - for RC. */
1135	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1136	/** PGM_RAM_RANGE_FLAGS_* flags. */
1137	uint32_t fFlags;
1138	/** Last address in the range (inclusive). Page aligned (-1). */
1139	RTGCPHYS GCPhysLast;
1140	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1141	R3PTRTYPE(void *) pvR3;
1142	/** Live save per page tracking data. */
1143	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1144	/** The range description. */
1145	R3PTRTYPE(const char *) pszDesc;
1146	/** Pointer to self - R0 pointer. */
1147	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1148	/** Pointer to self - RC pointer. */
1149	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1150	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1151	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1152	/** Array of physical guest page tracking structures. */
1153	PGMPAGE aPages[1];
1154	} PGMRAMRANGE;
1155	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1156	typedef PGMRAMRANGE *PPGMRAMRANGE;
1157
1158	/** @name PGMRAMRANGE::fFlags
1159	* @{ */
1160	/** The RAM range is floating around as an independent guest mapping. */
1161	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1162	/** Ad hoc RAM range for an ROM mapping. */
1163	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1164	/** Ad hoc RAM range for an MMIO mapping. */
1165	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1166	/** Ad hoc RAM range for an MMIO2 mapping. */
1167	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1168	/** @} */
1169
1170	/** Tests if a RAM range is an ad hoc one or not.
1171	* @returns true/false.
1172	* @param pRam The RAM range.
1173	*/
1174	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1175	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1176
1177
1178	/**
1179	* Per page tracking structure for ROM image.
1180	*
1181	* A ROM image may have a shadow page, in which case we may have two pages
1182	* backing it. This structure contains the PGMPAGE for both while
1183	* PGMRAMRANGE have a copy of the active one. It is important that these
1184	* aren't out of sync in any regard other than page pool tracking data.
1185	*/
1186	typedef struct PGMROMPAGE
1187	{
1188	/** The page structure for the virgin ROM page. */
1189	PGMPAGE Virgin;
1190	/** The page structure for the shadow RAM page. */
1191	PGMPAGE Shadow;
1192	/** The current protection setting. */
1193	PGMROMPROT enmProt;
1194	/** Live save status information. Makes use of unused alignment space. */
1195	struct
1196	{
1197	/** The previous protection value. */
1198	uint8_t u8Prot;
1199	/** Written to flag set by the handler. */
1200	bool fWrittenTo;
1201	/** Whether the shadow page is dirty or not. */
1202	bool fDirty;
1203	/** Whether it was dirtied in the recently. */
1204	bool fDirtiedRecently;
1205	} LiveSave;
1206	} PGMROMPAGE;
1207	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1208	/** Pointer to a ROM page tracking structure. */
1209	typedef PGMROMPAGE *PPGMROMPAGE;
1210
1211
1212	/**
1213	* A registered ROM image.
1214	*
1215	* This is needed to keep track of ROM image since they generally intrude
1216	* into a PGMRAMRANGE. It also keeps track of additional info like the
1217	* two page sets (read-only virgin and read-write shadow), the current
1218	* state of each page.
1219	*
1220	* Because access handlers cannot easily be executed in a different
1221	* context, the ROM ranges needs to be accessible and in all contexts.
1222	*/
1223	typedef struct PGMROMRANGE
1224	{
1225	/** Pointer to the next range - R3. */
1226	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1227	/** Pointer to the next range - R0. */
1228	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1229	/** Pointer to the next range - RC. */
1230	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1231	/** Pointer alignment */
1232	RTRCPTR RCPtrAlignment;
1233	/** Address of the range. */
1234	RTGCPHYS GCPhys;
1235	/** Address of the last byte in the range. */
1236	RTGCPHYS GCPhysLast;
1237	/** Size of the range. */
1238	RTGCPHYS cb;
1239	/** The flags (PGMPHYS_ROM_FLAGS_). /
1240	uint32_t fFlags;
1241	/** The saved state range ID. */
1242	uint8_t idSavedState;
1243	/** Alignment padding. */
1244	uint8_t au8Alignment[3];
1245	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1246	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1247	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1248	* This is used for strictness checks. */
1249	R3PTRTYPE(const void *) pvOriginal;
1250	/** The ROM description. */
1251	R3PTRTYPE(const char *) pszDesc;
1252	/** The per page tracking structures. */
1253	PGMROMPAGE aPages[1];
1254	} PGMROMRANGE;
1255	/** Pointer to a ROM range. */
1256	typedef PGMROMRANGE *PPGMROMRANGE;
1257
1258
1259	/**
1260	* Live save per page data for an MMIO2 page.
1261	*
1262	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1263	* of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1264	* CRC-32 for detecting changes as well as special handling of zero pages. This
1265	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1266	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1267	* because of speed (2.5x and 6x slower).)
1268	*
1269	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1270	* save but normally is disabled. Since we can write monitore guest
1271	* accesses on our own, we only need this for host accesses. Shouldn't be
1272	* too difficult for DevVGA, VMMDev might be doable, the planned
1273	* networking fun will be fun since it involves ring-0.
1274	*/
1275	typedef struct PGMLIVESAVEMMIO2PAGE
1276	{
1277	/** Set if the page is considered dirty. */
1278	bool fDirty;
1279	/** The number of scans this page has remained unchanged for.
1280	* Only updated for dirty pages. */
1281	uint8_t cUnchangedScans;
1282	/** Whether this page was zero at the last scan. */
1283	bool fZero;
1284	/** Alignment padding. */
1285	bool fReserved;
1286	/** CRC-32 for the first half of the page.
1287	* This is used together with u32CrcH2 to quickly detect changes in the page
1288	* during the non-final passes. */
1289	uint32_t u32CrcH1;
1290	/** CRC-32 for the second half of the page. */
1291	uint32_t u32CrcH2;
1292	/** SHA-1 for the saved page.
1293	* This is used in the final pass to skip pages without changes. */
1294	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1295	} PGMLIVESAVEMMIO2PAGE;
1296	/** Pointer to a live save status data for an MMIO2 page. */
1297	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1298
1299	/**
1300	* A registered MMIO2 (= Device RAM) range.
1301	*
1302	* There are a few reason why we need to keep track of these
1303	* registrations. One of them is the deregistration & cleanup stuff,
1304	* while another is that the PGMRAMRANGE associated with such a region may
1305	* have to be removed from the ram range list.
1306	*
1307	* Overlapping with a RAM range has to be 100% or none at all. The pages
1308	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1309	* will be raised if a partial overlap or an overlap of ROM pages is
1310	* encountered. On an overlap we will free all the existing RAM pages and
1311	* put in the ram range pages instead.
1312	*/
1313	typedef struct PGMMMIO2RANGE
1314	{
1315	/** The owner of the range. (a device) */
1316	PPDMDEVINSR3 pDevInsR3;
1317	/** Pointer to the ring-3 mapping of the allocation. */
1318	RTR3PTR pvR3;
1319	/** Pointer to the next range - R3. */
1320	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1321	/** Whether it's mapped or not. */
1322	bool fMapped;
1323	/** Whether it's overlapping or not. */
1324	bool fOverlapping;
1325	/** The PCI region number.
1326	* @remarks This ASSUMES that nobody will ever really need to have multiple
1327	* PCI devices with matching MMIO region numbers on a single device. */
1328	uint8_t iRegion;
1329	/** The saved state range ID. */
1330	uint8_t idSavedState;
1331	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1332	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1333	/** Live save per page tracking data. */
1334	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1335	/** The associated RAM range. */
1336	PGMRAMRANGE RamRange;
1337	} PGMMMIO2RANGE;
1338	/** Pointer to a MMIO2 range. */
1339	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1340
1341
1342
1343
1344	/**
1345	* PGMPhysRead/Write cache entry
1346	*/
1347	typedef struct PGMPHYSCACHEENTRY
1348	{
1349	/** R3 pointer to physical page. */
1350	R3PTRTYPE(uint8_t *) pbR3;
1351	/** GC Physical address for cache entry */
1352	RTGCPHYS GCPhys;
1353	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1354	RTGCPHYS u32Padding0; /*< alignment padding. /
1355	#endif
1356	} PGMPHYSCACHEENTRY;
1357
1358	/**
1359	* PGMPhysRead/Write cache to reduce REM memory access overhead
1360	*/
1361	typedef struct PGMPHYSCACHE
1362	{
1363	/** Bitmap of valid cache entries */
1364	uint64_t aEntries;
1365	/** Cache entries */
1366	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1367	} PGMPHYSCACHE;
1368
1369
1370	/** Pointer to an allocation chunk ring-3 mapping. */
1371	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1372	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1373	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1374
1375	/**
1376	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1377	*
1378	* The primary tree (Core) uses the chunk id as key.
1379	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1380	*/
1381	typedef struct PGMCHUNKR3MAP
1382	{
1383	/** The key is the chunk id. */
1384	AVLU32NODECORE Core;
1385	/** The key is the ageing sequence number. */
1386	AVLLU32NODECORE AgeCore;
1387	/** The current age thingy. */
1388	uint32_t iAge;
1389	/** The current reference count. */
1390	uint32_t volatile cRefs;
1391	/** The current permanent reference count. */
1392	uint32_t volatile cPermRefs;
1393	/** The mapping address. */
1394	void *pv;
1395	} PGMCHUNKR3MAP;
1396
1397	/**
1398	* Allocation chunk ring-3 mapping TLB entry.
1399	*/
1400	typedef struct PGMCHUNKR3MAPTLBE
1401	{
1402	/** The chunk id. */
1403	uint32_t volatile idChunk;
1404	#if HC_ARCH_BITS == 64
1405	uint32_t u32Padding; /*< alignment padding. /
1406	#endif
1407	/** The chunk map. */
1408	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1409	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1410	#else
1411	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1412	#endif
1413	} PGMCHUNKR3MAPTLBE;
1414	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1415	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1416
1417	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1418	* @remark Must be a power of two value. */
1419	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1420
1421	/**
1422	* Allocation chunk ring-3 mapping TLB.
1423	*
1424	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1425	* At first glance this might look kinda odd since AVL trees are
1426	* supposed to give the most optimial lookup times of all trees
1427	* due to their balancing. However, take a tree with 1023 nodes
1428	* in it, that's 10 levels, meaning that most searches has to go
1429	* down 9 levels before they find what they want. This isn't fast
1430	* compared to a TLB hit. There is the factor of cache misses,
1431	* and of course the problem with trees and branch prediction.
1432	* This is why we use TLBs in front of most of the trees.
1433	*
1434	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1435	* difficult when we switch to the new inlined AVL trees (from kStuff).
1436	*/
1437	typedef struct PGMCHUNKR3MAPTLB
1438	{
1439	/** The TLB entries. */
1440	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1441	} PGMCHUNKR3MAPTLB;
1442
1443	/**
1444	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1445	* @returns Chunk TLB index.
1446	* @param idChunk The Chunk ID.
1447	*/
1448	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1449
1450
1451	/**
1452	* Ring-3 guest page mapping TLB entry.
1453	* @remarks used in ring-0 as well at the moment.
1454	*/
1455	typedef struct PGMPAGER3MAPTLBE
1456	{
1457	/** Address of the page. */
1458	RTGCPHYS volatile GCPhys;
1459	/** The guest page. */
1460	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1461	R3PTRTYPE(PPGMPAGE) volatile pPage;
1462	#else
1463	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1464	#endif
1465	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1466	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1467	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1468	#else
1469	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1470	#endif
1471	/** The address */
1472	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1473	R3PTRTYPE(void *) volatile pv;
1474	#else
1475	R3R0PTRTYPE(void *) volatile pv;
1476	#endif
1477	#if HC_ARCH_BITS == 32
1478	uint32_t u32Padding; /*< alignment padding. /
1479	#endif
1480	} PGMPAGER3MAPTLBE;
1481	/** Pointer to an entry in the HC physical TLB. */
1482	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1483
1484
1485	/** The number of entries in the ring-3 guest page mapping TLB.
1486	* @remarks The value must be a power of two. */
1487	#define PGM_PAGER3MAPTLB_ENTRIES 256
1488
1489	/**
1490	* Ring-3 guest page mapping TLB.
1491	* @remarks used in ring-0 as well at the moment.
1492	*/
1493	typedef struct PGMPAGER3MAPTLB
1494	{
1495	/** The TLB entries. */
1496	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1497	} PGMPAGER3MAPTLB;
1498	/** Pointer to the ring-3 guest page mapping TLB. */
1499	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1500
1501	/**
1502	* Calculates the index of the TLB entry for the specified guest page.
1503	* @returns Physical TLB index.
1504	* @param GCPhys The guest physical address.
1505	*/
1506	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1507
1508
1509	/**
1510	* Mapping cache usage set entry.
1511	*
1512	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1513	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1514	* cache. If it's extended to include ring-3, well, then something will
1515	* have be changed here...
1516	*/
1517	typedef struct PGMMAPSETENTRY
1518	{
1519	/** The mapping cache index. */
1520	uint16_t iPage;
1521	/** The number of references.
1522	* The max is UINT16_MAX - 1. */
1523	uint16_t cRefs;
1524	#if HC_ARCH_BITS == 64
1525	uint32_t alignment;
1526	#endif
1527	/** Pointer to the page. */
1528	RTR0PTR pvPage;
1529	/** The physical address for this entry. */
1530	RTHCPHYS HCPhys;
1531	} PGMMAPSETENTRY;
1532	/** Pointer to a mapping cache usage set entry. */
1533	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1534
1535	/**
1536	* Mapping cache usage set.
1537	*
1538	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1539	* done during exits / traps. The set is
1540	*/
1541	typedef struct PGMMAPSET
1542	{
1543	/** The number of occupied entries.
1544	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1545	* dynamic mappings. */
1546	uint32_t cEntries;
1547	/** The start of the current subset.
1548	* This is UINT32_MAX if no subset is currently open. */
1549	uint32_t iSubset;
1550	/** The index of the current CPU, only valid if the set is open. */
1551	int32_t iCpu;
1552	uint32_t alignment;
1553	/** The entries. */
1554	PGMMAPSETENTRY aEntries[64];
1555	/** HCPhys -> iEntry fast lookup table.
1556	* Use PGMMAPSET_HASH for hashing.
1557	* The entries may or may not be valid, check against cEntries. */
1558	uint8_t aiHashTable[128];
1559	} PGMMAPSET;
1560	AssertCompileSizeAlignment(PGMMAPSET, 8);
1561	/** Pointer to the mapping cache set. */
1562	typedef PGMMAPSET *PPGMMAPSET;
1563
1564	/** PGMMAPSET::cEntries value for a closed set. */
1565	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1566
1567	/** Hash function for aiHashTable. */
1568	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1569
1570	/** The max fill size (strict builds). */
1571	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1572
1573
1574	/** @name Context neutrual page mapper TLB.
1575	*
1576	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1577	* code is writting in a kind of context neutrual way. Time will show whether
1578	* this actually makes sense or not...
1579	*
1580	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1581	* context ends up using a global mapping cache on some platforms
1582	* (darwin).
1583	*
1584	* @{ */
1585	/** @typedef PPGMPAGEMAPTLB
1586	* The page mapper TLB pointer type for the current context. */
1587	/** @typedef PPGMPAGEMAPTLB
1588	* The page mapper TLB entry pointer type for the current context. */
1589	/** @typedef PPGMPAGEMAPTLB
1590	* The page mapper TLB entry pointer pointer type for the current context. */
1591	/** @def PGM_PAGEMAPTLB_ENTRIES
1592	* The number of TLB entries in the page mapper TLB for the current context. */
1593	/** @def PGM_PAGEMAPTLB_IDX
1594	* Calculate the TLB index for a guest physical address.
1595	* @returns The TLB index.
1596	* @param GCPhys The guest physical address. */
1597	/** @typedef PPGMPAGEMAP
1598	* Pointer to a page mapper unit for current context. */
1599	/** @typedef PPPGMPAGEMAP
1600	* Pointer to a page mapper unit pointer for current context. */
1601	#ifdef IN_RC
1602	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1603	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1604	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1605	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1606	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1607	typedef void * PPGMPAGEMAP;
1608	typedef void ** PPPGMPAGEMAP;
1609	//#elif IN_RING0
1610	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1611	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1612	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1613	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1614	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1615	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1616	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1617	#else
1618	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1619	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1620	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1621	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1622	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1623	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1624	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1625	#endif
1626	/** @} */
1627
1628
1629	/** @name PGM Pool Indexes.
1630	* Aka. the unique shadow page identifier.
1631	* @{ */
1632	/** NIL page pool IDX. */
1633	#define NIL_PGMPOOL_IDX 0
1634	/** The first normal index. */
1635	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1636	/** Page directory (32-bit root). */
1637	#define PGMPOOL_IDX_PD 1
1638	/** Page Directory Pointer Table (PAE root). */
1639	#define PGMPOOL_IDX_PDPT 2
1640	/** AMD64 CR3 level index.*/
1641	#define PGMPOOL_IDX_AMD64_CR3 3
1642	/** Nested paging root.*/
1643	#define PGMPOOL_IDX_NESTED_ROOT 4
1644	/** The first normal index. */
1645	#define PGMPOOL_IDX_FIRST 5
1646	/** The last valid index. (inclusive, 14 bits) */
1647	#define PGMPOOL_IDX_LAST 0x3fff
1648	/** @} */
1649
1650	/** The NIL index for the parent chain. */
1651	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1652	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1653
1654	/**
1655	* Node in the chain linking a shadowed page to it's parent (user).
1656	*/
1657	#pragma pack(1)
1658	typedef struct PGMPOOLUSER
1659	{
1660	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1661	uint16_t iNext;
1662	/** The user page index. */
1663	uint16_t iUser;
1664	/** Index into the user table. */
1665	uint32_t iUserTable;
1666	} PGMPOOLUSER, *PPGMPOOLUSER;
1667	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1668	#pragma pack()
1669
1670
1671	/** The NIL index for the phys ext chain. */
1672	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1673
1674	/**
1675	* Node in the chain of physical cross reference extents.
1676	* @todo Calling this an 'extent' is not quite right, find a better name.
1677	*/
1678	#pragma pack(1)
1679	typedef struct PGMPOOLPHYSEXT
1680	{
1681	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1682	uint16_t iNext;
1683	/** The user page index. */
1684	uint16_t aidx[3];
1685	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1686	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1687	#pragma pack()
1688
1689
1690	/**
1691	* The kind of page that's being shadowed.
1692	*/
1693	typedef enum PGMPOOLKIND
1694	{
1695	/** The virtual invalid 0 entry. */
1696	PGMPOOLKIND_INVALID = 0,
1697	/** The entry is free (=unused). */
1698	PGMPOOLKIND_FREE,
1699
1700	/** Shw: 32-bit page table; Gst: no paging */
1701	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1702	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1703	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1704	/** Shw: 32-bit page table; Gst: 4MB page. */
1705	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1706	/** Shw: PAE page table; Gst: no paging */
1707	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1708	/** Shw: PAE page table; Gst: 32-bit page table. */
1709	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1710	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1711	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1712	/** Shw: PAE page table; Gst: PAE page table. */
1713	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1714	/** Shw: PAE page table; Gst: 2MB page. */
1715	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1716
1717	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1718	PGMPOOLKIND_32BIT_PD,
1719	/** Shw: 32-bit page directory. Gst: no paging. */
1720	PGMPOOLKIND_32BIT_PD_PHYS,
1721	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1722	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1723	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1724	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1725	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1726	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1727	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1728	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1729	/** Shw: PAE page directory; Gst: PAE page directory. */
1730	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1731	/** Shw: PAE page directory; Gst: no paging. */
1732	PGMPOOLKIND_PAE_PD_PHYS,
1733
1734	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1735	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1736	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1737	PGMPOOLKIND_PAE_PDPT,
1738	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1739	PGMPOOLKIND_PAE_PDPT_PHYS,
1740
1741	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1742	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1743	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1744	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1745	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1746	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1747	/** Shw: 64-bit page directory table; Gst: no paging */
1748	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1749
1750	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1751	PGMPOOLKIND_64BIT_PML4,
1752
1753	/** Shw: EPT page directory pointer table; Gst: no paging */
1754	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1755	/** Shw: EPT page directory table; Gst: no paging */
1756	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1757	/** Shw: EPT page table; Gst: no paging */
1758	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1759
1760	/** Shw: Root Nested paging table. */
1761	PGMPOOLKIND_ROOT_NESTED,
1762
1763	/** The last valid entry. */
1764	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1765	} PGMPOOLKIND;
1766
1767	/**
1768	* The access attributes of the page; only applies to big pages.
1769	*/
1770	typedef enum
1771	{
1772	PGMPOOLACCESS_DONTCARE = 0,
1773	PGMPOOLACCESS_USER_RW,
1774	PGMPOOLACCESS_USER_R,
1775	PGMPOOLACCESS_USER_RW_NX,
1776	PGMPOOLACCESS_USER_R_NX,
1777	PGMPOOLACCESS_SUPERVISOR_RW,
1778	PGMPOOLACCESS_SUPERVISOR_R,
1779	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1780	PGMPOOLACCESS_SUPERVISOR_R_NX
1781	} PGMPOOLACCESS;
1782
1783	/**
1784	* The tracking data for a page in the pool.
1785	*/
1786	typedef struct PGMPOOLPAGE
1787	{
1788	/** AVL node code with the (R3) physical address of this page. */
1789	AVLOHCPHYSNODECORE Core;
1790	/** Pointer to the R3 mapping of the page. */
1791	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1792	R3PTRTYPE(void *) pvPageR3;
1793	#else
1794	R3R0PTRTYPE(void *) pvPageR3;
1795	#endif
1796	/** The guest physical address. */
1797	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1798	uint32_t Alignment0;
1799	#endif
1800	RTGCPHYS GCPhys;
1801
1802	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1803	RTGCPTR pvLastAccessHandlerRip;
1804	RTGCPTR pvLastAccessHandlerFault;
1805	uint64_t cLastAccessHandlerCount;
1806
1807	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1808	uint8_t enmKind;
1809	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1810	uint8_t enmAccess;
1811	/** The index of this page. */
1812	uint16_t idx;
1813	/** The next entry in the list this page currently resides in.
1814	* It's either in the free list or in the GCPhys hash. */
1815	uint16_t iNext;
1816	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1817	uint16_t iUserHead;
1818	/** The number of present entries. */
1819	uint16_t cPresent;
1820	/** The first entry in the table which is present. */
1821	uint16_t iFirstPresent;
1822	/** The number of modifications to the monitored page. */
1823	uint16_t cModifications;
1824	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1825	uint16_t iModifiedNext;
1826	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1827	uint16_t iModifiedPrev;
1828	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1829	uint16_t iMonitoredNext;
1830	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1831	uint16_t iMonitoredPrev;
1832	/** The next page in the age list. */
1833	uint16_t iAgeNext;
1834	/** The previous page in the age list. */
1835	uint16_t iAgePrev;
1836	/** Used to indicate that the page is zeroed. */
1837	bool fZeroed;
1838	/** Used to indicate that a PT has non-global entries. */
1839	bool fSeenNonGlobal;
1840	/** Used to indicate that we're monitoring writes to the guest page. */
1841	bool fMonitored;
1842	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1843	* (All pages are in the age list.) */
1844	bool fCached;
1845	/** This is used by the R3 access handlers when invoked by an async thread.
1846	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1847	bool volatile fReusedFlushPending;
1848	/** Used to mark the page as dirty (write monitoring if temporarily off. */
1849	bool fDirty;
1850
1851	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1852	uint32_t cLocked;
1853	uint32_t idxDirty;
1854	RTGCPTR pvDirtyFault;
1855	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1856	/** Pointer to a const pool page. */
1857	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1858
1859
1860	/** The hash table size. */
1861	# define PGMPOOL_HASH_SIZE 0x40
1862	/** The hash function. */
1863	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1864
1865
1866	/**
1867	* The shadow page pool instance data.
1868	*
1869	* It's all one big allocation made at init time, except for the
1870	* pages that is. The user nodes follows immediatly after the
1871	* page structures.
1872	*/
1873	typedef struct PGMPOOL
1874	{
1875	/** The VM handle - R3 Ptr. */
1876	PVMR3 pVMR3;
1877	/** The VM handle - R0 Ptr. */
1878	PVMR0 pVMR0;
1879	/** The VM handle - RC Ptr. */
1880	PVMRC pVMRC;
1881	/** The max pool size. This includes the special IDs. */
1882	uint16_t cMaxPages;
1883	/** The current pool size. */
1884	uint16_t cCurPages;
1885	/** The head of the free page list. */
1886	uint16_t iFreeHead;
1887	/* Padding. */
1888	uint16_t u16Padding;
1889	/** Head of the chain of free user nodes. */
1890	uint16_t iUserFreeHead;
1891	/** The number of user nodes we've allocated. */
1892	uint16_t cMaxUsers;
1893	/** The number of present page table entries in the entire pool. */
1894	uint32_t cPresent;
1895	/** Pointer to the array of user nodes - RC pointer. */
1896	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1897	/** Pointer to the array of user nodes - R3 pointer. */
1898	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1899	/** Pointer to the array of user nodes - R0 pointer. */
1900	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1901	/** Head of the chain of free phys ext nodes. */
1902	uint16_t iPhysExtFreeHead;
1903	/** The number of user nodes we've allocated. */
1904	uint16_t cMaxPhysExts;
1905	/** Pointer to the array of physical xref extent - RC pointer. */
1906	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1907	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1908	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1909	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1910	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1911	/** Hash table for GCPhys addresses. */
1912	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1913	/** The head of the age list. */
1914	uint16_t iAgeHead;
1915	/** The tail of the age list. */
1916	uint16_t iAgeTail;
1917	/** Set if the cache is enabled. */
1918	bool fCacheEnabled;
1919	/** Alignment padding. */
1920	bool afPadding1[3];
1921	/** Head of the list of modified pages. */
1922	uint16_t iModifiedHead;
1923	/** The current number of modified pages. */
1924	uint16_t cModifiedPages;
1925	/** Access handler, RC. */
1926	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1927	/** Access handler, R0. */
1928	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1929	/** Access handler, R3. */
1930	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1931	/** The access handler description (R3 ptr). */
1932	R3PTRTYPE(const char *) pszAccessHandler;
1933	# if HC_ARCH_BITS == 32
1934	/** Alignment padding. */
1935	uint32_t u32Padding2;
1936	# endif
1937	/* Next available slot. */
1938	uint32_t idxFreeDirtyPage;
1939	/* Number of active dirty pages. */
1940	uint32_t cDirtyPages;
1941	/* Array of current dirty pgm pool page indices. */
1942	uint16_t aIdxDirtyPages[16];
1943	uint64_t aDirtyPages[16][512];
1944	/** The number of pages currently in use. */
1945	uint16_t cUsedPages;
1946	#ifdef VBOX_WITH_STATISTICS
1947	/** The high water mark for cUsedPages. */
1948	uint16_t cUsedPagesHigh;
1949	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1950	/** Profiling pgmPoolAlloc(). */
1951	STAMPROFILEADV StatAlloc;
1952	/** Profiling pgmR3PoolClearDoIt(). */
1953	STAMPROFILE StatClearAll;
1954	/** Profiling pgmR3PoolReset(). */
1955	STAMPROFILE StatR3Reset;
1956	/** Profiling pgmPoolFlushPage(). */
1957	STAMPROFILE StatFlushPage;
1958	/** Profiling pgmPoolFree(). */
1959	STAMPROFILE StatFree;
1960	/** Counting explicit flushes by PGMPoolFlushPage(). */
1961	STAMCOUNTER StatForceFlushPage;
1962	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1963	STAMCOUNTER StatForceFlushDirtyPage;
1964	/** Counting flushes for reused pages. */
1965	STAMCOUNTER StatForceFlushReused;
1966	/** Profiling time spent zeroing pages. */
1967	STAMPROFILE StatZeroPage;
1968	/** Profiling of pgmPoolTrackDeref. */
1969	STAMPROFILE StatTrackDeref;
1970	/** Profiling pgmTrackFlushGCPhysPT. */
1971	STAMPROFILE StatTrackFlushGCPhysPT;
1972	/** Profiling pgmTrackFlushGCPhysPTs. */
1973	STAMPROFILE StatTrackFlushGCPhysPTs;
1974	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1975	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1976	/** Number of times we've been out of user records. */
1977	STAMCOUNTER StatTrackFreeUpOneUser;
1978	/** Nr of flushed entries. */
1979	STAMCOUNTER StatTrackFlushEntry;
1980	/** Nr of updated entries. */
1981	STAMCOUNTER StatTrackFlushEntryKeep;
1982	/** Profiling deref activity related tracking GC physical pages. */
1983	STAMPROFILE StatTrackDerefGCPhys;
1984	/** Number of linear searches for a HCPhys in the ram ranges. */
1985	STAMCOUNTER StatTrackLinearRamSearches;
1986	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1987	STAMCOUNTER StamTrackPhysExtAllocFailures;
1988	/** Profiling the RC/R0 access handler. */
1989	STAMPROFILE StatMonitorRZ;
1990	/** Times we've failed interpreting the instruction. */
1991	STAMCOUNTER StatMonitorRZEmulateInstr;
1992	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1993	STAMPROFILE StatMonitorRZFlushPage;
1994	/* Times we've detected a page table reinit. */
1995	STAMCOUNTER StatMonitorRZFlushReinit;
1996	/** Counting flushes for pages that are modified too often. */
1997	STAMCOUNTER StatMonitorRZFlushModOverflow;
1998	/** Times we've detected fork(). */
1999	STAMCOUNTER StatMonitorRZFork;
2000	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2001	STAMPROFILE StatMonitorRZHandled;
2002	/** Times we've failed interpreting a patch code instruction. */
2003	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2004	/** Times we've failed interpreting a patch code instruction during flushing. */
2005	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2006	/** The number of times we've seen rep prefixes we can't handle. */
2007	STAMCOUNTER StatMonitorRZRepPrefix;
2008	/** Profiling the REP STOSD cases we've handled. */
2009	STAMPROFILE StatMonitorRZRepStosd;
2010	/** Nr of handled PT faults. */
2011	STAMCOUNTER StatMonitorRZFaultPT;
2012	/** Nr of handled PD faults. */
2013	STAMCOUNTER StatMonitorRZFaultPD;
2014	/** Nr of handled PDPT faults. */
2015	STAMCOUNTER StatMonitorRZFaultPDPT;
2016	/** Nr of handled PML4 faults. */
2017	STAMCOUNTER StatMonitorRZFaultPML4;
2018
2019	/** Profiling the R3 access handler. */
2020	STAMPROFILE StatMonitorR3;
2021	/** Times we've failed interpreting the instruction. */
2022	STAMCOUNTER StatMonitorR3EmulateInstr;
2023	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2024	STAMPROFILE StatMonitorR3FlushPage;
2025	/* Times we've detected a page table reinit. */
2026	STAMCOUNTER StatMonitorR3FlushReinit;
2027	/** Counting flushes for pages that are modified too often. */
2028	STAMCOUNTER StatMonitorR3FlushModOverflow;
2029	/** Times we've detected fork(). */
2030	STAMCOUNTER StatMonitorR3Fork;
2031	/** Profiling the R3 access we've handled (except REP STOSD). */
2032	STAMPROFILE StatMonitorR3Handled;
2033	/** The number of times we've seen rep prefixes we can't handle. */
2034	STAMCOUNTER StatMonitorR3RepPrefix;
2035	/** Profiling the REP STOSD cases we've handled. */
2036	STAMPROFILE StatMonitorR3RepStosd;
2037	/** Nr of handled PT faults. */
2038	STAMCOUNTER StatMonitorR3FaultPT;
2039	/** Nr of handled PD faults. */
2040	STAMCOUNTER StatMonitorR3FaultPD;
2041	/** Nr of handled PDPT faults. */
2042	STAMCOUNTER StatMonitorR3FaultPDPT;
2043	/** Nr of handled PML4 faults. */
2044	STAMCOUNTER StatMonitorR3FaultPML4;
2045	/** The number of times we're called in an async thread an need to flush. */
2046	STAMCOUNTER StatMonitorR3Async;
2047	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2048	STAMCOUNTER StatResetDirtyPages;
2049	/** Times we've called pgmPoolAddDirtyPage. */
2050	STAMCOUNTER StatDirtyPage;
2051	/** Times we've had to flush duplicates for dirty page management. */
2052	STAMCOUNTER StatDirtyPageDupFlush;
2053	/** Times we've had to flush because of overflow. */
2054	STAMCOUNTER StatDirtyPageOverFlowFlush;
2055
2056	/** The high wather mark for cModifiedPages. */
2057	uint16_t cModifiedPagesHigh;
2058	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
2059
2060	/** The number of cache hits. */
2061	STAMCOUNTER StatCacheHits;
2062	/** The number of cache misses. */
2063	STAMCOUNTER StatCacheMisses;
2064	/** The number of times we've got a conflict of 'kind' in the cache. */
2065	STAMCOUNTER StatCacheKindMismatches;
2066	/** Number of times we've been out of pages. */
2067	STAMCOUNTER StatCacheFreeUpOne;
2068	/** The number of cacheable allocations. */
2069	STAMCOUNTER StatCacheCacheable;
2070	/** The number of uncacheable allocations. */
2071	STAMCOUNTER StatCacheUncacheable;
2072	#else
2073	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
2074	#endif
2075	/** The AVL tree for looking up a page by its HC physical address. */
2076	AVLOHCPHYSTREE HCPhysTree;
2077	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
2078	/** Array of pages. (cMaxPages in length)
2079	* The Id is the index into thist array.
2080	*/
2081	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2082	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2083	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2084	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2085	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2086	#ifdef VBOX_WITH_STATISTICS
2087	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2088	#endif
2089	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2090
2091
2092	/** @def PGMPOOL_PAGE_2_PTR
2093	* Maps a pool page pool into the current context.
2094	*
2095	* @returns VBox status code.
2096	* @param pVM The VM handle.
2097	* @param pPage The pool page.
2098	*
2099	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2100	* small page window employeed by that function. Be careful.
2101	* @remark There is no need to assert on the result.
2102	*/
2103	#if defined(IN_RC)
2104	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2105	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2106	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2107	#elif defined(VBOX_STRICT)
2108	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2109	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2110	{
2111	Assert(pPage && pPage->pvPageR3);
2112	return pPage->pvPageR3;
2113	}
2114	#else
2115	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2116	#endif
2117
2118	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2119	* Maps a pool page pool into the current context.
2120	*
2121	* @returns VBox status code.
2122	* @param pPGM Pointer to the PGM instance data.
2123	* @param pPage The pool page.
2124	*
2125	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2126	* small page window employeed by that function. Be careful.
2127	* @remark There is no need to assert on the result.
2128	*/
2129	#if defined(IN_RC)
2130	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2131	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2132	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2133	#else
2134	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2135	#endif
2136
2137	/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2138	* Maps a pool page pool into the current context.
2139	*
2140	* @returns VBox status code.
2141	* @param pPGM Pointer to the PGMCPU instance data.
2142	* @param pPage The pool page.
2143	*
2144	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2145	* small page window employeed by that function. Be careful.
2146	* @remark There is no need to assert on the result.
2147	*/
2148	#if defined(IN_RC)
2149	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2150	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2151	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2152	#else
2153	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2154	#endif
2155
2156
2157	/** @name Per guest page tracking data.
2158	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2159	* is to use more bits for it and split it up later on. But for now we'll play
2160	* safe and change as little as possible.
2161	*
2162	* The 16-bit word has two parts:
2163	*
2164	* The first 14-bit forms the @a idx field. It is either the index of a page in
2165	* the shadow page pool, or and index into the extent list.
2166	*
2167	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2168	* shadow page pool references to the page. If cRefs equals
2169	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2170	* (misnomer) table and not the shadow page pool.
2171	*
2172	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2173	* the 16-bit word.
2174	*
2175	* @{ */
2176	/** The shift count for getting to the cRefs part. */
2177	#define PGMPOOL_TD_CREFS_SHIFT 14
2178	/** The mask applied after shifting the tracking data down by
2179	* PGMPOOL_TD_CREFS_SHIFT. */
2180	#define PGMPOOL_TD_CREFS_MASK 0x3
2181	/** The cRef value used to indiciate that the idx is the head of a
2182	* physical cross reference list. */
2183	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2184	/** The shift used to get idx. */
2185	#define PGMPOOL_TD_IDX_SHIFT 0
2186	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2187	#define PGMPOOL_TD_IDX_MASK 0x3fff
2188	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2189	* simply too many mappings of this page. */
2190	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2191
2192	/** @def PGMPOOL_TD_MAKE
2193	* Makes a 16-bit tracking data word.
2194	*
2195	* @returns tracking data.
2196	* @param cRefs The @a cRefs field. Must be within bounds!
2197	* @param idx The @a idx field. Must also be within bounds! */
2198	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2199
2200	/** @def PGMPOOL_TD_GET_CREFS
2201	* Get the @a cRefs field from a tracking data word.
2202	*
2203	* @returns The @a cRefs field
2204	* @param u16 The tracking data word. */
2205	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2206
2207	/** @def PGMPOOL_TD_GET_IDX
2208	* Get the @a idx field from a tracking data word.
2209	*
2210	* @returns The @a idx field
2211	* @param u16 The tracking data word. */
2212	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2213	/** @} */
2214
2215
2216	/**
2217	* Trees are using self relative offsets as pointers.
2218	* So, all its data, including the root pointer, must be in the heap for HC and GC
2219	* to have the same layout.
2220	*/
2221	typedef struct PGMTREES
2222	{
2223	/** Physical access handlers (AVL range+offsetptr tree). */
2224	AVLROGCPHYSTREE PhysHandlers;
2225	/** Virtual access handlers (AVL range + GC ptr tree). */
2226	AVLROGCPTRTREE VirtHandlers;
2227	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2228	AVLROGCPHYSTREE PhysToVirtHandlers;
2229	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2230	AVLROGCPTRTREE HyperVirtHandlers;
2231	} PGMTREES;
2232	/** Pointer to PGM trees. */
2233	typedef PGMTREES *PPGMTREES;
2234
2235
2236	/** @name Paging mode macros
2237	* @{ */
2238	#ifdef IN_RC
2239	# define PGM_CTX(a,b) a##RC##b
2240	# define PGM_CTX_STR(a,b) a "GC" b
2241	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2242	#else
2243	# ifdef IN_RING3
2244	# define PGM_CTX(a,b) a##R3##b
2245	# define PGM_CTX_STR(a,b) a "R3" b
2246	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2247	# else
2248	# define PGM_CTX(a,b) a##R0##b
2249	# define PGM_CTX_STR(a,b) a "R0" b
2250	# define PGM_CTX_DECL(type) VMMDECL(type)
2251	# endif
2252	#endif
2253
2254	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2255	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2256	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2257	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2258	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2259	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2260	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2261	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2262	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2263	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2264	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2265	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2266	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2267	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2268	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2269	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2270	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2271
2272	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2273	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2274	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2275	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2276	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2277	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2278	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2279	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2280	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2281	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2282	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2283	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2284	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2285	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2286	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2287	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2288	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2289
2290	/* Shw_Gst */
2291	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2292	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2293	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2294	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2295	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2296	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2297	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2298	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2299	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2300	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2301	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2302	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2303	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2304	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2305	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2306	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2307	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2308	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2309	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2310
2311	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2312	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2313	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2314	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2315	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2316	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2317	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2318	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2319	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2320	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2321	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2322	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2323	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2324	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2325	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2326	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2327	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2328	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2329	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2330	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2331	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2332	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2333	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2334	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2335	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2336	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2337	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2338	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2339	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2340	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2341	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2342	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2343	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2344	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2345	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2346	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2347	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2348
2349	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2350	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2351	/** @} */
2352
2353	/**
2354	* Data for each paging mode.
2355	*/
2356	typedef struct PGMMODEDATA
2357	{
2358	/** The guest mode type. */
2359	uint32_t uGstType;
2360	/** The shadow mode type. */
2361	uint32_t uShwType;
2362
2363	/** @name Function pointers for Shadow paging.
2364	* @{
2365	*/
2366	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2367	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2368	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2369	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2370
2371	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2372	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2373
2374	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2375	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2376	/** @} */
2377
2378	/** @name Function pointers for Guest paging.
2379	* @{
2380	*/
2381	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2382	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2383	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2384	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2385	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2386	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2387	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2388	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2389	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2390	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2391	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2392	/** @} */
2393
2394	/** @name Function pointers for Both Shadow and Guest paging.
2395	* @{
2396	*/
2397	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2398	/* no pfnR3BthTrap0eHandler */
2399	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2400	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2401	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2402	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2403	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2404	#ifdef VBOX_STRICT
2405	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2406	#endif
2407	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2408	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2409
2410	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2411	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2412	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2413	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2414	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2415	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2416	#ifdef VBOX_STRICT
2417	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2418	#endif
2419	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2420	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2421
2422	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2423	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2424	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2425	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2426	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2427	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2428	#ifdef VBOX_STRICT
2429	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2430	#endif
2431	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2432	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2433	/** @} */
2434	} PGMMODEDATA, *PPGMMODEDATA;
2435
2436
2437
2438	/**
2439	* Converts a PGM pointer into a VM pointer.
2440	* @returns Pointer to the VM structure the PGM is part of.
2441	* @param pPGM Pointer to PGM instance data.
2442	*/
2443	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2444
2445	/**
2446	* PGM Data (part of VM)
2447	*/
2448	typedef struct PGM
2449	{
2450	/** Offset to the VM structure. */
2451	RTINT offVM;
2452	/** Offset of the PGMCPU structure relative to VMCPU. */
2453	RTINT offVCpuPGM;
2454
2455	/** @cfgm{RamPreAlloc, boolean, false}
2456	* Indicates whether the base RAM should all be allocated before starting
2457	* the VM (default), or if it should be allocated when first written to.
2458	*/
2459	bool fRamPreAlloc;
2460	/** Indicates whether write monitoring is currently in use.
2461	* This is used to prevent conflicts between live saving and page sharing
2462	* detection. */
2463	bool fPhysWriteMonitoringEngaged;
2464	/** Alignment padding. */
2465	bool afAlignment0[2];
2466
2467	/*
2468	* This will be redefined at least two more times before we're done, I'm sure.
2469	* The current code is only to get on with the coding.
2470	* - 2004-06-10: initial version, bird.
2471	* - 2004-07-02: 1st time, bird.
2472	* - 2004-10-18: 2nd time, bird.
2473	* - 2005-07-xx: 3rd time, bird.
2474	*/
2475
2476	/** The host paging mode. (This is what SUPLib reports.) */
2477	SUPPAGINGMODE enmHostMode;
2478
2479	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2480	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2481	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2482	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2483
2484	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2485	RTGCPHYS GCPhys4MBPSEMask;
2486
2487	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2488	* This is sorted by physical address and contains no overlapping ranges. */
2489	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2490	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2491	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2492	/** RC pointer corresponding to PGM::pRamRangesR3. */
2493	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2494	/** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2495	* range is linked or unlinked. */
2496	uint32_t volatile idRamRangesGen;
2497
2498	/** Pointer to the list of ROM ranges - for R3.
2499	* This is sorted by physical address and contains no overlapping ranges. */
2500	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2501	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2502	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2503	/** RC pointer corresponding to PGM::pRomRangesR3. */
2504	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2505	#if HC_ARCH_BITS == 64
2506	/** Alignment padding. */
2507	RTRCPTR GCPtrPadding2;
2508	#endif
2509
2510	/** Pointer to the list of MMIO2 ranges - for R3.
2511	* Registration order. */
2512	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2513
2514	/** PGM offset based trees - R3 Ptr. */
2515	R3PTRTYPE(PPGMTREES) pTreesR3;
2516	/** PGM offset based trees - R0 Ptr. */
2517	R0PTRTYPE(PPGMTREES) pTreesR0;
2518	/** PGM offset based trees - RC Ptr. */
2519	RCPTRTYPE(PPGMTREES) pTreesRC;
2520
2521	/** Linked list of GC mappings - for RC.
2522	* The list is sorted ascending on address.
2523	*/
2524	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2525	/** Linked list of GC mappings - for HC.
2526	* The list is sorted ascending on address.
2527	*/
2528	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2529	/** Linked list of GC mappings - for R0.
2530	* The list is sorted ascending on address.
2531	*/
2532	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2533
2534	/** Pointer to the 5 page CR3 content mapping.
2535	* The first page is always the CR3 (in some form) while the 4 other pages
2536	* are used of the PDs in PAE mode. */
2537	RTGCPTR GCPtrCR3Mapping;
2538	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2539	uint32_t u32Alignment1;
2540	#endif
2541
2542	/** Indicates that PGMR3FinalizeMappings has been called and that further
2543	* PGMR3MapIntermediate calls will be rejected. */
2544	bool fFinalizedMappings;
2545	/** If set no conflict checks are required. */
2546	bool fMappingsFixed;
2547	/** If set if restored as fixed but we were unable to re-fixate at the old
2548	* location because of room or address incompatibilities. */
2549	bool fMappingsFixedRestored;
2550	/** If set, then no mappings are put into the shadow page table.
2551	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2552	bool fMappingsDisabled;
2553	/** Size of fixed mapping.
2554	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2555	uint32_t cbMappingFixed;
2556	/** Base address (GC) of fixed mapping.
2557	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2558	RTGCPTR GCPtrMappingFixed;
2559	/** The address of the previous RAM range mapping. */
2560	RTGCPTR GCPtrPrevRamRangeMapping;
2561
2562	/** @name Intermediate Context
2563	* @{ */
2564	/** Pointer to the intermediate page directory - Normal. */
2565	R3PTRTYPE(PX86PD) pInterPD;
2566	/** Pointer to the intermedate page tables - Normal.
2567	* There are two page tables, one for the identity mapping and one for
2568	* the host context mapping (of the core code). */
2569	R3PTRTYPE(PX86PT) apInterPTs[2];
2570	/** Pointer to the intermedate page tables - PAE. */
2571	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2572	/** Pointer to the intermedate page directory - PAE. */
2573	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2574	/** Pointer to the intermedate page directory - PAE. */
2575	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2576	/** Pointer to the intermedate page-map level 4 - AMD64. */
2577	R3PTRTYPE(PX86PML4) pInterPaePML4;
2578	/** Pointer to the intermedate page directory - AMD64. */
2579	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2580	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2581	RTHCPHYS HCPhysInterPD;
2582	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2583	RTHCPHYS HCPhysInterPaePDPT;
2584	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2585	RTHCPHYS HCPhysInterPaePML4;
2586	/** @} */
2587
2588	/** Base address of the dynamic page mapping area.
2589	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2590	*/
2591	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2592	/** The index of the last entry used in the dynamic page mapping area. */
2593	RTUINT iDynPageMapLast;
2594	/** Cache containing the last entries in the dynamic page mapping area.
2595	* The cache size is covering half of the mapping area. */
2596	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2597	/** Keep a lock counter for the full (!) mapping area. */
2598	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2599
2600	/** The address of the ring-0 mapping cache if we're making use of it. */
2601	RTR0PTR pvR0DynMapUsed;
2602	#if HC_ARCH_BITS == 32
2603	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2604	uint32_t u32Alignment2;
2605	#endif
2606
2607	/** PGM critical section.
2608	* This protects the physical & virtual access handlers, ram ranges,
2609	* and the page flag updating (some of it anyway).
2610	*/
2611	PDMCRITSECT CritSect;
2612
2613	/** Pointer to SHW+GST mode data (function pointers).
2614	* The index into this table is made up from */
2615	R3PTRTYPE(PPGMMODEDATA) paModeData;
2616
2617	/** Shadow Page Pool - R3 Ptr. */
2618	R3PTRTYPE(PPGMPOOL) pPoolR3;
2619	/** Shadow Page Pool - R0 Ptr. */
2620	R0PTRTYPE(PPGMPOOL) pPoolR0;
2621	/** Shadow Page Pool - RC Ptr. */
2622	RCPTRTYPE(PPGMPOOL) pPoolRC;
2623
2624	/** We're not in a state which permits writes to guest memory.
2625	* (Only used in strict builds.) */
2626	bool fNoMorePhysWrites;
2627	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2628	bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2629
2630	/**
2631	* Data associated with managing the ring-3 mappings of the allocation chunks.
2632	*/
2633	struct
2634	{
2635	/** The chunk tree, ordered by chunk id. */
2636	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2637	R3PTRTYPE(PAVLU32NODECORE) pTree;
2638	#else
2639	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2640	#endif
2641	/** The chunk age tree, ordered by ageing sequence number. */
2642	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2643	/** The chunk mapping TLB. */
2644	PGMCHUNKR3MAPTLB Tlb;
2645	/** The number of mapped chunks. */
2646	uint32_t c;
2647	/** The maximum number of mapped chunks.
2648	* @cfgm PGM/MaxRing3Chunks */
2649	uint32_t cMax;
2650	/** The current time. */
2651	uint32_t iNow;
2652	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2653	uint32_t AgeingCountdown;
2654	} ChunkR3Map;
2655
2656	/**
2657	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2658	*/
2659	PGMPAGER3MAPTLB PhysTlbHC;
2660
2661	/** @name The zero page.
2662	* @{ */
2663	/** The host physical address of the zero page. */
2664	RTHCPHYS HCPhysZeroPg;
2665	/** The ring-3 mapping of the zero page. */
2666	RTR3PTR pvZeroPgR3;
2667	/** The ring-0 mapping of the zero page. */
2668	RTR0PTR pvZeroPgR0;
2669	/** The GC mapping of the zero page. */
2670	RTGCPTR pvZeroPgRC;
2671	/** @}*/
2672
2673	/** The number of handy pages. */
2674	uint32_t cHandyPages;
2675
2676	/** The number of large handy pages. */
2677	uint32_t cLargeHandyPages;
2678
2679	/**
2680	* Array of handy pages.
2681	*
2682	* This array is used in a two way communication between pgmPhysAllocPage
2683	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2684	* an intermediary.
2685	*
2686	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2687	* (The current size of 32 pages, means 128 KB of handy memory.)
2688	*/
2689	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2690
2691	/**
2692	* Array of large handy pages. (currently size 1)
2693	*
2694	* This array is used in a two way communication between pgmPhysAllocLargePage
2695	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2696	* an intermediary.
2697	*/
2698	GMMPAGEDESC aLargeHandyPage[1];
2699
2700	/**
2701	* Live save data.
2702	*/
2703	struct
2704	{
2705	/** Per type statistics. */
2706	struct
2707	{
2708	/** The number of ready pages. */
2709	uint32_t cReadyPages;
2710	/** The number of dirty pages. */
2711	uint32_t cDirtyPages;
2712	/** The number of ready zero pages. */
2713	uint32_t cZeroPages;
2714	/** The number of write monitored pages. */
2715	uint32_t cMonitoredPages;
2716	} Rom,
2717	Mmio2,
2718	Ram;
2719	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2720	uint32_t cIgnoredPages;
2721	/** Indicates that a live save operation is active. */
2722	bool fActive;
2723	/** Padding. */
2724	bool afReserved[2];
2725	/** The next history index. */
2726	uint8_t iDirtyPagesHistory;
2727	/** History of the total amount of dirty pages. */
2728	uint32_t acDirtyPagesHistory[64];
2729	/** Short term dirty page average. */
2730	uint32_t cDirtyPagesShort;
2731	/** Long term dirty page average. */
2732	uint32_t cDirtyPagesLong;
2733	/** The number of saved pages. This is used to get some kind of estimate of the
2734	* link speed so we can decide when we're done. It is reset after the first
2735	* 7 passes so the speed estimate doesn't get inflated by the initial set of
2736	* zero pages. */
2737	uint64_t cSavedPages;
2738	/** The nanosecond timestamp when cSavedPages was 0. */
2739	uint64_t uSaveStartNS;
2740	/** Pages per second (for statistics). */
2741	uint32_t cPagesPerSecond;
2742	uint32_t cAlignment;
2743	} LiveSave;
2744
2745	/** @name Error injection.
2746	* @{ */
2747	/** Inject handy page allocation errors pretending we're completely out of
2748	* memory. */
2749	bool volatile fErrInjHandyPages;
2750	/** Padding. */
2751	bool afReserved[3];
2752	/** @} */
2753
2754	/** @name Release Statistics
2755	* @{ */
2756	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
2757	uint32_t cPrivatePages; /*< The number of private pages. /
2758	uint32_t cSharedPages; /*< The number of shared pages. /
2759	uint32_t cZeroPages; /*< The number of zero backed pages. /
2760	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
2761	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
2762	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
2763	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
2764	uint32_t cReadLockedPages; /*< The number of read locked pages. /
2765
2766	/** The number of times we were forced to change the hypervisor region location. */
2767	STAMCOUNTER cRelocations;
2768	/** @} */
2769
2770	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2771	/* R3 only: */
2772	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2773	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2774
2775	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2776	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2777	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2778	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2779	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2780	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2781	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2782	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2783	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2784	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2785	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2786	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2787	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2788	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2789	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2790	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2791	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2792	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2793	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2794	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2795	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2796	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2797	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2798	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2799
2800	/* RC only: */
2801	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache misses /
2802	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache hits /
2803	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2804	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2805
2806	STAMCOUNTER StatRZPhysRead;
2807	STAMCOUNTER StatRZPhysReadBytes;
2808	STAMCOUNTER StatRZPhysWrite;
2809	STAMCOUNTER StatRZPhysWriteBytes;
2810	STAMCOUNTER StatR3PhysRead;
2811	STAMCOUNTER StatR3PhysReadBytes;
2812	STAMCOUNTER StatR3PhysWrite;
2813	STAMCOUNTER StatR3PhysWriteBytes;
2814	STAMCOUNTER StatRCPhysRead;
2815	STAMCOUNTER StatRCPhysReadBytes;
2816	STAMCOUNTER StatRCPhysWrite;
2817	STAMCOUNTER StatRCPhysWriteBytes;
2818
2819	STAMCOUNTER StatRZPhysSimpleRead;
2820	STAMCOUNTER StatRZPhysSimpleReadBytes;
2821	STAMCOUNTER StatRZPhysSimpleWrite;
2822	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2823	STAMCOUNTER StatR3PhysSimpleRead;
2824	STAMCOUNTER StatR3PhysSimpleReadBytes;
2825	STAMCOUNTER StatR3PhysSimpleWrite;
2826	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2827	STAMCOUNTER StatRCPhysSimpleRead;
2828	STAMCOUNTER StatRCPhysSimpleReadBytes;
2829	STAMCOUNTER StatRCPhysSimpleWrite;
2830	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2831
2832	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2833	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2834	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2835	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2836	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2837	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2838	#endif
2839	} PGM;
2840	#ifndef IN_TSTVMSTRUCTGC /* HACK */
2841	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2842	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2843	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2844	AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2845	AssertCompileMemberAlignment(PGM, CritSect, 8);
2846	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2847	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2848	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2849	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2850	AssertCompileMemberAlignment(PGM, cRelocations, 8);
2851	#endif /* !IN_TSTVMSTRUCTGC */
2852	/** Pointer to the PGM instance data. */
2853	typedef PGM *PPGM;
2854
2855
2856	/**
2857	* Converts a PGMCPU pointer into a VM pointer.
2858	* @returns Pointer to the VM structure the PGM is part of.
2859	* @param pPGM Pointer to PGMCPU instance data.
2860	*/
2861	#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2862
2863	/**
2864	* Converts a PGMCPU pointer into a PGM pointer.
2865	* @returns Pointer to the VM structure the PGM is part of.
2866	* @param pPGM Pointer to PGMCPU instance data.
2867	*/
2868	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2869
2870	/**
2871	* PGMCPU Data (part of VMCPU).
2872	*/
2873	typedef struct PGMCPU
2874	{
2875	/** Offset to the VM structure. */
2876	RTINT offVM;
2877	/** Offset to the VMCPU structure. */
2878	RTINT offVCpu;
2879	/** Offset of the PGM structure relative to VMCPU. */
2880	RTINT offPGM;
2881	RTINT uPadding0; /*< structure size alignment. /
2882
2883	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2884	/** Automatically tracked physical memory mapping set.
2885	* Ring-0 and strict raw-mode builds. */
2886	PGMMAPSET AutoSet;
2887	#endif
2888
2889	/** A20 gate mask.
2890	* Our current approach to A20 emulation is to let REM do it and don't bother
2891	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2892	* But whould need arrise, we'll subject physical addresses to this mask. */
2893	RTGCPHYS GCPhysA20Mask;
2894	/** A20 gate state - boolean! */
2895	bool fA20Enabled;
2896
2897	/** What needs syncing (PGM_SYNC_*).
2898	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2899	* PGMFlushTLB, and PGMR3Load. */
2900	RTUINT fSyncFlags;
2901
2902	/** The shadow paging mode. */
2903	PGMMODE enmShadowMode;
2904	/** The guest paging mode. */
2905	PGMMODE enmGuestMode;
2906
2907	/** The current physical address representing in the guest CR3 register. */
2908	RTGCPHYS GCPhysCR3;
2909
2910	/** @name 32-bit Guest Paging.
2911	* @{ */
2912	/** The guest's page directory, R3 pointer. */
2913	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2914	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2915	/** The guest's page directory, R0 pointer. */
2916	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2917	#endif
2918	/** The guest's page directory, static RC mapping. */
2919	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2920	/** @} */
2921
2922	/** @name PAE Guest Paging.
2923	* @{ */
2924	/** The guest's page directory pointer table, static RC mapping. */
2925	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2926	/** The guest's page directory pointer table, R3 pointer. */
2927	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2928	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2929	/** The guest's page directory pointer table, R0 pointer. */
2930	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2931	#endif
2932
2933	/** The guest's page directories, R3 pointers.
2934	* These are individual pointers and don't have to be adjecent.
2935	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2936	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2937	/** The guest's page directories, R0 pointers.
2938	* Same restrictions as apGstPaePDsR3. */
2939	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2940	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2941	#endif
2942	/** The guest's page directories, static GC mapping.
2943	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2944	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2945	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2946	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2947	RTGCPHYS aGCPhysGstPaePDs[4];
2948	/** The physical addresses of the monitored guest page directories (PAE). */
2949	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2950	/** @} */
2951
2952	/** @name AMD64 Guest Paging.
2953	* @{ */
2954	/** The guest's page directory pointer table, R3 pointer. */
2955	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2956	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2957	/** The guest's page directory pointer table, R0 pointer. */
2958	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2959	#else
2960	RTR0PTR alignment6b; /*< alignment equalizer. /
2961	#endif
2962	/** @} */
2963
2964	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2965	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2966	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2967	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2968	/** Pointer to the page of the current active CR3 - RC Ptr. */
2969	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2970	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2971	uint32_t iShwUser;
2972	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2973	uint32_t iShwUserTable;
2974	# if HC_ARCH_BITS == 64
2975	RTRCPTR alignment6; /*< structure size alignment. /
2976	# endif
2977	/** @} */
2978
2979	/** @name Function pointers for Shadow paging.
2980	* @{
2981	*/
2982	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2983	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2984	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2985	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2986
2987	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2988	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2989
2990	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2991	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2992
2993	/** @} */
2994
2995	/** @name Function pointers for Guest paging.
2996	* @{
2997	*/
2998	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2999	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3000	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3001	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3002	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3003	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3004	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3005	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3006	#if HC_ARCH_BITS == 64
3007	RTRCPTR alignment3; /*< structure size alignment. /
3008	#endif
3009
3010	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3011	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3012	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3013	/** @} */
3014
3015	/** @name Function pointers for Both Shadow and Guest paging.
3016	* @{
3017	*/
3018	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3019	/* no pfnR3BthTrap0eHandler */
3020	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3021	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3022	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3023	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3024	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3025	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3026	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3027	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3028
3029	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3030	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3031	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3032	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3033	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3034	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3035	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3036	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3037	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3038
3039	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3040	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3041	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3042	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3043	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3044	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3045	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3046	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3047	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3048	RTRCPTR alignment2; /*< structure size alignment. /
3049	/** @} */
3050
3051	/** For saving stack space, the disassembler state is allocated here instead of
3052	* on the stack.
3053	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3054	union
3055	{
3056	/** The disassembler scratch space. */
3057	DISCPUSTATE DisState;
3058	/** Padding. */
3059	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3060	};
3061
3062	/* Count the number of pgm pool access handler calls. */
3063	uint64_t cPoolAccessHandler;
3064
3065	/** @name Release Statistics
3066	* @{ */
3067	/** The number of times the guest has switched mode since last reset or statistics reset. */
3068	STAMCOUNTER cGuestModeChanges;
3069	/** @} */
3070
3071	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3072	/** @name Statistics
3073	* @{ */
3074	/** RC: Which statistic this \#PF should be attributed to. */
3075	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3076	RTRCPTR padding0;
3077	/** R0: Which statistic this \#PF should be attributed to. */
3078	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3079	RTR0PTR padding1;
3080
3081	/* Common */
3082	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3083	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3084
3085	/* R0 only: */
3086	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
3087	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
3088	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
3089	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3090	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
3091	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
3092	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
3093	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
3094	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3095	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
3096	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
3097	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
3098	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
3099	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
3100	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
3101	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
3102	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
3103	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
3104	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
3105	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
3106	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
3107	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
3108	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
3109	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
3110	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
3111	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
3112
3113	/* RZ only: */
3114	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3115	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3116	STAMPROFILE StatRZTrap0eTimeSyncPT;
3117	STAMPROFILE StatRZTrap0eTimeMapping;
3118	STAMPROFILE StatRZTrap0eTimeOutOfSync;
3119	STAMPROFILE StatRZTrap0eTimeHandlers;
3120	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3121	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3122	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3123	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3124	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3125	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3126	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3127	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3128	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3129	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3130	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3131	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3132	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3133	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3134	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3135	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
3136	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3137	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3138	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3139	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3140	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3141	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3142	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3143	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3144	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3145	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3146	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3147	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3148	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3149	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3150	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3151	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3152	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3153	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest \#PF ending up at the end of the \#PF code. /
3154	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3155	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3156	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3157	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3158	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3159	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3160	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3161	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3162	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3163
3164	/* HC - R3 and (maybe) R0: */
3165
3166	/* RZ & R3: */
3167	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3168	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3169	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3170	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3171	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3172	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3173	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3174	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3175	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3176	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3177	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3178	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3179	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3180	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3181	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3182	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3183	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3184	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3185	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3186	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3187	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3188	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3189	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3190	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3191	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3192	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3193	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3194	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3195	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3196	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3197	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3198	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3199	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3200	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3201	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3202	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3203	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3204	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3205	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3206	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3207	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3208	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3209	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3210	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3211	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3212	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3213
3214	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3215	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3216	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3217	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3218	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3219	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3220	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3221	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3222	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3223	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3224	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3225	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3226	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3227	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3228	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3229	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3230	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3231	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3232	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3233	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3234	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3235	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3236	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3237	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3238	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3239	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3240	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3241	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3242	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3243	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3244	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3245	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3246	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3247	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3248	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3249	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3250	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3251	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3252	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3253	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3254	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3255	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3256	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3257	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3258	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3259	/** @} */
3260	#endif /* VBOX_WITH_STATISTICS */
3261	} PGMCPU;
3262	/** Pointer to the per-cpu PGM data. */
3263	typedef PGMCPU *PPGMCPU;
3264
3265
3266	/** @name PGM::fSyncFlags Flags
3267	* @{
3268	*/
3269	/** Updates the virtual access handler state bit in PGMPAGE. */
3270	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3271	/** Always sync CR3. */
3272	#define PGM_SYNC_ALWAYS RT_BIT(1)
3273	/** Check monitoring on next CR3 (re)load and invalidate page.
3274	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3275	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3276	/** Check guest mapping in SyncCR3. */
3277	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3278	/** Clear the page pool (a light weight flush). */
3279	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3280	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3281	/** @} */
3282
3283
3284	RT_C_DECLS_BEGIN
3285
3286	int pgmLock(PVM pVM);
3287	void pgmUnlock(PVM pVM);
3288
3289	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3290	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3291	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3292	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3293	int pgmMapResolveConflicts(PVM pVM);
3294	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3295
3296	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3297	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3298	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3299	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3300	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3301	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3302	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3303	#else
3304	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3305	#endif
3306	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3307	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3308
3309	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3310	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3311	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3312	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3313	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3314	int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3315	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3316	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3317	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3318	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3319	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3320	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3321	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3322	#ifdef IN_RING3
3323	void pgmR3PhysRelinkRamRanges(PVM pVM);
3324	int pgmR3PhysRamPreAllocate(PVM pVM);
3325	int pgmR3PhysRamReset(PVM pVM);
3326	int pgmR3PhysRomReset(PVM pVM);
3327	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3328
3329	int pgmR3PoolInit(PVM pVM);
3330	void pgmR3PoolRelocate(PVM pVM);
3331	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3332	void pgmR3PoolReset(PVM pVM);
3333	void pgmR3PoolClearAll(PVM pVM);
3334	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser);
3335
3336	#endif /* IN_RING3 */
3337	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3338	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3339	#endif
3340	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3341
3342	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3343	{
3344	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3345	}
3346
3347	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3348	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3349	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3350	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3351	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3352	int pgmPoolSyncCR3(PVMCPU pVCpu);
3353	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3354	int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3355	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3356	DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3357	{
3358	return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3359	}
3360
3361	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3362	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3363	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3364	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3365	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3366	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3367
3368	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3369	void pgmPoolResetDirtyPages(PVM pVM);
3370
3371	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3372	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3373
3374	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3375	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3376	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3377	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3378
3379	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3380	#ifndef IN_RC
3381	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3382	#endif
3383	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3384
3385	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3386	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3387	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3388	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3389
3390	RT_C_DECLS_END
3391
3392	/** @} */
3393
3394	#endif
3395

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 26606

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