VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 26994

Last change on this file since 26994 was 26947, checked in by vboxsync, 15 years ago

Avoid deadlocks in PGMR3PhysFreeRamPages
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1/* $Id: PGMInternal.h 26947 2010-03-02 14:11:43Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43#include <iprt/sha.h>
44
45
46
47/** @defgroup grp_pgm_int Internals
48 * @ingroup grp_pgm
49 * @internal
50 * @{
51 */
52
53
54/** @name PGM Compile Time Config
55 * @{
56 */
57
58/**
59 * Indicates that there are no guest mappings to care about.
60 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
61 */
62#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
63# define PGM_WITHOUT_MAPPINGS
64#endif
65
66/**
67 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
68 * Comment it if it will break something.
69 */
70#define PGM_OUT_OF_SYNC_IN_GC
71
72/**
73 * Check and skip global PDEs for non-global flushes
74 */
75#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
76
77/**
78 * Optimization for PAE page tables that are modified often
79 */
80//#if 0 /* disabled again while debugging */
81#ifndef IN_RC
82# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
83#endif
84//#endif
85
86/**
87 * Sync N pages instead of a whole page table
88 */
89#define PGM_SYNC_N_PAGES
90
91/**
92 * Number of pages to sync during a page fault
93 *
94 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
95 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
96 *
97 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
98 * world switch overhead, so let's sync more.
99 */
100# ifdef IN_RING0
101/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
102 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
103 * but ~5% fewer faults.
104 */
105# define PGM_SYNC_NR_PAGES 32
106#else
107# define PGM_SYNC_NR_PAGES 8
108#endif
109
110/**
111 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
112 */
113#define PGM_MAX_PHYSCACHE_ENTRIES 64
114#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
115
116
117/** @def PGMPOOL_CFG_MAX_GROW
118 * The maximum number of pages to add to the pool in one go.
119 */
120#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
121
122/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
123 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
124 */
125#ifdef VBOX_STRICT
126# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
127#endif
128
129/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130 * Enables the experimental lazy page allocation code. */
131/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
132
133/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
134 * Enables real write monitoring of pages, i.e. mapping them read-only and
135 * only making them writable when getting a write access #PF. */
136#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
137
138/** @} */
139
140
141/** @name PDPT and PML4 flags.
142 * These are placed in the three bits available for system programs in
143 * the PDPT and PML4 entries.
144 * @{ */
145/** The entry is a permanent one and it's must always be present.
146 * Never free such an entry. */
147#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
148/** Mapping (hypervisor allocated pagetable). */
149#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
150/** @} */
151
152/** @name Page directory flags.
153 * These are placed in the three bits available for system programs in
154 * the page directory entries.
155 * @{ */
156/** Mapping (hypervisor allocated pagetable). */
157#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
158/** Made read-only to facilitate dirty bit tracking. */
159#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
160/** @} */
161
162/** @name Page flags.
163 * These are placed in the three bits available for system programs in
164 * the page entries.
165 * @{ */
166/** Made read-only to facilitate dirty bit tracking. */
167#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
168
169#ifndef PGM_PTFLAGS_CSAM_VALIDATED
170/** Scanned and approved by CSAM (tm).
171 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
172 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
173#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
174#endif
175
176/** @} */
177
178/** @name Defines used to indicate the shadow and guest paging in the templates.
179 * @{ */
180#define PGM_TYPE_REAL 1
181#define PGM_TYPE_PROT 2
182#define PGM_TYPE_32BIT 3
183#define PGM_TYPE_PAE 4
184#define PGM_TYPE_AMD64 5
185#define PGM_TYPE_NESTED 6
186#define PGM_TYPE_EPT 7
187#define PGM_TYPE_MAX PGM_TYPE_EPT
188/** @} */
189
190/** Macro for checking if the guest is using paging.
191 * @param uGstType PGM_TYPE_*
192 * @param uShwType PGM_TYPE_*
193 * @remark ASSUMES certain order of the PGM_TYPE_* values.
194 */
195#define PGM_WITH_PAGING(uGstType, uShwType) \
196 ( (uGstType) >= PGM_TYPE_32BIT \
197 && (uShwType) != PGM_TYPE_NESTED \
198 && (uShwType) != PGM_TYPE_EPT)
199
200/** Macro for checking if the guest supports the NX bit.
201 * @param uGstType PGM_TYPE_*
202 * @param uShwType PGM_TYPE_*
203 * @remark ASSUMES certain order of the PGM_TYPE_* values.
204 */
205#define PGM_WITH_NX(uGstType, uShwType) \
206 ( (uGstType) >= PGM_TYPE_PAE \
207 && (uShwType) != PGM_TYPE_NESTED \
208 && (uShwType) != PGM_TYPE_EPT)
209
210
211/** @def PGM_HCPHYS_2_PTR
212 * Maps a HC physical page pool address to a virtual address.
213 *
214 * @returns VBox status code.
215 * @param pVM The VM handle.
216 * @param HCPhys The HC physical address to map to a virtual one.
217 * @param ppv Where to store the virtual address. No need to cast this.
218 *
219 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
220 * small page window employeed by that function. Be careful.
221 * @remark There is no need to assert on the result.
222 */
223#ifdef IN_RC
224# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
225 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
226#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
227# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
228 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
229#else
230# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
231 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
232#endif
233
234/** @def PGM_HCPHYS_2_PTR_BY_PGM
235 * Maps a HC physical page pool address to a virtual address.
236 *
237 * @returns VBox status code.
238 * @param pPGM The PGM instance data.
239 * @param HCPhys The HC physical address to map to a virtual one.
240 * @param ppv Where to store the virtual address. No need to cast this.
241 *
242 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
243 * small page window employeed by that function. Be careful.
244 * @remark There is no need to assert on the result.
245 */
246#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
247# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
248 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
249#else
250# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
251 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
252#endif
253
254/** @def PGM_GCPHYS_2_PTR
255 * Maps a GC physical page address to a virtual address.
256 *
257 * @returns VBox status code.
258 * @param pVM The VM handle.
259 * @param GCPhys The GC physical address to map to a virtual one.
260 * @param ppv Where to store the virtual address. No need to cast this.
261 *
262 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
263 * small page window employeed by that function. Be careful.
264 * @remark There is no need to assert on the result.
265 */
266#ifdef IN_RC
267# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
268 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
269#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
270# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
271 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
272#else
273# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
274 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
275#endif
276
277/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
278 * Maps a GC physical page address to a virtual address.
279 *
280 * @returns VBox status code.
281 * @param pPGM Pointer to the PGM instance data.
282 * @param GCPhys The GC physical address to map to a virtual one.
283 * @param ppv Where to store the virtual address. No need to cast this.
284 *
285 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
286 * small page window employeed by that function. Be careful.
287 * @remark There is no need to assert on the result.
288 */
289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
290# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
291 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
292#else
293# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
294 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
295#endif
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
306 * small page window employeed by that function. Be careful.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_INVL_PG
318 * Invalidates a page.
319 *
320 * @param pVCpu The VMCPU handle.
321 * @param GCVirt The virtual address of the page to invalidate.
322 */
323#ifdef IN_RC
324# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
325#elif defined(IN_RING0)
326# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
327#else
328# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
329#endif
330
331/** @def PGM_INVL_PG_ALL_VCPU
332 * Invalidates a page on all VCPUs
333 *
334 * @param pVM The VM handle.
335 * @param GCVirt The virtual address of the page to invalidate.
336 */
337#ifdef IN_RC
338# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
339#elif defined(IN_RING0)
340# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
341#else
342# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
343#endif
344
345/** @def PGM_INVL_BIG_PG
346 * Invalidates a 4MB page directory entry.
347 *
348 * @param pVCpu The VMCPU handle.
349 * @param GCVirt The virtual address within the page directory to invalidate.
350 */
351#ifdef IN_RC
352# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
353#elif defined(IN_RING0)
354# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
355#else
356# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
357#endif
358
359/** @def PGM_INVL_VCPU_TLBS()
360 * Invalidates the TLBs of the specified VCPU
361 *
362 * @param pVCpu The VMCPU handle.
363 */
364#ifdef IN_RC
365# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
366#elif defined(IN_RING0)
367# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
368#else
369# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
370#endif
371
372/** @def PGM_INVL_ALL_VCPU_TLBS()
373 * Invalidates the TLBs of all VCPUs
374 *
375 * @param pVM The VM handle.
376 */
377#ifdef IN_RC
378# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
379#elif defined(IN_RING0)
380# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
381#else
382# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
383#endif
384
385/** Size of the GCPtrConflict array in PGMMAPPING.
386 * @remarks Must be a power of two. */
387#define PGMMAPPING_CONFLICT_MAX 8
388
389/**
390 * Structure for tracking GC Mappings.
391 *
392 * This structure is used by linked list in both GC and HC.
393 */
394typedef struct PGMMAPPING
395{
396 /** Pointer to next entry. */
397 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
398 /** Pointer to next entry. */
399 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
400 /** Pointer to next entry. */
401 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
402 /** Indicate whether this entry is finalized. */
403 bool fFinalized;
404 /** Start Virtual address. */
405 RTGCPTR GCPtr;
406 /** Last Virtual address (inclusive). */
407 RTGCPTR GCPtrLast;
408 /** Range size (bytes). */
409 RTGCPTR cb;
410 /** Pointer to relocation callback function. */
411 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
412 /** User argument to the callback. */
413 R3PTRTYPE(void *) pvUser;
414 /** Mapping description / name. For easing debugging. */
415 R3PTRTYPE(const char *) pszDesc;
416 /** Last 8 addresses that caused conflicts. */
417 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
418 /** Number of conflicts for this hypervisor mapping. */
419 uint32_t cConflicts;
420 /** Number of page tables. */
421 uint32_t cPTs;
422
423 /** Array of page table mapping data. Each entry
424 * describes one page table. The array can be longer
425 * than the declared length.
426 */
427 struct
428 {
429 /** The HC physical address of the page table. */
430 RTHCPHYS HCPhysPT;
431 /** The HC physical address of the first PAE page table. */
432 RTHCPHYS HCPhysPaePT0;
433 /** The HC physical address of the second PAE page table. */
434 RTHCPHYS HCPhysPaePT1;
435 /** The HC virtual address of the 32-bit page table. */
436 R3PTRTYPE(PX86PT) pPTR3;
437 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
438 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
439 /** The RC virtual address of the 32-bit page table. */
440 RCPTRTYPE(PX86PT) pPTRC;
441 /** The RC virtual address of the two PAE page table. */
442 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
443 /** The R0 virtual address of the 32-bit page table. */
444 R0PTRTYPE(PX86PT) pPTR0;
445 /** The R0 virtual address of the two PAE page table. */
446 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
447 } aPTs[1];
448} PGMMAPPING;
449/** Pointer to structure for tracking GC Mappings. */
450typedef struct PGMMAPPING *PPGMMAPPING;
451
452
453/**
454 * Physical page access handler structure.
455 *
456 * This is used to keep track of physical address ranges
457 * which are being monitored in some kind of way.
458 */
459typedef struct PGMPHYSHANDLER
460{
461 AVLROGCPHYSNODECORE Core;
462 /** Access type. */
463 PGMPHYSHANDLERTYPE enmType;
464 /** Number of pages to update. */
465 uint32_t cPages;
466 /** Pointer to R3 callback function. */
467 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
468 /** User argument for R3 handlers. */
469 R3PTRTYPE(void *) pvUserR3;
470 /** Pointer to R0 callback function. */
471 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
472 /** User argument for R0 handlers. */
473 R0PTRTYPE(void *) pvUserR0;
474 /** Pointer to RC callback function. */
475 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
476 /** User argument for RC handlers. */
477 RCPTRTYPE(void *) pvUserRC;
478 /** Description / Name. For easing debugging. */
479 R3PTRTYPE(const char *) pszDesc;
480#ifdef VBOX_WITH_STATISTICS
481 /** Profiling of this handler. */
482 STAMPROFILE Stat;
483#endif
484} PGMPHYSHANDLER;
485/** Pointer to a physical page access handler structure. */
486typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
487
488
489/**
490 * Cache node for the physical addresses covered by a virtual handler.
491 */
492typedef struct PGMPHYS2VIRTHANDLER
493{
494 /** Core node for the tree based on physical ranges. */
495 AVLROGCPHYSNODECORE Core;
496 /** Offset from this struct to the PGMVIRTHANDLER structure. */
497 int32_t offVirtHandler;
498 /** Offset of the next alias relative to this one.
499 * Bit 0 is used for indicating whether we're in the tree.
500 * Bit 1 is used for indicating that we're the head node.
501 */
502 int32_t offNextAlias;
503} PGMPHYS2VIRTHANDLER;
504/** Pointer to a phys to virtual handler structure. */
505typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
506
507/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
508 * node is in the tree. */
509#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
510/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
511 * node is in the head of an alias chain.
512 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
513#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
514/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
515#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
516
517
518/**
519 * Virtual page access handler structure.
520 *
521 * This is used to keep track of virtual address ranges
522 * which are being monitored in some kind of way.
523 */
524typedef struct PGMVIRTHANDLER
525{
526 /** Core node for the tree based on virtual ranges. */
527 AVLROGCPTRNODECORE Core;
528 /** Size of the range (in bytes). */
529 RTGCPTR cb;
530 /** Number of cache pages. */
531 uint32_t cPages;
532 /** Access type. */
533 PGMVIRTHANDLERTYPE enmType;
534 /** Pointer to the RC callback function. */
535 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
536#if HC_ARCH_BITS == 64
537 RTRCPTR padding;
538#endif
539 /** Pointer to the R3 callback function for invalidation. */
540 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
541 /** Pointer to the R3 callback function. */
542 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
543 /** Description / Name. For easing debugging. */
544 R3PTRTYPE(const char *) pszDesc;
545#ifdef VBOX_WITH_STATISTICS
546 /** Profiling of this handler. */
547 STAMPROFILE Stat;
548#endif
549 /** Array of cached physical addresses for the monitored ranged. */
550 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
551} PGMVIRTHANDLER;
552/** Pointer to a virtual page access handler structure. */
553typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
554
555
556/**
557 * Page type.
558 *
559 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
560 * @remarks This is used in the saved state, so changes to it requires bumping
561 * the saved state version.
562 * @todo So, convert to \#defines!
563 */
564typedef enum PGMPAGETYPE
565{
566 /** The usual invalid zero entry. */
567 PGMPAGETYPE_INVALID = 0,
568 /** RAM page. (RWX) */
569 PGMPAGETYPE_RAM,
570 /** MMIO2 page. (RWX) */
571 PGMPAGETYPE_MMIO2,
572 /** MMIO2 page aliased over an MMIO page. (RWX)
573 * See PGMHandlerPhysicalPageAlias(). */
574 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
575 /** Shadowed ROM. (RWX) */
576 PGMPAGETYPE_ROM_SHADOW,
577 /** ROM page. (R-X) */
578 PGMPAGETYPE_ROM,
579 /** MMIO page. (---) */
580 PGMPAGETYPE_MMIO,
581 /** End of valid entries. */
582 PGMPAGETYPE_END
583} PGMPAGETYPE;
584AssertCompile(PGMPAGETYPE_END <= 7);
585
586/** @name Page type predicates.
587 * @{ */
588#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
589#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
590#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
591#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
592#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
593/** @} */
594
595
596/**
597 * A Physical Guest Page tracking structure.
598 *
599 * The format of this structure is complicated because we have to fit a lot
600 * of information into as few bits as possible. The format is also subject
601 * to change (there is one comming up soon). Which means that for we'll be
602 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
603 * accesses to the structure.
604 */
605typedef struct PGMPAGE
606{
607 /** The physical address and the Page ID. */
608 RTHCPHYS HCPhysAndPageID;
609 /** Combination of:
610 * - [0-7]: u2HandlerPhysStateY - the physical handler state
611 * (PGM_PAGE_HNDL_PHYS_STATE_*).
612 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
613 * (PGM_PAGE_HNDL_VIRT_STATE_*).
614 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
615 * - [15]: fWrittenToY - flag indicating that a write monitored page was
616 * written to when set.
617 * - [10-13]: 4 unused bits.
618 * @remarks Warning! All accesses to the bits are hardcoded.
619 *
620 * @todo Change this to a union with both bitfields, u8 and u accessors.
621 * That'll help deal with some of the hardcoded accesses.
622 *
623 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
624 * will make it possible to turn some of the 16-bit accesses into
625 * 32-bit ones, which may be efficient (stalls).
626 */
627 RTUINT16U u16MiscY;
628 /** The page state.
629 * Only 2 bits are really needed for this. */
630 uint8_t uStateY;
631 /** The page type (PGMPAGETYPE).
632 * Only 3 bits are really needed for this. */
633 uint8_t uTypeY;
634 /** Usage tracking (page pool). */
635 uint16_t u16TrackingY;
636 /** The number of read locks on this page. */
637 uint8_t cReadLocksY;
638 /** The number of write locks on this page. */
639 uint8_t cWriteLocksY;
640} PGMPAGE;
641AssertCompileSize(PGMPAGE, 16);
642/** Pointer to a physical guest page. */
643typedef PGMPAGE *PPGMPAGE;
644/** Pointer to a const physical guest page. */
645typedef const PGMPAGE *PCPGMPAGE;
646/** Pointer to a physical guest page pointer. */
647typedef PPGMPAGE *PPPGMPAGE;
648
649
650/**
651 * Clears the page structure.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_CLEAR(pPage) \
655 do { \
656 (pPage)->HCPhysAndPageID = 0; \
657 (pPage)->uStateY = 0; \
658 (pPage)->uTypeY = 0; \
659 (pPage)->u16MiscY.u = 0; \
660 (pPage)->u16TrackingY = 0; \
661 (pPage)->cReadLocksY = 0; \
662 (pPage)->cWriteLocksY = 0; \
663 } while (0)
664
665/**
666 * Initializes the page structure.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670 do { \
671 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
672 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
673 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
674 (pPage)->uStateY = (_uState); \
675 (pPage)->uTypeY = (_uType); \
676 (pPage)->u16MiscY.u = 0; \
677 (pPage)->u16TrackingY = 0; \
678 (pPage)->cReadLocksY = 0; \
679 (pPage)->cWriteLocksY = 0; \
680 } while (0)
681
682/**
683 * Initializes the page structure of a ZERO page.
684 * @param pPage Pointer to the physical guest page tracking structure.
685 * @param pVM The VM handle (for getting the zero page address).
686 * @param uType The page type (PGMPAGETYPE).
687 */
688#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
689 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
690
691
692/** @name The Page state, PGMPAGE::uStateY.
693 * @{ */
694/** The zero page.
695 * This is a per-VM page that's never ever mapped writable. */
696#define PGM_PAGE_STATE_ZERO 0
697/** A allocated page.
698 * This is a per-VM page allocated from the page pool (or wherever
699 * we get MMIO2 pages from if the type is MMIO2).
700 */
701#define PGM_PAGE_STATE_ALLOCATED 1
702/** A allocated page that's being monitored for writes.
703 * The shadow page table mappings are read-only. When a write occurs, the
704 * fWrittenTo member is set, the page remapped as read-write and the state
705 * moved back to allocated. */
706#define PGM_PAGE_STATE_WRITE_MONITORED 2
707/** The page is shared, aka. copy-on-write.
708 * This is a page that's shared with other VMs. */
709#define PGM_PAGE_STATE_SHARED 3
710/** @} */
711
712
713/**
714 * Gets the page state.
715 * @returns page state (PGM_PAGE_STATE_*).
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
719
720/**
721 * Sets the page state.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 * @param _uState The new page state.
724 */
725#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
726
727
728/**
729 * Gets the host physical address of the guest page.
730 * @returns host physical address (RTHCPHYS).
731 * @param pPage Pointer to the physical guest page tracking structure.
732 */
733#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
734
735/**
736 * Sets the host physical address of the guest page.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 * @param _HCPhys The new host physical address.
739 */
740#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
741 do { \
742 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
743 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
744 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
745 | (SetHCPhysTmp << (28-12)); \
746 } while (0)
747
748/**
749 * Get the Page ID.
750 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
754
755/**
756 * Sets the Page ID.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
760 do { \
761 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
762 | ((_idPage) & UINT32_C(0x0fffffff)); \
763 } while (0)
764
765/**
766 * Get the Chunk ID.
767 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
768 * @param pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
771
772/**
773 * Get the index of the page within the allocation chunk.
774 * @returns The page index.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 */
777#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
778
779/**
780 * Gets the page type.
781 * @returns The page type.
782 * @param pPage Pointer to the physical guest page tracking structure.
783 */
784#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
785
786/**
787 * Sets the page type.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 * @param _enmType The new page type (PGMPAGETYPE).
790 */
791#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
792
793/**
794 * Checks if the page is marked for MMIO.
795 * @returns true/false.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
799
800/**
801 * Checks if the page is backed by the ZERO page.
802 * @returns true/false.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
806
807/**
808 * Checks if the page is backed by a SHARED page.
809 * @returns true/false.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
813
814
815/**
816 * Marks the page as written to (for GMM change monitoring).
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
820
821/**
822 * Clears the written-to indicator.
823 * @param pPage Pointer to the physical guest page tracking structure.
824 */
825#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
826
827/**
828 * Checks if the page was marked as written-to.
829 * @returns true/false.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 */
832#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
833
834/** @name PT usage values (PGMPAGE::u2PDEType).
835 *
836 * @{ */
837/** Either as a PT or PDE. */
838#define PGM_PAGE_PDE_TYPE_DONTCARE 0
839/** Must use a page table to map the range. */
840#define PGM_PAGE_PDE_TYPE_PT 1
841/** Can use a page directory entry to map the continous range. */
842#define PGM_PAGE_PDE_TYPE_PDE 2
843/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
844#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
845/** @} */
846
847/**
848 * Set the PDE type of the page
849 * @param pPage Pointer to the physical guest page tracking structure.
850 * @param uType PGM_PAGE_PDE_TYPE_*
851 */
852#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
853 do { \
854 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
855 | (((uType) & UINT8_C(0x03)) << 5); \
856 } while (0)
857
858/**
859 * Checks if the page was marked being part of a large page
860 * @returns true/false.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
864
865/** Enabled optimized access handler tests.
866 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
867 * layout. When enabled, the compiler should normally generate more compact
868 * code.
869 */
870#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
871
872/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
873 *
874 * @remarks The values are assigned in order of priority, so we can calculate
875 * the correct state for a page with different handlers installed.
876 * @{ */
877/** No handler installed. */
878#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
879/** Monitoring is temporarily disabled. */
880#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
881/** Write access is monitored. */
882#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
883/** All access is monitored. */
884#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
885/** @} */
886
887/**
888 * Gets the physical access handler state of a page.
889 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
890 * @param pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
893 ( (pPage)->u16MiscY.au8[0] )
894
895/**
896 * Sets the physical access handler state of a page.
897 * @param pPage Pointer to the physical guest page tracking structure.
898 * @param _uState The new state value.
899 */
900#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
901 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
902
903/**
904 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
905 * @returns true/false
906 * @param pPage Pointer to the physical guest page tracking structure.
907 */
908#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
909 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
910
911/**
912 * Checks if the page has any active physical access handlers.
913 * @returns true/false
914 * @param pPage Pointer to the physical guest page tracking structure.
915 */
916#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
917 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
918
919
920/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
921 *
922 * @remarks The values are assigned in order of priority, so we can calculate
923 * the correct state for a page with different handlers installed.
924 * @{ */
925/** No handler installed. */
926#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
927/* 1 is reserved so the lineup is identical with the physical ones. */
928/** Write access is monitored. */
929#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
930/** All access is monitored. */
931#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
932/** @} */
933
934/**
935 * Gets the virtual access handler state of a page.
936 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
940
941/**
942 * Sets the virtual access handler state of a page.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 * @param _uState The new state value.
945 */
946#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
947 do { \
948 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
949 | ((_uState) & UINT8_C(0x03)); \
950 } while (0)
951
952/**
953 * Checks if the page has any virtual access handlers.
954 * @returns true/false
955 * @param pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
958 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
959
960/**
961 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
962 * virtual handlers.
963 * @returns true/false
964 * @param pPage Pointer to the physical guest page tracking structure.
965 */
966#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
967 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
968
969
970/**
971 * Checks if the page has any access handlers, including temporarily disabled ones.
972 * @returns true/false
973 * @param pPage Pointer to the physical guest page tracking structure.
974 */
975#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
976# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
977 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
978#else
979# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
980 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
981 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
982#endif
983
984/**
985 * Checks if the page has any active access handlers.
986 * @returns true/false
987 * @param pPage Pointer to the physical guest page tracking structure.
988 */
989#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
990# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
991 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
992#else
993# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
994 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
995 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
996#endif
997
998/**
999 * Checks if the page has any active access handlers catching all accesses.
1000 * @returns true/false
1001 * @param pPage Pointer to the physical guest page tracking structure.
1002 */
1003#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1004# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1005 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1006 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1007#else
1008# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1009 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1010 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1011#endif
1012
1013
1014/** @def PGM_PAGE_GET_TRACKING
1015 * Gets the packed shadow page pool tracking data associated with a guest page.
1016 * @returns uint16_t containing the data.
1017 * @param pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1020
1021/** @def PGM_PAGE_SET_TRACKING
1022 * Sets the packed shadow page pool tracking data associated with a guest page.
1023 * @param pPage Pointer to the physical guest page tracking structure.
1024 * @param u16TrackingData The tracking data to store.
1025 */
1026#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1027 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1028
1029/** @def PGM_PAGE_GET_TD_CREFS
1030 * Gets the @a cRefs tracking data member.
1031 * @returns cRefs.
1032 * @param pPage Pointer to the physical guest page tracking structure.
1033 */
1034#define PGM_PAGE_GET_TD_CREFS(pPage) \
1035 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1036
1037/** @def PGM_PAGE_GET_TD_IDX
1038 * Gets the @a idx tracking data member.
1039 * @returns idx.
1040 * @param pPage Pointer to the physical guest page tracking structure.
1041 */
1042#define PGM_PAGE_GET_TD_IDX(pPage) \
1043 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1044
1045
1046/** Max number of locks on a page. */
1047#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1048
1049/** Get the read lock count.
1050 * @returns count.
1051 * @param pPage Pointer to the physical guest page tracking structure.
1052 */
1053#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1054
1055/** Get the write lock count.
1056 * @returns count.
1057 * @param pPage Pointer to the physical guest page tracking structure.
1058 */
1059#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1060
1061/** Decrement the read lock counter.
1062 * @param pPage Pointer to the physical guest page tracking structure.
1063 */
1064#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1065
1066/** Decrement the write lock counter.
1067 * @param pPage Pointer to the physical guest page tracking structure.
1068 */
1069#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1070
1071/** Increment the read lock counter.
1072 * @param pPage Pointer to the physical guest page tracking structure.
1073 */
1074#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1075
1076/** Increment the write lock counter.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1080
1081
1082#if 0
1083/** Enables sanity checking of write monitoring using CRC-32. */
1084# define PGMLIVESAVERAMPAGE_WITH_CRC32
1085#endif
1086
1087/**
1088 * Per page live save tracking data.
1089 */
1090typedef struct PGMLIVESAVERAMPAGE
1091{
1092 /** Number of times it has been dirtied. */
1093 uint32_t cDirtied : 24;
1094 /** Whether it is currently dirty. */
1095 uint32_t fDirty : 1;
1096 /** Ignore the page.
1097 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1098 * deal with these after pausing the VM and DevPCI have said it bit about
1099 * remappings. */
1100 uint32_t fIgnore : 1;
1101 /** Was a ZERO page last time around. */
1102 uint32_t fZero : 1;
1103 /** Was a SHARED page last time around. */
1104 uint32_t fShared : 1;
1105 /** Whether the page is/was write monitored in a previous pass. */
1106 uint32_t fWriteMonitored : 1;
1107 /** Whether the page is/was write monitored earlier in this pass. */
1108 uint32_t fWriteMonitoredJustNow : 1;
1109 /** Bits reserved for future use. */
1110 uint32_t u2Reserved : 2;
1111#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1112 /** CRC-32 for the page. This is for internal consistency checks. */
1113 uint32_t u32Crc;
1114#endif
1115} PGMLIVESAVERAMPAGE;
1116#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1117AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1118#else
1119AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1120#endif
1121/** Pointer to the per page live save tracking data. */
1122typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1123
1124/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1125#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1126
1127
1128/**
1129 * Ram range for GC Phys to HC Phys conversion.
1130 *
1131 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1132 * conversions too, but we'll let MM handle that for now.
1133 *
1134 * This structure is used by linked lists in both GC and HC.
1135 */
1136typedef struct PGMRAMRANGE
1137{
1138 /** Start of the range. Page aligned. */
1139 RTGCPHYS GCPhys;
1140 /** Size of the range. (Page aligned of course). */
1141 RTGCPHYS cb;
1142 /** Pointer to the next RAM range - for R3. */
1143 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1144 /** Pointer to the next RAM range - for R0. */
1145 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1146 /** Pointer to the next RAM range - for RC. */
1147 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1148 /** PGM_RAM_RANGE_FLAGS_* flags. */
1149 uint32_t fFlags;
1150 /** Last address in the range (inclusive). Page aligned (-1). */
1151 RTGCPHYS GCPhysLast;
1152 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1153 R3PTRTYPE(void *) pvR3;
1154 /** Live save per page tracking data. */
1155 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1156 /** The range description. */
1157 R3PTRTYPE(const char *) pszDesc;
1158 /** Pointer to self - R0 pointer. */
1159 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1160 /** Pointer to self - RC pointer. */
1161 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1162 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1163 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1164 /** Array of physical guest page tracking structures. */
1165 PGMPAGE aPages[1];
1166} PGMRAMRANGE;
1167/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1168typedef PGMRAMRANGE *PPGMRAMRANGE;
1169
1170/** @name PGMRAMRANGE::fFlags
1171 * @{ */
1172/** The RAM range is floating around as an independent guest mapping. */
1173#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1174/** Ad hoc RAM range for an ROM mapping. */
1175#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1176/** Ad hoc RAM range for an MMIO mapping. */
1177#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1178/** Ad hoc RAM range for an MMIO2 mapping. */
1179#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1180/** @} */
1181
1182/** Tests if a RAM range is an ad hoc one or not.
1183 * @returns true/false.
1184 * @param pRam The RAM range.
1185 */
1186#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1187 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1188
1189
1190/**
1191 * Per page tracking structure for ROM image.
1192 *
1193 * A ROM image may have a shadow page, in which case we may have two pages
1194 * backing it. This structure contains the PGMPAGE for both while
1195 * PGMRAMRANGE have a copy of the active one. It is important that these
1196 * aren't out of sync in any regard other than page pool tracking data.
1197 */
1198typedef struct PGMROMPAGE
1199{
1200 /** The page structure for the virgin ROM page. */
1201 PGMPAGE Virgin;
1202 /** The page structure for the shadow RAM page. */
1203 PGMPAGE Shadow;
1204 /** The current protection setting. */
1205 PGMROMPROT enmProt;
1206 /** Live save status information. Makes use of unused alignment space. */
1207 struct
1208 {
1209 /** The previous protection value. */
1210 uint8_t u8Prot;
1211 /** Written to flag set by the handler. */
1212 bool fWrittenTo;
1213 /** Whether the shadow page is dirty or not. */
1214 bool fDirty;
1215 /** Whether it was dirtied in the recently. */
1216 bool fDirtiedRecently;
1217 } LiveSave;
1218} PGMROMPAGE;
1219AssertCompileSizeAlignment(PGMROMPAGE, 8);
1220/** Pointer to a ROM page tracking structure. */
1221typedef PGMROMPAGE *PPGMROMPAGE;
1222
1223
1224/**
1225 * A registered ROM image.
1226 *
1227 * This is needed to keep track of ROM image since they generally intrude
1228 * into a PGMRAMRANGE. It also keeps track of additional info like the
1229 * two page sets (read-only virgin and read-write shadow), the current
1230 * state of each page.
1231 *
1232 * Because access handlers cannot easily be executed in a different
1233 * context, the ROM ranges needs to be accessible and in all contexts.
1234 */
1235typedef struct PGMROMRANGE
1236{
1237 /** Pointer to the next range - R3. */
1238 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1239 /** Pointer to the next range - R0. */
1240 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1241 /** Pointer to the next range - RC. */
1242 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1243 /** Pointer alignment */
1244 RTRCPTR RCPtrAlignment;
1245 /** Address of the range. */
1246 RTGCPHYS GCPhys;
1247 /** Address of the last byte in the range. */
1248 RTGCPHYS GCPhysLast;
1249 /** Size of the range. */
1250 RTGCPHYS cb;
1251 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1252 uint32_t fFlags;
1253 /** The saved state range ID. */
1254 uint8_t idSavedState;
1255 /** Alignment padding. */
1256 uint8_t au8Alignment[3];
1257 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1258 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1259 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1260 * This is used for strictness checks. */
1261 R3PTRTYPE(const void *) pvOriginal;
1262 /** The ROM description. */
1263 R3PTRTYPE(const char *) pszDesc;
1264 /** The per page tracking structures. */
1265 PGMROMPAGE aPages[1];
1266} PGMROMRANGE;
1267/** Pointer to a ROM range. */
1268typedef PGMROMRANGE *PPGMROMRANGE;
1269
1270
1271/**
1272 * Live save per page data for an MMIO2 page.
1273 *
1274 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1275 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1276 * CRC-32 for detecting changes as well as special handling of zero pages. This
1277 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1278 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1279 * because of speed (2.5x and 6x slower).)
1280 *
1281 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1282 * save but normally is disabled. Since we can write monitore guest
1283 * accesses on our own, we only need this for host accesses. Shouldn't be
1284 * too difficult for DevVGA, VMMDev might be doable, the planned
1285 * networking fun will be fun since it involves ring-0.
1286 */
1287typedef struct PGMLIVESAVEMMIO2PAGE
1288{
1289 /** Set if the page is considered dirty. */
1290 bool fDirty;
1291 /** The number of scans this page has remained unchanged for.
1292 * Only updated for dirty pages. */
1293 uint8_t cUnchangedScans;
1294 /** Whether this page was zero at the last scan. */
1295 bool fZero;
1296 /** Alignment padding. */
1297 bool fReserved;
1298 /** CRC-32 for the first half of the page.
1299 * This is used together with u32CrcH2 to quickly detect changes in the page
1300 * during the non-final passes. */
1301 uint32_t u32CrcH1;
1302 /** CRC-32 for the second half of the page. */
1303 uint32_t u32CrcH2;
1304 /** SHA-1 for the saved page.
1305 * This is used in the final pass to skip pages without changes. */
1306 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1307} PGMLIVESAVEMMIO2PAGE;
1308/** Pointer to a live save status data for an MMIO2 page. */
1309typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1310
1311/**
1312 * A registered MMIO2 (= Device RAM) range.
1313 *
1314 * There are a few reason why we need to keep track of these
1315 * registrations. One of them is the deregistration & cleanup stuff,
1316 * while another is that the PGMRAMRANGE associated with such a region may
1317 * have to be removed from the ram range list.
1318 *
1319 * Overlapping with a RAM range has to be 100% or none at all. The pages
1320 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1321 * will be raised if a partial overlap or an overlap of ROM pages is
1322 * encountered. On an overlap we will free all the existing RAM pages and
1323 * put in the ram range pages instead.
1324 */
1325typedef struct PGMMMIO2RANGE
1326{
1327 /** The owner of the range. (a device) */
1328 PPDMDEVINSR3 pDevInsR3;
1329 /** Pointer to the ring-3 mapping of the allocation. */
1330 RTR3PTR pvR3;
1331 /** Pointer to the next range - R3. */
1332 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1333 /** Whether it's mapped or not. */
1334 bool fMapped;
1335 /** Whether it's overlapping or not. */
1336 bool fOverlapping;
1337 /** The PCI region number.
1338 * @remarks This ASSUMES that nobody will ever really need to have multiple
1339 * PCI devices with matching MMIO region numbers on a single device. */
1340 uint8_t iRegion;
1341 /** The saved state range ID. */
1342 uint8_t idSavedState;
1343 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1344 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1345 /** Live save per page tracking data. */
1346 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1347 /** The associated RAM range. */
1348 PGMRAMRANGE RamRange;
1349} PGMMMIO2RANGE;
1350/** Pointer to a MMIO2 range. */
1351typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1352
1353
1354
1355
1356/**
1357 * PGMPhysRead/Write cache entry
1358 */
1359typedef struct PGMPHYSCACHEENTRY
1360{
1361 /** R3 pointer to physical page. */
1362 R3PTRTYPE(uint8_t *) pbR3;
1363 /** GC Physical address for cache entry */
1364 RTGCPHYS GCPhys;
1365#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1366 RTGCPHYS u32Padding0; /**< alignment padding. */
1367#endif
1368} PGMPHYSCACHEENTRY;
1369
1370/**
1371 * PGMPhysRead/Write cache to reduce REM memory access overhead
1372 */
1373typedef struct PGMPHYSCACHE
1374{
1375 /** Bitmap of valid cache entries */
1376 uint64_t aEntries;
1377 /** Cache entries */
1378 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1379} PGMPHYSCACHE;
1380
1381
1382/** Pointer to an allocation chunk ring-3 mapping. */
1383typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1384/** Pointer to an allocation chunk ring-3 mapping pointer. */
1385typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1386
1387/**
1388 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1389 *
1390 * The primary tree (Core) uses the chunk id as key.
1391 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1392 */
1393typedef struct PGMCHUNKR3MAP
1394{
1395 /** The key is the chunk id. */
1396 AVLU32NODECORE Core;
1397 /** The key is the ageing sequence number. */
1398 AVLLU32NODECORE AgeCore;
1399 /** The current age thingy. */
1400 uint32_t iAge;
1401 /** The current reference count. */
1402 uint32_t volatile cRefs;
1403 /** The current permanent reference count. */
1404 uint32_t volatile cPermRefs;
1405 /** The mapping address. */
1406 void *pv;
1407} PGMCHUNKR3MAP;
1408
1409/**
1410 * Allocation chunk ring-3 mapping TLB entry.
1411 */
1412typedef struct PGMCHUNKR3MAPTLBE
1413{
1414 /** The chunk id. */
1415 uint32_t volatile idChunk;
1416#if HC_ARCH_BITS == 64
1417 uint32_t u32Padding; /**< alignment padding. */
1418#endif
1419 /** The chunk map. */
1420#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1421 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1422#else
1423 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1424#endif
1425} PGMCHUNKR3MAPTLBE;
1426/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1427typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1428
1429/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1430 * @remark Must be a power of two value. */
1431#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1432
1433/**
1434 * Allocation chunk ring-3 mapping TLB.
1435 *
1436 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1437 * At first glance this might look kinda odd since AVL trees are
1438 * supposed to give the most optimial lookup times of all trees
1439 * due to their balancing. However, take a tree with 1023 nodes
1440 * in it, that's 10 levels, meaning that most searches has to go
1441 * down 9 levels before they find what they want. This isn't fast
1442 * compared to a TLB hit. There is the factor of cache misses,
1443 * and of course the problem with trees and branch prediction.
1444 * This is why we use TLBs in front of most of the trees.
1445 *
1446 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1447 * difficult when we switch to the new inlined AVL trees (from kStuff).
1448 */
1449typedef struct PGMCHUNKR3MAPTLB
1450{
1451 /** The TLB entries. */
1452 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1453} PGMCHUNKR3MAPTLB;
1454
1455/**
1456 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1457 * @returns Chunk TLB index.
1458 * @param idChunk The Chunk ID.
1459 */
1460#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1461
1462
1463/**
1464 * Ring-3 guest page mapping TLB entry.
1465 * @remarks used in ring-0 as well at the moment.
1466 */
1467typedef struct PGMPAGER3MAPTLBE
1468{
1469 /** Address of the page. */
1470 RTGCPHYS volatile GCPhys;
1471 /** The guest page. */
1472#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1473 R3PTRTYPE(PPGMPAGE) volatile pPage;
1474#else
1475 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1476#endif
1477 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1478#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1479 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1480#else
1481 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1482#endif
1483 /** The address */
1484#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1485 R3PTRTYPE(void *) volatile pv;
1486#else
1487 R3R0PTRTYPE(void *) volatile pv;
1488#endif
1489#if HC_ARCH_BITS == 32
1490 uint32_t u32Padding; /**< alignment padding. */
1491#endif
1492} PGMPAGER3MAPTLBE;
1493/** Pointer to an entry in the HC physical TLB. */
1494typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1495
1496
1497/** The number of entries in the ring-3 guest page mapping TLB.
1498 * @remarks The value must be a power of two. */
1499#define PGM_PAGER3MAPTLB_ENTRIES 256
1500
1501/**
1502 * Ring-3 guest page mapping TLB.
1503 * @remarks used in ring-0 as well at the moment.
1504 */
1505typedef struct PGMPAGER3MAPTLB
1506{
1507 /** The TLB entries. */
1508 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1509} PGMPAGER3MAPTLB;
1510/** Pointer to the ring-3 guest page mapping TLB. */
1511typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1512
1513/**
1514 * Calculates the index of the TLB entry for the specified guest page.
1515 * @returns Physical TLB index.
1516 * @param GCPhys The guest physical address.
1517 */
1518#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1519
1520
1521/**
1522 * Mapping cache usage set entry.
1523 *
1524 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1525 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1526 * cache. If it's extended to include ring-3, well, then something will
1527 * have be changed here...
1528 */
1529typedef struct PGMMAPSETENTRY
1530{
1531 /** The mapping cache index. */
1532 uint16_t iPage;
1533 /** The number of references.
1534 * The max is UINT16_MAX - 1. */
1535 uint16_t cRefs;
1536#if HC_ARCH_BITS == 64
1537 uint32_t alignment;
1538#endif
1539 /** Pointer to the page. */
1540 RTR0PTR pvPage;
1541 /** The physical address for this entry. */
1542 RTHCPHYS HCPhys;
1543} PGMMAPSETENTRY;
1544/** Pointer to a mapping cache usage set entry. */
1545typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1546
1547/**
1548 * Mapping cache usage set.
1549 *
1550 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1551 * done during exits / traps. The set is
1552 */
1553typedef struct PGMMAPSET
1554{
1555 /** The number of occupied entries.
1556 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1557 * dynamic mappings. */
1558 uint32_t cEntries;
1559 /** The start of the current subset.
1560 * This is UINT32_MAX if no subset is currently open. */
1561 uint32_t iSubset;
1562 /** The index of the current CPU, only valid if the set is open. */
1563 int32_t iCpu;
1564 uint32_t alignment;
1565 /** The entries. */
1566 PGMMAPSETENTRY aEntries[64];
1567 /** HCPhys -> iEntry fast lookup table.
1568 * Use PGMMAPSET_HASH for hashing.
1569 * The entries may or may not be valid, check against cEntries. */
1570 uint8_t aiHashTable[128];
1571} PGMMAPSET;
1572AssertCompileSizeAlignment(PGMMAPSET, 8);
1573/** Pointer to the mapping cache set. */
1574typedef PGMMAPSET *PPGMMAPSET;
1575
1576/** PGMMAPSET::cEntries value for a closed set. */
1577#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1578
1579/** Hash function for aiHashTable. */
1580#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1581
1582/** The max fill size (strict builds). */
1583#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1584
1585
1586/** @name Context neutrual page mapper TLB.
1587 *
1588 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1589 * code is writting in a kind of context neutrual way. Time will show whether
1590 * this actually makes sense or not...
1591 *
1592 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1593 * context ends up using a global mapping cache on some platforms
1594 * (darwin).
1595 *
1596 * @{ */
1597/** @typedef PPGMPAGEMAPTLB
1598 * The page mapper TLB pointer type for the current context. */
1599/** @typedef PPGMPAGEMAPTLB
1600 * The page mapper TLB entry pointer type for the current context. */
1601/** @typedef PPGMPAGEMAPTLB
1602 * The page mapper TLB entry pointer pointer type for the current context. */
1603/** @def PGM_PAGEMAPTLB_ENTRIES
1604 * The number of TLB entries in the page mapper TLB for the current context. */
1605/** @def PGM_PAGEMAPTLB_IDX
1606 * Calculate the TLB index for a guest physical address.
1607 * @returns The TLB index.
1608 * @param GCPhys The guest physical address. */
1609/** @typedef PPGMPAGEMAP
1610 * Pointer to a page mapper unit for current context. */
1611/** @typedef PPPGMPAGEMAP
1612 * Pointer to a page mapper unit pointer for current context. */
1613#ifdef IN_RC
1614// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1615// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1616// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1617# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1618# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1619 typedef void * PPGMPAGEMAP;
1620 typedef void ** PPPGMPAGEMAP;
1621//#elif IN_RING0
1622// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1623// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1624// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1625//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1626//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1627// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1628// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1629#else
1630 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1631 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1632 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1633# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1634# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1635 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1636 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1637#endif
1638/** @} */
1639
1640
1641/** @name PGM Pool Indexes.
1642 * Aka. the unique shadow page identifier.
1643 * @{ */
1644/** NIL page pool IDX. */
1645#define NIL_PGMPOOL_IDX 0
1646/** The first normal index. */
1647#define PGMPOOL_IDX_FIRST_SPECIAL 1
1648/** Page directory (32-bit root). */
1649#define PGMPOOL_IDX_PD 1
1650/** Page Directory Pointer Table (PAE root). */
1651#define PGMPOOL_IDX_PDPT 2
1652/** AMD64 CR3 level index.*/
1653#define PGMPOOL_IDX_AMD64_CR3 3
1654/** Nested paging root.*/
1655#define PGMPOOL_IDX_NESTED_ROOT 4
1656/** The first normal index. */
1657#define PGMPOOL_IDX_FIRST 5
1658/** The last valid index. (inclusive, 14 bits) */
1659#define PGMPOOL_IDX_LAST 0x3fff
1660/** @} */
1661
1662/** The NIL index for the parent chain. */
1663#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1664#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1665
1666/**
1667 * Node in the chain linking a shadowed page to it's parent (user).
1668 */
1669#pragma pack(1)
1670typedef struct PGMPOOLUSER
1671{
1672 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1673 uint16_t iNext;
1674 /** The user page index. */
1675 uint16_t iUser;
1676 /** Index into the user table. */
1677 uint32_t iUserTable;
1678} PGMPOOLUSER, *PPGMPOOLUSER;
1679typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1680#pragma pack()
1681
1682
1683/** The NIL index for the phys ext chain. */
1684#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1685
1686/**
1687 * Node in the chain of physical cross reference extents.
1688 * @todo Calling this an 'extent' is not quite right, find a better name.
1689 */
1690#pragma pack(1)
1691typedef struct PGMPOOLPHYSEXT
1692{
1693 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1694 uint16_t iNext;
1695 /** The user page index. */
1696 uint16_t aidx[3];
1697} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1698typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1699#pragma pack()
1700
1701
1702/**
1703 * The kind of page that's being shadowed.
1704 */
1705typedef enum PGMPOOLKIND
1706{
1707 /** The virtual invalid 0 entry. */
1708 PGMPOOLKIND_INVALID = 0,
1709 /** The entry is free (=unused). */
1710 PGMPOOLKIND_FREE,
1711
1712 /** Shw: 32-bit page table; Gst: no paging */
1713 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1714 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1715 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1716 /** Shw: 32-bit page table; Gst: 4MB page. */
1717 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1718 /** Shw: PAE page table; Gst: no paging */
1719 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1720 /** Shw: PAE page table; Gst: 32-bit page table. */
1721 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1722 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1723 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1724 /** Shw: PAE page table; Gst: PAE page table. */
1725 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1726 /** Shw: PAE page table; Gst: 2MB page. */
1727 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1728
1729 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1730 PGMPOOLKIND_32BIT_PD,
1731 /** Shw: 32-bit page directory. Gst: no paging. */
1732 PGMPOOLKIND_32BIT_PD_PHYS,
1733 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1734 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1735 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1736 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1737 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1738 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1739 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1740 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1741 /** Shw: PAE page directory; Gst: PAE page directory. */
1742 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1743 /** Shw: PAE page directory; Gst: no paging. */
1744 PGMPOOLKIND_PAE_PD_PHYS,
1745
1746 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1747 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1748 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1749 PGMPOOLKIND_PAE_PDPT,
1750 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1751 PGMPOOLKIND_PAE_PDPT_PHYS,
1752
1753 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1754 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1755 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1756 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1757 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1758 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1759 /** Shw: 64-bit page directory table; Gst: no paging */
1760 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1761
1762 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1763 PGMPOOLKIND_64BIT_PML4,
1764
1765 /** Shw: EPT page directory pointer table; Gst: no paging */
1766 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1767 /** Shw: EPT page directory table; Gst: no paging */
1768 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1769 /** Shw: EPT page table; Gst: no paging */
1770 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1771
1772 /** Shw: Root Nested paging table. */
1773 PGMPOOLKIND_ROOT_NESTED,
1774
1775 /** The last valid entry. */
1776 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1777} PGMPOOLKIND;
1778
1779/**
1780 * The access attributes of the page; only applies to big pages.
1781 */
1782typedef enum
1783{
1784 PGMPOOLACCESS_DONTCARE = 0,
1785 PGMPOOLACCESS_USER_RW,
1786 PGMPOOLACCESS_USER_R,
1787 PGMPOOLACCESS_USER_RW_NX,
1788 PGMPOOLACCESS_USER_R_NX,
1789 PGMPOOLACCESS_SUPERVISOR_RW,
1790 PGMPOOLACCESS_SUPERVISOR_R,
1791 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1792 PGMPOOLACCESS_SUPERVISOR_R_NX
1793} PGMPOOLACCESS;
1794
1795/**
1796 * The tracking data for a page in the pool.
1797 */
1798typedef struct PGMPOOLPAGE
1799{
1800 /** AVL node code with the (R3) physical address of this page. */
1801 AVLOHCPHYSNODECORE Core;
1802 /** Pointer to the R3 mapping of the page. */
1803#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1804 R3PTRTYPE(void *) pvPageR3;
1805#else
1806 R3R0PTRTYPE(void *) pvPageR3;
1807#endif
1808 /** The guest physical address. */
1809#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1810 uint32_t Alignment0;
1811#endif
1812 RTGCPHYS GCPhys;
1813
1814 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1815 RTGCPTR pvLastAccessHandlerRip;
1816 RTGCPTR pvLastAccessHandlerFault;
1817 uint64_t cLastAccessHandlerCount;
1818
1819 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1820 uint8_t enmKind;
1821 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1822 uint8_t enmAccess;
1823 /** The index of this page. */
1824 uint16_t idx;
1825 /** The next entry in the list this page currently resides in.
1826 * It's either in the free list or in the GCPhys hash. */
1827 uint16_t iNext;
1828 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1829 uint16_t iUserHead;
1830 /** The number of present entries. */
1831 uint16_t cPresent;
1832 /** The first entry in the table which is present. */
1833 uint16_t iFirstPresent;
1834 /** The number of modifications to the monitored page. */
1835 uint16_t cModifications;
1836 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1837 uint16_t iModifiedNext;
1838 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1839 uint16_t iModifiedPrev;
1840 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1841 uint16_t iMonitoredNext;
1842 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1843 uint16_t iMonitoredPrev;
1844 /** The next page in the age list. */
1845 uint16_t iAgeNext;
1846 /** The previous page in the age list. */
1847 uint16_t iAgePrev;
1848 /** Used to indicate that the page is zeroed. */
1849 bool fZeroed;
1850 /** Used to indicate that a PT has non-global entries. */
1851 bool fSeenNonGlobal;
1852 /** Used to indicate that we're monitoring writes to the guest page. */
1853 bool fMonitored;
1854 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1855 * (All pages are in the age list.) */
1856 bool fCached;
1857 /** This is used by the R3 access handlers when invoked by an async thread.
1858 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1859 bool volatile fReusedFlushPending;
1860 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1861 bool fDirty;
1862
1863 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1864 uint32_t cLocked;
1865 uint32_t idxDirty;
1866 RTGCPTR pvDirtyFault;
1867} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1868/** Pointer to a const pool page. */
1869typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1870
1871
1872/** The hash table size. */
1873# define PGMPOOL_HASH_SIZE 0x40
1874/** The hash function. */
1875# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1876
1877
1878/**
1879 * The shadow page pool instance data.
1880 *
1881 * It's all one big allocation made at init time, except for the
1882 * pages that is. The user nodes follows immediatly after the
1883 * page structures.
1884 */
1885typedef struct PGMPOOL
1886{
1887 /** The VM handle - R3 Ptr. */
1888 PVMR3 pVMR3;
1889 /** The VM handle - R0 Ptr. */
1890 PVMR0 pVMR0;
1891 /** The VM handle - RC Ptr. */
1892 PVMRC pVMRC;
1893 /** The max pool size. This includes the special IDs. */
1894 uint16_t cMaxPages;
1895 /** The current pool size. */
1896 uint16_t cCurPages;
1897 /** The head of the free page list. */
1898 uint16_t iFreeHead;
1899 /* Padding. */
1900 uint16_t u16Padding;
1901 /** Head of the chain of free user nodes. */
1902 uint16_t iUserFreeHead;
1903 /** The number of user nodes we've allocated. */
1904 uint16_t cMaxUsers;
1905 /** The number of present page table entries in the entire pool. */
1906 uint32_t cPresent;
1907 /** Pointer to the array of user nodes - RC pointer. */
1908 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1909 /** Pointer to the array of user nodes - R3 pointer. */
1910 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1911 /** Pointer to the array of user nodes - R0 pointer. */
1912 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1913 /** Head of the chain of free phys ext nodes. */
1914 uint16_t iPhysExtFreeHead;
1915 /** The number of user nodes we've allocated. */
1916 uint16_t cMaxPhysExts;
1917 /** Pointer to the array of physical xref extent - RC pointer. */
1918 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1919 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1920 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1921 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1922 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1923 /** Hash table for GCPhys addresses. */
1924 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1925 /** The head of the age list. */
1926 uint16_t iAgeHead;
1927 /** The tail of the age list. */
1928 uint16_t iAgeTail;
1929 /** Set if the cache is enabled. */
1930 bool fCacheEnabled;
1931 /** Alignment padding. */
1932 bool afPadding1[3];
1933 /** Head of the list of modified pages. */
1934 uint16_t iModifiedHead;
1935 /** The current number of modified pages. */
1936 uint16_t cModifiedPages;
1937 /** Access handler, RC. */
1938 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1939 /** Access handler, R0. */
1940 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1941 /** Access handler, R3. */
1942 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1943 /** The access handler description (R3 ptr). */
1944 R3PTRTYPE(const char *) pszAccessHandler;
1945# if HC_ARCH_BITS == 32
1946 /** Alignment padding. */
1947 uint32_t u32Padding2;
1948# endif
1949 /* Next available slot. */
1950 uint32_t idxFreeDirtyPage;
1951 /* Number of active dirty pages. */
1952 uint32_t cDirtyPages;
1953 /* Array of current dirty pgm pool page indices. */
1954 uint16_t aIdxDirtyPages[16];
1955 uint64_t aDirtyPages[16][512];
1956 /** The number of pages currently in use. */
1957 uint16_t cUsedPages;
1958#ifdef VBOX_WITH_STATISTICS
1959 /** The high water mark for cUsedPages. */
1960 uint16_t cUsedPagesHigh;
1961 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1962 /** Profiling pgmPoolAlloc(). */
1963 STAMPROFILEADV StatAlloc;
1964 /** Profiling pgmR3PoolClearDoIt(). */
1965 STAMPROFILE StatClearAll;
1966 /** Profiling pgmR3PoolReset(). */
1967 STAMPROFILE StatR3Reset;
1968 /** Profiling pgmPoolFlushPage(). */
1969 STAMPROFILE StatFlushPage;
1970 /** Profiling pgmPoolFree(). */
1971 STAMPROFILE StatFree;
1972 /** Counting explicit flushes by PGMPoolFlushPage(). */
1973 STAMCOUNTER StatForceFlushPage;
1974 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1975 STAMCOUNTER StatForceFlushDirtyPage;
1976 /** Counting flushes for reused pages. */
1977 STAMCOUNTER StatForceFlushReused;
1978 /** Profiling time spent zeroing pages. */
1979 STAMPROFILE StatZeroPage;
1980 /** Profiling of pgmPoolTrackDeref. */
1981 STAMPROFILE StatTrackDeref;
1982 /** Profiling pgmTrackFlushGCPhysPT. */
1983 STAMPROFILE StatTrackFlushGCPhysPT;
1984 /** Profiling pgmTrackFlushGCPhysPTs. */
1985 STAMPROFILE StatTrackFlushGCPhysPTs;
1986 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1987 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1988 /** Number of times we've been out of user records. */
1989 STAMCOUNTER StatTrackFreeUpOneUser;
1990 /** Nr of flushed entries. */
1991 STAMCOUNTER StatTrackFlushEntry;
1992 /** Nr of updated entries. */
1993 STAMCOUNTER StatTrackFlushEntryKeep;
1994 /** Profiling deref activity related tracking GC physical pages. */
1995 STAMPROFILE StatTrackDerefGCPhys;
1996 /** Number of linear searches for a HCPhys in the ram ranges. */
1997 STAMCOUNTER StatTrackLinearRamSearches;
1998 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1999 STAMCOUNTER StamTrackPhysExtAllocFailures;
2000 /** Profiling the RC/R0 access handler. */
2001 STAMPROFILE StatMonitorRZ;
2002 /** Times we've failed interpreting the instruction. */
2003 STAMCOUNTER StatMonitorRZEmulateInstr;
2004 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2005 STAMPROFILE StatMonitorRZFlushPage;
2006 /* Times we've detected a page table reinit. */
2007 STAMCOUNTER StatMonitorRZFlushReinit;
2008 /** Counting flushes for pages that are modified too often. */
2009 STAMCOUNTER StatMonitorRZFlushModOverflow;
2010 /** Times we've detected fork(). */
2011 STAMCOUNTER StatMonitorRZFork;
2012 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2013 STAMPROFILE StatMonitorRZHandled;
2014 /** Times we've failed interpreting a patch code instruction. */
2015 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2016 /** Times we've failed interpreting a patch code instruction during flushing. */
2017 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2018 /** The number of times we've seen rep prefixes we can't handle. */
2019 STAMCOUNTER StatMonitorRZRepPrefix;
2020 /** Profiling the REP STOSD cases we've handled. */
2021 STAMPROFILE StatMonitorRZRepStosd;
2022 /** Nr of handled PT faults. */
2023 STAMCOUNTER StatMonitorRZFaultPT;
2024 /** Nr of handled PD faults. */
2025 STAMCOUNTER StatMonitorRZFaultPD;
2026 /** Nr of handled PDPT faults. */
2027 STAMCOUNTER StatMonitorRZFaultPDPT;
2028 /** Nr of handled PML4 faults. */
2029 STAMCOUNTER StatMonitorRZFaultPML4;
2030
2031 /** Profiling the R3 access handler. */
2032 STAMPROFILE StatMonitorR3;
2033 /** Times we've failed interpreting the instruction. */
2034 STAMCOUNTER StatMonitorR3EmulateInstr;
2035 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2036 STAMPROFILE StatMonitorR3FlushPage;
2037 /* Times we've detected a page table reinit. */
2038 STAMCOUNTER StatMonitorR3FlushReinit;
2039 /** Counting flushes for pages that are modified too often. */
2040 STAMCOUNTER StatMonitorR3FlushModOverflow;
2041 /** Times we've detected fork(). */
2042 STAMCOUNTER StatMonitorR3Fork;
2043 /** Profiling the R3 access we've handled (except REP STOSD). */
2044 STAMPROFILE StatMonitorR3Handled;
2045 /** The number of times we've seen rep prefixes we can't handle. */
2046 STAMCOUNTER StatMonitorR3RepPrefix;
2047 /** Profiling the REP STOSD cases we've handled. */
2048 STAMPROFILE StatMonitorR3RepStosd;
2049 /** Nr of handled PT faults. */
2050 STAMCOUNTER StatMonitorR3FaultPT;
2051 /** Nr of handled PD faults. */
2052 STAMCOUNTER StatMonitorR3FaultPD;
2053 /** Nr of handled PDPT faults. */
2054 STAMCOUNTER StatMonitorR3FaultPDPT;
2055 /** Nr of handled PML4 faults. */
2056 STAMCOUNTER StatMonitorR3FaultPML4;
2057 /** The number of times we're called in an async thread an need to flush. */
2058 STAMCOUNTER StatMonitorR3Async;
2059 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2060 STAMCOUNTER StatResetDirtyPages;
2061 /** Times we've called pgmPoolAddDirtyPage. */
2062 STAMCOUNTER StatDirtyPage;
2063 /** Times we've had to flush duplicates for dirty page management. */
2064 STAMCOUNTER StatDirtyPageDupFlush;
2065 /** Times we've had to flush because of overflow. */
2066 STAMCOUNTER StatDirtyPageOverFlowFlush;
2067
2068 /** The high wather mark for cModifiedPages. */
2069 uint16_t cModifiedPagesHigh;
2070 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2071
2072 /** The number of cache hits. */
2073 STAMCOUNTER StatCacheHits;
2074 /** The number of cache misses. */
2075 STAMCOUNTER StatCacheMisses;
2076 /** The number of times we've got a conflict of 'kind' in the cache. */
2077 STAMCOUNTER StatCacheKindMismatches;
2078 /** Number of times we've been out of pages. */
2079 STAMCOUNTER StatCacheFreeUpOne;
2080 /** The number of cacheable allocations. */
2081 STAMCOUNTER StatCacheCacheable;
2082 /** The number of uncacheable allocations. */
2083 STAMCOUNTER StatCacheUncacheable;
2084#else
2085 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2086#endif
2087 /** The AVL tree for looking up a page by its HC physical address. */
2088 AVLOHCPHYSTREE HCPhysTree;
2089 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2090 /** Array of pages. (cMaxPages in length)
2091 * The Id is the index into thist array.
2092 */
2093 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2094} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2095AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2096AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2097AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2098#ifdef VBOX_WITH_STATISTICS
2099AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2100#endif
2101AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2102
2103
2104/** @def PGMPOOL_PAGE_2_PTR
2105 * Maps a pool page pool into the current context.
2106 *
2107 * @returns VBox status code.
2108 * @param pVM The VM handle.
2109 * @param pPage The pool page.
2110 *
2111 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2112 * small page window employeed by that function. Be careful.
2113 * @remark There is no need to assert on the result.
2114 */
2115#if defined(IN_RC)
2116# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2117#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2118# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2119#elif defined(VBOX_STRICT)
2120# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2121DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2122{
2123 Assert(pPage && pPage->pvPageR3);
2124 return pPage->pvPageR3;
2125}
2126#else
2127# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2128#endif
2129
2130/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2131 * Maps a pool page pool into the current context.
2132 *
2133 * @returns VBox status code.
2134 * @param pPGM Pointer to the PGM instance data.
2135 * @param pPage The pool page.
2136 *
2137 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2138 * small page window employeed by that function. Be careful.
2139 * @remark There is no need to assert on the result.
2140 */
2141#if defined(IN_RC)
2142# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2143#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2144# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2145#else
2146# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2147#endif
2148
2149/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2150 * Maps a pool page pool into the current context.
2151 *
2152 * @returns VBox status code.
2153 * @param pPGM Pointer to the PGMCPU instance data.
2154 * @param pPage The pool page.
2155 *
2156 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2157 * small page window employeed by that function. Be careful.
2158 * @remark There is no need to assert on the result.
2159 */
2160#if defined(IN_RC)
2161# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2162#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2163# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2164#else
2165# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2166#endif
2167
2168
2169/** @name Per guest page tracking data.
2170 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2171 * is to use more bits for it and split it up later on. But for now we'll play
2172 * safe and change as little as possible.
2173 *
2174 * The 16-bit word has two parts:
2175 *
2176 * The first 14-bit forms the @a idx field. It is either the index of a page in
2177 * the shadow page pool, or and index into the extent list.
2178 *
2179 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2180 * shadow page pool references to the page. If cRefs equals
2181 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2182 * (misnomer) table and not the shadow page pool.
2183 *
2184 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2185 * the 16-bit word.
2186 *
2187 * @{ */
2188/** The shift count for getting to the cRefs part. */
2189#define PGMPOOL_TD_CREFS_SHIFT 14
2190/** The mask applied after shifting the tracking data down by
2191 * PGMPOOL_TD_CREFS_SHIFT. */
2192#define PGMPOOL_TD_CREFS_MASK 0x3
2193/** The cRef value used to indiciate that the idx is the head of a
2194 * physical cross reference list. */
2195#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2196/** The shift used to get idx. */
2197#define PGMPOOL_TD_IDX_SHIFT 0
2198/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2199#define PGMPOOL_TD_IDX_MASK 0x3fff
2200/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2201 * simply too many mappings of this page. */
2202#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2203
2204/** @def PGMPOOL_TD_MAKE
2205 * Makes a 16-bit tracking data word.
2206 *
2207 * @returns tracking data.
2208 * @param cRefs The @a cRefs field. Must be within bounds!
2209 * @param idx The @a idx field. Must also be within bounds! */
2210#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2211
2212/** @def PGMPOOL_TD_GET_CREFS
2213 * Get the @a cRefs field from a tracking data word.
2214 *
2215 * @returns The @a cRefs field
2216 * @param u16 The tracking data word. */
2217#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2218
2219/** @def PGMPOOL_TD_GET_IDX
2220 * Get the @a idx field from a tracking data word.
2221 *
2222 * @returns The @a idx field
2223 * @param u16 The tracking data word. */
2224#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2225/** @} */
2226
2227
2228/**
2229 * Trees are using self relative offsets as pointers.
2230 * So, all its data, including the root pointer, must be in the heap for HC and GC
2231 * to have the same layout.
2232 */
2233typedef struct PGMTREES
2234{
2235 /** Physical access handlers (AVL range+offsetptr tree). */
2236 AVLROGCPHYSTREE PhysHandlers;
2237 /** Virtual access handlers (AVL range + GC ptr tree). */
2238 AVLROGCPTRTREE VirtHandlers;
2239 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2240 AVLROGCPHYSTREE PhysToVirtHandlers;
2241 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2242 AVLROGCPTRTREE HyperVirtHandlers;
2243} PGMTREES;
2244/** Pointer to PGM trees. */
2245typedef PGMTREES *PPGMTREES;
2246
2247
2248/** @name Paging mode macros
2249 * @{ */
2250#ifdef IN_RC
2251# define PGM_CTX(a,b) a##RC##b
2252# define PGM_CTX_STR(a,b) a "GC" b
2253# define PGM_CTX_DECL(type) VMMRCDECL(type)
2254#else
2255# ifdef IN_RING3
2256# define PGM_CTX(a,b) a##R3##b
2257# define PGM_CTX_STR(a,b) a "R3" b
2258# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2259# else
2260# define PGM_CTX(a,b) a##R0##b
2261# define PGM_CTX_STR(a,b) a "R0" b
2262# define PGM_CTX_DECL(type) VMMDECL(type)
2263# endif
2264#endif
2265
2266#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2267#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2268#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2269#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2270#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2271#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2272#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2273#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2274#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2275#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2276#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2277#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2278#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2279#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2280#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2281#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2282#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2283
2284#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2285#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2286#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2287#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2288#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2289#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2290#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2291#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2292#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2293#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2294#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2295#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2296#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2297#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2298#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2299#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2300#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2301
2302/* Shw_Gst */
2303#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2304#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2305#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2306#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2307#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2308#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2309#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2310#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2311#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2312#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2313#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2314#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2315#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2316#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2317#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2318#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2319#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2320#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2321#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2322
2323#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2324#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2325#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2326#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2327#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2328#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2329#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2330#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2331#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2332#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2333#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2334#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2335#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2336#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2337#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2338#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2339#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2340#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2341#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2342#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2343#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2344#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2345#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2346#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2347#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2348#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2349#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2350#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2351#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2352#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2353#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2354#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2355#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2356#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2357#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2358#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2359#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2360
2361#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2362#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2363/** @} */
2364
2365/**
2366 * Data for each paging mode.
2367 */
2368typedef struct PGMMODEDATA
2369{
2370 /** The guest mode type. */
2371 uint32_t uGstType;
2372 /** The shadow mode type. */
2373 uint32_t uShwType;
2374
2375 /** @name Function pointers for Shadow paging.
2376 * @{
2377 */
2378 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2379 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2380 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2381 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2382
2383 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2384 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2385
2386 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2387 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2388 /** @} */
2389
2390 /** @name Function pointers for Guest paging.
2391 * @{
2392 */
2393 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2394 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2395 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2396 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2397 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2398 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2399 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2400 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2401 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2402 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2403 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2404 /** @} */
2405
2406 /** @name Function pointers for Both Shadow and Guest paging.
2407 * @{
2408 */
2409 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2410 /* no pfnR3BthTrap0eHandler */
2411 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2412 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2413 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2414 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2415 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2416#ifdef VBOX_STRICT
2417 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2418#endif
2419 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2420 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2421
2422 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2423 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2424 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2425 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2426 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2427 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2428#ifdef VBOX_STRICT
2429 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2430#endif
2431 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2432 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2433
2434 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2435 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2436 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2437 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2438 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2439 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2440#ifdef VBOX_STRICT
2441 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2442#endif
2443 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2444 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2445 /** @} */
2446} PGMMODEDATA, *PPGMMODEDATA;
2447
2448
2449
2450/**
2451 * Converts a PGM pointer into a VM pointer.
2452 * @returns Pointer to the VM structure the PGM is part of.
2453 * @param pPGM Pointer to PGM instance data.
2454 */
2455#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2456
2457/**
2458 * PGM Data (part of VM)
2459 */
2460typedef struct PGM
2461{
2462 /** Offset to the VM structure. */
2463 RTINT offVM;
2464 /** Offset of the PGMCPU structure relative to VMCPU. */
2465 RTINT offVCpuPGM;
2466
2467 /** @cfgm{RamPreAlloc, boolean, false}
2468 * Indicates whether the base RAM should all be allocated before starting
2469 * the VM (default), or if it should be allocated when first written to.
2470 */
2471 bool fRamPreAlloc;
2472 /** Indicates whether write monitoring is currently in use.
2473 * This is used to prevent conflicts between live saving and page sharing
2474 * detection. */
2475 bool fPhysWriteMonitoringEngaged;
2476 /** Alignment padding. */
2477 bool afAlignment0[2];
2478
2479 /*
2480 * This will be redefined at least two more times before we're done, I'm sure.
2481 * The current code is only to get on with the coding.
2482 * - 2004-06-10: initial version, bird.
2483 * - 2004-07-02: 1st time, bird.
2484 * - 2004-10-18: 2nd time, bird.
2485 * - 2005-07-xx: 3rd time, bird.
2486 */
2487
2488 /** The host paging mode. (This is what SUPLib reports.) */
2489 SUPPAGINGMODE enmHostMode;
2490
2491 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2492 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2493 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2494 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2495
2496 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2497 RTGCPHYS GCPhys4MBPSEMask;
2498
2499 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2500 * This is sorted by physical address and contains no overlapping ranges. */
2501 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2502 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2503 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2504 /** RC pointer corresponding to PGM::pRamRangesR3. */
2505 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2506 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2507 * range is linked or unlinked. */
2508 uint32_t volatile idRamRangesGen;
2509
2510 /** Pointer to the list of ROM ranges - for R3.
2511 * This is sorted by physical address and contains no overlapping ranges. */
2512 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2513 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2514 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2515 /** RC pointer corresponding to PGM::pRomRangesR3. */
2516 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2517#if HC_ARCH_BITS == 64
2518 /** Alignment padding. */
2519 RTRCPTR GCPtrPadding2;
2520#endif
2521
2522 /** Pointer to the list of MMIO2 ranges - for R3.
2523 * Registration order. */
2524 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2525
2526 /** PGM offset based trees - R3 Ptr. */
2527 R3PTRTYPE(PPGMTREES) pTreesR3;
2528 /** PGM offset based trees - R0 Ptr. */
2529 R0PTRTYPE(PPGMTREES) pTreesR0;
2530 /** PGM offset based trees - RC Ptr. */
2531 RCPTRTYPE(PPGMTREES) pTreesRC;
2532
2533 /** Linked list of GC mappings - for RC.
2534 * The list is sorted ascending on address.
2535 */
2536 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2537 /** Linked list of GC mappings - for HC.
2538 * The list is sorted ascending on address.
2539 */
2540 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2541 /** Linked list of GC mappings - for R0.
2542 * The list is sorted ascending on address.
2543 */
2544 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2545
2546 /** Pointer to the 5 page CR3 content mapping.
2547 * The first page is always the CR3 (in some form) while the 4 other pages
2548 * are used of the PDs in PAE mode. */
2549 RTGCPTR GCPtrCR3Mapping;
2550#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2551 uint32_t u32Alignment1;
2552#endif
2553
2554 /** Indicates that PGMR3FinalizeMappings has been called and that further
2555 * PGMR3MapIntermediate calls will be rejected. */
2556 bool fFinalizedMappings;
2557 /** If set no conflict checks are required. */
2558 bool fMappingsFixed;
2559 /** If set if restored as fixed but we were unable to re-fixate at the old
2560 * location because of room or address incompatibilities. */
2561 bool fMappingsFixedRestored;
2562 /** If set, then no mappings are put into the shadow page table.
2563 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2564 bool fMappingsDisabled;
2565 /** Size of fixed mapping.
2566 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2567 uint32_t cbMappingFixed;
2568 /** Base address (GC) of fixed mapping.
2569 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2570 RTGCPTR GCPtrMappingFixed;
2571 /** The address of the previous RAM range mapping. */
2572 RTGCPTR GCPtrPrevRamRangeMapping;
2573
2574 /** @name Intermediate Context
2575 * @{ */
2576 /** Pointer to the intermediate page directory - Normal. */
2577 R3PTRTYPE(PX86PD) pInterPD;
2578 /** Pointer to the intermedate page tables - Normal.
2579 * There are two page tables, one for the identity mapping and one for
2580 * the host context mapping (of the core code). */
2581 R3PTRTYPE(PX86PT) apInterPTs[2];
2582 /** Pointer to the intermedate page tables - PAE. */
2583 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2584 /** Pointer to the intermedate page directory - PAE. */
2585 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2586 /** Pointer to the intermedate page directory - PAE. */
2587 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2588 /** Pointer to the intermedate page-map level 4 - AMD64. */
2589 R3PTRTYPE(PX86PML4) pInterPaePML4;
2590 /** Pointer to the intermedate page directory - AMD64. */
2591 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2592 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2593 RTHCPHYS HCPhysInterPD;
2594 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2595 RTHCPHYS HCPhysInterPaePDPT;
2596 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2597 RTHCPHYS HCPhysInterPaePML4;
2598 /** @} */
2599
2600 /** Base address of the dynamic page mapping area.
2601 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2602 */
2603 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2604 /** The index of the last entry used in the dynamic page mapping area. */
2605 RTUINT iDynPageMapLast;
2606 /** Cache containing the last entries in the dynamic page mapping area.
2607 * The cache size is covering half of the mapping area. */
2608 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2609 /** Keep a lock counter for the full (!) mapping area. */
2610 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2611
2612 /** The address of the ring-0 mapping cache if we're making use of it. */
2613 RTR0PTR pvR0DynMapUsed;
2614#if HC_ARCH_BITS == 32
2615 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2616 uint32_t u32Alignment2;
2617#endif
2618
2619 /** PGM critical section.
2620 * This protects the physical & virtual access handlers, ram ranges,
2621 * and the page flag updating (some of it anyway).
2622 */
2623 PDMCRITSECT CritSect;
2624
2625 /** Pointer to SHW+GST mode data (function pointers).
2626 * The index into this table is made up from */
2627 R3PTRTYPE(PPGMMODEDATA) paModeData;
2628
2629 /** Shadow Page Pool - R3 Ptr. */
2630 R3PTRTYPE(PPGMPOOL) pPoolR3;
2631 /** Shadow Page Pool - R0 Ptr. */
2632 R0PTRTYPE(PPGMPOOL) pPoolR0;
2633 /** Shadow Page Pool - RC Ptr. */
2634 RCPTRTYPE(PPGMPOOL) pPoolRC;
2635
2636 /** We're not in a state which permits writes to guest memory.
2637 * (Only used in strict builds.) */
2638 bool fNoMorePhysWrites;
2639 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2640 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2641
2642 /**
2643 * Data associated with managing the ring-3 mappings of the allocation chunks.
2644 */
2645 struct
2646 {
2647 /** The chunk tree, ordered by chunk id. */
2648#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2649 R3PTRTYPE(PAVLU32NODECORE) pTree;
2650#else
2651 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2652#endif
2653 /** The chunk age tree, ordered by ageing sequence number. */
2654 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2655 /** The chunk mapping TLB. */
2656 PGMCHUNKR3MAPTLB Tlb;
2657 /** The number of mapped chunks. */
2658 uint32_t c;
2659 /** The maximum number of mapped chunks.
2660 * @cfgm PGM/MaxRing3Chunks */
2661 uint32_t cMax;
2662 /** The current time. */
2663 uint32_t iNow;
2664 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2665 uint32_t AgeingCountdown;
2666 } ChunkR3Map;
2667
2668 /**
2669 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2670 */
2671 PGMPAGER3MAPTLB PhysTlbHC;
2672
2673 /** @name The zero page.
2674 * @{ */
2675 /** The host physical address of the zero page. */
2676 RTHCPHYS HCPhysZeroPg;
2677 /** The ring-3 mapping of the zero page. */
2678 RTR3PTR pvZeroPgR3;
2679 /** The ring-0 mapping of the zero page. */
2680 RTR0PTR pvZeroPgR0;
2681 /** The GC mapping of the zero page. */
2682 RTGCPTR pvZeroPgRC;
2683 /** @}*/
2684
2685 /** The number of handy pages. */
2686 uint32_t cHandyPages;
2687
2688 /** The number of large handy pages. */
2689 uint32_t cLargeHandyPages;
2690
2691 /**
2692 * Array of handy pages.
2693 *
2694 * This array is used in a two way communication between pgmPhysAllocPage
2695 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2696 * an intermediary.
2697 *
2698 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2699 * (The current size of 32 pages, means 128 KB of handy memory.)
2700 */
2701 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2702
2703 /**
2704 * Array of large handy pages. (currently size 1)
2705 *
2706 * This array is used in a two way communication between pgmPhysAllocLargePage
2707 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2708 * an intermediary.
2709 */
2710 GMMPAGEDESC aLargeHandyPage[1];
2711
2712 /**
2713 * Live save data.
2714 */
2715 struct
2716 {
2717 /** Per type statistics. */
2718 struct
2719 {
2720 /** The number of ready pages. */
2721 uint32_t cReadyPages;
2722 /** The number of dirty pages. */
2723 uint32_t cDirtyPages;
2724 /** The number of ready zero pages. */
2725 uint32_t cZeroPages;
2726 /** The number of write monitored pages. */
2727 uint32_t cMonitoredPages;
2728 } Rom,
2729 Mmio2,
2730 Ram;
2731 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2732 uint32_t cIgnoredPages;
2733 /** Indicates that a live save operation is active. */
2734 bool fActive;
2735 /** Padding. */
2736 bool afReserved[2];
2737 /** The next history index. */
2738 uint8_t iDirtyPagesHistory;
2739 /** History of the total amount of dirty pages. */
2740 uint32_t acDirtyPagesHistory[64];
2741 /** Short term dirty page average. */
2742 uint32_t cDirtyPagesShort;
2743 /** Long term dirty page average. */
2744 uint32_t cDirtyPagesLong;
2745 /** The number of saved pages. This is used to get some kind of estimate of the
2746 * link speed so we can decide when we're done. It is reset after the first
2747 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2748 * zero pages. */
2749 uint64_t cSavedPages;
2750 /** The nanosecond timestamp when cSavedPages was 0. */
2751 uint64_t uSaveStartNS;
2752 /** Pages per second (for statistics). */
2753 uint32_t cPagesPerSecond;
2754 uint32_t cAlignment;
2755 } LiveSave;
2756
2757 /** @name Error injection.
2758 * @{ */
2759 /** Inject handy page allocation errors pretending we're completely out of
2760 * memory. */
2761 bool volatile fErrInjHandyPages;
2762 /** Padding. */
2763 bool afReserved[3];
2764 /** @} */
2765
2766 /** @name Release Statistics
2767 * @{ */
2768 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2769 uint32_t cPrivatePages; /**< The number of private pages. */
2770 uint32_t cSharedPages; /**< The number of shared pages. */
2771 uint32_t cZeroPages; /**< The number of zero backed pages. */
2772 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2773 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2774 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2775 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2776 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2777
2778 /** The number of times we were forced to change the hypervisor region location. */
2779 STAMCOUNTER cRelocations;
2780
2781 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
2782 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
2783 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2784 /** @} */
2785
2786#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2787 /* R3 only: */
2788 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2789 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2790
2791 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2792 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2793 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2794 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2795 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2796 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2797 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2798 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2799 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2800 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2801 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2802 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2803 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2804 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2805 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2806 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2807 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2808 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2809 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2810 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2811/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2812 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2813 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2814/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2815
2816 /* RC only: */
2817 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2818 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2819 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2820 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2821
2822 STAMCOUNTER StatRZPhysRead;
2823 STAMCOUNTER StatRZPhysReadBytes;
2824 STAMCOUNTER StatRZPhysWrite;
2825 STAMCOUNTER StatRZPhysWriteBytes;
2826 STAMCOUNTER StatR3PhysRead;
2827 STAMCOUNTER StatR3PhysReadBytes;
2828 STAMCOUNTER StatR3PhysWrite;
2829 STAMCOUNTER StatR3PhysWriteBytes;
2830 STAMCOUNTER StatRCPhysRead;
2831 STAMCOUNTER StatRCPhysReadBytes;
2832 STAMCOUNTER StatRCPhysWrite;
2833 STAMCOUNTER StatRCPhysWriteBytes;
2834
2835 STAMCOUNTER StatRZPhysSimpleRead;
2836 STAMCOUNTER StatRZPhysSimpleReadBytes;
2837 STAMCOUNTER StatRZPhysSimpleWrite;
2838 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2839 STAMCOUNTER StatR3PhysSimpleRead;
2840 STAMCOUNTER StatR3PhysSimpleReadBytes;
2841 STAMCOUNTER StatR3PhysSimpleWrite;
2842 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2843 STAMCOUNTER StatRCPhysSimpleRead;
2844 STAMCOUNTER StatRCPhysSimpleReadBytes;
2845 STAMCOUNTER StatRCPhysSimpleWrite;
2846 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2847
2848 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2849 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2850 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2851 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2852 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2853 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2854#endif
2855} PGM;
2856#ifndef IN_TSTVMSTRUCTGC /* HACK */
2857AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2858AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2859AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2860AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2861AssertCompileMemberAlignment(PGM, CritSect, 8);
2862AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2863AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2864AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2865AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2866AssertCompileMemberAlignment(PGM, cRelocations, 8);
2867#endif /* !IN_TSTVMSTRUCTGC */
2868/** Pointer to the PGM instance data. */
2869typedef PGM *PPGM;
2870
2871
2872/**
2873 * Converts a PGMCPU pointer into a VM pointer.
2874 * @returns Pointer to the VM structure the PGM is part of.
2875 * @param pPGM Pointer to PGMCPU instance data.
2876 */
2877#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2878
2879/**
2880 * Converts a PGMCPU pointer into a PGM pointer.
2881 * @returns Pointer to the VM structure the PGM is part of.
2882 * @param pPGM Pointer to PGMCPU instance data.
2883 */
2884#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2885
2886/**
2887 * PGMCPU Data (part of VMCPU).
2888 */
2889typedef struct PGMCPU
2890{
2891 /** Offset to the VM structure. */
2892 RTINT offVM;
2893 /** Offset to the VMCPU structure. */
2894 RTINT offVCpu;
2895 /** Offset of the PGM structure relative to VMCPU. */
2896 RTINT offPGM;
2897 RTINT uPadding0; /**< structure size alignment. */
2898
2899#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2900 /** Automatically tracked physical memory mapping set.
2901 * Ring-0 and strict raw-mode builds. */
2902 PGMMAPSET AutoSet;
2903#endif
2904
2905 /** A20 gate mask.
2906 * Our current approach to A20 emulation is to let REM do it and don't bother
2907 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2908 * But whould need arrise, we'll subject physical addresses to this mask. */
2909 RTGCPHYS GCPhysA20Mask;
2910 /** A20 gate state - boolean! */
2911 bool fA20Enabled;
2912
2913 /** What needs syncing (PGM_SYNC_*).
2914 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2915 * PGMFlushTLB, and PGMR3Load. */
2916 RTUINT fSyncFlags;
2917
2918 /** The shadow paging mode. */
2919 PGMMODE enmShadowMode;
2920 /** The guest paging mode. */
2921 PGMMODE enmGuestMode;
2922
2923 /** The current physical address representing in the guest CR3 register. */
2924 RTGCPHYS GCPhysCR3;
2925
2926 /** @name 32-bit Guest Paging.
2927 * @{ */
2928 /** The guest's page directory, R3 pointer. */
2929 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2930#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2931 /** The guest's page directory, R0 pointer. */
2932 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2933#endif
2934 /** The guest's page directory, static RC mapping. */
2935 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2936 /** @} */
2937
2938 /** @name PAE Guest Paging.
2939 * @{ */
2940 /** The guest's page directory pointer table, static RC mapping. */
2941 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2942 /** The guest's page directory pointer table, R3 pointer. */
2943 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2944#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2945 /** The guest's page directory pointer table, R0 pointer. */
2946 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2947#endif
2948
2949 /** The guest's page directories, R3 pointers.
2950 * These are individual pointers and don't have to be adjecent.
2951 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2952 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2953 /** The guest's page directories, R0 pointers.
2954 * Same restrictions as apGstPaePDsR3. */
2955#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2956 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2957#endif
2958 /** The guest's page directories, static GC mapping.
2959 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2960 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2961 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2962 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2963 RTGCPHYS aGCPhysGstPaePDs[4];
2964 /** The physical addresses of the monitored guest page directories (PAE). */
2965 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2966 /** @} */
2967
2968 /** @name AMD64 Guest Paging.
2969 * @{ */
2970 /** The guest's page directory pointer table, R3 pointer. */
2971 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2972#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2973 /** The guest's page directory pointer table, R0 pointer. */
2974 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2975#else
2976 RTR0PTR alignment6b; /**< alignment equalizer. */
2977#endif
2978 /** @} */
2979
2980 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2981 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2982 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2983 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2984 /** Pointer to the page of the current active CR3 - RC Ptr. */
2985 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2986 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2987 uint32_t iShwUser;
2988 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2989 uint32_t iShwUserTable;
2990# if HC_ARCH_BITS == 64
2991 RTRCPTR alignment6; /**< structure size alignment. */
2992# endif
2993 /** @} */
2994
2995 /** @name Function pointers for Shadow paging.
2996 * @{
2997 */
2998 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2999 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3000 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3001 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3002
3003 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3004 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3005
3006 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3007 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3008
3009 /** @} */
3010
3011 /** @name Function pointers for Guest paging.
3012 * @{
3013 */
3014 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3015 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3016 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3017 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3018 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3019 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3020 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3021 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3022#if HC_ARCH_BITS == 64
3023 RTRCPTR alignment3; /**< structure size alignment. */
3024#endif
3025
3026 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3027 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3028 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3029 /** @} */
3030
3031 /** @name Function pointers for Both Shadow and Guest paging.
3032 * @{
3033 */
3034 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3035 /* no pfnR3BthTrap0eHandler */
3036 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3037 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3038 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3039 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3040 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3041 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3042 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3043 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3044
3045 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3046 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3047 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3048 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3049 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3050 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3051 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3052 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3053 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3054
3055 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3056 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3057 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3058 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3059 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3060 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3061 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3062 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3063 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3064 RTRCPTR alignment2; /**< structure size alignment. */
3065 /** @} */
3066
3067 /** For saving stack space, the disassembler state is allocated here instead of
3068 * on the stack.
3069 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3070 union
3071 {
3072 /** The disassembler scratch space. */
3073 DISCPUSTATE DisState;
3074 /** Padding. */
3075 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3076 };
3077
3078 /* Count the number of pgm pool access handler calls. */
3079 uint64_t cPoolAccessHandler;
3080
3081 /** @name Release Statistics
3082 * @{ */
3083 /** The number of times the guest has switched mode since last reset or statistics reset. */
3084 STAMCOUNTER cGuestModeChanges;
3085 /** @} */
3086
3087#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3088 /** @name Statistics
3089 * @{ */
3090 /** RC: Which statistic this \#PF should be attributed to. */
3091 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3092 RTRCPTR padding0;
3093 /** R0: Which statistic this \#PF should be attributed to. */
3094 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3095 RTR0PTR padding1;
3096
3097 /* Common */
3098 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3099 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3100
3101 /* R0 only: */
3102 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3103 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3104 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3105 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3106 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3107 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3108 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3109 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3110 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3111 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3112 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3113 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3114 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3115 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3116 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3117 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3118 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3119 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3120 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3121 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3122 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3123 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3124 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3125 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3126 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3127 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3128
3129 /* RZ only: */
3130 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3131 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3132 STAMPROFILE StatRZTrap0eTimeSyncPT;
3133 STAMPROFILE StatRZTrap0eTimeMapping;
3134 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3135 STAMPROFILE StatRZTrap0eTimeHandlers;
3136 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3137 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3138 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3139 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3140 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3141 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3142 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3143 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3144 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3145 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3146 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3147 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3148 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3149 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3150 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3151 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3152 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3153 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3154 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3155 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3156 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3157 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3158 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3159 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3160 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3161 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3162 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3163 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3164 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3165 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3166 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3167 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3168 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3169 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3170 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3171 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3172 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3173 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3174 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3175 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3176 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3177 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3178 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3179
3180 /* HC - R3 and (maybe) R0: */
3181
3182 /* RZ & R3: */
3183 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3184 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3185 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3186 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3187 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3188 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3189 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3190 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3191 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3192 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3193 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3194 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3195 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3196 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3197 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3198 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3199 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3200 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3201 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3202 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3203 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3204 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3205 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3206 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3207 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3208 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3209 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3210 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3211 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3212 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3213 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3214 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3215 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3216 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3217 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3218 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3219 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3220 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3221 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3222 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3223 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3224 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3225 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3226 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3227 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3228 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3229
3230 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3231 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3232 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3233 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3234 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3235 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3236 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3237 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3238 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3239 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3240 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3241 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3242 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3243 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3244 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3245 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3246 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3247 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3248 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3249 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3250 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3251 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3252 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3253 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3254 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3255 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3256 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3257 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3258 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3259 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3260 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3261 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3262 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3263 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3264 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3265 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3266 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3267 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3268 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3269 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3270 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3271 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3272 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3273 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3274 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3275 /** @} */
3276#endif /* VBOX_WITH_STATISTICS */
3277} PGMCPU;
3278/** Pointer to the per-cpu PGM data. */
3279typedef PGMCPU *PPGMCPU;
3280
3281
3282/** @name PGM::fSyncFlags Flags
3283 * @{
3284 */
3285/** Updates the virtual access handler state bit in PGMPAGE. */
3286#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3287/** Always sync CR3. */
3288#define PGM_SYNC_ALWAYS RT_BIT(1)
3289/** Check monitoring on next CR3 (re)load and invalidate page.
3290 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3291#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3292/** Check guest mapping in SyncCR3. */
3293#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3294/** Clear the page pool (a light weight flush). */
3295#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3296#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3297/** @} */
3298
3299
3300RT_C_DECLS_BEGIN
3301
3302int pgmLock(PVM pVM);
3303void pgmUnlock(PVM pVM);
3304
3305int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3306int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3307int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3308PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3309int pgmMapResolveConflicts(PVM pVM);
3310DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3311
3312void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3313bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3314void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3315int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3316DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3317#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3318void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3319#else
3320# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3321#endif
3322DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3323int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3324
3325int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3326int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3327int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3328int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3329void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3330int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3331int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3332int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3333int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3334int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3335int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3336int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3337int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3338VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3339#ifdef IN_RING3
3340void pgmR3PhysRelinkRamRanges(PVM pVM);
3341int pgmR3PhysRamPreAllocate(PVM pVM);
3342int pgmR3PhysRamReset(PVM pVM);
3343int pgmR3PhysRomReset(PVM pVM);
3344int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3345
3346int pgmR3PoolInit(PVM pVM);
3347void pgmR3PoolRelocate(PVM pVM);
3348void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3349void pgmR3PoolReset(PVM pVM);
3350void pgmR3PoolClearAll(PVM pVM);
3351DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser);
3352
3353#endif /* IN_RING3 */
3354#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3355int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3356#endif
3357int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3358
3359DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3360{
3361 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3362}
3363
3364void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3365void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3366int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3367void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3368PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3369int pgmPoolSyncCR3(PVMCPU pVCpu);
3370bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3371int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3372void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3373DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3374{
3375 return pgmPoolTrackUpdateGCPhys(pVM, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3376}
3377
3378uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3379void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3380void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3381void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3382int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3383void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3384
3385void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3386void pgmPoolResetDirtyPages(PVM pVM);
3387
3388int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3389int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3390
3391void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3392void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3393int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3394int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3395
3396int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3397#ifndef IN_RC
3398int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3399#endif
3400int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3401
3402PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3403PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3404PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3405PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3406
3407RT_C_DECLS_END
3408
3409/** @} */
3410
3411#endif
3412
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