VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 28112

Last change on this file since 28112 was 27584, checked in by vboxsync, 15 years ago

Statistic counter for ballooned page accesses
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1/* $Id: PGMInternal.h 27584 2010-03-22 12:22:38Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43#include <iprt/sha.h>
44
45
46
47/** @defgroup grp_pgm_int Internals
48 * @ingroup grp_pgm
49 * @internal
50 * @{
51 */
52
53
54/** @name PGM Compile Time Config
55 * @{
56 */
57
58/**
59 * Indicates that there are no guest mappings to care about.
60 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
61 */
62#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
63# define PGM_WITHOUT_MAPPINGS
64#endif
65
66/**
67 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
68 * Comment it if it will break something.
69 */
70#define PGM_OUT_OF_SYNC_IN_GC
71
72/**
73 * Check and skip global PDEs for non-global flushes
74 */
75#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
76
77/**
78 * Optimization for PAE page tables that are modified often
79 */
80//#if 0 /* disabled again while debugging */
81#ifndef IN_RC
82# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
83#endif
84//#endif
85
86/**
87 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
88 */
89#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
90# define PGM_WITH_LARGE_PAGES
91#endif
92
93/**
94 * Sync N pages instead of a whole page table
95 */
96#define PGM_SYNC_N_PAGES
97
98/**
99 * Number of pages to sync during a page fault
100 *
101 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103 *
104 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105 * world switch overhead, so let's sync more.
106 */
107# ifdef IN_RING0
108/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
109 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110 * but ~5% fewer faults.
111 */
112# define PGM_SYNC_NR_PAGES 32
113#else
114# define PGM_SYNC_NR_PAGES 8
115#endif
116
117/**
118 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119 */
120#define PGM_MAX_PHYSCACHE_ENTRIES 64
121#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124/** @def PGMPOOL_CFG_MAX_GROW
125 * The maximum number of pages to add to the pool in one go.
126 */
127#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
128
129/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
131 */
132#ifdef VBOX_STRICT
133# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134#endif
135
136/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137 * Enables the experimental lazy page allocation code. */
138/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
139
140/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
141 * Enables real write monitoring of pages, i.e. mapping them read-only and
142 * only making them writable when getting a write access #PF. */
143#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
144
145/** @} */
146
147
148/** @name PDPT and PML4 flags.
149 * These are placed in the three bits available for system programs in
150 * the PDPT and PML4 entries.
151 * @{ */
152/** The entry is a permanent one and it's must always be present.
153 * Never free such an entry. */
154#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
155/** Mapping (hypervisor allocated pagetable). */
156#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
157/** @} */
158
159/** @name Page directory flags.
160 * These are placed in the three bits available for system programs in
161 * the page directory entries.
162 * @{ */
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
165/** Made read-only to facilitate dirty bit tracking. */
166#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
167/** @} */
168
169/** @name Page flags.
170 * These are placed in the three bits available for system programs in
171 * the page entries.
172 * @{ */
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
175
176#ifndef PGM_PTFLAGS_CSAM_VALIDATED
177/** Scanned and approved by CSAM (tm).
178 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
179 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
180#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
181#endif
182
183/** @} */
184
185/** @name Defines used to indicate the shadow and guest paging in the templates.
186 * @{ */
187#define PGM_TYPE_REAL 1
188#define PGM_TYPE_PROT 2
189#define PGM_TYPE_32BIT 3
190#define PGM_TYPE_PAE 4
191#define PGM_TYPE_AMD64 5
192#define PGM_TYPE_NESTED 6
193#define PGM_TYPE_EPT 7
194#define PGM_TYPE_MAX PGM_TYPE_EPT
195/** @} */
196
197/** Macro for checking if the guest is using paging.
198 * @param uGstType PGM_TYPE_*
199 * @param uShwType PGM_TYPE_*
200 * @remark ASSUMES certain order of the PGM_TYPE_* values.
201 */
202#define PGM_WITH_PAGING(uGstType, uShwType) \
203 ( (uGstType) >= PGM_TYPE_32BIT \
204 && (uShwType) != PGM_TYPE_NESTED \
205 && (uShwType) != PGM_TYPE_EPT)
206
207/** Macro for checking if the guest supports the NX bit.
208 * @param uGstType PGM_TYPE_*
209 * @param uShwType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_NX(uGstType, uShwType) \
213 ( (uGstType) >= PGM_TYPE_PAE \
214 && (uShwType) != PGM_TYPE_NESTED \
215 && (uShwType) != PGM_TYPE_EPT)
216
217
218/** @def PGM_HCPHYS_2_PTR
219 * Maps a HC physical page pool address to a virtual address.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM handle.
223 * @param HCPhys The HC physical address to map to a virtual one.
224 * @param ppv Where to store the virtual address. No need to cast this.
225 *
226 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
227 * small page window employeed by that function. Be careful.
228 * @remark There is no need to assert on the result.
229 */
230#ifdef IN_RC
231# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
232 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
233#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
236#else
237# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
239#endif
240
241/** @def PGM_HCPHYS_2_PTR_BY_PGM
242 * Maps a HC physical page pool address to a virtual address.
243 *
244 * @returns VBox status code.
245 * @param pPGM The PGM instance data.
246 * @param HCPhys The HC physical address to map to a virtual one.
247 * @param ppv Where to store the virtual address. No need to cast this.
248 *
249 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
250 * small page window employeed by that function. Be careful.
251 * @remark There is no need to assert on the result.
252 */
253#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
254# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_GCPHYS_2_PTR
262 * Maps a GC physical page address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pVM The VM handle.
266 * @param GCPhys The GC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef IN_RC
274# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
275 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
276#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
277# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
279#else
280# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
282#endif
283
284/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
285 * Maps a GC physical page address to a virtual address.
286 *
287 * @returns VBox status code.
288 * @param pPGM Pointer to the PGM instance data.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
293 * small page window employeed by that function. Be careful.
294 * @remark There is no need to assert on the result.
295 */
296#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
297# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
301 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_EX
305 * Maps a unaligned GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pVM The VM handle.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
317# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
318 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
322#endif
323
324/** @def PGM_INVL_PG
325 * Invalidates a page.
326 *
327 * @param pVCpu The VMCPU handle.
328 * @param GCVirt The virtual address of the page to invalidate.
329 */
330#ifdef IN_RC
331# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
332#elif defined(IN_RING0)
333# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
334#else
335# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
336#endif
337
338/** @def PGM_INVL_PG_ALL_VCPU
339 * Invalidates a page on all VCPUs
340 *
341 * @param pVM The VM handle.
342 * @param GCVirt The virtual address of the page to invalidate.
343 */
344#ifdef IN_RC
345# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
346#elif defined(IN_RING0)
347# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
348#else
349# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
350#endif
351
352/** @def PGM_INVL_BIG_PG
353 * Invalidates a 4MB page directory entry.
354 *
355 * @param pVCpu The VMCPU handle.
356 * @param GCVirt The virtual address within the page directory to invalidate.
357 */
358#ifdef IN_RC
359# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
360#elif defined(IN_RING0)
361# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
362#else
363# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
364#endif
365
366/** @def PGM_INVL_VCPU_TLBS()
367 * Invalidates the TLBs of the specified VCPU
368 *
369 * @param pVCpu The VMCPU handle.
370 */
371#ifdef IN_RC
372# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
373#elif defined(IN_RING0)
374# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
375#else
376# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
377#endif
378
379/** @def PGM_INVL_ALL_VCPU_TLBS()
380 * Invalidates the TLBs of all VCPUs
381 *
382 * @param pVM The VM handle.
383 */
384#ifdef IN_RC
385# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
386#elif defined(IN_RING0)
387# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
388#else
389# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
390#endif
391
392/** Size of the GCPtrConflict array in PGMMAPPING.
393 * @remarks Must be a power of two. */
394#define PGMMAPPING_CONFLICT_MAX 8
395
396/**
397 * Structure for tracking GC Mappings.
398 *
399 * This structure is used by linked list in both GC and HC.
400 */
401typedef struct PGMMAPPING
402{
403 /** Pointer to next entry. */
404 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
405 /** Pointer to next entry. */
406 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
407 /** Pointer to next entry. */
408 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
409 /** Indicate whether this entry is finalized. */
410 bool fFinalized;
411 /** Start Virtual address. */
412 RTGCPTR GCPtr;
413 /** Last Virtual address (inclusive). */
414 RTGCPTR GCPtrLast;
415 /** Range size (bytes). */
416 RTGCPTR cb;
417 /** Pointer to relocation callback function. */
418 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
419 /** User argument to the callback. */
420 R3PTRTYPE(void *) pvUser;
421 /** Mapping description / name. For easing debugging. */
422 R3PTRTYPE(const char *) pszDesc;
423 /** Last 8 addresses that caused conflicts. */
424 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
425 /** Number of conflicts for this hypervisor mapping. */
426 uint32_t cConflicts;
427 /** Number of page tables. */
428 uint32_t cPTs;
429
430 /** Array of page table mapping data. Each entry
431 * describes one page table. The array can be longer
432 * than the declared length.
433 */
434 struct
435 {
436 /** The HC physical address of the page table. */
437 RTHCPHYS HCPhysPT;
438 /** The HC physical address of the first PAE page table. */
439 RTHCPHYS HCPhysPaePT0;
440 /** The HC physical address of the second PAE page table. */
441 RTHCPHYS HCPhysPaePT1;
442 /** The HC virtual address of the 32-bit page table. */
443 R3PTRTYPE(PX86PT) pPTR3;
444 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
445 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
446 /** The RC virtual address of the 32-bit page table. */
447 RCPTRTYPE(PX86PT) pPTRC;
448 /** The RC virtual address of the two PAE page table. */
449 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
450 /** The R0 virtual address of the 32-bit page table. */
451 R0PTRTYPE(PX86PT) pPTR0;
452 /** The R0 virtual address of the two PAE page table. */
453 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
454 } aPTs[1];
455} PGMMAPPING;
456/** Pointer to structure for tracking GC Mappings. */
457typedef struct PGMMAPPING *PPGMMAPPING;
458
459
460/**
461 * Physical page access handler structure.
462 *
463 * This is used to keep track of physical address ranges
464 * which are being monitored in some kind of way.
465 */
466typedef struct PGMPHYSHANDLER
467{
468 AVLROGCPHYSNODECORE Core;
469 /** Access type. */
470 PGMPHYSHANDLERTYPE enmType;
471 /** Number of pages to update. */
472 uint32_t cPages;
473 /** Pointer to R3 callback function. */
474 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
475 /** User argument for R3 handlers. */
476 R3PTRTYPE(void *) pvUserR3;
477 /** Pointer to R0 callback function. */
478 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
479 /** User argument for R0 handlers. */
480 R0PTRTYPE(void *) pvUserR0;
481 /** Pointer to RC callback function. */
482 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
483 /** User argument for RC handlers. */
484 RCPTRTYPE(void *) pvUserRC;
485 /** Description / Name. For easing debugging. */
486 R3PTRTYPE(const char *) pszDesc;
487#ifdef VBOX_WITH_STATISTICS
488 /** Profiling of this handler. */
489 STAMPROFILE Stat;
490#endif
491} PGMPHYSHANDLER;
492/** Pointer to a physical page access handler structure. */
493typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
494
495
496/**
497 * Cache node for the physical addresses covered by a virtual handler.
498 */
499typedef struct PGMPHYS2VIRTHANDLER
500{
501 /** Core node for the tree based on physical ranges. */
502 AVLROGCPHYSNODECORE Core;
503 /** Offset from this struct to the PGMVIRTHANDLER structure. */
504 int32_t offVirtHandler;
505 /** Offset of the next alias relative to this one.
506 * Bit 0 is used for indicating whether we're in the tree.
507 * Bit 1 is used for indicating that we're the head node.
508 */
509 int32_t offNextAlias;
510} PGMPHYS2VIRTHANDLER;
511/** Pointer to a phys to virtual handler structure. */
512typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
513
514/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
515 * node is in the tree. */
516#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
517/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
518 * node is in the head of an alias chain.
519 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
520#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
521/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
522#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
523
524
525/**
526 * Virtual page access handler structure.
527 *
528 * This is used to keep track of virtual address ranges
529 * which are being monitored in some kind of way.
530 */
531typedef struct PGMVIRTHANDLER
532{
533 /** Core node for the tree based on virtual ranges. */
534 AVLROGCPTRNODECORE Core;
535 /** Size of the range (in bytes). */
536 RTGCPTR cb;
537 /** Number of cache pages. */
538 uint32_t cPages;
539 /** Access type. */
540 PGMVIRTHANDLERTYPE enmType;
541 /** Pointer to the RC callback function. */
542 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
543#if HC_ARCH_BITS == 64
544 RTRCPTR padding;
545#endif
546 /** Pointer to the R3 callback function for invalidation. */
547 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
548 /** Pointer to the R3 callback function. */
549 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
550 /** Description / Name. For easing debugging. */
551 R3PTRTYPE(const char *) pszDesc;
552#ifdef VBOX_WITH_STATISTICS
553 /** Profiling of this handler. */
554 STAMPROFILE Stat;
555#endif
556 /** Array of cached physical addresses for the monitored ranged. */
557 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
558} PGMVIRTHANDLER;
559/** Pointer to a virtual page access handler structure. */
560typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
561
562
563/**
564 * Page type.
565 *
566 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
567 * @remarks This is used in the saved state, so changes to it requires bumping
568 * the saved state version.
569 * @todo So, convert to \#defines!
570 */
571typedef enum PGMPAGETYPE
572{
573 /** The usual invalid zero entry. */
574 PGMPAGETYPE_INVALID = 0,
575 /** RAM page. (RWX) */
576 PGMPAGETYPE_RAM,
577 /** MMIO2 page. (RWX) */
578 PGMPAGETYPE_MMIO2,
579 /** MMIO2 page aliased over an MMIO page. (RWX)
580 * See PGMHandlerPhysicalPageAlias(). */
581 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
582 /** Shadowed ROM. (RWX) */
583 PGMPAGETYPE_ROM_SHADOW,
584 /** ROM page. (R-X) */
585 PGMPAGETYPE_ROM,
586 /** MMIO page. (---) */
587 PGMPAGETYPE_MMIO,
588 /** End of valid entries. */
589 PGMPAGETYPE_END
590} PGMPAGETYPE;
591AssertCompile(PGMPAGETYPE_END <= 7);
592
593/** @name Page type predicates.
594 * @{ */
595#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
596#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
597#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
598#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
599#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
600/** @} */
601
602
603/**
604 * A Physical Guest Page tracking structure.
605 *
606 * The format of this structure is complicated because we have to fit a lot
607 * of information into as few bits as possible. The format is also subject
608 * to change (there is one comming up soon). Which means that for we'll be
609 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
610 * accesses to the structure.
611 */
612typedef struct PGMPAGE
613{
614 /** The physical address and the Page ID. */
615 RTHCPHYS HCPhysAndPageID;
616 /** Combination of:
617 * - [0-7]: u2HandlerPhysStateY - the physical handler state
618 * (PGM_PAGE_HNDL_PHYS_STATE_*).
619 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
620 * (PGM_PAGE_HNDL_VIRT_STATE_*).
621 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
622 * - [15]: fWrittenToY - flag indicating that a write monitored page was
623 * written to when set.
624 * - [10-13]: 4 unused bits.
625 * @remarks Warning! All accesses to the bits are hardcoded.
626 *
627 * @todo Change this to a union with both bitfields, u8 and u accessors.
628 * That'll help deal with some of the hardcoded accesses.
629 *
630 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
631 * will make it possible to turn some of the 16-bit accesses into
632 * 32-bit ones, which may be efficient (stalls).
633 */
634 RTUINT16U u16MiscY;
635 /** The page state.
636 * Only 3 bits are really needed for this. */
637 uint8_t uStateY;
638 /** The page type (PGMPAGETYPE).
639 * Only 3 bits are really needed for this. */
640 uint8_t uTypeY;
641 /** Usage tracking (page pool). */
642 uint16_t u16TrackingY;
643 /** The number of read locks on this page. */
644 uint8_t cReadLocksY;
645 /** The number of write locks on this page. */
646 uint8_t cWriteLocksY;
647} PGMPAGE;
648AssertCompileSize(PGMPAGE, 16);
649/** Pointer to a physical guest page. */
650typedef PGMPAGE *PPGMPAGE;
651/** Pointer to a const physical guest page. */
652typedef const PGMPAGE *PCPGMPAGE;
653/** Pointer to a physical guest page pointer. */
654typedef PPGMPAGE *PPPGMPAGE;
655
656
657/**
658 * Clears the page structure.
659 * @param pPage Pointer to the physical guest page tracking structure.
660 */
661#define PGM_PAGE_CLEAR(pPage) \
662 do { \
663 (pPage)->HCPhysAndPageID = 0; \
664 (pPage)->uStateY = 0; \
665 (pPage)->uTypeY = 0; \
666 (pPage)->u16MiscY.u = 0; \
667 (pPage)->u16TrackingY = 0; \
668 (pPage)->cReadLocksY = 0; \
669 (pPage)->cWriteLocksY = 0; \
670 } while (0)
671
672/**
673 * Initializes the page structure.
674 * @param pPage Pointer to the physical guest page tracking structure.
675 */
676#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
677 do { \
678 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
679 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
680 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
681 (pPage)->uStateY = (_uState); \
682 (pPage)->uTypeY = (_uType); \
683 (pPage)->u16MiscY.u = 0; \
684 (pPage)->u16TrackingY = 0; \
685 (pPage)->cReadLocksY = 0; \
686 (pPage)->cWriteLocksY = 0; \
687 } while (0)
688
689/**
690 * Initializes the page structure of a ZERO page.
691 * @param pPage Pointer to the physical guest page tracking structure.
692 * @param pVM The VM handle (for getting the zero page address).
693 * @param uType The page type (PGMPAGETYPE).
694 */
695#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
696 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
697
698
699/** @name The Page state, PGMPAGE::uStateY.
700 * @{ */
701/** The zero page.
702 * This is a per-VM page that's never ever mapped writable. */
703#define PGM_PAGE_STATE_ZERO 0
704/** A allocated page.
705 * This is a per-VM page allocated from the page pool (or wherever
706 * we get MMIO2 pages from if the type is MMIO2).
707 */
708#define PGM_PAGE_STATE_ALLOCATED 1
709/** A allocated page that's being monitored for writes.
710 * The shadow page table mappings are read-only. When a write occurs, the
711 * fWrittenTo member is set, the page remapped as read-write and the state
712 * moved back to allocated. */
713#define PGM_PAGE_STATE_WRITE_MONITORED 2
714/** The page is shared, aka. copy-on-write.
715 * This is a page that's shared with other VMs. */
716#define PGM_PAGE_STATE_SHARED 3
717/** The page is ballooned, so no longer available for this VM. */
718#define PGM_PAGE_STATE_BALLOONED 4
719/** @} */
720
721
722/**
723 * Gets the page state.
724 * @returns page state (PGM_PAGE_STATE_*).
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
728
729/**
730 * Sets the page state.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 * @param _uState The new page state.
733 */
734#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
735
736
737/**
738 * Gets the host physical address of the guest page.
739 * @returns host physical address (RTHCPHYS).
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
743
744/**
745 * Sets the host physical address of the guest page.
746 * @param pPage Pointer to the physical guest page tracking structure.
747 * @param _HCPhys The new host physical address.
748 */
749#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
750 do { \
751 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
752 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
753 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
754 | (SetHCPhysTmp << (28-12)); \
755 } while (0)
756
757/**
758 * Get the Page ID.
759 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
760 * @param pPage Pointer to the physical guest page tracking structure.
761 */
762#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
763
764/**
765 * Sets the Page ID.
766 * @param pPage Pointer to the physical guest page tracking structure.
767 */
768#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
769 do { \
770 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
771 | ((_idPage) & UINT32_C(0x0fffffff)); \
772 } while (0)
773
774/**
775 * Get the Chunk ID.
776 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
777 * @param pPage Pointer to the physical guest page tracking structure.
778 */
779#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
780
781/**
782 * Get the index of the page within the allocation chunk.
783 * @returns The page index.
784 * @param pPage Pointer to the physical guest page tracking structure.
785 */
786#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
787
788/**
789 * Gets the page type.
790 * @returns The page type.
791 * @param pPage Pointer to the physical guest page tracking structure.
792 */
793#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
794
795/**
796 * Sets the page type.
797 * @param pPage Pointer to the physical guest page tracking structure.
798 * @param _enmType The new page type (PGMPAGETYPE).
799 */
800#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
801
802/**
803 * Checks if the page is marked for MMIO.
804 * @returns true/false.
805 * @param pPage Pointer to the physical guest page tracking structure.
806 */
807#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
808
809/**
810 * Checks if the page is backed by the ZERO page.
811 * @returns true/false.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 */
814#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
815
816/**
817 * Checks if the page is backed by a SHARED page.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
822
823/**
824 * Checks if the page is ballooned.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
829
830/**
831 * Marks the page as written to (for GMM change monitoring).
832 * @param pPage Pointer to the physical guest page tracking structure.
833 */
834#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
835
836/**
837 * Clears the written-to indicator.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
841
842/**
843 * Checks if the page was marked as written-to.
844 * @returns true/false.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
848
849/** @name PT usage values (PGMPAGE::u2PDEType).
850 *
851 * @{ */
852/** Either as a PT or PDE. */
853#define PGM_PAGE_PDE_TYPE_DONTCARE 0
854/** Must use a page table to map the range. */
855#define PGM_PAGE_PDE_TYPE_PT 1
856/** Can use a page directory entry to map the continous range. */
857#define PGM_PAGE_PDE_TYPE_PDE 2
858/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
859#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
860/** @} */
861
862/**
863 * Set the PDE type of the page
864 * @param pPage Pointer to the physical guest page tracking structure.
865 * @param uType PGM_PAGE_PDE_TYPE_*
866 */
867#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
868 do { \
869 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
870 | (((uType) & UINT8_C(0x03)) << 5); \
871 } while (0)
872
873/**
874 * Checks if the page was marked being part of a large page
875 * @returns true/false.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
879
880/** Enabled optimized access handler tests.
881 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
882 * layout. When enabled, the compiler should normally generate more compact
883 * code.
884 */
885#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
886
887/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
888 *
889 * @remarks The values are assigned in order of priority, so we can calculate
890 * the correct state for a page with different handlers installed.
891 * @{ */
892/** No handler installed. */
893#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
894/** Monitoring is temporarily disabled. */
895#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
896/** Write access is monitored. */
897#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
898/** All access is monitored. */
899#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
900/** @} */
901
902/**
903 * Gets the physical access handler state of a page.
904 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
905 * @param pPage Pointer to the physical guest page tracking structure.
906 */
907#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
908 ( (pPage)->u16MiscY.au8[0] )
909
910/**
911 * Sets the physical access handler state of a page.
912 * @param pPage Pointer to the physical guest page tracking structure.
913 * @param _uState The new state value.
914 */
915#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
916 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
917
918/**
919 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
920 * @returns true/false
921 * @param pPage Pointer to the physical guest page tracking structure.
922 */
923#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
924 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
925
926/**
927 * Checks if the page has any active physical access handlers.
928 * @returns true/false
929 * @param pPage Pointer to the physical guest page tracking structure.
930 */
931#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
932 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
933
934
935/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
936 *
937 * @remarks The values are assigned in order of priority, so we can calculate
938 * the correct state for a page with different handlers installed.
939 * @{ */
940/** No handler installed. */
941#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
942/* 1 is reserved so the lineup is identical with the physical ones. */
943/** Write access is monitored. */
944#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
945/** All access is monitored. */
946#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
947/** @} */
948
949/**
950 * Gets the virtual access handler state of a page.
951 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
955
956/**
957 * Sets the virtual access handler state of a page.
958 * @param pPage Pointer to the physical guest page tracking structure.
959 * @param _uState The new state value.
960 */
961#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
962 do { \
963 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
964 | ((_uState) & UINT8_C(0x03)); \
965 } while (0)
966
967/**
968 * Checks if the page has any virtual access handlers.
969 * @returns true/false
970 * @param pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
973 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
974
975/**
976 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
977 * virtual handlers.
978 * @returns true/false
979 * @param pPage Pointer to the physical guest page tracking structure.
980 */
981#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
982 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
983
984
985/**
986 * Checks if the page has any access handlers, including temporarily disabled ones.
987 * @returns true/false
988 * @param pPage Pointer to the physical guest page tracking structure.
989 */
990#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
991# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
992 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
993#else
994# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
995 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
996 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
997#endif
998
999/**
1000 * Checks if the page has any active access handlers.
1001 * @returns true/false
1002 * @param pPage Pointer to the physical guest page tracking structure.
1003 */
1004#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1005# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1006 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1007#else
1008# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1009 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1010 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1011#endif
1012
1013/**
1014 * Checks if the page has any active access handlers catching all accesses.
1015 * @returns true/false
1016 * @param pPage Pointer to the physical guest page tracking structure.
1017 */
1018#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1019# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1020 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1021 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1022#else
1023# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1024 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1025 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1026#endif
1027
1028
1029/** @def PGM_PAGE_GET_TRACKING
1030 * Gets the packed shadow page pool tracking data associated with a guest page.
1031 * @returns uint16_t containing the data.
1032 * @param pPage Pointer to the physical guest page tracking structure.
1033 */
1034#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1035
1036/** @def PGM_PAGE_SET_TRACKING
1037 * Sets the packed shadow page pool tracking data associated with a guest page.
1038 * @param pPage Pointer to the physical guest page tracking structure.
1039 * @param u16TrackingData The tracking data to store.
1040 */
1041#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1042 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1043
1044/** @def PGM_PAGE_GET_TD_CREFS
1045 * Gets the @a cRefs tracking data member.
1046 * @returns cRefs.
1047 * @param pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_GET_TD_CREFS(pPage) \
1050 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1051
1052/** @def PGM_PAGE_GET_TD_IDX
1053 * Gets the @a idx tracking data member.
1054 * @returns idx.
1055 * @param pPage Pointer to the physical guest page tracking structure.
1056 */
1057#define PGM_PAGE_GET_TD_IDX(pPage) \
1058 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1059
1060
1061/** Max number of locks on a page. */
1062#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1063
1064/** Get the read lock count.
1065 * @returns count.
1066 * @param pPage Pointer to the physical guest page tracking structure.
1067 */
1068#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1069
1070/** Get the write lock count.
1071 * @returns count.
1072 * @param pPage Pointer to the physical guest page tracking structure.
1073 */
1074#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1075
1076/** Decrement the read lock counter.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1080
1081/** Decrement the write lock counter.
1082 * @param pPage Pointer to the physical guest page tracking structure.
1083 */
1084#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1085
1086/** Increment the read lock counter.
1087 * @param pPage Pointer to the physical guest page tracking structure.
1088 */
1089#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1090
1091/** Increment the write lock counter.
1092 * @param pPage Pointer to the physical guest page tracking structure.
1093 */
1094#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1095
1096
1097#if 0
1098/** Enables sanity checking of write monitoring using CRC-32. */
1099# define PGMLIVESAVERAMPAGE_WITH_CRC32
1100#endif
1101
1102/**
1103 * Per page live save tracking data.
1104 */
1105typedef struct PGMLIVESAVERAMPAGE
1106{
1107 /** Number of times it has been dirtied. */
1108 uint32_t cDirtied : 24;
1109 /** Whether it is currently dirty. */
1110 uint32_t fDirty : 1;
1111 /** Ignore the page.
1112 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1113 * deal with these after pausing the VM and DevPCI have said it bit about
1114 * remappings. */
1115 uint32_t fIgnore : 1;
1116 /** Was a ZERO page last time around. */
1117 uint32_t fZero : 1;
1118 /** Was a SHARED page last time around. */
1119 uint32_t fShared : 1;
1120 /** Whether the page is/was write monitored in a previous pass. */
1121 uint32_t fWriteMonitored : 1;
1122 /** Whether the page is/was write monitored earlier in this pass. */
1123 uint32_t fWriteMonitoredJustNow : 1;
1124 /** Bits reserved for future use. */
1125 uint32_t u2Reserved : 2;
1126#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1127 /** CRC-32 for the page. This is for internal consistency checks. */
1128 uint32_t u32Crc;
1129#endif
1130} PGMLIVESAVERAMPAGE;
1131#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1132AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1133#else
1134AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1135#endif
1136/** Pointer to the per page live save tracking data. */
1137typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1138
1139/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1140#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1141
1142
1143/**
1144 * Ram range for GC Phys to HC Phys conversion.
1145 *
1146 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1147 * conversions too, but we'll let MM handle that for now.
1148 *
1149 * This structure is used by linked lists in both GC and HC.
1150 */
1151typedef struct PGMRAMRANGE
1152{
1153 /** Start of the range. Page aligned. */
1154 RTGCPHYS GCPhys;
1155 /** Size of the range. (Page aligned of course). */
1156 RTGCPHYS cb;
1157 /** Pointer to the next RAM range - for R3. */
1158 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1159 /** Pointer to the next RAM range - for R0. */
1160 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1161 /** Pointer to the next RAM range - for RC. */
1162 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1163 /** PGM_RAM_RANGE_FLAGS_* flags. */
1164 uint32_t fFlags;
1165 /** Last address in the range (inclusive). Page aligned (-1). */
1166 RTGCPHYS GCPhysLast;
1167 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1168 R3PTRTYPE(void *) pvR3;
1169 /** Live save per page tracking data. */
1170 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1171 /** The range description. */
1172 R3PTRTYPE(const char *) pszDesc;
1173 /** Pointer to self - R0 pointer. */
1174 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1175 /** Pointer to self - RC pointer. */
1176 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1177 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1178 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1179 /** Array of physical guest page tracking structures. */
1180 PGMPAGE aPages[1];
1181} PGMRAMRANGE;
1182/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1183typedef PGMRAMRANGE *PPGMRAMRANGE;
1184
1185/** @name PGMRAMRANGE::fFlags
1186 * @{ */
1187/** The RAM range is floating around as an independent guest mapping. */
1188#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1189/** Ad hoc RAM range for an ROM mapping. */
1190#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1191/** Ad hoc RAM range for an MMIO mapping. */
1192#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1193/** Ad hoc RAM range for an MMIO2 mapping. */
1194#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1195/** @} */
1196
1197/** Tests if a RAM range is an ad hoc one or not.
1198 * @returns true/false.
1199 * @param pRam The RAM range.
1200 */
1201#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1202 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1203
1204
1205/**
1206 * Per page tracking structure for ROM image.
1207 *
1208 * A ROM image may have a shadow page, in which case we may have two pages
1209 * backing it. This structure contains the PGMPAGE for both while
1210 * PGMRAMRANGE have a copy of the active one. It is important that these
1211 * aren't out of sync in any regard other than page pool tracking data.
1212 */
1213typedef struct PGMROMPAGE
1214{
1215 /** The page structure for the virgin ROM page. */
1216 PGMPAGE Virgin;
1217 /** The page structure for the shadow RAM page. */
1218 PGMPAGE Shadow;
1219 /** The current protection setting. */
1220 PGMROMPROT enmProt;
1221 /** Live save status information. Makes use of unused alignment space. */
1222 struct
1223 {
1224 /** The previous protection value. */
1225 uint8_t u8Prot;
1226 /** Written to flag set by the handler. */
1227 bool fWrittenTo;
1228 /** Whether the shadow page is dirty or not. */
1229 bool fDirty;
1230 /** Whether it was dirtied in the recently. */
1231 bool fDirtiedRecently;
1232 } LiveSave;
1233} PGMROMPAGE;
1234AssertCompileSizeAlignment(PGMROMPAGE, 8);
1235/** Pointer to a ROM page tracking structure. */
1236typedef PGMROMPAGE *PPGMROMPAGE;
1237
1238
1239/**
1240 * A registered ROM image.
1241 *
1242 * This is needed to keep track of ROM image since they generally intrude
1243 * into a PGMRAMRANGE. It also keeps track of additional info like the
1244 * two page sets (read-only virgin and read-write shadow), the current
1245 * state of each page.
1246 *
1247 * Because access handlers cannot easily be executed in a different
1248 * context, the ROM ranges needs to be accessible and in all contexts.
1249 */
1250typedef struct PGMROMRANGE
1251{
1252 /** Pointer to the next range - R3. */
1253 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1254 /** Pointer to the next range - R0. */
1255 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1256 /** Pointer to the next range - RC. */
1257 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1258 /** Pointer alignment */
1259 RTRCPTR RCPtrAlignment;
1260 /** Address of the range. */
1261 RTGCPHYS GCPhys;
1262 /** Address of the last byte in the range. */
1263 RTGCPHYS GCPhysLast;
1264 /** Size of the range. */
1265 RTGCPHYS cb;
1266 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1267 uint32_t fFlags;
1268 /** The saved state range ID. */
1269 uint8_t idSavedState;
1270 /** Alignment padding. */
1271 uint8_t au8Alignment[3];
1272 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1273 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1274 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1275 * This is used for strictness checks. */
1276 R3PTRTYPE(const void *) pvOriginal;
1277 /** The ROM description. */
1278 R3PTRTYPE(const char *) pszDesc;
1279 /** The per page tracking structures. */
1280 PGMROMPAGE aPages[1];
1281} PGMROMRANGE;
1282/** Pointer to a ROM range. */
1283typedef PGMROMRANGE *PPGMROMRANGE;
1284
1285
1286/**
1287 * Live save per page data for an MMIO2 page.
1288 *
1289 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1290 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1291 * CRC-32 for detecting changes as well as special handling of zero pages. This
1292 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1293 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1294 * because of speed (2.5x and 6x slower).)
1295 *
1296 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1297 * save but normally is disabled. Since we can write monitore guest
1298 * accesses on our own, we only need this for host accesses. Shouldn't be
1299 * too difficult for DevVGA, VMMDev might be doable, the planned
1300 * networking fun will be fun since it involves ring-0.
1301 */
1302typedef struct PGMLIVESAVEMMIO2PAGE
1303{
1304 /** Set if the page is considered dirty. */
1305 bool fDirty;
1306 /** The number of scans this page has remained unchanged for.
1307 * Only updated for dirty pages. */
1308 uint8_t cUnchangedScans;
1309 /** Whether this page was zero at the last scan. */
1310 bool fZero;
1311 /** Alignment padding. */
1312 bool fReserved;
1313 /** CRC-32 for the first half of the page.
1314 * This is used together with u32CrcH2 to quickly detect changes in the page
1315 * during the non-final passes. */
1316 uint32_t u32CrcH1;
1317 /** CRC-32 for the second half of the page. */
1318 uint32_t u32CrcH2;
1319 /** SHA-1 for the saved page.
1320 * This is used in the final pass to skip pages without changes. */
1321 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1322} PGMLIVESAVEMMIO2PAGE;
1323/** Pointer to a live save status data for an MMIO2 page. */
1324typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1325
1326/**
1327 * A registered MMIO2 (= Device RAM) range.
1328 *
1329 * There are a few reason why we need to keep track of these
1330 * registrations. One of them is the deregistration & cleanup stuff,
1331 * while another is that the PGMRAMRANGE associated with such a region may
1332 * have to be removed from the ram range list.
1333 *
1334 * Overlapping with a RAM range has to be 100% or none at all. The pages
1335 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1336 * will be raised if a partial overlap or an overlap of ROM pages is
1337 * encountered. On an overlap we will free all the existing RAM pages and
1338 * put in the ram range pages instead.
1339 */
1340typedef struct PGMMMIO2RANGE
1341{
1342 /** The owner of the range. (a device) */
1343 PPDMDEVINSR3 pDevInsR3;
1344 /** Pointer to the ring-3 mapping of the allocation. */
1345 RTR3PTR pvR3;
1346 /** Pointer to the next range - R3. */
1347 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1348 /** Whether it's mapped or not. */
1349 bool fMapped;
1350 /** Whether it's overlapping or not. */
1351 bool fOverlapping;
1352 /** The PCI region number.
1353 * @remarks This ASSUMES that nobody will ever really need to have multiple
1354 * PCI devices with matching MMIO region numbers on a single device. */
1355 uint8_t iRegion;
1356 /** The saved state range ID. */
1357 uint8_t idSavedState;
1358 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1359 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1360 /** Live save per page tracking data. */
1361 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1362 /** The associated RAM range. */
1363 PGMRAMRANGE RamRange;
1364} PGMMMIO2RANGE;
1365/** Pointer to a MMIO2 range. */
1366typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1367
1368
1369
1370
1371/**
1372 * PGMPhysRead/Write cache entry
1373 */
1374typedef struct PGMPHYSCACHEENTRY
1375{
1376 /** R3 pointer to physical page. */
1377 R3PTRTYPE(uint8_t *) pbR3;
1378 /** GC Physical address for cache entry */
1379 RTGCPHYS GCPhys;
1380#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1381 RTGCPHYS u32Padding0; /**< alignment padding. */
1382#endif
1383} PGMPHYSCACHEENTRY;
1384
1385/**
1386 * PGMPhysRead/Write cache to reduce REM memory access overhead
1387 */
1388typedef struct PGMPHYSCACHE
1389{
1390 /** Bitmap of valid cache entries */
1391 uint64_t aEntries;
1392 /** Cache entries */
1393 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1394} PGMPHYSCACHE;
1395
1396
1397/** Pointer to an allocation chunk ring-3 mapping. */
1398typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1399/** Pointer to an allocation chunk ring-3 mapping pointer. */
1400typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1401
1402/**
1403 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1404 *
1405 * The primary tree (Core) uses the chunk id as key.
1406 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1407 */
1408typedef struct PGMCHUNKR3MAP
1409{
1410 /** The key is the chunk id. */
1411 AVLU32NODECORE Core;
1412 /** The key is the ageing sequence number. */
1413 AVLLU32NODECORE AgeCore;
1414 /** The current age thingy. */
1415 uint32_t iAge;
1416 /** The current reference count. */
1417 uint32_t volatile cRefs;
1418 /** The current permanent reference count. */
1419 uint32_t volatile cPermRefs;
1420 /** The mapping address. */
1421 void *pv;
1422} PGMCHUNKR3MAP;
1423
1424/**
1425 * Allocation chunk ring-3 mapping TLB entry.
1426 */
1427typedef struct PGMCHUNKR3MAPTLBE
1428{
1429 /** The chunk id. */
1430 uint32_t volatile idChunk;
1431#if HC_ARCH_BITS == 64
1432 uint32_t u32Padding; /**< alignment padding. */
1433#endif
1434 /** The chunk map. */
1435#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1436 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1437#else
1438 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1439#endif
1440} PGMCHUNKR3MAPTLBE;
1441/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1442typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1443
1444/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1445 * @remark Must be a power of two value. */
1446#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1447
1448/**
1449 * Allocation chunk ring-3 mapping TLB.
1450 *
1451 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1452 * At first glance this might look kinda odd since AVL trees are
1453 * supposed to give the most optimial lookup times of all trees
1454 * due to their balancing. However, take a tree with 1023 nodes
1455 * in it, that's 10 levels, meaning that most searches has to go
1456 * down 9 levels before they find what they want. This isn't fast
1457 * compared to a TLB hit. There is the factor of cache misses,
1458 * and of course the problem with trees and branch prediction.
1459 * This is why we use TLBs in front of most of the trees.
1460 *
1461 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1462 * difficult when we switch to the new inlined AVL trees (from kStuff).
1463 */
1464typedef struct PGMCHUNKR3MAPTLB
1465{
1466 /** The TLB entries. */
1467 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1468} PGMCHUNKR3MAPTLB;
1469
1470/**
1471 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1472 * @returns Chunk TLB index.
1473 * @param idChunk The Chunk ID.
1474 */
1475#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1476
1477
1478/**
1479 * Ring-3 guest page mapping TLB entry.
1480 * @remarks used in ring-0 as well at the moment.
1481 */
1482typedef struct PGMPAGER3MAPTLBE
1483{
1484 /** Address of the page. */
1485 RTGCPHYS volatile GCPhys;
1486 /** The guest page. */
1487#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1488 R3PTRTYPE(PPGMPAGE) volatile pPage;
1489#else
1490 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1491#endif
1492 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1493#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1494 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1495#else
1496 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1497#endif
1498 /** The address */
1499#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1500 R3PTRTYPE(void *) volatile pv;
1501#else
1502 R3R0PTRTYPE(void *) volatile pv;
1503#endif
1504#if HC_ARCH_BITS == 32
1505 uint32_t u32Padding; /**< alignment padding. */
1506#endif
1507} PGMPAGER3MAPTLBE;
1508/** Pointer to an entry in the HC physical TLB. */
1509typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1510
1511
1512/** The number of entries in the ring-3 guest page mapping TLB.
1513 * @remarks The value must be a power of two. */
1514#define PGM_PAGER3MAPTLB_ENTRIES 256
1515
1516/**
1517 * Ring-3 guest page mapping TLB.
1518 * @remarks used in ring-0 as well at the moment.
1519 */
1520typedef struct PGMPAGER3MAPTLB
1521{
1522 /** The TLB entries. */
1523 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1524} PGMPAGER3MAPTLB;
1525/** Pointer to the ring-3 guest page mapping TLB. */
1526typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1527
1528/**
1529 * Calculates the index of the TLB entry for the specified guest page.
1530 * @returns Physical TLB index.
1531 * @param GCPhys The guest physical address.
1532 */
1533#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1534
1535
1536/**
1537 * Mapping cache usage set entry.
1538 *
1539 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1540 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1541 * cache. If it's extended to include ring-3, well, then something will
1542 * have be changed here...
1543 */
1544typedef struct PGMMAPSETENTRY
1545{
1546 /** The mapping cache index. */
1547 uint16_t iPage;
1548 /** The number of references.
1549 * The max is UINT16_MAX - 1. */
1550 uint16_t cRefs;
1551#if HC_ARCH_BITS == 64
1552 uint32_t alignment;
1553#endif
1554 /** Pointer to the page. */
1555 RTR0PTR pvPage;
1556 /** The physical address for this entry. */
1557 RTHCPHYS HCPhys;
1558} PGMMAPSETENTRY;
1559/** Pointer to a mapping cache usage set entry. */
1560typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1561
1562/**
1563 * Mapping cache usage set.
1564 *
1565 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1566 * done during exits / traps. The set is
1567 */
1568typedef struct PGMMAPSET
1569{
1570 /** The number of occupied entries.
1571 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1572 * dynamic mappings. */
1573 uint32_t cEntries;
1574 /** The start of the current subset.
1575 * This is UINT32_MAX if no subset is currently open. */
1576 uint32_t iSubset;
1577 /** The index of the current CPU, only valid if the set is open. */
1578 int32_t iCpu;
1579 uint32_t alignment;
1580 /** The entries. */
1581 PGMMAPSETENTRY aEntries[64];
1582 /** HCPhys -> iEntry fast lookup table.
1583 * Use PGMMAPSET_HASH for hashing.
1584 * The entries may or may not be valid, check against cEntries. */
1585 uint8_t aiHashTable[128];
1586} PGMMAPSET;
1587AssertCompileSizeAlignment(PGMMAPSET, 8);
1588/** Pointer to the mapping cache set. */
1589typedef PGMMAPSET *PPGMMAPSET;
1590
1591/** PGMMAPSET::cEntries value for a closed set. */
1592#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1593
1594/** Hash function for aiHashTable. */
1595#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1596
1597/** The max fill size (strict builds). */
1598#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1599
1600
1601/** @name Context neutrual page mapper TLB.
1602 *
1603 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1604 * code is writting in a kind of context neutrual way. Time will show whether
1605 * this actually makes sense or not...
1606 *
1607 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1608 * context ends up using a global mapping cache on some platforms
1609 * (darwin).
1610 *
1611 * @{ */
1612/** @typedef PPGMPAGEMAPTLB
1613 * The page mapper TLB pointer type for the current context. */
1614/** @typedef PPGMPAGEMAPTLB
1615 * The page mapper TLB entry pointer type for the current context. */
1616/** @typedef PPGMPAGEMAPTLB
1617 * The page mapper TLB entry pointer pointer type for the current context. */
1618/** @def PGM_PAGEMAPTLB_ENTRIES
1619 * The number of TLB entries in the page mapper TLB for the current context. */
1620/** @def PGM_PAGEMAPTLB_IDX
1621 * Calculate the TLB index for a guest physical address.
1622 * @returns The TLB index.
1623 * @param GCPhys The guest physical address. */
1624/** @typedef PPGMPAGEMAP
1625 * Pointer to a page mapper unit for current context. */
1626/** @typedef PPPGMPAGEMAP
1627 * Pointer to a page mapper unit pointer for current context. */
1628#ifdef IN_RC
1629// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1630// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1631// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1632# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1633# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1634 typedef void * PPGMPAGEMAP;
1635 typedef void ** PPPGMPAGEMAP;
1636//#elif IN_RING0
1637// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1638// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1639// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1640//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1641//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1642// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1643// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1644#else
1645 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1646 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1647 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1648# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1649# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1650 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1651 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1652#endif
1653/** @} */
1654
1655
1656/** @name PGM Pool Indexes.
1657 * Aka. the unique shadow page identifier.
1658 * @{ */
1659/** NIL page pool IDX. */
1660#define NIL_PGMPOOL_IDX 0
1661/** The first normal index. */
1662#define PGMPOOL_IDX_FIRST_SPECIAL 1
1663/** Page directory (32-bit root). */
1664#define PGMPOOL_IDX_PD 1
1665/** Page Directory Pointer Table (PAE root). */
1666#define PGMPOOL_IDX_PDPT 2
1667/** AMD64 CR3 level index.*/
1668#define PGMPOOL_IDX_AMD64_CR3 3
1669/** Nested paging root.*/
1670#define PGMPOOL_IDX_NESTED_ROOT 4
1671/** The first normal index. */
1672#define PGMPOOL_IDX_FIRST 5
1673/** The last valid index. (inclusive, 14 bits) */
1674#define PGMPOOL_IDX_LAST 0x3fff
1675/** @} */
1676
1677/** The NIL index for the parent chain. */
1678#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1679#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1680
1681/**
1682 * Node in the chain linking a shadowed page to it's parent (user).
1683 */
1684#pragma pack(1)
1685typedef struct PGMPOOLUSER
1686{
1687 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1688 uint16_t iNext;
1689 /** The user page index. */
1690 uint16_t iUser;
1691 /** Index into the user table. */
1692 uint32_t iUserTable;
1693} PGMPOOLUSER, *PPGMPOOLUSER;
1694typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1695#pragma pack()
1696
1697
1698/** The NIL index for the phys ext chain. */
1699#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1700
1701/**
1702 * Node in the chain of physical cross reference extents.
1703 * @todo Calling this an 'extent' is not quite right, find a better name.
1704 */
1705#pragma pack(1)
1706typedef struct PGMPOOLPHYSEXT
1707{
1708 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1709 uint16_t iNext;
1710 /** The user page index. */
1711 uint16_t aidx[3];
1712} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1713typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1714#pragma pack()
1715
1716
1717/**
1718 * The kind of page that's being shadowed.
1719 */
1720typedef enum PGMPOOLKIND
1721{
1722 /** The virtual invalid 0 entry. */
1723 PGMPOOLKIND_INVALID = 0,
1724 /** The entry is free (=unused). */
1725 PGMPOOLKIND_FREE,
1726
1727 /** Shw: 32-bit page table; Gst: no paging */
1728 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1729 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1730 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1731 /** Shw: 32-bit page table; Gst: 4MB page. */
1732 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1733 /** Shw: PAE page table; Gst: no paging */
1734 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1735 /** Shw: PAE page table; Gst: 32-bit page table. */
1736 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1737 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1738 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1739 /** Shw: PAE page table; Gst: PAE page table. */
1740 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1741 /** Shw: PAE page table; Gst: 2MB page. */
1742 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1743
1744 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1745 PGMPOOLKIND_32BIT_PD,
1746 /** Shw: 32-bit page directory. Gst: no paging. */
1747 PGMPOOLKIND_32BIT_PD_PHYS,
1748 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1749 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1750 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1751 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1752 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1753 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1754 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1755 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1756 /** Shw: PAE page directory; Gst: PAE page directory. */
1757 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1758 /** Shw: PAE page directory; Gst: no paging. */
1759 PGMPOOLKIND_PAE_PD_PHYS,
1760
1761 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1762 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1763 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1764 PGMPOOLKIND_PAE_PDPT,
1765 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1766 PGMPOOLKIND_PAE_PDPT_PHYS,
1767
1768 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1769 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1770 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1771 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1772 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1773 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1774 /** Shw: 64-bit page directory table; Gst: no paging */
1775 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1776
1777 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1778 PGMPOOLKIND_64BIT_PML4,
1779
1780 /** Shw: EPT page directory pointer table; Gst: no paging */
1781 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1782 /** Shw: EPT page directory table; Gst: no paging */
1783 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1784 /** Shw: EPT page table; Gst: no paging */
1785 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1786
1787 /** Shw: Root Nested paging table. */
1788 PGMPOOLKIND_ROOT_NESTED,
1789
1790 /** The last valid entry. */
1791 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1792} PGMPOOLKIND;
1793
1794/**
1795 * The access attributes of the page; only applies to big pages.
1796 */
1797typedef enum
1798{
1799 PGMPOOLACCESS_DONTCARE = 0,
1800 PGMPOOLACCESS_USER_RW,
1801 PGMPOOLACCESS_USER_R,
1802 PGMPOOLACCESS_USER_RW_NX,
1803 PGMPOOLACCESS_USER_R_NX,
1804 PGMPOOLACCESS_SUPERVISOR_RW,
1805 PGMPOOLACCESS_SUPERVISOR_R,
1806 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1807 PGMPOOLACCESS_SUPERVISOR_R_NX
1808} PGMPOOLACCESS;
1809
1810/**
1811 * The tracking data for a page in the pool.
1812 */
1813typedef struct PGMPOOLPAGE
1814{
1815 /** AVL node code with the (R3) physical address of this page. */
1816 AVLOHCPHYSNODECORE Core;
1817 /** Pointer to the R3 mapping of the page. */
1818#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1819 R3PTRTYPE(void *) pvPageR3;
1820#else
1821 R3R0PTRTYPE(void *) pvPageR3;
1822#endif
1823 /** The guest physical address. */
1824#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1825 uint32_t Alignment0;
1826#endif
1827 RTGCPHYS GCPhys;
1828
1829 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1830 RTGCPTR pvLastAccessHandlerRip;
1831 RTGCPTR pvLastAccessHandlerFault;
1832 uint64_t cLastAccessHandlerCount;
1833
1834 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1835 uint8_t enmKind;
1836 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1837 uint8_t enmAccess;
1838 /** The index of this page. */
1839 uint16_t idx;
1840 /** The next entry in the list this page currently resides in.
1841 * It's either in the free list or in the GCPhys hash. */
1842 uint16_t iNext;
1843 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1844 uint16_t iUserHead;
1845 /** The number of present entries. */
1846 uint16_t cPresent;
1847 /** The first entry in the table which is present. */
1848 uint16_t iFirstPresent;
1849 /** The number of modifications to the monitored page. */
1850 uint16_t cModifications;
1851 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1852 uint16_t iModifiedNext;
1853 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1854 uint16_t iModifiedPrev;
1855 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1856 uint16_t iMonitoredNext;
1857 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1858 uint16_t iMonitoredPrev;
1859 /** The next page in the age list. */
1860 uint16_t iAgeNext;
1861 /** The previous page in the age list. */
1862 uint16_t iAgePrev;
1863 /** Used to indicate that the page is zeroed. */
1864 bool fZeroed;
1865 /** Used to indicate that a PT has non-global entries. */
1866 bool fSeenNonGlobal;
1867 /** Used to indicate that we're monitoring writes to the guest page. */
1868 bool fMonitored;
1869 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1870 * (All pages are in the age list.) */
1871 bool fCached;
1872 /** This is used by the R3 access handlers when invoked by an async thread.
1873 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1874 bool volatile fReusedFlushPending;
1875 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1876 bool fDirty;
1877
1878 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1879 uint32_t cLocked;
1880 uint32_t idxDirty;
1881 RTGCPTR pvDirtyFault;
1882} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1883/** Pointer to a const pool page. */
1884typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1885
1886
1887/** The hash table size. */
1888# define PGMPOOL_HASH_SIZE 0x40
1889/** The hash function. */
1890# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1891
1892
1893/**
1894 * The shadow page pool instance data.
1895 *
1896 * It's all one big allocation made at init time, except for the
1897 * pages that is. The user nodes follows immediatly after the
1898 * page structures.
1899 */
1900typedef struct PGMPOOL
1901{
1902 /** The VM handle - R3 Ptr. */
1903 PVMR3 pVMR3;
1904 /** The VM handle - R0 Ptr. */
1905 PVMR0 pVMR0;
1906 /** The VM handle - RC Ptr. */
1907 PVMRC pVMRC;
1908 /** The max pool size. This includes the special IDs. */
1909 uint16_t cMaxPages;
1910 /** The current pool size. */
1911 uint16_t cCurPages;
1912 /** The head of the free page list. */
1913 uint16_t iFreeHead;
1914 /* Padding. */
1915 uint16_t u16Padding;
1916 /** Head of the chain of free user nodes. */
1917 uint16_t iUserFreeHead;
1918 /** The number of user nodes we've allocated. */
1919 uint16_t cMaxUsers;
1920 /** The number of present page table entries in the entire pool. */
1921 uint32_t cPresent;
1922 /** Pointer to the array of user nodes - RC pointer. */
1923 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1924 /** Pointer to the array of user nodes - R3 pointer. */
1925 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1926 /** Pointer to the array of user nodes - R0 pointer. */
1927 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1928 /** Head of the chain of free phys ext nodes. */
1929 uint16_t iPhysExtFreeHead;
1930 /** The number of user nodes we've allocated. */
1931 uint16_t cMaxPhysExts;
1932 /** Pointer to the array of physical xref extent - RC pointer. */
1933 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1934 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1935 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1936 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1937 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1938 /** Hash table for GCPhys addresses. */
1939 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1940 /** The head of the age list. */
1941 uint16_t iAgeHead;
1942 /** The tail of the age list. */
1943 uint16_t iAgeTail;
1944 /** Set if the cache is enabled. */
1945 bool fCacheEnabled;
1946 /** Alignment padding. */
1947 bool afPadding1[3];
1948 /** Head of the list of modified pages. */
1949 uint16_t iModifiedHead;
1950 /** The current number of modified pages. */
1951 uint16_t cModifiedPages;
1952 /** Access handler, RC. */
1953 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1954 /** Access handler, R0. */
1955 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1956 /** Access handler, R3. */
1957 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1958 /** The access handler description (R3 ptr). */
1959 R3PTRTYPE(const char *) pszAccessHandler;
1960# if HC_ARCH_BITS == 32
1961 /** Alignment padding. */
1962 uint32_t u32Padding2;
1963# endif
1964 /* Next available slot. */
1965 uint32_t idxFreeDirtyPage;
1966 /* Number of active dirty pages. */
1967 uint32_t cDirtyPages;
1968 /* Array of current dirty pgm pool page indices. */
1969 uint16_t aIdxDirtyPages[16];
1970 uint64_t aDirtyPages[16][512];
1971 /** The number of pages currently in use. */
1972 uint16_t cUsedPages;
1973#ifdef VBOX_WITH_STATISTICS
1974 /** The high water mark for cUsedPages. */
1975 uint16_t cUsedPagesHigh;
1976 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1977 /** Profiling pgmPoolAlloc(). */
1978 STAMPROFILEADV StatAlloc;
1979 /** Profiling pgmR3PoolClearDoIt(). */
1980 STAMPROFILE StatClearAll;
1981 /** Profiling pgmR3PoolReset(). */
1982 STAMPROFILE StatR3Reset;
1983 /** Profiling pgmPoolFlushPage(). */
1984 STAMPROFILE StatFlushPage;
1985 /** Profiling pgmPoolFree(). */
1986 STAMPROFILE StatFree;
1987 /** Counting explicit flushes by PGMPoolFlushPage(). */
1988 STAMCOUNTER StatForceFlushPage;
1989 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1990 STAMCOUNTER StatForceFlushDirtyPage;
1991 /** Counting flushes for reused pages. */
1992 STAMCOUNTER StatForceFlushReused;
1993 /** Profiling time spent zeroing pages. */
1994 STAMPROFILE StatZeroPage;
1995 /** Profiling of pgmPoolTrackDeref. */
1996 STAMPROFILE StatTrackDeref;
1997 /** Profiling pgmTrackFlushGCPhysPT. */
1998 STAMPROFILE StatTrackFlushGCPhysPT;
1999 /** Profiling pgmTrackFlushGCPhysPTs. */
2000 STAMPROFILE StatTrackFlushGCPhysPTs;
2001 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2002 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2003 /** Number of times we've been out of user records. */
2004 STAMCOUNTER StatTrackFreeUpOneUser;
2005 /** Nr of flushed entries. */
2006 STAMCOUNTER StatTrackFlushEntry;
2007 /** Nr of updated entries. */
2008 STAMCOUNTER StatTrackFlushEntryKeep;
2009 /** Profiling deref activity related tracking GC physical pages. */
2010 STAMPROFILE StatTrackDerefGCPhys;
2011 /** Number of linear searches for a HCPhys in the ram ranges. */
2012 STAMCOUNTER StatTrackLinearRamSearches;
2013 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2014 STAMCOUNTER StamTrackPhysExtAllocFailures;
2015 /** Profiling the RC/R0 access handler. */
2016 STAMPROFILE StatMonitorRZ;
2017 /** Times we've failed interpreting the instruction. */
2018 STAMCOUNTER StatMonitorRZEmulateInstr;
2019 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2020 STAMPROFILE StatMonitorRZFlushPage;
2021 /* Times we've detected a page table reinit. */
2022 STAMCOUNTER StatMonitorRZFlushReinit;
2023 /** Counting flushes for pages that are modified too often. */
2024 STAMCOUNTER StatMonitorRZFlushModOverflow;
2025 /** Times we've detected fork(). */
2026 STAMCOUNTER StatMonitorRZFork;
2027 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2028 STAMPROFILE StatMonitorRZHandled;
2029 /** Times we've failed interpreting a patch code instruction. */
2030 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2031 /** Times we've failed interpreting a patch code instruction during flushing. */
2032 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2033 /** The number of times we've seen rep prefixes we can't handle. */
2034 STAMCOUNTER StatMonitorRZRepPrefix;
2035 /** Profiling the REP STOSD cases we've handled. */
2036 STAMPROFILE StatMonitorRZRepStosd;
2037 /** Nr of handled PT faults. */
2038 STAMCOUNTER StatMonitorRZFaultPT;
2039 /** Nr of handled PD faults. */
2040 STAMCOUNTER StatMonitorRZFaultPD;
2041 /** Nr of handled PDPT faults. */
2042 STAMCOUNTER StatMonitorRZFaultPDPT;
2043 /** Nr of handled PML4 faults. */
2044 STAMCOUNTER StatMonitorRZFaultPML4;
2045
2046 /** Profiling the R3 access handler. */
2047 STAMPROFILE StatMonitorR3;
2048 /** Times we've failed interpreting the instruction. */
2049 STAMCOUNTER StatMonitorR3EmulateInstr;
2050 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2051 STAMPROFILE StatMonitorR3FlushPage;
2052 /* Times we've detected a page table reinit. */
2053 STAMCOUNTER StatMonitorR3FlushReinit;
2054 /** Counting flushes for pages that are modified too often. */
2055 STAMCOUNTER StatMonitorR3FlushModOverflow;
2056 /** Times we've detected fork(). */
2057 STAMCOUNTER StatMonitorR3Fork;
2058 /** Profiling the R3 access we've handled (except REP STOSD). */
2059 STAMPROFILE StatMonitorR3Handled;
2060 /** The number of times we've seen rep prefixes we can't handle. */
2061 STAMCOUNTER StatMonitorR3RepPrefix;
2062 /** Profiling the REP STOSD cases we've handled. */
2063 STAMPROFILE StatMonitorR3RepStosd;
2064 /** Nr of handled PT faults. */
2065 STAMCOUNTER StatMonitorR3FaultPT;
2066 /** Nr of handled PD faults. */
2067 STAMCOUNTER StatMonitorR3FaultPD;
2068 /** Nr of handled PDPT faults. */
2069 STAMCOUNTER StatMonitorR3FaultPDPT;
2070 /** Nr of handled PML4 faults. */
2071 STAMCOUNTER StatMonitorR3FaultPML4;
2072 /** The number of times we're called in an async thread an need to flush. */
2073 STAMCOUNTER StatMonitorR3Async;
2074 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2075 STAMCOUNTER StatResetDirtyPages;
2076 /** Times we've called pgmPoolAddDirtyPage. */
2077 STAMCOUNTER StatDirtyPage;
2078 /** Times we've had to flush duplicates for dirty page management. */
2079 STAMCOUNTER StatDirtyPageDupFlush;
2080 /** Times we've had to flush because of overflow. */
2081 STAMCOUNTER StatDirtyPageOverFlowFlush;
2082
2083 /** The high wather mark for cModifiedPages. */
2084 uint16_t cModifiedPagesHigh;
2085 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2086
2087 /** The number of cache hits. */
2088 STAMCOUNTER StatCacheHits;
2089 /** The number of cache misses. */
2090 STAMCOUNTER StatCacheMisses;
2091 /** The number of times we've got a conflict of 'kind' in the cache. */
2092 STAMCOUNTER StatCacheKindMismatches;
2093 /** Number of times we've been out of pages. */
2094 STAMCOUNTER StatCacheFreeUpOne;
2095 /** The number of cacheable allocations. */
2096 STAMCOUNTER StatCacheCacheable;
2097 /** The number of uncacheable allocations. */
2098 STAMCOUNTER StatCacheUncacheable;
2099#else
2100 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2101#endif
2102 /** The AVL tree for looking up a page by its HC physical address. */
2103 AVLOHCPHYSTREE HCPhysTree;
2104 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2105 /** Array of pages. (cMaxPages in length)
2106 * The Id is the index into thist array.
2107 */
2108 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2109} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2110AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2111AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2112AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2113#ifdef VBOX_WITH_STATISTICS
2114AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2115#endif
2116AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2117
2118
2119/** @def PGMPOOL_PAGE_2_PTR
2120 * Maps a pool page pool into the current context.
2121 *
2122 * @returns VBox status code.
2123 * @param pVM The VM handle.
2124 * @param pPage The pool page.
2125 *
2126 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2127 * small page window employeed by that function. Be careful.
2128 * @remark There is no need to assert on the result.
2129 */
2130#if defined(IN_RC)
2131# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2132#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2133# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2134#elif defined(VBOX_STRICT)
2135# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2136DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2137{
2138 Assert(pPage && pPage->pvPageR3);
2139 return pPage->pvPageR3;
2140}
2141#else
2142# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2143#endif
2144
2145/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2146 * Maps a pool page pool into the current context.
2147 *
2148 * @returns VBox status code.
2149 * @param pPGM Pointer to the PGM instance data.
2150 * @param pPage The pool page.
2151 *
2152 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2153 * small page window employeed by that function. Be careful.
2154 * @remark There is no need to assert on the result.
2155 */
2156#if defined(IN_RC)
2157# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2158#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2159# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2160#else
2161# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2162#endif
2163
2164/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2165 * Maps a pool page pool into the current context.
2166 *
2167 * @returns VBox status code.
2168 * @param pPGM Pointer to the PGMCPU instance data.
2169 * @param pPage The pool page.
2170 *
2171 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2172 * small page window employeed by that function. Be careful.
2173 * @remark There is no need to assert on the result.
2174 */
2175#if defined(IN_RC)
2176# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2177#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2178# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2179#else
2180# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2181#endif
2182
2183
2184/** @name Per guest page tracking data.
2185 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2186 * is to use more bits for it and split it up later on. But for now we'll play
2187 * safe and change as little as possible.
2188 *
2189 * The 16-bit word has two parts:
2190 *
2191 * The first 14-bit forms the @a idx field. It is either the index of a page in
2192 * the shadow page pool, or and index into the extent list.
2193 *
2194 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2195 * shadow page pool references to the page. If cRefs equals
2196 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2197 * (misnomer) table and not the shadow page pool.
2198 *
2199 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2200 * the 16-bit word.
2201 *
2202 * @{ */
2203/** The shift count for getting to the cRefs part. */
2204#define PGMPOOL_TD_CREFS_SHIFT 14
2205/** The mask applied after shifting the tracking data down by
2206 * PGMPOOL_TD_CREFS_SHIFT. */
2207#define PGMPOOL_TD_CREFS_MASK 0x3
2208/** The cRef value used to indiciate that the idx is the head of a
2209 * physical cross reference list. */
2210#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2211/** The shift used to get idx. */
2212#define PGMPOOL_TD_IDX_SHIFT 0
2213/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2214#define PGMPOOL_TD_IDX_MASK 0x3fff
2215/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2216 * simply too many mappings of this page. */
2217#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2218
2219/** @def PGMPOOL_TD_MAKE
2220 * Makes a 16-bit tracking data word.
2221 *
2222 * @returns tracking data.
2223 * @param cRefs The @a cRefs field. Must be within bounds!
2224 * @param idx The @a idx field. Must also be within bounds! */
2225#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2226
2227/** @def PGMPOOL_TD_GET_CREFS
2228 * Get the @a cRefs field from a tracking data word.
2229 *
2230 * @returns The @a cRefs field
2231 * @param u16 The tracking data word. */
2232#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2233
2234/** @def PGMPOOL_TD_GET_IDX
2235 * Get the @a idx field from a tracking data word.
2236 *
2237 * @returns The @a idx field
2238 * @param u16 The tracking data word. */
2239#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2240/** @} */
2241
2242
2243/**
2244 * Trees are using self relative offsets as pointers.
2245 * So, all its data, including the root pointer, must be in the heap for HC and GC
2246 * to have the same layout.
2247 */
2248typedef struct PGMTREES
2249{
2250 /** Physical access handlers (AVL range+offsetptr tree). */
2251 AVLROGCPHYSTREE PhysHandlers;
2252 /** Virtual access handlers (AVL range + GC ptr tree). */
2253 AVLROGCPTRTREE VirtHandlers;
2254 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2255 AVLROGCPHYSTREE PhysToVirtHandlers;
2256 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2257 AVLROGCPTRTREE HyperVirtHandlers;
2258} PGMTREES;
2259/** Pointer to PGM trees. */
2260typedef PGMTREES *PPGMTREES;
2261
2262
2263/** @name Paging mode macros
2264 * @{ */
2265#ifdef IN_RC
2266# define PGM_CTX(a,b) a##RC##b
2267# define PGM_CTX_STR(a,b) a "GC" b
2268# define PGM_CTX_DECL(type) VMMRCDECL(type)
2269#else
2270# ifdef IN_RING3
2271# define PGM_CTX(a,b) a##R3##b
2272# define PGM_CTX_STR(a,b) a "R3" b
2273# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2274# else
2275# define PGM_CTX(a,b) a##R0##b
2276# define PGM_CTX_STR(a,b) a "R0" b
2277# define PGM_CTX_DECL(type) VMMDECL(type)
2278# endif
2279#endif
2280
2281#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2282#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2283#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2284#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2285#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2286#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2287#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2288#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2289#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2290#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2291#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2292#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2293#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2294#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2295#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2296#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2297#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2298
2299#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2300#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2301#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2302#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2303#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2304#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2305#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2306#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2307#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2308#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2309#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2310#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2311#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2312#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2313#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2314#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2315#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2316
2317/* Shw_Gst */
2318#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2319#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2320#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2321#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2322#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2323#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2324#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2325#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2326#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2327#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2328#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2329#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2330#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2331#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2332#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2333#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2334#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2335#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2336#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2337
2338#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2339#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2340#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2341#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2342#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2343#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2344#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2345#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2346#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2347#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2348#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2349#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2350#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2351#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2352#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2353#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2354#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2355#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2356#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2357#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2358#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2359#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2360#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2361#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2362#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2363#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2364#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2365#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2366#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2367#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2368#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2369#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2370#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2371#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2372#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2373#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2374#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2375
2376#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2377#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2378/** @} */
2379
2380/**
2381 * Data for each paging mode.
2382 */
2383typedef struct PGMMODEDATA
2384{
2385 /** The guest mode type. */
2386 uint32_t uGstType;
2387 /** The shadow mode type. */
2388 uint32_t uShwType;
2389
2390 /** @name Function pointers for Shadow paging.
2391 * @{
2392 */
2393 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2394 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2395 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2396 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2397
2398 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2399 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2400
2401 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2402 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2403 /** @} */
2404
2405 /** @name Function pointers for Guest paging.
2406 * @{
2407 */
2408 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2409 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2410 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2411 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2412 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2413 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2414 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2415 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2416 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2417 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2418 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2419 /** @} */
2420
2421 /** @name Function pointers for Both Shadow and Guest paging.
2422 * @{
2423 */
2424 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2425 /* no pfnR3BthTrap0eHandler */
2426 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2427 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2428 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2429 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2430 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2431#ifdef VBOX_STRICT
2432 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2433#endif
2434 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2435 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2436
2437 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2438 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2439 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2440 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2441 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2442 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2443#ifdef VBOX_STRICT
2444 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2445#endif
2446 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2447 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2448
2449 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2450 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2451 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2452 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2453 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2454 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2455#ifdef VBOX_STRICT
2456 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2457#endif
2458 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2459 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2460 /** @} */
2461} PGMMODEDATA, *PPGMMODEDATA;
2462
2463
2464
2465/**
2466 * Converts a PGM pointer into a VM pointer.
2467 * @returns Pointer to the VM structure the PGM is part of.
2468 * @param pPGM Pointer to PGM instance data.
2469 */
2470#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2471
2472/**
2473 * PGM Data (part of VM)
2474 */
2475typedef struct PGM
2476{
2477 /** Offset to the VM structure. */
2478 RTINT offVM;
2479 /** Offset of the PGMCPU structure relative to VMCPU. */
2480 RTINT offVCpuPGM;
2481
2482 /** @cfgm{RamPreAlloc, boolean, false}
2483 * Indicates whether the base RAM should all be allocated before starting
2484 * the VM (default), or if it should be allocated when first written to.
2485 */
2486 bool fRamPreAlloc;
2487 /** Indicates whether write monitoring is currently in use.
2488 * This is used to prevent conflicts between live saving and page sharing
2489 * detection. */
2490 bool fPhysWriteMonitoringEngaged;
2491 /** Alignment padding. */
2492 bool afAlignment0[2];
2493
2494 /*
2495 * This will be redefined at least two more times before we're done, I'm sure.
2496 * The current code is only to get on with the coding.
2497 * - 2004-06-10: initial version, bird.
2498 * - 2004-07-02: 1st time, bird.
2499 * - 2004-10-18: 2nd time, bird.
2500 * - 2005-07-xx: 3rd time, bird.
2501 */
2502
2503 /** The host paging mode. (This is what SUPLib reports.) */
2504 SUPPAGINGMODE enmHostMode;
2505
2506 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2507 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2508 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2509 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2510
2511 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2512 RTGCPHYS GCPhys4MBPSEMask;
2513
2514 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2515 * This is sorted by physical address and contains no overlapping ranges. */
2516 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2517 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2518 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2519 /** RC pointer corresponding to PGM::pRamRangesR3. */
2520 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2521 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2522 * range is linked or unlinked. */
2523 uint32_t volatile idRamRangesGen;
2524
2525 /** Pointer to the list of ROM ranges - for R3.
2526 * This is sorted by physical address and contains no overlapping ranges. */
2527 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2528 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2529 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2530 /** RC pointer corresponding to PGM::pRomRangesR3. */
2531 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2532#if HC_ARCH_BITS == 64
2533 /** Alignment padding. */
2534 RTRCPTR GCPtrPadding2;
2535#endif
2536
2537 /** Pointer to the list of MMIO2 ranges - for R3.
2538 * Registration order. */
2539 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2540
2541 /** PGM offset based trees - R3 Ptr. */
2542 R3PTRTYPE(PPGMTREES) pTreesR3;
2543 /** PGM offset based trees - R0 Ptr. */
2544 R0PTRTYPE(PPGMTREES) pTreesR0;
2545 /** PGM offset based trees - RC Ptr. */
2546 RCPTRTYPE(PPGMTREES) pTreesRC;
2547
2548 /** Linked list of GC mappings - for RC.
2549 * The list is sorted ascending on address.
2550 */
2551 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2552 /** Linked list of GC mappings - for HC.
2553 * The list is sorted ascending on address.
2554 */
2555 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2556 /** Linked list of GC mappings - for R0.
2557 * The list is sorted ascending on address.
2558 */
2559 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2560
2561 /** Pointer to the 5 page CR3 content mapping.
2562 * The first page is always the CR3 (in some form) while the 4 other pages
2563 * are used of the PDs in PAE mode. */
2564 RTGCPTR GCPtrCR3Mapping;
2565#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2566 uint32_t u32Alignment1;
2567#endif
2568
2569 /** Indicates that PGMR3FinalizeMappings has been called and that further
2570 * PGMR3MapIntermediate calls will be rejected. */
2571 bool fFinalizedMappings;
2572 /** If set no conflict checks are required. */
2573 bool fMappingsFixed;
2574 /** If set if restored as fixed but we were unable to re-fixate at the old
2575 * location because of room or address incompatibilities. */
2576 bool fMappingsFixedRestored;
2577 /** If set, then no mappings are put into the shadow page table.
2578 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2579 bool fMappingsDisabled;
2580 /** Size of fixed mapping.
2581 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2582 uint32_t cbMappingFixed;
2583 /** Base address (GC) of fixed mapping.
2584 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2585 RTGCPTR GCPtrMappingFixed;
2586 /** The address of the previous RAM range mapping. */
2587 RTGCPTR GCPtrPrevRamRangeMapping;
2588
2589 /** @name Intermediate Context
2590 * @{ */
2591 /** Pointer to the intermediate page directory - Normal. */
2592 R3PTRTYPE(PX86PD) pInterPD;
2593 /** Pointer to the intermedate page tables - Normal.
2594 * There are two page tables, one for the identity mapping and one for
2595 * the host context mapping (of the core code). */
2596 R3PTRTYPE(PX86PT) apInterPTs[2];
2597 /** Pointer to the intermedate page tables - PAE. */
2598 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2599 /** Pointer to the intermedate page directory - PAE. */
2600 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2601 /** Pointer to the intermedate page directory - PAE. */
2602 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2603 /** Pointer to the intermedate page-map level 4 - AMD64. */
2604 R3PTRTYPE(PX86PML4) pInterPaePML4;
2605 /** Pointer to the intermedate page directory - AMD64. */
2606 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2607 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2608 RTHCPHYS HCPhysInterPD;
2609 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2610 RTHCPHYS HCPhysInterPaePDPT;
2611 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2612 RTHCPHYS HCPhysInterPaePML4;
2613 /** @} */
2614
2615 /** Base address of the dynamic page mapping area.
2616 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2617 */
2618 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2619 /** The index of the last entry used in the dynamic page mapping area. */
2620 RTUINT iDynPageMapLast;
2621 /** Cache containing the last entries in the dynamic page mapping area.
2622 * The cache size is covering half of the mapping area. */
2623 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2624 /** Keep a lock counter for the full (!) mapping area. */
2625 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2626
2627 /** The address of the ring-0 mapping cache if we're making use of it. */
2628 RTR0PTR pvR0DynMapUsed;
2629#if HC_ARCH_BITS == 32
2630 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2631 uint32_t u32Alignment2;
2632#endif
2633
2634 /** PGM critical section.
2635 * This protects the physical & virtual access handlers, ram ranges,
2636 * and the page flag updating (some of it anyway).
2637 */
2638 PDMCRITSECT CritSect;
2639
2640 /** Pointer to SHW+GST mode data (function pointers).
2641 * The index into this table is made up from */
2642 R3PTRTYPE(PPGMMODEDATA) paModeData;
2643
2644 /** Shadow Page Pool - R3 Ptr. */
2645 R3PTRTYPE(PPGMPOOL) pPoolR3;
2646 /** Shadow Page Pool - R0 Ptr. */
2647 R0PTRTYPE(PPGMPOOL) pPoolR0;
2648 /** Shadow Page Pool - RC Ptr. */
2649 RCPTRTYPE(PPGMPOOL) pPoolRC;
2650
2651 /** We're not in a state which permits writes to guest memory.
2652 * (Only used in strict builds.) */
2653 bool fNoMorePhysWrites;
2654 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2655 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2656
2657 /**
2658 * Data associated with managing the ring-3 mappings of the allocation chunks.
2659 */
2660 struct
2661 {
2662 /** The chunk tree, ordered by chunk id. */
2663#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2664 R3PTRTYPE(PAVLU32NODECORE) pTree;
2665#else
2666 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2667#endif
2668 /** The chunk age tree, ordered by ageing sequence number. */
2669 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2670 /** The chunk mapping TLB. */
2671 PGMCHUNKR3MAPTLB Tlb;
2672 /** The number of mapped chunks. */
2673 uint32_t c;
2674 /** The maximum number of mapped chunks.
2675 * @cfgm PGM/MaxRing3Chunks */
2676 uint32_t cMax;
2677 /** The current time. */
2678 uint32_t iNow;
2679 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2680 uint32_t AgeingCountdown;
2681 } ChunkR3Map;
2682
2683 /**
2684 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2685 */
2686 PGMPAGER3MAPTLB PhysTlbHC;
2687
2688 /** @name The zero page.
2689 * @{ */
2690 /** The host physical address of the zero page. */
2691 RTHCPHYS HCPhysZeroPg;
2692 /** The ring-3 mapping of the zero page. */
2693 RTR3PTR pvZeroPgR3;
2694 /** The ring-0 mapping of the zero page. */
2695 RTR0PTR pvZeroPgR0;
2696 /** The GC mapping of the zero page. */
2697 RTGCPTR pvZeroPgRC;
2698 /** @}*/
2699
2700 /** The number of handy pages. */
2701 uint32_t cHandyPages;
2702
2703 /** The number of large handy pages. */
2704 uint32_t cLargeHandyPages;
2705
2706 /**
2707 * Array of handy pages.
2708 *
2709 * This array is used in a two way communication between pgmPhysAllocPage
2710 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2711 * an intermediary.
2712 *
2713 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2714 * (The current size of 32 pages, means 128 KB of handy memory.)
2715 */
2716 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2717
2718 /**
2719 * Array of large handy pages. (currently size 1)
2720 *
2721 * This array is used in a two way communication between pgmPhysAllocLargePage
2722 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2723 * an intermediary.
2724 */
2725 GMMPAGEDESC aLargeHandyPage[1];
2726
2727 /**
2728 * Live save data.
2729 */
2730 struct
2731 {
2732 /** Per type statistics. */
2733 struct
2734 {
2735 /** The number of ready pages. */
2736 uint32_t cReadyPages;
2737 /** The number of dirty pages. */
2738 uint32_t cDirtyPages;
2739 /** The number of ready zero pages. */
2740 uint32_t cZeroPages;
2741 /** The number of write monitored pages. */
2742 uint32_t cMonitoredPages;
2743 } Rom,
2744 Mmio2,
2745 Ram;
2746 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2747 uint32_t cIgnoredPages;
2748 /** Indicates that a live save operation is active. */
2749 bool fActive;
2750 /** Padding. */
2751 bool afReserved[2];
2752 /** The next history index. */
2753 uint8_t iDirtyPagesHistory;
2754 /** History of the total amount of dirty pages. */
2755 uint32_t acDirtyPagesHistory[64];
2756 /** Short term dirty page average. */
2757 uint32_t cDirtyPagesShort;
2758 /** Long term dirty page average. */
2759 uint32_t cDirtyPagesLong;
2760 /** The number of saved pages. This is used to get some kind of estimate of the
2761 * link speed so we can decide when we're done. It is reset after the first
2762 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2763 * zero pages. */
2764 uint64_t cSavedPages;
2765 /** The nanosecond timestamp when cSavedPages was 0. */
2766 uint64_t uSaveStartNS;
2767 /** Pages per second (for statistics). */
2768 uint32_t cPagesPerSecond;
2769 uint32_t cAlignment;
2770 } LiveSave;
2771
2772 /** @name Error injection.
2773 * @{ */
2774 /** Inject handy page allocation errors pretending we're completely out of
2775 * memory. */
2776 bool volatile fErrInjHandyPages;
2777 /** Padding. */
2778 bool afReserved[3];
2779 /** @} */
2780
2781 /** @name Release Statistics
2782 * @{ */
2783 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2784 uint32_t cPrivatePages; /**< The number of private pages. */
2785 uint32_t cSharedPages; /**< The number of shared pages. */
2786 uint32_t cZeroPages; /**< The number of zero backed pages. */
2787 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2788 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2789 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2790 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2791 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2792 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
2793 uint32_t aAlignment4[1];
2794
2795 /** The number of times we were forced to change the hypervisor region location. */
2796 STAMCOUNTER cRelocations;
2797
2798 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
2799 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
2800 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2801 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
2802 /** @} */
2803
2804#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2805 /* R3 only: */
2806 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2807 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2808
2809 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2810 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2811 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2812 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2813 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2814 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2815 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2816 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2817 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2818 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2819 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2820 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2821 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2822 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2823 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2824 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2825 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2826 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2827 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2828 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2829/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2830 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2831 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2832/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2833
2834 /* RC only: */
2835 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2836 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2837 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2838 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2839
2840 STAMCOUNTER StatRZPhysRead;
2841 STAMCOUNTER StatRZPhysReadBytes;
2842 STAMCOUNTER StatRZPhysWrite;
2843 STAMCOUNTER StatRZPhysWriteBytes;
2844 STAMCOUNTER StatR3PhysRead;
2845 STAMCOUNTER StatR3PhysReadBytes;
2846 STAMCOUNTER StatR3PhysWrite;
2847 STAMCOUNTER StatR3PhysWriteBytes;
2848 STAMCOUNTER StatRCPhysRead;
2849 STAMCOUNTER StatRCPhysReadBytes;
2850 STAMCOUNTER StatRCPhysWrite;
2851 STAMCOUNTER StatRCPhysWriteBytes;
2852
2853 STAMCOUNTER StatRZPhysSimpleRead;
2854 STAMCOUNTER StatRZPhysSimpleReadBytes;
2855 STAMCOUNTER StatRZPhysSimpleWrite;
2856 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2857 STAMCOUNTER StatR3PhysSimpleRead;
2858 STAMCOUNTER StatR3PhysSimpleReadBytes;
2859 STAMCOUNTER StatR3PhysSimpleWrite;
2860 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2861 STAMCOUNTER StatRCPhysSimpleRead;
2862 STAMCOUNTER StatRCPhysSimpleReadBytes;
2863 STAMCOUNTER StatRCPhysSimpleWrite;
2864 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2865
2866 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2867 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2868 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2869 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2870 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2871 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2872 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2873
2874 /** Time spent by the host OS for large page allocation. */
2875 STAMPROFILE StatAllocLargePage;
2876 /** Time spent clearing the newly allocated large pages. */
2877 STAMPROFILE StatClearLargePage;
2878 /** pgmPhysIsValidLargePage profiling - R3 */
2879 STAMPROFILE StatR3IsValidLargePage;
2880 /** pgmPhysIsValidLargePage profiling - RZ*/
2881 STAMPROFILE StatRZIsValidLargePage;
2882#endif
2883} PGM;
2884#ifndef IN_TSTVMSTRUCTGC /* HACK */
2885AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2886AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2887AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2888AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2889AssertCompileMemberAlignment(PGM, CritSect, 8);
2890AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2891AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2892AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2893AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2894AssertCompileMemberAlignment(PGM, cRelocations, 8);
2895#endif /* !IN_TSTVMSTRUCTGC */
2896/** Pointer to the PGM instance data. */
2897typedef PGM *PPGM;
2898
2899
2900/**
2901 * Converts a PGMCPU pointer into a VM pointer.
2902 * @returns Pointer to the VM structure the PGM is part of.
2903 * @param pPGM Pointer to PGMCPU instance data.
2904 */
2905#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2906
2907/**
2908 * Converts a PGMCPU pointer into a PGM pointer.
2909 * @returns Pointer to the VM structure the PGM is part of.
2910 * @param pPGM Pointer to PGMCPU instance data.
2911 */
2912#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2913
2914/**
2915 * PGMCPU Data (part of VMCPU).
2916 */
2917typedef struct PGMCPU
2918{
2919 /** Offset to the VM structure. */
2920 RTINT offVM;
2921 /** Offset to the VMCPU structure. */
2922 RTINT offVCpu;
2923 /** Offset of the PGM structure relative to VMCPU. */
2924 RTINT offPGM;
2925 RTINT uPadding0; /**< structure size alignment. */
2926
2927#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2928 /** Automatically tracked physical memory mapping set.
2929 * Ring-0 and strict raw-mode builds. */
2930 PGMMAPSET AutoSet;
2931#endif
2932
2933 /** A20 gate mask.
2934 * Our current approach to A20 emulation is to let REM do it and don't bother
2935 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2936 * But whould need arrise, we'll subject physical addresses to this mask. */
2937 RTGCPHYS GCPhysA20Mask;
2938 /** A20 gate state - boolean! */
2939 bool fA20Enabled;
2940
2941 /** What needs syncing (PGM_SYNC_*).
2942 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2943 * PGMFlushTLB, and PGMR3Load. */
2944 RTUINT fSyncFlags;
2945
2946 /** The shadow paging mode. */
2947 PGMMODE enmShadowMode;
2948 /** The guest paging mode. */
2949 PGMMODE enmGuestMode;
2950
2951 /** The current physical address representing in the guest CR3 register. */
2952 RTGCPHYS GCPhysCR3;
2953
2954 /** @name 32-bit Guest Paging.
2955 * @{ */
2956 /** The guest's page directory, R3 pointer. */
2957 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2958#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2959 /** The guest's page directory, R0 pointer. */
2960 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2961#endif
2962 /** The guest's page directory, static RC mapping. */
2963 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2964 /** @} */
2965
2966 /** @name PAE Guest Paging.
2967 * @{ */
2968 /** The guest's page directory pointer table, static RC mapping. */
2969 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2970 /** The guest's page directory pointer table, R3 pointer. */
2971 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2972#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2973 /** The guest's page directory pointer table, R0 pointer. */
2974 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2975#endif
2976
2977 /** The guest's page directories, R3 pointers.
2978 * These are individual pointers and don't have to be adjecent.
2979 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2980 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2981 /** The guest's page directories, R0 pointers.
2982 * Same restrictions as apGstPaePDsR3. */
2983#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2984 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2985#endif
2986 /** The guest's page directories, static GC mapping.
2987 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2988 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2989 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2990 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2991 RTGCPHYS aGCPhysGstPaePDs[4];
2992 /** The physical addresses of the monitored guest page directories (PAE). */
2993 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2994 /** @} */
2995
2996 /** @name AMD64 Guest Paging.
2997 * @{ */
2998 /** The guest's page directory pointer table, R3 pointer. */
2999 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3000#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3001 /** The guest's page directory pointer table, R0 pointer. */
3002 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3003#else
3004 RTR0PTR alignment6b; /**< alignment equalizer. */
3005#endif
3006 /** @} */
3007
3008 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3009 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3010 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3011 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3012 /** Pointer to the page of the current active CR3 - RC Ptr. */
3013 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3014 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3015 uint32_t iShwUser;
3016 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3017 uint32_t iShwUserTable;
3018# if HC_ARCH_BITS == 64
3019 RTRCPTR alignment6; /**< structure size alignment. */
3020# endif
3021 /** @} */
3022
3023 /** @name Function pointers for Shadow paging.
3024 * @{
3025 */
3026 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3027 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3028 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3029 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3030
3031 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3032 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3033
3034 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3035 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3036
3037 /** @} */
3038
3039 /** @name Function pointers for Guest paging.
3040 * @{
3041 */
3042 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3043 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3044 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3045 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3046 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3047 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3048 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3049 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3050#if HC_ARCH_BITS == 64
3051 RTRCPTR alignment3; /**< structure size alignment. */
3052#endif
3053
3054 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3055 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3056 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3057 /** @} */
3058
3059 /** @name Function pointers for Both Shadow and Guest paging.
3060 * @{
3061 */
3062 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3063 /* no pfnR3BthTrap0eHandler */
3064 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3065 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3066 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3067 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3068 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3069 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3070 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3071 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3072
3073 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3074 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3075 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3076 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3077 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3078 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3079 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3080 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3081 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3082
3083 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3084 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3085 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3086 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3087 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3088 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3089 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3090 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3091 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3092 RTRCPTR alignment2; /**< structure size alignment. */
3093 /** @} */
3094
3095 /** For saving stack space, the disassembler state is allocated here instead of
3096 * on the stack.
3097 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3098 union
3099 {
3100 /** The disassembler scratch space. */
3101 DISCPUSTATE DisState;
3102 /** Padding. */
3103 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3104 };
3105
3106 /* Count the number of pgm pool access handler calls. */
3107 uint64_t cPoolAccessHandler;
3108
3109 /** @name Release Statistics
3110 * @{ */
3111 /** The number of times the guest has switched mode since last reset or statistics reset. */
3112 STAMCOUNTER cGuestModeChanges;
3113 /** @} */
3114
3115#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3116 /** @name Statistics
3117 * @{ */
3118 /** RC: Which statistic this \#PF should be attributed to. */
3119 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3120 RTRCPTR padding0;
3121 /** R0: Which statistic this \#PF should be attributed to. */
3122 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3123 RTR0PTR padding1;
3124
3125 /* Common */
3126 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3127 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3128
3129 /* R0 only: */
3130 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3131 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3132 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3133 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3134 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3135 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3136 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3137 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3138 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3139 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3140 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3141 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3142 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3143 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3144 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3145 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3146 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3147 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3148 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3149 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3150 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3151 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3152 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3153 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3154 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3155 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3156
3157 /* RZ only: */
3158 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3159 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3160 STAMPROFILE StatRZTrap0eTimeSyncPT;
3161 STAMPROFILE StatRZTrap0eTimeMapping;
3162 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3163 STAMPROFILE StatRZTrap0eTimeHandlers;
3164 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3165 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3166 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3167 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3168 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3169 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3170 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3171 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3172 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3173 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3174 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3175 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3176 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3177 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3178 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3179 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3180 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3181 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3182 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3183 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3184 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3185 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3186 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3187 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3188 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3189 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3190 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3191 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3192 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3193 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3194 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3195 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3196 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3197 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3198 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3199 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3200 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3201 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3202 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3203 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3204 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3205 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3206 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3207
3208 /* HC - R3 and (maybe) R0: */
3209
3210 /* RZ & R3: */
3211 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3212 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3213 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3214 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3215 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3216 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3217 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3218 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3219 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3220 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3221 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3222 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3223 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3224 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3225 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3226 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3227 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3228 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3229 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3230 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3231 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3232 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3233 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3234 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3235 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3236 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3237 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3238 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3239 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3240 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3241 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3242 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3243 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3244 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3245 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3246 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3247 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3248 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3249 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3250 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3251 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3252 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3253 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3254 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3255 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3256 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3257 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3258
3259 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3260 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3261 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3262 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3263 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3264 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3265 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3266 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3267 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3268 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3269 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3270 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3271 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3272 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3273 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3274 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3275 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3276 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3277 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3278 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3279 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3280 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3281 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3282 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3283 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3284 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3285 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3286 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3287 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3288 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3289 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3290 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3291 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3292 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3293 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3294 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3295 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3296 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3297 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3298 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3299 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3300 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3301 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3302 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3303 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3304 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3305 /** @} */
3306#endif /* VBOX_WITH_STATISTICS */
3307} PGMCPU;
3308/** Pointer to the per-cpu PGM data. */
3309typedef PGMCPU *PPGMCPU;
3310
3311
3312/** @name PGM::fSyncFlags Flags
3313 * @{
3314 */
3315/** Updates the virtual access handler state bit in PGMPAGE. */
3316#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3317/** Always sync CR3. */
3318#define PGM_SYNC_ALWAYS RT_BIT(1)
3319/** Check monitoring on next CR3 (re)load and invalidate page.
3320 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3321#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3322/** Check guest mapping in SyncCR3. */
3323#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3324/** Clear the page pool (a light weight flush). */
3325#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3326#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3327/** @} */
3328
3329
3330RT_C_DECLS_BEGIN
3331
3332int pgmLock(PVM pVM);
3333void pgmUnlock(PVM pVM);
3334
3335int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3336int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3337int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3338PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3339int pgmMapResolveConflicts(PVM pVM);
3340DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3341
3342void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3343bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3344void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3345int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3346DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3347#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3348void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3349#else
3350# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3351#endif
3352DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3353int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3354
3355int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3356int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3357int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3358int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3359int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3360void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3361int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3362int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3363int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3364int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3365int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3366int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3367int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3368VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3369VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3370#ifdef IN_RING3
3371void pgmR3PhysRelinkRamRanges(PVM pVM);
3372int pgmR3PhysRamPreAllocate(PVM pVM);
3373int pgmR3PhysRamReset(PVM pVM);
3374int pgmR3PhysRomReset(PVM pVM);
3375int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3376
3377int pgmR3PoolInit(PVM pVM);
3378void pgmR3PoolRelocate(PVM pVM);
3379void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3380void pgmR3PoolReset(PVM pVM);
3381void pgmR3PoolClearAll(PVM pVM);
3382DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser);
3383
3384#endif /* IN_RING3 */
3385#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3386int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3387#endif
3388int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3389
3390DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3391{
3392 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3393}
3394
3395void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3396void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3397int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3398void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3399PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3400int pgmPoolSyncCR3(PVMCPU pVCpu);
3401bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3402int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3403void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3404void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3405DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3406{
3407 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3408}
3409
3410uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3411void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3412void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3413int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3414void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3415
3416void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3417void pgmPoolResetDirtyPages(PVM pVM);
3418
3419int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3420int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3421
3422void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3423void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3424int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3425int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3426
3427int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3428#ifndef IN_RC
3429int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3430#endif
3431int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3432
3433PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3434PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3435PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3436PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3437
3438RT_C_DECLS_END
3439
3440/** @} */
3441
3442#endif
3443
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