VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 30757

Last change on this file since 30757 was 30613, checked in by vboxsync, 14 years ago

Free zero page when loading a saved state with prealloc enabled.
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1/* $Id: PGMInternal.h 30613 2010-07-05 12:56:59Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/stam.h>
25#include <VBox/param.h>
26#include <VBox/vmm.h>
27#include <VBox/mm.h>
28#include <VBox/pdmcritsect.h>
29#include <VBox/pdmapi.h>
30#include <VBox/dis.h>
31#include <VBox/dbgf.h>
32#include <VBox/log.h>
33#include <VBox/gmm.h>
34#include <VBox/hwaccm.h>
35#include <include/internal/pgm.h>
36#include <iprt/asm.h>
37#include <iprt/assert.h>
38#include <iprt/avl.h>
39#include <iprt/critsect.h>
40#include <iprt/sha.h>
41
42
43
44/** @defgroup grp_pgm_int Internals
45 * @ingroup grp_pgm
46 * @internal
47 * @{
48 */
49
50
51/** @name PGM Compile Time Config
52 * @{
53 */
54
55/**
56 * Indicates that there are no guest mappings to care about.
57 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
58 */
59#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
60# define PGM_WITHOUT_MAPPINGS
61#endif
62
63/**
64 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
65 * Comment it if it will break something.
66 */
67#define PGM_OUT_OF_SYNC_IN_GC
68
69/**
70 * Check and skip global PDEs for non-global flushes
71 */
72#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
73
74/**
75 * Optimization for PAE page tables that are modified often
76 */
77//#if 0 /* disabled again while debugging */
78#ifndef IN_RC
79# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80#endif
81//#endif
82
83/**
84 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
85 */
86#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
87# define PGM_WITH_LARGE_PAGES
88#endif
89
90/**
91 * Sync N pages instead of a whole page table
92 */
93#define PGM_SYNC_N_PAGES
94
95/**
96 * Number of pages to sync during a page fault
97 *
98 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
99 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
100 *
101 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
102 * world switch overhead, so let's sync more.
103 */
104# ifdef IN_RING0
105/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
106 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
107 * but ~5% fewer faults.
108 */
109# define PGM_SYNC_NR_PAGES 32
110#else
111# define PGM_SYNC_NR_PAGES 8
112#endif
113
114/**
115 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
116 */
117#define PGM_MAX_PHYSCACHE_ENTRIES 64
118#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
119
120
121/** @def PGMPOOL_CFG_MAX_GROW
122 * The maximum number of pages to add to the pool in one go.
123 */
124#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
125
126/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
127 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
128 */
129#ifdef VBOX_STRICT
130# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
131#endif
132
133/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
134 * Enables the experimental lazy page allocation code. */
135/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
136
137/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
138 * Enables real write monitoring of pages, i.e. mapping them read-only and
139 * only making them writable when getting a write access #PF. */
140#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
141
142/** @} */
143
144
145/** @name PDPT and PML4 flags.
146 * These are placed in the three bits available for system programs in
147 * the PDPT and PML4 entries.
148 * @{ */
149/** The entry is a permanent one and it's must always be present.
150 * Never free such an entry. */
151#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
152/** Mapping (hypervisor allocated pagetable). */
153#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
154/** @} */
155
156/** @name Page directory flags.
157 * These are placed in the three bits available for system programs in
158 * the page directory entries.
159 * @{ */
160/** Mapping (hypervisor allocated pagetable). */
161#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
162/** Made read-only to facilitate dirty bit tracking. */
163#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
164/** @} */
165
166/** @name Page flags.
167 * These are placed in the three bits available for system programs in
168 * the page entries.
169 * @{ */
170/** Made read-only to facilitate dirty bit tracking. */
171#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
172
173#ifndef PGM_PTFLAGS_CSAM_VALIDATED
174/** Scanned and approved by CSAM (tm).
175 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
176 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
177#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
178#endif
179
180/** @} */
181
182/** @name Defines used to indicate the shadow and guest paging in the templates.
183 * @{ */
184#define PGM_TYPE_REAL 1
185#define PGM_TYPE_PROT 2
186#define PGM_TYPE_32BIT 3
187#define PGM_TYPE_PAE 4
188#define PGM_TYPE_AMD64 5
189#define PGM_TYPE_NESTED 6
190#define PGM_TYPE_EPT 7
191#define PGM_TYPE_MAX PGM_TYPE_EPT
192/** @} */
193
194/** Macro for checking if the guest is using paging.
195 * @param uGstType PGM_TYPE_*
196 * @param uShwType PGM_TYPE_*
197 * @remark ASSUMES certain order of the PGM_TYPE_* values.
198 */
199#define PGM_WITH_PAGING(uGstType, uShwType) \
200 ( (uGstType) >= PGM_TYPE_32BIT \
201 && (uShwType) != PGM_TYPE_NESTED \
202 && (uShwType) != PGM_TYPE_EPT)
203
204/** Macro for checking if the guest supports the NX bit.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_NX(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_PAE \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214
215/** @def PGM_HCPHYS_2_PTR
216 * Maps a HC physical page pool address to a virtual address.
217 *
218 * @returns VBox status code.
219 * @param pVM The VM handle.
220 * @param HCPhys The HC physical address to map to a virtual one.
221 * @param ppv Where to store the virtual address. No need to cast this.
222 *
223 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
224 * small page window employeed by that function. Be careful.
225 * @remark There is no need to assert on the result.
226 */
227#ifdef IN_RC
228# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
229 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
230#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
231# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
232 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
233#else
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
236#endif
237
238/** @def PGM_GCPHYS_2_PTR
239 * Maps a GC physical page address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM handle.
243 * @param GCPhys The GC physical address to map to a virtual one.
244 * @param ppv Where to store the virtual address. No need to cast this.
245 *
246 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
247 * small page window employeed by that function. Be careful.
248 * @remark There is no need to assert on the result.
249 */
250#ifdef IN_RC
251# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
252 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
253#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
254# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
255 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
256#else
257# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
258 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
259#endif
260
261/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
262 * Maps a GC physical page address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pPGM Pointer to the PGM instance data.
266 * @param GCPhys The GC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
274# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
275 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
276#else
277# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
278 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
279#endif
280
281/** @def PGM_GCPHYS_2_PTR_EX
282 * Maps a unaligned GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The VM handle.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
290 * small page window employeed by that function. Be careful.
291 * @remark There is no need to assert on the result.
292 */
293#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
294# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
295 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
296#else
297# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
298 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
299#endif
300
301/** @def PGM_INVL_PG
302 * Invalidates a page.
303 *
304 * @param pVCpu The VMCPU handle.
305 * @param GCVirt The virtual address of the page to invalidate.
306 */
307#ifdef IN_RC
308# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
309#elif defined(IN_RING0)
310# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
311#else
312# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
313#endif
314
315/** @def PGM_INVL_PG_ALL_VCPU
316 * Invalidates a page on all VCPUs
317 *
318 * @param pVM The VM handle.
319 * @param GCVirt The virtual address of the page to invalidate.
320 */
321#ifdef IN_RC
322# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
323#elif defined(IN_RING0)
324# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
325#else
326# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
327#endif
328
329/** @def PGM_INVL_BIG_PG
330 * Invalidates a 4MB page directory entry.
331 *
332 * @param pVCpu The VMCPU handle.
333 * @param GCVirt The virtual address within the page directory to invalidate.
334 */
335#ifdef IN_RC
336# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
337#elif defined(IN_RING0)
338# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
339#else
340# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
341#endif
342
343/** @def PGM_INVL_VCPU_TLBS()
344 * Invalidates the TLBs of the specified VCPU
345 *
346 * @param pVCpu The VMCPU handle.
347 */
348#ifdef IN_RC
349# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
350#elif defined(IN_RING0)
351# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
352#else
353# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
354#endif
355
356/** @def PGM_INVL_ALL_VCPU_TLBS()
357 * Invalidates the TLBs of all VCPUs
358 *
359 * @param pVM The VM handle.
360 */
361#ifdef IN_RC
362# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
363#elif defined(IN_RING0)
364# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
365#else
366# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
367#endif
368
369/** Size of the GCPtrConflict array in PGMMAPPING.
370 * @remarks Must be a power of two. */
371#define PGMMAPPING_CONFLICT_MAX 8
372
373/**
374 * Structure for tracking GC Mappings.
375 *
376 * This structure is used by linked list in both GC and HC.
377 */
378typedef struct PGMMAPPING
379{
380 /** Pointer to next entry. */
381 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
382 /** Pointer to next entry. */
383 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
384 /** Pointer to next entry. */
385 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
386 /** Indicate whether this entry is finalized. */
387 bool fFinalized;
388 /** Start Virtual address. */
389 RTGCPTR GCPtr;
390 /** Last Virtual address (inclusive). */
391 RTGCPTR GCPtrLast;
392 /** Range size (bytes). */
393 RTGCPTR cb;
394 /** Pointer to relocation callback function. */
395 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
396 /** User argument to the callback. */
397 R3PTRTYPE(void *) pvUser;
398 /** Mapping description / name. For easing debugging. */
399 R3PTRTYPE(const char *) pszDesc;
400 /** Last 8 addresses that caused conflicts. */
401 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
402 /** Number of conflicts for this hypervisor mapping. */
403 uint32_t cConflicts;
404 /** Number of page tables. */
405 uint32_t cPTs;
406
407 /** Array of page table mapping data. Each entry
408 * describes one page table. The array can be longer
409 * than the declared length.
410 */
411 struct
412 {
413 /** The HC physical address of the page table. */
414 RTHCPHYS HCPhysPT;
415 /** The HC physical address of the first PAE page table. */
416 RTHCPHYS HCPhysPaePT0;
417 /** The HC physical address of the second PAE page table. */
418 RTHCPHYS HCPhysPaePT1;
419 /** The HC virtual address of the 32-bit page table. */
420 R3PTRTYPE(PX86PT) pPTR3;
421 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
422 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
423 /** The RC virtual address of the 32-bit page table. */
424 RCPTRTYPE(PX86PT) pPTRC;
425 /** The RC virtual address of the two PAE page table. */
426 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
427 /** The R0 virtual address of the 32-bit page table. */
428 R0PTRTYPE(PX86PT) pPTR0;
429 /** The R0 virtual address of the two PAE page table. */
430 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
431 } aPTs[1];
432} PGMMAPPING;
433/** Pointer to structure for tracking GC Mappings. */
434typedef struct PGMMAPPING *PPGMMAPPING;
435
436
437/**
438 * Physical page access handler structure.
439 *
440 * This is used to keep track of physical address ranges
441 * which are being monitored in some kind of way.
442 */
443typedef struct PGMPHYSHANDLER
444{
445 AVLROGCPHYSNODECORE Core;
446 /** Access type. */
447 PGMPHYSHANDLERTYPE enmType;
448 /** Number of pages to update. */
449 uint32_t cPages;
450 /** Pointer to R3 callback function. */
451 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
452 /** User argument for R3 handlers. */
453 R3PTRTYPE(void *) pvUserR3;
454 /** Pointer to R0 callback function. */
455 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
456 /** User argument for R0 handlers. */
457 R0PTRTYPE(void *) pvUserR0;
458 /** Pointer to RC callback function. */
459 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
460 /** User argument for RC handlers. */
461 RCPTRTYPE(void *) pvUserRC;
462 /** Description / Name. For easing debugging. */
463 R3PTRTYPE(const char *) pszDesc;
464#ifdef VBOX_WITH_STATISTICS
465 /** Profiling of this handler. */
466 STAMPROFILE Stat;
467#endif
468} PGMPHYSHANDLER;
469/** Pointer to a physical page access handler structure. */
470typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
471
472
473/**
474 * Cache node for the physical addresses covered by a virtual handler.
475 */
476typedef struct PGMPHYS2VIRTHANDLER
477{
478 /** Core node for the tree based on physical ranges. */
479 AVLROGCPHYSNODECORE Core;
480 /** Offset from this struct to the PGMVIRTHANDLER structure. */
481 int32_t offVirtHandler;
482 /** Offset of the next alias relative to this one.
483 * Bit 0 is used for indicating whether we're in the tree.
484 * Bit 1 is used for indicating that we're the head node.
485 */
486 int32_t offNextAlias;
487} PGMPHYS2VIRTHANDLER;
488/** Pointer to a phys to virtual handler structure. */
489typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
490
491/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
492 * node is in the tree. */
493#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
494/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
495 * node is in the head of an alias chain.
496 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
497#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
498/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
499#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
500
501
502/**
503 * Virtual page access handler structure.
504 *
505 * This is used to keep track of virtual address ranges
506 * which are being monitored in some kind of way.
507 */
508typedef struct PGMVIRTHANDLER
509{
510 /** Core node for the tree based on virtual ranges. */
511 AVLROGCPTRNODECORE Core;
512 /** Size of the range (in bytes). */
513 RTGCPTR cb;
514 /** Number of cache pages. */
515 uint32_t cPages;
516 /** Access type. */
517 PGMVIRTHANDLERTYPE enmType;
518 /** Pointer to the RC callback function. */
519 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
520#if HC_ARCH_BITS == 64
521 RTRCPTR padding;
522#endif
523 /** Pointer to the R3 callback function for invalidation. */
524 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
525 /** Pointer to the R3 callback function. */
526 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
527 /** Description / Name. For easing debugging. */
528 R3PTRTYPE(const char *) pszDesc;
529#ifdef VBOX_WITH_STATISTICS
530 /** Profiling of this handler. */
531 STAMPROFILE Stat;
532#endif
533 /** Array of cached physical addresses for the monitored ranged. */
534 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
535} PGMVIRTHANDLER;
536/** Pointer to a virtual page access handler structure. */
537typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
538
539
540/**
541 * Page type.
542 *
543 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
544 * @remarks This is used in the saved state, so changes to it requires bumping
545 * the saved state version.
546 * @todo So, convert to \#defines!
547 */
548typedef enum PGMPAGETYPE
549{
550 /** The usual invalid zero entry. */
551 PGMPAGETYPE_INVALID = 0,
552 /** RAM page. (RWX) */
553 PGMPAGETYPE_RAM,
554 /** MMIO2 page. (RWX) */
555 PGMPAGETYPE_MMIO2,
556 /** MMIO2 page aliased over an MMIO page. (RWX)
557 * See PGMHandlerPhysicalPageAlias(). */
558 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
559 /** Shadowed ROM. (RWX) */
560 PGMPAGETYPE_ROM_SHADOW,
561 /** ROM page. (R-X) */
562 PGMPAGETYPE_ROM,
563 /** MMIO page. (---) */
564 PGMPAGETYPE_MMIO,
565 /** End of valid entries. */
566 PGMPAGETYPE_END
567} PGMPAGETYPE;
568AssertCompile(PGMPAGETYPE_END <= 7);
569
570/** @name Page type predicates.
571 * @{ */
572#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
573#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
574#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
575#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
576#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
577/** @} */
578
579
580/**
581 * A Physical Guest Page tracking structure.
582 *
583 * The format of this structure is complicated because we have to fit a lot
584 * of information into as few bits as possible. The format is also subject
585 * to change (there is one comming up soon). Which means that for we'll be
586 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
587 * accesses to the structure.
588 */
589typedef struct PGMPAGE
590{
591 /** The physical address and the Page ID. */
592 RTHCPHYS HCPhysAndPageID;
593 /** Combination of:
594 * - [0-7]: u2HandlerPhysStateY - the physical handler state
595 * (PGM_PAGE_HNDL_PHYS_STATE_*).
596 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
597 * (PGM_PAGE_HNDL_VIRT_STATE_*).
598 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
599 * - [15]: fWrittenToY - flag indicating that a write monitored page was
600 * written to when set.
601 * - [10-13]: 4 unused bits.
602 * @remarks Warning! All accesses to the bits are hardcoded.
603 *
604 * @todo Change this to a union with both bitfields, u8 and u accessors.
605 * That'll help deal with some of the hardcoded accesses.
606 *
607 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
608 * will make it possible to turn some of the 16-bit accesses into
609 * 32-bit ones, which may be efficient (stalls).
610 */
611 RTUINT16U u16MiscY;
612 /** The page state.
613 * Only 3 bits are really needed for this. */
614 uint16_t uStateY : 3;
615 /** The page type (PGMPAGETYPE).
616 * Only 3 bits are really needed for this. */
617 uint16_t uTypeY : 3;
618 /** PTE index for usage tracking (page pool). */
619 uint16_t uPteIdx : 10;
620 /** Usage tracking (page pool). */
621 uint16_t u16TrackingY;
622 /** The number of read locks on this page. */
623 uint8_t cReadLocksY;
624 /** The number of write locks on this page. */
625 uint8_t cWriteLocksY;
626} PGMPAGE;
627AssertCompileSize(PGMPAGE, 16);
628/** Pointer to a physical guest page. */
629typedef PGMPAGE *PPGMPAGE;
630/** Pointer to a const physical guest page. */
631typedef const PGMPAGE *PCPGMPAGE;
632/** Pointer to a physical guest page pointer. */
633typedef PPGMPAGE *PPPGMPAGE;
634
635
636/**
637 * Clears the page structure.
638 * @param pPage Pointer to the physical guest page tracking structure.
639 */
640#define PGM_PAGE_CLEAR(pPage) \
641 do { \
642 (pPage)->HCPhysAndPageID = 0; \
643 (pPage)->uStateY = 0; \
644 (pPage)->uTypeY = 0; \
645 (pPage)->uPteIdx = 0; \
646 (pPage)->u16MiscY.u = 0; \
647 (pPage)->u16TrackingY = 0; \
648 (pPage)->cReadLocksY = 0; \
649 (pPage)->cWriteLocksY = 0; \
650 } while (0)
651
652/**
653 * Initializes the page structure.
654 * @param pPage Pointer to the physical guest page tracking structure.
655 */
656#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
657 do { \
658 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
659 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
660 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
661 (pPage)->uStateY = (_uState); \
662 (pPage)->uTypeY = (_uType); \
663 (pPage)->uPteIdx = 0; \
664 (pPage)->u16MiscY.u = 0; \
665 (pPage)->u16TrackingY = 0; \
666 (pPage)->cReadLocksY = 0; \
667 (pPage)->cWriteLocksY = 0; \
668 } while (0)
669
670/**
671 * Initializes the page structure of a ZERO page.
672 * @param pPage Pointer to the physical guest page tracking structure.
673 * @param pVM The VM handle (for getting the zero page address).
674 * @param uType The page type (PGMPAGETYPE).
675 */
676#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
677 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
678
679
680/** @name The Page state, PGMPAGE::uStateY.
681 * @{ */
682/** The zero page.
683 * This is a per-VM page that's never ever mapped writable. */
684#define PGM_PAGE_STATE_ZERO 0
685/** A allocated page.
686 * This is a per-VM page allocated from the page pool (or wherever
687 * we get MMIO2 pages from if the type is MMIO2).
688 */
689#define PGM_PAGE_STATE_ALLOCATED 1
690/** A allocated page that's being monitored for writes.
691 * The shadow page table mappings are read-only. When a write occurs, the
692 * fWrittenTo member is set, the page remapped as read-write and the state
693 * moved back to allocated. */
694#define PGM_PAGE_STATE_WRITE_MONITORED 2
695/** The page is shared, aka. copy-on-write.
696 * This is a page that's shared with other VMs. */
697#define PGM_PAGE_STATE_SHARED 3
698/** The page is ballooned, so no longer available for this VM. */
699#define PGM_PAGE_STATE_BALLOONED 4
700/** @} */
701
702
703/**
704 * Gets the page state.
705 * @returns page state (PGM_PAGE_STATE_*).
706 * @param pPage Pointer to the physical guest page tracking structure.
707 */
708#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
709
710/**
711 * Sets the page state.
712 * @param pPage Pointer to the physical guest page tracking structure.
713 * @param _uState The new page state.
714 */
715#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
716
717
718/**
719 * Gets the host physical address of the guest page.
720 * @returns host physical address (RTHCPHYS).
721 * @param pPage Pointer to the physical guest page tracking structure.
722 */
723#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
724
725/**
726 * Sets the host physical address of the guest page.
727 * @param pPage Pointer to the physical guest page tracking structure.
728 * @param _HCPhys The new host physical address.
729 */
730#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
731 do { \
732 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
733 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
734 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
735 | (SetHCPhysTmp << (28-12)); \
736 } while (0)
737
738/**
739 * Get the Page ID.
740 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
744
745/**
746 * Sets the Page ID.
747 * @param pPage Pointer to the physical guest page tracking structure.
748 */
749#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
750 do { \
751 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
752 | ((_idPage) & UINT32_C(0x0fffffff)); \
753 } while (0)
754
755/**
756 * Get the Chunk ID.
757 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
758 * @param pPage Pointer to the physical guest page tracking structure.
759 */
760#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
761
762/**
763 * Get the index of the page within the allocation chunk.
764 * @returns The page index.
765 * @param pPage Pointer to the physical guest page tracking structure.
766 */
767#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
768
769/**
770 * Gets the page type.
771 * @returns The page type.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
775
776/**
777 * Sets the page type.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 * @param _enmType The new page type (PGMPAGETYPE).
780 */
781#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
782
783/**
784 * Gets the page table index
785 * @returns The page table index.
786 * @param pPage Pointer to the physical guest page tracking structure.
787 */
788#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
789
790/**
791 * Sets the page table index
792 * @param pPage Pointer to the physical guest page tracking structure.
793 * @param iPte New page table index.
794 */
795#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
796
797/**
798 * Checks if the page is marked for MMIO.
799 * @returns true/false.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 */
802#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
803
804/**
805 * Checks if the page is backed by the ZERO page.
806 * @returns true/false.
807 * @param pPage Pointer to the physical guest page tracking structure.
808 */
809#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
810
811/**
812 * Checks if the page is backed by a SHARED page.
813 * @returns true/false.
814 * @param pPage Pointer to the physical guest page tracking structure.
815 */
816#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
817
818/**
819 * Checks if the page is ballooned.
820 * @returns true/false.
821 * @param pPage Pointer to the physical guest page tracking structure.
822 */
823#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
824
825/**
826 * Marks the page as written to (for GMM change monitoring).
827 * @param pPage Pointer to the physical guest page tracking structure.
828 */
829#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
830
831/**
832 * Clears the written-to indicator.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
836
837/**
838 * Checks if the page was marked as written-to.
839 * @returns true/false.
840 * @param pPage Pointer to the physical guest page tracking structure.
841 */
842#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
843
844/** @name PT usage values (PGMPAGE::u2PDEType).
845 *
846 * @{ */
847/** Either as a PT or PDE. */
848#define PGM_PAGE_PDE_TYPE_DONTCARE 0
849/** Must use a page table to map the range. */
850#define PGM_PAGE_PDE_TYPE_PT 1
851/** Can use a page directory entry to map the continous range. */
852#define PGM_PAGE_PDE_TYPE_PDE 2
853/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
854#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
855/** @} */
856
857/**
858 * Set the PDE type of the page
859 * @param pPage Pointer to the physical guest page tracking structure.
860 * @param uType PGM_PAGE_PDE_TYPE_*
861 */
862#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
863 do { \
864 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
865 | (((uType) & UINT8_C(0x03)) << 5); \
866 } while (0)
867
868/**
869 * Checks if the page was marked being part of a large page
870 * @returns true/false.
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
874
875/** Enabled optimized access handler tests.
876 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
877 * layout. When enabled, the compiler should normally generate more compact
878 * code.
879 */
880#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
881
882/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
883 *
884 * @remarks The values are assigned in order of priority, so we can calculate
885 * the correct state for a page with different handlers installed.
886 * @{ */
887/** No handler installed. */
888#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
889/** Monitoring is temporarily disabled. */
890#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
891/** Write access is monitored. */
892#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
893/** All access is monitored. */
894#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
895/** @} */
896
897/**
898 * Gets the physical access handler state of a page.
899 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
900 * @param pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
903 ( (pPage)->u16MiscY.au8[0] )
904
905/**
906 * Sets the physical access handler state of a page.
907 * @param pPage Pointer to the physical guest page tracking structure.
908 * @param _uState The new state value.
909 */
910#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
911 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
912
913/**
914 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
915 * @returns true/false
916 * @param pPage Pointer to the physical guest page tracking structure.
917 */
918#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
919 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
920
921/**
922 * Checks if the page has any active physical access handlers.
923 * @returns true/false
924 * @param pPage Pointer to the physical guest page tracking structure.
925 */
926#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
927 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
928
929
930/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
931 *
932 * @remarks The values are assigned in order of priority, so we can calculate
933 * the correct state for a page with different handlers installed.
934 * @{ */
935/** No handler installed. */
936#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
937/* 1 is reserved so the lineup is identical with the physical ones. */
938/** Write access is monitored. */
939#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
940/** All access is monitored. */
941#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
942/** @} */
943
944/**
945 * Gets the virtual access handler state of a page.
946 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
947 * @param pPage Pointer to the physical guest page tracking structure.
948 */
949#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
950
951/**
952 * Sets the virtual access handler state of a page.
953 * @param pPage Pointer to the physical guest page tracking structure.
954 * @param _uState The new state value.
955 */
956#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
957 do { \
958 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
959 | ((_uState) & UINT8_C(0x03)); \
960 } while (0)
961
962/**
963 * Checks if the page has any virtual access handlers.
964 * @returns true/false
965 * @param pPage Pointer to the physical guest page tracking structure.
966 */
967#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
968 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
969
970/**
971 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
972 * virtual handlers.
973 * @returns true/false
974 * @param pPage Pointer to the physical guest page tracking structure.
975 */
976#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
977 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
978
979
980/**
981 * Checks if the page has any access handlers, including temporarily disabled ones.
982 * @returns true/false
983 * @param pPage Pointer to the physical guest page tracking structure.
984 */
985#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
986# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
987 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
988#else
989# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
990 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
991 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
992#endif
993
994/**
995 * Checks if the page has any active access handlers.
996 * @returns true/false
997 * @param pPage Pointer to the physical guest page tracking structure.
998 */
999#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1000# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1001 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1002#else
1003# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1004 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1005 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1006#endif
1007
1008/**
1009 * Checks if the page has any active access handlers catching all accesses.
1010 * @returns true/false
1011 * @param pPage Pointer to the physical guest page tracking structure.
1012 */
1013#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1014# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1015 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1016 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1017#else
1018# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1019 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1020 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1021#endif
1022
1023
1024/** @def PGM_PAGE_GET_TRACKING
1025 * Gets the packed shadow page pool tracking data associated with a guest page.
1026 * @returns uint16_t containing the data.
1027 * @param pPage Pointer to the physical guest page tracking structure.
1028 */
1029#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1030
1031/** @def PGM_PAGE_SET_TRACKING
1032 * Sets the packed shadow page pool tracking data associated with a guest page.
1033 * @param pPage Pointer to the physical guest page tracking structure.
1034 * @param u16TrackingData The tracking data to store.
1035 */
1036#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1037 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1038
1039/** @def PGM_PAGE_GET_TD_CREFS
1040 * Gets the @a cRefs tracking data member.
1041 * @returns cRefs.
1042 * @param pPage Pointer to the physical guest page tracking structure.
1043 */
1044#define PGM_PAGE_GET_TD_CREFS(pPage) \
1045 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1046
1047/** @def PGM_PAGE_GET_TD_IDX
1048 * Gets the @a idx tracking data member.
1049 * @returns idx.
1050 * @param pPage Pointer to the physical guest page tracking structure.
1051 */
1052#define PGM_PAGE_GET_TD_IDX(pPage) \
1053 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1054
1055
1056/** Max number of locks on a page. */
1057#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1058
1059/** Get the read lock count.
1060 * @returns count.
1061 * @param pPage Pointer to the physical guest page tracking structure.
1062 */
1063#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1064
1065/** Get the write lock count.
1066 * @returns count.
1067 * @param pPage Pointer to the physical guest page tracking structure.
1068 */
1069#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1070
1071/** Decrement the read lock counter.
1072 * @param pPage Pointer to the physical guest page tracking structure.
1073 */
1074#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1075
1076/** Decrement the write lock counter.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1080
1081/** Increment the read lock counter.
1082 * @param pPage Pointer to the physical guest page tracking structure.
1083 */
1084#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1085
1086/** Increment the write lock counter.
1087 * @param pPage Pointer to the physical guest page tracking structure.
1088 */
1089#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1090
1091
1092#if 0
1093/** Enables sanity checking of write monitoring using CRC-32. */
1094# define PGMLIVESAVERAMPAGE_WITH_CRC32
1095#endif
1096
1097/**
1098 * Per page live save tracking data.
1099 */
1100typedef struct PGMLIVESAVERAMPAGE
1101{
1102 /** Number of times it has been dirtied. */
1103 uint32_t cDirtied : 24;
1104 /** Whether it is currently dirty. */
1105 uint32_t fDirty : 1;
1106 /** Ignore the page.
1107 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1108 * deal with these after pausing the VM and DevPCI have said it bit about
1109 * remappings. */
1110 uint32_t fIgnore : 1;
1111 /** Was a ZERO page last time around. */
1112 uint32_t fZero : 1;
1113 /** Was a SHARED page last time around. */
1114 uint32_t fShared : 1;
1115 /** Whether the page is/was write monitored in a previous pass. */
1116 uint32_t fWriteMonitored : 1;
1117 /** Whether the page is/was write monitored earlier in this pass. */
1118 uint32_t fWriteMonitoredJustNow : 1;
1119 /** Bits reserved for future use. */
1120 uint32_t u2Reserved : 2;
1121#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1122 /** CRC-32 for the page. This is for internal consistency checks. */
1123 uint32_t u32Crc;
1124#endif
1125} PGMLIVESAVERAMPAGE;
1126#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1127AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1128#else
1129AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1130#endif
1131/** Pointer to the per page live save tracking data. */
1132typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1133
1134/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1135#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1136
1137
1138/**
1139 * Ram range for GC Phys to HC Phys conversion.
1140 *
1141 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1142 * conversions too, but we'll let MM handle that for now.
1143 *
1144 * This structure is used by linked lists in both GC and HC.
1145 */
1146typedef struct PGMRAMRANGE
1147{
1148 /** Start of the range. Page aligned. */
1149 RTGCPHYS GCPhys;
1150 /** Size of the range. (Page aligned of course). */
1151 RTGCPHYS cb;
1152 /** Pointer to the next RAM range - for R3. */
1153 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1154 /** Pointer to the next RAM range - for R0. */
1155 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1156 /** Pointer to the next RAM range - for RC. */
1157 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1158 /** PGM_RAM_RANGE_FLAGS_* flags. */
1159 uint32_t fFlags;
1160 /** Last address in the range (inclusive). Page aligned (-1). */
1161 RTGCPHYS GCPhysLast;
1162 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1163 R3PTRTYPE(void *) pvR3;
1164 /** Live save per page tracking data. */
1165 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1166 /** The range description. */
1167 R3PTRTYPE(const char *) pszDesc;
1168 /** Pointer to self - R0 pointer. */
1169 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1170 /** Pointer to self - RC pointer. */
1171 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1172 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1173 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1174 /** Array of physical guest page tracking structures. */
1175 PGMPAGE aPages[1];
1176} PGMRAMRANGE;
1177/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1178typedef PGMRAMRANGE *PPGMRAMRANGE;
1179
1180/** @name PGMRAMRANGE::fFlags
1181 * @{ */
1182/** The RAM range is floating around as an independent guest mapping. */
1183#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1184/** Ad hoc RAM range for an ROM mapping. */
1185#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1186/** Ad hoc RAM range for an MMIO mapping. */
1187#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1188/** Ad hoc RAM range for an MMIO2 mapping. */
1189#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1190/** @} */
1191
1192/** Tests if a RAM range is an ad hoc one or not.
1193 * @returns true/false.
1194 * @param pRam The RAM range.
1195 */
1196#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1197 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1198
1199
1200/**
1201 * Per page tracking structure for ROM image.
1202 *
1203 * A ROM image may have a shadow page, in which case we may have two pages
1204 * backing it. This structure contains the PGMPAGE for both while
1205 * PGMRAMRANGE have a copy of the active one. It is important that these
1206 * aren't out of sync in any regard other than page pool tracking data.
1207 */
1208typedef struct PGMROMPAGE
1209{
1210 /** The page structure for the virgin ROM page. */
1211 PGMPAGE Virgin;
1212 /** The page structure for the shadow RAM page. */
1213 PGMPAGE Shadow;
1214 /** The current protection setting. */
1215 PGMROMPROT enmProt;
1216 /** Live save status information. Makes use of unused alignment space. */
1217 struct
1218 {
1219 /** The previous protection value. */
1220 uint8_t u8Prot;
1221 /** Written to flag set by the handler. */
1222 bool fWrittenTo;
1223 /** Whether the shadow page is dirty or not. */
1224 bool fDirty;
1225 /** Whether it was dirtied in the recently. */
1226 bool fDirtiedRecently;
1227 } LiveSave;
1228} PGMROMPAGE;
1229AssertCompileSizeAlignment(PGMROMPAGE, 8);
1230/** Pointer to a ROM page tracking structure. */
1231typedef PGMROMPAGE *PPGMROMPAGE;
1232
1233
1234/**
1235 * A registered ROM image.
1236 *
1237 * This is needed to keep track of ROM image since they generally intrude
1238 * into a PGMRAMRANGE. It also keeps track of additional info like the
1239 * two page sets (read-only virgin and read-write shadow), the current
1240 * state of each page.
1241 *
1242 * Because access handlers cannot easily be executed in a different
1243 * context, the ROM ranges needs to be accessible and in all contexts.
1244 */
1245typedef struct PGMROMRANGE
1246{
1247 /** Pointer to the next range - R3. */
1248 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1249 /** Pointer to the next range - R0. */
1250 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1251 /** Pointer to the next range - RC. */
1252 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1253 /** Pointer alignment */
1254 RTRCPTR RCPtrAlignment;
1255 /** Address of the range. */
1256 RTGCPHYS GCPhys;
1257 /** Address of the last byte in the range. */
1258 RTGCPHYS GCPhysLast;
1259 /** Size of the range. */
1260 RTGCPHYS cb;
1261 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1262 uint32_t fFlags;
1263 /** The saved state range ID. */
1264 uint8_t idSavedState;
1265 /** Alignment padding. */
1266 uint8_t au8Alignment[3];
1267 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1268 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1269 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1270 * This is used for strictness checks. */
1271 R3PTRTYPE(const void *) pvOriginal;
1272 /** The ROM description. */
1273 R3PTRTYPE(const char *) pszDesc;
1274 /** The per page tracking structures. */
1275 PGMROMPAGE aPages[1];
1276} PGMROMRANGE;
1277/** Pointer to a ROM range. */
1278typedef PGMROMRANGE *PPGMROMRANGE;
1279
1280
1281/**
1282 * Live save per page data for an MMIO2 page.
1283 *
1284 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1285 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1286 * CRC-32 for detecting changes as well as special handling of zero pages. This
1287 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1288 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1289 * because of speed (2.5x and 6x slower).)
1290 *
1291 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1292 * save but normally is disabled. Since we can write monitore guest
1293 * accesses on our own, we only need this for host accesses. Shouldn't be
1294 * too difficult for DevVGA, VMMDev might be doable, the planned
1295 * networking fun will be fun since it involves ring-0.
1296 */
1297typedef struct PGMLIVESAVEMMIO2PAGE
1298{
1299 /** Set if the page is considered dirty. */
1300 bool fDirty;
1301 /** The number of scans this page has remained unchanged for.
1302 * Only updated for dirty pages. */
1303 uint8_t cUnchangedScans;
1304 /** Whether this page was zero at the last scan. */
1305 bool fZero;
1306 /** Alignment padding. */
1307 bool fReserved;
1308 /** CRC-32 for the first half of the page.
1309 * This is used together with u32CrcH2 to quickly detect changes in the page
1310 * during the non-final passes. */
1311 uint32_t u32CrcH1;
1312 /** CRC-32 for the second half of the page. */
1313 uint32_t u32CrcH2;
1314 /** SHA-1 for the saved page.
1315 * This is used in the final pass to skip pages without changes. */
1316 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1317} PGMLIVESAVEMMIO2PAGE;
1318/** Pointer to a live save status data for an MMIO2 page. */
1319typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1320
1321/**
1322 * A registered MMIO2 (= Device RAM) range.
1323 *
1324 * There are a few reason why we need to keep track of these
1325 * registrations. One of them is the deregistration & cleanup stuff,
1326 * while another is that the PGMRAMRANGE associated with such a region may
1327 * have to be removed from the ram range list.
1328 *
1329 * Overlapping with a RAM range has to be 100% or none at all. The pages
1330 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1331 * will be raised if a partial overlap or an overlap of ROM pages is
1332 * encountered. On an overlap we will free all the existing RAM pages and
1333 * put in the ram range pages instead.
1334 */
1335typedef struct PGMMMIO2RANGE
1336{
1337 /** The owner of the range. (a device) */
1338 PPDMDEVINSR3 pDevInsR3;
1339 /** Pointer to the ring-3 mapping of the allocation. */
1340 RTR3PTR pvR3;
1341 /** Pointer to the next range - R3. */
1342 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1343 /** Whether it's mapped or not. */
1344 bool fMapped;
1345 /** Whether it's overlapping or not. */
1346 bool fOverlapping;
1347 /** The PCI region number.
1348 * @remarks This ASSUMES that nobody will ever really need to have multiple
1349 * PCI devices with matching MMIO region numbers on a single device. */
1350 uint8_t iRegion;
1351 /** The saved state range ID. */
1352 uint8_t idSavedState;
1353 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1354 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1355 /** Live save per page tracking data. */
1356 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1357 /** The associated RAM range. */
1358 PGMRAMRANGE RamRange;
1359} PGMMMIO2RANGE;
1360/** Pointer to a MMIO2 range. */
1361typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1362
1363
1364
1365
1366/**
1367 * PGMPhysRead/Write cache entry
1368 */
1369typedef struct PGMPHYSCACHEENTRY
1370{
1371 /** R3 pointer to physical page. */
1372 R3PTRTYPE(uint8_t *) pbR3;
1373 /** GC Physical address for cache entry */
1374 RTGCPHYS GCPhys;
1375#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1376 RTGCPHYS u32Padding0; /**< alignment padding. */
1377#endif
1378} PGMPHYSCACHEENTRY;
1379
1380/**
1381 * PGMPhysRead/Write cache to reduce REM memory access overhead
1382 */
1383typedef struct PGMPHYSCACHE
1384{
1385 /** Bitmap of valid cache entries */
1386 uint64_t aEntries;
1387 /** Cache entries */
1388 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1389} PGMPHYSCACHE;
1390
1391
1392/** Pointer to an allocation chunk ring-3 mapping. */
1393typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1394/** Pointer to an allocation chunk ring-3 mapping pointer. */
1395typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1396
1397/**
1398 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1399 *
1400 * The primary tree (Core) uses the chunk id as key.
1401 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1402 */
1403typedef struct PGMCHUNKR3MAP
1404{
1405 /** The key is the chunk id. */
1406 AVLU32NODECORE Core;
1407 /** The key is the ageing sequence number. */
1408 AVLLU32NODECORE AgeCore;
1409 /** The current age thingy. */
1410 uint32_t iAge;
1411 /** The current reference count. */
1412 uint32_t volatile cRefs;
1413 /** The current permanent reference count. */
1414 uint32_t volatile cPermRefs;
1415 /** The mapping address. */
1416 void *pv;
1417} PGMCHUNKR3MAP;
1418
1419/**
1420 * Allocation chunk ring-3 mapping TLB entry.
1421 */
1422typedef struct PGMCHUNKR3MAPTLBE
1423{
1424 /** The chunk id. */
1425 uint32_t volatile idChunk;
1426#if HC_ARCH_BITS == 64
1427 uint32_t u32Padding; /**< alignment padding. */
1428#endif
1429 /** The chunk map. */
1430#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1431 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1432#else
1433 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1434#endif
1435} PGMCHUNKR3MAPTLBE;
1436/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1437typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1438
1439/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1440 * @remark Must be a power of two value. */
1441#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1442
1443/**
1444 * Allocation chunk ring-3 mapping TLB.
1445 *
1446 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1447 * At first glance this might look kinda odd since AVL trees are
1448 * supposed to give the most optimial lookup times of all trees
1449 * due to their balancing. However, take a tree with 1023 nodes
1450 * in it, that's 10 levels, meaning that most searches has to go
1451 * down 9 levels before they find what they want. This isn't fast
1452 * compared to a TLB hit. There is the factor of cache misses,
1453 * and of course the problem with trees and branch prediction.
1454 * This is why we use TLBs in front of most of the trees.
1455 *
1456 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1457 * difficult when we switch to the new inlined AVL trees (from kStuff).
1458 */
1459typedef struct PGMCHUNKR3MAPTLB
1460{
1461 /** The TLB entries. */
1462 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1463} PGMCHUNKR3MAPTLB;
1464
1465/**
1466 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1467 * @returns Chunk TLB index.
1468 * @param idChunk The Chunk ID.
1469 */
1470#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1471
1472
1473/**
1474 * Ring-3 guest page mapping TLB entry.
1475 * @remarks used in ring-0 as well at the moment.
1476 */
1477typedef struct PGMPAGER3MAPTLBE
1478{
1479 /** Address of the page. */
1480 RTGCPHYS volatile GCPhys;
1481 /** The guest page. */
1482#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1483 R3PTRTYPE(PPGMPAGE) volatile pPage;
1484#else
1485 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1486#endif
1487 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1488#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1489 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1490#else
1491 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1492#endif
1493 /** The address */
1494#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1495 R3PTRTYPE(void *) volatile pv;
1496#else
1497 R3R0PTRTYPE(void *) volatile pv;
1498#endif
1499#if HC_ARCH_BITS == 32
1500 uint32_t u32Padding; /**< alignment padding. */
1501#endif
1502} PGMPAGER3MAPTLBE;
1503/** Pointer to an entry in the HC physical TLB. */
1504typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1505
1506
1507/** The number of entries in the ring-3 guest page mapping TLB.
1508 * @remarks The value must be a power of two. */
1509#define PGM_PAGER3MAPTLB_ENTRIES 256
1510
1511/**
1512 * Ring-3 guest page mapping TLB.
1513 * @remarks used in ring-0 as well at the moment.
1514 */
1515typedef struct PGMPAGER3MAPTLB
1516{
1517 /** The TLB entries. */
1518 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1519} PGMPAGER3MAPTLB;
1520/** Pointer to the ring-3 guest page mapping TLB. */
1521typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1522
1523/**
1524 * Calculates the index of the TLB entry for the specified guest page.
1525 * @returns Physical TLB index.
1526 * @param GCPhys The guest physical address.
1527 */
1528#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1529
1530
1531/**
1532 * Mapping cache usage set entry.
1533 *
1534 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1535 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1536 * cache. If it's extended to include ring-3, well, then something will
1537 * have be changed here...
1538 */
1539typedef struct PGMMAPSETENTRY
1540{
1541 /** The mapping cache index. */
1542 uint16_t iPage;
1543 /** The number of references.
1544 * The max is UINT16_MAX - 1. */
1545 uint16_t cRefs;
1546#if HC_ARCH_BITS == 64
1547 uint32_t alignment;
1548#endif
1549 /** Pointer to the page. */
1550 RTR0PTR pvPage;
1551 /** The physical address for this entry. */
1552 RTHCPHYS HCPhys;
1553} PGMMAPSETENTRY;
1554/** Pointer to a mapping cache usage set entry. */
1555typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1556
1557/**
1558 * Mapping cache usage set.
1559 *
1560 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1561 * done during exits / traps. The set is
1562 */
1563typedef struct PGMMAPSET
1564{
1565 /** The number of occupied entries.
1566 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1567 * dynamic mappings. */
1568 uint32_t cEntries;
1569 /** The start of the current subset.
1570 * This is UINT32_MAX if no subset is currently open. */
1571 uint32_t iSubset;
1572 /** The index of the current CPU, only valid if the set is open. */
1573 int32_t iCpu;
1574 uint32_t alignment;
1575 /** The entries. */
1576 PGMMAPSETENTRY aEntries[64];
1577 /** HCPhys -> iEntry fast lookup table.
1578 * Use PGMMAPSET_HASH for hashing.
1579 * The entries may or may not be valid, check against cEntries. */
1580 uint8_t aiHashTable[128];
1581} PGMMAPSET;
1582AssertCompileSizeAlignment(PGMMAPSET, 8);
1583/** Pointer to the mapping cache set. */
1584typedef PGMMAPSET *PPGMMAPSET;
1585
1586/** PGMMAPSET::cEntries value for a closed set. */
1587#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1588
1589/** Hash function for aiHashTable. */
1590#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1591
1592/** The max fill size (strict builds). */
1593#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1594
1595
1596/** @name Context neutrual page mapper TLB.
1597 *
1598 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1599 * code is writting in a kind of context neutrual way. Time will show whether
1600 * this actually makes sense or not...
1601 *
1602 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1603 * context ends up using a global mapping cache on some platforms
1604 * (darwin).
1605 *
1606 * @{ */
1607/** @typedef PPGMPAGEMAPTLB
1608 * The page mapper TLB pointer type for the current context. */
1609/** @typedef PPGMPAGEMAPTLB
1610 * The page mapper TLB entry pointer type for the current context. */
1611/** @typedef PPGMPAGEMAPTLB
1612 * The page mapper TLB entry pointer pointer type for the current context. */
1613/** @def PGM_PAGEMAPTLB_ENTRIES
1614 * The number of TLB entries in the page mapper TLB for the current context. */
1615/** @def PGM_PAGEMAPTLB_IDX
1616 * Calculate the TLB index for a guest physical address.
1617 * @returns The TLB index.
1618 * @param GCPhys The guest physical address. */
1619/** @typedef PPGMPAGEMAP
1620 * Pointer to a page mapper unit for current context. */
1621/** @typedef PPPGMPAGEMAP
1622 * Pointer to a page mapper unit pointer for current context. */
1623#ifdef IN_RC
1624// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1625// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1626// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1627# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1628# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1629 typedef void * PPGMPAGEMAP;
1630 typedef void ** PPPGMPAGEMAP;
1631//#elif IN_RING0
1632// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1633// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1634// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1635//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1636//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1637// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1638// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1639#else
1640 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1641 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1642 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1643# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1644# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1645 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1646 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1647#endif
1648/** @} */
1649
1650
1651/** @name PGM Pool Indexes.
1652 * Aka. the unique shadow page identifier.
1653 * @{ */
1654/** NIL page pool IDX. */
1655#define NIL_PGMPOOL_IDX 0
1656/** The first normal index. */
1657#define PGMPOOL_IDX_FIRST_SPECIAL 1
1658/** Page directory (32-bit root). */
1659#define PGMPOOL_IDX_PD 1
1660/** Page Directory Pointer Table (PAE root). */
1661#define PGMPOOL_IDX_PDPT 2
1662/** AMD64 CR3 level index.*/
1663#define PGMPOOL_IDX_AMD64_CR3 3
1664/** Nested paging root.*/
1665#define PGMPOOL_IDX_NESTED_ROOT 4
1666/** The first normal index. */
1667#define PGMPOOL_IDX_FIRST 5
1668/** The last valid index. (inclusive, 14 bits) */
1669#define PGMPOOL_IDX_LAST 0x3fff
1670/** @} */
1671
1672/** The NIL index for the parent chain. */
1673#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1674#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1675
1676/**
1677 * Node in the chain linking a shadowed page to it's parent (user).
1678 */
1679#pragma pack(1)
1680typedef struct PGMPOOLUSER
1681{
1682 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1683 uint16_t iNext;
1684 /** The user page index. */
1685 uint16_t iUser;
1686 /** Index into the user table. */
1687 uint32_t iUserTable;
1688} PGMPOOLUSER, *PPGMPOOLUSER;
1689typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1690#pragma pack()
1691
1692
1693/** The NIL index for the phys ext chain. */
1694#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1695/** The NIL pte index for a phys ext chain slot. */
1696#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1697
1698/**
1699 * Node in the chain of physical cross reference extents.
1700 * @todo Calling this an 'extent' is not quite right, find a better name.
1701 * @todo find out the optimal size of the aidx array
1702 */
1703#pragma pack(1)
1704typedef struct PGMPOOLPHYSEXT
1705{
1706 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1707 uint16_t iNext;
1708 /** Alignment. */
1709 uint16_t u16Align;
1710 /** The user page index. */
1711 uint16_t aidx[3];
1712 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1713 uint16_t apte[3];
1714} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1715typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1716#pragma pack()
1717
1718
1719/**
1720 * The kind of page that's being shadowed.
1721 */
1722typedef enum PGMPOOLKIND
1723{
1724 /** The virtual invalid 0 entry. */
1725 PGMPOOLKIND_INVALID = 0,
1726 /** The entry is free (=unused). */
1727 PGMPOOLKIND_FREE,
1728
1729 /** Shw: 32-bit page table; Gst: no paging */
1730 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1731 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1732 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1733 /** Shw: 32-bit page table; Gst: 4MB page. */
1734 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1735 /** Shw: PAE page table; Gst: no paging */
1736 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1737 /** Shw: PAE page table; Gst: 32-bit page table. */
1738 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1739 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1740 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1741 /** Shw: PAE page table; Gst: PAE page table. */
1742 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1743 /** Shw: PAE page table; Gst: 2MB page. */
1744 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1745
1746 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1747 PGMPOOLKIND_32BIT_PD,
1748 /** Shw: 32-bit page directory. Gst: no paging. */
1749 PGMPOOLKIND_32BIT_PD_PHYS,
1750 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1751 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1752 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1753 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1754 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1755 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1756 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1757 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1758 /** Shw: PAE page directory; Gst: PAE page directory. */
1759 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1760 /** Shw: PAE page directory; Gst: no paging. */
1761 PGMPOOLKIND_PAE_PD_PHYS,
1762
1763 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1764 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1765 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1766 PGMPOOLKIND_PAE_PDPT,
1767 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1768 PGMPOOLKIND_PAE_PDPT_PHYS,
1769
1770 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1771 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1772 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1773 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1774 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1775 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1776 /** Shw: 64-bit page directory table; Gst: no paging */
1777 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1778
1779 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1780 PGMPOOLKIND_64BIT_PML4,
1781
1782 /** Shw: EPT page directory pointer table; Gst: no paging */
1783 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1784 /** Shw: EPT page directory table; Gst: no paging */
1785 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1786 /** Shw: EPT page table; Gst: no paging */
1787 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1788
1789 /** Shw: Root Nested paging table. */
1790 PGMPOOLKIND_ROOT_NESTED,
1791
1792 /** The last valid entry. */
1793 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1794} PGMPOOLKIND;
1795
1796/**
1797 * The access attributes of the page; only applies to big pages.
1798 */
1799typedef enum
1800{
1801 PGMPOOLACCESS_DONTCARE = 0,
1802 PGMPOOLACCESS_USER_RW,
1803 PGMPOOLACCESS_USER_R,
1804 PGMPOOLACCESS_USER_RW_NX,
1805 PGMPOOLACCESS_USER_R_NX,
1806 PGMPOOLACCESS_SUPERVISOR_RW,
1807 PGMPOOLACCESS_SUPERVISOR_R,
1808 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1809 PGMPOOLACCESS_SUPERVISOR_R_NX
1810} PGMPOOLACCESS;
1811
1812/**
1813 * The tracking data for a page in the pool.
1814 */
1815typedef struct PGMPOOLPAGE
1816{
1817 /** AVL node code with the (R3) physical address of this page. */
1818 AVLOHCPHYSNODECORE Core;
1819 /** Pointer to the R3 mapping of the page. */
1820#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1821 R3PTRTYPE(void *) pvPageR3;
1822#else
1823 R3R0PTRTYPE(void *) pvPageR3;
1824#endif
1825 /** The guest physical address. */
1826#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1827 uint32_t Alignment0;
1828#endif
1829 RTGCPHYS GCPhys;
1830
1831 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1832 RTGCPTR pvLastAccessHandlerRip;
1833 RTGCPTR pvLastAccessHandlerFault;
1834 uint64_t cLastAccessHandlerCount;
1835
1836 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1837 uint8_t enmKind;
1838 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1839 uint8_t enmAccess;
1840 /** The index of this page. */
1841 uint16_t idx;
1842 /** The next entry in the list this page currently resides in.
1843 * It's either in the free list or in the GCPhys hash. */
1844 uint16_t iNext;
1845 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1846 uint16_t iUserHead;
1847 /** The number of present entries. */
1848 uint16_t cPresent;
1849 /** The first entry in the table which is present. */
1850 uint16_t iFirstPresent;
1851 /** The number of modifications to the monitored page. */
1852 uint16_t cModifications;
1853 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1854 uint16_t iModifiedNext;
1855 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1856 uint16_t iModifiedPrev;
1857 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1858 uint16_t iMonitoredNext;
1859 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1860 uint16_t iMonitoredPrev;
1861 /** The next page in the age list. */
1862 uint16_t iAgeNext;
1863 /** The previous page in the age list. */
1864 uint16_t iAgePrev;
1865 /** Used to indicate that the page is zeroed. */
1866 bool fZeroed;
1867 /** Used to indicate that a PT has non-global entries. */
1868 bool fSeenNonGlobal;
1869 /** Used to indicate that we're monitoring writes to the guest page. */
1870 bool fMonitored;
1871 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1872 * (All pages are in the age list.) */
1873 bool fCached;
1874 /** This is used by the R3 access handlers when invoked by an async thread.
1875 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1876 bool volatile fReusedFlushPending;
1877 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1878 bool fDirty;
1879
1880 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1881 uint32_t cLocked;
1882 uint32_t idxDirty;
1883 RTGCPTR pvDirtyFault;
1884} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1885/** Pointer to a const pool page. */
1886typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1887
1888
1889/** The hash table size. */
1890# define PGMPOOL_HASH_SIZE 0x40
1891/** The hash function. */
1892# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1893
1894
1895/**
1896 * The shadow page pool instance data.
1897 *
1898 * It's all one big allocation made at init time, except for the
1899 * pages that is. The user nodes follows immediatly after the
1900 * page structures.
1901 */
1902typedef struct PGMPOOL
1903{
1904 /** The VM handle - R3 Ptr. */
1905 PVMR3 pVMR3;
1906 /** The VM handle - R0 Ptr. */
1907 PVMR0 pVMR0;
1908 /** The VM handle - RC Ptr. */
1909 PVMRC pVMRC;
1910 /** The max pool size. This includes the special IDs. */
1911 uint16_t cMaxPages;
1912 /** The current pool size. */
1913 uint16_t cCurPages;
1914 /** The head of the free page list. */
1915 uint16_t iFreeHead;
1916 /* Padding. */
1917 uint16_t u16Padding;
1918 /** Head of the chain of free user nodes. */
1919 uint16_t iUserFreeHead;
1920 /** The number of user nodes we've allocated. */
1921 uint16_t cMaxUsers;
1922 /** The number of present page table entries in the entire pool. */
1923 uint32_t cPresent;
1924 /** Pointer to the array of user nodes - RC pointer. */
1925 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1926 /** Pointer to the array of user nodes - R3 pointer. */
1927 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1928 /** Pointer to the array of user nodes - R0 pointer. */
1929 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1930 /** Head of the chain of free phys ext nodes. */
1931 uint16_t iPhysExtFreeHead;
1932 /** The number of user nodes we've allocated. */
1933 uint16_t cMaxPhysExts;
1934 /** Pointer to the array of physical xref extent - RC pointer. */
1935 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1936 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1937 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1938 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1939 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1940 /** Hash table for GCPhys addresses. */
1941 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1942 /** The head of the age list. */
1943 uint16_t iAgeHead;
1944 /** The tail of the age list. */
1945 uint16_t iAgeTail;
1946 /** Set if the cache is enabled. */
1947 bool fCacheEnabled;
1948 /** Alignment padding. */
1949 bool afPadding1[3];
1950 /** Head of the list of modified pages. */
1951 uint16_t iModifiedHead;
1952 /** The current number of modified pages. */
1953 uint16_t cModifiedPages;
1954 /** Access handler, RC. */
1955 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1956 /** Access handler, R0. */
1957 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1958 /** Access handler, R3. */
1959 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1960 /** The access handler description (R3 ptr). */
1961 R3PTRTYPE(const char *) pszAccessHandler;
1962# if HC_ARCH_BITS == 32
1963 /** Alignment padding. */
1964 uint32_t u32Padding2;
1965# endif
1966 /* Next available slot. */
1967 uint32_t idxFreeDirtyPage;
1968 /* Number of active dirty pages. */
1969 uint32_t cDirtyPages;
1970 /* Array of current dirty pgm pool page indices. */
1971 uint16_t aIdxDirtyPages[16];
1972 uint64_t aDirtyPages[16][512];
1973 /** The number of pages currently in use. */
1974 uint16_t cUsedPages;
1975#ifdef VBOX_WITH_STATISTICS
1976 /** The high water mark for cUsedPages. */
1977 uint16_t cUsedPagesHigh;
1978 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1979 /** Profiling pgmPoolAlloc(). */
1980 STAMPROFILEADV StatAlloc;
1981 /** Profiling pgmR3PoolClearDoIt(). */
1982 STAMPROFILE StatClearAll;
1983 /** Profiling pgmR3PoolReset(). */
1984 STAMPROFILE StatR3Reset;
1985 /** Profiling pgmPoolFlushPage(). */
1986 STAMPROFILE StatFlushPage;
1987 /** Profiling pgmPoolFree(). */
1988 STAMPROFILE StatFree;
1989 /** Counting explicit flushes by PGMPoolFlushPage(). */
1990 STAMCOUNTER StatForceFlushPage;
1991 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1992 STAMCOUNTER StatForceFlushDirtyPage;
1993 /** Counting flushes for reused pages. */
1994 STAMCOUNTER StatForceFlushReused;
1995 /** Profiling time spent zeroing pages. */
1996 STAMPROFILE StatZeroPage;
1997 /** Profiling of pgmPoolTrackDeref. */
1998 STAMPROFILE StatTrackDeref;
1999 /** Profiling pgmTrackFlushGCPhysPT. */
2000 STAMPROFILE StatTrackFlushGCPhysPT;
2001 /** Profiling pgmTrackFlushGCPhysPTs. */
2002 STAMPROFILE StatTrackFlushGCPhysPTs;
2003 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2004 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2005 /** Number of times we've been out of user records. */
2006 STAMCOUNTER StatTrackFreeUpOneUser;
2007 /** Nr of flushed entries. */
2008 STAMCOUNTER StatTrackFlushEntry;
2009 /** Nr of updated entries. */
2010 STAMCOUNTER StatTrackFlushEntryKeep;
2011 /** Profiling deref activity related tracking GC physical pages. */
2012 STAMPROFILE StatTrackDerefGCPhys;
2013 /** Number of linear searches for a HCPhys in the ram ranges. */
2014 STAMCOUNTER StatTrackLinearRamSearches;
2015 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2016 STAMCOUNTER StamTrackPhysExtAllocFailures;
2017 /** Profiling the RC/R0 access handler. */
2018 STAMPROFILE StatMonitorRZ;
2019 /** Times we've failed interpreting the instruction. */
2020 STAMCOUNTER StatMonitorRZEmulateInstr;
2021 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2022 STAMPROFILE StatMonitorRZFlushPage;
2023 /* Times we've detected a page table reinit. */
2024 STAMCOUNTER StatMonitorRZFlushReinit;
2025 /** Counting flushes for pages that are modified too often. */
2026 STAMCOUNTER StatMonitorRZFlushModOverflow;
2027 /** Times we've detected fork(). */
2028 STAMCOUNTER StatMonitorRZFork;
2029 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2030 STAMPROFILE StatMonitorRZHandled;
2031 /** Times we've failed interpreting a patch code instruction. */
2032 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2033 /** Times we've failed interpreting a patch code instruction during flushing. */
2034 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2035 /** The number of times we've seen rep prefixes we can't handle. */
2036 STAMCOUNTER StatMonitorRZRepPrefix;
2037 /** Profiling the REP STOSD cases we've handled. */
2038 STAMPROFILE StatMonitorRZRepStosd;
2039 /** Nr of handled PT faults. */
2040 STAMCOUNTER StatMonitorRZFaultPT;
2041 /** Nr of handled PD faults. */
2042 STAMCOUNTER StatMonitorRZFaultPD;
2043 /** Nr of handled PDPT faults. */
2044 STAMCOUNTER StatMonitorRZFaultPDPT;
2045 /** Nr of handled PML4 faults. */
2046 STAMCOUNTER StatMonitorRZFaultPML4;
2047
2048 /** Profiling the R3 access handler. */
2049 STAMPROFILE StatMonitorR3;
2050 /** Times we've failed interpreting the instruction. */
2051 STAMCOUNTER StatMonitorR3EmulateInstr;
2052 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2053 STAMPROFILE StatMonitorR3FlushPage;
2054 /* Times we've detected a page table reinit. */
2055 STAMCOUNTER StatMonitorR3FlushReinit;
2056 /** Counting flushes for pages that are modified too often. */
2057 STAMCOUNTER StatMonitorR3FlushModOverflow;
2058 /** Times we've detected fork(). */
2059 STAMCOUNTER StatMonitorR3Fork;
2060 /** Profiling the R3 access we've handled (except REP STOSD). */
2061 STAMPROFILE StatMonitorR3Handled;
2062 /** The number of times we've seen rep prefixes we can't handle. */
2063 STAMCOUNTER StatMonitorR3RepPrefix;
2064 /** Profiling the REP STOSD cases we've handled. */
2065 STAMPROFILE StatMonitorR3RepStosd;
2066 /** Nr of handled PT faults. */
2067 STAMCOUNTER StatMonitorR3FaultPT;
2068 /** Nr of handled PD faults. */
2069 STAMCOUNTER StatMonitorR3FaultPD;
2070 /** Nr of handled PDPT faults. */
2071 STAMCOUNTER StatMonitorR3FaultPDPT;
2072 /** Nr of handled PML4 faults. */
2073 STAMCOUNTER StatMonitorR3FaultPML4;
2074 /** The number of times we're called in an async thread an need to flush. */
2075 STAMCOUNTER StatMonitorR3Async;
2076 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2077 STAMCOUNTER StatResetDirtyPages;
2078 /** Times we've called pgmPoolAddDirtyPage. */
2079 STAMCOUNTER StatDirtyPage;
2080 /** Times we've had to flush duplicates for dirty page management. */
2081 STAMCOUNTER StatDirtyPageDupFlush;
2082 /** Times we've had to flush because of overflow. */
2083 STAMCOUNTER StatDirtyPageOverFlowFlush;
2084
2085 /** The high wather mark for cModifiedPages. */
2086 uint16_t cModifiedPagesHigh;
2087 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2088
2089 /** The number of cache hits. */
2090 STAMCOUNTER StatCacheHits;
2091 /** The number of cache misses. */
2092 STAMCOUNTER StatCacheMisses;
2093 /** The number of times we've got a conflict of 'kind' in the cache. */
2094 STAMCOUNTER StatCacheKindMismatches;
2095 /** Number of times we've been out of pages. */
2096 STAMCOUNTER StatCacheFreeUpOne;
2097 /** The number of cacheable allocations. */
2098 STAMCOUNTER StatCacheCacheable;
2099 /** The number of uncacheable allocations. */
2100 STAMCOUNTER StatCacheUncacheable;
2101#else
2102 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2103#endif
2104 /** The AVL tree for looking up a page by its HC physical address. */
2105 AVLOHCPHYSTREE HCPhysTree;
2106 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2107 /** Array of pages. (cMaxPages in length)
2108 * The Id is the index into thist array.
2109 */
2110 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2111} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2112AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2113AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2114AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2115#ifdef VBOX_WITH_STATISTICS
2116AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2117#endif
2118AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2119
2120
2121/** @def PGMPOOL_PAGE_2_PTR
2122 * Maps a pool page pool into the current context.
2123 *
2124 * @returns VBox status code.
2125 * @param pVM The VM handle.
2126 * @param pPage The pool page.
2127 *
2128 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2129 * small page window employeed by that function. Be careful.
2130 * @remark There is no need to assert on the result.
2131 */
2132#if defined(IN_RC)
2133# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2134#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2135# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2136#elif defined(VBOX_STRICT)
2137# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2138DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2139{
2140 Assert(pPage && pPage->pvPageR3);
2141 return pPage->pvPageR3;
2142}
2143#else
2144# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2145#endif
2146
2147/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2148 * Maps a pool page pool into the current context.
2149 *
2150 * @returns VBox status code.
2151 * @param pPGM Pointer to the PGM instance data.
2152 * @param pPage The pool page.
2153 *
2154 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2155 * small page window employeed by that function. Be careful.
2156 * @remark There is no need to assert on the result.
2157 */
2158#if defined(IN_RC)
2159# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2160#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2161# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2162#else
2163# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2164#endif
2165
2166/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2167 * Maps a pool page pool into the current context.
2168 *
2169 * @returns VBox status code.
2170 * @param pPGM Pointer to the PGMCPU instance data.
2171 * @param pPage The pool page.
2172 *
2173 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2174 * small page window employeed by that function. Be careful.
2175 * @remark There is no need to assert on the result.
2176 */
2177#if defined(IN_RC)
2178# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2179#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2180# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2181#else
2182# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2183#endif
2184
2185
2186/** @name Per guest page tracking data.
2187 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2188 * is to use more bits for it and split it up later on. But for now we'll play
2189 * safe and change as little as possible.
2190 *
2191 * The 16-bit word has two parts:
2192 *
2193 * The first 14-bit forms the @a idx field. It is either the index of a page in
2194 * the shadow page pool, or and index into the extent list.
2195 *
2196 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2197 * shadow page pool references to the page. If cRefs equals
2198 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2199 * (misnomer) table and not the shadow page pool.
2200 *
2201 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2202 * the 16-bit word.
2203 *
2204 * @{ */
2205/** The shift count for getting to the cRefs part. */
2206#define PGMPOOL_TD_CREFS_SHIFT 14
2207/** The mask applied after shifting the tracking data down by
2208 * PGMPOOL_TD_CREFS_SHIFT. */
2209#define PGMPOOL_TD_CREFS_MASK 0x3
2210/** The cRef value used to indiciate that the idx is the head of a
2211 * physical cross reference list. */
2212#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2213/** The shift used to get idx. */
2214#define PGMPOOL_TD_IDX_SHIFT 0
2215/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2216#define PGMPOOL_TD_IDX_MASK 0x3fff
2217/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2218 * simply too many mappings of this page. */
2219#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2220
2221/** @def PGMPOOL_TD_MAKE
2222 * Makes a 16-bit tracking data word.
2223 *
2224 * @returns tracking data.
2225 * @param cRefs The @a cRefs field. Must be within bounds!
2226 * @param idx The @a idx field. Must also be within bounds! */
2227#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2228
2229/** @def PGMPOOL_TD_GET_CREFS
2230 * Get the @a cRefs field from a tracking data word.
2231 *
2232 * @returns The @a cRefs field
2233 * @param u16 The tracking data word. */
2234#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2235
2236/** @def PGMPOOL_TD_GET_IDX
2237 * Get the @a idx field from a tracking data word.
2238 *
2239 * @returns The @a idx field
2240 * @param u16 The tracking data word. */
2241#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2242/** @} */
2243
2244
2245/**
2246 * Trees are using self relative offsets as pointers.
2247 * So, all its data, including the root pointer, must be in the heap for HC and GC
2248 * to have the same layout.
2249 */
2250typedef struct PGMTREES
2251{
2252 /** Physical access handlers (AVL range+offsetptr tree). */
2253 AVLROGCPHYSTREE PhysHandlers;
2254 /** Virtual access handlers (AVL range + GC ptr tree). */
2255 AVLROGCPTRTREE VirtHandlers;
2256 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2257 AVLROGCPHYSTREE PhysToVirtHandlers;
2258 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2259 AVLROGCPTRTREE HyperVirtHandlers;
2260} PGMTREES;
2261/** Pointer to PGM trees. */
2262typedef PGMTREES *PPGMTREES;
2263
2264
2265/** @name Paging mode macros
2266 * @{ */
2267#ifdef IN_RC
2268# define PGM_CTX(a,b) a##RC##b
2269# define PGM_CTX_STR(a,b) a "GC" b
2270# define PGM_CTX_DECL(type) VMMRCDECL(type)
2271#else
2272# ifdef IN_RING3
2273# define PGM_CTX(a,b) a##R3##b
2274# define PGM_CTX_STR(a,b) a "R3" b
2275# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2276# else
2277# define PGM_CTX(a,b) a##R0##b
2278# define PGM_CTX_STR(a,b) a "R0" b
2279# define PGM_CTX_DECL(type) VMMDECL(type)
2280# endif
2281#endif
2282
2283#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2284#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2285#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2286#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2287#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2288#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2289#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2290#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2291#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2292#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2293#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2294#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2295#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2296#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2297#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2298#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2299#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2300
2301#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2302#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2303#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2304#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2305#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2306#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2307#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2308#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2309#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2310#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2311#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2312#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2313#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2314#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2315#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2316#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2317#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2318
2319/* Shw_Gst */
2320#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2321#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2322#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2323#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2324#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2325#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2326#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2327#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2328#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2329#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2330#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2331#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2332#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2333#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2334#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2335#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2336#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2337#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2338#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2339
2340#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2341#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2342#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2343#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2344#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2345#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2346#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2347#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2348#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2349#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2350#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2351#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2352#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2353#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2354#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2355#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2356#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2357#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2358#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2359#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2360#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2361#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2362#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2363#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2364#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2365#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2366#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2367#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2368#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2369#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2370#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2371#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2372#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2373#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2374#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2375#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2376#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2377
2378#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2379#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2380/** @} */
2381
2382/**
2383 * Data for each paging mode.
2384 */
2385typedef struct PGMMODEDATA
2386{
2387 /** The guest mode type. */
2388 uint32_t uGstType;
2389 /** The shadow mode type. */
2390 uint32_t uShwType;
2391
2392 /** @name Function pointers for Shadow paging.
2393 * @{
2394 */
2395 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2396 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2397 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2398 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2399
2400 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2401 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2402
2403 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2404 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2405 /** @} */
2406
2407 /** @name Function pointers for Guest paging.
2408 * @{
2409 */
2410 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2411 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2412 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2413 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2414 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2415 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2416 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2417 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2418 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2419 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2420 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2421 /** @} */
2422
2423 /** @name Function pointers for Both Shadow and Guest paging.
2424 * @{
2425 */
2426 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2427 /* no pfnR3BthTrap0eHandler */
2428 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2429 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2430 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2431 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2432 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2433#ifdef VBOX_STRICT
2434 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2435#endif
2436 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2437 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2438
2439 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2440 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2441 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2442 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2443 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2444 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2445#ifdef VBOX_STRICT
2446 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2447#endif
2448 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2449 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2450
2451 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2452 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2453 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2454 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2455 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2456 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2457#ifdef VBOX_STRICT
2458 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2459#endif
2460 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2461 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2462 /** @} */
2463} PGMMODEDATA, *PPGMMODEDATA;
2464
2465
2466
2467/**
2468 * Converts a PGM pointer into a VM pointer.
2469 * @returns Pointer to the VM structure the PGM is part of.
2470 * @param pPGM Pointer to PGM instance data.
2471 */
2472#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2473
2474/**
2475 * PGM Data (part of VM)
2476 */
2477typedef struct PGM
2478{
2479 /** Offset to the VM structure. */
2480 RTINT offVM;
2481 /** Offset of the PGMCPU structure relative to VMCPU. */
2482 RTINT offVCpuPGM;
2483
2484 /** @cfgm{RamPreAlloc, boolean, false}
2485 * Indicates whether the base RAM should all be allocated before starting
2486 * the VM (default), or if it should be allocated when first written to.
2487 */
2488 bool fRamPreAlloc;
2489 /** Indicates whether write monitoring is currently in use.
2490 * This is used to prevent conflicts between live saving and page sharing
2491 * detection. */
2492 bool fPhysWriteMonitoringEngaged;
2493 /** Alignment padding. */
2494 bool afAlignment0[2];
2495
2496 /*
2497 * This will be redefined at least two more times before we're done, I'm sure.
2498 * The current code is only to get on with the coding.
2499 * - 2004-06-10: initial version, bird.
2500 * - 2004-07-02: 1st time, bird.
2501 * - 2004-10-18: 2nd time, bird.
2502 * - 2005-07-xx: 3rd time, bird.
2503 */
2504
2505 /** The host paging mode. (This is what SUPLib reports.) */
2506 SUPPAGINGMODE enmHostMode;
2507
2508 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2509 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2510 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2511 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2512
2513 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2514 RTGCPHYS GCPhys4MBPSEMask;
2515
2516 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2517 * This is sorted by physical address and contains no overlapping ranges. */
2518 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2519 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2520 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2521 /** RC pointer corresponding to PGM::pRamRangesR3. */
2522 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2523 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2524 * range is linked or unlinked. */
2525 uint32_t volatile idRamRangesGen;
2526
2527 /** Pointer to the list of ROM ranges - for R3.
2528 * This is sorted by physical address and contains no overlapping ranges. */
2529 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2530 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2531 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2532 /** RC pointer corresponding to PGM::pRomRangesR3. */
2533 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2534#if HC_ARCH_BITS == 64
2535 /** Alignment padding. */
2536 RTRCPTR GCPtrPadding2;
2537#endif
2538
2539 /** Pointer to the list of MMIO2 ranges - for R3.
2540 * Registration order. */
2541 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2542
2543 /** PGM offset based trees - R3 Ptr. */
2544 R3PTRTYPE(PPGMTREES) pTreesR3;
2545 /** PGM offset based trees - R0 Ptr. */
2546 R0PTRTYPE(PPGMTREES) pTreesR0;
2547 /** PGM offset based trees - RC Ptr. */
2548 RCPTRTYPE(PPGMTREES) pTreesRC;
2549
2550 /** Linked list of GC mappings - for RC.
2551 * The list is sorted ascending on address.
2552 */
2553 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2554 /** Linked list of GC mappings - for HC.
2555 * The list is sorted ascending on address.
2556 */
2557 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2558 /** Linked list of GC mappings - for R0.
2559 * The list is sorted ascending on address.
2560 */
2561 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2562
2563 /** Pointer to the 5 page CR3 content mapping.
2564 * The first page is always the CR3 (in some form) while the 4 other pages
2565 * are used of the PDs in PAE mode. */
2566 RTGCPTR GCPtrCR3Mapping;
2567#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2568 uint32_t u32Alignment1;
2569#endif
2570
2571 /** Indicates that PGMR3FinalizeMappings has been called and that further
2572 * PGMR3MapIntermediate calls will be rejected. */
2573 bool fFinalizedMappings;
2574 /** If set no conflict checks are required. */
2575 bool fMappingsFixed;
2576 /** If set if restored as fixed but we were unable to re-fixate at the old
2577 * location because of room or address incompatibilities. */
2578 bool fMappingsFixedRestored;
2579 /** If set, then no mappings are put into the shadow page table.
2580 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2581 bool fMappingsDisabled;
2582 /** Size of fixed mapping.
2583 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2584 uint32_t cbMappingFixed;
2585 /** Base address (GC) of fixed mapping.
2586 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2587 RTGCPTR GCPtrMappingFixed;
2588 /** The address of the previous RAM range mapping. */
2589 RTGCPTR GCPtrPrevRamRangeMapping;
2590
2591 /** @name Intermediate Context
2592 * @{ */
2593 /** Pointer to the intermediate page directory - Normal. */
2594 R3PTRTYPE(PX86PD) pInterPD;
2595 /** Pointer to the intermedate page tables - Normal.
2596 * There are two page tables, one for the identity mapping and one for
2597 * the host context mapping (of the core code). */
2598 R3PTRTYPE(PX86PT) apInterPTs[2];
2599 /** Pointer to the intermedate page tables - PAE. */
2600 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2601 /** Pointer to the intermedate page directory - PAE. */
2602 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2603 /** Pointer to the intermedate page directory - PAE. */
2604 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2605 /** Pointer to the intermedate page-map level 4 - AMD64. */
2606 R3PTRTYPE(PX86PML4) pInterPaePML4;
2607 /** Pointer to the intermedate page directory - AMD64. */
2608 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2609 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2610 RTHCPHYS HCPhysInterPD;
2611 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2612 RTHCPHYS HCPhysInterPaePDPT;
2613 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2614 RTHCPHYS HCPhysInterPaePML4;
2615 /** @} */
2616
2617 /** Base address of the dynamic page mapping area.
2618 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2619 */
2620 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2621 /** The index of the last entry used in the dynamic page mapping area. */
2622 RTUINT iDynPageMapLast;
2623 /** Cache containing the last entries in the dynamic page mapping area.
2624 * The cache size is covering half of the mapping area. */
2625 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2626 /** Keep a lock counter for the full (!) mapping area. */
2627 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2628
2629 /** The address of the ring-0 mapping cache if we're making use of it. */
2630 RTR0PTR pvR0DynMapUsed;
2631#if HC_ARCH_BITS == 32
2632 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2633 uint32_t u32Alignment2;
2634#endif
2635
2636 /** PGM critical section.
2637 * This protects the physical & virtual access handlers, ram ranges,
2638 * and the page flag updating (some of it anyway).
2639 */
2640 PDMCRITSECT CritSect;
2641
2642 /** Pointer to SHW+GST mode data (function pointers).
2643 * The index into this table is made up from */
2644 R3PTRTYPE(PPGMMODEDATA) paModeData;
2645
2646 /** Shadow Page Pool - R3 Ptr. */
2647 R3PTRTYPE(PPGMPOOL) pPoolR3;
2648 /** Shadow Page Pool - R0 Ptr. */
2649 R0PTRTYPE(PPGMPOOL) pPoolR0;
2650 /** Shadow Page Pool - RC Ptr. */
2651 RCPTRTYPE(PPGMPOOL) pPoolRC;
2652
2653 /** We're not in a state which permits writes to guest memory.
2654 * (Only used in strict builds.) */
2655 bool fNoMorePhysWrites;
2656 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2657 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2658
2659 /**
2660 * Data associated with managing the ring-3 mappings of the allocation chunks.
2661 */
2662 struct
2663 {
2664 /** The chunk tree, ordered by chunk id. */
2665#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2666 R3PTRTYPE(PAVLU32NODECORE) pTree;
2667#else
2668 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2669#endif
2670 /** The chunk age tree, ordered by ageing sequence number. */
2671 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2672 /** The chunk mapping TLB. */
2673 PGMCHUNKR3MAPTLB Tlb;
2674 /** The number of mapped chunks. */
2675 uint32_t c;
2676 /** The maximum number of mapped chunks.
2677 * @cfgm PGM/MaxRing3Chunks */
2678 uint32_t cMax;
2679 /** The current time. */
2680 uint32_t iNow;
2681 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2682 uint32_t AgeingCountdown;
2683 } ChunkR3Map;
2684
2685 /**
2686 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2687 */
2688 PGMPAGER3MAPTLB PhysTlbHC;
2689
2690 /** @name The zero page.
2691 * @{ */
2692 /** The host physical address of the zero page. */
2693 RTHCPHYS HCPhysZeroPg;
2694 /** The ring-3 mapping of the zero page. */
2695 RTR3PTR pvZeroPgR3;
2696 /** The ring-0 mapping of the zero page. */
2697 RTR0PTR pvZeroPgR0;
2698 /** The GC mapping of the zero page. */
2699 RTGCPTR pvZeroPgRC;
2700 /** @}*/
2701
2702 /** The number of handy pages. */
2703 uint32_t cHandyPages;
2704
2705 /** The number of large handy pages. */
2706 uint32_t cLargeHandyPages;
2707
2708 /**
2709 * Array of handy pages.
2710 *
2711 * This array is used in a two way communication between pgmPhysAllocPage
2712 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2713 * an intermediary.
2714 *
2715 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2716 * (The current size of 32 pages, means 128 KB of handy memory.)
2717 */
2718 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2719
2720 /**
2721 * Array of large handy pages. (currently size 1)
2722 *
2723 * This array is used in a two way communication between pgmPhysAllocLargePage
2724 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2725 * an intermediary.
2726 */
2727 GMMPAGEDESC aLargeHandyPage[1];
2728
2729 /**
2730 * Live save data.
2731 */
2732 struct
2733 {
2734 /** Per type statistics. */
2735 struct
2736 {
2737 /** The number of ready pages. */
2738 uint32_t cReadyPages;
2739 /** The number of dirty pages. */
2740 uint32_t cDirtyPages;
2741 /** The number of ready zero pages. */
2742 uint32_t cZeroPages;
2743 /** The number of write monitored pages. */
2744 uint32_t cMonitoredPages;
2745 } Rom,
2746 Mmio2,
2747 Ram;
2748 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2749 uint32_t cIgnoredPages;
2750 /** Indicates that a live save operation is active. */
2751 bool fActive;
2752 /** Padding. */
2753 bool afReserved[2];
2754 /** The next history index. */
2755 uint8_t iDirtyPagesHistory;
2756 /** History of the total amount of dirty pages. */
2757 uint32_t acDirtyPagesHistory[64];
2758 /** Short term dirty page average. */
2759 uint32_t cDirtyPagesShort;
2760 /** Long term dirty page average. */
2761 uint32_t cDirtyPagesLong;
2762 /** The number of saved pages. This is used to get some kind of estimate of the
2763 * link speed so we can decide when we're done. It is reset after the first
2764 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2765 * zero pages. */
2766 uint64_t cSavedPages;
2767 /** The nanosecond timestamp when cSavedPages was 0. */
2768 uint64_t uSaveStartNS;
2769 /** Pages per second (for statistics). */
2770 uint32_t cPagesPerSecond;
2771 uint32_t cAlignment;
2772 } LiveSave;
2773
2774 /** @name Error injection.
2775 * @{ */
2776 /** Inject handy page allocation errors pretending we're completely out of
2777 * memory. */
2778 bool volatile fErrInjHandyPages;
2779 /** Padding. */
2780 bool afReserved[3];
2781 /** @} */
2782
2783 /** @name Release Statistics
2784 * @{ */
2785 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2786 uint32_t cPrivatePages; /**< The number of private pages. */
2787 uint32_t cSharedPages; /**< The number of shared pages. */
2788 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
2789 uint32_t cZeroPages; /**< The number of zero backed pages. */
2790 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2791 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2792 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2793 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2794 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2795 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
2796/* uint32_t aAlignment4[1]; */
2797
2798 /** The number of times we were forced to change the hypervisor region location. */
2799 STAMCOUNTER cRelocations;
2800
2801 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
2802 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
2803 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2804 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
2805 /** @} */
2806
2807#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2808 /* R3 only: */
2809 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2810 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2811
2812 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2813 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2814 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2815 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2816 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2817 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2818 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2819 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2820 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2821 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2822 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2823 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2824 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2825 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2826 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2827 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2828 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2829 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2830 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2831 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2832/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2833 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2834 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2835/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2836
2837 /* RC only: */
2838 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2839 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2840 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2841 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2842
2843 STAMCOUNTER StatRZPhysRead;
2844 STAMCOUNTER StatRZPhysReadBytes;
2845 STAMCOUNTER StatRZPhysWrite;
2846 STAMCOUNTER StatRZPhysWriteBytes;
2847 STAMCOUNTER StatR3PhysRead;
2848 STAMCOUNTER StatR3PhysReadBytes;
2849 STAMCOUNTER StatR3PhysWrite;
2850 STAMCOUNTER StatR3PhysWriteBytes;
2851 STAMCOUNTER StatRCPhysRead;
2852 STAMCOUNTER StatRCPhysReadBytes;
2853 STAMCOUNTER StatRCPhysWrite;
2854 STAMCOUNTER StatRCPhysWriteBytes;
2855
2856 STAMCOUNTER StatRZPhysSimpleRead;
2857 STAMCOUNTER StatRZPhysSimpleReadBytes;
2858 STAMCOUNTER StatRZPhysSimpleWrite;
2859 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2860 STAMCOUNTER StatR3PhysSimpleRead;
2861 STAMCOUNTER StatR3PhysSimpleReadBytes;
2862 STAMCOUNTER StatR3PhysSimpleWrite;
2863 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2864 STAMCOUNTER StatRCPhysSimpleRead;
2865 STAMCOUNTER StatRCPhysSimpleReadBytes;
2866 STAMCOUNTER StatRCPhysSimpleWrite;
2867 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2868
2869 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2870 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2871 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2872 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2873 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2874 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2875 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2876
2877 /** Time spent by the host OS for large page allocation. */
2878 STAMPROFILE StatAllocLargePage;
2879 /** Time spent clearing the newly allocated large pages. */
2880 STAMPROFILE StatClearLargePage;
2881 /** pgmPhysIsValidLargePage profiling - R3 */
2882 STAMPROFILE StatR3IsValidLargePage;
2883 /** pgmPhysIsValidLargePage profiling - RZ*/
2884 STAMPROFILE StatRZIsValidLargePage;
2885#endif
2886} PGM;
2887#ifndef IN_TSTVMSTRUCTGC /* HACK */
2888AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2889AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2890AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2891AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2892AssertCompileMemberAlignment(PGM, CritSect, 8);
2893AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2894AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2895AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2896AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2897AssertCompileMemberAlignment(PGM, cRelocations, 8);
2898#endif /* !IN_TSTVMSTRUCTGC */
2899/** Pointer to the PGM instance data. */
2900typedef PGM *PPGM;
2901
2902
2903/**
2904 * Converts a PGMCPU pointer into a VM pointer.
2905 * @returns Pointer to the VM structure the PGM is part of.
2906 * @param pPGM Pointer to PGMCPU instance data.
2907 */
2908#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2909
2910/**
2911 * Converts a PGMCPU pointer into a PGM pointer.
2912 * @returns Pointer to the VM structure the PGM is part of.
2913 * @param pPGM Pointer to PGMCPU instance data.
2914 */
2915#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2916
2917/**
2918 * PGMCPU Data (part of VMCPU).
2919 */
2920typedef struct PGMCPU
2921{
2922 /** Offset to the VM structure. */
2923 RTINT offVM;
2924 /** Offset to the VMCPU structure. */
2925 RTINT offVCpu;
2926 /** Offset of the PGM structure relative to VMCPU. */
2927 RTINT offPGM;
2928 RTINT uPadding0; /**< structure size alignment. */
2929
2930#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2931 /** Automatically tracked physical memory mapping set.
2932 * Ring-0 and strict raw-mode builds. */
2933 PGMMAPSET AutoSet;
2934#endif
2935
2936 /** A20 gate mask.
2937 * Our current approach to A20 emulation is to let REM do it and don't bother
2938 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2939 * But whould need arrise, we'll subject physical addresses to this mask. */
2940 RTGCPHYS GCPhysA20Mask;
2941 /** A20 gate state - boolean! */
2942 bool fA20Enabled;
2943
2944 /** What needs syncing (PGM_SYNC_*).
2945 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2946 * PGMFlushTLB, and PGMR3Load. */
2947 RTUINT fSyncFlags;
2948
2949 /** The shadow paging mode. */
2950 PGMMODE enmShadowMode;
2951 /** The guest paging mode. */
2952 PGMMODE enmGuestMode;
2953
2954 /** The current physical address representing in the guest CR3 register. */
2955 RTGCPHYS GCPhysCR3;
2956
2957 /** @name 32-bit Guest Paging.
2958 * @{ */
2959 /** The guest's page directory, R3 pointer. */
2960 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2961#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2962 /** The guest's page directory, R0 pointer. */
2963 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2964#endif
2965 /** The guest's page directory, static RC mapping. */
2966 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2967 /** @} */
2968
2969 /** @name PAE Guest Paging.
2970 * @{ */
2971 /** The guest's page directory pointer table, static RC mapping. */
2972 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2973 /** The guest's page directory pointer table, R3 pointer. */
2974 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2975#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2976 /** The guest's page directory pointer table, R0 pointer. */
2977 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2978#endif
2979
2980 /** The guest's page directories, R3 pointers.
2981 * These are individual pointers and don't have to be adjecent.
2982 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2983 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2984 /** The guest's page directories, R0 pointers.
2985 * Same restrictions as apGstPaePDsR3. */
2986#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2987 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2988#endif
2989 /** The guest's page directories, static GC mapping.
2990 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2991 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2992 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2993 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2994 RTGCPHYS aGCPhysGstPaePDs[4];
2995 /** The physical addresses of the monitored guest page directories (PAE). */
2996 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2997 /** @} */
2998
2999 /** @name AMD64 Guest Paging.
3000 * @{ */
3001 /** The guest's page directory pointer table, R3 pointer. */
3002 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3003#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3004 /** The guest's page directory pointer table, R0 pointer. */
3005 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3006#else
3007 RTR0PTR alignment6b; /**< alignment equalizer. */
3008#endif
3009 /** @} */
3010
3011 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3012 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3013 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3014 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3015 /** Pointer to the page of the current active CR3 - RC Ptr. */
3016 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3017 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3018 uint32_t iShwUser;
3019 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3020 uint32_t iShwUserTable;
3021# if HC_ARCH_BITS == 64
3022 RTRCPTR alignment6; /**< structure size alignment. */
3023# endif
3024 /** @} */
3025
3026 /** @name Function pointers for Shadow paging.
3027 * @{
3028 */
3029 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3030 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3031 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3032 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3033
3034 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3035 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3036
3037 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3038 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3039
3040 /** @} */
3041
3042 /** @name Function pointers for Guest paging.
3043 * @{
3044 */
3045 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3046 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3047 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3048 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3049 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3050 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3051 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3052 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3053#if HC_ARCH_BITS == 64
3054 RTRCPTR alignment3; /**< structure size alignment. */
3055#endif
3056
3057 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3058 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3059 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3060 /** @} */
3061
3062 /** @name Function pointers for Both Shadow and Guest paging.
3063 * @{
3064 */
3065 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3066 /* no pfnR3BthTrap0eHandler */
3067 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3068 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3069 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3070 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3071 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3072 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3073 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3074 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3075
3076 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3077 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3078 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3079 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3080 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3081 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3082 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3083 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3084 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3085
3086 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3087 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3088 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3089 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3090 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3091 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3092 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3093 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3094 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3095 RTRCPTR alignment2; /**< structure size alignment. */
3096 /** @} */
3097
3098 /** For saving stack space, the disassembler state is allocated here instead of
3099 * on the stack.
3100 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3101 union
3102 {
3103 /** The disassembler scratch space. */
3104 DISCPUSTATE DisState;
3105 /** Padding. */
3106 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3107 };
3108
3109 /* Count the number of pgm pool access handler calls. */
3110 uint64_t cPoolAccessHandler;
3111
3112 /** @name Release Statistics
3113 * @{ */
3114 /** The number of times the guest has switched mode since last reset or statistics reset. */
3115 STAMCOUNTER cGuestModeChanges;
3116 /** @} */
3117
3118#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3119 /** @name Statistics
3120 * @{ */
3121 /** RC: Which statistic this \#PF should be attributed to. */
3122 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3123 RTRCPTR padding0;
3124 /** R0: Which statistic this \#PF should be attributed to. */
3125 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3126 RTR0PTR padding1;
3127
3128 /* Common */
3129 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3130 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3131
3132 /* R0 only: */
3133 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3134 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3135 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3136 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3137 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3138 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3139 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3140 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3141 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3142 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3143 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3144 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3145 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3146 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3147 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3148 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3149 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3150 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3151 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3152 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3153 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3154 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3155 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3156 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3157 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3158 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3159
3160 /* RZ only: */
3161 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3162 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3163 STAMPROFILE StatRZTrap0eTimeSyncPT;
3164 STAMPROFILE StatRZTrap0eTimeMapping;
3165 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3166 STAMPROFILE StatRZTrap0eTimeHandlers;
3167 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3168 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3169 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3170 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3171 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3172 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3173 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3174 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3175 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3176 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3177 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3178 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3179 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3180 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3181 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3182 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3183 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3184 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3185 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3186 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3187 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3188 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3189 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3190 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3191 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3192 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3193 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3194 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3195 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3196 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3197 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3198 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3199 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3200 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3201 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3202 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3203 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3204 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3205 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3206 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3207 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3208 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3209 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3210
3211 /* HC - R3 and (maybe) R0: */
3212
3213 /* RZ & R3: */
3214 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3215 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3216 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3217 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3218 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3219 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3220 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3221 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3222 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3223 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3224 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3225 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3226 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3227 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3228 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3229 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3230 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3231 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3232 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3233 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3234 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3235 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3236 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3237 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3238 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3239 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3240 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3241 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3242 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3243 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3244 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3245 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3246 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3247 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3248 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3249 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3250 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3251 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3252 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3253 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3254 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3255 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3256 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3257 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3258 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3259 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3260 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3261
3262 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3263 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3264 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3265 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3266 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3267 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3268 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3269 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3270 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3271 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3272 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3273 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3274 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3275 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3276 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3277 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3278 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3279 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3280 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3281 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3282 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3283 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3284 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3285 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3286 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3287 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3288 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3289 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3290 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3291 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3292 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3293 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3294 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3295 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3296 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3297 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3298 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3299 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3300 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3301 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3302 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3303 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3304 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3305 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3306 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3307 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3308 /** @} */
3309#endif /* VBOX_WITH_STATISTICS */
3310} PGMCPU;
3311/** Pointer to the per-cpu PGM data. */
3312typedef PGMCPU *PPGMCPU;
3313
3314
3315/** @name PGM::fSyncFlags Flags
3316 * @{
3317 */
3318/** Updates the virtual access handler state bit in PGMPAGE. */
3319#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3320/** Always sync CR3. */
3321#define PGM_SYNC_ALWAYS RT_BIT(1)
3322/** Check monitoring on next CR3 (re)load and invalidate page.
3323 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3324#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3325/** Check guest mapping in SyncCR3. */
3326#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3327/** Clear the page pool (a light weight flush). */
3328#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3329#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3330/** @} */
3331
3332
3333RT_C_DECLS_BEGIN
3334
3335int pgmLock(PVM pVM);
3336void pgmUnlock(PVM pVM);
3337
3338int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3339int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3340int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3341PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3342int pgmMapResolveConflicts(PVM pVM);
3343DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3344
3345void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3346bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3347void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3348int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3349DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3350#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3351void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3352#else
3353# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3354#endif
3355DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3356int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3357
3358int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3359int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3360int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3361int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3362int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3363void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3364int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3365int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3366int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3367int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3368int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3369int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3370int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3371VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3372VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3373int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3374
3375#ifdef IN_RING3
3376void pgmR3PhysRelinkRamRanges(PVM pVM);
3377int pgmR3PhysRamPreAllocate(PVM pVM);
3378int pgmR3PhysRamReset(PVM pVM);
3379int pgmR3PhysRomReset(PVM pVM);
3380int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3381int pgmR3PhysRamTerm(PVM pVM);
3382
3383int pgmR3PoolInit(PVM pVM);
3384void pgmR3PoolRelocate(PVM pVM);
3385void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3386void pgmR3PoolReset(PVM pVM);
3387void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3388DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3389
3390#endif /* IN_RING3 */
3391#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3392int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3393#endif
3394int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3395
3396DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3397{
3398 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3399}
3400
3401void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3402void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3403int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3404void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3405PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3406int pgmPoolSyncCR3(PVMCPU pVCpu);
3407bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3408int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3409void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3410void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3411DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3412{
3413 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3414}
3415
3416uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3417void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3418void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3419int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3420void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3421
3422void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3423void pgmPoolResetDirtyPages(PVM pVM);
3424
3425int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3426int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3427
3428void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3429void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3430int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3431int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3432
3433int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3434#ifndef IN_RC
3435int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3436#endif
3437int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3438
3439PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3440PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3441PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3442PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3443
3444RT_C_DECLS_END
3445
3446/** @} */
3447
3448#endif
3449
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