VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 30842

Last change on this file since 30842 was 30842, checked in by vboxsync, 15 years ago

Activated large guest memory support for 32-bit guests
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1/* $Id: PGMInternal.h 30842 2010-07-14 14:19:44Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
67 * Comment it if it will break something.
68 */
69#define PGM_OUT_OF_SYNC_IN_GC
70
71/**
72 * Check and skip global PDEs for non-global flushes
73 */
74#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
75
76/**
77 * Optimization for PAE page tables that are modified often
78 */
79//#if 0 /* disabled again while debugging */
80#ifndef IN_RC
81# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
82#endif
83//#endif
84
85/**
86 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
87 */
88#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
89# define PGM_WITH_LARGE_PAGES
90#endif
91
92/**
93 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
94 */
95#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
96# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
97#endif
98
99/**
100 * Sync N pages instead of a whole page table
101 */
102#define PGM_SYNC_N_PAGES
103
104/**
105 * Number of pages to sync during a page fault
106 *
107 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
108 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
109 *
110 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
111 * world switch overhead, so let's sync more.
112 */
113# ifdef IN_RING0
114/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
115 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
116 * but ~5% fewer faults.
117 */
118# define PGM_SYNC_NR_PAGES 32
119#else
120# define PGM_SYNC_NR_PAGES 8
121#endif
122
123/**
124 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
125 */
126#define PGM_MAX_PHYSCACHE_ENTRIES 64
127#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
128
129
130/** @def PGMPOOL_CFG_MAX_GROW
131 * The maximum number of pages to add to the pool in one go.
132 */
133#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
134
135/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
136 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
137 */
138#ifdef VBOX_STRICT
139# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
140#endif
141
142/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
143 * Enables the experimental lazy page allocation code. */
144/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
145
146/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
147 * Enables real write monitoring of pages, i.e. mapping them read-only and
148 * only making them writable when getting a write access #PF. */
149#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
150
151/** @} */
152
153
154/** @name PDPT and PML4 flags.
155 * These are placed in the three bits available for system programs in
156 * the PDPT and PML4 entries.
157 * @{ */
158/** The entry is a permanent one and it's must always be present.
159 * Never free such an entry. */
160#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
161/** Mapping (hypervisor allocated pagetable). */
162#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
163/** @} */
164
165/** @name Page directory flags.
166 * These are placed in the three bits available for system programs in
167 * the page directory entries.
168 * @{ */
169/** Mapping (hypervisor allocated pagetable). */
170#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
171/** Made read-only to facilitate dirty bit tracking. */
172#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
173/** @} */
174
175/** @name Page flags.
176 * These are placed in the three bits available for system programs in
177 * the page entries.
178 * @{ */
179/** Made read-only to facilitate dirty bit tracking. */
180#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
181
182#ifndef PGM_PTFLAGS_CSAM_VALIDATED
183/** Scanned and approved by CSAM (tm).
184 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
185 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
186#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
187#endif
188
189/** @} */
190
191/** @name Defines used to indicate the shadow and guest paging in the templates.
192 * @{ */
193#define PGM_TYPE_REAL 1
194#define PGM_TYPE_PROT 2
195#define PGM_TYPE_32BIT 3
196#define PGM_TYPE_PAE 4
197#define PGM_TYPE_AMD64 5
198#define PGM_TYPE_NESTED 6
199#define PGM_TYPE_EPT 7
200#define PGM_TYPE_MAX PGM_TYPE_EPT
201/** @} */
202
203/** Macro for checking if the guest is using paging.
204 * @param uGstType PGM_TYPE_*
205 * @param uShwType PGM_TYPE_*
206 * @remark ASSUMES certain order of the PGM_TYPE_* values.
207 */
208#define PGM_WITH_PAGING(uGstType, uShwType) \
209 ( (uGstType) >= PGM_TYPE_32BIT \
210 && (uShwType) != PGM_TYPE_NESTED \
211 && (uShwType) != PGM_TYPE_EPT)
212
213/** Macro for checking if the guest supports the NX bit.
214 * @param uGstType PGM_TYPE_*
215 * @param uShwType PGM_TYPE_*
216 * @remark ASSUMES certain order of the PGM_TYPE_* values.
217 */
218#define PGM_WITH_NX(uGstType, uShwType) \
219 ( (uGstType) >= PGM_TYPE_PAE \
220 && (uShwType) != PGM_TYPE_NESTED \
221 && (uShwType) != PGM_TYPE_EPT)
222
223
224/** @def PGM_HCPHYS_2_PTR
225 * Maps a HC physical page pool address to a virtual address.
226 *
227 * @returns VBox status code.
228 * @param pVM The VM handle.
229 * @param HCPhys The HC physical address to map to a virtual one.
230 * @param ppv Where to store the virtual address. No need to cast this.
231 *
232 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
233 * small page window employeed by that function. Be careful.
234 * @remark There is no need to assert on the result.
235 */
236#ifdef IN_RC
237# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
239#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
240# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
241 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
242#else
243# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
244 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
245#endif
246
247/** @def PGM_GCPHYS_2_PTR
248 * Maps a GC physical page address to a virtual address.
249 *
250 * @returns VBox status code.
251 * @param pVM The VM handle.
252 * @param GCPhys The GC physical address to map to a virtual one.
253 * @param ppv Where to store the virtual address. No need to cast this.
254 *
255 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
256 * small page window employeed by that function. Be careful.
257 * @remark There is no need to assert on the result.
258 */
259#ifdef IN_RC
260# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
261 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
262#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
263# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
264 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
265#else
266# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
267 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
268#endif
269
270/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
271 * Maps a GC physical page address to a virtual address.
272 *
273 * @returns VBox status code.
274 * @param pPGM Pointer to the PGM instance data.
275 * @param GCPhys The GC physical address to map to a virtual one.
276 * @param ppv Where to store the virtual address. No need to cast this.
277 *
278 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
279 * small page window employeed by that function. Be careful.
280 * @remark There is no need to assert on the result.
281 */
282#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
283# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
284 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
285#else
286# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
287 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
288#endif
289
290/** @def PGM_GCPHYS_2_PTR_EX
291 * Maps a unaligned GC physical page address to a virtual address.
292 *
293 * @returns VBox status code.
294 * @param pVM The VM handle.
295 * @param GCPhys The GC physical address to map to a virtual one.
296 * @param ppv Where to store the virtual address. No need to cast this.
297 *
298 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
299 * small page window employeed by that function. Be careful.
300 * @remark There is no need to assert on the result.
301 */
302#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
303# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
304 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
305#else
306# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
307 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
308#endif
309
310/** @def PGM_INVL_PG
311 * Invalidates a page.
312 *
313 * @param pVCpu The VMCPU handle.
314 * @param GCVirt The virtual address of the page to invalidate.
315 */
316#ifdef IN_RC
317# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
318#elif defined(IN_RING0)
319# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
320#else
321# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
322#endif
323
324/** @def PGM_INVL_PG_ALL_VCPU
325 * Invalidates a page on all VCPUs
326 *
327 * @param pVM The VM handle.
328 * @param GCVirt The virtual address of the page to invalidate.
329 */
330#ifdef IN_RC
331# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
332#elif defined(IN_RING0)
333# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
334#else
335# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
336#endif
337
338/** @def PGM_INVL_BIG_PG
339 * Invalidates a 4MB page directory entry.
340 *
341 * @param pVCpu The VMCPU handle.
342 * @param GCVirt The virtual address within the page directory to invalidate.
343 */
344#ifdef IN_RC
345# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
346#elif defined(IN_RING0)
347# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
348#else
349# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
350#endif
351
352/** @def PGM_INVL_VCPU_TLBS()
353 * Invalidates the TLBs of the specified VCPU
354 *
355 * @param pVCpu The VMCPU handle.
356 */
357#ifdef IN_RC
358# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
359#elif defined(IN_RING0)
360# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
361#else
362# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
363#endif
364
365/** @def PGM_INVL_ALL_VCPU_TLBS()
366 * Invalidates the TLBs of all VCPUs
367 *
368 * @param pVM The VM handle.
369 */
370#ifdef IN_RC
371# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
372#elif defined(IN_RING0)
373# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
374#else
375# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
376#endif
377
378/** Size of the GCPtrConflict array in PGMMAPPING.
379 * @remarks Must be a power of two. */
380#define PGMMAPPING_CONFLICT_MAX 8
381
382/**
383 * Structure for tracking GC Mappings.
384 *
385 * This structure is used by linked list in both GC and HC.
386 */
387typedef struct PGMMAPPING
388{
389 /** Pointer to next entry. */
390 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
391 /** Pointer to next entry. */
392 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
393 /** Pointer to next entry. */
394 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
395 /** Indicate whether this entry is finalized. */
396 bool fFinalized;
397 /** Start Virtual address. */
398 RTGCPTR GCPtr;
399 /** Last Virtual address (inclusive). */
400 RTGCPTR GCPtrLast;
401 /** Range size (bytes). */
402 RTGCPTR cb;
403 /** Pointer to relocation callback function. */
404 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
405 /** User argument to the callback. */
406 R3PTRTYPE(void *) pvUser;
407 /** Mapping description / name. For easing debugging. */
408 R3PTRTYPE(const char *) pszDesc;
409 /** Last 8 addresses that caused conflicts. */
410 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
411 /** Number of conflicts for this hypervisor mapping. */
412 uint32_t cConflicts;
413 /** Number of page tables. */
414 uint32_t cPTs;
415
416 /** Array of page table mapping data. Each entry
417 * describes one page table. The array can be longer
418 * than the declared length.
419 */
420 struct
421 {
422 /** The HC physical address of the page table. */
423 RTHCPHYS HCPhysPT;
424 /** The HC physical address of the first PAE page table. */
425 RTHCPHYS HCPhysPaePT0;
426 /** The HC physical address of the second PAE page table. */
427 RTHCPHYS HCPhysPaePT1;
428 /** The HC virtual address of the 32-bit page table. */
429 R3PTRTYPE(PX86PT) pPTR3;
430 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
431 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
432 /** The RC virtual address of the 32-bit page table. */
433 RCPTRTYPE(PX86PT) pPTRC;
434 /** The RC virtual address of the two PAE page table. */
435 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
436 /** The R0 virtual address of the 32-bit page table. */
437 R0PTRTYPE(PX86PT) pPTR0;
438 /** The R0 virtual address of the two PAE page table. */
439 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
440 } aPTs[1];
441} PGMMAPPING;
442/** Pointer to structure for tracking GC Mappings. */
443typedef struct PGMMAPPING *PPGMMAPPING;
444
445
446/**
447 * Physical page access handler structure.
448 *
449 * This is used to keep track of physical address ranges
450 * which are being monitored in some kind of way.
451 */
452typedef struct PGMPHYSHANDLER
453{
454 AVLROGCPHYSNODECORE Core;
455 /** Access type. */
456 PGMPHYSHANDLERTYPE enmType;
457 /** Number of pages to update. */
458 uint32_t cPages;
459 /** Pointer to R3 callback function. */
460 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
461 /** User argument for R3 handlers. */
462 R3PTRTYPE(void *) pvUserR3;
463 /** Pointer to R0 callback function. */
464 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
465 /** User argument for R0 handlers. */
466 R0PTRTYPE(void *) pvUserR0;
467 /** Pointer to RC callback function. */
468 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
469 /** User argument for RC handlers. */
470 RCPTRTYPE(void *) pvUserRC;
471 /** Description / Name. For easing debugging. */
472 R3PTRTYPE(const char *) pszDesc;
473#ifdef VBOX_WITH_STATISTICS
474 /** Profiling of this handler. */
475 STAMPROFILE Stat;
476#endif
477} PGMPHYSHANDLER;
478/** Pointer to a physical page access handler structure. */
479typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
480
481
482/**
483 * Cache node for the physical addresses covered by a virtual handler.
484 */
485typedef struct PGMPHYS2VIRTHANDLER
486{
487 /** Core node for the tree based on physical ranges. */
488 AVLROGCPHYSNODECORE Core;
489 /** Offset from this struct to the PGMVIRTHANDLER structure. */
490 int32_t offVirtHandler;
491 /** Offset of the next alias relative to this one.
492 * Bit 0 is used for indicating whether we're in the tree.
493 * Bit 1 is used for indicating that we're the head node.
494 */
495 int32_t offNextAlias;
496} PGMPHYS2VIRTHANDLER;
497/** Pointer to a phys to virtual handler structure. */
498typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
499
500/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
501 * node is in the tree. */
502#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
503/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
504 * node is in the head of an alias chain.
505 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
506#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
507/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
508#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
509
510
511/**
512 * Virtual page access handler structure.
513 *
514 * This is used to keep track of virtual address ranges
515 * which are being monitored in some kind of way.
516 */
517typedef struct PGMVIRTHANDLER
518{
519 /** Core node for the tree based on virtual ranges. */
520 AVLROGCPTRNODECORE Core;
521 /** Size of the range (in bytes). */
522 RTGCPTR cb;
523 /** Number of cache pages. */
524 uint32_t cPages;
525 /** Access type. */
526 PGMVIRTHANDLERTYPE enmType;
527 /** Pointer to the RC callback function. */
528 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
529#if HC_ARCH_BITS == 64
530 RTRCPTR padding;
531#endif
532 /** Pointer to the R3 callback function for invalidation. */
533 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
534 /** Pointer to the R3 callback function. */
535 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
536 /** Description / Name. For easing debugging. */
537 R3PTRTYPE(const char *) pszDesc;
538#ifdef VBOX_WITH_STATISTICS
539 /** Profiling of this handler. */
540 STAMPROFILE Stat;
541#endif
542 /** Array of cached physical addresses for the monitored ranged. */
543 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
544} PGMVIRTHANDLER;
545/** Pointer to a virtual page access handler structure. */
546typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
547
548
549/**
550 * Page type.
551 *
552 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
553 * @remarks This is used in the saved state, so changes to it requires bumping
554 * the saved state version.
555 * @todo So, convert to \#defines!
556 */
557typedef enum PGMPAGETYPE
558{
559 /** The usual invalid zero entry. */
560 PGMPAGETYPE_INVALID = 0,
561 /** RAM page. (RWX) */
562 PGMPAGETYPE_RAM,
563 /** MMIO2 page. (RWX) */
564 PGMPAGETYPE_MMIO2,
565 /** MMIO2 page aliased over an MMIO page. (RWX)
566 * See PGMHandlerPhysicalPageAlias(). */
567 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
568 /** Shadowed ROM. (RWX) */
569 PGMPAGETYPE_ROM_SHADOW,
570 /** ROM page. (R-X) */
571 PGMPAGETYPE_ROM,
572 /** MMIO page. (---) */
573 PGMPAGETYPE_MMIO,
574 /** End of valid entries. */
575 PGMPAGETYPE_END
576} PGMPAGETYPE;
577AssertCompile(PGMPAGETYPE_END <= 7);
578
579/** @name Page type predicates.
580 * @{ */
581#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
582#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
583#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
584#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
585#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
586/** @} */
587
588
589/**
590 * A Physical Guest Page tracking structure.
591 *
592 * The format of this structure is complicated because we have to fit a lot
593 * of information into as few bits as possible. The format is also subject
594 * to change (there is one comming up soon). Which means that for we'll be
595 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
596 * accesses to the structure.
597 */
598typedef struct PGMPAGE
599{
600 /** The physical address and the Page ID. */
601 RTHCPHYS HCPhysAndPageID;
602 /** Combination of:
603 * - [0-7]: u2HandlerPhysStateY - the physical handler state
604 * (PGM_PAGE_HNDL_PHYS_STATE_*).
605 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
606 * (PGM_PAGE_HNDL_VIRT_STATE_*).
607 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
608 * - [15]: fWrittenToY - flag indicating that a write monitored page was
609 * written to when set.
610 * - [10-13]: 4 unused bits.
611 * @remarks Warning! All accesses to the bits are hardcoded.
612 *
613 * @todo Change this to a union with both bitfields, u8 and u accessors.
614 * That'll help deal with some of the hardcoded accesses.
615 *
616 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
617 * will make it possible to turn some of the 16-bit accesses into
618 * 32-bit ones, which may be efficient (stalls).
619 */
620 RTUINT16U u16MiscY;
621 /** The page state.
622 * Only 3 bits are really needed for this. */
623 uint16_t uStateY : 3;
624 /** The page type (PGMPAGETYPE).
625 * Only 3 bits are really needed for this. */
626 uint16_t uTypeY : 3;
627 /** PTE index for usage tracking (page pool). */
628 uint16_t uPteIdx : 10;
629 /** Usage tracking (page pool). */
630 uint16_t u16TrackingY;
631 /** The number of read locks on this page. */
632 uint8_t cReadLocksY;
633 /** The number of write locks on this page. */
634 uint8_t cWriteLocksY;
635} PGMPAGE;
636AssertCompileSize(PGMPAGE, 16);
637/** Pointer to a physical guest page. */
638typedef PGMPAGE *PPGMPAGE;
639/** Pointer to a const physical guest page. */
640typedef const PGMPAGE *PCPGMPAGE;
641/** Pointer to a physical guest page pointer. */
642typedef PPGMPAGE *PPPGMPAGE;
643
644
645/**
646 * Clears the page structure.
647 * @param pPage Pointer to the physical guest page tracking structure.
648 */
649#define PGM_PAGE_CLEAR(pPage) \
650 do { \
651 (pPage)->HCPhysAndPageID = 0; \
652 (pPage)->uStateY = 0; \
653 (pPage)->uTypeY = 0; \
654 (pPage)->uPteIdx = 0; \
655 (pPage)->u16MiscY.u = 0; \
656 (pPage)->u16TrackingY = 0; \
657 (pPage)->cReadLocksY = 0; \
658 (pPage)->cWriteLocksY = 0; \
659 } while (0)
660
661/**
662 * Initializes the page structure.
663 * @param pPage Pointer to the physical guest page tracking structure.
664 */
665#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
666 do { \
667 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
668 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
669 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
670 (pPage)->uStateY = (_uState); \
671 (pPage)->uTypeY = (_uType); \
672 (pPage)->uPteIdx = 0; \
673 (pPage)->u16MiscY.u = 0; \
674 (pPage)->u16TrackingY = 0; \
675 (pPage)->cReadLocksY = 0; \
676 (pPage)->cWriteLocksY = 0; \
677 } while (0)
678
679/**
680 * Initializes the page structure of a ZERO page.
681 * @param pPage Pointer to the physical guest page tracking structure.
682 * @param pVM The VM handle (for getting the zero page address).
683 * @param uType The page type (PGMPAGETYPE).
684 */
685#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
686 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
687
688
689/** @name The Page state, PGMPAGE::uStateY.
690 * @{ */
691/** The zero page.
692 * This is a per-VM page that's never ever mapped writable. */
693#define PGM_PAGE_STATE_ZERO 0
694/** A allocated page.
695 * This is a per-VM page allocated from the page pool (or wherever
696 * we get MMIO2 pages from if the type is MMIO2).
697 */
698#define PGM_PAGE_STATE_ALLOCATED 1
699/** A allocated page that's being monitored for writes.
700 * The shadow page table mappings are read-only. When a write occurs, the
701 * fWrittenTo member is set, the page remapped as read-write and the state
702 * moved back to allocated. */
703#define PGM_PAGE_STATE_WRITE_MONITORED 2
704/** The page is shared, aka. copy-on-write.
705 * This is a page that's shared with other VMs. */
706#define PGM_PAGE_STATE_SHARED 3
707/** The page is ballooned, so no longer available for this VM. */
708#define PGM_PAGE_STATE_BALLOONED 4
709/** @} */
710
711
712/**
713 * Gets the page state.
714 * @returns page state (PGM_PAGE_STATE_*).
715 * @param pPage Pointer to the physical guest page tracking structure.
716 */
717#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
718
719/**
720 * Sets the page state.
721 * @param pPage Pointer to the physical guest page tracking structure.
722 * @param _uState The new page state.
723 */
724#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
725
726
727/**
728 * Gets the host physical address of the guest page.
729 * @returns host physical address (RTHCPHYS).
730 * @param pPage Pointer to the physical guest page tracking structure.
731 */
732#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
733
734/**
735 * Sets the host physical address of the guest page.
736 * @param pPage Pointer to the physical guest page tracking structure.
737 * @param _HCPhys The new host physical address.
738 */
739#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
740 do { \
741 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
742 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
743 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
744 | (SetHCPhysTmp << (28-12)); \
745 } while (0)
746
747/**
748 * Get the Page ID.
749 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
750 * @param pPage Pointer to the physical guest page tracking structure.
751 */
752#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
753
754/**
755 * Sets the Page ID.
756 * @param pPage Pointer to the physical guest page tracking structure.
757 */
758#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
759 do { \
760 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
761 | ((_idPage) & UINT32_C(0x0fffffff)); \
762 } while (0)
763
764/**
765 * Get the Chunk ID.
766 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
770
771/**
772 * Get the index of the page within the allocation chunk.
773 * @returns The page index.
774 * @param pPage Pointer to the physical guest page tracking structure.
775 */
776#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
777
778/**
779 * Gets the page type.
780 * @returns The page type.
781 * @param pPage Pointer to the physical guest page tracking structure.
782 */
783#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
784
785/**
786 * Sets the page type.
787 * @param pPage Pointer to the physical guest page tracking structure.
788 * @param _enmType The new page type (PGMPAGETYPE).
789 */
790#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
791
792/**
793 * Gets the page table index
794 * @returns The page table index.
795 * @param pPage Pointer to the physical guest page tracking structure.
796 */
797#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
798
799/**
800 * Sets the page table index
801 * @param pPage Pointer to the physical guest page tracking structure.
802 * @param iPte New page table index.
803 */
804#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
805
806/**
807 * Checks if the page is marked for MMIO.
808 * @returns true/false.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
812
813/**
814 * Checks if the page is backed by the ZERO page.
815 * @returns true/false.
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
819
820/**
821 * Checks if the page is backed by a SHARED page.
822 * @returns true/false.
823 * @param pPage Pointer to the physical guest page tracking structure.
824 */
825#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
826
827/**
828 * Checks if the page is ballooned.
829 * @returns true/false.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 */
832#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
833
834/**
835 * Marks the page as written to (for GMM change monitoring).
836 * @param pPage Pointer to the physical guest page tracking structure.
837 */
838#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
839
840/**
841 * Clears the written-to indicator.
842 * @param pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
845
846/**
847 * Checks if the page was marked as written-to.
848 * @returns true/false.
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
852
853/** @name PT usage values (PGMPAGE::u2PDEType).
854 *
855 * @{ */
856/** Either as a PT or PDE. */
857#define PGM_PAGE_PDE_TYPE_DONTCARE 0
858/** Must use a page table to map the range. */
859#define PGM_PAGE_PDE_TYPE_PT 1
860/** Can use a page directory entry to map the continous range. */
861#define PGM_PAGE_PDE_TYPE_PDE 2
862/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
863#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
864/** @} */
865
866/**
867 * Set the PDE type of the page
868 * @param pPage Pointer to the physical guest page tracking structure.
869 * @param uType PGM_PAGE_PDE_TYPE_*
870 */
871#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
872 do { \
873 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
874 | (((uType) & UINT8_C(0x03)) << 5); \
875 } while (0)
876
877/**
878 * Checks if the page was marked being part of a large page
879 * @returns true/false.
880 * @param pPage Pointer to the physical guest page tracking structure.
881 */
882#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
883
884/** Enabled optimized access handler tests.
885 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
886 * layout. When enabled, the compiler should normally generate more compact
887 * code.
888 */
889#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
890
891/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
892 *
893 * @remarks The values are assigned in order of priority, so we can calculate
894 * the correct state for a page with different handlers installed.
895 * @{ */
896/** No handler installed. */
897#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
898/** Monitoring is temporarily disabled. */
899#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
900/** Write access is monitored. */
901#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
902/** All access is monitored. */
903#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
904/** @} */
905
906/**
907 * Gets the physical access handler state of a page.
908 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
909 * @param pPage Pointer to the physical guest page tracking structure.
910 */
911#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
912 ( (pPage)->u16MiscY.au8[0] )
913
914/**
915 * Sets the physical access handler state of a page.
916 * @param pPage Pointer to the physical guest page tracking structure.
917 * @param _uState The new state value.
918 */
919#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
920 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
921
922/**
923 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
924 * @returns true/false
925 * @param pPage Pointer to the physical guest page tracking structure.
926 */
927#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
928 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
929
930/**
931 * Checks if the page has any active physical access handlers.
932 * @returns true/false
933 * @param pPage Pointer to the physical guest page tracking structure.
934 */
935#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
936 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
937
938
939/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
940 *
941 * @remarks The values are assigned in order of priority, so we can calculate
942 * the correct state for a page with different handlers installed.
943 * @{ */
944/** No handler installed. */
945#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
946/* 1 is reserved so the lineup is identical with the physical ones. */
947/** Write access is monitored. */
948#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
949/** All access is monitored. */
950#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
951/** @} */
952
953/**
954 * Gets the virtual access handler state of a page.
955 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
956 * @param pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
959
960/**
961 * Sets the virtual access handler state of a page.
962 * @param pPage Pointer to the physical guest page tracking structure.
963 * @param _uState The new state value.
964 */
965#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
966 do { \
967 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
968 | ((_uState) & UINT8_C(0x03)); \
969 } while (0)
970
971/**
972 * Checks if the page has any virtual access handlers.
973 * @returns true/false
974 * @param pPage Pointer to the physical guest page tracking structure.
975 */
976#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
977 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
978
979/**
980 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
981 * virtual handlers.
982 * @returns true/false
983 * @param pPage Pointer to the physical guest page tracking structure.
984 */
985#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
986 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
987
988
989/**
990 * Checks if the page has any access handlers, including temporarily disabled ones.
991 * @returns true/false
992 * @param pPage Pointer to the physical guest page tracking structure.
993 */
994#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
995# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
996 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
997#else
998# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
999 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1000 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1001#endif
1002
1003/**
1004 * Checks if the page has any active access handlers.
1005 * @returns true/false
1006 * @param pPage Pointer to the physical guest page tracking structure.
1007 */
1008#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1009# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1010 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1011#else
1012# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1013 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1014 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1015#endif
1016
1017/**
1018 * Checks if the page has any active access handlers catching all accesses.
1019 * @returns true/false
1020 * @param pPage Pointer to the physical guest page tracking structure.
1021 */
1022#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1023# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1024 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1025 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1026#else
1027# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1028 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1029 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1030#endif
1031
1032
1033/** @def PGM_PAGE_GET_TRACKING
1034 * Gets the packed shadow page pool tracking data associated with a guest page.
1035 * @returns uint16_t containing the data.
1036 * @param pPage Pointer to the physical guest page tracking structure.
1037 */
1038#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1039
1040/** @def PGM_PAGE_SET_TRACKING
1041 * Sets the packed shadow page pool tracking data associated with a guest page.
1042 * @param pPage Pointer to the physical guest page tracking structure.
1043 * @param u16TrackingData The tracking data to store.
1044 */
1045#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1046 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1047
1048/** @def PGM_PAGE_GET_TD_CREFS
1049 * Gets the @a cRefs tracking data member.
1050 * @returns cRefs.
1051 * @param pPage Pointer to the physical guest page tracking structure.
1052 */
1053#define PGM_PAGE_GET_TD_CREFS(pPage) \
1054 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1055
1056/** @def PGM_PAGE_GET_TD_IDX
1057 * Gets the @a idx tracking data member.
1058 * @returns idx.
1059 * @param pPage Pointer to the physical guest page tracking structure.
1060 */
1061#define PGM_PAGE_GET_TD_IDX(pPage) \
1062 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1063
1064
1065/** Max number of locks on a page. */
1066#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1067
1068/** Get the read lock count.
1069 * @returns count.
1070 * @param pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1073
1074/** Get the write lock count.
1075 * @returns count.
1076 * @param pPage Pointer to the physical guest page tracking structure.
1077 */
1078#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1079
1080/** Decrement the read lock counter.
1081 * @param pPage Pointer to the physical guest page tracking structure.
1082 */
1083#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1084
1085/** Decrement the write lock counter.
1086 * @param pPage Pointer to the physical guest page tracking structure.
1087 */
1088#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1089
1090/** Increment the read lock counter.
1091 * @param pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1094
1095/** Increment the write lock counter.
1096 * @param pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1099
1100
1101#if 0
1102/** Enables sanity checking of write monitoring using CRC-32. */
1103# define PGMLIVESAVERAMPAGE_WITH_CRC32
1104#endif
1105
1106/**
1107 * Per page live save tracking data.
1108 */
1109typedef struct PGMLIVESAVERAMPAGE
1110{
1111 /** Number of times it has been dirtied. */
1112 uint32_t cDirtied : 24;
1113 /** Whether it is currently dirty. */
1114 uint32_t fDirty : 1;
1115 /** Ignore the page.
1116 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1117 * deal with these after pausing the VM and DevPCI have said it bit about
1118 * remappings. */
1119 uint32_t fIgnore : 1;
1120 /** Was a ZERO page last time around. */
1121 uint32_t fZero : 1;
1122 /** Was a SHARED page last time around. */
1123 uint32_t fShared : 1;
1124 /** Whether the page is/was write monitored in a previous pass. */
1125 uint32_t fWriteMonitored : 1;
1126 /** Whether the page is/was write monitored earlier in this pass. */
1127 uint32_t fWriteMonitoredJustNow : 1;
1128 /** Bits reserved for future use. */
1129 uint32_t u2Reserved : 2;
1130#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1131 /** CRC-32 for the page. This is for internal consistency checks. */
1132 uint32_t u32Crc;
1133#endif
1134} PGMLIVESAVERAMPAGE;
1135#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1136AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1137#else
1138AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1139#endif
1140/** Pointer to the per page live save tracking data. */
1141typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1142
1143/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1144#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1145
1146
1147/**
1148 * Ram range for GC Phys to HC Phys conversion.
1149 *
1150 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1151 * conversions too, but we'll let MM handle that for now.
1152 *
1153 * This structure is used by linked lists in both GC and HC.
1154 */
1155typedef struct PGMRAMRANGE
1156{
1157 /** Start of the range. Page aligned. */
1158 RTGCPHYS GCPhys;
1159 /** Size of the range. (Page aligned of course). */
1160 RTGCPHYS cb;
1161 /** Pointer to the next RAM range - for R3. */
1162 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1163 /** Pointer to the next RAM range - for R0. */
1164 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1165 /** Pointer to the next RAM range - for RC. */
1166 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1167 /** PGM_RAM_RANGE_FLAGS_* flags. */
1168 uint32_t fFlags;
1169 /** Last address in the range (inclusive). Page aligned (-1). */
1170 RTGCPHYS GCPhysLast;
1171 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1172 R3PTRTYPE(void *) pvR3;
1173 /** Live save per page tracking data. */
1174 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1175 /** The range description. */
1176 R3PTRTYPE(const char *) pszDesc;
1177 /** Pointer to self - R0 pointer. */
1178 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1179 /** Pointer to self - RC pointer. */
1180 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1181 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1182 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1183 /** Array of physical guest page tracking structures. */
1184 PGMPAGE aPages[1];
1185} PGMRAMRANGE;
1186/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1187typedef PGMRAMRANGE *PPGMRAMRANGE;
1188
1189/** @name PGMRAMRANGE::fFlags
1190 * @{ */
1191/** The RAM range is floating around as an independent guest mapping. */
1192#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1193/** Ad hoc RAM range for an ROM mapping. */
1194#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1195/** Ad hoc RAM range for an MMIO mapping. */
1196#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1197/** Ad hoc RAM range for an MMIO2 mapping. */
1198#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1199/** @} */
1200
1201/** Tests if a RAM range is an ad hoc one or not.
1202 * @returns true/false.
1203 * @param pRam The RAM range.
1204 */
1205#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1206 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1207
1208
1209/**
1210 * Per page tracking structure for ROM image.
1211 *
1212 * A ROM image may have a shadow page, in which case we may have two pages
1213 * backing it. This structure contains the PGMPAGE for both while
1214 * PGMRAMRANGE have a copy of the active one. It is important that these
1215 * aren't out of sync in any regard other than page pool tracking data.
1216 */
1217typedef struct PGMROMPAGE
1218{
1219 /** The page structure for the virgin ROM page. */
1220 PGMPAGE Virgin;
1221 /** The page structure for the shadow RAM page. */
1222 PGMPAGE Shadow;
1223 /** The current protection setting. */
1224 PGMROMPROT enmProt;
1225 /** Live save status information. Makes use of unused alignment space. */
1226 struct
1227 {
1228 /** The previous protection value. */
1229 uint8_t u8Prot;
1230 /** Written to flag set by the handler. */
1231 bool fWrittenTo;
1232 /** Whether the shadow page is dirty or not. */
1233 bool fDirty;
1234 /** Whether it was dirtied in the recently. */
1235 bool fDirtiedRecently;
1236 } LiveSave;
1237} PGMROMPAGE;
1238AssertCompileSizeAlignment(PGMROMPAGE, 8);
1239/** Pointer to a ROM page tracking structure. */
1240typedef PGMROMPAGE *PPGMROMPAGE;
1241
1242
1243/**
1244 * A registered ROM image.
1245 *
1246 * This is needed to keep track of ROM image since they generally intrude
1247 * into a PGMRAMRANGE. It also keeps track of additional info like the
1248 * two page sets (read-only virgin and read-write shadow), the current
1249 * state of each page.
1250 *
1251 * Because access handlers cannot easily be executed in a different
1252 * context, the ROM ranges needs to be accessible and in all contexts.
1253 */
1254typedef struct PGMROMRANGE
1255{
1256 /** Pointer to the next range - R3. */
1257 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1258 /** Pointer to the next range - R0. */
1259 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1260 /** Pointer to the next range - RC. */
1261 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1262 /** Pointer alignment */
1263 RTRCPTR RCPtrAlignment;
1264 /** Address of the range. */
1265 RTGCPHYS GCPhys;
1266 /** Address of the last byte in the range. */
1267 RTGCPHYS GCPhysLast;
1268 /** Size of the range. */
1269 RTGCPHYS cb;
1270 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1271 uint32_t fFlags;
1272 /** The saved state range ID. */
1273 uint8_t idSavedState;
1274 /** Alignment padding. */
1275 uint8_t au8Alignment[3];
1276 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1277 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1278 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1279 * This is used for strictness checks. */
1280 R3PTRTYPE(const void *) pvOriginal;
1281 /** The ROM description. */
1282 R3PTRTYPE(const char *) pszDesc;
1283 /** The per page tracking structures. */
1284 PGMROMPAGE aPages[1];
1285} PGMROMRANGE;
1286/** Pointer to a ROM range. */
1287typedef PGMROMRANGE *PPGMROMRANGE;
1288
1289
1290/**
1291 * Live save per page data for an MMIO2 page.
1292 *
1293 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1294 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1295 * CRC-32 for detecting changes as well as special handling of zero pages. This
1296 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1297 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1298 * because of speed (2.5x and 6x slower).)
1299 *
1300 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1301 * save but normally is disabled. Since we can write monitore guest
1302 * accesses on our own, we only need this for host accesses. Shouldn't be
1303 * too difficult for DevVGA, VMMDev might be doable, the planned
1304 * networking fun will be fun since it involves ring-0.
1305 */
1306typedef struct PGMLIVESAVEMMIO2PAGE
1307{
1308 /** Set if the page is considered dirty. */
1309 bool fDirty;
1310 /** The number of scans this page has remained unchanged for.
1311 * Only updated for dirty pages. */
1312 uint8_t cUnchangedScans;
1313 /** Whether this page was zero at the last scan. */
1314 bool fZero;
1315 /** Alignment padding. */
1316 bool fReserved;
1317 /** CRC-32 for the first half of the page.
1318 * This is used together with u32CrcH2 to quickly detect changes in the page
1319 * during the non-final passes. */
1320 uint32_t u32CrcH1;
1321 /** CRC-32 for the second half of the page. */
1322 uint32_t u32CrcH2;
1323 /** SHA-1 for the saved page.
1324 * This is used in the final pass to skip pages without changes. */
1325 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1326} PGMLIVESAVEMMIO2PAGE;
1327/** Pointer to a live save status data for an MMIO2 page. */
1328typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1329
1330/**
1331 * A registered MMIO2 (= Device RAM) range.
1332 *
1333 * There are a few reason why we need to keep track of these
1334 * registrations. One of them is the deregistration & cleanup stuff,
1335 * while another is that the PGMRAMRANGE associated with such a region may
1336 * have to be removed from the ram range list.
1337 *
1338 * Overlapping with a RAM range has to be 100% or none at all. The pages
1339 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1340 * will be raised if a partial overlap or an overlap of ROM pages is
1341 * encountered. On an overlap we will free all the existing RAM pages and
1342 * put in the ram range pages instead.
1343 */
1344typedef struct PGMMMIO2RANGE
1345{
1346 /** The owner of the range. (a device) */
1347 PPDMDEVINSR3 pDevInsR3;
1348 /** Pointer to the ring-3 mapping of the allocation. */
1349 RTR3PTR pvR3;
1350 /** Pointer to the next range - R3. */
1351 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1352 /** Whether it's mapped or not. */
1353 bool fMapped;
1354 /** Whether it's overlapping or not. */
1355 bool fOverlapping;
1356 /** The PCI region number.
1357 * @remarks This ASSUMES that nobody will ever really need to have multiple
1358 * PCI devices with matching MMIO region numbers on a single device. */
1359 uint8_t iRegion;
1360 /** The saved state range ID. */
1361 uint8_t idSavedState;
1362 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1363 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1364 /** Live save per page tracking data. */
1365 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1366 /** The associated RAM range. */
1367 PGMRAMRANGE RamRange;
1368} PGMMMIO2RANGE;
1369/** Pointer to a MMIO2 range. */
1370typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1371
1372
1373
1374
1375/**
1376 * PGMPhysRead/Write cache entry
1377 */
1378typedef struct PGMPHYSCACHEENTRY
1379{
1380 /** R3 pointer to physical page. */
1381 R3PTRTYPE(uint8_t *) pbR3;
1382 /** GC Physical address for cache entry */
1383 RTGCPHYS GCPhys;
1384#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1385 RTGCPHYS u32Padding0; /**< alignment padding. */
1386#endif
1387} PGMPHYSCACHEENTRY;
1388
1389/**
1390 * PGMPhysRead/Write cache to reduce REM memory access overhead
1391 */
1392typedef struct PGMPHYSCACHE
1393{
1394 /** Bitmap of valid cache entries */
1395 uint64_t aEntries;
1396 /** Cache entries */
1397 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1398} PGMPHYSCACHE;
1399
1400
1401/** Pointer to an allocation chunk ring-3 mapping. */
1402typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1403/** Pointer to an allocation chunk ring-3 mapping pointer. */
1404typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1405
1406/**
1407 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1408 *
1409 * The primary tree (Core) uses the chunk id as key.
1410 */
1411typedef struct PGMCHUNKR3MAP
1412{
1413 /** The key is the chunk id. */
1414 AVLU32NODECORE Core;
1415 /** The current age thingy. */
1416 uint32_t iAge;
1417 /** The current reference count. */
1418 uint32_t volatile cRefs;
1419 /** The current permanent reference count. */
1420 uint32_t volatile cPermRefs;
1421 /** The mapping address. */
1422 void *pv;
1423} PGMCHUNKR3MAP;
1424
1425/**
1426 * Allocation chunk ring-3 mapping TLB entry.
1427 */
1428typedef struct PGMCHUNKR3MAPTLBE
1429{
1430 /** The chunk id. */
1431 uint32_t volatile idChunk;
1432#if HC_ARCH_BITS == 64
1433 uint32_t u32Padding; /**< alignment padding. */
1434#endif
1435 /** The chunk map. */
1436#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1437 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1438#else
1439 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1440#endif
1441} PGMCHUNKR3MAPTLBE;
1442/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1443typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1444
1445/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1446 * @remark Must be a power of two value. */
1447#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1448
1449/**
1450 * Allocation chunk ring-3 mapping TLB.
1451 *
1452 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1453 * At first glance this might look kinda odd since AVL trees are
1454 * supposed to give the most optimial lookup times of all trees
1455 * due to their balancing. However, take a tree with 1023 nodes
1456 * in it, that's 10 levels, meaning that most searches has to go
1457 * down 9 levels before they find what they want. This isn't fast
1458 * compared to a TLB hit. There is the factor of cache misses,
1459 * and of course the problem with trees and branch prediction.
1460 * This is why we use TLBs in front of most of the trees.
1461 *
1462 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1463 * difficult when we switch to the new inlined AVL trees (from kStuff).
1464 */
1465typedef struct PGMCHUNKR3MAPTLB
1466{
1467 /** The TLB entries. */
1468 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1469} PGMCHUNKR3MAPTLB;
1470
1471/**
1472 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1473 * @returns Chunk TLB index.
1474 * @param idChunk The Chunk ID.
1475 */
1476#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1477
1478
1479/**
1480 * Ring-3 guest page mapping TLB entry.
1481 * @remarks used in ring-0 as well at the moment.
1482 */
1483typedef struct PGMPAGER3MAPTLBE
1484{
1485 /** Address of the page. */
1486 RTGCPHYS volatile GCPhys;
1487 /** The guest page. */
1488#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1489 R3PTRTYPE(PPGMPAGE) volatile pPage;
1490#else
1491 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1492#endif
1493 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1494#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1495 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1496#else
1497 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1498#endif
1499 /** The address */
1500#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1501 R3PTRTYPE(void *) volatile pv;
1502#else
1503 R3R0PTRTYPE(void *) volatile pv;
1504#endif
1505#if HC_ARCH_BITS == 32
1506 uint32_t u32Padding; /**< alignment padding. */
1507#endif
1508} PGMPAGER3MAPTLBE;
1509/** Pointer to an entry in the HC physical TLB. */
1510typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1511
1512
1513/** The number of entries in the ring-3 guest page mapping TLB.
1514 * @remarks The value must be a power of two. */
1515#define PGM_PAGER3MAPTLB_ENTRIES 256
1516
1517/**
1518 * Ring-3 guest page mapping TLB.
1519 * @remarks used in ring-0 as well at the moment.
1520 */
1521typedef struct PGMPAGER3MAPTLB
1522{
1523 /** The TLB entries. */
1524 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1525} PGMPAGER3MAPTLB;
1526/** Pointer to the ring-3 guest page mapping TLB. */
1527typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1528
1529/**
1530 * Calculates the index of the TLB entry for the specified guest page.
1531 * @returns Physical TLB index.
1532 * @param GCPhys The guest physical address.
1533 */
1534#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1535
1536
1537/**
1538 * Mapping cache usage set entry.
1539 *
1540 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1541 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1542 * cache. If it's extended to include ring-3, well, then something will
1543 * have be changed here...
1544 */
1545typedef struct PGMMAPSETENTRY
1546{
1547 /** The mapping cache index. */
1548 uint16_t iPage;
1549 /** The number of references.
1550 * The max is UINT16_MAX - 1. */
1551 uint16_t cRefs;
1552#if HC_ARCH_BITS == 64
1553 uint32_t alignment;
1554#endif
1555 /** Pointer to the page. */
1556 RTR0PTR pvPage;
1557 /** The physical address for this entry. */
1558 RTHCPHYS HCPhys;
1559} PGMMAPSETENTRY;
1560/** Pointer to a mapping cache usage set entry. */
1561typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1562
1563/**
1564 * Mapping cache usage set.
1565 *
1566 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1567 * done during exits / traps. The set is
1568 */
1569typedef struct PGMMAPSET
1570{
1571 /** The number of occupied entries.
1572 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1573 * dynamic mappings. */
1574 uint32_t cEntries;
1575 /** The start of the current subset.
1576 * This is UINT32_MAX if no subset is currently open. */
1577 uint32_t iSubset;
1578 /** The index of the current CPU, only valid if the set is open. */
1579 int32_t iCpu;
1580 uint32_t alignment;
1581 /** The entries. */
1582 PGMMAPSETENTRY aEntries[64];
1583 /** HCPhys -> iEntry fast lookup table.
1584 * Use PGMMAPSET_HASH for hashing.
1585 * The entries may or may not be valid, check against cEntries. */
1586 uint8_t aiHashTable[128];
1587} PGMMAPSET;
1588AssertCompileSizeAlignment(PGMMAPSET, 8);
1589/** Pointer to the mapping cache set. */
1590typedef PGMMAPSET *PPGMMAPSET;
1591
1592/** PGMMAPSET::cEntries value for a closed set. */
1593#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1594
1595/** Hash function for aiHashTable. */
1596#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1597
1598/** The max fill size (strict builds). */
1599#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1600
1601
1602/** @name Context neutrual page mapper TLB.
1603 *
1604 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1605 * code is writting in a kind of context neutrual way. Time will show whether
1606 * this actually makes sense or not...
1607 *
1608 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1609 * context ends up using a global mapping cache on some platforms
1610 * (darwin).
1611 *
1612 * @{ */
1613/** @typedef PPGMPAGEMAPTLB
1614 * The page mapper TLB pointer type for the current context. */
1615/** @typedef PPGMPAGEMAPTLB
1616 * The page mapper TLB entry pointer type for the current context. */
1617/** @typedef PPGMPAGEMAPTLB
1618 * The page mapper TLB entry pointer pointer type for the current context. */
1619/** @def PGM_PAGEMAPTLB_ENTRIES
1620 * The number of TLB entries in the page mapper TLB for the current context. */
1621/** @def PGM_PAGEMAPTLB_IDX
1622 * Calculate the TLB index for a guest physical address.
1623 * @returns The TLB index.
1624 * @param GCPhys The guest physical address. */
1625/** @typedef PPGMPAGEMAP
1626 * Pointer to a page mapper unit for current context. */
1627/** @typedef PPPGMPAGEMAP
1628 * Pointer to a page mapper unit pointer for current context. */
1629#ifdef IN_RC
1630// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1631// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1632// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1633# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1634# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1635 typedef void * PPGMPAGEMAP;
1636 typedef void ** PPPGMPAGEMAP;
1637//#elif IN_RING0
1638// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1639// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1640// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1641//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1642//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1643// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1644// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1645#else
1646 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1647 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1648 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1649# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1650# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1651 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1652 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1653#endif
1654/** @} */
1655
1656
1657/** @name PGM Pool Indexes.
1658 * Aka. the unique shadow page identifier.
1659 * @{ */
1660/** NIL page pool IDX. */
1661#define NIL_PGMPOOL_IDX 0
1662/** The first normal index. */
1663#define PGMPOOL_IDX_FIRST_SPECIAL 1
1664/** Page directory (32-bit root). */
1665#define PGMPOOL_IDX_PD 1
1666/** Page Directory Pointer Table (PAE root). */
1667#define PGMPOOL_IDX_PDPT 2
1668/** AMD64 CR3 level index.*/
1669#define PGMPOOL_IDX_AMD64_CR3 3
1670/** Nested paging root.*/
1671#define PGMPOOL_IDX_NESTED_ROOT 4
1672/** The first normal index. */
1673#define PGMPOOL_IDX_FIRST 5
1674/** The last valid index. (inclusive, 14 bits) */
1675#define PGMPOOL_IDX_LAST 0x3fff
1676/** @} */
1677
1678/** The NIL index for the parent chain. */
1679#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1680#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1681
1682/**
1683 * Node in the chain linking a shadowed page to it's parent (user).
1684 */
1685#pragma pack(1)
1686typedef struct PGMPOOLUSER
1687{
1688 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1689 uint16_t iNext;
1690 /** The user page index. */
1691 uint16_t iUser;
1692 /** Index into the user table. */
1693 uint32_t iUserTable;
1694} PGMPOOLUSER, *PPGMPOOLUSER;
1695typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1696#pragma pack()
1697
1698
1699/** The NIL index for the phys ext chain. */
1700#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1701/** The NIL pte index for a phys ext chain slot. */
1702#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1703
1704/**
1705 * Node in the chain of physical cross reference extents.
1706 * @todo Calling this an 'extent' is not quite right, find a better name.
1707 * @todo find out the optimal size of the aidx array
1708 */
1709#pragma pack(1)
1710typedef struct PGMPOOLPHYSEXT
1711{
1712 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1713 uint16_t iNext;
1714 /** Alignment. */
1715 uint16_t u16Align;
1716 /** The user page index. */
1717 uint16_t aidx[3];
1718 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1719 uint16_t apte[3];
1720} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1721typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1722#pragma pack()
1723
1724
1725/**
1726 * The kind of page that's being shadowed.
1727 */
1728typedef enum PGMPOOLKIND
1729{
1730 /** The virtual invalid 0 entry. */
1731 PGMPOOLKIND_INVALID = 0,
1732 /** The entry is free (=unused). */
1733 PGMPOOLKIND_FREE,
1734
1735 /** Shw: 32-bit page table; Gst: no paging */
1736 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1737 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1738 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1739 /** Shw: 32-bit page table; Gst: 4MB page. */
1740 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1741 /** Shw: PAE page table; Gst: no paging */
1742 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1743 /** Shw: PAE page table; Gst: 32-bit page table. */
1744 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1745 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1746 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1747 /** Shw: PAE page table; Gst: PAE page table. */
1748 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1749 /** Shw: PAE page table; Gst: 2MB page. */
1750 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1751
1752 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1753 PGMPOOLKIND_32BIT_PD,
1754 /** Shw: 32-bit page directory. Gst: no paging. */
1755 PGMPOOLKIND_32BIT_PD_PHYS,
1756 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1757 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1758 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1759 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1760 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1761 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1762 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1763 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1764 /** Shw: PAE page directory; Gst: PAE page directory. */
1765 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1766 /** Shw: PAE page directory; Gst: no paging. */
1767 PGMPOOLKIND_PAE_PD_PHYS,
1768
1769 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1770 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1771 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1772 PGMPOOLKIND_PAE_PDPT,
1773 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1774 PGMPOOLKIND_PAE_PDPT_PHYS,
1775
1776 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1777 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1778 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1779 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1780 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1781 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1782 /** Shw: 64-bit page directory table; Gst: no paging */
1783 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1784
1785 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1786 PGMPOOLKIND_64BIT_PML4,
1787
1788 /** Shw: EPT page directory pointer table; Gst: no paging */
1789 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1790 /** Shw: EPT page directory table; Gst: no paging */
1791 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1792 /** Shw: EPT page table; Gst: no paging */
1793 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1794
1795 /** Shw: Root Nested paging table. */
1796 PGMPOOLKIND_ROOT_NESTED,
1797
1798 /** The last valid entry. */
1799 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1800} PGMPOOLKIND;
1801
1802/**
1803 * The access attributes of the page; only applies to big pages.
1804 */
1805typedef enum
1806{
1807 PGMPOOLACCESS_DONTCARE = 0,
1808 PGMPOOLACCESS_USER_RW,
1809 PGMPOOLACCESS_USER_R,
1810 PGMPOOLACCESS_USER_RW_NX,
1811 PGMPOOLACCESS_USER_R_NX,
1812 PGMPOOLACCESS_SUPERVISOR_RW,
1813 PGMPOOLACCESS_SUPERVISOR_R,
1814 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1815 PGMPOOLACCESS_SUPERVISOR_R_NX
1816} PGMPOOLACCESS;
1817
1818/**
1819 * The tracking data for a page in the pool.
1820 */
1821typedef struct PGMPOOLPAGE
1822{
1823 /** AVL node code with the (R3) physical address of this page. */
1824 AVLOHCPHYSNODECORE Core;
1825 /** Pointer to the R3 mapping of the page. */
1826#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1827 R3PTRTYPE(void *) pvPageR3;
1828#else
1829 R3R0PTRTYPE(void *) pvPageR3;
1830#endif
1831 /** The guest physical address. */
1832#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1833 uint32_t Alignment0;
1834#endif
1835 RTGCPHYS GCPhys;
1836
1837 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1838 RTGCPTR pvLastAccessHandlerRip;
1839 RTGCPTR pvLastAccessHandlerFault;
1840 uint64_t cLastAccessHandlerCount;
1841
1842 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1843 uint8_t enmKind;
1844 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1845 uint8_t enmAccess;
1846 /** The index of this page. */
1847 uint16_t idx;
1848 /** The next entry in the list this page currently resides in.
1849 * It's either in the free list or in the GCPhys hash. */
1850 uint16_t iNext;
1851 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1852 uint16_t iUserHead;
1853 /** The number of present entries. */
1854 uint16_t cPresent;
1855 /** The first entry in the table which is present. */
1856 uint16_t iFirstPresent;
1857 /** The number of modifications to the monitored page. */
1858 uint16_t cModifications;
1859 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1860 uint16_t iModifiedNext;
1861 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1862 uint16_t iModifiedPrev;
1863 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1864 uint16_t iMonitoredNext;
1865 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1866 uint16_t iMonitoredPrev;
1867 /** The next page in the age list. */
1868 uint16_t iAgeNext;
1869 /** The previous page in the age list. */
1870 uint16_t iAgePrev;
1871 /** Used to indicate that the page is zeroed. */
1872 bool fZeroed;
1873 /** Used to indicate that a PT has non-global entries. */
1874 bool fSeenNonGlobal;
1875 /** Used to indicate that we're monitoring writes to the guest page. */
1876 bool fMonitored;
1877 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1878 * (All pages are in the age list.) */
1879 bool fCached;
1880 /** This is used by the R3 access handlers when invoked by an async thread.
1881 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1882 bool volatile fReusedFlushPending;
1883 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1884 bool fDirty;
1885
1886 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1887 uint32_t cLocked;
1888 uint32_t idxDirty;
1889 RTGCPTR pvDirtyFault;
1890} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1891/** Pointer to a const pool page. */
1892typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1893
1894
1895/** The hash table size. */
1896# define PGMPOOL_HASH_SIZE 0x40
1897/** The hash function. */
1898# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1899
1900
1901/**
1902 * The shadow page pool instance data.
1903 *
1904 * It's all one big allocation made at init time, except for the
1905 * pages that is. The user nodes follows immediatly after the
1906 * page structures.
1907 */
1908typedef struct PGMPOOL
1909{
1910 /** The VM handle - R3 Ptr. */
1911 PVMR3 pVMR3;
1912 /** The VM handle - R0 Ptr. */
1913 PVMR0 pVMR0;
1914 /** The VM handle - RC Ptr. */
1915 PVMRC pVMRC;
1916 /** The max pool size. This includes the special IDs. */
1917 uint16_t cMaxPages;
1918 /** The current pool size. */
1919 uint16_t cCurPages;
1920 /** The head of the free page list. */
1921 uint16_t iFreeHead;
1922 /* Padding. */
1923 uint16_t u16Padding;
1924 /** Head of the chain of free user nodes. */
1925 uint16_t iUserFreeHead;
1926 /** The number of user nodes we've allocated. */
1927 uint16_t cMaxUsers;
1928 /** The number of present page table entries in the entire pool. */
1929 uint32_t cPresent;
1930 /** Pointer to the array of user nodes - RC pointer. */
1931 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1932 /** Pointer to the array of user nodes - R3 pointer. */
1933 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1934 /** Pointer to the array of user nodes - R0 pointer. */
1935 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1936 /** Head of the chain of free phys ext nodes. */
1937 uint16_t iPhysExtFreeHead;
1938 /** The number of user nodes we've allocated. */
1939 uint16_t cMaxPhysExts;
1940 /** Pointer to the array of physical xref extent - RC pointer. */
1941 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1942 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1943 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1944 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1945 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1946 /** Hash table for GCPhys addresses. */
1947 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1948 /** The head of the age list. */
1949 uint16_t iAgeHead;
1950 /** The tail of the age list. */
1951 uint16_t iAgeTail;
1952 /** Set if the cache is enabled. */
1953 bool fCacheEnabled;
1954 /** Alignment padding. */
1955 bool afPadding1[3];
1956 /** Head of the list of modified pages. */
1957 uint16_t iModifiedHead;
1958 /** The current number of modified pages. */
1959 uint16_t cModifiedPages;
1960 /** Access handler, RC. */
1961 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1962 /** Access handler, R0. */
1963 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1964 /** Access handler, R3. */
1965 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1966 /** The access handler description (R3 ptr). */
1967 R3PTRTYPE(const char *) pszAccessHandler;
1968# if HC_ARCH_BITS == 32
1969 /** Alignment padding. */
1970 uint32_t u32Padding2;
1971# endif
1972 /* Next available slot. */
1973 uint32_t idxFreeDirtyPage;
1974 /* Number of active dirty pages. */
1975 uint32_t cDirtyPages;
1976 /* Array of current dirty pgm pool page indices. */
1977 uint16_t aIdxDirtyPages[16];
1978 uint64_t aDirtyPages[16][512];
1979 /** The number of pages currently in use. */
1980 uint16_t cUsedPages;
1981#ifdef VBOX_WITH_STATISTICS
1982 /** The high water mark for cUsedPages. */
1983 uint16_t cUsedPagesHigh;
1984 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1985 /** Profiling pgmPoolAlloc(). */
1986 STAMPROFILEADV StatAlloc;
1987 /** Profiling pgmR3PoolClearDoIt(). */
1988 STAMPROFILE StatClearAll;
1989 /** Profiling pgmR3PoolReset(). */
1990 STAMPROFILE StatR3Reset;
1991 /** Profiling pgmPoolFlushPage(). */
1992 STAMPROFILE StatFlushPage;
1993 /** Profiling pgmPoolFree(). */
1994 STAMPROFILE StatFree;
1995 /** Counting explicit flushes by PGMPoolFlushPage(). */
1996 STAMCOUNTER StatForceFlushPage;
1997 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1998 STAMCOUNTER StatForceFlushDirtyPage;
1999 /** Counting flushes for reused pages. */
2000 STAMCOUNTER StatForceFlushReused;
2001 /** Profiling time spent zeroing pages. */
2002 STAMPROFILE StatZeroPage;
2003 /** Profiling of pgmPoolTrackDeref. */
2004 STAMPROFILE StatTrackDeref;
2005 /** Profiling pgmTrackFlushGCPhysPT. */
2006 STAMPROFILE StatTrackFlushGCPhysPT;
2007 /** Profiling pgmTrackFlushGCPhysPTs. */
2008 STAMPROFILE StatTrackFlushGCPhysPTs;
2009 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2010 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2011 /** Number of times we've been out of user records. */
2012 STAMCOUNTER StatTrackFreeUpOneUser;
2013 /** Nr of flushed entries. */
2014 STAMCOUNTER StatTrackFlushEntry;
2015 /** Nr of updated entries. */
2016 STAMCOUNTER StatTrackFlushEntryKeep;
2017 /** Profiling deref activity related tracking GC physical pages. */
2018 STAMPROFILE StatTrackDerefGCPhys;
2019 /** Number of linear searches for a HCPhys in the ram ranges. */
2020 STAMCOUNTER StatTrackLinearRamSearches;
2021 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2022 STAMCOUNTER StamTrackPhysExtAllocFailures;
2023 /** Profiling the RC/R0 access handler. */
2024 STAMPROFILE StatMonitorRZ;
2025 /** Times we've failed interpreting the instruction. */
2026 STAMCOUNTER StatMonitorRZEmulateInstr;
2027 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2028 STAMPROFILE StatMonitorRZFlushPage;
2029 /* Times we've detected a page table reinit. */
2030 STAMCOUNTER StatMonitorRZFlushReinit;
2031 /** Counting flushes for pages that are modified too often. */
2032 STAMCOUNTER StatMonitorRZFlushModOverflow;
2033 /** Times we've detected fork(). */
2034 STAMCOUNTER StatMonitorRZFork;
2035 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2036 STAMPROFILE StatMonitorRZHandled;
2037 /** Times we've failed interpreting a patch code instruction. */
2038 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2039 /** Times we've failed interpreting a patch code instruction during flushing. */
2040 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2041 /** The number of times we've seen rep prefixes we can't handle. */
2042 STAMCOUNTER StatMonitorRZRepPrefix;
2043 /** Profiling the REP STOSD cases we've handled. */
2044 STAMPROFILE StatMonitorRZRepStosd;
2045 /** Nr of handled PT faults. */
2046 STAMCOUNTER StatMonitorRZFaultPT;
2047 /** Nr of handled PD faults. */
2048 STAMCOUNTER StatMonitorRZFaultPD;
2049 /** Nr of handled PDPT faults. */
2050 STAMCOUNTER StatMonitorRZFaultPDPT;
2051 /** Nr of handled PML4 faults. */
2052 STAMCOUNTER StatMonitorRZFaultPML4;
2053
2054 /** Profiling the R3 access handler. */
2055 STAMPROFILE StatMonitorR3;
2056 /** Times we've failed interpreting the instruction. */
2057 STAMCOUNTER StatMonitorR3EmulateInstr;
2058 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2059 STAMPROFILE StatMonitorR3FlushPage;
2060 /* Times we've detected a page table reinit. */
2061 STAMCOUNTER StatMonitorR3FlushReinit;
2062 /** Counting flushes for pages that are modified too often. */
2063 STAMCOUNTER StatMonitorR3FlushModOverflow;
2064 /** Times we've detected fork(). */
2065 STAMCOUNTER StatMonitorR3Fork;
2066 /** Profiling the R3 access we've handled (except REP STOSD). */
2067 STAMPROFILE StatMonitorR3Handled;
2068 /** The number of times we've seen rep prefixes we can't handle. */
2069 STAMCOUNTER StatMonitorR3RepPrefix;
2070 /** Profiling the REP STOSD cases we've handled. */
2071 STAMPROFILE StatMonitorR3RepStosd;
2072 /** Nr of handled PT faults. */
2073 STAMCOUNTER StatMonitorR3FaultPT;
2074 /** Nr of handled PD faults. */
2075 STAMCOUNTER StatMonitorR3FaultPD;
2076 /** Nr of handled PDPT faults. */
2077 STAMCOUNTER StatMonitorR3FaultPDPT;
2078 /** Nr of handled PML4 faults. */
2079 STAMCOUNTER StatMonitorR3FaultPML4;
2080 /** The number of times we're called in an async thread an need to flush. */
2081 STAMCOUNTER StatMonitorR3Async;
2082 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2083 STAMCOUNTER StatResetDirtyPages;
2084 /** Times we've called pgmPoolAddDirtyPage. */
2085 STAMCOUNTER StatDirtyPage;
2086 /** Times we've had to flush duplicates for dirty page management. */
2087 STAMCOUNTER StatDirtyPageDupFlush;
2088 /** Times we've had to flush because of overflow. */
2089 STAMCOUNTER StatDirtyPageOverFlowFlush;
2090
2091 /** The high wather mark for cModifiedPages. */
2092 uint16_t cModifiedPagesHigh;
2093 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2094
2095 /** The number of cache hits. */
2096 STAMCOUNTER StatCacheHits;
2097 /** The number of cache misses. */
2098 STAMCOUNTER StatCacheMisses;
2099 /** The number of times we've got a conflict of 'kind' in the cache. */
2100 STAMCOUNTER StatCacheKindMismatches;
2101 /** Number of times we've been out of pages. */
2102 STAMCOUNTER StatCacheFreeUpOne;
2103 /** The number of cacheable allocations. */
2104 STAMCOUNTER StatCacheCacheable;
2105 /** The number of uncacheable allocations. */
2106 STAMCOUNTER StatCacheUncacheable;
2107#else
2108 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2109#endif
2110 /** The AVL tree for looking up a page by its HC physical address. */
2111 AVLOHCPHYSTREE HCPhysTree;
2112 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2113 /** Array of pages. (cMaxPages in length)
2114 * The Id is the index into thist array.
2115 */
2116 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2117} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2118AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2119AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2120AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2121#ifdef VBOX_WITH_STATISTICS
2122AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2123#endif
2124AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2125
2126
2127/** @def PGMPOOL_PAGE_2_PTR
2128 * Maps a pool page pool into the current context.
2129 *
2130 * @returns VBox status code.
2131 * @param pVM The VM handle.
2132 * @param pPage The pool page.
2133 *
2134 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2135 * small page window employeed by that function. Be careful.
2136 * @remark There is no need to assert on the result.
2137 */
2138#if defined(IN_RC)
2139# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2140#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2141# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2142#elif defined(VBOX_STRICT)
2143# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2144DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2145{
2146 Assert(pPage && pPage->pvPageR3);
2147 return pPage->pvPageR3;
2148}
2149#else
2150# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2151#endif
2152
2153/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2154 * Maps a pool page pool into the current context.
2155 *
2156 * @returns VBox status code.
2157 * @param pPGM Pointer to the PGM instance data.
2158 * @param pPage The pool page.
2159 *
2160 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2161 * small page window employeed by that function. Be careful.
2162 * @remark There is no need to assert on the result.
2163 */
2164#if defined(IN_RC)
2165# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2166#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2167# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2168#else
2169# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2170#endif
2171
2172/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2173 * Maps a pool page pool into the current context.
2174 *
2175 * @returns VBox status code.
2176 * @param pPGM Pointer to the PGMCPU instance data.
2177 * @param pPage The pool page.
2178 *
2179 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2180 * small page window employeed by that function. Be careful.
2181 * @remark There is no need to assert on the result.
2182 */
2183#if defined(IN_RC)
2184# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2185#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2186# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2187#else
2188# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2189#endif
2190
2191
2192/** @name Per guest page tracking data.
2193 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2194 * is to use more bits for it and split it up later on. But for now we'll play
2195 * safe and change as little as possible.
2196 *
2197 * The 16-bit word has two parts:
2198 *
2199 * The first 14-bit forms the @a idx field. It is either the index of a page in
2200 * the shadow page pool, or and index into the extent list.
2201 *
2202 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2203 * shadow page pool references to the page. If cRefs equals
2204 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2205 * (misnomer) table and not the shadow page pool.
2206 *
2207 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2208 * the 16-bit word.
2209 *
2210 * @{ */
2211/** The shift count for getting to the cRefs part. */
2212#define PGMPOOL_TD_CREFS_SHIFT 14
2213/** The mask applied after shifting the tracking data down by
2214 * PGMPOOL_TD_CREFS_SHIFT. */
2215#define PGMPOOL_TD_CREFS_MASK 0x3
2216/** The cRef value used to indiciate that the idx is the head of a
2217 * physical cross reference list. */
2218#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2219/** The shift used to get idx. */
2220#define PGMPOOL_TD_IDX_SHIFT 0
2221/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2222#define PGMPOOL_TD_IDX_MASK 0x3fff
2223/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2224 * simply too many mappings of this page. */
2225#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2226
2227/** @def PGMPOOL_TD_MAKE
2228 * Makes a 16-bit tracking data word.
2229 *
2230 * @returns tracking data.
2231 * @param cRefs The @a cRefs field. Must be within bounds!
2232 * @param idx The @a idx field. Must also be within bounds! */
2233#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2234
2235/** @def PGMPOOL_TD_GET_CREFS
2236 * Get the @a cRefs field from a tracking data word.
2237 *
2238 * @returns The @a cRefs field
2239 * @param u16 The tracking data word. */
2240#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2241
2242/** @def PGMPOOL_TD_GET_IDX
2243 * Get the @a idx field from a tracking data word.
2244 *
2245 * @returns The @a idx field
2246 * @param u16 The tracking data word. */
2247#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2248/** @} */
2249
2250
2251/**
2252 * Trees are using self relative offsets as pointers.
2253 * So, all its data, including the root pointer, must be in the heap for HC and GC
2254 * to have the same layout.
2255 */
2256typedef struct PGMTREES
2257{
2258 /** Physical access handlers (AVL range+offsetptr tree). */
2259 AVLROGCPHYSTREE PhysHandlers;
2260 /** Virtual access handlers (AVL range + GC ptr tree). */
2261 AVLROGCPTRTREE VirtHandlers;
2262 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2263 AVLROGCPHYSTREE PhysToVirtHandlers;
2264 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2265 AVLROGCPTRTREE HyperVirtHandlers;
2266} PGMTREES;
2267/** Pointer to PGM trees. */
2268typedef PGMTREES *PPGMTREES;
2269
2270
2271/** @name Paging mode macros
2272 * @{ */
2273#ifdef IN_RC
2274# define PGM_CTX(a,b) a##RC##b
2275# define PGM_CTX_STR(a,b) a "GC" b
2276# define PGM_CTX_DECL(type) VMMRCDECL(type)
2277#else
2278# ifdef IN_RING3
2279# define PGM_CTX(a,b) a##R3##b
2280# define PGM_CTX_STR(a,b) a "R3" b
2281# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2282# else
2283# define PGM_CTX(a,b) a##R0##b
2284# define PGM_CTX_STR(a,b) a "R0" b
2285# define PGM_CTX_DECL(type) VMMDECL(type)
2286# endif
2287#endif
2288
2289#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2290#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2291#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2292#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2293#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2294#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2295#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2296#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2297#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2298#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2299#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2300#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2301#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2302#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2303#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2304#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2305#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2306
2307#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2308#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2309#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2310#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2311#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2312#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2313#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2314#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2315#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2316#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2317#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2318#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2319#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2320#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2321#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2322#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2323#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2324
2325/* Shw_Gst */
2326#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2327#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2328#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2329#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2330#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2331#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2332#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2333#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2334#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2335#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2336#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2337#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2338#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2339#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2340#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2341#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2342#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2343#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2344#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2345
2346#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2347#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2348#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2349#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2350#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2351#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2352#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2353#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2354#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2355#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2356#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2357#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2358#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2359#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2360#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2361#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2362#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2363#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2364#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2365#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2366#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2367#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2368#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2369#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2370#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2371#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2372#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2373#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2374#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2375#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2376#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2377#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2378#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2379#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2380#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2381#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2382#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2383
2384#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2385#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2386/** @} */
2387
2388/**
2389 * Data for each paging mode.
2390 */
2391typedef struct PGMMODEDATA
2392{
2393 /** The guest mode type. */
2394 uint32_t uGstType;
2395 /** The shadow mode type. */
2396 uint32_t uShwType;
2397
2398 /** @name Function pointers for Shadow paging.
2399 * @{
2400 */
2401 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2402 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2403 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2404 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2405
2406 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2407 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2408
2409 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2410 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2411 /** @} */
2412
2413 /** @name Function pointers for Guest paging.
2414 * @{
2415 */
2416 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2417 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2418 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2419 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2420 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2421 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2422 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2423 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2424 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2425 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2426 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2427 /** @} */
2428
2429 /** @name Function pointers for Both Shadow and Guest paging.
2430 * @{
2431 */
2432 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2433 /* no pfnR3BthTrap0eHandler */
2434 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2435 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2436 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2437 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2438 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2439#ifdef VBOX_STRICT
2440 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2441#endif
2442 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2443 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2444
2445 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2446 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2447 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2448 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2449 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2450 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2451#ifdef VBOX_STRICT
2452 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2453#endif
2454 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2455 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2456
2457 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2458 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2459 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2460 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2461 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2462 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2463#ifdef VBOX_STRICT
2464 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2465#endif
2466 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2467 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2468 /** @} */
2469} PGMMODEDATA, *PPGMMODEDATA;
2470
2471
2472
2473/**
2474 * Converts a PGM pointer into a VM pointer.
2475 * @returns Pointer to the VM structure the PGM is part of.
2476 * @param pPGM Pointer to PGM instance data.
2477 */
2478#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2479
2480/**
2481 * PGM Data (part of VM)
2482 */
2483typedef struct PGM
2484{
2485 /** Offset to the VM structure. */
2486 RTINT offVM;
2487 /** Offset of the PGMCPU structure relative to VMCPU. */
2488 RTINT offVCpuPGM;
2489
2490 /** @cfgm{RamPreAlloc, boolean, false}
2491 * Indicates whether the base RAM should all be allocated before starting
2492 * the VM (default), or if it should be allocated when first written to.
2493 */
2494 bool fRamPreAlloc;
2495 /** Indicates whether write monitoring is currently in use.
2496 * This is used to prevent conflicts between live saving and page sharing
2497 * detection. */
2498 bool fPhysWriteMonitoringEngaged;
2499 /** Alignment padding. */
2500 bool afAlignment0[2];
2501
2502 /*
2503 * This will be redefined at least two more times before we're done, I'm sure.
2504 * The current code is only to get on with the coding.
2505 * - 2004-06-10: initial version, bird.
2506 * - 2004-07-02: 1st time, bird.
2507 * - 2004-10-18: 2nd time, bird.
2508 * - 2005-07-xx: 3rd time, bird.
2509 */
2510
2511 /** The host paging mode. (This is what SUPLib reports.) */
2512 SUPPAGINGMODE enmHostMode;
2513
2514 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2515 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2516 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2517 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2518
2519 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2520 RTGCPHYS GCPhys4MBPSEMask;
2521
2522 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2523 * This is sorted by physical address and contains no overlapping ranges. */
2524 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2525 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2526 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2527 /** RC pointer corresponding to PGM::pRamRangesR3. */
2528 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2529 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2530 * range is linked or unlinked. */
2531 uint32_t volatile idRamRangesGen;
2532
2533 /** Pointer to the list of ROM ranges - for R3.
2534 * This is sorted by physical address and contains no overlapping ranges. */
2535 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2536 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2537 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2538 /** RC pointer corresponding to PGM::pRomRangesR3. */
2539 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2540#if HC_ARCH_BITS == 64
2541 /** Alignment padding. */
2542 RTRCPTR GCPtrPadding2;
2543#endif
2544
2545 /** Pointer to the list of MMIO2 ranges - for R3.
2546 * Registration order. */
2547 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2548
2549 /** PGM offset based trees - R3 Ptr. */
2550 R3PTRTYPE(PPGMTREES) pTreesR3;
2551 /** PGM offset based trees - R0 Ptr. */
2552 R0PTRTYPE(PPGMTREES) pTreesR0;
2553 /** PGM offset based trees - RC Ptr. */
2554 RCPTRTYPE(PPGMTREES) pTreesRC;
2555
2556 /** Linked list of GC mappings - for RC.
2557 * The list is sorted ascending on address.
2558 */
2559 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2560 /** Linked list of GC mappings - for HC.
2561 * The list is sorted ascending on address.
2562 */
2563 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2564 /** Linked list of GC mappings - for R0.
2565 * The list is sorted ascending on address.
2566 */
2567 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2568
2569 /** Pointer to the 5 page CR3 content mapping.
2570 * The first page is always the CR3 (in some form) while the 4 other pages
2571 * are used of the PDs in PAE mode. */
2572 RTGCPTR GCPtrCR3Mapping;
2573#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2574 uint32_t u32Alignment1;
2575#endif
2576
2577 /** Indicates that PGMR3FinalizeMappings has been called and that further
2578 * PGMR3MapIntermediate calls will be rejected. */
2579 bool fFinalizedMappings;
2580 /** If set no conflict checks are required. */
2581 bool fMappingsFixed;
2582 /** If set if restored as fixed but we were unable to re-fixate at the old
2583 * location because of room or address incompatibilities. */
2584 bool fMappingsFixedRestored;
2585 /** If set, then no mappings are put into the shadow page table.
2586 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2587 bool fMappingsDisabled;
2588 /** Size of fixed mapping.
2589 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2590 uint32_t cbMappingFixed;
2591 /** Base address (GC) of fixed mapping.
2592 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2593 RTGCPTR GCPtrMappingFixed;
2594 /** The address of the previous RAM range mapping. */
2595 RTGCPTR GCPtrPrevRamRangeMapping;
2596
2597 /** @name Intermediate Context
2598 * @{ */
2599 /** Pointer to the intermediate page directory - Normal. */
2600 R3PTRTYPE(PX86PD) pInterPD;
2601 /** Pointer to the intermedate page tables - Normal.
2602 * There are two page tables, one for the identity mapping and one for
2603 * the host context mapping (of the core code). */
2604 R3PTRTYPE(PX86PT) apInterPTs[2];
2605 /** Pointer to the intermedate page tables - PAE. */
2606 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2607 /** Pointer to the intermedate page directory - PAE. */
2608 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2609 /** Pointer to the intermedate page directory - PAE. */
2610 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2611 /** Pointer to the intermedate page-map level 4 - AMD64. */
2612 R3PTRTYPE(PX86PML4) pInterPaePML4;
2613 /** Pointer to the intermedate page directory - AMD64. */
2614 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2615 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2616 RTHCPHYS HCPhysInterPD;
2617 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2618 RTHCPHYS HCPhysInterPaePDPT;
2619 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2620 RTHCPHYS HCPhysInterPaePML4;
2621 /** @} */
2622
2623 /** Base address of the dynamic page mapping area.
2624 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2625 */
2626 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2627 /** The index of the last entry used in the dynamic page mapping area. */
2628 RTUINT iDynPageMapLast;
2629 /** Cache containing the last entries in the dynamic page mapping area.
2630 * The cache size is covering half of the mapping area. */
2631 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2632 /** Keep a lock counter for the full (!) mapping area. */
2633 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2634
2635 /** The address of the ring-0 mapping cache if we're making use of it. */
2636 RTR0PTR pvR0DynMapUsed;
2637#if HC_ARCH_BITS == 32
2638 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2639 uint32_t u32Alignment2;
2640#endif
2641
2642 /** PGM critical section.
2643 * This protects the physical & virtual access handlers, ram ranges,
2644 * and the page flag updating (some of it anyway).
2645 */
2646 PDMCRITSECT CritSect;
2647
2648 /** Pointer to SHW+GST mode data (function pointers).
2649 * The index into this table is made up from */
2650 R3PTRTYPE(PPGMMODEDATA) paModeData;
2651
2652 /** Shadow Page Pool - R3 Ptr. */
2653 R3PTRTYPE(PPGMPOOL) pPoolR3;
2654 /** Shadow Page Pool - R0 Ptr. */
2655 R0PTRTYPE(PPGMPOOL) pPoolR0;
2656 /** Shadow Page Pool - RC Ptr. */
2657 RCPTRTYPE(PPGMPOOL) pPoolRC;
2658
2659 /** We're not in a state which permits writes to guest memory.
2660 * (Only used in strict builds.) */
2661 bool fNoMorePhysWrites;
2662 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2663 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2664
2665 /**
2666 * Data associated with managing the ring-3 mappings of the allocation chunks.
2667 */
2668 struct
2669 {
2670 /** The chunk tree, ordered by chunk id. */
2671#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2672 R3PTRTYPE(PAVLU32NODECORE) pTree;
2673#else
2674 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2675#endif
2676#if HC_ARCH_BITS == 32
2677 uint32_t u32Alignment;
2678#endif
2679 /** The chunk mapping TLB. */
2680 PGMCHUNKR3MAPTLB Tlb;
2681 /** The number of mapped chunks. */
2682 uint32_t c;
2683 /** The maximum number of mapped chunks.
2684 * @cfgm PGM/MaxRing3Chunks */
2685 uint32_t cMax;
2686 /** The current time. */
2687 uint32_t iNow;
2688 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2689 uint32_t AgeingCountdown;
2690 } ChunkR3Map;
2691
2692 /**
2693 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2694 */
2695 PGMPAGER3MAPTLB PhysTlbHC;
2696
2697 /** @name The zero page.
2698 * @{ */
2699 /** The host physical address of the zero page. */
2700 RTHCPHYS HCPhysZeroPg;
2701 /** The ring-3 mapping of the zero page. */
2702 RTR3PTR pvZeroPgR3;
2703 /** The ring-0 mapping of the zero page. */
2704 RTR0PTR pvZeroPgR0;
2705 /** The GC mapping of the zero page. */
2706 RTGCPTR pvZeroPgRC;
2707 /** @}*/
2708
2709 /** The number of handy pages. */
2710 uint32_t cHandyPages;
2711
2712 /** The number of large handy pages. */
2713 uint32_t cLargeHandyPages;
2714
2715 /**
2716 * Array of handy pages.
2717 *
2718 * This array is used in a two way communication between pgmPhysAllocPage
2719 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2720 * an intermediary.
2721 *
2722 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2723 * (The current size of 32 pages, means 128 KB of handy memory.)
2724 */
2725 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2726
2727 /**
2728 * Array of large handy pages. (currently size 1)
2729 *
2730 * This array is used in a two way communication between pgmPhysAllocLargePage
2731 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2732 * an intermediary.
2733 */
2734 GMMPAGEDESC aLargeHandyPage[1];
2735
2736 /**
2737 * Live save data.
2738 */
2739 struct
2740 {
2741 /** Per type statistics. */
2742 struct
2743 {
2744 /** The number of ready pages. */
2745 uint32_t cReadyPages;
2746 /** The number of dirty pages. */
2747 uint32_t cDirtyPages;
2748 /** The number of ready zero pages. */
2749 uint32_t cZeroPages;
2750 /** The number of write monitored pages. */
2751 uint32_t cMonitoredPages;
2752 } Rom,
2753 Mmio2,
2754 Ram;
2755 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2756 uint32_t cIgnoredPages;
2757 /** Indicates that a live save operation is active. */
2758 bool fActive;
2759 /** Padding. */
2760 bool afReserved[2];
2761 /** The next history index. */
2762 uint8_t iDirtyPagesHistory;
2763 /** History of the total amount of dirty pages. */
2764 uint32_t acDirtyPagesHistory[64];
2765 /** Short term dirty page average. */
2766 uint32_t cDirtyPagesShort;
2767 /** Long term dirty page average. */
2768 uint32_t cDirtyPagesLong;
2769 /** The number of saved pages. This is used to get some kind of estimate of the
2770 * link speed so we can decide when we're done. It is reset after the first
2771 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2772 * zero pages. */
2773 uint64_t cSavedPages;
2774 /** The nanosecond timestamp when cSavedPages was 0. */
2775 uint64_t uSaveStartNS;
2776 /** Pages per second (for statistics). */
2777 uint32_t cPagesPerSecond;
2778 uint32_t cAlignment;
2779 } LiveSave;
2780
2781 /** @name Error injection.
2782 * @{ */
2783 /** Inject handy page allocation errors pretending we're completely out of
2784 * memory. */
2785 bool volatile fErrInjHandyPages;
2786 /** Padding. */
2787 bool afReserved[3];
2788 /** @} */
2789
2790 /** @name Release Statistics
2791 * @{ */
2792 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2793 uint32_t cPrivatePages; /**< The number of private pages. */
2794 uint32_t cSharedPages; /**< The number of shared pages. */
2795 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
2796 uint32_t cZeroPages; /**< The number of zero backed pages. */
2797 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2798 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2799 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2800 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2801 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2802 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
2803 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
2804 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
2805/* uint32_t aAlignment4[1]; */
2806
2807 /** The number of times we were forced to change the hypervisor region location. */
2808 STAMCOUNTER cRelocations;
2809
2810 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
2811 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
2812 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2813 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
2814 /** @} */
2815
2816#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2817 /* R3 only: */
2818 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2819 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2820
2821 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2822 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2823 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2824 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2825 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2826 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2827 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2828 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2829 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2830 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2831 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2832 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2833 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2834 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2835 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2836 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2837 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2838 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2839 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2840 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2841/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2842 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2843 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2844/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2845
2846 /* RC only: */
2847 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2848 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2849 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2850 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2851
2852 STAMCOUNTER StatRZPhysRead;
2853 STAMCOUNTER StatRZPhysReadBytes;
2854 STAMCOUNTER StatRZPhysWrite;
2855 STAMCOUNTER StatRZPhysWriteBytes;
2856 STAMCOUNTER StatR3PhysRead;
2857 STAMCOUNTER StatR3PhysReadBytes;
2858 STAMCOUNTER StatR3PhysWrite;
2859 STAMCOUNTER StatR3PhysWriteBytes;
2860 STAMCOUNTER StatRCPhysRead;
2861 STAMCOUNTER StatRCPhysReadBytes;
2862 STAMCOUNTER StatRCPhysWrite;
2863 STAMCOUNTER StatRCPhysWriteBytes;
2864
2865 STAMCOUNTER StatRZPhysSimpleRead;
2866 STAMCOUNTER StatRZPhysSimpleReadBytes;
2867 STAMCOUNTER StatRZPhysSimpleWrite;
2868 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2869 STAMCOUNTER StatR3PhysSimpleRead;
2870 STAMCOUNTER StatR3PhysSimpleReadBytes;
2871 STAMCOUNTER StatR3PhysSimpleWrite;
2872 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2873 STAMCOUNTER StatRCPhysSimpleRead;
2874 STAMCOUNTER StatRCPhysSimpleReadBytes;
2875 STAMCOUNTER StatRCPhysSimpleWrite;
2876 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2877
2878 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2879 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2880 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2881 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2882 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2883 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2884 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2885
2886 /** Time spent by the host OS for large page allocation. */
2887 STAMPROFILE StatAllocLargePage;
2888 /** Time spent clearing the newly allocated large pages. */
2889 STAMPROFILE StatClearLargePage;
2890 /** pgmPhysIsValidLargePage profiling - R3 */
2891 STAMPROFILE StatR3IsValidLargePage;
2892 /** pgmPhysIsValidLargePage profiling - RZ*/
2893 STAMPROFILE StatRZIsValidLargePage;
2894#endif
2895} PGM;
2896#ifndef IN_TSTVMSTRUCTGC /* HACK */
2897AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2898AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2899AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2900AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2901AssertCompileMemberAlignment(PGM, CritSect, 8);
2902AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2903AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2904AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2905AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2906AssertCompileMemberAlignment(PGM, cRelocations, 8);
2907#endif /* !IN_TSTVMSTRUCTGC */
2908/** Pointer to the PGM instance data. */
2909typedef PGM *PPGM;
2910
2911
2912/**
2913 * Converts a PGMCPU pointer into a VM pointer.
2914 * @returns Pointer to the VM structure the PGM is part of.
2915 * @param pPGM Pointer to PGMCPU instance data.
2916 */
2917#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2918
2919/**
2920 * Converts a PGMCPU pointer into a PGM pointer.
2921 * @returns Pointer to the VM structure the PGM is part of.
2922 * @param pPGM Pointer to PGMCPU instance data.
2923 */
2924#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2925
2926/**
2927 * PGMCPU Data (part of VMCPU).
2928 */
2929typedef struct PGMCPU
2930{
2931 /** Offset to the VM structure. */
2932 RTINT offVM;
2933 /** Offset to the VMCPU structure. */
2934 RTINT offVCpu;
2935 /** Offset of the PGM structure relative to VMCPU. */
2936 RTINT offPGM;
2937 RTINT uPadding0; /**< structure size alignment. */
2938
2939#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2940 /** Automatically tracked physical memory mapping set.
2941 * Ring-0 and strict raw-mode builds. */
2942 PGMMAPSET AutoSet;
2943#endif
2944
2945 /** A20 gate mask.
2946 * Our current approach to A20 emulation is to let REM do it and don't bother
2947 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2948 * But whould need arrise, we'll subject physical addresses to this mask. */
2949 RTGCPHYS GCPhysA20Mask;
2950 /** A20 gate state - boolean! */
2951 bool fA20Enabled;
2952
2953 /** What needs syncing (PGM_SYNC_*).
2954 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2955 * PGMFlushTLB, and PGMR3Load. */
2956 RTUINT fSyncFlags;
2957
2958 /** The shadow paging mode. */
2959 PGMMODE enmShadowMode;
2960 /** The guest paging mode. */
2961 PGMMODE enmGuestMode;
2962
2963 /** The current physical address representing in the guest CR3 register. */
2964 RTGCPHYS GCPhysCR3;
2965
2966 /** @name 32-bit Guest Paging.
2967 * @{ */
2968 /** The guest's page directory, R3 pointer. */
2969 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2970#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2971 /** The guest's page directory, R0 pointer. */
2972 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2973#endif
2974 /** The guest's page directory, static RC mapping. */
2975 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2976 /** @} */
2977
2978 /** @name PAE Guest Paging.
2979 * @{ */
2980 /** The guest's page directory pointer table, static RC mapping. */
2981 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2982 /** The guest's page directory pointer table, R3 pointer. */
2983 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2984#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2985 /** The guest's page directory pointer table, R0 pointer. */
2986 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2987#endif
2988
2989 /** The guest's page directories, R3 pointers.
2990 * These are individual pointers and don't have to be adjecent.
2991 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2992 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2993 /** The guest's page directories, R0 pointers.
2994 * Same restrictions as apGstPaePDsR3. */
2995#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2996 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2997#endif
2998 /** The guest's page directories, static GC mapping.
2999 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3000 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3001 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3002 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3003 RTGCPHYS aGCPhysGstPaePDs[4];
3004 /** The physical addresses of the monitored guest page directories (PAE). */
3005 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3006 /** @} */
3007
3008 /** @name AMD64 Guest Paging.
3009 * @{ */
3010 /** The guest's page directory pointer table, R3 pointer. */
3011 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3012#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3013 /** The guest's page directory pointer table, R0 pointer. */
3014 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3015#else
3016 RTR0PTR alignment6b; /**< alignment equalizer. */
3017#endif
3018 /** @} */
3019
3020 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3021 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3022 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3023 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3024 /** Pointer to the page of the current active CR3 - RC Ptr. */
3025 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3026 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3027 uint32_t iShwUser;
3028 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3029 uint32_t iShwUserTable;
3030# if HC_ARCH_BITS == 64
3031 RTRCPTR alignment6; /**< structure size alignment. */
3032# endif
3033 /** @} */
3034
3035 /** @name Function pointers for Shadow paging.
3036 * @{
3037 */
3038 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3039 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3040 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3041 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3042
3043 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3044 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3045
3046 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3047 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3048
3049 /** @} */
3050
3051 /** @name Function pointers for Guest paging.
3052 * @{
3053 */
3054 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3055 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3056 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3057 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3058 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3059 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3060 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3061 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3062#if HC_ARCH_BITS == 64
3063 RTRCPTR alignment3; /**< structure size alignment. */
3064#endif
3065
3066 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3067 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3068 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3069 /** @} */
3070
3071 /** @name Function pointers for Both Shadow and Guest paging.
3072 * @{
3073 */
3074 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3075 /* no pfnR3BthTrap0eHandler */
3076 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3077 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3078 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3079 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3080 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3081 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3082 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3083 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3084
3085 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3086 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3087 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3088 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3089 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3090 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3091 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3092 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3093 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3094
3095 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3096 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3097 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3098 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3099 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3100 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3101 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3102 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3103 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3104 RTRCPTR alignment2; /**< structure size alignment. */
3105 /** @} */
3106
3107 /** For saving stack space, the disassembler state is allocated here instead of
3108 * on the stack.
3109 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3110 union
3111 {
3112 /** The disassembler scratch space. */
3113 DISCPUSTATE DisState;
3114 /** Padding. */
3115 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3116 };
3117
3118 /* Count the number of pgm pool access handler calls. */
3119 uint64_t cPoolAccessHandler;
3120
3121 /** @name Release Statistics
3122 * @{ */
3123 /** The number of times the guest has switched mode since last reset or statistics reset. */
3124 STAMCOUNTER cGuestModeChanges;
3125 /** @} */
3126
3127#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3128 /** @name Statistics
3129 * @{ */
3130 /** RC: Which statistic this \#PF should be attributed to. */
3131 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3132 RTRCPTR padding0;
3133 /** R0: Which statistic this \#PF should be attributed to. */
3134 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3135 RTR0PTR padding1;
3136
3137 /* Common */
3138 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3139 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3140
3141 /* R0 only: */
3142 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3143 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3144 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3145 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3146 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3147 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3148 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3149 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3150 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3151 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3152 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3153 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3154 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3155 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3156 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3157 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3158 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3159 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3160 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3161 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3162 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3163 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3164 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3165 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3166 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3167 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3168
3169 /* RZ only: */
3170 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3171 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3172 STAMPROFILE StatRZTrap0eTimeSyncPT;
3173 STAMPROFILE StatRZTrap0eTimeMapping;
3174 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3175 STAMPROFILE StatRZTrap0eTimeHandlers;
3176 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3177 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3178 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3179 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3180 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3181 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3182 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3183 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3184 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3185 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3186 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3187 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3188 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3189 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3190 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3191 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3192 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3193 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3194 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3195 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3196 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3197 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3198 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3199 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3200 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3201 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3202 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3203 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3204 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3205 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3206 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3207 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3208 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3209 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3210 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3211 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3212 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3213 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3214 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3215 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3216 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3217 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3218 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3219
3220 /* HC - R3 and (maybe) R0: */
3221
3222 /* RZ & R3: */
3223 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3224 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3225 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3226 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3227 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3228 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3229 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3230 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3231 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3232 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3233 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3234 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3235 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3236 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3237 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3238 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3239 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3240 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3241 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3242 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3243 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3244 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3245 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3246 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3247 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3248 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3249 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3250 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3251 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3252 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3253 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3254 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3255 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3256 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3257 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3258 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3259 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3260 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3261 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3262 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3263 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3264 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3265 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3266 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3267 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3268 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3269 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3270
3271 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3272 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3273 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3274 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3275 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3276 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3277 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3278 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3279 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3280 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3281 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3282 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3283 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3284 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3285 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3286 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3287 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3288 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3289 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3290 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3291 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3292 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3293 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3294 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3295 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3296 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3297 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3298 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3299 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3300 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3301 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3302 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3303 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3304 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3305 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3306 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3307 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3308 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3309 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3310 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3311 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3312 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3313 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3314 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3315 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3316 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3317 /** @} */
3318#endif /* VBOX_WITH_STATISTICS */
3319} PGMCPU;
3320/** Pointer to the per-cpu PGM data. */
3321typedef PGMCPU *PPGMCPU;
3322
3323
3324/** @name PGM::fSyncFlags Flags
3325 * @{
3326 */
3327/** Updates the virtual access handler state bit in PGMPAGE. */
3328#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3329/** Always sync CR3. */
3330#define PGM_SYNC_ALWAYS RT_BIT(1)
3331/** Check monitoring on next CR3 (re)load and invalidate page.
3332 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3333#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3334/** Check guest mapping in SyncCR3. */
3335#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3336/** Clear the page pool (a light weight flush). */
3337#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3338#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3339/** @} */
3340
3341
3342RT_C_DECLS_BEGIN
3343
3344int pgmLock(PVM pVM);
3345void pgmUnlock(PVM pVM);
3346
3347int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3348int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3349int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3350PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3351int pgmMapResolveConflicts(PVM pVM);
3352DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3353
3354void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3355bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3356void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3357int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3358DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3359#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3360void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3361#else
3362# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3363#endif
3364DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3365int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3366
3367int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3368int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3369int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3370int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3371int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3372void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3373int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3374int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3375int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3376int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3377int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3378int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3379int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3380VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3381VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3382int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3383
3384#ifdef IN_RING3
3385void pgmR3PhysRelinkRamRanges(PVM pVM);
3386int pgmR3PhysRamPreAllocate(PVM pVM);
3387int pgmR3PhysRamReset(PVM pVM);
3388int pgmR3PhysRomReset(PVM pVM);
3389int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3390int pgmR3PhysRamTerm(PVM pVM);
3391
3392int pgmR3PoolInit(PVM pVM);
3393void pgmR3PoolRelocate(PVM pVM);
3394void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3395void pgmR3PoolReset(PVM pVM);
3396void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3397DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3398
3399#endif /* IN_RING3 */
3400#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3401int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3402#endif
3403int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3404
3405DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3406{
3407 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3408}
3409
3410void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3411void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3412int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3413void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3414PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3415int pgmPoolSyncCR3(PVMCPU pVCpu);
3416bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3417int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3418void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3419void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3420DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3421{
3422 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3423}
3424
3425uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3426void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3427void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3428int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3429void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3430
3431void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3432void pgmPoolResetDirtyPages(PVM pVM);
3433
3434int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3435int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3436
3437void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3438void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3439int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3440int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3441
3442int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3443#ifndef IN_RC
3444int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3445#endif
3446int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3447
3448PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3449PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3450PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3451PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3452
3453# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3454DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3455DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3456# endif
3457
3458RT_C_DECLS_END
3459
3460/** @} */
3461
3462#endif
3463
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