VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31140

Last change on this file since 31140 was 31140, checked in by vboxsync, 14 years ago

PGM: Removed CheckPageFault as it is no longer used. Removed pfn*SyncPage since it is always used directly. Made a few more internal functions static to encourage compiler optimizations.
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File size: 166.4 KB
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1/* $Id: PGMInternal.h 31140 2010-07-27 13:29:43Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param HCPhys The HC physical address to map to a virtual one.
232 * @param ppv Where to store the virtual address. No need to cast this.
233 *
234 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
235 * small page window employeed by that function. Be careful.
236 * @remark There is no need to assert on the result.
237 */
238#ifdef IN_RC
239# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
240 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
241#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
242# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
243 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
244#else
245# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
246 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
247#endif
248
249/** @def PGM_GCPHYS_2_PTR
250 * Maps a GC physical page address to a virtual address.
251 *
252 * @returns VBox status code.
253 * @param pVM The VM handle.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
258 * small page window employeed by that function. Be careful.
259 * @remark There is no need to assert on the result.
260 */
261#ifdef IN_RC
262# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
263 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
264#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
265# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
266 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
267#else
268# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
269 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
270#endif
271
272/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
273 * Maps a GC physical page address to a virtual address.
274 *
275 * @returns VBox status code.
276 * @param pVCpu The current CPU.
277 * @param GCPhys The GC physical address to map to a virtual one.
278 * @param ppv Where to store the virtual address. No need to cast this.
279 *
280 * @remark In RC this uses PGMGCDynMapGCPage(), so it will consume of the
281 * small page window employeed by that function. Be careful.
282 * @remark There is no need to assert on the result.
283 */
284#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
285# define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) \
286 pgmR0DynMapGCPageInlined(&(pVCpu)->CTX_SUFF(pVM)->pgm.s, GCPhys, (void **)(ppv))
287#else
288# define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) \
289 PGM_GCPHYS_2_PTR((pVCpu)->CTX_SUFF(pVM), GCPhys, ppv)
290#endif
291
292/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
293 * Maps a GC physical page address to a virtual address.
294 *
295 * @returns VBox status code.
296 * @param pPGM Pointer to the PGM instance data.
297 * @param GCPhys The GC physical address to map to a virtual one.
298 * @param ppv Where to store the virtual address. No need to cast this.
299 *
300 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
301 * small page window employeed by that function. Be careful.
302 * @remark There is no need to assert on the result.
303 */
304#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
305# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
306 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
307#else
308# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
309 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
310#endif
311
312/** @def PGM_GCPHYS_2_PTR_EX
313 * Maps a unaligned GC physical page address to a virtual address.
314 *
315 * @returns VBox status code.
316 * @param pVM The VM handle.
317 * @param GCPhys The GC physical address to map to a virtual one.
318 * @param ppv Where to store the virtual address. No need to cast this.
319 *
320 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
321 * small page window employeed by that function. Be careful.
322 * @remark There is no need to assert on the result.
323 */
324#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
325# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
327#else
328# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
329 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
330#endif
331
332/** @def PGM_INVL_PG
333 * Invalidates a page.
334 *
335 * @param pVCpu The VMCPU handle.
336 * @param GCVirt The virtual address of the page to invalidate.
337 */
338#ifdef IN_RC
339# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
340#elif defined(IN_RING0)
341# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
342#else
343# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
344#endif
345
346/** @def PGM_INVL_PG_ALL_VCPU
347 * Invalidates a page on all VCPUs
348 *
349 * @param pVM The VM handle.
350 * @param GCVirt The virtual address of the page to invalidate.
351 */
352#ifdef IN_RC
353# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
354#elif defined(IN_RING0)
355# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
356#else
357# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
358#endif
359
360/** @def PGM_INVL_BIG_PG
361 * Invalidates a 4MB page directory entry.
362 *
363 * @param pVCpu The VMCPU handle.
364 * @param GCVirt The virtual address within the page directory to invalidate.
365 */
366#ifdef IN_RC
367# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
368#elif defined(IN_RING0)
369# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
370#else
371# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
372#endif
373
374/** @def PGM_INVL_VCPU_TLBS()
375 * Invalidates the TLBs of the specified VCPU
376 *
377 * @param pVCpu The VMCPU handle.
378 */
379#ifdef IN_RC
380# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
381#elif defined(IN_RING0)
382# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
383#else
384# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
385#endif
386
387/** @def PGM_INVL_ALL_VCPU_TLBS()
388 * Invalidates the TLBs of all VCPUs
389 *
390 * @param pVM The VM handle.
391 */
392#ifdef IN_RC
393# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
394#elif defined(IN_RING0)
395# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
396#else
397# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
398#endif
399
400/** Size of the GCPtrConflict array in PGMMAPPING.
401 * @remarks Must be a power of two. */
402#define PGMMAPPING_CONFLICT_MAX 8
403
404/**
405 * Structure for tracking GC Mappings.
406 *
407 * This structure is used by linked list in both GC and HC.
408 */
409typedef struct PGMMAPPING
410{
411 /** Pointer to next entry. */
412 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
413 /** Pointer to next entry. */
414 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
415 /** Pointer to next entry. */
416 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
417 /** Indicate whether this entry is finalized. */
418 bool fFinalized;
419 /** Start Virtual address. */
420 RTGCPTR GCPtr;
421 /** Last Virtual address (inclusive). */
422 RTGCPTR GCPtrLast;
423 /** Range size (bytes). */
424 RTGCPTR cb;
425 /** Pointer to relocation callback function. */
426 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
427 /** User argument to the callback. */
428 R3PTRTYPE(void *) pvUser;
429 /** Mapping description / name. For easing debugging. */
430 R3PTRTYPE(const char *) pszDesc;
431 /** Last 8 addresses that caused conflicts. */
432 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
433 /** Number of conflicts for this hypervisor mapping. */
434 uint32_t cConflicts;
435 /** Number of page tables. */
436 uint32_t cPTs;
437
438 /** Array of page table mapping data. Each entry
439 * describes one page table. The array can be longer
440 * than the declared length.
441 */
442 struct
443 {
444 /** The HC physical address of the page table. */
445 RTHCPHYS HCPhysPT;
446 /** The HC physical address of the first PAE page table. */
447 RTHCPHYS HCPhysPaePT0;
448 /** The HC physical address of the second PAE page table. */
449 RTHCPHYS HCPhysPaePT1;
450 /** The HC virtual address of the 32-bit page table. */
451 R3PTRTYPE(PX86PT) pPTR3;
452 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
453 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
454 /** The RC virtual address of the 32-bit page table. */
455 RCPTRTYPE(PX86PT) pPTRC;
456 /** The RC virtual address of the two PAE page table. */
457 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
458 /** The R0 virtual address of the 32-bit page table. */
459 R0PTRTYPE(PX86PT) pPTR0;
460 /** The R0 virtual address of the two PAE page table. */
461 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
462 } aPTs[1];
463} PGMMAPPING;
464/** Pointer to structure for tracking GC Mappings. */
465typedef struct PGMMAPPING *PPGMMAPPING;
466
467
468/**
469 * Physical page access handler structure.
470 *
471 * This is used to keep track of physical address ranges
472 * which are being monitored in some kind of way.
473 */
474typedef struct PGMPHYSHANDLER
475{
476 AVLROGCPHYSNODECORE Core;
477 /** Access type. */
478 PGMPHYSHANDLERTYPE enmType;
479 /** Number of pages to update. */
480 uint32_t cPages;
481 /** Pointer to R3 callback function. */
482 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
483 /** User argument for R3 handlers. */
484 R3PTRTYPE(void *) pvUserR3;
485 /** Pointer to R0 callback function. */
486 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
487 /** User argument for R0 handlers. */
488 R0PTRTYPE(void *) pvUserR0;
489 /** Pointer to RC callback function. */
490 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
491 /** User argument for RC handlers. */
492 RCPTRTYPE(void *) pvUserRC;
493 /** Description / Name. For easing debugging. */
494 R3PTRTYPE(const char *) pszDesc;
495#ifdef VBOX_WITH_STATISTICS
496 /** Profiling of this handler. */
497 STAMPROFILE Stat;
498#endif
499} PGMPHYSHANDLER;
500/** Pointer to a physical page access handler structure. */
501typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
502
503
504/**
505 * Cache node for the physical addresses covered by a virtual handler.
506 */
507typedef struct PGMPHYS2VIRTHANDLER
508{
509 /** Core node for the tree based on physical ranges. */
510 AVLROGCPHYSNODECORE Core;
511 /** Offset from this struct to the PGMVIRTHANDLER structure. */
512 int32_t offVirtHandler;
513 /** Offset of the next alias relative to this one.
514 * Bit 0 is used for indicating whether we're in the tree.
515 * Bit 1 is used for indicating that we're the head node.
516 */
517 int32_t offNextAlias;
518} PGMPHYS2VIRTHANDLER;
519/** Pointer to a phys to virtual handler structure. */
520typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
521
522/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
523 * node is in the tree. */
524#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
525/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
526 * node is in the head of an alias chain.
527 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
528#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
529/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
530#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
531
532
533/**
534 * Virtual page access handler structure.
535 *
536 * This is used to keep track of virtual address ranges
537 * which are being monitored in some kind of way.
538 */
539typedef struct PGMVIRTHANDLER
540{
541 /** Core node for the tree based on virtual ranges. */
542 AVLROGCPTRNODECORE Core;
543 /** Size of the range (in bytes). */
544 RTGCPTR cb;
545 /** Number of cache pages. */
546 uint32_t cPages;
547 /** Access type. */
548 PGMVIRTHANDLERTYPE enmType;
549 /** Pointer to the RC callback function. */
550 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
551#if HC_ARCH_BITS == 64
552 RTRCPTR padding;
553#endif
554 /** Pointer to the R3 callback function for invalidation. */
555 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
556 /** Pointer to the R3 callback function. */
557 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
558 /** Description / Name. For easing debugging. */
559 R3PTRTYPE(const char *) pszDesc;
560#ifdef VBOX_WITH_STATISTICS
561 /** Profiling of this handler. */
562 STAMPROFILE Stat;
563#endif
564 /** Array of cached physical addresses for the monitored ranged. */
565 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
566} PGMVIRTHANDLER;
567/** Pointer to a virtual page access handler structure. */
568typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
569
570
571/**
572 * Page type.
573 *
574 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
575 * @remarks This is used in the saved state, so changes to it requires bumping
576 * the saved state version.
577 * @todo So, convert to \#defines!
578 */
579typedef enum PGMPAGETYPE
580{
581 /** The usual invalid zero entry. */
582 PGMPAGETYPE_INVALID = 0,
583 /** RAM page. (RWX) */
584 PGMPAGETYPE_RAM,
585 /** MMIO2 page. (RWX) */
586 PGMPAGETYPE_MMIO2,
587 /** MMIO2 page aliased over an MMIO page. (RWX)
588 * See PGMHandlerPhysicalPageAlias(). */
589 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
590 /** Shadowed ROM. (RWX) */
591 PGMPAGETYPE_ROM_SHADOW,
592 /** ROM page. (R-X) */
593 PGMPAGETYPE_ROM,
594 /** MMIO page. (---) */
595 PGMPAGETYPE_MMIO,
596 /** End of valid entries. */
597 PGMPAGETYPE_END
598} PGMPAGETYPE;
599AssertCompile(PGMPAGETYPE_END <= 7);
600
601/** @name Page type predicates.
602 * @{ */
603#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
604#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
605#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
606#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
607#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
608/** @} */
609
610
611/**
612 * A Physical Guest Page tracking structure.
613 *
614 * The format of this structure is complicated because we have to fit a lot
615 * of information into as few bits as possible. The format is also subject
616 * to change (there is one comming up soon). Which means that for we'll be
617 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
618 * accesses to the structure.
619 */
620typedef struct PGMPAGE
621{
622 /** The physical address and the Page ID. */
623 RTHCPHYS HCPhysAndPageID;
624 /** Combination of:
625 * - [0-7]: u2HandlerPhysStateY - the physical handler state
626 * (PGM_PAGE_HNDL_PHYS_STATE_*).
627 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
628 * (PGM_PAGE_HNDL_VIRT_STATE_*).
629 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
630 * - [15]: fWrittenToY - flag indicating that a write monitored page was
631 * written to when set.
632 * - [10-13]: 4 unused bits.
633 * @remarks Warning! All accesses to the bits are hardcoded.
634 *
635 * @todo Change this to a union with both bitfields, u8 and u accessors.
636 * That'll help deal with some of the hardcoded accesses.
637 *
638 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
639 * will make it possible to turn some of the 16-bit accesses into
640 * 32-bit ones, which may be efficient (stalls).
641 */
642 RTUINT16U u16MiscY;
643 /** The page state.
644 * Only 3 bits are really needed for this. */
645 uint16_t uStateY : 3;
646 /** The page type (PGMPAGETYPE).
647 * Only 3 bits are really needed for this. */
648 uint16_t uTypeY : 3;
649 /** PTE index for usage tracking (page pool). */
650 uint16_t uPteIdx : 10;
651 /** Usage tracking (page pool). */
652 uint16_t u16TrackingY;
653 /** The number of read locks on this page. */
654 uint8_t cReadLocksY;
655 /** The number of write locks on this page. */
656 uint8_t cWriteLocksY;
657} PGMPAGE;
658AssertCompileSize(PGMPAGE, 16);
659/** Pointer to a physical guest page. */
660typedef PGMPAGE *PPGMPAGE;
661/** Pointer to a const physical guest page. */
662typedef const PGMPAGE *PCPGMPAGE;
663/** Pointer to a physical guest page pointer. */
664typedef PPGMPAGE *PPPGMPAGE;
665
666
667/**
668 * Clears the page structure.
669 * @param pPage Pointer to the physical guest page tracking structure.
670 */
671#define PGM_PAGE_CLEAR(pPage) \
672 do { \
673 (pPage)->HCPhysAndPageID = 0; \
674 (pPage)->uStateY = 0; \
675 (pPage)->uTypeY = 0; \
676 (pPage)->uPteIdx = 0; \
677 (pPage)->u16MiscY.u = 0; \
678 (pPage)->u16TrackingY = 0; \
679 (pPage)->cReadLocksY = 0; \
680 (pPage)->cWriteLocksY = 0; \
681 } while (0)
682
683/**
684 * Initializes the page structure.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 */
687#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
688 do { \
689 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
690 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
691 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
692 (pPage)->uStateY = (_uState); \
693 (pPage)->uTypeY = (_uType); \
694 (pPage)->uPteIdx = 0; \
695 (pPage)->u16MiscY.u = 0; \
696 (pPage)->u16TrackingY = 0; \
697 (pPage)->cReadLocksY = 0; \
698 (pPage)->cWriteLocksY = 0; \
699 } while (0)
700
701/**
702 * Initializes the page structure of a ZERO page.
703 * @param pPage Pointer to the physical guest page tracking structure.
704 * @param pVM The VM handle (for getting the zero page address).
705 * @param uType The page type (PGMPAGETYPE).
706 */
707#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
708 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
709
710
711/** @name The Page state, PGMPAGE::uStateY.
712 * @{ */
713/** The zero page.
714 * This is a per-VM page that's never ever mapped writable. */
715#define PGM_PAGE_STATE_ZERO 0
716/** A allocated page.
717 * This is a per-VM page allocated from the page pool (or wherever
718 * we get MMIO2 pages from if the type is MMIO2).
719 */
720#define PGM_PAGE_STATE_ALLOCATED 1
721/** A allocated page that's being monitored for writes.
722 * The shadow page table mappings are read-only. When a write occurs, the
723 * fWrittenTo member is set, the page remapped as read-write and the state
724 * moved back to allocated. */
725#define PGM_PAGE_STATE_WRITE_MONITORED 2
726/** The page is shared, aka. copy-on-write.
727 * This is a page that's shared with other VMs. */
728#define PGM_PAGE_STATE_SHARED 3
729/** The page is ballooned, so no longer available for this VM. */
730#define PGM_PAGE_STATE_BALLOONED 4
731/** @} */
732
733
734/**
735 * Gets the page state.
736 * @returns page state (PGM_PAGE_STATE_*).
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
740
741/**
742 * Sets the page state.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 * @param _uState The new page state.
745 */
746#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
747
748
749/**
750 * Gets the host physical address of the guest page.
751 * @returns host physical address (RTHCPHYS).
752 * @param pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
755
756/**
757 * Sets the host physical address of the guest page.
758 * @param pPage Pointer to the physical guest page tracking structure.
759 * @param _HCPhys The new host physical address.
760 */
761#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
762 do { \
763 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
764 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
765 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
766 | (SetHCPhysTmp << (28-12)); \
767 } while (0)
768
769/**
770 * Get the Page ID.
771 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
772 * @param pPage Pointer to the physical guest page tracking structure.
773 */
774#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
775
776/**
777 * Sets the Page ID.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 */
780#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
781 do { \
782 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
783 | ((_idPage) & UINT32_C(0x0fffffff)); \
784 } while (0)
785
786/**
787 * Get the Chunk ID.
788 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
789 * @param pPage Pointer to the physical guest page tracking structure.
790 */
791#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
792
793/**
794 * Get the index of the page within the allocation chunk.
795 * @returns The page index.
796 * @param pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
799
800/**
801 * Gets the page type.
802 * @returns The page type.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
806
807/**
808 * Sets the page type.
809 * @param pPage Pointer to the physical guest page tracking structure.
810 * @param _enmType The new page type (PGMPAGETYPE).
811 */
812#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
813
814/**
815 * Gets the page table index
816 * @returns The page table index.
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
820
821/**
822 * Sets the page table index
823 * @param pPage Pointer to the physical guest page tracking structure.
824 * @param iPte New page table index.
825 */
826#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
827
828/**
829 * Checks if the page is marked for MMIO.
830 * @returns true/false.
831 * @param pPage Pointer to the physical guest page tracking structure.
832 */
833#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
834
835/**
836 * Checks if the page is backed by the ZERO page.
837 * @returns true/false.
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
841
842/**
843 * Checks if the page is backed by a SHARED page.
844 * @returns true/false.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
848
849/**
850 * Checks if the page is ballooned.
851 * @returns true/false.
852 * @param pPage Pointer to the physical guest page tracking structure.
853 */
854#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
855
856/**
857 * Marks the page as written to (for GMM change monitoring).
858 * @param pPage Pointer to the physical guest page tracking structure.
859 */
860#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
861
862/**
863 * Clears the written-to indicator.
864 * @param pPage Pointer to the physical guest page tracking structure.
865 */
866#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
867
868/**
869 * Checks if the page was marked as written-to.
870 * @returns true/false.
871 * @param pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
874
875/** @name PT usage values (PGMPAGE::u2PDEType).
876 *
877 * @{ */
878/** Either as a PT or PDE. */
879#define PGM_PAGE_PDE_TYPE_DONTCARE 0
880/** Must use a page table to map the range. */
881#define PGM_PAGE_PDE_TYPE_PT 1
882/** Can use a page directory entry to map the continous range. */
883#define PGM_PAGE_PDE_TYPE_PDE 2
884/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
885#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
886/** @} */
887
888/**
889 * Set the PDE type of the page
890 * @param pPage Pointer to the physical guest page tracking structure.
891 * @param uType PGM_PAGE_PDE_TYPE_*
892 */
893#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
894 do { \
895 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
896 | (((uType) & UINT8_C(0x03)) << 5); \
897 } while (0)
898
899/**
900 * Checks if the page was marked being part of a large page
901 * @returns true/false.
902 * @param pPage Pointer to the physical guest page tracking structure.
903 */
904#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
905
906/** Enabled optimized access handler tests.
907 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
908 * layout. When enabled, the compiler should normally generate more compact
909 * code.
910 */
911#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
912
913/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
914 *
915 * @remarks The values are assigned in order of priority, so we can calculate
916 * the correct state for a page with different handlers installed.
917 * @{ */
918/** No handler installed. */
919#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
920/** Monitoring is temporarily disabled. */
921#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
922/** Write access is monitored. */
923#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
924/** All access is monitored. */
925#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
926/** @} */
927
928/**
929 * Gets the physical access handler state of a page.
930 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
931 * @param pPage Pointer to the physical guest page tracking structure.
932 */
933#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
934 ( (pPage)->u16MiscY.au8[0] )
935
936/**
937 * Sets the physical access handler state of a page.
938 * @param pPage Pointer to the physical guest page tracking structure.
939 * @param _uState The new state value.
940 */
941#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
942 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
943
944/**
945 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
946 * @returns true/false
947 * @param pPage Pointer to the physical guest page tracking structure.
948 */
949#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
950 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
951
952/**
953 * Checks if the page has any active physical access handlers.
954 * @returns true/false
955 * @param pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
958 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
959
960
961/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
962 *
963 * @remarks The values are assigned in order of priority, so we can calculate
964 * the correct state for a page with different handlers installed.
965 * @{ */
966/** No handler installed. */
967#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
968/* 1 is reserved so the lineup is identical with the physical ones. */
969/** Write access is monitored. */
970#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
971/** All access is monitored. */
972#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
973/** @} */
974
975/**
976 * Gets the virtual access handler state of a page.
977 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
978 * @param pPage Pointer to the physical guest page tracking structure.
979 */
980#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
981
982/**
983 * Sets the virtual access handler state of a page.
984 * @param pPage Pointer to the physical guest page tracking structure.
985 * @param _uState The new state value.
986 */
987#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
988 do { \
989 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
990 | ((_uState) & UINT8_C(0x03)); \
991 } while (0)
992
993/**
994 * Checks if the page has any virtual access handlers.
995 * @returns true/false
996 * @param pPage Pointer to the physical guest page tracking structure.
997 */
998#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
999 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1000
1001/**
1002 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1003 * virtual handlers.
1004 * @returns true/false
1005 * @param pPage Pointer to the physical guest page tracking structure.
1006 */
1007#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1008 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1009
1010
1011/**
1012 * Checks if the page has any access handlers, including temporarily disabled ones.
1013 * @returns true/false
1014 * @param pPage Pointer to the physical guest page tracking structure.
1015 */
1016#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1017# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1018 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1019#else
1020# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1021 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1022 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1023#endif
1024
1025/**
1026 * Checks if the page has any active access handlers.
1027 * @returns true/false
1028 * @param pPage Pointer to the physical guest page tracking structure.
1029 */
1030#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1031# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1032 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1033#else
1034# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1035 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1036 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1037#endif
1038
1039/**
1040 * Checks if the page has any active access handlers catching all accesses.
1041 * @returns true/false
1042 * @param pPage Pointer to the physical guest page tracking structure.
1043 */
1044#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1045# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1046 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1047 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1048#else
1049# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1050 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1051 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1052#endif
1053
1054
1055/** @def PGM_PAGE_GET_TRACKING
1056 * Gets the packed shadow page pool tracking data associated with a guest page.
1057 * @returns uint16_t containing the data.
1058 * @param pPage Pointer to the physical guest page tracking structure.
1059 */
1060#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1061
1062/** @def PGM_PAGE_SET_TRACKING
1063 * Sets the packed shadow page pool tracking data associated with a guest page.
1064 * @param pPage Pointer to the physical guest page tracking structure.
1065 * @param u16TrackingData The tracking data to store.
1066 */
1067#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1068 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1069
1070/** @def PGM_PAGE_GET_TD_CREFS
1071 * Gets the @a cRefs tracking data member.
1072 * @returns cRefs.
1073 * @param pPage Pointer to the physical guest page tracking structure.
1074 */
1075#define PGM_PAGE_GET_TD_CREFS(pPage) \
1076 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1077
1078/** @def PGM_PAGE_GET_TD_IDX
1079 * Gets the @a idx tracking data member.
1080 * @returns idx.
1081 * @param pPage Pointer to the physical guest page tracking structure.
1082 */
1083#define PGM_PAGE_GET_TD_IDX(pPage) \
1084 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1085
1086
1087/** Max number of locks on a page. */
1088#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1089
1090/** Get the read lock count.
1091 * @returns count.
1092 * @param pPage Pointer to the physical guest page tracking structure.
1093 */
1094#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1095
1096/** Get the write lock count.
1097 * @returns count.
1098 * @param pPage Pointer to the physical guest page tracking structure.
1099 */
1100#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1101
1102/** Decrement the read lock counter.
1103 * @param pPage Pointer to the physical guest page tracking structure.
1104 */
1105#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1106
1107/** Decrement the write lock counter.
1108 * @param pPage Pointer to the physical guest page tracking structure.
1109 */
1110#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1111
1112/** Increment the read lock counter.
1113 * @param pPage Pointer to the physical guest page tracking structure.
1114 */
1115#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1116
1117/** Increment the write lock counter.
1118 * @param pPage Pointer to the physical guest page tracking structure.
1119 */
1120#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1121
1122
1123#if 0
1124/** Enables sanity checking of write monitoring using CRC-32. */
1125# define PGMLIVESAVERAMPAGE_WITH_CRC32
1126#endif
1127
1128/**
1129 * Per page live save tracking data.
1130 */
1131typedef struct PGMLIVESAVERAMPAGE
1132{
1133 /** Number of times it has been dirtied. */
1134 uint32_t cDirtied : 24;
1135 /** Whether it is currently dirty. */
1136 uint32_t fDirty : 1;
1137 /** Ignore the page.
1138 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1139 * deal with these after pausing the VM and DevPCI have said it bit about
1140 * remappings. */
1141 uint32_t fIgnore : 1;
1142 /** Was a ZERO page last time around. */
1143 uint32_t fZero : 1;
1144 /** Was a SHARED page last time around. */
1145 uint32_t fShared : 1;
1146 /** Whether the page is/was write monitored in a previous pass. */
1147 uint32_t fWriteMonitored : 1;
1148 /** Whether the page is/was write monitored earlier in this pass. */
1149 uint32_t fWriteMonitoredJustNow : 1;
1150 /** Bits reserved for future use. */
1151 uint32_t u2Reserved : 2;
1152#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1153 /** CRC-32 for the page. This is for internal consistency checks. */
1154 uint32_t u32Crc;
1155#endif
1156} PGMLIVESAVERAMPAGE;
1157#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1158AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1159#else
1160AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1161#endif
1162/** Pointer to the per page live save tracking data. */
1163typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1164
1165/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1166#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1167
1168
1169/**
1170 * Ram range for GC Phys to HC Phys conversion.
1171 *
1172 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1173 * conversions too, but we'll let MM handle that for now.
1174 *
1175 * This structure is used by linked lists in both GC and HC.
1176 */
1177typedef struct PGMRAMRANGE
1178{
1179 /** Start of the range. Page aligned. */
1180 RTGCPHYS GCPhys;
1181 /** Size of the range. (Page aligned of course). */
1182 RTGCPHYS cb;
1183 /** Pointer to the next RAM range - for R3. */
1184 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1185 /** Pointer to the next RAM range - for R0. */
1186 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1187 /** Pointer to the next RAM range - for RC. */
1188 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1189 /** PGM_RAM_RANGE_FLAGS_* flags. */
1190 uint32_t fFlags;
1191 /** Last address in the range (inclusive). Page aligned (-1). */
1192 RTGCPHYS GCPhysLast;
1193 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1194 R3PTRTYPE(void *) pvR3;
1195 /** Live save per page tracking data. */
1196 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1197 /** The range description. */
1198 R3PTRTYPE(const char *) pszDesc;
1199 /** Pointer to self - R0 pointer. */
1200 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1201 /** Pointer to self - RC pointer. */
1202 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1203 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1204 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1205 /** Array of physical guest page tracking structures. */
1206 PGMPAGE aPages[1];
1207} PGMRAMRANGE;
1208/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1209typedef PGMRAMRANGE *PPGMRAMRANGE;
1210
1211/** @name PGMRAMRANGE::fFlags
1212 * @{ */
1213/** The RAM range is floating around as an independent guest mapping. */
1214#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1215/** Ad hoc RAM range for an ROM mapping. */
1216#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1217/** Ad hoc RAM range for an MMIO mapping. */
1218#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1219/** Ad hoc RAM range for an MMIO2 mapping. */
1220#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1221/** @} */
1222
1223/** Tests if a RAM range is an ad hoc one or not.
1224 * @returns true/false.
1225 * @param pRam The RAM range.
1226 */
1227#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1228 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1229
1230
1231/**
1232 * Per page tracking structure for ROM image.
1233 *
1234 * A ROM image may have a shadow page, in which case we may have two pages
1235 * backing it. This structure contains the PGMPAGE for both while
1236 * PGMRAMRANGE have a copy of the active one. It is important that these
1237 * aren't out of sync in any regard other than page pool tracking data.
1238 */
1239typedef struct PGMROMPAGE
1240{
1241 /** The page structure for the virgin ROM page. */
1242 PGMPAGE Virgin;
1243 /** The page structure for the shadow RAM page. */
1244 PGMPAGE Shadow;
1245 /** The current protection setting. */
1246 PGMROMPROT enmProt;
1247 /** Live save status information. Makes use of unused alignment space. */
1248 struct
1249 {
1250 /** The previous protection value. */
1251 uint8_t u8Prot;
1252 /** Written to flag set by the handler. */
1253 bool fWrittenTo;
1254 /** Whether the shadow page is dirty or not. */
1255 bool fDirty;
1256 /** Whether it was dirtied in the recently. */
1257 bool fDirtiedRecently;
1258 } LiveSave;
1259} PGMROMPAGE;
1260AssertCompileSizeAlignment(PGMROMPAGE, 8);
1261/** Pointer to a ROM page tracking structure. */
1262typedef PGMROMPAGE *PPGMROMPAGE;
1263
1264
1265/**
1266 * A registered ROM image.
1267 *
1268 * This is needed to keep track of ROM image since they generally intrude
1269 * into a PGMRAMRANGE. It also keeps track of additional info like the
1270 * two page sets (read-only virgin and read-write shadow), the current
1271 * state of each page.
1272 *
1273 * Because access handlers cannot easily be executed in a different
1274 * context, the ROM ranges needs to be accessible and in all contexts.
1275 */
1276typedef struct PGMROMRANGE
1277{
1278 /** Pointer to the next range - R3. */
1279 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1280 /** Pointer to the next range - R0. */
1281 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1282 /** Pointer to the next range - RC. */
1283 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1284 /** Pointer alignment */
1285 RTRCPTR RCPtrAlignment;
1286 /** Address of the range. */
1287 RTGCPHYS GCPhys;
1288 /** Address of the last byte in the range. */
1289 RTGCPHYS GCPhysLast;
1290 /** Size of the range. */
1291 RTGCPHYS cb;
1292 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1293 uint32_t fFlags;
1294 /** The saved state range ID. */
1295 uint8_t idSavedState;
1296 /** Alignment padding. */
1297 uint8_t au8Alignment[3];
1298 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1299 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1300 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1301 * This is used for strictness checks. */
1302 R3PTRTYPE(const void *) pvOriginal;
1303 /** The ROM description. */
1304 R3PTRTYPE(const char *) pszDesc;
1305 /** The per page tracking structures. */
1306 PGMROMPAGE aPages[1];
1307} PGMROMRANGE;
1308/** Pointer to a ROM range. */
1309typedef PGMROMRANGE *PPGMROMRANGE;
1310
1311
1312/**
1313 * Live save per page data for an MMIO2 page.
1314 *
1315 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1316 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1317 * CRC-32 for detecting changes as well as special handling of zero pages. This
1318 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1319 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1320 * because of speed (2.5x and 6x slower).)
1321 *
1322 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1323 * save but normally is disabled. Since we can write monitore guest
1324 * accesses on our own, we only need this for host accesses. Shouldn't be
1325 * too difficult for DevVGA, VMMDev might be doable, the planned
1326 * networking fun will be fun since it involves ring-0.
1327 */
1328typedef struct PGMLIVESAVEMMIO2PAGE
1329{
1330 /** Set if the page is considered dirty. */
1331 bool fDirty;
1332 /** The number of scans this page has remained unchanged for.
1333 * Only updated for dirty pages. */
1334 uint8_t cUnchangedScans;
1335 /** Whether this page was zero at the last scan. */
1336 bool fZero;
1337 /** Alignment padding. */
1338 bool fReserved;
1339 /** CRC-32 for the first half of the page.
1340 * This is used together with u32CrcH2 to quickly detect changes in the page
1341 * during the non-final passes. */
1342 uint32_t u32CrcH1;
1343 /** CRC-32 for the second half of the page. */
1344 uint32_t u32CrcH2;
1345 /** SHA-1 for the saved page.
1346 * This is used in the final pass to skip pages without changes. */
1347 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1348} PGMLIVESAVEMMIO2PAGE;
1349/** Pointer to a live save status data for an MMIO2 page. */
1350typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1351
1352/**
1353 * A registered MMIO2 (= Device RAM) range.
1354 *
1355 * There are a few reason why we need to keep track of these
1356 * registrations. One of them is the deregistration & cleanup stuff,
1357 * while another is that the PGMRAMRANGE associated with such a region may
1358 * have to be removed from the ram range list.
1359 *
1360 * Overlapping with a RAM range has to be 100% or none at all. The pages
1361 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1362 * will be raised if a partial overlap or an overlap of ROM pages is
1363 * encountered. On an overlap we will free all the existing RAM pages and
1364 * put in the ram range pages instead.
1365 */
1366typedef struct PGMMMIO2RANGE
1367{
1368 /** The owner of the range. (a device) */
1369 PPDMDEVINSR3 pDevInsR3;
1370 /** Pointer to the ring-3 mapping of the allocation. */
1371 RTR3PTR pvR3;
1372 /** Pointer to the next range - R3. */
1373 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1374 /** Whether it's mapped or not. */
1375 bool fMapped;
1376 /** Whether it's overlapping or not. */
1377 bool fOverlapping;
1378 /** The PCI region number.
1379 * @remarks This ASSUMES that nobody will ever really need to have multiple
1380 * PCI devices with matching MMIO region numbers on a single device. */
1381 uint8_t iRegion;
1382 /** The saved state range ID. */
1383 uint8_t idSavedState;
1384 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1385 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1386 /** Live save per page tracking data. */
1387 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1388 /** The associated RAM range. */
1389 PGMRAMRANGE RamRange;
1390} PGMMMIO2RANGE;
1391/** Pointer to a MMIO2 range. */
1392typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1393
1394
1395
1396
1397/**
1398 * PGMPhysRead/Write cache entry
1399 */
1400typedef struct PGMPHYSCACHEENTRY
1401{
1402 /** R3 pointer to physical page. */
1403 R3PTRTYPE(uint8_t *) pbR3;
1404 /** GC Physical address for cache entry */
1405 RTGCPHYS GCPhys;
1406#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1407 RTGCPHYS u32Padding0; /**< alignment padding. */
1408#endif
1409} PGMPHYSCACHEENTRY;
1410
1411/**
1412 * PGMPhysRead/Write cache to reduce REM memory access overhead
1413 */
1414typedef struct PGMPHYSCACHE
1415{
1416 /** Bitmap of valid cache entries */
1417 uint64_t aEntries;
1418 /** Cache entries */
1419 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1420} PGMPHYSCACHE;
1421
1422
1423/** Pointer to an allocation chunk ring-3 mapping. */
1424typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1425/** Pointer to an allocation chunk ring-3 mapping pointer. */
1426typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1427
1428/**
1429 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1430 *
1431 * The primary tree (Core) uses the chunk id as key.
1432 */
1433typedef struct PGMCHUNKR3MAP
1434{
1435 /** The key is the chunk id. */
1436 AVLU32NODECORE Core;
1437 /** The current age thingy. */
1438 uint32_t iAge;
1439 /** The current reference count. */
1440 uint32_t volatile cRefs;
1441 /** The current permanent reference count. */
1442 uint32_t volatile cPermRefs;
1443 /** The mapping address. */
1444 void *pv;
1445} PGMCHUNKR3MAP;
1446
1447/**
1448 * Allocation chunk ring-3 mapping TLB entry.
1449 */
1450typedef struct PGMCHUNKR3MAPTLBE
1451{
1452 /** The chunk id. */
1453 uint32_t volatile idChunk;
1454#if HC_ARCH_BITS == 64
1455 uint32_t u32Padding; /**< alignment padding. */
1456#endif
1457 /** The chunk map. */
1458#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1459 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1460#else
1461 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1462#endif
1463} PGMCHUNKR3MAPTLBE;
1464/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1465typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1466
1467/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1468 * @remark Must be a power of two value. */
1469#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1470
1471/**
1472 * Allocation chunk ring-3 mapping TLB.
1473 *
1474 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1475 * At first glance this might look kinda odd since AVL trees are
1476 * supposed to give the most optimial lookup times of all trees
1477 * due to their balancing. However, take a tree with 1023 nodes
1478 * in it, that's 10 levels, meaning that most searches has to go
1479 * down 9 levels before they find what they want. This isn't fast
1480 * compared to a TLB hit. There is the factor of cache misses,
1481 * and of course the problem with trees and branch prediction.
1482 * This is why we use TLBs in front of most of the trees.
1483 *
1484 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1485 * difficult when we switch to the new inlined AVL trees (from kStuff).
1486 */
1487typedef struct PGMCHUNKR3MAPTLB
1488{
1489 /** The TLB entries. */
1490 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1491} PGMCHUNKR3MAPTLB;
1492
1493/**
1494 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1495 * @returns Chunk TLB index.
1496 * @param idChunk The Chunk ID.
1497 */
1498#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1499
1500
1501/**
1502 * Ring-3 guest page mapping TLB entry.
1503 * @remarks used in ring-0 as well at the moment.
1504 */
1505typedef struct PGMPAGER3MAPTLBE
1506{
1507 /** Address of the page. */
1508 RTGCPHYS volatile GCPhys;
1509 /** The guest page. */
1510#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1511 R3PTRTYPE(PPGMPAGE) volatile pPage;
1512#else
1513 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1514#endif
1515 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1516#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1517 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1518#else
1519 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1520#endif
1521 /** The address */
1522#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1523 R3PTRTYPE(void *) volatile pv;
1524#else
1525 R3R0PTRTYPE(void *) volatile pv;
1526#endif
1527#if HC_ARCH_BITS == 32
1528 uint32_t u32Padding; /**< alignment padding. */
1529#endif
1530} PGMPAGER3MAPTLBE;
1531/** Pointer to an entry in the HC physical TLB. */
1532typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1533
1534
1535/** The number of entries in the ring-3 guest page mapping TLB.
1536 * @remarks The value must be a power of two. */
1537#define PGM_PAGER3MAPTLB_ENTRIES 256
1538
1539/**
1540 * Ring-3 guest page mapping TLB.
1541 * @remarks used in ring-0 as well at the moment.
1542 */
1543typedef struct PGMPAGER3MAPTLB
1544{
1545 /** The TLB entries. */
1546 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1547} PGMPAGER3MAPTLB;
1548/** Pointer to the ring-3 guest page mapping TLB. */
1549typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1550
1551/**
1552 * Calculates the index of the TLB entry for the specified guest page.
1553 * @returns Physical TLB index.
1554 * @param GCPhys The guest physical address.
1555 */
1556#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1557
1558
1559/**
1560 * Mapping cache usage set entry.
1561 *
1562 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1563 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1564 * cache. If it's extended to include ring-3, well, then something will
1565 * have be changed here...
1566 */
1567typedef struct PGMMAPSETENTRY
1568{
1569 /** The mapping cache index. */
1570 uint16_t iPage;
1571 /** The number of references.
1572 * The max is UINT16_MAX - 1. */
1573 uint16_t cRefs;
1574#if HC_ARCH_BITS == 64
1575 uint32_t alignment;
1576#endif
1577 /** Pointer to the page. */
1578 RTR0PTR pvPage;
1579 /** The physical address for this entry. */
1580 RTHCPHYS HCPhys;
1581} PGMMAPSETENTRY;
1582/** Pointer to a mapping cache usage set entry. */
1583typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1584
1585/**
1586 * Mapping cache usage set.
1587 *
1588 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1589 * done during exits / traps. The set is
1590 */
1591typedef struct PGMMAPSET
1592{
1593 /** The number of occupied entries.
1594 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1595 * dynamic mappings. */
1596 uint32_t cEntries;
1597 /** The start of the current subset.
1598 * This is UINT32_MAX if no subset is currently open. */
1599 uint32_t iSubset;
1600 /** The index of the current CPU, only valid if the set is open. */
1601 int32_t iCpu;
1602 uint32_t alignment;
1603 /** The entries. */
1604 PGMMAPSETENTRY aEntries[64];
1605 /** HCPhys -> iEntry fast lookup table.
1606 * Use PGMMAPSET_HASH for hashing.
1607 * The entries may or may not be valid, check against cEntries. */
1608 uint8_t aiHashTable[128];
1609} PGMMAPSET;
1610AssertCompileSizeAlignment(PGMMAPSET, 8);
1611/** Pointer to the mapping cache set. */
1612typedef PGMMAPSET *PPGMMAPSET;
1613
1614/** PGMMAPSET::cEntries value for a closed set. */
1615#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1616
1617/** Hash function for aiHashTable. */
1618#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1619
1620/** The max fill size (strict builds). */
1621#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1622
1623
1624/** @name Context neutrual page mapper TLB.
1625 *
1626 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1627 * code is writting in a kind of context neutrual way. Time will show whether
1628 * this actually makes sense or not...
1629 *
1630 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1631 * context ends up using a global mapping cache on some platforms
1632 * (darwin).
1633 *
1634 * @{ */
1635/** @typedef PPGMPAGEMAPTLB
1636 * The page mapper TLB pointer type for the current context. */
1637/** @typedef PPGMPAGEMAPTLB
1638 * The page mapper TLB entry pointer type for the current context. */
1639/** @typedef PPGMPAGEMAPTLB
1640 * The page mapper TLB entry pointer pointer type for the current context. */
1641/** @def PGM_PAGEMAPTLB_ENTRIES
1642 * The number of TLB entries in the page mapper TLB for the current context. */
1643/** @def PGM_PAGEMAPTLB_IDX
1644 * Calculate the TLB index for a guest physical address.
1645 * @returns The TLB index.
1646 * @param GCPhys The guest physical address. */
1647/** @typedef PPGMPAGEMAP
1648 * Pointer to a page mapper unit for current context. */
1649/** @typedef PPPGMPAGEMAP
1650 * Pointer to a page mapper unit pointer for current context. */
1651#ifdef IN_RC
1652// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1653// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1654// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1655# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1656# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1657 typedef void * PPGMPAGEMAP;
1658 typedef void ** PPPGMPAGEMAP;
1659//#elif IN_RING0
1660// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1661// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1662// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1663//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1664//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1665// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1666// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1667#else
1668 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1669 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1670 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1671# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1672# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1673 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1674 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1675#endif
1676/** @} */
1677
1678
1679/** @name PGM Pool Indexes.
1680 * Aka. the unique shadow page identifier.
1681 * @{ */
1682/** NIL page pool IDX. */
1683#define NIL_PGMPOOL_IDX 0
1684/** The first normal index. */
1685#define PGMPOOL_IDX_FIRST_SPECIAL 1
1686/** Page directory (32-bit root). */
1687#define PGMPOOL_IDX_PD 1
1688/** Page Directory Pointer Table (PAE root). */
1689#define PGMPOOL_IDX_PDPT 2
1690/** AMD64 CR3 level index.*/
1691#define PGMPOOL_IDX_AMD64_CR3 3
1692/** Nested paging root.*/
1693#define PGMPOOL_IDX_NESTED_ROOT 4
1694/** The first normal index. */
1695#define PGMPOOL_IDX_FIRST 5
1696/** The last valid index. (inclusive, 14 bits) */
1697#define PGMPOOL_IDX_LAST 0x3fff
1698/** @} */
1699
1700/** The NIL index for the parent chain. */
1701#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1702#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1703
1704/**
1705 * Node in the chain linking a shadowed page to it's parent (user).
1706 */
1707#pragma pack(1)
1708typedef struct PGMPOOLUSER
1709{
1710 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1711 uint16_t iNext;
1712 /** The user page index. */
1713 uint16_t iUser;
1714 /** Index into the user table. */
1715 uint32_t iUserTable;
1716} PGMPOOLUSER, *PPGMPOOLUSER;
1717typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1718#pragma pack()
1719
1720
1721/** The NIL index for the phys ext chain. */
1722#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1723/** The NIL pte index for a phys ext chain slot. */
1724#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1725
1726/**
1727 * Node in the chain of physical cross reference extents.
1728 * @todo Calling this an 'extent' is not quite right, find a better name.
1729 * @todo find out the optimal size of the aidx array
1730 */
1731#pragma pack(1)
1732typedef struct PGMPOOLPHYSEXT
1733{
1734 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1735 uint16_t iNext;
1736 /** Alignment. */
1737 uint16_t u16Align;
1738 /** The user page index. */
1739 uint16_t aidx[3];
1740 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1741 uint16_t apte[3];
1742} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1743typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1744#pragma pack()
1745
1746
1747/**
1748 * The kind of page that's being shadowed.
1749 */
1750typedef enum PGMPOOLKIND
1751{
1752 /** The virtual invalid 0 entry. */
1753 PGMPOOLKIND_INVALID = 0,
1754 /** The entry is free (=unused). */
1755 PGMPOOLKIND_FREE,
1756
1757 /** Shw: 32-bit page table; Gst: no paging */
1758 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1759 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1760 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1761 /** Shw: 32-bit page table; Gst: 4MB page. */
1762 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1763 /** Shw: PAE page table; Gst: no paging */
1764 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1765 /** Shw: PAE page table; Gst: 32-bit page table. */
1766 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1767 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1768 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1769 /** Shw: PAE page table; Gst: PAE page table. */
1770 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1771 /** Shw: PAE page table; Gst: 2MB page. */
1772 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1773
1774 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1775 PGMPOOLKIND_32BIT_PD,
1776 /** Shw: 32-bit page directory. Gst: no paging. */
1777 PGMPOOLKIND_32BIT_PD_PHYS,
1778 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1779 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1780 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1781 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1782 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1783 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1784 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1785 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1786 /** Shw: PAE page directory; Gst: PAE page directory. */
1787 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1788 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1789 PGMPOOLKIND_PAE_PD_PHYS,
1790
1791 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1792 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1793 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1794 PGMPOOLKIND_PAE_PDPT,
1795 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1796 PGMPOOLKIND_PAE_PDPT_PHYS,
1797
1798 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1799 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1800 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1801 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1802 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1803 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1804 /** Shw: 64-bit page directory table; Gst: no paging */
1805 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1806
1807 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1808 PGMPOOLKIND_64BIT_PML4,
1809
1810 /** Shw: EPT page directory pointer table; Gst: no paging */
1811 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1812 /** Shw: EPT page directory table; Gst: no paging */
1813 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1814 /** Shw: EPT page table; Gst: no paging */
1815 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1816
1817 /** Shw: Root Nested paging table. */
1818 PGMPOOLKIND_ROOT_NESTED,
1819
1820 /** The last valid entry. */
1821 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1822} PGMPOOLKIND;
1823
1824/**
1825 * The access attributes of the page; only applies to big pages.
1826 */
1827typedef enum
1828{
1829 PGMPOOLACCESS_DONTCARE = 0,
1830 PGMPOOLACCESS_USER_RW,
1831 PGMPOOLACCESS_USER_R,
1832 PGMPOOLACCESS_USER_RW_NX,
1833 PGMPOOLACCESS_USER_R_NX,
1834 PGMPOOLACCESS_SUPERVISOR_RW,
1835 PGMPOOLACCESS_SUPERVISOR_R,
1836 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1837 PGMPOOLACCESS_SUPERVISOR_R_NX
1838} PGMPOOLACCESS;
1839
1840/**
1841 * The tracking data for a page in the pool.
1842 */
1843typedef struct PGMPOOLPAGE
1844{
1845 /** AVL node code with the (R3) physical address of this page. */
1846 AVLOHCPHYSNODECORE Core;
1847 /** Pointer to the R3 mapping of the page. */
1848#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1849 R3PTRTYPE(void *) pvPageR3;
1850#else
1851 R3R0PTRTYPE(void *) pvPageR3;
1852#endif
1853 /** The guest physical address. */
1854#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1855 uint32_t Alignment0;
1856#endif
1857 RTGCPHYS GCPhys;
1858
1859 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1860 RTGCPTR pvLastAccessHandlerRip;
1861 RTGCPTR pvLastAccessHandlerFault;
1862 uint64_t cLastAccessHandlerCount;
1863
1864 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1865 uint8_t enmKind;
1866 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1867 uint8_t enmAccess;
1868 /** The index of this page. */
1869 uint16_t idx;
1870 /** The next entry in the list this page currently resides in.
1871 * It's either in the free list or in the GCPhys hash. */
1872 uint16_t iNext;
1873 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1874 uint16_t iUserHead;
1875 /** The number of present entries. */
1876 uint16_t cPresent;
1877 /** The first entry in the table which is present. */
1878 uint16_t iFirstPresent;
1879 /** The number of modifications to the monitored page. */
1880 uint16_t cModifications;
1881 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1882 uint16_t iModifiedNext;
1883 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1884 uint16_t iModifiedPrev;
1885 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1886 uint16_t iMonitoredNext;
1887 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1888 uint16_t iMonitoredPrev;
1889 /** The next page in the age list. */
1890 uint16_t iAgeNext;
1891 /** The previous page in the age list. */
1892 uint16_t iAgePrev;
1893 /** Used to indicate that the page is zeroed. */
1894 bool fZeroed;
1895 /** Used to indicate that a PT has non-global entries. */
1896 bool fSeenNonGlobal;
1897 /** Used to indicate that we're monitoring writes to the guest page. */
1898 bool fMonitored;
1899 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1900 * (All pages are in the age list.) */
1901 bool fCached;
1902 /** This is used by the R3 access handlers when invoked by an async thread.
1903 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1904 bool volatile fReusedFlushPending;
1905 /** Used to mark the page as dirty (write monitoring is temporarily
1906 * off). */
1907 bool fDirty;
1908
1909 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1910 uint32_t cLocked;
1911 uint32_t idxDirty;
1912 RTGCPTR pvDirtyFault;
1913} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1914/** Pointer to a const pool page. */
1915typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1916
1917
1918/** The hash table size. */
1919# define PGMPOOL_HASH_SIZE 0x40
1920/** The hash function. */
1921# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1922
1923
1924/**
1925 * The shadow page pool instance data.
1926 *
1927 * It's all one big allocation made at init time, except for the
1928 * pages that is. The user nodes follows immediatly after the
1929 * page structures.
1930 */
1931typedef struct PGMPOOL
1932{
1933 /** The VM handle - R3 Ptr. */
1934 PVMR3 pVMR3;
1935 /** The VM handle - R0 Ptr. */
1936 PVMR0 pVMR0;
1937 /** The VM handle - RC Ptr. */
1938 PVMRC pVMRC;
1939 /** The max pool size. This includes the special IDs. */
1940 uint16_t cMaxPages;
1941 /** The current pool size. */
1942 uint16_t cCurPages;
1943 /** The head of the free page list. */
1944 uint16_t iFreeHead;
1945 /* Padding. */
1946 uint16_t u16Padding;
1947 /** Head of the chain of free user nodes. */
1948 uint16_t iUserFreeHead;
1949 /** The number of user nodes we've allocated. */
1950 uint16_t cMaxUsers;
1951 /** The number of present page table entries in the entire pool. */
1952 uint32_t cPresent;
1953 /** Pointer to the array of user nodes - RC pointer. */
1954 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1955 /** Pointer to the array of user nodes - R3 pointer. */
1956 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1957 /** Pointer to the array of user nodes - R0 pointer. */
1958 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1959 /** Head of the chain of free phys ext nodes. */
1960 uint16_t iPhysExtFreeHead;
1961 /** The number of user nodes we've allocated. */
1962 uint16_t cMaxPhysExts;
1963 /** Pointer to the array of physical xref extent - RC pointer. */
1964 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1965 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1966 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1967 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1968 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1969 /** Hash table for GCPhys addresses. */
1970 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1971 /** The head of the age list. */
1972 uint16_t iAgeHead;
1973 /** The tail of the age list. */
1974 uint16_t iAgeTail;
1975 /** Set if the cache is enabled. */
1976 bool fCacheEnabled;
1977 /** Alignment padding. */
1978 bool afPadding1[3];
1979 /** Head of the list of modified pages. */
1980 uint16_t iModifiedHead;
1981 /** The current number of modified pages. */
1982 uint16_t cModifiedPages;
1983 /** Access handler, RC. */
1984 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1985 /** Access handler, R0. */
1986 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1987 /** Access handler, R3. */
1988 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1989 /** The access handler description (R3 ptr). */
1990 R3PTRTYPE(const char *) pszAccessHandler;
1991# if HC_ARCH_BITS == 32
1992 /** Alignment padding. */
1993 uint32_t u32Padding2;
1994# endif
1995 /* Next available slot. */
1996 uint32_t idxFreeDirtyPage;
1997 /* Number of active dirty pages. */
1998 uint32_t cDirtyPages;
1999 /* Array of current dirty pgm pool page indices. */
2000 uint16_t aIdxDirtyPages[16];
2001 uint64_t aDirtyPages[16][512];
2002 /** The number of pages currently in use. */
2003 uint16_t cUsedPages;
2004#ifdef VBOX_WITH_STATISTICS
2005 /** The high water mark for cUsedPages. */
2006 uint16_t cUsedPagesHigh;
2007 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2008 /** Profiling pgmPoolAlloc(). */
2009 STAMPROFILEADV StatAlloc;
2010 /** Profiling pgmR3PoolClearDoIt(). */
2011 STAMPROFILE StatClearAll;
2012 /** Profiling pgmR3PoolReset(). */
2013 STAMPROFILE StatR3Reset;
2014 /** Profiling pgmPoolFlushPage(). */
2015 STAMPROFILE StatFlushPage;
2016 /** Profiling pgmPoolFree(). */
2017 STAMPROFILE StatFree;
2018 /** Counting explicit flushes by PGMPoolFlushPage(). */
2019 STAMCOUNTER StatForceFlushPage;
2020 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2021 STAMCOUNTER StatForceFlushDirtyPage;
2022 /** Counting flushes for reused pages. */
2023 STAMCOUNTER StatForceFlushReused;
2024 /** Profiling time spent zeroing pages. */
2025 STAMPROFILE StatZeroPage;
2026 /** Profiling of pgmPoolTrackDeref. */
2027 STAMPROFILE StatTrackDeref;
2028 /** Profiling pgmTrackFlushGCPhysPT. */
2029 STAMPROFILE StatTrackFlushGCPhysPT;
2030 /** Profiling pgmTrackFlushGCPhysPTs. */
2031 STAMPROFILE StatTrackFlushGCPhysPTs;
2032 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2033 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2034 /** Number of times we've been out of user records. */
2035 STAMCOUNTER StatTrackFreeUpOneUser;
2036 /** Nr of flushed entries. */
2037 STAMCOUNTER StatTrackFlushEntry;
2038 /** Nr of updated entries. */
2039 STAMCOUNTER StatTrackFlushEntryKeep;
2040 /** Profiling deref activity related tracking GC physical pages. */
2041 STAMPROFILE StatTrackDerefGCPhys;
2042 /** Number of linear searches for a HCPhys in the ram ranges. */
2043 STAMCOUNTER StatTrackLinearRamSearches;
2044 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2045 STAMCOUNTER StamTrackPhysExtAllocFailures;
2046 /** Profiling the RC/R0 access handler. */
2047 STAMPROFILE StatMonitorRZ;
2048 /** Times we've failed interpreting the instruction. */
2049 STAMCOUNTER StatMonitorRZEmulateInstr;
2050 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2051 STAMPROFILE StatMonitorRZFlushPage;
2052 /* Times we've detected a page table reinit. */
2053 STAMCOUNTER StatMonitorRZFlushReinit;
2054 /** Counting flushes for pages that are modified too often. */
2055 STAMCOUNTER StatMonitorRZFlushModOverflow;
2056 /** Times we've detected fork(). */
2057 STAMCOUNTER StatMonitorRZFork;
2058 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2059 STAMPROFILE StatMonitorRZHandled;
2060 /** Times we've failed interpreting a patch code instruction. */
2061 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2062 /** Times we've failed interpreting a patch code instruction during flushing. */
2063 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2064 /** The number of times we've seen rep prefixes we can't handle. */
2065 STAMCOUNTER StatMonitorRZRepPrefix;
2066 /** Profiling the REP STOSD cases we've handled. */
2067 STAMPROFILE StatMonitorRZRepStosd;
2068 /** Nr of handled PT faults. */
2069 STAMCOUNTER StatMonitorRZFaultPT;
2070 /** Nr of handled PD faults. */
2071 STAMCOUNTER StatMonitorRZFaultPD;
2072 /** Nr of handled PDPT faults. */
2073 STAMCOUNTER StatMonitorRZFaultPDPT;
2074 /** Nr of handled PML4 faults. */
2075 STAMCOUNTER StatMonitorRZFaultPML4;
2076
2077 /** Profiling the R3 access handler. */
2078 STAMPROFILE StatMonitorR3;
2079 /** Times we've failed interpreting the instruction. */
2080 STAMCOUNTER StatMonitorR3EmulateInstr;
2081 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2082 STAMPROFILE StatMonitorR3FlushPage;
2083 /* Times we've detected a page table reinit. */
2084 STAMCOUNTER StatMonitorR3FlushReinit;
2085 /** Counting flushes for pages that are modified too often. */
2086 STAMCOUNTER StatMonitorR3FlushModOverflow;
2087 /** Times we've detected fork(). */
2088 STAMCOUNTER StatMonitorR3Fork;
2089 /** Profiling the R3 access we've handled (except REP STOSD). */
2090 STAMPROFILE StatMonitorR3Handled;
2091 /** The number of times we've seen rep prefixes we can't handle. */
2092 STAMCOUNTER StatMonitorR3RepPrefix;
2093 /** Profiling the REP STOSD cases we've handled. */
2094 STAMPROFILE StatMonitorR3RepStosd;
2095 /** Nr of handled PT faults. */
2096 STAMCOUNTER StatMonitorR3FaultPT;
2097 /** Nr of handled PD faults. */
2098 STAMCOUNTER StatMonitorR3FaultPD;
2099 /** Nr of handled PDPT faults. */
2100 STAMCOUNTER StatMonitorR3FaultPDPT;
2101 /** Nr of handled PML4 faults. */
2102 STAMCOUNTER StatMonitorR3FaultPML4;
2103 /** The number of times we're called in an async thread an need to flush. */
2104 STAMCOUNTER StatMonitorR3Async;
2105 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2106 STAMCOUNTER StatResetDirtyPages;
2107 /** Times we've called pgmPoolAddDirtyPage. */
2108 STAMCOUNTER StatDirtyPage;
2109 /** Times we've had to flush duplicates for dirty page management. */
2110 STAMCOUNTER StatDirtyPageDupFlush;
2111 /** Times we've had to flush because of overflow. */
2112 STAMCOUNTER StatDirtyPageOverFlowFlush;
2113
2114 /** The high wather mark for cModifiedPages. */
2115 uint16_t cModifiedPagesHigh;
2116 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2117
2118 /** The number of cache hits. */
2119 STAMCOUNTER StatCacheHits;
2120 /** The number of cache misses. */
2121 STAMCOUNTER StatCacheMisses;
2122 /** The number of times we've got a conflict of 'kind' in the cache. */
2123 STAMCOUNTER StatCacheKindMismatches;
2124 /** Number of times we've been out of pages. */
2125 STAMCOUNTER StatCacheFreeUpOne;
2126 /** The number of cacheable allocations. */
2127 STAMCOUNTER StatCacheCacheable;
2128 /** The number of uncacheable allocations. */
2129 STAMCOUNTER StatCacheUncacheable;
2130#else
2131 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2132#endif
2133 /** The AVL tree for looking up a page by its HC physical address. */
2134 AVLOHCPHYSTREE HCPhysTree;
2135 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2136 /** Array of pages. (cMaxPages in length)
2137 * The Id is the index into thist array.
2138 */
2139 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2140} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2141AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2142AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2143AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2144#ifdef VBOX_WITH_STATISTICS
2145AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2146#endif
2147AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2148
2149
2150/** @def PGMPOOL_PAGE_2_PTR
2151 * Maps a pool page pool into the current context.
2152 *
2153 * @returns VBox status code.
2154 * @param pVM The VM handle.
2155 * @param pPage The pool page.
2156 *
2157 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2158 * small page window employeed by that function. Be careful.
2159 * @remark There is no need to assert on the result.
2160 */
2161#if defined(IN_RC)
2162# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2163#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2164# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2165#elif defined(VBOX_STRICT)
2166# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2167DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2168{
2169 Assert(pPage && pPage->pvPageR3);
2170 return pPage->pvPageR3;
2171}
2172#else
2173# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2174#endif
2175
2176/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2177 * Maps a pool page pool into the current context.
2178 *
2179 * @returns VBox status code.
2180 * @param pPGM Pointer to the PGM instance data.
2181 * @param pPage The pool page.
2182 *
2183 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2184 * small page window employeed by that function. Be careful.
2185 * @remark There is no need to assert on the result.
2186 */
2187#if defined(IN_RC)
2188# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2189#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2190# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2191#else
2192# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2193#endif
2194
2195/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2196 * Maps a pool page pool into the current context.
2197 *
2198 * @returns VBox status code.
2199 * @param pPGM Pointer to the PGMCPU instance data.
2200 * @param pPage The pool page.
2201 *
2202 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2203 * small page window employeed by that function. Be careful.
2204 * @remark There is no need to assert on the result.
2205 */
2206#if defined(IN_RC)
2207# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2208#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2209# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2210#else
2211# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2212#endif
2213
2214
2215/** @name Per guest page tracking data.
2216 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2217 * is to use more bits for it and split it up later on. But for now we'll play
2218 * safe and change as little as possible.
2219 *
2220 * The 16-bit word has two parts:
2221 *
2222 * The first 14-bit forms the @a idx field. It is either the index of a page in
2223 * the shadow page pool, or and index into the extent list.
2224 *
2225 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2226 * shadow page pool references to the page. If cRefs equals
2227 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2228 * (misnomer) table and not the shadow page pool.
2229 *
2230 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2231 * the 16-bit word.
2232 *
2233 * @{ */
2234/** The shift count for getting to the cRefs part. */
2235#define PGMPOOL_TD_CREFS_SHIFT 14
2236/** The mask applied after shifting the tracking data down by
2237 * PGMPOOL_TD_CREFS_SHIFT. */
2238#define PGMPOOL_TD_CREFS_MASK 0x3
2239/** The cRef value used to indiciate that the idx is the head of a
2240 * physical cross reference list. */
2241#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2242/** The shift used to get idx. */
2243#define PGMPOOL_TD_IDX_SHIFT 0
2244/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2245#define PGMPOOL_TD_IDX_MASK 0x3fff
2246/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2247 * simply too many mappings of this page. */
2248#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2249
2250/** @def PGMPOOL_TD_MAKE
2251 * Makes a 16-bit tracking data word.
2252 *
2253 * @returns tracking data.
2254 * @param cRefs The @a cRefs field. Must be within bounds!
2255 * @param idx The @a idx field. Must also be within bounds! */
2256#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2257
2258/** @def PGMPOOL_TD_GET_CREFS
2259 * Get the @a cRefs field from a tracking data word.
2260 *
2261 * @returns The @a cRefs field
2262 * @param u16 The tracking data word. */
2263#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2264
2265/** @def PGMPOOL_TD_GET_IDX
2266 * Get the @a idx field from a tracking data word.
2267 *
2268 * @returns The @a idx field
2269 * @param u16 The tracking data word. */
2270#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2271/** @} */
2272
2273
2274/**
2275 * Trees are using self relative offsets as pointers.
2276 * So, all its data, including the root pointer, must be in the heap for HC and GC
2277 * to have the same layout.
2278 */
2279typedef struct PGMTREES
2280{
2281 /** Physical access handlers (AVL range+offsetptr tree). */
2282 AVLROGCPHYSTREE PhysHandlers;
2283 /** Virtual access handlers (AVL range + GC ptr tree). */
2284 AVLROGCPTRTREE VirtHandlers;
2285 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2286 AVLROGCPHYSTREE PhysToVirtHandlers;
2287 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2288 AVLROGCPTRTREE HyperVirtHandlers;
2289} PGMTREES;
2290/** Pointer to PGM trees. */
2291typedef PGMTREES *PPGMTREES;
2292
2293
2294/**
2295 * Page fault guest state for the AMD64 paging mode.
2296 */
2297typedef struct PGMPTWALKCORE
2298{
2299 /** The guest virtual address that is being resolved by the walk
2300 * (input). */
2301 RTGCPTR GCPtr;
2302
2303 /** The guest physcial address that is the result of the walk.
2304 * @remarks only valid if fSucceeded is set. */
2305 RTGCPHYS GCPhys;
2306
2307 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2308 bool fSucceeded;
2309 /** The level problem arrised at.
2310 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2311 * level 8. This is 0 on success. */
2312 uint8_t uLevel;
2313 /** Set if the page isn't present. */
2314 bool fNotPresent;
2315 /** Encountered a bad physical address. */
2316 bool fBadPhysAddr;
2317 /** Set if there was reserved bit violations. */
2318 bool fRsvdError;
2319 /** Set if it involves a big page (2/4 MB). */
2320 bool fBigPage;
2321 /** Set if it involves a gigantic page (1 GB). */
2322 bool fGigantPage;
2323 /** The effect X86_PTE_US flag for the address. */
2324 bool fEffectiveUS;
2325 /** The effect X86_PTE_RW flag for the address. */
2326 bool fEffectiveRW;
2327 /** The effect X86_PTE_NX flag for the address. */
2328 bool fEffectiveNX;
2329} PGMPTWALKCORE;
2330
2331
2332/**
2333 * Guest page table walk for the AMD64 mode.
2334 */
2335typedef struct PGMPTWALKGSTAMD64
2336{
2337 /** The common core. */
2338 PGMPTWALKCORE Core;
2339
2340 PX86PML4 pPml4;
2341 PX86PML4E pPml4e;
2342 X86PML4E Pml4e;
2343
2344 PX86PDPT pPdpt;
2345 PX86PDPE pPdpe;
2346 X86PDPE Pdpe;
2347
2348 PX86PDPAE pPd;
2349 PX86PDEPAE pPde;
2350 X86PDEPAE Pde;
2351
2352 PX86PTPAE pPt;
2353 PX86PTEPAE pPte;
2354 X86PTEPAE Pte;
2355} PGMPTWALKGSTAMD64;
2356/** Pointer to a AMD64 guest page table walk. */
2357typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2358/** Pointer to a const AMD64 guest page table walk. */
2359typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2360
2361/**
2362 * Guest page table walk for the PAE mode.
2363 */
2364typedef struct PGMPTWALKGSTPAE
2365{
2366 /** The common core. */
2367 PGMPTWALKCORE Core;
2368
2369 PX86PDPT pPdpt;
2370 PX86PDPE pPdpe;
2371 X86PDPE Pdpe;
2372
2373 PX86PDPAE pPd;
2374 PX86PDEPAE pPde;
2375 X86PDEPAE Pde;
2376
2377 PX86PTPAE pPt;
2378 PX86PTEPAE pPte;
2379 X86PTEPAE Pte;
2380} PGMPTWALKGSTPAE;
2381/** Pointer to a PAE guest page table walk. */
2382typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2383/** Pointer to a const AMD64 guest page table walk. */
2384typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2385
2386/**
2387 * Guest page table walk for the 32-bit mode.
2388 */
2389typedef struct PGMPTWALKGST32BIT
2390{
2391 /** The common core. */
2392 PGMPTWALKCORE Core;
2393
2394 PX86PD pPd;
2395 PX86PDE pPde;
2396 X86PDE Pde;
2397
2398 PX86PT pPt;
2399 PX86PTE pPte;
2400 X86PTE Pte;
2401} PGMPTWALKGST32BIT;
2402/** Pointer to a 32-bit guest page table walk. */
2403typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2404/** Pointer to a const 32-bit guest page table walk. */
2405typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2406
2407
2408/** @name Paging mode macros
2409 * @{
2410 */
2411#ifdef IN_RC
2412# define PGM_CTX(a,b) a##RC##b
2413# define PGM_CTX_STR(a,b) a "GC" b
2414# define PGM_CTX_DECL(type) VMMRCDECL(type)
2415#else
2416# ifdef IN_RING3
2417# define PGM_CTX(a,b) a##R3##b
2418# define PGM_CTX_STR(a,b) a "R3" b
2419# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2420# else
2421# define PGM_CTX(a,b) a##R0##b
2422# define PGM_CTX_STR(a,b) a "R0" b
2423# define PGM_CTX_DECL(type) VMMDECL(type)
2424# endif
2425#endif
2426
2427#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2428#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2429#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2430#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2431#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2432#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2433#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2434#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2435#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2436#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2437#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2438#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2439#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2440#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2441#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2442#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2443#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2444
2445#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2446#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2447#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2448#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2449#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2450#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2451#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2452#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2453#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2454#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2455#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2456#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2457#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2458#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2459#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2460#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2461#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2462
2463/* Shw_Gst */
2464#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2465#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2466#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2467#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2468#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2469#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2470#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2471#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2472#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2473#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2474#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2475#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2476#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2477#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2478#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2479#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2480#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2481#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2482#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2483
2484#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2485#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2486#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2487#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2488#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2489#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2490#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2491#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2492#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2493#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2494#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2495#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2496#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2497#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2498#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2499#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2500#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2501#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2502#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2503#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2504#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2505#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2506#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2507#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2508#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2509#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2510#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2511#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2512#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2513#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2514#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2515#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2516#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2517#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2518#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2519#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2520#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2521
2522#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2523#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2524/** @} */
2525
2526/**
2527 * Data for each paging mode.
2528 */
2529typedef struct PGMMODEDATA
2530{
2531 /** The guest mode type. */
2532 uint32_t uGstType;
2533 /** The shadow mode type. */
2534 uint32_t uShwType;
2535
2536 /** @name Function pointers for Shadow paging.
2537 * @{
2538 */
2539 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2540 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2541 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2542 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2543
2544 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2545 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2546
2547 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2548 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2549 /** @} */
2550
2551 /** @name Function pointers for Guest paging.
2552 * @{
2553 */
2554 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2555 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2556 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2557 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2558 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2559 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2560 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2561 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2562 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2563 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2564 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2565 /** @} */
2566
2567 /** @name Function pointers for Both Shadow and Guest paging.
2568 * @{
2569 */
2570 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2571 /* no pfnR3BthTrap0eHandler */
2572 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2573 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2574 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2575 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2576#ifdef VBOX_STRICT
2577 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2578#endif
2579 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2580 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2581
2582 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2583 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2584 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2585 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2586 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2587#ifdef VBOX_STRICT
2588 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2589#endif
2590 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2591 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2592
2593 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2594 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2595 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2596 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2597 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2598#ifdef VBOX_STRICT
2599 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2600#endif
2601 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2602 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2603 /** @} */
2604} PGMMODEDATA, *PPGMMODEDATA;
2605
2606
2607#ifdef VBOX_WITH_STATISTICS
2608/**
2609 * PGM statistics.
2610 *
2611 * These lives on the heap when compiled in as they would otherwise waste
2612 * unecessary space in release builds.
2613 */
2614typedef struct PGMSTATS
2615{
2616 /* R3 only: */
2617 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2618 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2619
2620 /* R3+RZ */
2621 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2622 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2623 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2624 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2625 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2626 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2627 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2628 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2629 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2630 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2631 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2632 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2633 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2634 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2635 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2636 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2637 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2638 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2639 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2640 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2641 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2642 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2643 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2644 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2645/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2646 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2647 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2648/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2649
2650 /* RC only: */
2651 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2652 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2653 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2654 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2655
2656 STAMCOUNTER StatRZPhysRead;
2657 STAMCOUNTER StatRZPhysReadBytes;
2658 STAMCOUNTER StatRZPhysWrite;
2659 STAMCOUNTER StatRZPhysWriteBytes;
2660 STAMCOUNTER StatR3PhysRead;
2661 STAMCOUNTER StatR3PhysReadBytes;
2662 STAMCOUNTER StatR3PhysWrite;
2663 STAMCOUNTER StatR3PhysWriteBytes;
2664 STAMCOUNTER StatRCPhysRead;
2665 STAMCOUNTER StatRCPhysReadBytes;
2666 STAMCOUNTER StatRCPhysWrite;
2667 STAMCOUNTER StatRCPhysWriteBytes;
2668
2669 STAMCOUNTER StatRZPhysSimpleRead;
2670 STAMCOUNTER StatRZPhysSimpleReadBytes;
2671 STAMCOUNTER StatRZPhysSimpleWrite;
2672 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2673 STAMCOUNTER StatR3PhysSimpleRead;
2674 STAMCOUNTER StatR3PhysSimpleReadBytes;
2675 STAMCOUNTER StatR3PhysSimpleWrite;
2676 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2677 STAMCOUNTER StatRCPhysSimpleRead;
2678 STAMCOUNTER StatRCPhysSimpleReadBytes;
2679 STAMCOUNTER StatRCPhysSimpleWrite;
2680 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2681
2682 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2683 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2684 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2685 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2686 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2687 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2688 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2689
2690 /** Time spent by the host OS for large page allocation. */
2691 STAMPROFILE StatAllocLargePage;
2692 /** Time spent clearing the newly allocated large pages. */
2693 STAMPROFILE StatClearLargePage;
2694 /** pgmPhysIsValidLargePage profiling - R3 */
2695 STAMPROFILE StatR3IsValidLargePage;
2696 /** pgmPhysIsValidLargePage profiling - RZ*/
2697 STAMPROFILE StatRZIsValidLargePage;
2698
2699 STAMPROFILE StatChunkAging;
2700 STAMPROFILE StatChunkFindCandidate;
2701 STAMPROFILE StatChunkUnmap;
2702 STAMPROFILE StatChunkMap;
2703} PGMSTATS;
2704#endif /* VBOX_WITH_STATISTICS */
2705
2706
2707/**
2708 * Converts a PGM pointer into a VM pointer.
2709 * @returns Pointer to the VM structure the PGM is part of.
2710 * @param pPGM Pointer to PGM instance data.
2711 */
2712#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2713
2714/**
2715 * PGM Data (part of VM)
2716 */
2717typedef struct PGM
2718{
2719 /** Offset to the VM structure. */
2720 int32_t offVM;
2721 /** Offset of the PGMCPU structure relative to VMCPU. */
2722 int32_t offVCpuPGM;
2723
2724 /** @cfgm{RamPreAlloc, boolean, false}
2725 * Indicates whether the base RAM should all be allocated before starting
2726 * the VM (default), or if it should be allocated when first written to.
2727 */
2728 bool fRamPreAlloc;
2729 /** Indicates whether write monitoring is currently in use.
2730 * This is used to prevent conflicts between live saving and page sharing
2731 * detection. */
2732 bool fPhysWriteMonitoringEngaged;
2733 /** Set if the CPU has less than 52-bit physical address width.
2734 * This is used */
2735 bool fLessThan52PhysicalAddressBits;
2736 /** Set when nested paging is active.
2737 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2738 * compilers optimize the code better. Whether we use nested paging or
2739 * not is something we find out during VMM initialization and we won't
2740 * change this later on. */
2741 bool fNestedPaging;
2742 /** The host paging mode. (This is what SUPLib reports.) */
2743 SUPPAGINGMODE enmHostMode;
2744 /** We're not in a state which permits writes to guest memory.
2745 * (Only used in strict builds.) */
2746 bool fNoMorePhysWrites;
2747 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2748 bool afAlignment1[3];
2749
2750 /** Indicates that PGMR3FinalizeMappings has been called and that further
2751 * PGMR3MapIntermediate calls will be rejected. */
2752 bool fFinalizedMappings;
2753 /** If set no conflict checks are required. */
2754 bool fMappingsFixed;
2755 /** If set if restored as fixed but we were unable to re-fixate at the old
2756 * location because of room or address incompatibilities. */
2757 bool fMappingsFixedRestored;
2758 /** If set, then no mappings are put into the shadow page table.
2759 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2760 bool fMappingsDisabled;
2761 /** Size of fixed mapping.
2762 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2763 uint32_t cbMappingFixed;
2764 /** Generation ID for the RAM ranges. This member is incremented everytime
2765 * a RAM range is linked or unlinked. */
2766 uint32_t volatile idRamRangesGen;
2767
2768 /** Base address (GC) of fixed mapping.
2769 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2770 RTGCPTR GCPtrMappingFixed;
2771 /** The address of the previous RAM range mapping. */
2772 RTGCPTR GCPtrPrevRamRangeMapping;
2773
2774 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2775 RTGCPHYS GCPhys4MBPSEMask;
2776 /** Mask containing the invalid bits of a guest physical address.
2777 * @remarks this does not stop at bit 52. */
2778 RTGCPHYS GCPhysInvAddrMask;
2779
2780
2781 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2782 * This is sorted by physical address and contains no overlapping ranges. */
2783 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2784 /** PGM offset based trees - R3 Ptr. */
2785 R3PTRTYPE(PPGMTREES) pTreesR3;
2786 /** Caching the last physical handler we looked up in R3. */
2787 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2788 /** Shadow Page Pool - R3 Ptr. */
2789 R3PTRTYPE(PPGMPOOL) pPoolR3;
2790 /** Linked list of GC mappings - for HC.
2791 * The list is sorted ascending on address. */
2792 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2793 /** Pointer to the list of ROM ranges - for R3.
2794 * This is sorted by physical address and contains no overlapping ranges. */
2795 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2796 /** Pointer to the list of MMIO2 ranges - for R3.
2797 * Registration order. */
2798 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2799 /** Pointer to SHW+GST mode data (function pointers).
2800 * The index into this table is made up from */
2801 R3PTRTYPE(PPGMMODEDATA) paModeData;
2802 /*RTR3PTR R3PtrAlignment0;*/
2803
2804
2805 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2806 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2807 /** PGM offset based trees - R0 Ptr. */
2808 R0PTRTYPE(PPGMTREES) pTreesR0;
2809 /** Caching the last physical handler we looked up in R0. */
2810 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2811 /** Shadow Page Pool - R0 Ptr. */
2812 R0PTRTYPE(PPGMPOOL) pPoolR0;
2813 /** Linked list of GC mappings - for R0.
2814 * The list is sorted ascending on address. */
2815 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2816 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2817 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2818 /*RTR0PTR R0PtrAlignment0;*/
2819
2820
2821 /** RC pointer corresponding to PGM::pRamRangesR3. */
2822 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2823 /** PGM offset based trees - RC Ptr. */
2824 RCPTRTYPE(PPGMTREES) pTreesRC;
2825 /** Caching the last physical handler we looked up in RC. */
2826 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2827 /** Shadow Page Pool - RC Ptr. */
2828 RCPTRTYPE(PPGMPOOL) pPoolRC;
2829 /** Linked list of GC mappings - for RC.
2830 * The list is sorted ascending on address. */
2831 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2832 /** RC pointer corresponding to PGM::pRomRangesR3. */
2833 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2834 /*RTRCPTR RCPtrAlignment0;*/
2835 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2836 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2837 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2838 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2839
2840
2841 /** Pointer to the 5 page CR3 content mapping.
2842 * The first page is always the CR3 (in some form) while the 4 other pages
2843 * are used of the PDs in PAE mode. */
2844 RTGCPTR GCPtrCR3Mapping;
2845
2846 /** @name Intermediate Context
2847 * @{ */
2848 /** Pointer to the intermediate page directory - Normal. */
2849 R3PTRTYPE(PX86PD) pInterPD;
2850 /** Pointer to the intermedate page tables - Normal.
2851 * There are two page tables, one for the identity mapping and one for
2852 * the host context mapping (of the core code). */
2853 R3PTRTYPE(PX86PT) apInterPTs[2];
2854 /** Pointer to the intermedate page tables - PAE. */
2855 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2856 /** Pointer to the intermedate page directory - PAE. */
2857 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2858 /** Pointer to the intermedate page directory - PAE. */
2859 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2860 /** Pointer to the intermedate page-map level 4 - AMD64. */
2861 R3PTRTYPE(PX86PML4) pInterPaePML4;
2862 /** Pointer to the intermedate page directory - AMD64. */
2863 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2864 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2865 RTHCPHYS HCPhysInterPD;
2866 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2867 RTHCPHYS HCPhysInterPaePDPT;
2868 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2869 RTHCPHYS HCPhysInterPaePML4;
2870 /** @} */
2871
2872 /** Base address of the dynamic page mapping area.
2873 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2874 */
2875 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2876 /** The index of the last entry used in the dynamic page mapping area. */
2877 RTUINT iDynPageMapLast;
2878 /** Cache containing the last entries in the dynamic page mapping area.
2879 * The cache size is covering half of the mapping area. */
2880 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2881 /** Keep a lock counter for the full (!) mapping area. */
2882 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2883
2884 /** The address of the ring-0 mapping cache if we're making use of it. */
2885 RTR0PTR pvR0DynMapUsed;
2886#if HC_ARCH_BITS == 32
2887 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2888 uint32_t u32Alignment2;
2889#endif
2890
2891 /** PGM critical section.
2892 * This protects the physical & virtual access handlers, ram ranges,
2893 * and the page flag updating (some of it anyway).
2894 */
2895 PDMCRITSECT CritSect;
2896
2897 /**
2898 * Data associated with managing the ring-3 mappings of the allocation chunks.
2899 */
2900 struct
2901 {
2902 /** The chunk tree, ordered by chunk id. */
2903#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2904 R3PTRTYPE(PAVLU32NODECORE) pTree;
2905#else
2906 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2907#endif
2908#if HC_ARCH_BITS == 32
2909 uint32_t u32Alignment;
2910#endif
2911 /** The chunk mapping TLB. */
2912 PGMCHUNKR3MAPTLB Tlb;
2913 /** The number of mapped chunks. */
2914 uint32_t c;
2915 /** The maximum number of mapped chunks.
2916 * @cfgm PGM/MaxRing3Chunks */
2917 uint32_t cMax;
2918 /** The current time. */
2919 uint32_t iNow;
2920 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2921 uint32_t AgeingCountdown;
2922 } ChunkR3Map;
2923
2924 /**
2925 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2926 */
2927 PGMPAGER3MAPTLB PhysTlbHC;
2928
2929 /** @name The zero page.
2930 * @{ */
2931 /** The host physical address of the zero page. */
2932 RTHCPHYS HCPhysZeroPg;
2933 /** The ring-3 mapping of the zero page. */
2934 RTR3PTR pvZeroPgR3;
2935 /** The ring-0 mapping of the zero page. */
2936 RTR0PTR pvZeroPgR0;
2937 /** The GC mapping of the zero page. */
2938 RTRCPTR pvZeroPgRC;
2939 RTRCPTR RCPtrAlignment3;
2940 /** @}*/
2941
2942 /** @name The Invalid MMIO page.
2943 * This page is filled with 0xfeedface.
2944 * @{ */
2945 /** The host physical address of the invalid MMIO page. */
2946 RTHCPHYS HCPhysMmioPg;
2947 /** The host pysical address of the invalid MMIO page pluss all invalid
2948 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2949 * @remarks Check fLessThan52PhysicalAddressBits before use. */
2950 RTHCPHYS HCPhysInvMmioPg;
2951 /** The ring-3 mapping of the invalid MMIO page. */
2952 RTR3PTR pvMmioPgR3;
2953#if HC_ARCH_BITS == 32
2954 RTR3PTR R3PtrAlignment4;
2955#endif
2956 /** @} */
2957
2958
2959 /** The number of handy pages. */
2960 uint32_t cHandyPages;
2961
2962 /** The number of large handy pages. */
2963 uint32_t cLargeHandyPages;
2964
2965 /**
2966 * Array of handy pages.
2967 *
2968 * This array is used in a two way communication between pgmPhysAllocPage
2969 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2970 * an intermediary.
2971 *
2972 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2973 * (The current size of 32 pages, means 128 KB of handy memory.)
2974 */
2975 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2976
2977 /**
2978 * Array of large handy pages. (currently size 1)
2979 *
2980 * This array is used in a two way communication between pgmPhysAllocLargePage
2981 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2982 * an intermediary.
2983 */
2984 GMMPAGEDESC aLargeHandyPage[1];
2985
2986 /**
2987 * Live save data.
2988 */
2989 struct
2990 {
2991 /** Per type statistics. */
2992 struct
2993 {
2994 /** The number of ready pages. */
2995 uint32_t cReadyPages;
2996 /** The number of dirty pages. */
2997 uint32_t cDirtyPages;
2998 /** The number of ready zero pages. */
2999 uint32_t cZeroPages;
3000 /** The number of write monitored pages. */
3001 uint32_t cMonitoredPages;
3002 } Rom,
3003 Mmio2,
3004 Ram;
3005 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3006 uint32_t cIgnoredPages;
3007 /** Indicates that a live save operation is active. */
3008 bool fActive;
3009 /** Padding. */
3010 bool afReserved[2];
3011 /** The next history index. */
3012 uint8_t iDirtyPagesHistory;
3013 /** History of the total amount of dirty pages. */
3014 uint32_t acDirtyPagesHistory[64];
3015 /** Short term dirty page average. */
3016 uint32_t cDirtyPagesShort;
3017 /** Long term dirty page average. */
3018 uint32_t cDirtyPagesLong;
3019 /** The number of saved pages. This is used to get some kind of estimate of the
3020 * link speed so we can decide when we're done. It is reset after the first
3021 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3022 * zero pages. */
3023 uint64_t cSavedPages;
3024 /** The nanosecond timestamp when cSavedPages was 0. */
3025 uint64_t uSaveStartNS;
3026 /** Pages per second (for statistics). */
3027 uint32_t cPagesPerSecond;
3028 uint32_t cAlignment;
3029 } LiveSave;
3030
3031 /** @name Error injection.
3032 * @{ */
3033 /** Inject handy page allocation errors pretending we're completely out of
3034 * memory. */
3035 bool volatile fErrInjHandyPages;
3036 /** Padding. */
3037 bool afReserved[3];
3038 /** @} */
3039
3040 /** @name Release Statistics
3041 * @{ */
3042 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3043 uint32_t cPrivatePages; /**< The number of private pages. */
3044 uint32_t cSharedPages; /**< The number of shared pages. */
3045 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3046 uint32_t cZeroPages; /**< The number of zero backed pages. */
3047 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3048 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3049 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3050 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3051 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3052 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3053 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3054 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3055/* uint32_t aAlignment4[1]; */
3056
3057 /** The number of times we were forced to change the hypervisor region location. */
3058 STAMCOUNTER cRelocations;
3059
3060 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3061 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3062 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3063 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3064 /** @} */
3065
3066#ifdef VBOX_WITH_STATISTICS
3067 /** @name Statistics on the heap.
3068 * @{ */
3069 R3PTRTYPE(PGMSTATS *) pStatsR3;
3070 R0PTRTYPE(PGMSTATS *) pStatsR0;
3071 RCPTRTYPE(PGMSTATS *) pStatsRC;
3072 RTRCPTR RCPtrAlignment;
3073 /** @} */
3074#endif
3075} PGM;
3076#ifndef IN_TSTVMSTRUCTGC /* HACK */
3077AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3078AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3079AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3080AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
3081AssertCompileMemberAlignment(PGM, CritSect, 8);
3082AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3083AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3084AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3085AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3086AssertCompileMemberAlignment(PGM, cRelocations, 8);
3087#endif /* !IN_TSTVMSTRUCTGC */
3088/** Pointer to the PGM instance data. */
3089typedef PGM *PPGM;
3090
3091
3092
3093typedef struct PGMCPUSTATS
3094{
3095 /* Common */
3096 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3097 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3098
3099 /* R0 only: */
3100 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3101 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3102 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3103 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3104 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3105 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3106 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3107 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3108 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3109 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3110 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3111 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3112 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3113 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3114 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3115 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3116 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3117 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3118 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3119 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3120 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3121 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3122 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3123 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3124 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3125 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3126
3127 /* RZ only: */
3128 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3129 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3130 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3131 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3132 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3133 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3134 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3135 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3136 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3137 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3138 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3139 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3140 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3141 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3142 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3143 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3144 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3145 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3146 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3147 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3148 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3149 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3150 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3151 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3152 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3153 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3154 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3155 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3156 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3157 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3158 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3159 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3160 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3161 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3162 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3163 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3164 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3165 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3166 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3167 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3168 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3169 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3170 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3171 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3172 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3173 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3174 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3175 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3176 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3177
3178 /* HC - R3 and (maybe) R0: */
3179
3180 /* RZ & R3: */
3181 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3182 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3183 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3184 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3185 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3186 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3187 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3188 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3189 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3190 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3191 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3192 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3193 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3194 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3195 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3196 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3197 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3198 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3199 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3200 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3201 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3202 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3203 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3204 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3205 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3206 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3207 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3208 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3209 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3210 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3211 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3212 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3213 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3214 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3215 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3216 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3217 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3218 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3219 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3220 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3221 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3222 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3223 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3224 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3225 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3226 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3227 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3228
3229 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3230 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3231 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3232 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3233 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3234 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3235 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3236 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3237 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3238 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3239 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3240 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3241 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3242 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3243 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3244 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3245 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3246 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3247 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3248 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3249 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3250 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3251 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3252 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3253 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3254 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3255 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3256 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3257 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3258 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3259 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3260 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3261 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3262 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3263 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3264 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3265 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3266 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3267 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3268 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3269 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3270 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3271 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3272 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3273 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3274 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3275 /** @} */
3276} PGMCPUSTATS;
3277
3278
3279/**
3280 * Converts a PGMCPU pointer into a VM pointer.
3281 * @returns Pointer to the VM structure the PGM is part of.
3282 * @param pPGM Pointer to PGMCPU instance data.
3283 */
3284#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3285
3286/**
3287 * Converts a PGMCPU pointer into a PGM pointer.
3288 * @returns Pointer to the VM structure the PGM is part of.
3289 * @param pPGM Pointer to PGMCPU instance data.
3290 */
3291#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3292
3293/**
3294 * PGMCPU Data (part of VMCPU).
3295 */
3296typedef struct PGMCPU
3297{
3298 /** Offset to the VM structure. */
3299 RTINT offVM;
3300 /** Offset to the VMCPU structure. */
3301 RTINT offVCpu;
3302 /** Offset of the PGM structure relative to VMCPU. */
3303 RTINT offPGM;
3304 RTINT uPadding0; /**< structure size alignment. */
3305
3306#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3307 /** Automatically tracked physical memory mapping set.
3308 * Ring-0 and strict raw-mode builds. */
3309 PGMMAPSET AutoSet;
3310#endif
3311
3312 /** A20 gate mask.
3313 * Our current approach to A20 emulation is to let REM do it and don't bother
3314 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3315 * But whould need arrise, we'll subject physical addresses to this mask. */
3316 RTGCPHYS GCPhysA20Mask;
3317 /** A20 gate state - boolean! */
3318 bool fA20Enabled;
3319 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3320 bool fNoExecuteEnabled;
3321 /** Unused bits. */
3322 bool afUnused[2];
3323
3324 /** What needs syncing (PGM_SYNC_*).
3325 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3326 * PGMFlushTLB, and PGMR3Load. */
3327 RTUINT fSyncFlags;
3328
3329 /** The shadow paging mode. */
3330 PGMMODE enmShadowMode;
3331 /** The guest paging mode. */
3332 PGMMODE enmGuestMode;
3333
3334 /** The current physical address representing in the guest CR3 register. */
3335 RTGCPHYS GCPhysCR3;
3336
3337 /** @name 32-bit Guest Paging.
3338 * @{ */
3339 /** The guest's page directory, R3 pointer. */
3340 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3341#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3342 /** The guest's page directory, R0 pointer. */
3343 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3344#endif
3345 /** The guest's page directory, static RC mapping. */
3346 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3347 /** Mask containing the MBZ bits of a big page PDE. */
3348 uint32_t fGst32BitMbzBigPdeMask;
3349 /** Set if the page size extension (PSE) is enabled. */
3350 bool fGst32BitPageSizeExtension;
3351 /** Alignment padding. */
3352 bool afAlignment2[3];
3353 /** @} */
3354
3355 /** @name PAE Guest Paging.
3356 * @{ */
3357 /** The guest's page directory pointer table, static RC mapping. */
3358 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3359 /** The guest's page directory pointer table, R3 pointer. */
3360 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3361#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3362 /** The guest's page directory pointer table, R0 pointer. */
3363 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3364#endif
3365
3366 /** The guest's page directories, R3 pointers.
3367 * These are individual pointers and don't have to be adjecent.
3368 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3369 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3370 /** The guest's page directories, R0 pointers.
3371 * Same restrictions as apGstPaePDsR3. */
3372#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3373 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3374#endif
3375 /** The guest's page directories, static GC mapping.
3376 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3377 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3378 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3379 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3380 RTGCPHYS aGCPhysGstPaePDs[4];
3381 /** The physical addresses of the monitored guest page directories (PAE). */
3382 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3383 /** Mask containing the MBZ PTE bits. */
3384 uint64_t fGstPaeMbzPteMask;
3385 /** Mask containing the MBZ PDE bits. */
3386 uint64_t fGstPaeMbzPdeMask;
3387 /** Mask containing the MBZ big page PDE bits. */
3388 uint64_t fGstPaeMbzBigPdeMask;
3389 /** Mask containing the MBZ PDPE bits. */
3390 uint64_t fGstPaeMbzPdpeMask;
3391 /** @} */
3392
3393 /** @name AMD64 Guest Paging.
3394 * @{ */
3395 /** The guest's page directory pointer table, R3 pointer. */
3396 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3397#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3398 /** The guest's page directory pointer table, R0 pointer. */
3399 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3400#else
3401 RTR0PTR alignment6b; /**< alignment equalizer. */
3402#endif
3403 /** Mask containing the MBZ PTE bits. */
3404 uint64_t fGstAmd64MbzPteMask;
3405 /** Mask containing the MBZ PDE bits. */
3406 uint64_t fGstAmd64MbzPdeMask;
3407 /** Mask containing the MBZ big page PDE bits. */
3408 uint64_t fGstAmd64MbzBigPdeMask;
3409 /** Mask containing the MBZ PDPE bits. */
3410 uint64_t fGstAmd64MbzPdpeMask;
3411 /** Mask containing the MBZ big page PDPE bits. */
3412 uint64_t fGstAmd64MbzBigPdpeMask;
3413 /** Mask containing the MBZ PML4E bits. */
3414 uint64_t fGstAmd64MbzPml4eMask;
3415 /** @} */
3416
3417 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3418 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3419 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3420 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3421 /** Pointer to the page of the current active CR3 - RC Ptr. */
3422 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3423 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3424 uint32_t iShwUser;
3425 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3426 uint32_t iShwUserTable;
3427# if HC_ARCH_BITS == 64
3428 RTRCPTR alignment6; /**< structure size alignment. */
3429# endif
3430 /** @} */
3431
3432 /** @name Function pointers for Shadow paging.
3433 * @{
3434 */
3435 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3436 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3437 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3438 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3439
3440 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3441 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3442
3443 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3444 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3445
3446 /** @} */
3447
3448 /** @name Function pointers for Guest paging.
3449 * @{
3450 */
3451 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3452 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3453 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3454 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3455 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3456 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3457 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3458 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3459#if HC_ARCH_BITS == 64
3460 RTRCPTR alignment3; /**< structure size alignment. */
3461#endif
3462
3463 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3464 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3465 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3466 /** @} */
3467
3468 /** @name Function pointers for Both Shadow and Guest paging.
3469 * @{
3470 */
3471 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3472 /* no pfnR3BthTrap0eHandler */
3473 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3474 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3475 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3476 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3477 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3478 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3479 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3480
3481 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3482 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3483 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3484 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3485 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3486 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3487 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3488 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3489
3490 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3491 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3492 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3493 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3494 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3495 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3496 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3497 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3498#if 0
3499 RTRCPTR alignment2; /**< structure size alignment. */
3500#endif
3501 /** @} */
3502
3503 /** For saving stack space, the disassembler state is allocated here instead of
3504 * on the stack.
3505 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3506 union
3507 {
3508 /** The disassembler scratch space. */
3509 DISCPUSTATE DisState;
3510 /** Padding. */
3511 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3512 };
3513
3514 /** Count the number of pgm pool access handler calls. */
3515 uint64_t cPoolAccessHandler;
3516
3517 /** @name Release Statistics
3518 * @{ */
3519 /** The number of times the guest has switched mode since last reset or statistics reset. */
3520 STAMCOUNTER cGuestModeChanges;
3521 /** @} */
3522
3523#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3524 /** @name Statistics
3525 * @{ */
3526 /** RC: Pointer to the statistics. */
3527 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3528 /** RC: Which statistic this \#PF should be attributed to. */
3529 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3530 /** R0: Pointer to the statistics. */
3531 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3532 /** R0: Which statistic this \#PF should be attributed to. */
3533 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3534 /** R3: Pointer to the statistics. */
3535 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3536 /** Alignment padding. */
3537 RTR3PTR pPaddingR3;
3538 /** @} */
3539#endif /* VBOX_WITH_STATISTICS */
3540} PGMCPU;
3541/** Pointer to the per-cpu PGM data. */
3542typedef PGMCPU *PPGMCPU;
3543
3544
3545/** @name PGM::fSyncFlags Flags
3546 * @{
3547 */
3548/** Updates the virtual access handler state bit in PGMPAGE. */
3549#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3550/** Always sync CR3. */
3551#define PGM_SYNC_ALWAYS RT_BIT(1)
3552/** Check monitoring on next CR3 (re)load and invalidate page.
3553 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3554#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3555/** Check guest mapping in SyncCR3. */
3556#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3557/** Clear the page pool (a light weight flush). */
3558#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3559#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3560/** @} */
3561
3562
3563RT_C_DECLS_BEGIN
3564
3565int pgmLock(PVM pVM);
3566void pgmUnlock(PVM pVM);
3567
3568int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3569int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3570int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3571PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3572int pgmMapResolveConflicts(PVM pVM);
3573DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3574
3575void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3576bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3577void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3578int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3579DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3580#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3581void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3582#else
3583# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3584#endif
3585DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3586int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3587
3588int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3589int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3590int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3591int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3592int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3593void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3594int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3595int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3596int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3597int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3598int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3599int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3600int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3601VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3602VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3603int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3604
3605#ifdef IN_RING3
3606void pgmR3PhysRelinkRamRanges(PVM pVM);
3607int pgmR3PhysRamPreAllocate(PVM pVM);
3608int pgmR3PhysRamReset(PVM pVM);
3609int pgmR3PhysRomReset(PVM pVM);
3610int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3611int pgmR3PhysRamTerm(PVM pVM);
3612
3613int pgmR3PoolInit(PVM pVM);
3614void pgmR3PoolRelocate(PVM pVM);
3615void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3616void pgmR3PoolReset(PVM pVM);
3617void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3618DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3619
3620#endif /* IN_RING3 */
3621#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3622int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3623#endif
3624int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3625
3626DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3627{
3628 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3629}
3630
3631void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3632void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3633int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3634void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3635PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3636int pgmPoolSyncCR3(PVMCPU pVCpu);
3637bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3638int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3639void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3640void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3641DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3642{
3643 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3644}
3645
3646uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3647void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3648void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3649int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3650void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3651
3652void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3653void pgmPoolResetDirtyPages(PVM pVM);
3654
3655int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3656int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3657
3658void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3659void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3660int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3661int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3662
3663int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3664
3665int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3666int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3667int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3668int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3669
3670# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3671DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3672DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3673# endif
3674
3675RT_C_DECLS_END
3676
3677/** @} */
3678
3679#endif
3680
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