VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31370

Last change on this file since 31370 was 31206, checked in by vboxsync, 15 years ago

PGM: Always make sure to have the original bits around for verification in strict builds.
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1/* $Id: PGMInternal.h 31206 2010-07-29 13:05:31Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark In RC this uses PGMDynMapHCPage(), so it will consume of the small
237 * page window employeed by that function. Be careful.
238 * @remark There is no need to assert on the result.
239 */
240#ifdef IN_RC
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
243#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 pgmR0DynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv))
246#else
247# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
248 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
249#endif
250
251/** @def PGM_GCPHYS_2_PTR_V2
252 * Maps a GC physical page address to a virtual address.
253 *
254 * @returns VBox status code.
255 * @param pVM The VM handle.
256 * @param pVCpu The current CPU.
257 * @param GCPhys The GC physical address to map to a virtual one.
258 * @param ppv Where to store the virtual address. No need to cast this.
259 *
260 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
261 * small page window employeed by that function. Be careful.
262 * @remark There is no need to assert on the result.
263 */
264#ifdef IN_RC
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
267#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
268# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
269 pgmR0DynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv))
270#else
271# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
272 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
273#endif
274
275/** @def PGM_GCPHYS_2_PTR
276 * Maps a GC physical page address to a virtual address.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM handle.
280 * @param GCPhys The GC physical address to map to a virtual one.
281 * @param ppv Where to store the virtual address. No need to cast this.
282 *
283 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
284 * small page window employeed by that function. Be careful.
285 * @remark There is no need to assert on the result.
286 */
287#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
288
289/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
290 * Maps a GC physical page address to a virtual address.
291 *
292 * @returns VBox status code.
293 * @param pVCpu The current CPU.
294 * @param GCPhys The GC physical address to map to a virtual one.
295 * @param ppv Where to store the virtual address. No need to cast this.
296 *
297 * @remark In RC this uses PGMGCDynMapGCPage(), so it will consume of the
298 * small page window employeed by that function. Be careful.
299 * @remark There is no need to assert on the result.
300 */
301#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
302
303/** @def PGM_GCPHYS_2_PTR_EX
304 * Maps a unaligned GC physical page address to a virtual address.
305 *
306 * @returns VBox status code.
307 * @param pVM The VM handle.
308 * @param GCPhys The GC physical address to map to a virtual one.
309 * @param ppv Where to store the virtual address. No need to cast this.
310 *
311 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
312 * small page window employeed by that function. Be careful.
313 * @remark There is no need to assert on the result.
314 */
315#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
316# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
317 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
318#else
319# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
320 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
321#endif
322
323/** @def PGM_INVL_PG
324 * Invalidates a page.
325 *
326 * @param pVCpu The VMCPU handle.
327 * @param GCVirt The virtual address of the page to invalidate.
328 */
329#ifdef IN_RC
330# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
331#elif defined(IN_RING0)
332# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
333#else
334# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
335#endif
336
337/** @def PGM_INVL_PG_ALL_VCPU
338 * Invalidates a page on all VCPUs
339 *
340 * @param pVM The VM handle.
341 * @param GCVirt The virtual address of the page to invalidate.
342 */
343#ifdef IN_RC
344# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
345#elif defined(IN_RING0)
346# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
347#else
348# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
349#endif
350
351/** @def PGM_INVL_BIG_PG
352 * Invalidates a 4MB page directory entry.
353 *
354 * @param pVCpu The VMCPU handle.
355 * @param GCVirt The virtual address within the page directory to invalidate.
356 */
357#ifdef IN_RC
358# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
359#elif defined(IN_RING0)
360# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
361#else
362# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
363#endif
364
365/** @def PGM_INVL_VCPU_TLBS()
366 * Invalidates the TLBs of the specified VCPU
367 *
368 * @param pVCpu The VMCPU handle.
369 */
370#ifdef IN_RC
371# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
372#elif defined(IN_RING0)
373# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
374#else
375# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
376#endif
377
378/** @def PGM_INVL_ALL_VCPU_TLBS()
379 * Invalidates the TLBs of all VCPUs
380 *
381 * @param pVM The VM handle.
382 */
383#ifdef IN_RC
384# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
385#elif defined(IN_RING0)
386# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
387#else
388# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
389#endif
390
391/** Size of the GCPtrConflict array in PGMMAPPING.
392 * @remarks Must be a power of two. */
393#define PGMMAPPING_CONFLICT_MAX 8
394
395/**
396 * Structure for tracking GC Mappings.
397 *
398 * This structure is used by linked list in both GC and HC.
399 */
400typedef struct PGMMAPPING
401{
402 /** Pointer to next entry. */
403 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
404 /** Pointer to next entry. */
405 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
406 /** Pointer to next entry. */
407 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
408 /** Indicate whether this entry is finalized. */
409 bool fFinalized;
410 /** Start Virtual address. */
411 RTGCPTR GCPtr;
412 /** Last Virtual address (inclusive). */
413 RTGCPTR GCPtrLast;
414 /** Range size (bytes). */
415 RTGCPTR cb;
416 /** Pointer to relocation callback function. */
417 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
418 /** User argument to the callback. */
419 R3PTRTYPE(void *) pvUser;
420 /** Mapping description / name. For easing debugging. */
421 R3PTRTYPE(const char *) pszDesc;
422 /** Last 8 addresses that caused conflicts. */
423 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
424 /** Number of conflicts for this hypervisor mapping. */
425 uint32_t cConflicts;
426 /** Number of page tables. */
427 uint32_t cPTs;
428
429 /** Array of page table mapping data. Each entry
430 * describes one page table. The array can be longer
431 * than the declared length.
432 */
433 struct
434 {
435 /** The HC physical address of the page table. */
436 RTHCPHYS HCPhysPT;
437 /** The HC physical address of the first PAE page table. */
438 RTHCPHYS HCPhysPaePT0;
439 /** The HC physical address of the second PAE page table. */
440 RTHCPHYS HCPhysPaePT1;
441 /** The HC virtual address of the 32-bit page table. */
442 R3PTRTYPE(PX86PT) pPTR3;
443 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
444 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
445 /** The RC virtual address of the 32-bit page table. */
446 RCPTRTYPE(PX86PT) pPTRC;
447 /** The RC virtual address of the two PAE page table. */
448 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
449 /** The R0 virtual address of the 32-bit page table. */
450 R0PTRTYPE(PX86PT) pPTR0;
451 /** The R0 virtual address of the two PAE page table. */
452 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
453 } aPTs[1];
454} PGMMAPPING;
455/** Pointer to structure for tracking GC Mappings. */
456typedef struct PGMMAPPING *PPGMMAPPING;
457
458
459/**
460 * Physical page access handler structure.
461 *
462 * This is used to keep track of physical address ranges
463 * which are being monitored in some kind of way.
464 */
465typedef struct PGMPHYSHANDLER
466{
467 AVLROGCPHYSNODECORE Core;
468 /** Access type. */
469 PGMPHYSHANDLERTYPE enmType;
470 /** Number of pages to update. */
471 uint32_t cPages;
472 /** Pointer to R3 callback function. */
473 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
474 /** User argument for R3 handlers. */
475 R3PTRTYPE(void *) pvUserR3;
476 /** Pointer to R0 callback function. */
477 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
478 /** User argument for R0 handlers. */
479 R0PTRTYPE(void *) pvUserR0;
480 /** Pointer to RC callback function. */
481 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
482 /** User argument for RC handlers. */
483 RCPTRTYPE(void *) pvUserRC;
484 /** Description / Name. For easing debugging. */
485 R3PTRTYPE(const char *) pszDesc;
486#ifdef VBOX_WITH_STATISTICS
487 /** Profiling of this handler. */
488 STAMPROFILE Stat;
489#endif
490} PGMPHYSHANDLER;
491/** Pointer to a physical page access handler structure. */
492typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
493
494
495/**
496 * Cache node for the physical addresses covered by a virtual handler.
497 */
498typedef struct PGMPHYS2VIRTHANDLER
499{
500 /** Core node for the tree based on physical ranges. */
501 AVLROGCPHYSNODECORE Core;
502 /** Offset from this struct to the PGMVIRTHANDLER structure. */
503 int32_t offVirtHandler;
504 /** Offset of the next alias relative to this one.
505 * Bit 0 is used for indicating whether we're in the tree.
506 * Bit 1 is used for indicating that we're the head node.
507 */
508 int32_t offNextAlias;
509} PGMPHYS2VIRTHANDLER;
510/** Pointer to a phys to virtual handler structure. */
511typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
512
513/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
514 * node is in the tree. */
515#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
516/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
517 * node is in the head of an alias chain.
518 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
519#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
520/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
521#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
522
523
524/**
525 * Virtual page access handler structure.
526 *
527 * This is used to keep track of virtual address ranges
528 * which are being monitored in some kind of way.
529 */
530typedef struct PGMVIRTHANDLER
531{
532 /** Core node for the tree based on virtual ranges. */
533 AVLROGCPTRNODECORE Core;
534 /** Size of the range (in bytes). */
535 RTGCPTR cb;
536 /** Number of cache pages. */
537 uint32_t cPages;
538 /** Access type. */
539 PGMVIRTHANDLERTYPE enmType;
540 /** Pointer to the RC callback function. */
541 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
542#if HC_ARCH_BITS == 64
543 RTRCPTR padding;
544#endif
545 /** Pointer to the R3 callback function for invalidation. */
546 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
547 /** Pointer to the R3 callback function. */
548 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
549 /** Description / Name. For easing debugging. */
550 R3PTRTYPE(const char *) pszDesc;
551#ifdef VBOX_WITH_STATISTICS
552 /** Profiling of this handler. */
553 STAMPROFILE Stat;
554#endif
555 /** Array of cached physical addresses for the monitored ranged. */
556 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
557} PGMVIRTHANDLER;
558/** Pointer to a virtual page access handler structure. */
559typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
560
561
562/**
563 * Page type.
564 *
565 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
566 * @remarks This is used in the saved state, so changes to it requires bumping
567 * the saved state version.
568 * @todo So, convert to \#defines!
569 */
570typedef enum PGMPAGETYPE
571{
572 /** The usual invalid zero entry. */
573 PGMPAGETYPE_INVALID = 0,
574 /** RAM page. (RWX) */
575 PGMPAGETYPE_RAM,
576 /** MMIO2 page. (RWX) */
577 PGMPAGETYPE_MMIO2,
578 /** MMIO2 page aliased over an MMIO page. (RWX)
579 * See PGMHandlerPhysicalPageAlias(). */
580 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
581 /** Shadowed ROM. (RWX) */
582 PGMPAGETYPE_ROM_SHADOW,
583 /** ROM page. (R-X) */
584 PGMPAGETYPE_ROM,
585 /** MMIO page. (---) */
586 PGMPAGETYPE_MMIO,
587 /** End of valid entries. */
588 PGMPAGETYPE_END
589} PGMPAGETYPE;
590AssertCompile(PGMPAGETYPE_END <= 7);
591
592/** @name Page type predicates.
593 * @{ */
594#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
595#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
596#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
597#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
598#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
599/** @} */
600
601
602/**
603 * A Physical Guest Page tracking structure.
604 *
605 * The format of this structure is complicated because we have to fit a lot
606 * of information into as few bits as possible. The format is also subject
607 * to change (there is one comming up soon). Which means that for we'll be
608 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
609 * accesses to the structure.
610 */
611typedef struct PGMPAGE
612{
613 /** The physical address and the Page ID. */
614 RTHCPHYS HCPhysAndPageID;
615 /** Combination of:
616 * - [0-7]: u2HandlerPhysStateY - the physical handler state
617 * (PGM_PAGE_HNDL_PHYS_STATE_*).
618 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
619 * (PGM_PAGE_HNDL_VIRT_STATE_*).
620 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
621 * - [15]: fWrittenToY - flag indicating that a write monitored page was
622 * written to when set.
623 * - [10-13]: 4 unused bits.
624 * @remarks Warning! All accesses to the bits are hardcoded.
625 *
626 * @todo Change this to a union with both bitfields, u8 and u accessors.
627 * That'll help deal with some of the hardcoded accesses.
628 *
629 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
630 * will make it possible to turn some of the 16-bit accesses into
631 * 32-bit ones, which may be efficient (stalls).
632 */
633 RTUINT16U u16MiscY;
634 /** The page state.
635 * Only 3 bits are really needed for this. */
636 uint16_t uStateY : 3;
637 /** The page type (PGMPAGETYPE).
638 * Only 3 bits are really needed for this. */
639 uint16_t uTypeY : 3;
640 /** PTE index for usage tracking (page pool). */
641 uint16_t uPteIdx : 10;
642 /** Usage tracking (page pool). */
643 uint16_t u16TrackingY;
644 /** The number of read locks on this page. */
645 uint8_t cReadLocksY;
646 /** The number of write locks on this page. */
647 uint8_t cWriteLocksY;
648} PGMPAGE;
649AssertCompileSize(PGMPAGE, 16);
650/** Pointer to a physical guest page. */
651typedef PGMPAGE *PPGMPAGE;
652/** Pointer to a const physical guest page. */
653typedef const PGMPAGE *PCPGMPAGE;
654/** Pointer to a physical guest page pointer. */
655typedef PPGMPAGE *PPPGMPAGE;
656
657
658/**
659 * Clears the page structure.
660 * @param pPage Pointer to the physical guest page tracking structure.
661 */
662#define PGM_PAGE_CLEAR(pPage) \
663 do { \
664 (pPage)->HCPhysAndPageID = 0; \
665 (pPage)->uStateY = 0; \
666 (pPage)->uTypeY = 0; \
667 (pPage)->uPteIdx = 0; \
668 (pPage)->u16MiscY.u = 0; \
669 (pPage)->u16TrackingY = 0; \
670 (pPage)->cReadLocksY = 0; \
671 (pPage)->cWriteLocksY = 0; \
672 } while (0)
673
674/**
675 * Initializes the page structure.
676 * @param pPage Pointer to the physical guest page tracking structure.
677 */
678#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
679 do { \
680 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
681 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
682 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
683 (pPage)->uStateY = (_uState); \
684 (pPage)->uTypeY = (_uType); \
685 (pPage)->uPteIdx = 0; \
686 (pPage)->u16MiscY.u = 0; \
687 (pPage)->u16TrackingY = 0; \
688 (pPage)->cReadLocksY = 0; \
689 (pPage)->cWriteLocksY = 0; \
690 } while (0)
691
692/**
693 * Initializes the page structure of a ZERO page.
694 * @param pPage Pointer to the physical guest page tracking structure.
695 * @param pVM The VM handle (for getting the zero page address).
696 * @param uType The page type (PGMPAGETYPE).
697 */
698#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
699 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
700
701
702/** @name The Page state, PGMPAGE::uStateY.
703 * @{ */
704/** The zero page.
705 * This is a per-VM page that's never ever mapped writable. */
706#define PGM_PAGE_STATE_ZERO 0
707/** A allocated page.
708 * This is a per-VM page allocated from the page pool (or wherever
709 * we get MMIO2 pages from if the type is MMIO2).
710 */
711#define PGM_PAGE_STATE_ALLOCATED 1
712/** A allocated page that's being monitored for writes.
713 * The shadow page table mappings are read-only. When a write occurs, the
714 * fWrittenTo member is set, the page remapped as read-write and the state
715 * moved back to allocated. */
716#define PGM_PAGE_STATE_WRITE_MONITORED 2
717/** The page is shared, aka. copy-on-write.
718 * This is a page that's shared with other VMs. */
719#define PGM_PAGE_STATE_SHARED 3
720/** The page is ballooned, so no longer available for this VM. */
721#define PGM_PAGE_STATE_BALLOONED 4
722/** @} */
723
724
725/**
726 * Gets the page state.
727 * @returns page state (PGM_PAGE_STATE_*).
728 * @param pPage Pointer to the physical guest page tracking structure.
729 */
730#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
731
732/**
733 * Sets the page state.
734 * @param pPage Pointer to the physical guest page tracking structure.
735 * @param _uState The new page state.
736 */
737#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
738
739
740/**
741 * Gets the host physical address of the guest page.
742 * @returns host physical address (RTHCPHYS).
743 * @param pPage Pointer to the physical guest page tracking structure.
744 */
745#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
746
747/**
748 * Sets the host physical address of the guest page.
749 * @param pPage Pointer to the physical guest page tracking structure.
750 * @param _HCPhys The new host physical address.
751 */
752#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
753 do { \
754 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
755 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
756 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
757 | (SetHCPhysTmp << (28-12)); \
758 } while (0)
759
760/**
761 * Get the Page ID.
762 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
763 * @param pPage Pointer to the physical guest page tracking structure.
764 */
765#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
766
767/**
768 * Sets the Page ID.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 */
771#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
772 do { \
773 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
774 | ((_idPage) & UINT32_C(0x0fffffff)); \
775 } while (0)
776
777/**
778 * Get the Chunk ID.
779 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
780 * @param pPage Pointer to the physical guest page tracking structure.
781 */
782#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
783
784/**
785 * Get the index of the page within the allocation chunk.
786 * @returns The page index.
787 * @param pPage Pointer to the physical guest page tracking structure.
788 */
789#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
790
791/**
792 * Gets the page type.
793 * @returns The page type.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
797
798/**
799 * Sets the page type.
800 * @param pPage Pointer to the physical guest page tracking structure.
801 * @param _enmType The new page type (PGMPAGETYPE).
802 */
803#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
804
805/**
806 * Gets the page table index
807 * @returns The page table index.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
811
812/**
813 * Sets the page table index
814 * @param pPage Pointer to the physical guest page tracking structure.
815 * @param iPte New page table index.
816 */
817#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
818
819/**
820 * Checks if the page is marked for MMIO.
821 * @returns true/false.
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
825
826/**
827 * Checks if the page is backed by the ZERO page.
828 * @returns true/false.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
832
833/**
834 * Checks if the page is backed by a SHARED page.
835 * @returns true/false.
836 * @param pPage Pointer to the physical guest page tracking structure.
837 */
838#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
839
840/**
841 * Checks if the page is ballooned.
842 * @returns true/false.
843 * @param pPage Pointer to the physical guest page tracking structure.
844 */
845#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
846
847/**
848 * Marks the page as written to (for GMM change monitoring).
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
852
853/**
854 * Clears the written-to indicator.
855 * @param pPage Pointer to the physical guest page tracking structure.
856 */
857#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
858
859/**
860 * Checks if the page was marked as written-to.
861 * @returns true/false.
862 * @param pPage Pointer to the physical guest page tracking structure.
863 */
864#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
865
866/** @name PT usage values (PGMPAGE::u2PDEType).
867 *
868 * @{ */
869/** Either as a PT or PDE. */
870#define PGM_PAGE_PDE_TYPE_DONTCARE 0
871/** Must use a page table to map the range. */
872#define PGM_PAGE_PDE_TYPE_PT 1
873/** Can use a page directory entry to map the continous range. */
874#define PGM_PAGE_PDE_TYPE_PDE 2
875/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
876#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
877/** @} */
878
879/**
880 * Set the PDE type of the page
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param uType PGM_PAGE_PDE_TYPE_*
883 */
884#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
885 do { \
886 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
887 | (((uType) & UINT8_C(0x03)) << 5); \
888 } while (0)
889
890/**
891 * Checks if the page was marked being part of a large page
892 * @returns true/false.
893 * @param pPage Pointer to the physical guest page tracking structure.
894 */
895#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
896
897/** Enabled optimized access handler tests.
898 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
899 * layout. When enabled, the compiler should normally generate more compact
900 * code.
901 */
902#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
903
904/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
905 *
906 * @remarks The values are assigned in order of priority, so we can calculate
907 * the correct state for a page with different handlers installed.
908 * @{ */
909/** No handler installed. */
910#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
911/** Monitoring is temporarily disabled. */
912#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
913/** Write access is monitored. */
914#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
915/** All access is monitored. */
916#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
917/** @} */
918
919/**
920 * Gets the physical access handler state of a page.
921 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
922 * @param pPage Pointer to the physical guest page tracking structure.
923 */
924#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
925 ( (pPage)->u16MiscY.au8[0] )
926
927/**
928 * Sets the physical access handler state of a page.
929 * @param pPage Pointer to the physical guest page tracking structure.
930 * @param _uState The new state value.
931 */
932#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
933 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
934
935/**
936 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
937 * @returns true/false
938 * @param pPage Pointer to the physical guest page tracking structure.
939 */
940#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
941 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
942
943/**
944 * Checks if the page has any active physical access handlers.
945 * @returns true/false
946 * @param pPage Pointer to the physical guest page tracking structure.
947 */
948#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
949 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
950
951
952/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
953 *
954 * @remarks The values are assigned in order of priority, so we can calculate
955 * the correct state for a page with different handlers installed.
956 * @{ */
957/** No handler installed. */
958#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
959/* 1 is reserved so the lineup is identical with the physical ones. */
960/** Write access is monitored. */
961#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
962/** All access is monitored. */
963#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
964/** @} */
965
966/**
967 * Gets the virtual access handler state of a page.
968 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
972
973/**
974 * Sets the virtual access handler state of a page.
975 * @param pPage Pointer to the physical guest page tracking structure.
976 * @param _uState The new state value.
977 */
978#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
979 do { \
980 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
981 | ((_uState) & UINT8_C(0x03)); \
982 } while (0)
983
984/**
985 * Checks if the page has any virtual access handlers.
986 * @returns true/false
987 * @param pPage Pointer to the physical guest page tracking structure.
988 */
989#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
990 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
991
992/**
993 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
994 * virtual handlers.
995 * @returns true/false
996 * @param pPage Pointer to the physical guest page tracking structure.
997 */
998#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
999 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1000
1001
1002/**
1003 * Checks if the page has any access handlers, including temporarily disabled ones.
1004 * @returns true/false
1005 * @param pPage Pointer to the physical guest page tracking structure.
1006 */
1007#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1008# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1009 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1010#else
1011# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1012 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1013 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1014#endif
1015
1016/**
1017 * Checks if the page has any active access handlers.
1018 * @returns true/false
1019 * @param pPage Pointer to the physical guest page tracking structure.
1020 */
1021#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1022# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1023 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1024#else
1025# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1026 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1027 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1028#endif
1029
1030/**
1031 * Checks if the page has any active access handlers catching all accesses.
1032 * @returns true/false
1033 * @param pPage Pointer to the physical guest page tracking structure.
1034 */
1035#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1036# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1037 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1038 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1039#else
1040# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1041 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1042 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1043#endif
1044
1045
1046/** @def PGM_PAGE_GET_TRACKING
1047 * Gets the packed shadow page pool tracking data associated with a guest page.
1048 * @returns uint16_t containing the data.
1049 * @param pPage Pointer to the physical guest page tracking structure.
1050 */
1051#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1052
1053/** @def PGM_PAGE_SET_TRACKING
1054 * Sets the packed shadow page pool tracking data associated with a guest page.
1055 * @param pPage Pointer to the physical guest page tracking structure.
1056 * @param u16TrackingData The tracking data to store.
1057 */
1058#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1059 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1060
1061/** @def PGM_PAGE_GET_TD_CREFS
1062 * Gets the @a cRefs tracking data member.
1063 * @returns cRefs.
1064 * @param pPage Pointer to the physical guest page tracking structure.
1065 */
1066#define PGM_PAGE_GET_TD_CREFS(pPage) \
1067 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1068
1069/** @def PGM_PAGE_GET_TD_IDX
1070 * Gets the @a idx tracking data member.
1071 * @returns idx.
1072 * @param pPage Pointer to the physical guest page tracking structure.
1073 */
1074#define PGM_PAGE_GET_TD_IDX(pPage) \
1075 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1076
1077
1078/** Max number of locks on a page. */
1079#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1080
1081/** Get the read lock count.
1082 * @returns count.
1083 * @param pPage Pointer to the physical guest page tracking structure.
1084 */
1085#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1086
1087/** Get the write lock count.
1088 * @returns count.
1089 * @param pPage Pointer to the physical guest page tracking structure.
1090 */
1091#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1092
1093/** Decrement the read lock counter.
1094 * @param pPage Pointer to the physical guest page tracking structure.
1095 */
1096#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1097
1098/** Decrement the write lock counter.
1099 * @param pPage Pointer to the physical guest page tracking structure.
1100 */
1101#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1102
1103/** Increment the read lock counter.
1104 * @param pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1107
1108/** Increment the write lock counter.
1109 * @param pPage Pointer to the physical guest page tracking structure.
1110 */
1111#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1112
1113
1114#if 0
1115/** Enables sanity checking of write monitoring using CRC-32. */
1116# define PGMLIVESAVERAMPAGE_WITH_CRC32
1117#endif
1118
1119/**
1120 * Per page live save tracking data.
1121 */
1122typedef struct PGMLIVESAVERAMPAGE
1123{
1124 /** Number of times it has been dirtied. */
1125 uint32_t cDirtied : 24;
1126 /** Whether it is currently dirty. */
1127 uint32_t fDirty : 1;
1128 /** Ignore the page.
1129 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1130 * deal with these after pausing the VM and DevPCI have said it bit about
1131 * remappings. */
1132 uint32_t fIgnore : 1;
1133 /** Was a ZERO page last time around. */
1134 uint32_t fZero : 1;
1135 /** Was a SHARED page last time around. */
1136 uint32_t fShared : 1;
1137 /** Whether the page is/was write monitored in a previous pass. */
1138 uint32_t fWriteMonitored : 1;
1139 /** Whether the page is/was write monitored earlier in this pass. */
1140 uint32_t fWriteMonitoredJustNow : 1;
1141 /** Bits reserved for future use. */
1142 uint32_t u2Reserved : 2;
1143#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1144 /** CRC-32 for the page. This is for internal consistency checks. */
1145 uint32_t u32Crc;
1146#endif
1147} PGMLIVESAVERAMPAGE;
1148#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1149AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1150#else
1151AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1152#endif
1153/** Pointer to the per page live save tracking data. */
1154typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1155
1156/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1157#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1158
1159
1160/**
1161 * Ram range for GC Phys to HC Phys conversion.
1162 *
1163 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1164 * conversions too, but we'll let MM handle that for now.
1165 *
1166 * This structure is used by linked lists in both GC and HC.
1167 */
1168typedef struct PGMRAMRANGE
1169{
1170 /** Start of the range. Page aligned. */
1171 RTGCPHYS GCPhys;
1172 /** Size of the range. (Page aligned of course). */
1173 RTGCPHYS cb;
1174 /** Pointer to the next RAM range - for R3. */
1175 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1176 /** Pointer to the next RAM range - for R0. */
1177 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1178 /** Pointer to the next RAM range - for RC. */
1179 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1180 /** PGM_RAM_RANGE_FLAGS_* flags. */
1181 uint32_t fFlags;
1182 /** Last address in the range (inclusive). Page aligned (-1). */
1183 RTGCPHYS GCPhysLast;
1184 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1185 R3PTRTYPE(void *) pvR3;
1186 /** Live save per page tracking data. */
1187 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1188 /** The range description. */
1189 R3PTRTYPE(const char *) pszDesc;
1190 /** Pointer to self - R0 pointer. */
1191 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1192 /** Pointer to self - RC pointer. */
1193 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1194 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1195 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1196 /** Array of physical guest page tracking structures. */
1197 PGMPAGE aPages[1];
1198} PGMRAMRANGE;
1199/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1200typedef PGMRAMRANGE *PPGMRAMRANGE;
1201
1202/** @name PGMRAMRANGE::fFlags
1203 * @{ */
1204/** The RAM range is floating around as an independent guest mapping. */
1205#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1206/** Ad hoc RAM range for an ROM mapping. */
1207#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1208/** Ad hoc RAM range for an MMIO mapping. */
1209#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1210/** Ad hoc RAM range for an MMIO2 mapping. */
1211#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1212/** @} */
1213
1214/** Tests if a RAM range is an ad hoc one or not.
1215 * @returns true/false.
1216 * @param pRam The RAM range.
1217 */
1218#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1219 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1220
1221
1222/**
1223 * Per page tracking structure for ROM image.
1224 *
1225 * A ROM image may have a shadow page, in which case we may have two pages
1226 * backing it. This structure contains the PGMPAGE for both while
1227 * PGMRAMRANGE have a copy of the active one. It is important that these
1228 * aren't out of sync in any regard other than page pool tracking data.
1229 */
1230typedef struct PGMROMPAGE
1231{
1232 /** The page structure for the virgin ROM page. */
1233 PGMPAGE Virgin;
1234 /** The page structure for the shadow RAM page. */
1235 PGMPAGE Shadow;
1236 /** The current protection setting. */
1237 PGMROMPROT enmProt;
1238 /** Live save status information. Makes use of unused alignment space. */
1239 struct
1240 {
1241 /** The previous protection value. */
1242 uint8_t u8Prot;
1243 /** Written to flag set by the handler. */
1244 bool fWrittenTo;
1245 /** Whether the shadow page is dirty or not. */
1246 bool fDirty;
1247 /** Whether it was dirtied in the recently. */
1248 bool fDirtiedRecently;
1249 } LiveSave;
1250} PGMROMPAGE;
1251AssertCompileSizeAlignment(PGMROMPAGE, 8);
1252/** Pointer to a ROM page tracking structure. */
1253typedef PGMROMPAGE *PPGMROMPAGE;
1254
1255
1256/**
1257 * A registered ROM image.
1258 *
1259 * This is needed to keep track of ROM image since they generally intrude
1260 * into a PGMRAMRANGE. It also keeps track of additional info like the
1261 * two page sets (read-only virgin and read-write shadow), the current
1262 * state of each page.
1263 *
1264 * Because access handlers cannot easily be executed in a different
1265 * context, the ROM ranges needs to be accessible and in all contexts.
1266 */
1267typedef struct PGMROMRANGE
1268{
1269 /** Pointer to the next range - R3. */
1270 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1271 /** Pointer to the next range - R0. */
1272 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1273 /** Pointer to the next range - RC. */
1274 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1275 /** Pointer alignment */
1276 RTRCPTR RCPtrAlignment;
1277 /** Address of the range. */
1278 RTGCPHYS GCPhys;
1279 /** Address of the last byte in the range. */
1280 RTGCPHYS GCPhysLast;
1281 /** Size of the range. */
1282 RTGCPHYS cb;
1283 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1284 uint32_t fFlags;
1285 /** The saved state range ID. */
1286 uint8_t idSavedState;
1287 /** Alignment padding. */
1288 uint8_t au8Alignment[3];
1289 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1290 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1291 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1292 * This is used for strictness checks. */
1293 R3PTRTYPE(const void *) pvOriginal;
1294 /** The ROM description. */
1295 R3PTRTYPE(const char *) pszDesc;
1296 /** The per page tracking structures. */
1297 PGMROMPAGE aPages[1];
1298} PGMROMRANGE;
1299/** Pointer to a ROM range. */
1300typedef PGMROMRANGE *PPGMROMRANGE;
1301
1302
1303/**
1304 * Live save per page data for an MMIO2 page.
1305 *
1306 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1307 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1308 * CRC-32 for detecting changes as well as special handling of zero pages. This
1309 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1310 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1311 * because of speed (2.5x and 6x slower).)
1312 *
1313 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1314 * save but normally is disabled. Since we can write monitore guest
1315 * accesses on our own, we only need this for host accesses. Shouldn't be
1316 * too difficult for DevVGA, VMMDev might be doable, the planned
1317 * networking fun will be fun since it involves ring-0.
1318 */
1319typedef struct PGMLIVESAVEMMIO2PAGE
1320{
1321 /** Set if the page is considered dirty. */
1322 bool fDirty;
1323 /** The number of scans this page has remained unchanged for.
1324 * Only updated for dirty pages. */
1325 uint8_t cUnchangedScans;
1326 /** Whether this page was zero at the last scan. */
1327 bool fZero;
1328 /** Alignment padding. */
1329 bool fReserved;
1330 /** CRC-32 for the first half of the page.
1331 * This is used together with u32CrcH2 to quickly detect changes in the page
1332 * during the non-final passes. */
1333 uint32_t u32CrcH1;
1334 /** CRC-32 for the second half of the page. */
1335 uint32_t u32CrcH2;
1336 /** SHA-1 for the saved page.
1337 * This is used in the final pass to skip pages without changes. */
1338 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1339} PGMLIVESAVEMMIO2PAGE;
1340/** Pointer to a live save status data for an MMIO2 page. */
1341typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1342
1343/**
1344 * A registered MMIO2 (= Device RAM) range.
1345 *
1346 * There are a few reason why we need to keep track of these
1347 * registrations. One of them is the deregistration & cleanup stuff,
1348 * while another is that the PGMRAMRANGE associated with such a region may
1349 * have to be removed from the ram range list.
1350 *
1351 * Overlapping with a RAM range has to be 100% or none at all. The pages
1352 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1353 * will be raised if a partial overlap or an overlap of ROM pages is
1354 * encountered. On an overlap we will free all the existing RAM pages and
1355 * put in the ram range pages instead.
1356 */
1357typedef struct PGMMMIO2RANGE
1358{
1359 /** The owner of the range. (a device) */
1360 PPDMDEVINSR3 pDevInsR3;
1361 /** Pointer to the ring-3 mapping of the allocation. */
1362 RTR3PTR pvR3;
1363 /** Pointer to the next range - R3. */
1364 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1365 /** Whether it's mapped or not. */
1366 bool fMapped;
1367 /** Whether it's overlapping or not. */
1368 bool fOverlapping;
1369 /** The PCI region number.
1370 * @remarks This ASSUMES that nobody will ever really need to have multiple
1371 * PCI devices with matching MMIO region numbers on a single device. */
1372 uint8_t iRegion;
1373 /** The saved state range ID. */
1374 uint8_t idSavedState;
1375 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1376 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1377 /** Live save per page tracking data. */
1378 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1379 /** The associated RAM range. */
1380 PGMRAMRANGE RamRange;
1381} PGMMMIO2RANGE;
1382/** Pointer to a MMIO2 range. */
1383typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1384
1385
1386
1387
1388/**
1389 * PGMPhysRead/Write cache entry
1390 */
1391typedef struct PGMPHYSCACHEENTRY
1392{
1393 /** R3 pointer to physical page. */
1394 R3PTRTYPE(uint8_t *) pbR3;
1395 /** GC Physical address for cache entry */
1396 RTGCPHYS GCPhys;
1397#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1398 RTGCPHYS u32Padding0; /**< alignment padding. */
1399#endif
1400} PGMPHYSCACHEENTRY;
1401
1402/**
1403 * PGMPhysRead/Write cache to reduce REM memory access overhead
1404 */
1405typedef struct PGMPHYSCACHE
1406{
1407 /** Bitmap of valid cache entries */
1408 uint64_t aEntries;
1409 /** Cache entries */
1410 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1411} PGMPHYSCACHE;
1412
1413
1414/** Pointer to an allocation chunk ring-3 mapping. */
1415typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1416/** Pointer to an allocation chunk ring-3 mapping pointer. */
1417typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1418
1419/**
1420 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1421 *
1422 * The primary tree (Core) uses the chunk id as key.
1423 */
1424typedef struct PGMCHUNKR3MAP
1425{
1426 /** The key is the chunk id. */
1427 AVLU32NODECORE Core;
1428 /** The current age thingy. */
1429 uint32_t iAge;
1430 /** The current reference count. */
1431 uint32_t volatile cRefs;
1432 /** The current permanent reference count. */
1433 uint32_t volatile cPermRefs;
1434 /** The mapping address. */
1435 void *pv;
1436} PGMCHUNKR3MAP;
1437
1438/**
1439 * Allocation chunk ring-3 mapping TLB entry.
1440 */
1441typedef struct PGMCHUNKR3MAPTLBE
1442{
1443 /** The chunk id. */
1444 uint32_t volatile idChunk;
1445#if HC_ARCH_BITS == 64
1446 uint32_t u32Padding; /**< alignment padding. */
1447#endif
1448 /** The chunk map. */
1449#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1450 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1451#else
1452 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1453#endif
1454} PGMCHUNKR3MAPTLBE;
1455/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1456typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1457
1458/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1459 * @remark Must be a power of two value. */
1460#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1461
1462/**
1463 * Allocation chunk ring-3 mapping TLB.
1464 *
1465 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1466 * At first glance this might look kinda odd since AVL trees are
1467 * supposed to give the most optimial lookup times of all trees
1468 * due to their balancing. However, take a tree with 1023 nodes
1469 * in it, that's 10 levels, meaning that most searches has to go
1470 * down 9 levels before they find what they want. This isn't fast
1471 * compared to a TLB hit. There is the factor of cache misses,
1472 * and of course the problem with trees and branch prediction.
1473 * This is why we use TLBs in front of most of the trees.
1474 *
1475 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1476 * difficult when we switch to the new inlined AVL trees (from kStuff).
1477 */
1478typedef struct PGMCHUNKR3MAPTLB
1479{
1480 /** The TLB entries. */
1481 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1482} PGMCHUNKR3MAPTLB;
1483
1484/**
1485 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1486 * @returns Chunk TLB index.
1487 * @param idChunk The Chunk ID.
1488 */
1489#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1490
1491
1492/**
1493 * Ring-3 guest page mapping TLB entry.
1494 * @remarks used in ring-0 as well at the moment.
1495 */
1496typedef struct PGMPAGER3MAPTLBE
1497{
1498 /** Address of the page. */
1499 RTGCPHYS volatile GCPhys;
1500 /** The guest page. */
1501#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1502 R3PTRTYPE(PPGMPAGE) volatile pPage;
1503#else
1504 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1505#endif
1506 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1507#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1508 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1509#else
1510 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1511#endif
1512 /** The address */
1513#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1514 R3PTRTYPE(void *) volatile pv;
1515#else
1516 R3R0PTRTYPE(void *) volatile pv;
1517#endif
1518#if HC_ARCH_BITS == 32
1519 uint32_t u32Padding; /**< alignment padding. */
1520#endif
1521} PGMPAGER3MAPTLBE;
1522/** Pointer to an entry in the HC physical TLB. */
1523typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1524
1525
1526/** The number of entries in the ring-3 guest page mapping TLB.
1527 * @remarks The value must be a power of two. */
1528#define PGM_PAGER3MAPTLB_ENTRIES 256
1529
1530/**
1531 * Ring-3 guest page mapping TLB.
1532 * @remarks used in ring-0 as well at the moment.
1533 */
1534typedef struct PGMPAGER3MAPTLB
1535{
1536 /** The TLB entries. */
1537 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1538} PGMPAGER3MAPTLB;
1539/** Pointer to the ring-3 guest page mapping TLB. */
1540typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1541
1542/**
1543 * Calculates the index of the TLB entry for the specified guest page.
1544 * @returns Physical TLB index.
1545 * @param GCPhys The guest physical address.
1546 */
1547#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1548
1549
1550/**
1551 * Mapping cache usage set entry.
1552 *
1553 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1554 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1555 * cache. If it's extended to include ring-3, well, then something will
1556 * have be changed here...
1557 */
1558typedef struct PGMMAPSETENTRY
1559{
1560 /** The mapping cache index. */
1561 uint16_t iPage;
1562 /** The number of references.
1563 * The max is UINT16_MAX - 1. */
1564 uint16_t cRefs;
1565#if HC_ARCH_BITS == 64
1566 uint32_t alignment;
1567#endif
1568 /** Pointer to the page. */
1569 RTR0PTR pvPage;
1570 /** The physical address for this entry. */
1571 RTHCPHYS HCPhys;
1572} PGMMAPSETENTRY;
1573/** Pointer to a mapping cache usage set entry. */
1574typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1575
1576/**
1577 * Mapping cache usage set.
1578 *
1579 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1580 * done during exits / traps. The set is
1581 */
1582typedef struct PGMMAPSET
1583{
1584 /** The number of occupied entries.
1585 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1586 * dynamic mappings. */
1587 uint32_t cEntries;
1588 /** The start of the current subset.
1589 * This is UINT32_MAX if no subset is currently open. */
1590 uint32_t iSubset;
1591 /** The index of the current CPU, only valid if the set is open. */
1592 int32_t iCpu;
1593 uint32_t alignment;
1594 /** The entries. */
1595 PGMMAPSETENTRY aEntries[64];
1596 /** HCPhys -> iEntry fast lookup table.
1597 * Use PGMMAPSET_HASH for hashing.
1598 * The entries may or may not be valid, check against cEntries. */
1599 uint8_t aiHashTable[128];
1600} PGMMAPSET;
1601AssertCompileSizeAlignment(PGMMAPSET, 8);
1602/** Pointer to the mapping cache set. */
1603typedef PGMMAPSET *PPGMMAPSET;
1604
1605/** PGMMAPSET::cEntries value for a closed set. */
1606#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1607
1608/** Hash function for aiHashTable. */
1609#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1610
1611/** The max fill size (strict builds). */
1612#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1613
1614
1615/** @name Context neutrual page mapper TLB.
1616 *
1617 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1618 * code is writting in a kind of context neutrual way. Time will show whether
1619 * this actually makes sense or not...
1620 *
1621 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1622 * context ends up using a global mapping cache on some platforms
1623 * (darwin).
1624 *
1625 * @{ */
1626/** @typedef PPGMPAGEMAPTLB
1627 * The page mapper TLB pointer type for the current context. */
1628/** @typedef PPGMPAGEMAPTLB
1629 * The page mapper TLB entry pointer type for the current context. */
1630/** @typedef PPGMPAGEMAPTLB
1631 * The page mapper TLB entry pointer pointer type for the current context. */
1632/** @def PGM_PAGEMAPTLB_ENTRIES
1633 * The number of TLB entries in the page mapper TLB for the current context. */
1634/** @def PGM_PAGEMAPTLB_IDX
1635 * Calculate the TLB index for a guest physical address.
1636 * @returns The TLB index.
1637 * @param GCPhys The guest physical address. */
1638/** @typedef PPGMPAGEMAP
1639 * Pointer to a page mapper unit for current context. */
1640/** @typedef PPPGMPAGEMAP
1641 * Pointer to a page mapper unit pointer for current context. */
1642#ifdef IN_RC
1643// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1644// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1645// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1646# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1647# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1648 typedef void * PPGMPAGEMAP;
1649 typedef void ** PPPGMPAGEMAP;
1650//#elif IN_RING0
1651// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1652// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1653// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1654//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1655//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1656// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1657// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1658#else
1659 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1660 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1661 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1662# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1663# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1664 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1665 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1666#endif
1667/** @} */
1668
1669
1670/** @name PGM Pool Indexes.
1671 * Aka. the unique shadow page identifier.
1672 * @{ */
1673/** NIL page pool IDX. */
1674#define NIL_PGMPOOL_IDX 0
1675/** The first normal index. */
1676#define PGMPOOL_IDX_FIRST_SPECIAL 1
1677/** Page directory (32-bit root). */
1678#define PGMPOOL_IDX_PD 1
1679/** Page Directory Pointer Table (PAE root). */
1680#define PGMPOOL_IDX_PDPT 2
1681/** AMD64 CR3 level index.*/
1682#define PGMPOOL_IDX_AMD64_CR3 3
1683/** Nested paging root.*/
1684#define PGMPOOL_IDX_NESTED_ROOT 4
1685/** The first normal index. */
1686#define PGMPOOL_IDX_FIRST 5
1687/** The last valid index. (inclusive, 14 bits) */
1688#define PGMPOOL_IDX_LAST 0x3fff
1689/** @} */
1690
1691/** The NIL index for the parent chain. */
1692#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1693#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1694
1695/**
1696 * Node in the chain linking a shadowed page to it's parent (user).
1697 */
1698#pragma pack(1)
1699typedef struct PGMPOOLUSER
1700{
1701 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1702 uint16_t iNext;
1703 /** The user page index. */
1704 uint16_t iUser;
1705 /** Index into the user table. */
1706 uint32_t iUserTable;
1707} PGMPOOLUSER, *PPGMPOOLUSER;
1708typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1709#pragma pack()
1710
1711
1712/** The NIL index for the phys ext chain. */
1713#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1714/** The NIL pte index for a phys ext chain slot. */
1715#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1716
1717/**
1718 * Node in the chain of physical cross reference extents.
1719 * @todo Calling this an 'extent' is not quite right, find a better name.
1720 * @todo find out the optimal size of the aidx array
1721 */
1722#pragma pack(1)
1723typedef struct PGMPOOLPHYSEXT
1724{
1725 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1726 uint16_t iNext;
1727 /** Alignment. */
1728 uint16_t u16Align;
1729 /** The user page index. */
1730 uint16_t aidx[3];
1731 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1732 uint16_t apte[3];
1733} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1734typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1735#pragma pack()
1736
1737
1738/**
1739 * The kind of page that's being shadowed.
1740 */
1741typedef enum PGMPOOLKIND
1742{
1743 /** The virtual invalid 0 entry. */
1744 PGMPOOLKIND_INVALID = 0,
1745 /** The entry is free (=unused). */
1746 PGMPOOLKIND_FREE,
1747
1748 /** Shw: 32-bit page table; Gst: no paging */
1749 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1750 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1751 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1752 /** Shw: 32-bit page table; Gst: 4MB page. */
1753 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1754 /** Shw: PAE page table; Gst: no paging */
1755 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1756 /** Shw: PAE page table; Gst: 32-bit page table. */
1757 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1758 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1759 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1760 /** Shw: PAE page table; Gst: PAE page table. */
1761 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1762 /** Shw: PAE page table; Gst: 2MB page. */
1763 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1764
1765 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1766 PGMPOOLKIND_32BIT_PD,
1767 /** Shw: 32-bit page directory. Gst: no paging. */
1768 PGMPOOLKIND_32BIT_PD_PHYS,
1769 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1770 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1771 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1772 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1773 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1774 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1775 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1776 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1777 /** Shw: PAE page directory; Gst: PAE page directory. */
1778 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1779 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1780 PGMPOOLKIND_PAE_PD_PHYS,
1781
1782 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1783 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1784 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1785 PGMPOOLKIND_PAE_PDPT,
1786 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1787 PGMPOOLKIND_PAE_PDPT_PHYS,
1788
1789 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1790 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1791 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1792 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1793 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1794 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1795 /** Shw: 64-bit page directory table; Gst: no paging */
1796 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1797
1798 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1799 PGMPOOLKIND_64BIT_PML4,
1800
1801 /** Shw: EPT page directory pointer table; Gst: no paging */
1802 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1803 /** Shw: EPT page directory table; Gst: no paging */
1804 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1805 /** Shw: EPT page table; Gst: no paging */
1806 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1807
1808 /** Shw: Root Nested paging table. */
1809 PGMPOOLKIND_ROOT_NESTED,
1810
1811 /** The last valid entry. */
1812 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1813} PGMPOOLKIND;
1814
1815/**
1816 * The access attributes of the page; only applies to big pages.
1817 */
1818typedef enum
1819{
1820 PGMPOOLACCESS_DONTCARE = 0,
1821 PGMPOOLACCESS_USER_RW,
1822 PGMPOOLACCESS_USER_R,
1823 PGMPOOLACCESS_USER_RW_NX,
1824 PGMPOOLACCESS_USER_R_NX,
1825 PGMPOOLACCESS_SUPERVISOR_RW,
1826 PGMPOOLACCESS_SUPERVISOR_R,
1827 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1828 PGMPOOLACCESS_SUPERVISOR_R_NX
1829} PGMPOOLACCESS;
1830
1831/**
1832 * The tracking data for a page in the pool.
1833 */
1834typedef struct PGMPOOLPAGE
1835{
1836 /** AVL node code with the (R3) physical address of this page. */
1837 AVLOHCPHYSNODECORE Core;
1838 /** Pointer to the R3 mapping of the page. */
1839#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1840 R3PTRTYPE(void *) pvPageR3;
1841#else
1842 R3R0PTRTYPE(void *) pvPageR3;
1843#endif
1844 /** The guest physical address. */
1845#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1846 uint32_t Alignment0;
1847#endif
1848 RTGCPHYS GCPhys;
1849
1850 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1851 RTGCPTR pvLastAccessHandlerRip;
1852 RTGCPTR pvLastAccessHandlerFault;
1853 uint64_t cLastAccessHandlerCount;
1854
1855 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1856 uint8_t enmKind;
1857 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1858 uint8_t enmAccess;
1859 /** The index of this page. */
1860 uint16_t idx;
1861 /** The next entry in the list this page currently resides in.
1862 * It's either in the free list or in the GCPhys hash. */
1863 uint16_t iNext;
1864 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1865 uint16_t iUserHead;
1866 /** The number of present entries. */
1867 uint16_t cPresent;
1868 /** The first entry in the table which is present. */
1869 uint16_t iFirstPresent;
1870 /** The number of modifications to the monitored page. */
1871 uint16_t cModifications;
1872 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1873 uint16_t iModifiedNext;
1874 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1875 uint16_t iModifiedPrev;
1876 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1877 uint16_t iMonitoredNext;
1878 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1879 uint16_t iMonitoredPrev;
1880 /** The next page in the age list. */
1881 uint16_t iAgeNext;
1882 /** The previous page in the age list. */
1883 uint16_t iAgePrev;
1884 /** Used to indicate that the page is zeroed. */
1885 bool fZeroed;
1886 /** Used to indicate that a PT has non-global entries. */
1887 bool fSeenNonGlobal;
1888 /** Used to indicate that we're monitoring writes to the guest page. */
1889 bool fMonitored;
1890 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1891 * (All pages are in the age list.) */
1892 bool fCached;
1893 /** This is used by the R3 access handlers when invoked by an async thread.
1894 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1895 bool volatile fReusedFlushPending;
1896 /** Used to mark the page as dirty (write monitoring is temporarily
1897 * off). */
1898 bool fDirty;
1899
1900 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1901 uint32_t cLocked;
1902 uint32_t idxDirty;
1903 RTGCPTR pvDirtyFault;
1904} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1905/** Pointer to a const pool page. */
1906typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1907
1908
1909/** The hash table size. */
1910# define PGMPOOL_HASH_SIZE 0x40
1911/** The hash function. */
1912# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1913
1914
1915/**
1916 * The shadow page pool instance data.
1917 *
1918 * It's all one big allocation made at init time, except for the
1919 * pages that is. The user nodes follows immediatly after the
1920 * page structures.
1921 */
1922typedef struct PGMPOOL
1923{
1924 /** The VM handle - R3 Ptr. */
1925 PVMR3 pVMR3;
1926 /** The VM handle - R0 Ptr. */
1927 PVMR0 pVMR0;
1928 /** The VM handle - RC Ptr. */
1929 PVMRC pVMRC;
1930 /** The max pool size. This includes the special IDs. */
1931 uint16_t cMaxPages;
1932 /** The current pool size. */
1933 uint16_t cCurPages;
1934 /** The head of the free page list. */
1935 uint16_t iFreeHead;
1936 /* Padding. */
1937 uint16_t u16Padding;
1938 /** Head of the chain of free user nodes. */
1939 uint16_t iUserFreeHead;
1940 /** The number of user nodes we've allocated. */
1941 uint16_t cMaxUsers;
1942 /** The number of present page table entries in the entire pool. */
1943 uint32_t cPresent;
1944 /** Pointer to the array of user nodes - RC pointer. */
1945 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1946 /** Pointer to the array of user nodes - R3 pointer. */
1947 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1948 /** Pointer to the array of user nodes - R0 pointer. */
1949 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1950 /** Head of the chain of free phys ext nodes. */
1951 uint16_t iPhysExtFreeHead;
1952 /** The number of user nodes we've allocated. */
1953 uint16_t cMaxPhysExts;
1954 /** Pointer to the array of physical xref extent - RC pointer. */
1955 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1956 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1957 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1958 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1959 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1960 /** Hash table for GCPhys addresses. */
1961 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1962 /** The head of the age list. */
1963 uint16_t iAgeHead;
1964 /** The tail of the age list. */
1965 uint16_t iAgeTail;
1966 /** Set if the cache is enabled. */
1967 bool fCacheEnabled;
1968 /** Alignment padding. */
1969 bool afPadding1[3];
1970 /** Head of the list of modified pages. */
1971 uint16_t iModifiedHead;
1972 /** The current number of modified pages. */
1973 uint16_t cModifiedPages;
1974 /** Access handler, RC. */
1975 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1976 /** Access handler, R0. */
1977 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1978 /** Access handler, R3. */
1979 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1980 /** The access handler description (R3 ptr). */
1981 R3PTRTYPE(const char *) pszAccessHandler;
1982# if HC_ARCH_BITS == 32
1983 /** Alignment padding. */
1984 uint32_t u32Padding2;
1985# endif
1986 /* Next available slot. */
1987 uint32_t idxFreeDirtyPage;
1988 /* Number of active dirty pages. */
1989 uint32_t cDirtyPages;
1990 /* Array of current dirty pgm pool page indices. */
1991 uint16_t aIdxDirtyPages[16];
1992 uint64_t aDirtyPages[16][512];
1993 /** The number of pages currently in use. */
1994 uint16_t cUsedPages;
1995#ifdef VBOX_WITH_STATISTICS
1996 /** The high water mark for cUsedPages. */
1997 uint16_t cUsedPagesHigh;
1998 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1999 /** Profiling pgmPoolAlloc(). */
2000 STAMPROFILEADV StatAlloc;
2001 /** Profiling pgmR3PoolClearDoIt(). */
2002 STAMPROFILE StatClearAll;
2003 /** Profiling pgmR3PoolReset(). */
2004 STAMPROFILE StatR3Reset;
2005 /** Profiling pgmPoolFlushPage(). */
2006 STAMPROFILE StatFlushPage;
2007 /** Profiling pgmPoolFree(). */
2008 STAMPROFILE StatFree;
2009 /** Counting explicit flushes by PGMPoolFlushPage(). */
2010 STAMCOUNTER StatForceFlushPage;
2011 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2012 STAMCOUNTER StatForceFlushDirtyPage;
2013 /** Counting flushes for reused pages. */
2014 STAMCOUNTER StatForceFlushReused;
2015 /** Profiling time spent zeroing pages. */
2016 STAMPROFILE StatZeroPage;
2017 /** Profiling of pgmPoolTrackDeref. */
2018 STAMPROFILE StatTrackDeref;
2019 /** Profiling pgmTrackFlushGCPhysPT. */
2020 STAMPROFILE StatTrackFlushGCPhysPT;
2021 /** Profiling pgmTrackFlushGCPhysPTs. */
2022 STAMPROFILE StatTrackFlushGCPhysPTs;
2023 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2024 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2025 /** Number of times we've been out of user records. */
2026 STAMCOUNTER StatTrackFreeUpOneUser;
2027 /** Nr of flushed entries. */
2028 STAMCOUNTER StatTrackFlushEntry;
2029 /** Nr of updated entries. */
2030 STAMCOUNTER StatTrackFlushEntryKeep;
2031 /** Profiling deref activity related tracking GC physical pages. */
2032 STAMPROFILE StatTrackDerefGCPhys;
2033 /** Number of linear searches for a HCPhys in the ram ranges. */
2034 STAMCOUNTER StatTrackLinearRamSearches;
2035 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2036 STAMCOUNTER StamTrackPhysExtAllocFailures;
2037 /** Profiling the RC/R0 access handler. */
2038 STAMPROFILE StatMonitorRZ;
2039 /** Times we've failed interpreting the instruction. */
2040 STAMCOUNTER StatMonitorRZEmulateInstr;
2041 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2042 STAMPROFILE StatMonitorRZFlushPage;
2043 /* Times we've detected a page table reinit. */
2044 STAMCOUNTER StatMonitorRZFlushReinit;
2045 /** Counting flushes for pages that are modified too often. */
2046 STAMCOUNTER StatMonitorRZFlushModOverflow;
2047 /** Times we've detected fork(). */
2048 STAMCOUNTER StatMonitorRZFork;
2049 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2050 STAMPROFILE StatMonitorRZHandled;
2051 /** Times we've failed interpreting a patch code instruction. */
2052 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2053 /** Times we've failed interpreting a patch code instruction during flushing. */
2054 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2055 /** The number of times we've seen rep prefixes we can't handle. */
2056 STAMCOUNTER StatMonitorRZRepPrefix;
2057 /** Profiling the REP STOSD cases we've handled. */
2058 STAMPROFILE StatMonitorRZRepStosd;
2059 /** Nr of handled PT faults. */
2060 STAMCOUNTER StatMonitorRZFaultPT;
2061 /** Nr of handled PD faults. */
2062 STAMCOUNTER StatMonitorRZFaultPD;
2063 /** Nr of handled PDPT faults. */
2064 STAMCOUNTER StatMonitorRZFaultPDPT;
2065 /** Nr of handled PML4 faults. */
2066 STAMCOUNTER StatMonitorRZFaultPML4;
2067
2068 /** Profiling the R3 access handler. */
2069 STAMPROFILE StatMonitorR3;
2070 /** Times we've failed interpreting the instruction. */
2071 STAMCOUNTER StatMonitorR3EmulateInstr;
2072 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2073 STAMPROFILE StatMonitorR3FlushPage;
2074 /* Times we've detected a page table reinit. */
2075 STAMCOUNTER StatMonitorR3FlushReinit;
2076 /** Counting flushes for pages that are modified too often. */
2077 STAMCOUNTER StatMonitorR3FlushModOverflow;
2078 /** Times we've detected fork(). */
2079 STAMCOUNTER StatMonitorR3Fork;
2080 /** Profiling the R3 access we've handled (except REP STOSD). */
2081 STAMPROFILE StatMonitorR3Handled;
2082 /** The number of times we've seen rep prefixes we can't handle. */
2083 STAMCOUNTER StatMonitorR3RepPrefix;
2084 /** Profiling the REP STOSD cases we've handled. */
2085 STAMPROFILE StatMonitorR3RepStosd;
2086 /** Nr of handled PT faults. */
2087 STAMCOUNTER StatMonitorR3FaultPT;
2088 /** Nr of handled PD faults. */
2089 STAMCOUNTER StatMonitorR3FaultPD;
2090 /** Nr of handled PDPT faults. */
2091 STAMCOUNTER StatMonitorR3FaultPDPT;
2092 /** Nr of handled PML4 faults. */
2093 STAMCOUNTER StatMonitorR3FaultPML4;
2094 /** The number of times we're called in an async thread an need to flush. */
2095 STAMCOUNTER StatMonitorR3Async;
2096 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2097 STAMCOUNTER StatResetDirtyPages;
2098 /** Times we've called pgmPoolAddDirtyPage. */
2099 STAMCOUNTER StatDirtyPage;
2100 /** Times we've had to flush duplicates for dirty page management. */
2101 STAMCOUNTER StatDirtyPageDupFlush;
2102 /** Times we've had to flush because of overflow. */
2103 STAMCOUNTER StatDirtyPageOverFlowFlush;
2104
2105 /** The high wather mark for cModifiedPages. */
2106 uint16_t cModifiedPagesHigh;
2107 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2108
2109 /** The number of cache hits. */
2110 STAMCOUNTER StatCacheHits;
2111 /** The number of cache misses. */
2112 STAMCOUNTER StatCacheMisses;
2113 /** The number of times we've got a conflict of 'kind' in the cache. */
2114 STAMCOUNTER StatCacheKindMismatches;
2115 /** Number of times we've been out of pages. */
2116 STAMCOUNTER StatCacheFreeUpOne;
2117 /** The number of cacheable allocations. */
2118 STAMCOUNTER StatCacheCacheable;
2119 /** The number of uncacheable allocations. */
2120 STAMCOUNTER StatCacheUncacheable;
2121#else
2122 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2123#endif
2124 /** The AVL tree for looking up a page by its HC physical address. */
2125 AVLOHCPHYSTREE HCPhysTree;
2126 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2127 /** Array of pages. (cMaxPages in length)
2128 * The Id is the index into thist array.
2129 */
2130 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2131} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2132AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2133AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2134AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2135#ifdef VBOX_WITH_STATISTICS
2136AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2137#endif
2138AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2139
2140
2141/** @def PGMPOOL_PAGE_2_PTR
2142 * Maps a pool page pool into the current context.
2143 *
2144 * @returns VBox status code.
2145 * @param pVM The VM handle.
2146 * @param pPage The pool page.
2147 *
2148 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2149 * small page window employeed by that function. Be careful.
2150 * @remark There is no need to assert on the result.
2151 */
2152#if defined(IN_RC)
2153# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage))
2154#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2155# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage))
2156#elif defined(VBOX_STRICT)
2157# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2158DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2159{
2160 Assert(pPage && pPage->pvPageR3);
2161 return pPage->pvPageR3;
2162}
2163#else
2164# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2165#endif
2166
2167
2168/** @def PGMPOOL_PAGE_2_PTR_V2
2169 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2170 *
2171 * @returns VBox status code.
2172 * @param pVM The VM handle.
2173 * @param pVCpu The current CPU.
2174 * @param pPage The pool page.
2175 *
2176 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2177 * small page window employeed by that function. Be careful.
2178 * @remark There is no need to assert on the result.
2179 */
2180#if defined(IN_RC)
2181# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage))
2182#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2183# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage))
2184#else
2185# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2186#endif
2187
2188
2189/** @name Per guest page tracking data.
2190 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2191 * is to use more bits for it and split it up later on. But for now we'll play
2192 * safe and change as little as possible.
2193 *
2194 * The 16-bit word has two parts:
2195 *
2196 * The first 14-bit forms the @a idx field. It is either the index of a page in
2197 * the shadow page pool, or and index into the extent list.
2198 *
2199 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2200 * shadow page pool references to the page. If cRefs equals
2201 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2202 * (misnomer) table and not the shadow page pool.
2203 *
2204 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2205 * the 16-bit word.
2206 *
2207 * @{ */
2208/** The shift count for getting to the cRefs part. */
2209#define PGMPOOL_TD_CREFS_SHIFT 14
2210/** The mask applied after shifting the tracking data down by
2211 * PGMPOOL_TD_CREFS_SHIFT. */
2212#define PGMPOOL_TD_CREFS_MASK 0x3
2213/** The cRef value used to indiciate that the idx is the head of a
2214 * physical cross reference list. */
2215#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2216/** The shift used to get idx. */
2217#define PGMPOOL_TD_IDX_SHIFT 0
2218/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2219#define PGMPOOL_TD_IDX_MASK 0x3fff
2220/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2221 * simply too many mappings of this page. */
2222#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2223
2224/** @def PGMPOOL_TD_MAKE
2225 * Makes a 16-bit tracking data word.
2226 *
2227 * @returns tracking data.
2228 * @param cRefs The @a cRefs field. Must be within bounds!
2229 * @param idx The @a idx field. Must also be within bounds! */
2230#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2231
2232/** @def PGMPOOL_TD_GET_CREFS
2233 * Get the @a cRefs field from a tracking data word.
2234 *
2235 * @returns The @a cRefs field
2236 * @param u16 The tracking data word. */
2237#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2238
2239/** @def PGMPOOL_TD_GET_IDX
2240 * Get the @a idx field from a tracking data word.
2241 *
2242 * @returns The @a idx field
2243 * @param u16 The tracking data word. */
2244#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2245/** @} */
2246
2247
2248/**
2249 * Trees are using self relative offsets as pointers.
2250 * So, all its data, including the root pointer, must be in the heap for HC and GC
2251 * to have the same layout.
2252 */
2253typedef struct PGMTREES
2254{
2255 /** Physical access handlers (AVL range+offsetptr tree). */
2256 AVLROGCPHYSTREE PhysHandlers;
2257 /** Virtual access handlers (AVL range + GC ptr tree). */
2258 AVLROGCPTRTREE VirtHandlers;
2259 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2260 AVLROGCPHYSTREE PhysToVirtHandlers;
2261 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2262 AVLROGCPTRTREE HyperVirtHandlers;
2263} PGMTREES;
2264/** Pointer to PGM trees. */
2265typedef PGMTREES *PPGMTREES;
2266
2267
2268/**
2269 * Page fault guest state for the AMD64 paging mode.
2270 */
2271typedef struct PGMPTWALKCORE
2272{
2273 /** The guest virtual address that is being resolved by the walk
2274 * (input). */
2275 RTGCPTR GCPtr;
2276
2277 /** The guest physcial address that is the result of the walk.
2278 * @remarks only valid if fSucceeded is set. */
2279 RTGCPHYS GCPhys;
2280
2281 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2282 bool fSucceeded;
2283 /** The level problem arrised at.
2284 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2285 * level 8. This is 0 on success. */
2286 uint8_t uLevel;
2287 /** Set if the page isn't present. */
2288 bool fNotPresent;
2289 /** Encountered a bad physical address. */
2290 bool fBadPhysAddr;
2291 /** Set if there was reserved bit violations. */
2292 bool fRsvdError;
2293 /** Set if it involves a big page (2/4 MB). */
2294 bool fBigPage;
2295 /** Set if it involves a gigantic page (1 GB). */
2296 bool fGigantPage;
2297 /** The effect X86_PTE_US flag for the address. */
2298 bool fEffectiveUS;
2299 /** The effect X86_PTE_RW flag for the address. */
2300 bool fEffectiveRW;
2301 /** The effect X86_PTE_NX flag for the address. */
2302 bool fEffectiveNX;
2303} PGMPTWALKCORE;
2304
2305
2306/**
2307 * Guest page table walk for the AMD64 mode.
2308 */
2309typedef struct PGMPTWALKGSTAMD64
2310{
2311 /** The common core. */
2312 PGMPTWALKCORE Core;
2313
2314 PX86PML4 pPml4;
2315 PX86PML4E pPml4e;
2316 X86PML4E Pml4e;
2317
2318 PX86PDPT pPdpt;
2319 PX86PDPE pPdpe;
2320 X86PDPE Pdpe;
2321
2322 PX86PDPAE pPd;
2323 PX86PDEPAE pPde;
2324 X86PDEPAE Pde;
2325
2326 PX86PTPAE pPt;
2327 PX86PTEPAE pPte;
2328 X86PTEPAE Pte;
2329} PGMPTWALKGSTAMD64;
2330/** Pointer to a AMD64 guest page table walk. */
2331typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2332/** Pointer to a const AMD64 guest page table walk. */
2333typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2334
2335/**
2336 * Guest page table walk for the PAE mode.
2337 */
2338typedef struct PGMPTWALKGSTPAE
2339{
2340 /** The common core. */
2341 PGMPTWALKCORE Core;
2342
2343 PX86PDPT pPdpt;
2344 PX86PDPE pPdpe;
2345 X86PDPE Pdpe;
2346
2347 PX86PDPAE pPd;
2348 PX86PDEPAE pPde;
2349 X86PDEPAE Pde;
2350
2351 PX86PTPAE pPt;
2352 PX86PTEPAE pPte;
2353 X86PTEPAE Pte;
2354} PGMPTWALKGSTPAE;
2355/** Pointer to a PAE guest page table walk. */
2356typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2357/** Pointer to a const AMD64 guest page table walk. */
2358typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2359
2360/**
2361 * Guest page table walk for the 32-bit mode.
2362 */
2363typedef struct PGMPTWALKGST32BIT
2364{
2365 /** The common core. */
2366 PGMPTWALKCORE Core;
2367
2368 PX86PD pPd;
2369 PX86PDE pPde;
2370 X86PDE Pde;
2371
2372 PX86PT pPt;
2373 PX86PTE pPte;
2374 X86PTE Pte;
2375} PGMPTWALKGST32BIT;
2376/** Pointer to a 32-bit guest page table walk. */
2377typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2378/** Pointer to a const 32-bit guest page table walk. */
2379typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2380
2381
2382/** @name Paging mode macros
2383 * @{
2384 */
2385#ifdef IN_RC
2386# define PGM_CTX(a,b) a##RC##b
2387# define PGM_CTX_STR(a,b) a "GC" b
2388# define PGM_CTX_DECL(type) VMMRCDECL(type)
2389#else
2390# ifdef IN_RING3
2391# define PGM_CTX(a,b) a##R3##b
2392# define PGM_CTX_STR(a,b) a "R3" b
2393# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2394# else
2395# define PGM_CTX(a,b) a##R0##b
2396# define PGM_CTX_STR(a,b) a "R0" b
2397# define PGM_CTX_DECL(type) VMMDECL(type)
2398# endif
2399#endif
2400
2401#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2402#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2403#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2404#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2405#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2406#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2407#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2408#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2409#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2410#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2411#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2412#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2413#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2414#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2415#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2416#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2417#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2418
2419#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2420#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2421#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2422#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2423#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2424#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2425#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2426#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2427#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2428#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2429#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2430#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2431#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2432#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2433#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2434#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2435#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2436
2437/* Shw_Gst */
2438#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2439#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2440#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2441#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2442#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2443#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2444#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2445#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2446#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2447#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2448#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2449#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2450#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2451#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2452#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2453#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2454#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2455#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2456#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2457
2458#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2459#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2460#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2461#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2462#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2463#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2464#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2465#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2466#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2467#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2468#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2469#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2470#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2471#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2472#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2473#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2474#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2475#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2476#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2477#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2478#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2479#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2480#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2481#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2482#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2483#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2484#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2485#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2486#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2487#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2488#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2489#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2490#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2491#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2492#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2493#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2494#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2495
2496#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2497#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2498/** @} */
2499
2500/**
2501 * Data for each paging mode.
2502 */
2503typedef struct PGMMODEDATA
2504{
2505 /** The guest mode type. */
2506 uint32_t uGstType;
2507 /** The shadow mode type. */
2508 uint32_t uShwType;
2509
2510 /** @name Function pointers for Shadow paging.
2511 * @{
2512 */
2513 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2514 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2515 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2516 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2517
2518 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2519 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2520
2521 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2522 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2523 /** @} */
2524
2525 /** @name Function pointers for Guest paging.
2526 * @{
2527 */
2528 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2529 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2530 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2531 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2532 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2533 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2534 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2535 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2536 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2537 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2538 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2539 /** @} */
2540
2541 /** @name Function pointers for Both Shadow and Guest paging.
2542 * @{
2543 */
2544 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2545 /* no pfnR3BthTrap0eHandler */
2546 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2547 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2548 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2549 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2550#ifdef VBOX_STRICT
2551 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2552#endif
2553 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2554 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2555
2556 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2557 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2558 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2559 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2560 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2561#ifdef VBOX_STRICT
2562 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2563#endif
2564 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2565 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2566
2567 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2568 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2569 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2570 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2571 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2572#ifdef VBOX_STRICT
2573 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2574#endif
2575 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2576 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2577 /** @} */
2578} PGMMODEDATA, *PPGMMODEDATA;
2579
2580
2581#ifdef VBOX_WITH_STATISTICS
2582/**
2583 * PGM statistics.
2584 *
2585 * These lives on the heap when compiled in as they would otherwise waste
2586 * unecessary space in release builds.
2587 */
2588typedef struct PGMSTATS
2589{
2590 /* R3 only: */
2591 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2592 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2593
2594 /* R3+RZ */
2595 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2596 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2597 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2598 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2599 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2600 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2601 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2602 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2603 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2604 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2605 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2606 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2607 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2608 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2609 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2610 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2611 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2612 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2613 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2614 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2615 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2616 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2617 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2618 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2619/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2620 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2621 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2622/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2623
2624 /* RC only: */
2625 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2626 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2627 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2628 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2629
2630 STAMCOUNTER StatRZPhysRead;
2631 STAMCOUNTER StatRZPhysReadBytes;
2632 STAMCOUNTER StatRZPhysWrite;
2633 STAMCOUNTER StatRZPhysWriteBytes;
2634 STAMCOUNTER StatR3PhysRead;
2635 STAMCOUNTER StatR3PhysReadBytes;
2636 STAMCOUNTER StatR3PhysWrite;
2637 STAMCOUNTER StatR3PhysWriteBytes;
2638 STAMCOUNTER StatRCPhysRead;
2639 STAMCOUNTER StatRCPhysReadBytes;
2640 STAMCOUNTER StatRCPhysWrite;
2641 STAMCOUNTER StatRCPhysWriteBytes;
2642
2643 STAMCOUNTER StatRZPhysSimpleRead;
2644 STAMCOUNTER StatRZPhysSimpleReadBytes;
2645 STAMCOUNTER StatRZPhysSimpleWrite;
2646 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2647 STAMCOUNTER StatR3PhysSimpleRead;
2648 STAMCOUNTER StatR3PhysSimpleReadBytes;
2649 STAMCOUNTER StatR3PhysSimpleWrite;
2650 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2651 STAMCOUNTER StatRCPhysSimpleRead;
2652 STAMCOUNTER StatRCPhysSimpleReadBytes;
2653 STAMCOUNTER StatRCPhysSimpleWrite;
2654 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2655
2656 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2657 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2658 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2659 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2660 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2661 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2662 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2663
2664 /** Time spent by the host OS for large page allocation. */
2665 STAMPROFILE StatAllocLargePage;
2666 /** Time spent clearing the newly allocated large pages. */
2667 STAMPROFILE StatClearLargePage;
2668 /** pgmPhysIsValidLargePage profiling - R3 */
2669 STAMPROFILE StatR3IsValidLargePage;
2670 /** pgmPhysIsValidLargePage profiling - RZ*/
2671 STAMPROFILE StatRZIsValidLargePage;
2672
2673 STAMPROFILE StatChunkAging;
2674 STAMPROFILE StatChunkFindCandidate;
2675 STAMPROFILE StatChunkUnmap;
2676 STAMPROFILE StatChunkMap;
2677} PGMSTATS;
2678#endif /* VBOX_WITH_STATISTICS */
2679
2680
2681/**
2682 * Converts a PGM pointer into a VM pointer.
2683 * @returns Pointer to the VM structure the PGM is part of.
2684 * @param pPGM Pointer to PGM instance data.
2685 */
2686#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2687
2688/**
2689 * PGM Data (part of VM)
2690 */
2691typedef struct PGM
2692{
2693 /** Offset to the VM structure. */
2694 int32_t offVM;
2695 /** Offset of the PGMCPU structure relative to VMCPU. */
2696 int32_t offVCpuPGM;
2697
2698 /** @cfgm{RamPreAlloc, boolean, false}
2699 * Indicates whether the base RAM should all be allocated before starting
2700 * the VM (default), or if it should be allocated when first written to.
2701 */
2702 bool fRamPreAlloc;
2703 /** Indicates whether write monitoring is currently in use.
2704 * This is used to prevent conflicts between live saving and page sharing
2705 * detection. */
2706 bool fPhysWriteMonitoringEngaged;
2707 /** Set if the CPU has less than 52-bit physical address width.
2708 * This is used */
2709 bool fLessThan52PhysicalAddressBits;
2710 /** Set when nested paging is active.
2711 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2712 * compilers optimize the code better. Whether we use nested paging or
2713 * not is something we find out during VMM initialization and we won't
2714 * change this later on. */
2715 bool fNestedPaging;
2716 /** The host paging mode. (This is what SUPLib reports.) */
2717 SUPPAGINGMODE enmHostMode;
2718 /** We're not in a state which permits writes to guest memory.
2719 * (Only used in strict builds.) */
2720 bool fNoMorePhysWrites;
2721 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2722 bool afAlignment1[3];
2723
2724 /** Indicates that PGMR3FinalizeMappings has been called and that further
2725 * PGMR3MapIntermediate calls will be rejected. */
2726 bool fFinalizedMappings;
2727 /** If set no conflict checks are required. */
2728 bool fMappingsFixed;
2729 /** If set if restored as fixed but we were unable to re-fixate at the old
2730 * location because of room or address incompatibilities. */
2731 bool fMappingsFixedRestored;
2732 /** If set, then no mappings are put into the shadow page table.
2733 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2734 bool fMappingsDisabled;
2735 /** Size of fixed mapping.
2736 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2737 uint32_t cbMappingFixed;
2738 /** Generation ID for the RAM ranges. This member is incremented everytime
2739 * a RAM range is linked or unlinked. */
2740 uint32_t volatile idRamRangesGen;
2741
2742 /** Base address (GC) of fixed mapping.
2743 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2744 RTGCPTR GCPtrMappingFixed;
2745 /** The address of the previous RAM range mapping. */
2746 RTGCPTR GCPtrPrevRamRangeMapping;
2747
2748 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2749 RTGCPHYS GCPhys4MBPSEMask;
2750 /** Mask containing the invalid bits of a guest physical address.
2751 * @remarks this does not stop at bit 52. */
2752 RTGCPHYS GCPhysInvAddrMask;
2753
2754
2755 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2756 * This is sorted by physical address and contains no overlapping ranges. */
2757 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2758 /** PGM offset based trees - R3 Ptr. */
2759 R3PTRTYPE(PPGMTREES) pTreesR3;
2760 /** Caching the last physical handler we looked up in R3. */
2761 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2762 /** Shadow Page Pool - R3 Ptr. */
2763 R3PTRTYPE(PPGMPOOL) pPoolR3;
2764 /** Linked list of GC mappings - for HC.
2765 * The list is sorted ascending on address. */
2766 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2767 /** Pointer to the list of ROM ranges - for R3.
2768 * This is sorted by physical address and contains no overlapping ranges. */
2769 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2770 /** Pointer to the list of MMIO2 ranges - for R3.
2771 * Registration order. */
2772 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2773 /** Pointer to SHW+GST mode data (function pointers).
2774 * The index into this table is made up from */
2775 R3PTRTYPE(PPGMMODEDATA) paModeData;
2776 /*RTR3PTR R3PtrAlignment0;*/
2777
2778
2779 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2780 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2781 /** PGM offset based trees - R0 Ptr. */
2782 R0PTRTYPE(PPGMTREES) pTreesR0;
2783 /** Caching the last physical handler we looked up in R0. */
2784 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2785 /** Shadow Page Pool - R0 Ptr. */
2786 R0PTRTYPE(PPGMPOOL) pPoolR0;
2787 /** Linked list of GC mappings - for R0.
2788 * The list is sorted ascending on address. */
2789 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2790 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2791 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2792 /*RTR0PTR R0PtrAlignment0;*/
2793
2794
2795 /** RC pointer corresponding to PGM::pRamRangesR3. */
2796 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2797 /** PGM offset based trees - RC Ptr. */
2798 RCPTRTYPE(PPGMTREES) pTreesRC;
2799 /** Caching the last physical handler we looked up in RC. */
2800 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2801 /** Shadow Page Pool - RC Ptr. */
2802 RCPTRTYPE(PPGMPOOL) pPoolRC;
2803 /** Linked list of GC mappings - for RC.
2804 * The list is sorted ascending on address. */
2805 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2806 /** RC pointer corresponding to PGM::pRomRangesR3. */
2807 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2808 /*RTRCPTR RCPtrAlignment0;*/
2809 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2810 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2811 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2812 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2813
2814
2815 /** Pointer to the 5 page CR3 content mapping.
2816 * The first page is always the CR3 (in some form) while the 4 other pages
2817 * are used of the PDs in PAE mode. */
2818 RTGCPTR GCPtrCR3Mapping;
2819
2820 /** @name Intermediate Context
2821 * @{ */
2822 /** Pointer to the intermediate page directory - Normal. */
2823 R3PTRTYPE(PX86PD) pInterPD;
2824 /** Pointer to the intermedate page tables - Normal.
2825 * There are two page tables, one for the identity mapping and one for
2826 * the host context mapping (of the core code). */
2827 R3PTRTYPE(PX86PT) apInterPTs[2];
2828 /** Pointer to the intermedate page tables - PAE. */
2829 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2830 /** Pointer to the intermedate page directory - PAE. */
2831 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2832 /** Pointer to the intermedate page directory - PAE. */
2833 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2834 /** Pointer to the intermedate page-map level 4 - AMD64. */
2835 R3PTRTYPE(PX86PML4) pInterPaePML4;
2836 /** Pointer to the intermedate page directory - AMD64. */
2837 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2838 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2839 RTHCPHYS HCPhysInterPD;
2840 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2841 RTHCPHYS HCPhysInterPaePDPT;
2842 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2843 RTHCPHYS HCPhysInterPaePML4;
2844 /** @} */
2845
2846 /** Base address of the dynamic page mapping area.
2847 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2848 */
2849 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2850 /** The index of the last entry used in the dynamic page mapping area. */
2851 RTUINT iDynPageMapLast;
2852 /** Cache containing the last entries in the dynamic page mapping area.
2853 * The cache size is covering half of the mapping area. */
2854 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2855 /** Keep a lock counter for the full (!) mapping area. */
2856 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2857
2858 /** The address of the ring-0 mapping cache if we're making use of it. */
2859 RTR0PTR pvR0DynMapUsed;
2860#if HC_ARCH_BITS == 32
2861 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2862 uint32_t u32Alignment2;
2863#endif
2864
2865 /** PGM critical section.
2866 * This protects the physical & virtual access handlers, ram ranges,
2867 * and the page flag updating (some of it anyway).
2868 */
2869 PDMCRITSECT CritSect;
2870
2871 /**
2872 * Data associated with managing the ring-3 mappings of the allocation chunks.
2873 */
2874 struct
2875 {
2876 /** The chunk tree, ordered by chunk id. */
2877#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2878 R3PTRTYPE(PAVLU32NODECORE) pTree;
2879#else
2880 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2881#endif
2882#if HC_ARCH_BITS == 32
2883 uint32_t u32Alignment;
2884#endif
2885 /** The chunk mapping TLB. */
2886 PGMCHUNKR3MAPTLB Tlb;
2887 /** The number of mapped chunks. */
2888 uint32_t c;
2889 /** The maximum number of mapped chunks.
2890 * @cfgm PGM/MaxRing3Chunks */
2891 uint32_t cMax;
2892 /** The current time. */
2893 uint32_t iNow;
2894 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2895 uint32_t AgeingCountdown;
2896 } ChunkR3Map;
2897
2898 /**
2899 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2900 */
2901 PGMPAGER3MAPTLB PhysTlbHC;
2902
2903 /** @name The zero page.
2904 * @{ */
2905 /** The host physical address of the zero page. */
2906 RTHCPHYS HCPhysZeroPg;
2907 /** The ring-3 mapping of the zero page. */
2908 RTR3PTR pvZeroPgR3;
2909 /** The ring-0 mapping of the zero page. */
2910 RTR0PTR pvZeroPgR0;
2911 /** The GC mapping of the zero page. */
2912 RTRCPTR pvZeroPgRC;
2913 RTRCPTR RCPtrAlignment3;
2914 /** @}*/
2915
2916 /** @name The Invalid MMIO page.
2917 * This page is filled with 0xfeedface.
2918 * @{ */
2919 /** The host physical address of the invalid MMIO page. */
2920 RTHCPHYS HCPhysMmioPg;
2921 /** The host pysical address of the invalid MMIO page pluss all invalid
2922 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2923 * @remarks Check fLessThan52PhysicalAddressBits before use. */
2924 RTHCPHYS HCPhysInvMmioPg;
2925 /** The ring-3 mapping of the invalid MMIO page. */
2926 RTR3PTR pvMmioPgR3;
2927#if HC_ARCH_BITS == 32
2928 RTR3PTR R3PtrAlignment4;
2929#endif
2930 /** @} */
2931
2932
2933 /** The number of handy pages. */
2934 uint32_t cHandyPages;
2935
2936 /** The number of large handy pages. */
2937 uint32_t cLargeHandyPages;
2938
2939 /**
2940 * Array of handy pages.
2941 *
2942 * This array is used in a two way communication between pgmPhysAllocPage
2943 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2944 * an intermediary.
2945 *
2946 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2947 * (The current size of 32 pages, means 128 KB of handy memory.)
2948 */
2949 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2950
2951 /**
2952 * Array of large handy pages. (currently size 1)
2953 *
2954 * This array is used in a two way communication between pgmPhysAllocLargePage
2955 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2956 * an intermediary.
2957 */
2958 GMMPAGEDESC aLargeHandyPage[1];
2959
2960 /**
2961 * Live save data.
2962 */
2963 struct
2964 {
2965 /** Per type statistics. */
2966 struct
2967 {
2968 /** The number of ready pages. */
2969 uint32_t cReadyPages;
2970 /** The number of dirty pages. */
2971 uint32_t cDirtyPages;
2972 /** The number of ready zero pages. */
2973 uint32_t cZeroPages;
2974 /** The number of write monitored pages. */
2975 uint32_t cMonitoredPages;
2976 } Rom,
2977 Mmio2,
2978 Ram;
2979 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2980 uint32_t cIgnoredPages;
2981 /** Indicates that a live save operation is active. */
2982 bool fActive;
2983 /** Padding. */
2984 bool afReserved[2];
2985 /** The next history index. */
2986 uint8_t iDirtyPagesHistory;
2987 /** History of the total amount of dirty pages. */
2988 uint32_t acDirtyPagesHistory[64];
2989 /** Short term dirty page average. */
2990 uint32_t cDirtyPagesShort;
2991 /** Long term dirty page average. */
2992 uint32_t cDirtyPagesLong;
2993 /** The number of saved pages. This is used to get some kind of estimate of the
2994 * link speed so we can decide when we're done. It is reset after the first
2995 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2996 * zero pages. */
2997 uint64_t cSavedPages;
2998 /** The nanosecond timestamp when cSavedPages was 0. */
2999 uint64_t uSaveStartNS;
3000 /** Pages per second (for statistics). */
3001 uint32_t cPagesPerSecond;
3002 uint32_t cAlignment;
3003 } LiveSave;
3004
3005 /** @name Error injection.
3006 * @{ */
3007 /** Inject handy page allocation errors pretending we're completely out of
3008 * memory. */
3009 bool volatile fErrInjHandyPages;
3010 /** Padding. */
3011 bool afReserved[3];
3012 /** @} */
3013
3014 /** @name Release Statistics
3015 * @{ */
3016 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3017 uint32_t cPrivatePages; /**< The number of private pages. */
3018 uint32_t cSharedPages; /**< The number of shared pages. */
3019 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3020 uint32_t cZeroPages; /**< The number of zero backed pages. */
3021 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3022 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3023 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3024 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3025 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3026 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3027 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3028 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3029/* uint32_t aAlignment4[1]; */
3030
3031 /** The number of times we were forced to change the hypervisor region location. */
3032 STAMCOUNTER cRelocations;
3033
3034 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3035 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3036 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3037 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3038 /** @} */
3039
3040#ifdef VBOX_WITH_STATISTICS
3041 /** @name Statistics on the heap.
3042 * @{ */
3043 R3PTRTYPE(PGMSTATS *) pStatsR3;
3044 R0PTRTYPE(PGMSTATS *) pStatsR0;
3045 RCPTRTYPE(PGMSTATS *) pStatsRC;
3046 RTRCPTR RCPtrAlignment;
3047 /** @} */
3048#endif
3049} PGM;
3050#ifndef IN_TSTVMSTRUCTGC /* HACK */
3051AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3052AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3053AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3054AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
3055AssertCompileMemberAlignment(PGM, CritSect, 8);
3056AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3057AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3058AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3059AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3060AssertCompileMemberAlignment(PGM, cRelocations, 8);
3061#endif /* !IN_TSTVMSTRUCTGC */
3062/** Pointer to the PGM instance data. */
3063typedef PGM *PPGM;
3064
3065
3066
3067typedef struct PGMCPUSTATS
3068{
3069 /* Common */
3070 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3071 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3072
3073 /* R0 only: */
3074 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3075 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3076 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3077 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3078 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3079 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3080 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3081 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3082 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3083 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3084 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3085 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3086 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3087 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3088 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3089 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3090 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3091 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3092 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3093 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3094 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3095 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3096 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3097 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3098 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3099 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3100
3101 /* RZ only: */
3102 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3103 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3104 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3105 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3106 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3107 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3108 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3109 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3110 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3111 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3112 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3113 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3114 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3115 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3116 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3117 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3118 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3119 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3120 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3121 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3122 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3123 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3124 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3125 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3126 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3127 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3128 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3129 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3130 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3131 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3132 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3133 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3134 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3135 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3136 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3137 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3138 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3139 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3140 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3141 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3142 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3143 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3144 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3145 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3146 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3147 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3148 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3149 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3150
3151 /* HC - R3 and (maybe) R0: */
3152
3153 /* RZ & R3: */
3154 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3155 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3156 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3157 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3158 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3159 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3160 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3161 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3162 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3163 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3164 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3165 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3166 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3167 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3168 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3169 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3170 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3171 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3172 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3173 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3174 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3175 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3176 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3177 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3178 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3179 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3180 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3181 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3182 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3183 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3184 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3185 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3186 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3187 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3188 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3189 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3190 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3191 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3192 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3193 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3194 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3195 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3196 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3197 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3198 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3199 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3200 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3201
3202 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3203 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3204 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3205 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3206 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3207 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3208 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3209 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3210 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3211 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3212 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3213 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3214 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3215 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3216 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3217 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3218 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3219 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3220 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3221 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3222 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3223 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3224 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3225 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3226 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3227 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3228 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3229 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3230 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3231 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3232 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3233 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3234 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3235 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3236 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3237 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3238 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3239 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3240 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3241 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3242 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3243 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3244 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3245 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3246 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3247 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3248 /** @} */
3249} PGMCPUSTATS;
3250
3251
3252/**
3253 * Converts a PGMCPU pointer into a VM pointer.
3254 * @returns Pointer to the VM structure the PGM is part of.
3255 * @param pPGM Pointer to PGMCPU instance data.
3256 */
3257#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3258
3259/**
3260 * Converts a PGMCPU pointer into a PGM pointer.
3261 * @returns Pointer to the VM structure the PGM is part of.
3262 * @param pPGM Pointer to PGMCPU instance data.
3263 */
3264#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3265
3266/**
3267 * PGMCPU Data (part of VMCPU).
3268 */
3269typedef struct PGMCPU
3270{
3271 /** Offset to the VM structure. */
3272 RTINT offVM;
3273 /** Offset to the VMCPU structure. */
3274 RTINT offVCpu;
3275 /** Offset of the PGM structure relative to VMCPU. */
3276 RTINT offPGM;
3277 RTINT uPadding0; /**< structure size alignment. */
3278
3279#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3280 /** Automatically tracked physical memory mapping set.
3281 * Ring-0 and strict raw-mode builds. */
3282 PGMMAPSET AutoSet;
3283#endif
3284
3285 /** A20 gate mask.
3286 * Our current approach to A20 emulation is to let REM do it and don't bother
3287 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3288 * But whould need arrise, we'll subject physical addresses to this mask. */
3289 RTGCPHYS GCPhysA20Mask;
3290 /** A20 gate state - boolean! */
3291 bool fA20Enabled;
3292 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3293 bool fNoExecuteEnabled;
3294 /** Unused bits. */
3295 bool afUnused[2];
3296
3297 /** What needs syncing (PGM_SYNC_*).
3298 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3299 * PGMFlushTLB, and PGMR3Load. */
3300 RTUINT fSyncFlags;
3301
3302 /** The shadow paging mode. */
3303 PGMMODE enmShadowMode;
3304 /** The guest paging mode. */
3305 PGMMODE enmGuestMode;
3306
3307 /** The current physical address representing in the guest CR3 register. */
3308 RTGCPHYS GCPhysCR3;
3309
3310 /** @name 32-bit Guest Paging.
3311 * @{ */
3312 /** The guest's page directory, R3 pointer. */
3313 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3314#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3315 /** The guest's page directory, R0 pointer. */
3316 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3317#endif
3318 /** The guest's page directory, static RC mapping. */
3319 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3320 /** Mask containing the MBZ bits of a big page PDE. */
3321 uint32_t fGst32BitMbzBigPdeMask;
3322 /** Set if the page size extension (PSE) is enabled. */
3323 bool fGst32BitPageSizeExtension;
3324 /** Alignment padding. */
3325 bool afAlignment2[3];
3326 /** @} */
3327
3328 /** @name PAE Guest Paging.
3329 * @{ */
3330 /** The guest's page directory pointer table, static RC mapping. */
3331 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3332 /** The guest's page directory pointer table, R3 pointer. */
3333 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3334#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3335 /** The guest's page directory pointer table, R0 pointer. */
3336 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3337#endif
3338
3339 /** The guest's page directories, R3 pointers.
3340 * These are individual pointers and don't have to be adjecent.
3341 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3342 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3343 /** The guest's page directories, R0 pointers.
3344 * Same restrictions as apGstPaePDsR3. */
3345#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3346 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3347#endif
3348 /** The guest's page directories, static GC mapping.
3349 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3350 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3351 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3352 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3353 RTGCPHYS aGCPhysGstPaePDs[4];
3354 /** The physical addresses of the monitored guest page directories (PAE). */
3355 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3356 /** Mask containing the MBZ PTE bits. */
3357 uint64_t fGstPaeMbzPteMask;
3358 /** Mask containing the MBZ PDE bits. */
3359 uint64_t fGstPaeMbzPdeMask;
3360 /** Mask containing the MBZ big page PDE bits. */
3361 uint64_t fGstPaeMbzBigPdeMask;
3362 /** Mask containing the MBZ PDPE bits. */
3363 uint64_t fGstPaeMbzPdpeMask;
3364 /** @} */
3365
3366 /** @name AMD64 Guest Paging.
3367 * @{ */
3368 /** The guest's page directory pointer table, R3 pointer. */
3369 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3370#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3371 /** The guest's page directory pointer table, R0 pointer. */
3372 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3373#else
3374 RTR0PTR alignment6b; /**< alignment equalizer. */
3375#endif
3376 /** Mask containing the MBZ PTE bits. */
3377 uint64_t fGstAmd64MbzPteMask;
3378 /** Mask containing the MBZ PDE bits. */
3379 uint64_t fGstAmd64MbzPdeMask;
3380 /** Mask containing the MBZ big page PDE bits. */
3381 uint64_t fGstAmd64MbzBigPdeMask;
3382 /** Mask containing the MBZ PDPE bits. */
3383 uint64_t fGstAmd64MbzPdpeMask;
3384 /** Mask containing the MBZ big page PDPE bits. */
3385 uint64_t fGstAmd64MbzBigPdpeMask;
3386 /** Mask containing the MBZ PML4E bits. */
3387 uint64_t fGstAmd64MbzPml4eMask;
3388 /** @} */
3389
3390 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3391 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3392 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3393 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3394 /** Pointer to the page of the current active CR3 - RC Ptr. */
3395 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3396 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3397 uint32_t iShwUser;
3398 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3399 uint32_t iShwUserTable;
3400# if HC_ARCH_BITS == 64
3401 RTRCPTR alignment6; /**< structure size alignment. */
3402# endif
3403 /** @} */
3404
3405 /** @name Function pointers for Shadow paging.
3406 * @{
3407 */
3408 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3409 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3410 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3411 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3412
3413 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3414 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3415
3416 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3417 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3418
3419 /** @} */
3420
3421 /** @name Function pointers for Guest paging.
3422 * @{
3423 */
3424 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3425 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3426 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3427 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3428 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3429 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3430 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3431 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3432#if HC_ARCH_BITS == 64
3433 RTRCPTR alignment3; /**< structure size alignment. */
3434#endif
3435
3436 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3437 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3438 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3439 /** @} */
3440
3441 /** @name Function pointers for Both Shadow and Guest paging.
3442 * @{
3443 */
3444 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3445 /* no pfnR3BthTrap0eHandler */
3446 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3447 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3448 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3449 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3450 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3451 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3452 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3453
3454 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3455 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3456 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3457 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3458 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3459 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3460 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3461 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3462
3463 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3464 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3465 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3466 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3467 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3468 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3469 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3470 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3471#if 0
3472 RTRCPTR alignment2; /**< structure size alignment. */
3473#endif
3474 /** @} */
3475
3476 /** For saving stack space, the disassembler state is allocated here instead of
3477 * on the stack.
3478 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3479 union
3480 {
3481 /** The disassembler scratch space. */
3482 DISCPUSTATE DisState;
3483 /** Padding. */
3484 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3485 };
3486
3487 /** Count the number of pgm pool access handler calls. */
3488 uint64_t cPoolAccessHandler;
3489
3490 /** @name Release Statistics
3491 * @{ */
3492 /** The number of times the guest has switched mode since last reset or statistics reset. */
3493 STAMCOUNTER cGuestModeChanges;
3494 /** @} */
3495
3496#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3497 /** @name Statistics
3498 * @{ */
3499 /** RC: Pointer to the statistics. */
3500 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3501 /** RC: Which statistic this \#PF should be attributed to. */
3502 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3503 /** R0: Pointer to the statistics. */
3504 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3505 /** R0: Which statistic this \#PF should be attributed to. */
3506 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3507 /** R3: Pointer to the statistics. */
3508 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3509 /** Alignment padding. */
3510 RTR3PTR pPaddingR3;
3511 /** @} */
3512#endif /* VBOX_WITH_STATISTICS */
3513} PGMCPU;
3514/** Pointer to the per-cpu PGM data. */
3515typedef PGMCPU *PPGMCPU;
3516
3517
3518/** @name PGM::fSyncFlags Flags
3519 * @{
3520 */
3521/** Updates the virtual access handler state bit in PGMPAGE. */
3522#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3523/** Always sync CR3. */
3524#define PGM_SYNC_ALWAYS RT_BIT(1)
3525/** Check monitoring on next CR3 (re)load and invalidate page.
3526 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3527#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3528/** Check guest mapping in SyncCR3. */
3529#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3530/** Clear the page pool (a light weight flush). */
3531#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3532#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3533/** @} */
3534
3535
3536RT_C_DECLS_BEGIN
3537
3538int pgmLock(PVM pVM);
3539void pgmUnlock(PVM pVM);
3540
3541int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3542int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3543int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3544PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3545int pgmMapResolveConflicts(PVM pVM);
3546DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3547
3548void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3549bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3550void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3551int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3552DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3553#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3554void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3555#else
3556# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3557#endif
3558DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3559int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3560
3561int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3562int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3563int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3564int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3565int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3566void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3567int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3568int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3569int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3570int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3571int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3572int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3573int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3574VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3575VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3576int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3577
3578#ifdef IN_RING3
3579void pgmR3PhysRelinkRamRanges(PVM pVM);
3580int pgmR3PhysRamPreAllocate(PVM pVM);
3581int pgmR3PhysRamReset(PVM pVM);
3582int pgmR3PhysRomReset(PVM pVM);
3583int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3584int pgmR3PhysRamTerm(PVM pVM);
3585void pgmR3PhysRomTerm(PVM pVM);
3586
3587int pgmR3PoolInit(PVM pVM);
3588void pgmR3PoolRelocate(PVM pVM);
3589void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3590void pgmR3PoolReset(PVM pVM);
3591void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3592DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3593
3594#endif /* IN_RING3 */
3595#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3596int pgmR0DynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3597#endif
3598int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3599
3600DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3601{
3602 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3603}
3604
3605void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3606void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3607int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3608void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3609PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3610int pgmPoolSyncCR3(PVMCPU pVCpu);
3611bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3612int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3613void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3614void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3615DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3616{
3617 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3618}
3619
3620uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3621void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3622void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3623int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3624void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3625
3626void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3627void pgmPoolResetDirtyPages(PVM pVM);
3628
3629int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3630int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3631
3632void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3633void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3634int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3635int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3636
3637int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3638
3639int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3640int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3641int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3642int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3643
3644# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3645DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3646DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3647# endif
3648
3649RT_C_DECLS_END
3650
3651/** @} */
3652
3653#endif
3654
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