VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31402

Last change on this file since 31402 was 31402, checked in by vboxsync, 14 years ago

PGM: Replaced the hazzardous raw-mode context dynamic mapping code with the PGMR0DynMap code used by darwin/x86. This is a risky change but it should pay off once stable by providing 100% certainty that dynamically mapped pages aren't resued behind our back (this has been observed in seemingly benign code paths recently).
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1/* $Id: PGMInternal.h 31402 2010-08-05 12:28:18Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * @param pVCpu The current CPU.
322 * @param pPage The pool page.
323 */
324#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
325# ifdef LOG_ENABLED
326# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
327# else
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
329# endif
330#else
331# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
332#endif
333
334/** @def PGM_DYNMAP_UNUSED_HINT_VM
335 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
336 * is no longer used.
337 *
338 * @param pVM The VM handle.
339 * @param pPage The pool page.
340 */
341#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
342
343
344/** @def PGM_INVL_PG
345 * Invalidates a page.
346 *
347 * @param pVCpu The VMCPU handle.
348 * @param GCVirt The virtual address of the page to invalidate.
349 */
350#ifdef IN_RC
351# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
352#elif defined(IN_RING0)
353# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354#else
355# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
356#endif
357
358/** @def PGM_INVL_PG_ALL_VCPU
359 * Invalidates a page on all VCPUs
360 *
361 * @param pVM The VM handle.
362 * @param GCVirt The virtual address of the page to invalidate.
363 */
364#ifdef IN_RC
365# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
366#elif defined(IN_RING0)
367# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368#else
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
370#endif
371
372/** @def PGM_INVL_BIG_PG
373 * Invalidates a 4MB page directory entry.
374 *
375 * @param pVCpu The VMCPU handle.
376 * @param GCVirt The virtual address within the page directory to invalidate.
377 */
378#ifdef IN_RC
379# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_VCPU_TLBS()
387 * Invalidates the TLBs of the specified VCPU
388 *
389 * @param pVCpu The VMCPU handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_ALL_VCPU_TLBS()
400 * Invalidates the TLBs of all VCPUs
401 *
402 * @param pVM The VM handle.
403 */
404#ifdef IN_RC
405# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
408#else
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
410#endif
411
412/** Size of the GCPtrConflict array in PGMMAPPING.
413 * @remarks Must be a power of two. */
414#define PGMMAPPING_CONFLICT_MAX 8
415
416/**
417 * Structure for tracking GC Mappings.
418 *
419 * This structure is used by linked list in both GC and HC.
420 */
421typedef struct PGMMAPPING
422{
423 /** Pointer to next entry. */
424 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
425 /** Pointer to next entry. */
426 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
427 /** Pointer to next entry. */
428 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
429 /** Indicate whether this entry is finalized. */
430 bool fFinalized;
431 /** Start Virtual address. */
432 RTGCPTR GCPtr;
433 /** Last Virtual address (inclusive). */
434 RTGCPTR GCPtrLast;
435 /** Range size (bytes). */
436 RTGCPTR cb;
437 /** Pointer to relocation callback function. */
438 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
439 /** User argument to the callback. */
440 R3PTRTYPE(void *) pvUser;
441 /** Mapping description / name. For easing debugging. */
442 R3PTRTYPE(const char *) pszDesc;
443 /** Last 8 addresses that caused conflicts. */
444 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
445 /** Number of conflicts for this hypervisor mapping. */
446 uint32_t cConflicts;
447 /** Number of page tables. */
448 uint32_t cPTs;
449
450 /** Array of page table mapping data. Each entry
451 * describes one page table. The array can be longer
452 * than the declared length.
453 */
454 struct
455 {
456 /** The HC physical address of the page table. */
457 RTHCPHYS HCPhysPT;
458 /** The HC physical address of the first PAE page table. */
459 RTHCPHYS HCPhysPaePT0;
460 /** The HC physical address of the second PAE page table. */
461 RTHCPHYS HCPhysPaePT1;
462 /** The HC virtual address of the 32-bit page table. */
463 R3PTRTYPE(PX86PT) pPTR3;
464 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
465 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
466 /** The RC virtual address of the 32-bit page table. */
467 RCPTRTYPE(PX86PT) pPTRC;
468 /** The RC virtual address of the two PAE page table. */
469 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
470 /** The R0 virtual address of the 32-bit page table. */
471 R0PTRTYPE(PX86PT) pPTR0;
472 /** The R0 virtual address of the two PAE page table. */
473 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
474 } aPTs[1];
475} PGMMAPPING;
476/** Pointer to structure for tracking GC Mappings. */
477typedef struct PGMMAPPING *PPGMMAPPING;
478
479
480/**
481 * Physical page access handler structure.
482 *
483 * This is used to keep track of physical address ranges
484 * which are being monitored in some kind of way.
485 */
486typedef struct PGMPHYSHANDLER
487{
488 AVLROGCPHYSNODECORE Core;
489 /** Access type. */
490 PGMPHYSHANDLERTYPE enmType;
491 /** Number of pages to update. */
492 uint32_t cPages;
493 /** Pointer to R3 callback function. */
494 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
495 /** User argument for R3 handlers. */
496 R3PTRTYPE(void *) pvUserR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
499 /** User argument for R0 handlers. */
500 R0PTRTYPE(void *) pvUserR0;
501 /** Pointer to RC callback function. */
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
503 /** User argument for RC handlers. */
504 RCPTRTYPE(void *) pvUserRC;
505 /** Description / Name. For easing debugging. */
506 R3PTRTYPE(const char *) pszDesc;
507#ifdef VBOX_WITH_STATISTICS
508 /** Profiling of this handler. */
509 STAMPROFILE Stat;
510#endif
511} PGMPHYSHANDLER;
512/** Pointer to a physical page access handler structure. */
513typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
514
515
516/**
517 * Cache node for the physical addresses covered by a virtual handler.
518 */
519typedef struct PGMPHYS2VIRTHANDLER
520{
521 /** Core node for the tree based on physical ranges. */
522 AVLROGCPHYSNODECORE Core;
523 /** Offset from this struct to the PGMVIRTHANDLER structure. */
524 int32_t offVirtHandler;
525 /** Offset of the next alias relative to this one.
526 * Bit 0 is used for indicating whether we're in the tree.
527 * Bit 1 is used for indicating that we're the head node.
528 */
529 int32_t offNextAlias;
530} PGMPHYS2VIRTHANDLER;
531/** Pointer to a phys to virtual handler structure. */
532typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
533
534/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
535 * node is in the tree. */
536#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
537/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
538 * node is in the head of an alias chain.
539 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
540#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
541/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
542#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
543
544
545/**
546 * Virtual page access handler structure.
547 *
548 * This is used to keep track of virtual address ranges
549 * which are being monitored in some kind of way.
550 */
551typedef struct PGMVIRTHANDLER
552{
553 /** Core node for the tree based on virtual ranges. */
554 AVLROGCPTRNODECORE Core;
555 /** Size of the range (in bytes). */
556 RTGCPTR cb;
557 /** Number of cache pages. */
558 uint32_t cPages;
559 /** Access type. */
560 PGMVIRTHANDLERTYPE enmType;
561 /** Pointer to the RC callback function. */
562 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
563#if HC_ARCH_BITS == 64
564 RTRCPTR padding;
565#endif
566 /** Pointer to the R3 callback function for invalidation. */
567 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
568 /** Pointer to the R3 callback function. */
569 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
570 /** Description / Name. For easing debugging. */
571 R3PTRTYPE(const char *) pszDesc;
572#ifdef VBOX_WITH_STATISTICS
573 /** Profiling of this handler. */
574 STAMPROFILE Stat;
575#endif
576 /** Array of cached physical addresses for the monitored ranged. */
577 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
578} PGMVIRTHANDLER;
579/** Pointer to a virtual page access handler structure. */
580typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
581
582
583/**
584 * Page type.
585 *
586 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
587 * @remarks This is used in the saved state, so changes to it requires bumping
588 * the saved state version.
589 * @todo So, convert to \#defines!
590 */
591typedef enum PGMPAGETYPE
592{
593 /** The usual invalid zero entry. */
594 PGMPAGETYPE_INVALID = 0,
595 /** RAM page. (RWX) */
596 PGMPAGETYPE_RAM,
597 /** MMIO2 page. (RWX) */
598 PGMPAGETYPE_MMIO2,
599 /** MMIO2 page aliased over an MMIO page. (RWX)
600 * See PGMHandlerPhysicalPageAlias(). */
601 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
602 /** Shadowed ROM. (RWX) */
603 PGMPAGETYPE_ROM_SHADOW,
604 /** ROM page. (R-X) */
605 PGMPAGETYPE_ROM,
606 /** MMIO page. (---) */
607 PGMPAGETYPE_MMIO,
608 /** End of valid entries. */
609 PGMPAGETYPE_END
610} PGMPAGETYPE;
611AssertCompile(PGMPAGETYPE_END <= 7);
612
613/** @name Page type predicates.
614 * @{ */
615#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
616#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
617#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
618#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
619#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
620/** @} */
621
622
623/**
624 * A Physical Guest Page tracking structure.
625 *
626 * The format of this structure is complicated because we have to fit a lot
627 * of information into as few bits as possible. The format is also subject
628 * to change (there is one comming up soon). Which means that for we'll be
629 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
630 * accesses to the structure.
631 */
632typedef struct PGMPAGE
633{
634 /** The physical address and the Page ID. */
635 RTHCPHYS HCPhysAndPageID;
636 /** Combination of:
637 * - [0-7]: u2HandlerPhysStateY - the physical handler state
638 * (PGM_PAGE_HNDL_PHYS_STATE_*).
639 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
640 * (PGM_PAGE_HNDL_VIRT_STATE_*).
641 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
642 * - [15]: fWrittenToY - flag indicating that a write monitored page was
643 * written to when set.
644 * - [10-13]: 4 unused bits.
645 * @remarks Warning! All accesses to the bits are hardcoded.
646 *
647 * @todo Change this to a union with both bitfields, u8 and u accessors.
648 * That'll help deal with some of the hardcoded accesses.
649 *
650 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
651 * will make it possible to turn some of the 16-bit accesses into
652 * 32-bit ones, which may be efficient (stalls).
653 */
654 RTUINT16U u16MiscY;
655 /** The page state.
656 * Only 3 bits are really needed for this. */
657 uint16_t uStateY : 3;
658 /** The page type (PGMPAGETYPE).
659 * Only 3 bits are really needed for this. */
660 uint16_t uTypeY : 3;
661 /** PTE index for usage tracking (page pool). */
662 uint16_t uPteIdx : 10;
663 /** Usage tracking (page pool). */
664 uint16_t u16TrackingY;
665 /** The number of read locks on this page. */
666 uint8_t cReadLocksY;
667 /** The number of write locks on this page. */
668 uint8_t cWriteLocksY;
669} PGMPAGE;
670AssertCompileSize(PGMPAGE, 16);
671/** Pointer to a physical guest page. */
672typedef PGMPAGE *PPGMPAGE;
673/** Pointer to a const physical guest page. */
674typedef const PGMPAGE *PCPGMPAGE;
675/** Pointer to a physical guest page pointer. */
676typedef PPGMPAGE *PPPGMPAGE;
677
678
679/**
680 * Clears the page structure.
681 * @param pPage Pointer to the physical guest page tracking structure.
682 */
683#define PGM_PAGE_CLEAR(pPage) \
684 do { \
685 (pPage)->HCPhysAndPageID = 0; \
686 (pPage)->uStateY = 0; \
687 (pPage)->uTypeY = 0; \
688 (pPage)->uPteIdx = 0; \
689 (pPage)->u16MiscY.u = 0; \
690 (pPage)->u16TrackingY = 0; \
691 (pPage)->cReadLocksY = 0; \
692 (pPage)->cWriteLocksY = 0; \
693 } while (0)
694
695/**
696 * Initializes the page structure.
697 * @param pPage Pointer to the physical guest page tracking structure.
698 */
699#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
700 do { \
701 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
702 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
703 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
704 (pPage)->uStateY = (_uState); \
705 (pPage)->uTypeY = (_uType); \
706 (pPage)->uPteIdx = 0; \
707 (pPage)->u16MiscY.u = 0; \
708 (pPage)->u16TrackingY = 0; \
709 (pPage)->cReadLocksY = 0; \
710 (pPage)->cWriteLocksY = 0; \
711 } while (0)
712
713/**
714 * Initializes the page structure of a ZERO page.
715 * @param pPage Pointer to the physical guest page tracking structure.
716 * @param pVM The VM handle (for getting the zero page address).
717 * @param uType The page type (PGMPAGETYPE).
718 */
719#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
720 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
721
722
723/** @name The Page state, PGMPAGE::uStateY.
724 * @{ */
725/** The zero page.
726 * This is a per-VM page that's never ever mapped writable. */
727#define PGM_PAGE_STATE_ZERO 0
728/** A allocated page.
729 * This is a per-VM page allocated from the page pool (or wherever
730 * we get MMIO2 pages from if the type is MMIO2).
731 */
732#define PGM_PAGE_STATE_ALLOCATED 1
733/** A allocated page that's being monitored for writes.
734 * The shadow page table mappings are read-only. When a write occurs, the
735 * fWrittenTo member is set, the page remapped as read-write and the state
736 * moved back to allocated. */
737#define PGM_PAGE_STATE_WRITE_MONITORED 2
738/** The page is shared, aka. copy-on-write.
739 * This is a page that's shared with other VMs. */
740#define PGM_PAGE_STATE_SHARED 3
741/** The page is ballooned, so no longer available for this VM. */
742#define PGM_PAGE_STATE_BALLOONED 4
743/** @} */
744
745
746/**
747 * Gets the page state.
748 * @returns page state (PGM_PAGE_STATE_*).
749 * @param pPage Pointer to the physical guest page tracking structure.
750 */
751#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
752
753/**
754 * Sets the page state.
755 * @param pPage Pointer to the physical guest page tracking structure.
756 * @param _uState The new page state.
757 */
758#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
759
760
761/**
762 * Gets the host physical address of the guest page.
763 * @returns host physical address (RTHCPHYS).
764 * @param pPage Pointer to the physical guest page tracking structure.
765 */
766#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
767
768/**
769 * Sets the host physical address of the guest page.
770 * @param pPage Pointer to the physical guest page tracking structure.
771 * @param _HCPhys The new host physical address.
772 */
773#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
774 do { \
775 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
776 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
777 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
778 | (SetHCPhysTmp << (28-12)); \
779 } while (0)
780
781/**
782 * Get the Page ID.
783 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
784 * @param pPage Pointer to the physical guest page tracking structure.
785 */
786#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
787
788/**
789 * Sets the Page ID.
790 * @param pPage Pointer to the physical guest page tracking structure.
791 */
792#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
793 do { \
794 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
795 | ((_idPage) & UINT32_C(0x0fffffff)); \
796 } while (0)
797
798/**
799 * Get the Chunk ID.
800 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
804
805/**
806 * Get the index of the page within the allocation chunk.
807 * @returns The page index.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 */
810#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
811
812/**
813 * Gets the page type.
814 * @returns The page type.
815 * @param pPage Pointer to the physical guest page tracking structure.
816 */
817#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
818
819/**
820 * Sets the page type.
821 * @param pPage Pointer to the physical guest page tracking structure.
822 * @param _enmType The new page type (PGMPAGETYPE).
823 */
824#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
825
826/**
827 * Gets the page table index
828 * @returns The page table index.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
832
833/**
834 * Sets the page table index
835 * @param pPage Pointer to the physical guest page tracking structure.
836 * @param iPte New page table index.
837 */
838#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
839
840/**
841 * Checks if the page is marked for MMIO.
842 * @returns true/false.
843 * @param pPage Pointer to the physical guest page tracking structure.
844 */
845#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
846
847/**
848 * Checks if the page is backed by the ZERO page.
849 * @returns true/false.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
853
854/**
855 * Checks if the page is backed by a SHARED page.
856 * @returns true/false.
857 * @param pPage Pointer to the physical guest page tracking structure.
858 */
859#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
860
861/**
862 * Checks if the page is ballooned.
863 * @returns true/false.
864 * @param pPage Pointer to the physical guest page tracking structure.
865 */
866#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
867
868/**
869 * Marks the page as written to (for GMM change monitoring).
870 * @param pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
873
874/**
875 * Clears the written-to indicator.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
879
880/**
881 * Checks if the page was marked as written-to.
882 * @returns true/false.
883 * @param pPage Pointer to the physical guest page tracking structure.
884 */
885#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
886
887/** @name PT usage values (PGMPAGE::u2PDEType).
888 *
889 * @{ */
890/** Either as a PT or PDE. */
891#define PGM_PAGE_PDE_TYPE_DONTCARE 0
892/** Must use a page table to map the range. */
893#define PGM_PAGE_PDE_TYPE_PT 1
894/** Can use a page directory entry to map the continous range. */
895#define PGM_PAGE_PDE_TYPE_PDE 2
896/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
897#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
898/** @} */
899
900/**
901 * Set the PDE type of the page
902 * @param pPage Pointer to the physical guest page tracking structure.
903 * @param uType PGM_PAGE_PDE_TYPE_*
904 */
905#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
906 do { \
907 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
908 | (((uType) & UINT8_C(0x03)) << 5); \
909 } while (0)
910
911/**
912 * Checks if the page was marked being part of a large page
913 * @returns true/false.
914 * @param pPage Pointer to the physical guest page tracking structure.
915 */
916#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
917
918/** Enabled optimized access handler tests.
919 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
920 * layout. When enabled, the compiler should normally generate more compact
921 * code.
922 */
923#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
924
925/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
926 *
927 * @remarks The values are assigned in order of priority, so we can calculate
928 * the correct state for a page with different handlers installed.
929 * @{ */
930/** No handler installed. */
931#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
932/** Monitoring is temporarily disabled. */
933#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
934/** Write access is monitored. */
935#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
936/** All access is monitored. */
937#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
938/** @} */
939
940/**
941 * Gets the physical access handler state of a page.
942 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
946 ( (pPage)->u16MiscY.au8[0] )
947
948/**
949 * Sets the physical access handler state of a page.
950 * @param pPage Pointer to the physical guest page tracking structure.
951 * @param _uState The new state value.
952 */
953#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
954 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
955
956/**
957 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
958 * @returns true/false
959 * @param pPage Pointer to the physical guest page tracking structure.
960 */
961#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
962 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
963
964/**
965 * Checks if the page has any active physical access handlers.
966 * @returns true/false
967 * @param pPage Pointer to the physical guest page tracking structure.
968 */
969#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
970 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
971
972
973/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
974 *
975 * @remarks The values are assigned in order of priority, so we can calculate
976 * the correct state for a page with different handlers installed.
977 * @{ */
978/** No handler installed. */
979#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
980/* 1 is reserved so the lineup is identical with the physical ones. */
981/** Write access is monitored. */
982#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
983/** All access is monitored. */
984#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
985/** @} */
986
987/**
988 * Gets the virtual access handler state of a page.
989 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
990 * @param pPage Pointer to the physical guest page tracking structure.
991 */
992#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
993
994/**
995 * Sets the virtual access handler state of a page.
996 * @param pPage Pointer to the physical guest page tracking structure.
997 * @param _uState The new state value.
998 */
999#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1000 do { \
1001 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1002 | ((_uState) & UINT8_C(0x03)); \
1003 } while (0)
1004
1005/**
1006 * Checks if the page has any virtual access handlers.
1007 * @returns true/false
1008 * @param pPage Pointer to the physical guest page tracking structure.
1009 */
1010#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1011 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1012
1013/**
1014 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1015 * virtual handlers.
1016 * @returns true/false
1017 * @param pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1020 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1021
1022
1023/**
1024 * Checks if the page has any access handlers, including temporarily disabled ones.
1025 * @returns true/false
1026 * @param pPage Pointer to the physical guest page tracking structure.
1027 */
1028#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1029# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1030 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1031#else
1032# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1033 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1034 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1035#endif
1036
1037/**
1038 * Checks if the page has any active access handlers.
1039 * @returns true/false
1040 * @param pPage Pointer to the physical guest page tracking structure.
1041 */
1042#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1043# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1044 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1045#else
1046# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1047 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1048 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1049#endif
1050
1051/**
1052 * Checks if the page has any active access handlers catching all accesses.
1053 * @returns true/false
1054 * @param pPage Pointer to the physical guest page tracking structure.
1055 */
1056#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1057# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1058 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1059 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1060#else
1061# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1062 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1063 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1064#endif
1065
1066
1067/** @def PGM_PAGE_GET_TRACKING
1068 * Gets the packed shadow page pool tracking data associated with a guest page.
1069 * @returns uint16_t containing the data.
1070 * @param pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1073
1074/** @def PGM_PAGE_SET_TRACKING
1075 * Sets the packed shadow page pool tracking data associated with a guest page.
1076 * @param pPage Pointer to the physical guest page tracking structure.
1077 * @param u16TrackingData The tracking data to store.
1078 */
1079#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1080 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1081
1082/** @def PGM_PAGE_GET_TD_CREFS
1083 * Gets the @a cRefs tracking data member.
1084 * @returns cRefs.
1085 * @param pPage Pointer to the physical guest page tracking structure.
1086 */
1087#define PGM_PAGE_GET_TD_CREFS(pPage) \
1088 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1089
1090/** @def PGM_PAGE_GET_TD_IDX
1091 * Gets the @a idx tracking data member.
1092 * @returns idx.
1093 * @param pPage Pointer to the physical guest page tracking structure.
1094 */
1095#define PGM_PAGE_GET_TD_IDX(pPage) \
1096 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1097
1098
1099/** Max number of locks on a page. */
1100#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1101
1102/** Get the read lock count.
1103 * @returns count.
1104 * @param pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1107
1108/** Get the write lock count.
1109 * @returns count.
1110 * @param pPage Pointer to the physical guest page tracking structure.
1111 */
1112#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1113
1114/** Decrement the read lock counter.
1115 * @param pPage Pointer to the physical guest page tracking structure.
1116 */
1117#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1118
1119/** Decrement the write lock counter.
1120 * @param pPage Pointer to the physical guest page tracking structure.
1121 */
1122#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1123
1124/** Increment the read lock counter.
1125 * @param pPage Pointer to the physical guest page tracking structure.
1126 */
1127#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1128
1129/** Increment the write lock counter.
1130 * @param pPage Pointer to the physical guest page tracking structure.
1131 */
1132#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1133
1134
1135#if 0
1136/** Enables sanity checking of write monitoring using CRC-32. */
1137# define PGMLIVESAVERAMPAGE_WITH_CRC32
1138#endif
1139
1140/**
1141 * Per page live save tracking data.
1142 */
1143typedef struct PGMLIVESAVERAMPAGE
1144{
1145 /** Number of times it has been dirtied. */
1146 uint32_t cDirtied : 24;
1147 /** Whether it is currently dirty. */
1148 uint32_t fDirty : 1;
1149 /** Ignore the page.
1150 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1151 * deal with these after pausing the VM and DevPCI have said it bit about
1152 * remappings. */
1153 uint32_t fIgnore : 1;
1154 /** Was a ZERO page last time around. */
1155 uint32_t fZero : 1;
1156 /** Was a SHARED page last time around. */
1157 uint32_t fShared : 1;
1158 /** Whether the page is/was write monitored in a previous pass. */
1159 uint32_t fWriteMonitored : 1;
1160 /** Whether the page is/was write monitored earlier in this pass. */
1161 uint32_t fWriteMonitoredJustNow : 1;
1162 /** Bits reserved for future use. */
1163 uint32_t u2Reserved : 2;
1164#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1165 /** CRC-32 for the page. This is for internal consistency checks. */
1166 uint32_t u32Crc;
1167#endif
1168} PGMLIVESAVERAMPAGE;
1169#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1170AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1171#else
1172AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1173#endif
1174/** Pointer to the per page live save tracking data. */
1175typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1176
1177/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1178#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1179
1180
1181/**
1182 * Ram range for GC Phys to HC Phys conversion.
1183 *
1184 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1185 * conversions too, but we'll let MM handle that for now.
1186 *
1187 * This structure is used by linked lists in both GC and HC.
1188 */
1189typedef struct PGMRAMRANGE
1190{
1191 /** Start of the range. Page aligned. */
1192 RTGCPHYS GCPhys;
1193 /** Size of the range. (Page aligned of course). */
1194 RTGCPHYS cb;
1195 /** Pointer to the next RAM range - for R3. */
1196 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1197 /** Pointer to the next RAM range - for R0. */
1198 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1199 /** Pointer to the next RAM range - for RC. */
1200 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1201 /** PGM_RAM_RANGE_FLAGS_* flags. */
1202 uint32_t fFlags;
1203 /** Last address in the range (inclusive). Page aligned (-1). */
1204 RTGCPHYS GCPhysLast;
1205 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1206 R3PTRTYPE(void *) pvR3;
1207 /** Live save per page tracking data. */
1208 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1209 /** The range description. */
1210 R3PTRTYPE(const char *) pszDesc;
1211 /** Pointer to self - R0 pointer. */
1212 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1213 /** Pointer to self - RC pointer. */
1214 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1215 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1216 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1217 /** Array of physical guest page tracking structures. */
1218 PGMPAGE aPages[1];
1219} PGMRAMRANGE;
1220/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1221typedef PGMRAMRANGE *PPGMRAMRANGE;
1222
1223/** @name PGMRAMRANGE::fFlags
1224 * @{ */
1225/** The RAM range is floating around as an independent guest mapping. */
1226#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1227/** Ad hoc RAM range for an ROM mapping. */
1228#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1229/** Ad hoc RAM range for an MMIO mapping. */
1230#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1231/** Ad hoc RAM range for an MMIO2 mapping. */
1232#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1233/** @} */
1234
1235/** Tests if a RAM range is an ad hoc one or not.
1236 * @returns true/false.
1237 * @param pRam The RAM range.
1238 */
1239#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1240 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1241
1242
1243/**
1244 * Per page tracking structure for ROM image.
1245 *
1246 * A ROM image may have a shadow page, in which case we may have two pages
1247 * backing it. This structure contains the PGMPAGE for both while
1248 * PGMRAMRANGE have a copy of the active one. It is important that these
1249 * aren't out of sync in any regard other than page pool tracking data.
1250 */
1251typedef struct PGMROMPAGE
1252{
1253 /** The page structure for the virgin ROM page. */
1254 PGMPAGE Virgin;
1255 /** The page structure for the shadow RAM page. */
1256 PGMPAGE Shadow;
1257 /** The current protection setting. */
1258 PGMROMPROT enmProt;
1259 /** Live save status information. Makes use of unused alignment space. */
1260 struct
1261 {
1262 /** The previous protection value. */
1263 uint8_t u8Prot;
1264 /** Written to flag set by the handler. */
1265 bool fWrittenTo;
1266 /** Whether the shadow page is dirty or not. */
1267 bool fDirty;
1268 /** Whether it was dirtied in the recently. */
1269 bool fDirtiedRecently;
1270 } LiveSave;
1271} PGMROMPAGE;
1272AssertCompileSizeAlignment(PGMROMPAGE, 8);
1273/** Pointer to a ROM page tracking structure. */
1274typedef PGMROMPAGE *PPGMROMPAGE;
1275
1276
1277/**
1278 * A registered ROM image.
1279 *
1280 * This is needed to keep track of ROM image since they generally intrude
1281 * into a PGMRAMRANGE. It also keeps track of additional info like the
1282 * two page sets (read-only virgin and read-write shadow), the current
1283 * state of each page.
1284 *
1285 * Because access handlers cannot easily be executed in a different
1286 * context, the ROM ranges needs to be accessible and in all contexts.
1287 */
1288typedef struct PGMROMRANGE
1289{
1290 /** Pointer to the next range - R3. */
1291 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1292 /** Pointer to the next range - R0. */
1293 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1294 /** Pointer to the next range - RC. */
1295 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1296 /** Pointer alignment */
1297 RTRCPTR RCPtrAlignment;
1298 /** Address of the range. */
1299 RTGCPHYS GCPhys;
1300 /** Address of the last byte in the range. */
1301 RTGCPHYS GCPhysLast;
1302 /** Size of the range. */
1303 RTGCPHYS cb;
1304 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1305 uint32_t fFlags;
1306 /** The saved state range ID. */
1307 uint8_t idSavedState;
1308 /** Alignment padding. */
1309 uint8_t au8Alignment[3];
1310 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1311 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1312 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1313 * This is used for strictness checks. */
1314 R3PTRTYPE(const void *) pvOriginal;
1315 /** The ROM description. */
1316 R3PTRTYPE(const char *) pszDesc;
1317 /** The per page tracking structures. */
1318 PGMROMPAGE aPages[1];
1319} PGMROMRANGE;
1320/** Pointer to a ROM range. */
1321typedef PGMROMRANGE *PPGMROMRANGE;
1322
1323
1324/**
1325 * Live save per page data for an MMIO2 page.
1326 *
1327 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1328 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1329 * CRC-32 for detecting changes as well as special handling of zero pages. This
1330 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1331 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1332 * because of speed (2.5x and 6x slower).)
1333 *
1334 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1335 * save but normally is disabled. Since we can write monitore guest
1336 * accesses on our own, we only need this for host accesses. Shouldn't be
1337 * too difficult for DevVGA, VMMDev might be doable, the planned
1338 * networking fun will be fun since it involves ring-0.
1339 */
1340typedef struct PGMLIVESAVEMMIO2PAGE
1341{
1342 /** Set if the page is considered dirty. */
1343 bool fDirty;
1344 /** The number of scans this page has remained unchanged for.
1345 * Only updated for dirty pages. */
1346 uint8_t cUnchangedScans;
1347 /** Whether this page was zero at the last scan. */
1348 bool fZero;
1349 /** Alignment padding. */
1350 bool fReserved;
1351 /** CRC-32 for the first half of the page.
1352 * This is used together with u32CrcH2 to quickly detect changes in the page
1353 * during the non-final passes. */
1354 uint32_t u32CrcH1;
1355 /** CRC-32 for the second half of the page. */
1356 uint32_t u32CrcH2;
1357 /** SHA-1 for the saved page.
1358 * This is used in the final pass to skip pages without changes. */
1359 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1360} PGMLIVESAVEMMIO2PAGE;
1361/** Pointer to a live save status data for an MMIO2 page. */
1362typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1363
1364/**
1365 * A registered MMIO2 (= Device RAM) range.
1366 *
1367 * There are a few reason why we need to keep track of these
1368 * registrations. One of them is the deregistration & cleanup stuff,
1369 * while another is that the PGMRAMRANGE associated with such a region may
1370 * have to be removed from the ram range list.
1371 *
1372 * Overlapping with a RAM range has to be 100% or none at all. The pages
1373 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1374 * will be raised if a partial overlap or an overlap of ROM pages is
1375 * encountered. On an overlap we will free all the existing RAM pages and
1376 * put in the ram range pages instead.
1377 */
1378typedef struct PGMMMIO2RANGE
1379{
1380 /** The owner of the range. (a device) */
1381 PPDMDEVINSR3 pDevInsR3;
1382 /** Pointer to the ring-3 mapping of the allocation. */
1383 RTR3PTR pvR3;
1384 /** Pointer to the next range - R3. */
1385 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1386 /** Whether it's mapped or not. */
1387 bool fMapped;
1388 /** Whether it's overlapping or not. */
1389 bool fOverlapping;
1390 /** The PCI region number.
1391 * @remarks This ASSUMES that nobody will ever really need to have multiple
1392 * PCI devices with matching MMIO region numbers on a single device. */
1393 uint8_t iRegion;
1394 /** The saved state range ID. */
1395 uint8_t idSavedState;
1396 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1397 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1398 /** Live save per page tracking data. */
1399 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1400 /** The associated RAM range. */
1401 PGMRAMRANGE RamRange;
1402} PGMMMIO2RANGE;
1403/** Pointer to a MMIO2 range. */
1404typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1405
1406
1407
1408
1409/**
1410 * PGMPhysRead/Write cache entry
1411 */
1412typedef struct PGMPHYSCACHEENTRY
1413{
1414 /** R3 pointer to physical page. */
1415 R3PTRTYPE(uint8_t *) pbR3;
1416 /** GC Physical address for cache entry */
1417 RTGCPHYS GCPhys;
1418#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1419 RTGCPHYS u32Padding0; /**< alignment padding. */
1420#endif
1421} PGMPHYSCACHEENTRY;
1422
1423/**
1424 * PGMPhysRead/Write cache to reduce REM memory access overhead
1425 */
1426typedef struct PGMPHYSCACHE
1427{
1428 /** Bitmap of valid cache entries */
1429 uint64_t aEntries;
1430 /** Cache entries */
1431 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1432} PGMPHYSCACHE;
1433
1434
1435/** Pointer to an allocation chunk ring-3 mapping. */
1436typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1437/** Pointer to an allocation chunk ring-3 mapping pointer. */
1438typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1439
1440/**
1441 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1442 *
1443 * The primary tree (Core) uses the chunk id as key.
1444 */
1445typedef struct PGMCHUNKR3MAP
1446{
1447 /** The key is the chunk id. */
1448 AVLU32NODECORE Core;
1449 /** The current age thingy. */
1450 uint32_t iAge;
1451 /** The current reference count. */
1452 uint32_t volatile cRefs;
1453 /** The current permanent reference count. */
1454 uint32_t volatile cPermRefs;
1455 /** The mapping address. */
1456 void *pv;
1457} PGMCHUNKR3MAP;
1458
1459/**
1460 * Allocation chunk ring-3 mapping TLB entry.
1461 */
1462typedef struct PGMCHUNKR3MAPTLBE
1463{
1464 /** The chunk id. */
1465 uint32_t volatile idChunk;
1466#if HC_ARCH_BITS == 64
1467 uint32_t u32Padding; /**< alignment padding. */
1468#endif
1469 /** The chunk map. */
1470#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1471 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1472#else
1473 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1474#endif
1475} PGMCHUNKR3MAPTLBE;
1476/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1477typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1478
1479/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1480 * @remark Must be a power of two value. */
1481#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1482
1483/**
1484 * Allocation chunk ring-3 mapping TLB.
1485 *
1486 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1487 * At first glance this might look kinda odd since AVL trees are
1488 * supposed to give the most optimial lookup times of all trees
1489 * due to their balancing. However, take a tree with 1023 nodes
1490 * in it, that's 10 levels, meaning that most searches has to go
1491 * down 9 levels before they find what they want. This isn't fast
1492 * compared to a TLB hit. There is the factor of cache misses,
1493 * and of course the problem with trees and branch prediction.
1494 * This is why we use TLBs in front of most of the trees.
1495 *
1496 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1497 * difficult when we switch to the new inlined AVL trees (from kStuff).
1498 */
1499typedef struct PGMCHUNKR3MAPTLB
1500{
1501 /** The TLB entries. */
1502 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1503} PGMCHUNKR3MAPTLB;
1504
1505/**
1506 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1507 * @returns Chunk TLB index.
1508 * @param idChunk The Chunk ID.
1509 */
1510#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1511
1512
1513/**
1514 * Ring-3 guest page mapping TLB entry.
1515 * @remarks used in ring-0 as well at the moment.
1516 */
1517typedef struct PGMPAGER3MAPTLBE
1518{
1519 /** Address of the page. */
1520 RTGCPHYS volatile GCPhys;
1521 /** The guest page. */
1522#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1523 R3PTRTYPE(PPGMPAGE) volatile pPage;
1524#else
1525 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1526#endif
1527 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1528#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1529 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1530#else
1531 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1532#endif
1533 /** The address */
1534#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1535 R3PTRTYPE(void *) volatile pv;
1536#else
1537 R3R0PTRTYPE(void *) volatile pv;
1538#endif
1539#if HC_ARCH_BITS == 32
1540 uint32_t u32Padding; /**< alignment padding. */
1541#endif
1542} PGMPAGER3MAPTLBE;
1543/** Pointer to an entry in the HC physical TLB. */
1544typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1545
1546
1547/** The number of entries in the ring-3 guest page mapping TLB.
1548 * @remarks The value must be a power of two. */
1549#define PGM_PAGER3MAPTLB_ENTRIES 256
1550
1551/**
1552 * Ring-3 guest page mapping TLB.
1553 * @remarks used in ring-0 as well at the moment.
1554 */
1555typedef struct PGMPAGER3MAPTLB
1556{
1557 /** The TLB entries. */
1558 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1559} PGMPAGER3MAPTLB;
1560/** Pointer to the ring-3 guest page mapping TLB. */
1561typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1562
1563/**
1564 * Calculates the index of the TLB entry for the specified guest page.
1565 * @returns Physical TLB index.
1566 * @param GCPhys The guest physical address.
1567 */
1568#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1569
1570
1571/**
1572 * Raw-mode context dynamic mapping cache entry.
1573 *
1574 * Because of raw-mode context being reloctable and all relocations are applied
1575 * in ring-3, this has to be defined here and be RC specfic.
1576 *
1577 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1578 */
1579typedef struct PGMRCDYNMAPENTRY
1580{
1581 /** The physical address of the currently mapped page.
1582 * This is duplicate for three reasons: cache locality, cache policy of the PT
1583 * mappings and sanity checks. */
1584 RTHCPHYS HCPhys;
1585 /** Pointer to the page. */
1586 RTRCPTR pvPage;
1587 /** The number of references. */
1588 int32_t volatile cRefs;
1589 /** PTE pointer union. */
1590 union PGMRCDYNMAPENTRY_PPTE
1591 {
1592 /** PTE pointer, 32-bit legacy version. */
1593 RCPTRTYPE(PX86PTE) pLegacy;
1594 /** PTE pointer, PAE version. */
1595 RCPTRTYPE(PX86PTEPAE) pPae;
1596 /** PTE pointer, the void version. */
1597 RTRCPTR pv;
1598 } uPte;
1599 /** Alignment padding. */
1600 RTRCPTR RCPtrAlignment;
1601} PGMRCDYNMAPENTRY;
1602/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1603typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1604
1605
1606/**
1607 * Dynamic mapping cache for the raw-mode context.
1608 *
1609 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1610 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1611 * so that we can perform relocations from PGMR3Relocate. This has the
1612 * consequence that we must have separate ring-0 and raw-mode context versions
1613 * of this struct even if they share the basic elements.
1614 *
1615 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1616 */
1617typedef struct PGMRCDYNMAP
1618{
1619 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1620 uint32_t u32Magic;
1621 /** Array for tracking and managing the pages. */
1622 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1623 /** The cache size given as a number of pages. */
1624 uint32_t cPages;
1625 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1626 bool fLegacyMode;
1627 /** The current load.
1628 * This does not include guard pages. */
1629 uint32_t cLoad;
1630 /** The max load ever.
1631 * This is maintained to get trigger adding of more mapping space. */
1632 uint32_t cMaxLoad;
1633 /** The number of guard pages. */
1634 uint32_t cGuardPages;
1635 /** The number of users (protected by hInitLock). */
1636 uint32_t cUsers;
1637} PGMRCDYNMAP;
1638/** Pointer to the dynamic cache for the raw-mode context. */
1639typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1640
1641
1642/**
1643 * Mapping cache usage set entry.
1644 *
1645 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1646 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1647 * cache. If it's extended to include ring-3, well, then something
1648 * will have be changed here...
1649 */
1650typedef struct PGMMAPSETENTRY
1651{
1652 /** Pointer to the page. */
1653#ifndef IN_RC
1654 RTR0PTR pvPage;
1655#else
1656 RTRCPTR pvPage;
1657# if HC_ARCH_BITS == 64
1658 uint32_t u32Alignment2;
1659# endif
1660#endif
1661 /** The mapping cache index. */
1662 uint16_t iPage;
1663 /** The number of references.
1664 * The max is UINT16_MAX - 1. */
1665 uint16_t cRefs;
1666 /** The number inlined references.
1667 * The max is UINT16_MAX - 1. */
1668 uint16_t cInlinedRefs;
1669 /** Unreferences. */
1670 uint16_t cUnrefs;
1671
1672#if HC_ARCH_BITS == 32
1673 uint32_t u32Alignment1;
1674#endif
1675 /** The physical address for this entry. */
1676 RTHCPHYS HCPhys;
1677} PGMMAPSETENTRY;
1678AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1679AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1680/** Pointer to a mapping cache usage set entry. */
1681typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1682
1683/**
1684 * Mapping cache usage set.
1685 *
1686 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1687 * done during exits / traps. The set is
1688 */
1689typedef struct PGMMAPSET
1690{
1691 /** The number of occupied entries.
1692 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1693 * dynamic mappings. */
1694 uint32_t cEntries;
1695 /** The start of the current subset.
1696 * This is UINT32_MAX if no subset is currently open. */
1697 uint32_t iSubset;
1698 /** The index of the current CPU, only valid if the set is open. */
1699 int32_t iCpu;
1700 uint32_t alignment;
1701 /** The entries. */
1702 PGMMAPSETENTRY aEntries[64];
1703 /** HCPhys -> iEntry fast lookup table.
1704 * Use PGMMAPSET_HASH for hashing.
1705 * The entries may or may not be valid, check against cEntries. */
1706 uint8_t aiHashTable[128];
1707} PGMMAPSET;
1708AssertCompileSizeAlignment(PGMMAPSET, 8);
1709/** Pointer to the mapping cache set. */
1710typedef PGMMAPSET *PPGMMAPSET;
1711
1712/** PGMMAPSET::cEntries value for a closed set. */
1713#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1714
1715/** Hash function for aiHashTable. */
1716#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1717
1718/** The max fill size (strict builds). */
1719#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1720
1721
1722/** @name Context neutrual page mapper TLB.
1723 *
1724 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1725 * code is writting in a kind of context neutrual way. Time will show whether
1726 * this actually makes sense or not...
1727 *
1728 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1729 * context ends up using a global mapping cache on some platforms
1730 * (darwin).
1731 *
1732 * @{ */
1733/** @typedef PPGMPAGEMAPTLB
1734 * The page mapper TLB pointer type for the current context. */
1735/** @typedef PPGMPAGEMAPTLB
1736 * The page mapper TLB entry pointer type for the current context. */
1737/** @typedef PPGMPAGEMAPTLB
1738 * The page mapper TLB entry pointer pointer type for the current context. */
1739/** @def PGM_PAGEMAPTLB_ENTRIES
1740 * The number of TLB entries in the page mapper TLB for the current context. */
1741/** @def PGM_PAGEMAPTLB_IDX
1742 * Calculate the TLB index for a guest physical address.
1743 * @returns The TLB index.
1744 * @param GCPhys The guest physical address. */
1745/** @typedef PPGMPAGEMAP
1746 * Pointer to a page mapper unit for current context. */
1747/** @typedef PPPGMPAGEMAP
1748 * Pointer to a page mapper unit pointer for current context. */
1749#ifdef IN_RC
1750// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1751// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1752// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1753# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1754# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1755 typedef void * PPGMPAGEMAP;
1756 typedef void ** PPPGMPAGEMAP;
1757//#elif IN_RING0
1758// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1759// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1760// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1761//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1762//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1763// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1764// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1765#else
1766 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1767 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1768 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1769# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1770# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1771 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1772 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1773#endif
1774/** @} */
1775
1776
1777/** @name PGM Pool Indexes.
1778 * Aka. the unique shadow page identifier.
1779 * @{ */
1780/** NIL page pool IDX. */
1781#define NIL_PGMPOOL_IDX 0
1782/** The first normal index. */
1783#define PGMPOOL_IDX_FIRST_SPECIAL 1
1784/** Page directory (32-bit root). */
1785#define PGMPOOL_IDX_PD 1
1786/** Page Directory Pointer Table (PAE root). */
1787#define PGMPOOL_IDX_PDPT 2
1788/** AMD64 CR3 level index.*/
1789#define PGMPOOL_IDX_AMD64_CR3 3
1790/** Nested paging root.*/
1791#define PGMPOOL_IDX_NESTED_ROOT 4
1792/** The first normal index. */
1793#define PGMPOOL_IDX_FIRST 5
1794/** The last valid index. (inclusive, 14 bits) */
1795#define PGMPOOL_IDX_LAST 0x3fff
1796/** @} */
1797
1798/** The NIL index for the parent chain. */
1799#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1800#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1801
1802/**
1803 * Node in the chain linking a shadowed page to it's parent (user).
1804 */
1805#pragma pack(1)
1806typedef struct PGMPOOLUSER
1807{
1808 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1809 uint16_t iNext;
1810 /** The user page index. */
1811 uint16_t iUser;
1812 /** Index into the user table. */
1813 uint32_t iUserTable;
1814} PGMPOOLUSER, *PPGMPOOLUSER;
1815typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1816#pragma pack()
1817
1818
1819/** The NIL index for the phys ext chain. */
1820#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1821/** The NIL pte index for a phys ext chain slot. */
1822#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1823
1824/**
1825 * Node in the chain of physical cross reference extents.
1826 * @todo Calling this an 'extent' is not quite right, find a better name.
1827 * @todo find out the optimal size of the aidx array
1828 */
1829#pragma pack(1)
1830typedef struct PGMPOOLPHYSEXT
1831{
1832 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1833 uint16_t iNext;
1834 /** Alignment. */
1835 uint16_t u16Align;
1836 /** The user page index. */
1837 uint16_t aidx[3];
1838 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1839 uint16_t apte[3];
1840} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1841typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1842#pragma pack()
1843
1844
1845/**
1846 * The kind of page that's being shadowed.
1847 */
1848typedef enum PGMPOOLKIND
1849{
1850 /** The virtual invalid 0 entry. */
1851 PGMPOOLKIND_INVALID = 0,
1852 /** The entry is free (=unused). */
1853 PGMPOOLKIND_FREE,
1854
1855 /** Shw: 32-bit page table; Gst: no paging */
1856 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1857 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1858 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1859 /** Shw: 32-bit page table; Gst: 4MB page. */
1860 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1861 /** Shw: PAE page table; Gst: no paging */
1862 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1863 /** Shw: PAE page table; Gst: 32-bit page table. */
1864 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1865 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1866 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1867 /** Shw: PAE page table; Gst: PAE page table. */
1868 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1869 /** Shw: PAE page table; Gst: 2MB page. */
1870 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1871
1872 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1873 PGMPOOLKIND_32BIT_PD,
1874 /** Shw: 32-bit page directory. Gst: no paging. */
1875 PGMPOOLKIND_32BIT_PD_PHYS,
1876 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1877 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1878 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1879 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1880 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1881 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1882 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1883 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1884 /** Shw: PAE page directory; Gst: PAE page directory. */
1885 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1886 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1887 PGMPOOLKIND_PAE_PD_PHYS,
1888
1889 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1890 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1891 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1892 PGMPOOLKIND_PAE_PDPT,
1893 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1894 PGMPOOLKIND_PAE_PDPT_PHYS,
1895
1896 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1897 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1898 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1899 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1900 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1901 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1902 /** Shw: 64-bit page directory table; Gst: no paging */
1903 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1904
1905 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1906 PGMPOOLKIND_64BIT_PML4,
1907
1908 /** Shw: EPT page directory pointer table; Gst: no paging */
1909 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1910 /** Shw: EPT page directory table; Gst: no paging */
1911 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1912 /** Shw: EPT page table; Gst: no paging */
1913 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1914
1915 /** Shw: Root Nested paging table. */
1916 PGMPOOLKIND_ROOT_NESTED,
1917
1918 /** The last valid entry. */
1919 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1920} PGMPOOLKIND;
1921
1922/**
1923 * The access attributes of the page; only applies to big pages.
1924 */
1925typedef enum
1926{
1927 PGMPOOLACCESS_DONTCARE = 0,
1928 PGMPOOLACCESS_USER_RW,
1929 PGMPOOLACCESS_USER_R,
1930 PGMPOOLACCESS_USER_RW_NX,
1931 PGMPOOLACCESS_USER_R_NX,
1932 PGMPOOLACCESS_SUPERVISOR_RW,
1933 PGMPOOLACCESS_SUPERVISOR_R,
1934 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1935 PGMPOOLACCESS_SUPERVISOR_R_NX
1936} PGMPOOLACCESS;
1937
1938/**
1939 * The tracking data for a page in the pool.
1940 */
1941typedef struct PGMPOOLPAGE
1942{
1943 /** AVL node code with the (R3) physical address of this page. */
1944 AVLOHCPHYSNODECORE Core;
1945 /** Pointer to the R3 mapping of the page. */
1946#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1947 R3PTRTYPE(void *) pvPageR3;
1948#else
1949 R3R0PTRTYPE(void *) pvPageR3;
1950#endif
1951 /** The guest physical address. */
1952#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1953 uint32_t Alignment0;
1954#endif
1955 RTGCPHYS GCPhys;
1956
1957 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1958 RTGCPTR pvLastAccessHandlerRip;
1959 RTGCPTR pvLastAccessHandlerFault;
1960 uint64_t cLastAccessHandlerCount;
1961
1962 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1963 uint8_t enmKind;
1964 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1965 uint8_t enmAccess;
1966 /** The index of this page. */
1967 uint16_t idx;
1968 /** The next entry in the list this page currently resides in.
1969 * It's either in the free list or in the GCPhys hash. */
1970 uint16_t iNext;
1971 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1972 uint16_t iUserHead;
1973 /** The number of present entries. */
1974 uint16_t cPresent;
1975 /** The first entry in the table which is present. */
1976 uint16_t iFirstPresent;
1977 /** The number of modifications to the monitored page. */
1978 uint16_t cModifications;
1979 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1980 uint16_t iModifiedNext;
1981 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1982 uint16_t iModifiedPrev;
1983 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1984 uint16_t iMonitoredNext;
1985 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1986 uint16_t iMonitoredPrev;
1987 /** The next page in the age list. */
1988 uint16_t iAgeNext;
1989 /** The previous page in the age list. */
1990 uint16_t iAgePrev;
1991 /** Used to indicate that the page is zeroed. */
1992 bool fZeroed;
1993 /** Used to indicate that a PT has non-global entries. */
1994 bool fSeenNonGlobal;
1995 /** Used to indicate that we're monitoring writes to the guest page. */
1996 bool fMonitored;
1997 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1998 * (All pages are in the age list.) */
1999 bool fCached;
2000 /** This is used by the R3 access handlers when invoked by an async thread.
2001 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2002 bool volatile fReusedFlushPending;
2003 /** Used to mark the page as dirty (write monitoring is temporarily
2004 * off). */
2005 bool fDirty;
2006
2007 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2008 uint32_t cLocked;
2009 uint32_t idxDirty;
2010 RTGCPTR pvDirtyFault;
2011} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2012/** Pointer to a const pool page. */
2013typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2014
2015
2016/** The hash table size. */
2017# define PGMPOOL_HASH_SIZE 0x40
2018/** The hash function. */
2019# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2020
2021
2022/**
2023 * The shadow page pool instance data.
2024 *
2025 * It's all one big allocation made at init time, except for the
2026 * pages that is. The user nodes follows immediatly after the
2027 * page structures.
2028 */
2029typedef struct PGMPOOL
2030{
2031 /** The VM handle - R3 Ptr. */
2032 PVMR3 pVMR3;
2033 /** The VM handle - R0 Ptr. */
2034 PVMR0 pVMR0;
2035 /** The VM handle - RC Ptr. */
2036 PVMRC pVMRC;
2037 /** The max pool size. This includes the special IDs. */
2038 uint16_t cMaxPages;
2039 /** The current pool size. */
2040 uint16_t cCurPages;
2041 /** The head of the free page list. */
2042 uint16_t iFreeHead;
2043 /* Padding. */
2044 uint16_t u16Padding;
2045 /** Head of the chain of free user nodes. */
2046 uint16_t iUserFreeHead;
2047 /** The number of user nodes we've allocated. */
2048 uint16_t cMaxUsers;
2049 /** The number of present page table entries in the entire pool. */
2050 uint32_t cPresent;
2051 /** Pointer to the array of user nodes - RC pointer. */
2052 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2053 /** Pointer to the array of user nodes - R3 pointer. */
2054 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2055 /** Pointer to the array of user nodes - R0 pointer. */
2056 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2057 /** Head of the chain of free phys ext nodes. */
2058 uint16_t iPhysExtFreeHead;
2059 /** The number of user nodes we've allocated. */
2060 uint16_t cMaxPhysExts;
2061 /** Pointer to the array of physical xref extent - RC pointer. */
2062 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2063 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2064 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2065 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2066 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2067 /** Hash table for GCPhys addresses. */
2068 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2069 /** The head of the age list. */
2070 uint16_t iAgeHead;
2071 /** The tail of the age list. */
2072 uint16_t iAgeTail;
2073 /** Set if the cache is enabled. */
2074 bool fCacheEnabled;
2075 /** Alignment padding. */
2076 bool afPadding1[3];
2077 /** Head of the list of modified pages. */
2078 uint16_t iModifiedHead;
2079 /** The current number of modified pages. */
2080 uint16_t cModifiedPages;
2081 /** Access handler, RC. */
2082 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2083 /** Access handler, R0. */
2084 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2085 /** Access handler, R3. */
2086 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2087 /** The access handler description (R3 ptr). */
2088 R3PTRTYPE(const char *) pszAccessHandler;
2089# if HC_ARCH_BITS == 32
2090 /** Alignment padding. */
2091 uint32_t u32Padding2;
2092# endif
2093 /* Next available slot. */
2094 uint32_t idxFreeDirtyPage;
2095 /* Number of active dirty pages. */
2096 uint32_t cDirtyPages;
2097 /* Array of current dirty pgm pool page indices. */
2098 uint16_t aIdxDirtyPages[16];
2099 uint64_t aDirtyPages[16][512];
2100 /** The number of pages currently in use. */
2101 uint16_t cUsedPages;
2102#ifdef VBOX_WITH_STATISTICS
2103 /** The high water mark for cUsedPages. */
2104 uint16_t cUsedPagesHigh;
2105 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2106 /** Profiling pgmPoolAlloc(). */
2107 STAMPROFILEADV StatAlloc;
2108 /** Profiling pgmR3PoolClearDoIt(). */
2109 STAMPROFILE StatClearAll;
2110 /** Profiling pgmR3PoolReset(). */
2111 STAMPROFILE StatR3Reset;
2112 /** Profiling pgmPoolFlushPage(). */
2113 STAMPROFILE StatFlushPage;
2114 /** Profiling pgmPoolFree(). */
2115 STAMPROFILE StatFree;
2116 /** Counting explicit flushes by PGMPoolFlushPage(). */
2117 STAMCOUNTER StatForceFlushPage;
2118 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2119 STAMCOUNTER StatForceFlushDirtyPage;
2120 /** Counting flushes for reused pages. */
2121 STAMCOUNTER StatForceFlushReused;
2122 /** Profiling time spent zeroing pages. */
2123 STAMPROFILE StatZeroPage;
2124 /** Profiling of pgmPoolTrackDeref. */
2125 STAMPROFILE StatTrackDeref;
2126 /** Profiling pgmTrackFlushGCPhysPT. */
2127 STAMPROFILE StatTrackFlushGCPhysPT;
2128 /** Profiling pgmTrackFlushGCPhysPTs. */
2129 STAMPROFILE StatTrackFlushGCPhysPTs;
2130 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2131 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2132 /** Number of times we've been out of user records. */
2133 STAMCOUNTER StatTrackFreeUpOneUser;
2134 /** Nr of flushed entries. */
2135 STAMCOUNTER StatTrackFlushEntry;
2136 /** Nr of updated entries. */
2137 STAMCOUNTER StatTrackFlushEntryKeep;
2138 /** Profiling deref activity related tracking GC physical pages. */
2139 STAMPROFILE StatTrackDerefGCPhys;
2140 /** Number of linear searches for a HCPhys in the ram ranges. */
2141 STAMCOUNTER StatTrackLinearRamSearches;
2142 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2143 STAMCOUNTER StamTrackPhysExtAllocFailures;
2144 /** Profiling the RC/R0 access handler. */
2145 STAMPROFILE StatMonitorRZ;
2146 /** Times we've failed interpreting the instruction. */
2147 STAMCOUNTER StatMonitorRZEmulateInstr;
2148 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2149 STAMPROFILE StatMonitorRZFlushPage;
2150 /* Times we've detected a page table reinit. */
2151 STAMCOUNTER StatMonitorRZFlushReinit;
2152 /** Counting flushes for pages that are modified too often. */
2153 STAMCOUNTER StatMonitorRZFlushModOverflow;
2154 /** Times we've detected fork(). */
2155 STAMCOUNTER StatMonitorRZFork;
2156 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2157 STAMPROFILE StatMonitorRZHandled;
2158 /** Times we've failed interpreting a patch code instruction. */
2159 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2160 /** Times we've failed interpreting a patch code instruction during flushing. */
2161 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2162 /** The number of times we've seen rep prefixes we can't handle. */
2163 STAMCOUNTER StatMonitorRZRepPrefix;
2164 /** Profiling the REP STOSD cases we've handled. */
2165 STAMPROFILE StatMonitorRZRepStosd;
2166 /** Nr of handled PT faults. */
2167 STAMCOUNTER StatMonitorRZFaultPT;
2168 /** Nr of handled PD faults. */
2169 STAMCOUNTER StatMonitorRZFaultPD;
2170 /** Nr of handled PDPT faults. */
2171 STAMCOUNTER StatMonitorRZFaultPDPT;
2172 /** Nr of handled PML4 faults. */
2173 STAMCOUNTER StatMonitorRZFaultPML4;
2174
2175 /** Profiling the R3 access handler. */
2176 STAMPROFILE StatMonitorR3;
2177 /** Times we've failed interpreting the instruction. */
2178 STAMCOUNTER StatMonitorR3EmulateInstr;
2179 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2180 STAMPROFILE StatMonitorR3FlushPage;
2181 /* Times we've detected a page table reinit. */
2182 STAMCOUNTER StatMonitorR3FlushReinit;
2183 /** Counting flushes for pages that are modified too often. */
2184 STAMCOUNTER StatMonitorR3FlushModOverflow;
2185 /** Times we've detected fork(). */
2186 STAMCOUNTER StatMonitorR3Fork;
2187 /** Profiling the R3 access we've handled (except REP STOSD). */
2188 STAMPROFILE StatMonitorR3Handled;
2189 /** The number of times we've seen rep prefixes we can't handle. */
2190 STAMCOUNTER StatMonitorR3RepPrefix;
2191 /** Profiling the REP STOSD cases we've handled. */
2192 STAMPROFILE StatMonitorR3RepStosd;
2193 /** Nr of handled PT faults. */
2194 STAMCOUNTER StatMonitorR3FaultPT;
2195 /** Nr of handled PD faults. */
2196 STAMCOUNTER StatMonitorR3FaultPD;
2197 /** Nr of handled PDPT faults. */
2198 STAMCOUNTER StatMonitorR3FaultPDPT;
2199 /** Nr of handled PML4 faults. */
2200 STAMCOUNTER StatMonitorR3FaultPML4;
2201 /** The number of times we're called in an async thread an need to flush. */
2202 STAMCOUNTER StatMonitorR3Async;
2203 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2204 STAMCOUNTER StatResetDirtyPages;
2205 /** Times we've called pgmPoolAddDirtyPage. */
2206 STAMCOUNTER StatDirtyPage;
2207 /** Times we've had to flush duplicates for dirty page management. */
2208 STAMCOUNTER StatDirtyPageDupFlush;
2209 /** Times we've had to flush because of overflow. */
2210 STAMCOUNTER StatDirtyPageOverFlowFlush;
2211
2212 /** The high wather mark for cModifiedPages. */
2213 uint16_t cModifiedPagesHigh;
2214 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2215
2216 /** The number of cache hits. */
2217 STAMCOUNTER StatCacheHits;
2218 /** The number of cache misses. */
2219 STAMCOUNTER StatCacheMisses;
2220 /** The number of times we've got a conflict of 'kind' in the cache. */
2221 STAMCOUNTER StatCacheKindMismatches;
2222 /** Number of times we've been out of pages. */
2223 STAMCOUNTER StatCacheFreeUpOne;
2224 /** The number of cacheable allocations. */
2225 STAMCOUNTER StatCacheCacheable;
2226 /** The number of uncacheable allocations. */
2227 STAMCOUNTER StatCacheUncacheable;
2228#else
2229 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2230#endif
2231 /** The AVL tree for looking up a page by its HC physical address. */
2232 AVLOHCPHYSTREE HCPhysTree;
2233 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2234 /** Array of pages. (cMaxPages in length)
2235 * The Id is the index into thist array.
2236 */
2237 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2238} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2239AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2240AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2241AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2242#ifdef VBOX_WITH_STATISTICS
2243AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2244#endif
2245AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2246
2247
2248/** @def PGMPOOL_PAGE_2_PTR
2249 * Maps a pool page pool into the current context.
2250 *
2251 * @returns VBox status code.
2252 * @param pVM The VM handle.
2253 * @param pPage The pool page.
2254 *
2255 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2256 * small page window employeed by that function. Be careful.
2257 * @remark There is no need to assert on the result.
2258 */
2259#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2260# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2261#elif defined(VBOX_STRICT)
2262# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2263DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2264{
2265 Assert(pPage && pPage->pvPageR3);
2266 return pPage->pvPageR3;
2267}
2268#else
2269# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2270#endif
2271
2272
2273/** @def PGMPOOL_PAGE_2_PTR_V2
2274 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2275 *
2276 * @returns VBox status code.
2277 * @param pVM The VM handle.
2278 * @param pVCpu The current CPU.
2279 * @param pPage The pool page.
2280 *
2281 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2282 * small page window employeed by that function. Be careful.
2283 * @remark There is no need to assert on the result.
2284 */
2285#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2286# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2287#else
2288# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2289#endif
2290
2291
2292/** @name Per guest page tracking data.
2293 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2294 * is to use more bits for it and split it up later on. But for now we'll play
2295 * safe and change as little as possible.
2296 *
2297 * The 16-bit word has two parts:
2298 *
2299 * The first 14-bit forms the @a idx field. It is either the index of a page in
2300 * the shadow page pool, or and index into the extent list.
2301 *
2302 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2303 * shadow page pool references to the page. If cRefs equals
2304 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2305 * (misnomer) table and not the shadow page pool.
2306 *
2307 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2308 * the 16-bit word.
2309 *
2310 * @{ */
2311/** The shift count for getting to the cRefs part. */
2312#define PGMPOOL_TD_CREFS_SHIFT 14
2313/** The mask applied after shifting the tracking data down by
2314 * PGMPOOL_TD_CREFS_SHIFT. */
2315#define PGMPOOL_TD_CREFS_MASK 0x3
2316/** The cRef value used to indiciate that the idx is the head of a
2317 * physical cross reference list. */
2318#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2319/** The shift used to get idx. */
2320#define PGMPOOL_TD_IDX_SHIFT 0
2321/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2322#define PGMPOOL_TD_IDX_MASK 0x3fff
2323/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2324 * simply too many mappings of this page. */
2325#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2326
2327/** @def PGMPOOL_TD_MAKE
2328 * Makes a 16-bit tracking data word.
2329 *
2330 * @returns tracking data.
2331 * @param cRefs The @a cRefs field. Must be within bounds!
2332 * @param idx The @a idx field. Must also be within bounds! */
2333#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2334
2335/** @def PGMPOOL_TD_GET_CREFS
2336 * Get the @a cRefs field from a tracking data word.
2337 *
2338 * @returns The @a cRefs field
2339 * @param u16 The tracking data word. */
2340#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2341
2342/** @def PGMPOOL_TD_GET_IDX
2343 * Get the @a idx field from a tracking data word.
2344 *
2345 * @returns The @a idx field
2346 * @param u16 The tracking data word. */
2347#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2348/** @} */
2349
2350
2351/**
2352 * Trees are using self relative offsets as pointers.
2353 * So, all its data, including the root pointer, must be in the heap for HC and GC
2354 * to have the same layout.
2355 */
2356typedef struct PGMTREES
2357{
2358 /** Physical access handlers (AVL range+offsetptr tree). */
2359 AVLROGCPHYSTREE PhysHandlers;
2360 /** Virtual access handlers (AVL range + GC ptr tree). */
2361 AVLROGCPTRTREE VirtHandlers;
2362 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2363 AVLROGCPHYSTREE PhysToVirtHandlers;
2364 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2365 AVLROGCPTRTREE HyperVirtHandlers;
2366} PGMTREES;
2367/** Pointer to PGM trees. */
2368typedef PGMTREES *PPGMTREES;
2369
2370
2371/**
2372 * Page fault guest state for the AMD64 paging mode.
2373 */
2374typedef struct PGMPTWALKCORE
2375{
2376 /** The guest virtual address that is being resolved by the walk
2377 * (input). */
2378 RTGCPTR GCPtr;
2379
2380 /** The guest physcial address that is the result of the walk.
2381 * @remarks only valid if fSucceeded is set. */
2382 RTGCPHYS GCPhys;
2383
2384 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2385 bool fSucceeded;
2386 /** The level problem arrised at.
2387 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2388 * level 8. This is 0 on success. */
2389 uint8_t uLevel;
2390 /** Set if the page isn't present. */
2391 bool fNotPresent;
2392 /** Encountered a bad physical address. */
2393 bool fBadPhysAddr;
2394 /** Set if there was reserved bit violations. */
2395 bool fRsvdError;
2396 /** Set if it involves a big page (2/4 MB). */
2397 bool fBigPage;
2398 /** Set if it involves a gigantic page (1 GB). */
2399 bool fGigantPage;
2400 /** The effect X86_PTE_US flag for the address. */
2401 bool fEffectiveUS;
2402 /** The effect X86_PTE_RW flag for the address. */
2403 bool fEffectiveRW;
2404 /** The effect X86_PTE_NX flag for the address. */
2405 bool fEffectiveNX;
2406} PGMPTWALKCORE;
2407
2408
2409/**
2410 * Guest page table walk for the AMD64 mode.
2411 */
2412typedef struct PGMPTWALKGSTAMD64
2413{
2414 /** The common core. */
2415 PGMPTWALKCORE Core;
2416
2417 PX86PML4 pPml4;
2418 PX86PML4E pPml4e;
2419 X86PML4E Pml4e;
2420
2421 PX86PDPT pPdpt;
2422 PX86PDPE pPdpe;
2423 X86PDPE Pdpe;
2424
2425 PX86PDPAE pPd;
2426 PX86PDEPAE pPde;
2427 X86PDEPAE Pde;
2428
2429 PX86PTPAE pPt;
2430 PX86PTEPAE pPte;
2431 X86PTEPAE Pte;
2432} PGMPTWALKGSTAMD64;
2433/** Pointer to a AMD64 guest page table walk. */
2434typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2435/** Pointer to a const AMD64 guest page table walk. */
2436typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2437
2438/**
2439 * Guest page table walk for the PAE mode.
2440 */
2441typedef struct PGMPTWALKGSTPAE
2442{
2443 /** The common core. */
2444 PGMPTWALKCORE Core;
2445
2446 PX86PDPT pPdpt;
2447 PX86PDPE pPdpe;
2448 X86PDPE Pdpe;
2449
2450 PX86PDPAE pPd;
2451 PX86PDEPAE pPde;
2452 X86PDEPAE Pde;
2453
2454 PX86PTPAE pPt;
2455 PX86PTEPAE pPte;
2456 X86PTEPAE Pte;
2457} PGMPTWALKGSTPAE;
2458/** Pointer to a PAE guest page table walk. */
2459typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2460/** Pointer to a const AMD64 guest page table walk. */
2461typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2462
2463/**
2464 * Guest page table walk for the 32-bit mode.
2465 */
2466typedef struct PGMPTWALKGST32BIT
2467{
2468 /** The common core. */
2469 PGMPTWALKCORE Core;
2470
2471 PX86PD pPd;
2472 PX86PDE pPde;
2473 X86PDE Pde;
2474
2475 PX86PT pPt;
2476 PX86PTE pPte;
2477 X86PTE Pte;
2478} PGMPTWALKGST32BIT;
2479/** Pointer to a 32-bit guest page table walk. */
2480typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2481/** Pointer to a const 32-bit guest page table walk. */
2482typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2483
2484
2485/** @name Paging mode macros
2486 * @{
2487 */
2488#ifdef IN_RC
2489# define PGM_CTX(a,b) a##RC##b
2490# define PGM_CTX_STR(a,b) a "GC" b
2491# define PGM_CTX_DECL(type) VMMRCDECL(type)
2492#else
2493# ifdef IN_RING3
2494# define PGM_CTX(a,b) a##R3##b
2495# define PGM_CTX_STR(a,b) a "R3" b
2496# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2497# else
2498# define PGM_CTX(a,b) a##R0##b
2499# define PGM_CTX_STR(a,b) a "R0" b
2500# define PGM_CTX_DECL(type) VMMDECL(type)
2501# endif
2502#endif
2503
2504#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2505#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2506#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2507#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2508#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2509#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2510#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2511#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2512#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2513#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2514#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2515#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2516#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2517#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2518#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2519#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2520#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2521
2522#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2523#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2524#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2525#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2526#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2527#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2528#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2529#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2530#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2531#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2532#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2533#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2534#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2535#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2536#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2537#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2538#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2539
2540/* Shw_Gst */
2541#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2542#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2543#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2544#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2545#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2546#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2547#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2548#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2549#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2550#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2551#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2552#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2553#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2554#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2555#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2556#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2557#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2558#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2559#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2560
2561#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2562#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2563#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2564#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2565#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2566#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2567#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2568#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2569#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2570#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2571#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2572#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2573#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2574#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2575#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2576#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2577#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2578#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2579#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2580#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2581#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2582#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2583#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2584#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2585#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2586#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2587#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2588#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2589#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2590#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2591#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2592#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2593#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2594#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2595#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2596#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2597#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2598
2599#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2600#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2601/** @} */
2602
2603/**
2604 * Data for each paging mode.
2605 */
2606typedef struct PGMMODEDATA
2607{
2608 /** The guest mode type. */
2609 uint32_t uGstType;
2610 /** The shadow mode type. */
2611 uint32_t uShwType;
2612
2613 /** @name Function pointers for Shadow paging.
2614 * @{
2615 */
2616 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2617 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2618 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2619 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2620
2621 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2622 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2623
2624 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2625 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2626 /** @} */
2627
2628 /** @name Function pointers for Guest paging.
2629 * @{
2630 */
2631 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2632 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2633 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2634 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2635 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2636 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2637 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2638 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2639 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2640 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2641 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2642 /** @} */
2643
2644 /** @name Function pointers for Both Shadow and Guest paging.
2645 * @{
2646 */
2647 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2648 /* no pfnR3BthTrap0eHandler */
2649 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2650 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2651 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2652 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2653#ifdef VBOX_STRICT
2654 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2655#endif
2656 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2657 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2658
2659 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2660 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2661 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2662 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2663 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2664#ifdef VBOX_STRICT
2665 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2666#endif
2667 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2668 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2669
2670 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2671 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2672 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2673 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2674 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2675#ifdef VBOX_STRICT
2676 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2677#endif
2678 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2679 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2680 /** @} */
2681} PGMMODEDATA, *PPGMMODEDATA;
2682
2683
2684#ifdef VBOX_WITH_STATISTICS
2685/**
2686 * PGM statistics.
2687 *
2688 * These lives on the heap when compiled in as they would otherwise waste
2689 * unecessary space in release builds.
2690 */
2691typedef struct PGMSTATS
2692{
2693 /* R3 only: */
2694 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2695 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2696
2697 /* R3+RZ */
2698 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2699 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2700 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2701 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2702 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2703 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2704 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2705 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2706 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2707 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2708 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2709 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2710 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2711 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2712 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2713 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2714 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2715 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2716 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2717 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2718 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2719 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2720 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2721 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2722/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2723 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2724 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2725/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2726
2727 /* RC only: */
2728 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2729 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2730
2731 STAMCOUNTER StatRZPhysRead;
2732 STAMCOUNTER StatRZPhysReadBytes;
2733 STAMCOUNTER StatRZPhysWrite;
2734 STAMCOUNTER StatRZPhysWriteBytes;
2735 STAMCOUNTER StatR3PhysRead;
2736 STAMCOUNTER StatR3PhysReadBytes;
2737 STAMCOUNTER StatR3PhysWrite;
2738 STAMCOUNTER StatR3PhysWriteBytes;
2739 STAMCOUNTER StatRCPhysRead;
2740 STAMCOUNTER StatRCPhysReadBytes;
2741 STAMCOUNTER StatRCPhysWrite;
2742 STAMCOUNTER StatRCPhysWriteBytes;
2743
2744 STAMCOUNTER StatRZPhysSimpleRead;
2745 STAMCOUNTER StatRZPhysSimpleReadBytes;
2746 STAMCOUNTER StatRZPhysSimpleWrite;
2747 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2748 STAMCOUNTER StatR3PhysSimpleRead;
2749 STAMCOUNTER StatR3PhysSimpleReadBytes;
2750 STAMCOUNTER StatR3PhysSimpleWrite;
2751 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2752 STAMCOUNTER StatRCPhysSimpleRead;
2753 STAMCOUNTER StatRCPhysSimpleReadBytes;
2754 STAMCOUNTER StatRCPhysSimpleWrite;
2755 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2756
2757 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2758 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2759 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2760 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2761 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2762 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2763 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2764
2765 /** Time spent by the host OS for large page allocation. */
2766 STAMPROFILE StatAllocLargePage;
2767 /** Time spent clearing the newly allocated large pages. */
2768 STAMPROFILE StatClearLargePage;
2769 /** pgmPhysIsValidLargePage profiling - R3 */
2770 STAMPROFILE StatR3IsValidLargePage;
2771 /** pgmPhysIsValidLargePage profiling - RZ*/
2772 STAMPROFILE StatRZIsValidLargePage;
2773
2774 STAMPROFILE StatChunkAging;
2775 STAMPROFILE StatChunkFindCandidate;
2776 STAMPROFILE StatChunkUnmap;
2777 STAMPROFILE StatChunkMap;
2778} PGMSTATS;
2779#endif /* VBOX_WITH_STATISTICS */
2780
2781
2782/**
2783 * Converts a PGM pointer into a VM pointer.
2784 * @returns Pointer to the VM structure the PGM is part of.
2785 * @param pPGM Pointer to PGM instance data.
2786 */
2787#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2788
2789/**
2790 * PGM Data (part of VM)
2791 */
2792typedef struct PGM
2793{
2794 /** Offset to the VM structure. */
2795 int32_t offVM;
2796 /** Offset of the PGMCPU structure relative to VMCPU. */
2797 int32_t offVCpuPGM;
2798
2799 /** @cfgm{RamPreAlloc, boolean, false}
2800 * Indicates whether the base RAM should all be allocated before starting
2801 * the VM (default), or if it should be allocated when first written to.
2802 */
2803 bool fRamPreAlloc;
2804 /** Indicates whether write monitoring is currently in use.
2805 * This is used to prevent conflicts between live saving and page sharing
2806 * detection. */
2807 bool fPhysWriteMonitoringEngaged;
2808 /** Set if the CPU has less than 52-bit physical address width.
2809 * This is used */
2810 bool fLessThan52PhysicalAddressBits;
2811 /** Set when nested paging is active.
2812 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2813 * compilers optimize the code better. Whether we use nested paging or
2814 * not is something we find out during VMM initialization and we won't
2815 * change this later on. */
2816 bool fNestedPaging;
2817 /** The host paging mode. (This is what SUPLib reports.) */
2818 SUPPAGINGMODE enmHostMode;
2819 /** We're not in a state which permits writes to guest memory.
2820 * (Only used in strict builds.) */
2821 bool fNoMorePhysWrites;
2822 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2823 bool afAlignment1[3];
2824
2825 /** Indicates that PGMR3FinalizeMappings has been called and that further
2826 * PGMR3MapIntermediate calls will be rejected. */
2827 bool fFinalizedMappings;
2828 /** If set no conflict checks are required. */
2829 bool fMappingsFixed;
2830 /** If set if restored as fixed but we were unable to re-fixate at the old
2831 * location because of room or address incompatibilities. */
2832 bool fMappingsFixedRestored;
2833 /** If set, then no mappings are put into the shadow page table.
2834 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2835 bool fMappingsDisabled;
2836 /** Size of fixed mapping.
2837 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2838 uint32_t cbMappingFixed;
2839 /** Generation ID for the RAM ranges. This member is incremented everytime
2840 * a RAM range is linked or unlinked. */
2841 uint32_t volatile idRamRangesGen;
2842
2843 /** Base address (GC) of fixed mapping.
2844 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2845 RTGCPTR GCPtrMappingFixed;
2846 /** The address of the previous RAM range mapping. */
2847 RTGCPTR GCPtrPrevRamRangeMapping;
2848
2849 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2850 RTGCPHYS GCPhys4MBPSEMask;
2851 /** Mask containing the invalid bits of a guest physical address.
2852 * @remarks this does not stop at bit 52. */
2853 RTGCPHYS GCPhysInvAddrMask;
2854
2855
2856 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2857 * This is sorted by physical address and contains no overlapping ranges. */
2858 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2859 /** PGM offset based trees - R3 Ptr. */
2860 R3PTRTYPE(PPGMTREES) pTreesR3;
2861 /** Caching the last physical handler we looked up in R3. */
2862 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2863 /** Shadow Page Pool - R3 Ptr. */
2864 R3PTRTYPE(PPGMPOOL) pPoolR3;
2865 /** Linked list of GC mappings - for HC.
2866 * The list is sorted ascending on address. */
2867 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2868 /** Pointer to the list of ROM ranges - for R3.
2869 * This is sorted by physical address and contains no overlapping ranges. */
2870 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2871 /** Pointer to the list of MMIO2 ranges - for R3.
2872 * Registration order. */
2873 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2874 /** Pointer to SHW+GST mode data (function pointers).
2875 * The index into this table is made up from */
2876 R3PTRTYPE(PPGMMODEDATA) paModeData;
2877 /*RTR3PTR R3PtrAlignment0;*/
2878
2879
2880 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2881 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2882 /** PGM offset based trees - R0 Ptr. */
2883 R0PTRTYPE(PPGMTREES) pTreesR0;
2884 /** Caching the last physical handler we looked up in R0. */
2885 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2886 /** Shadow Page Pool - R0 Ptr. */
2887 R0PTRTYPE(PPGMPOOL) pPoolR0;
2888 /** Linked list of GC mappings - for R0.
2889 * The list is sorted ascending on address. */
2890 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2891 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2892 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2893 /*RTR0PTR R0PtrAlignment0;*/
2894
2895
2896 /** RC pointer corresponding to PGM::pRamRangesR3. */
2897 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2898 /** PGM offset based trees - RC Ptr. */
2899 RCPTRTYPE(PPGMTREES) pTreesRC;
2900 /** Caching the last physical handler we looked up in RC. */
2901 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2902 /** Shadow Page Pool - RC Ptr. */
2903 RCPTRTYPE(PPGMPOOL) pPoolRC;
2904 /** Linked list of GC mappings - for RC.
2905 * The list is sorted ascending on address. */
2906 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2907 /** RC pointer corresponding to PGM::pRomRangesR3. */
2908 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2909 /*RTRCPTR RCPtrAlignment0;*/
2910 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2911 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2912 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2913 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2914
2915
2916 /** Pointer to the 5 page CR3 content mapping.
2917 * The first page is always the CR3 (in some form) while the 4 other pages
2918 * are used of the PDs in PAE mode. */
2919 RTGCPTR GCPtrCR3Mapping;
2920
2921 /** @name Intermediate Context
2922 * @{ */
2923 /** Pointer to the intermediate page directory - Normal. */
2924 R3PTRTYPE(PX86PD) pInterPD;
2925 /** Pointer to the intermedate page tables - Normal.
2926 * There are two page tables, one for the identity mapping and one for
2927 * the host context mapping (of the core code). */
2928 R3PTRTYPE(PX86PT) apInterPTs[2];
2929 /** Pointer to the intermedate page tables - PAE. */
2930 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2931 /** Pointer to the intermedate page directory - PAE. */
2932 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2933 /** Pointer to the intermedate page directory - PAE. */
2934 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2935 /** Pointer to the intermedate page-map level 4 - AMD64. */
2936 R3PTRTYPE(PX86PML4) pInterPaePML4;
2937 /** Pointer to the intermedate page directory - AMD64. */
2938 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2939 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2940 RTHCPHYS HCPhysInterPD;
2941 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2942 RTHCPHYS HCPhysInterPaePDPT;
2943 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2944 RTHCPHYS HCPhysInterPaePML4;
2945 /** @} */
2946
2947 /** Base address of the dynamic page mapping area.
2948 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2949 *
2950 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
2951 * work out. Some cleaning up of the initialization that would
2952 * remove this memory is yet to be done...
2953 */
2954 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2955 /** The address of the raw-mode context mapping cache. */
2956 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
2957 /** The address of the ring-0 mapping cache if we're making use of it. */
2958 RTR0PTR pvR0DynMapUsed;
2959#if HC_ARCH_BITS == 32
2960 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2961 uint32_t u32Alignment2;
2962#endif
2963
2964 /** PGM critical section.
2965 * This protects the physical & virtual access handlers, ram ranges,
2966 * and the page flag updating (some of it anyway).
2967 */
2968 PDMCRITSECT CritSect;
2969
2970 /**
2971 * Data associated with managing the ring-3 mappings of the allocation chunks.
2972 */
2973 struct
2974 {
2975 /** The chunk tree, ordered by chunk id. */
2976#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2977 R3PTRTYPE(PAVLU32NODECORE) pTree;
2978#else
2979 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2980#endif
2981#if HC_ARCH_BITS == 32
2982 uint32_t u32Alignment;
2983#endif
2984 /** The chunk mapping TLB. */
2985 PGMCHUNKR3MAPTLB Tlb;
2986 /** The number of mapped chunks. */
2987 uint32_t c;
2988 /** The maximum number of mapped chunks.
2989 * @cfgm PGM/MaxRing3Chunks */
2990 uint32_t cMax;
2991 /** The current time. */
2992 uint32_t iNow;
2993 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2994 uint32_t AgeingCountdown;
2995 } ChunkR3Map;
2996
2997 /**
2998 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2999 */
3000 PGMPAGER3MAPTLB PhysTlbHC;
3001
3002 /** @name The zero page.
3003 * @{ */
3004 /** The host physical address of the zero page. */
3005 RTHCPHYS HCPhysZeroPg;
3006 /** The ring-3 mapping of the zero page. */
3007 RTR3PTR pvZeroPgR3;
3008 /** The ring-0 mapping of the zero page. */
3009 RTR0PTR pvZeroPgR0;
3010 /** The GC mapping of the zero page. */
3011 RTRCPTR pvZeroPgRC;
3012 RTRCPTR RCPtrAlignment3;
3013 /** @}*/
3014
3015 /** @name The Invalid MMIO page.
3016 * This page is filled with 0xfeedface.
3017 * @{ */
3018 /** The host physical address of the invalid MMIO page. */
3019 RTHCPHYS HCPhysMmioPg;
3020 /** The host pysical address of the invalid MMIO page pluss all invalid
3021 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3022 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3023 RTHCPHYS HCPhysInvMmioPg;
3024 /** The ring-3 mapping of the invalid MMIO page. */
3025 RTR3PTR pvMmioPgR3;
3026#if HC_ARCH_BITS == 32
3027 RTR3PTR R3PtrAlignment4;
3028#endif
3029 /** @} */
3030
3031
3032 /** The number of handy pages. */
3033 uint32_t cHandyPages;
3034
3035 /** The number of large handy pages. */
3036 uint32_t cLargeHandyPages;
3037
3038 /**
3039 * Array of handy pages.
3040 *
3041 * This array is used in a two way communication between pgmPhysAllocPage
3042 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3043 * an intermediary.
3044 *
3045 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3046 * (The current size of 32 pages, means 128 KB of handy memory.)
3047 */
3048 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3049
3050 /**
3051 * Array of large handy pages. (currently size 1)
3052 *
3053 * This array is used in a two way communication between pgmPhysAllocLargePage
3054 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3055 * an intermediary.
3056 */
3057 GMMPAGEDESC aLargeHandyPage[1];
3058
3059 /**
3060 * Live save data.
3061 */
3062 struct
3063 {
3064 /** Per type statistics. */
3065 struct
3066 {
3067 /** The number of ready pages. */
3068 uint32_t cReadyPages;
3069 /** The number of dirty pages. */
3070 uint32_t cDirtyPages;
3071 /** The number of ready zero pages. */
3072 uint32_t cZeroPages;
3073 /** The number of write monitored pages. */
3074 uint32_t cMonitoredPages;
3075 } Rom,
3076 Mmio2,
3077 Ram;
3078 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3079 uint32_t cIgnoredPages;
3080 /** Indicates that a live save operation is active. */
3081 bool fActive;
3082 /** Padding. */
3083 bool afReserved[2];
3084 /** The next history index. */
3085 uint8_t iDirtyPagesHistory;
3086 /** History of the total amount of dirty pages. */
3087 uint32_t acDirtyPagesHistory[64];
3088 /** Short term dirty page average. */
3089 uint32_t cDirtyPagesShort;
3090 /** Long term dirty page average. */
3091 uint32_t cDirtyPagesLong;
3092 /** The number of saved pages. This is used to get some kind of estimate of the
3093 * link speed so we can decide when we're done. It is reset after the first
3094 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3095 * zero pages. */
3096 uint64_t cSavedPages;
3097 /** The nanosecond timestamp when cSavedPages was 0. */
3098 uint64_t uSaveStartNS;
3099 /** Pages per second (for statistics). */
3100 uint32_t cPagesPerSecond;
3101 uint32_t cAlignment;
3102 } LiveSave;
3103
3104 /** @name Error injection.
3105 * @{ */
3106 /** Inject handy page allocation errors pretending we're completely out of
3107 * memory. */
3108 bool volatile fErrInjHandyPages;
3109 /** Padding. */
3110 bool afReserved[3];
3111 /** @} */
3112
3113 /** @name Release Statistics
3114 * @{ */
3115 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3116 uint32_t cPrivatePages; /**< The number of private pages. */
3117 uint32_t cSharedPages; /**< The number of shared pages. */
3118 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3119 uint32_t cZeroPages; /**< The number of zero backed pages. */
3120 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3121 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3122 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3123 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3124 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3125 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3126 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3127 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3128/* uint32_t aAlignment4[1]; */
3129
3130 /** The number of times we were forced to change the hypervisor region location. */
3131 STAMCOUNTER cRelocations;
3132
3133 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3134 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3135 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3136 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3137 /** @} */
3138
3139#ifdef VBOX_WITH_STATISTICS
3140 /** @name Statistics on the heap.
3141 * @{ */
3142 R3PTRTYPE(PGMSTATS *) pStatsR3;
3143 R0PTRTYPE(PGMSTATS *) pStatsR0;
3144 RCPTRTYPE(PGMSTATS *) pStatsRC;
3145 RTRCPTR RCPtrAlignment;
3146 /** @} */
3147#endif
3148} PGM;
3149#ifndef IN_TSTVMSTRUCTGC /* HACK */
3150AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3151AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3152AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3153AssertCompileMemberAlignment(PGM, CritSect, 8);
3154AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3155AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3156AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3157AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3158AssertCompileMemberAlignment(PGM, cRelocations, 8);
3159#endif /* !IN_TSTVMSTRUCTGC */
3160/** Pointer to the PGM instance data. */
3161typedef PGM *PPGM;
3162
3163
3164
3165typedef struct PGMCPUSTATS
3166{
3167 /* Common */
3168 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3169 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3170
3171 /* R0 only: */
3172
3173 /* RZ only: */
3174 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3175 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3176 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3177 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3178 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3179 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3180 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3181 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3182 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3183 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3184 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3185 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3186 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3187 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3188 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3189 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3190 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3191 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3192 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3193 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3194 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3195 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3196 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3197 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3198 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3199 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3200 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3201 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3202 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3203 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3204 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3205 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3206 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3207 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3208 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3209 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3210 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3211 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3212 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3213 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3214 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3215 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3216 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3217 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3218 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3219 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3220 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3221 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3222 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3223 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3224 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3225 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3226 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3227 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3228 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3229 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3230 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3231 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3232 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3233 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restorting to subset flushes. */
3234 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3235 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3236 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3237 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3238 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3239 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3240 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3241 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3242 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3243 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3244 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3245 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3246 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3247 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3248
3249 /* HC - R3 and (maybe) R0: */
3250
3251 /* RZ & R3: */
3252 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3253 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3254 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3255 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3256 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3257 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3258 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3259 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3260 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3261 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3262 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3263 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3264 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3265 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3266 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3267 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3268 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3269 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3270 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3271 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3272 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3273 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3274 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3275 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3276 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3277 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3278 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3279 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3280 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3281 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3282 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3283 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3284 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3285 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3286 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3287 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3288 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3289 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3290 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3291 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3292 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3293 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3294 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3295 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3296 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3297 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3298 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3299
3300 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3301 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3302 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3303 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3304 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3305 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3306 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3307 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3308 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3309 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3310 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3311 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3312 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3313 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3314 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3315 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3316 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3317 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3318 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3319 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3320 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3321 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3322 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3323 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3324 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3325 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3326 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3327 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3328 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3329 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3330 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3331 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3332 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3333 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3334 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3335 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3336 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3337 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3338 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3339 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3340 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3341 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3342 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3343 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3344 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3345 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3346 /** @} */
3347} PGMCPUSTATS;
3348
3349
3350/**
3351 * Converts a PGMCPU pointer into a VM pointer.
3352 * @returns Pointer to the VM structure the PGM is part of.
3353 * @param pPGM Pointer to PGMCPU instance data.
3354 */
3355#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3356
3357/**
3358 * Converts a PGMCPU pointer into a PGM pointer.
3359 * @returns Pointer to the VM structure the PGM is part of.
3360 * @param pPGM Pointer to PGMCPU instance data.
3361 */
3362#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3363
3364/**
3365 * PGMCPU Data (part of VMCPU).
3366 */
3367typedef struct PGMCPU
3368{
3369 /** Offset to the VM structure. */
3370 int32_t offVM;
3371 /** Offset to the VMCPU structure. */
3372 int32_t offVCpu;
3373 /** Offset of the PGM structure relative to VMCPU. */
3374 int32_t offPGM;
3375 uint32_t uPadding0; /**< structure size alignment. */
3376
3377#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3378 /** Automatically tracked physical memory mapping set.
3379 * Ring-0 and strict raw-mode builds. */
3380 PGMMAPSET AutoSet;
3381#endif
3382
3383 /** A20 gate mask.
3384 * Our current approach to A20 emulation is to let REM do it and don't bother
3385 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3386 * But whould need arrise, we'll subject physical addresses to this mask. */
3387 RTGCPHYS GCPhysA20Mask;
3388 /** A20 gate state - boolean! */
3389 bool fA20Enabled;
3390 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3391 bool fNoExecuteEnabled;
3392 /** Unused bits. */
3393 bool afUnused[2];
3394
3395 /** What needs syncing (PGM_SYNC_*).
3396 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3397 * PGMFlushTLB, and PGMR3Load. */
3398 RTUINT fSyncFlags;
3399
3400 /** The shadow paging mode. */
3401 PGMMODE enmShadowMode;
3402 /** The guest paging mode. */
3403 PGMMODE enmGuestMode;
3404
3405 /** The current physical address representing in the guest CR3 register. */
3406 RTGCPHYS GCPhysCR3;
3407
3408 /** @name 32-bit Guest Paging.
3409 * @{ */
3410 /** The guest's page directory, R3 pointer. */
3411 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3412#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3413 /** The guest's page directory, R0 pointer. */
3414 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3415#endif
3416 /** The guest's page directory, static RC mapping. */
3417 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3418 /** Mask containing the MBZ bits of a big page PDE. */
3419 uint32_t fGst32BitMbzBigPdeMask;
3420 /** Set if the page size extension (PSE) is enabled. */
3421 bool fGst32BitPageSizeExtension;
3422 /** Alignment padding. */
3423 bool afAlignment2[3];
3424 /** @} */
3425
3426 /** @name PAE Guest Paging.
3427 * @{ */
3428 /** The guest's page directory pointer table, static RC mapping. */
3429 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3430 /** The guest's page directory pointer table, R3 pointer. */
3431 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3432#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3433 /** The guest's page directory pointer table, R0 pointer. */
3434 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3435#endif
3436
3437 /** The guest's page directories, R3 pointers.
3438 * These are individual pointers and don't have to be adjecent.
3439 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3440 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3441 /** The guest's page directories, R0 pointers.
3442 * Same restrictions as apGstPaePDsR3. */
3443#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3444 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3445#endif
3446 /** The guest's page directories, static GC mapping.
3447 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3448 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3449 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3450 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3451 RTGCPHYS aGCPhysGstPaePDs[4];
3452 /** The physical addresses of the monitored guest page directories (PAE). */
3453 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3454 /** Mask containing the MBZ PTE bits. */
3455 uint64_t fGstPaeMbzPteMask;
3456 /** Mask containing the MBZ PDE bits. */
3457 uint64_t fGstPaeMbzPdeMask;
3458 /** Mask containing the MBZ big page PDE bits. */
3459 uint64_t fGstPaeMbzBigPdeMask;
3460 /** Mask containing the MBZ PDPE bits. */
3461 uint64_t fGstPaeMbzPdpeMask;
3462 /** @} */
3463
3464 /** @name AMD64 Guest Paging.
3465 * @{ */
3466 /** The guest's page directory pointer table, R3 pointer. */
3467 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3468#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3469 /** The guest's page directory pointer table, R0 pointer. */
3470 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3471#else
3472 RTR0PTR alignment6b; /**< alignment equalizer. */
3473#endif
3474 /** Mask containing the MBZ PTE bits. */
3475 uint64_t fGstAmd64MbzPteMask;
3476 /** Mask containing the MBZ PDE bits. */
3477 uint64_t fGstAmd64MbzPdeMask;
3478 /** Mask containing the MBZ big page PDE bits. */
3479 uint64_t fGstAmd64MbzBigPdeMask;
3480 /** Mask containing the MBZ PDPE bits. */
3481 uint64_t fGstAmd64MbzPdpeMask;
3482 /** Mask containing the MBZ big page PDPE bits. */
3483 uint64_t fGstAmd64MbzBigPdpeMask;
3484 /** Mask containing the MBZ PML4E bits. */
3485 uint64_t fGstAmd64MbzPml4eMask;
3486 /** @} */
3487
3488 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3489 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3490 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3491 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3492 /** Pointer to the page of the current active CR3 - RC Ptr. */
3493 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3494 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3495 uint32_t iShwUser;
3496 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3497 uint32_t iShwUserTable;
3498# if HC_ARCH_BITS == 64
3499 RTRCPTR alignment6; /**< structure size alignment. */
3500# endif
3501 /** @} */
3502
3503 /** @name Function pointers for Shadow paging.
3504 * @{
3505 */
3506 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3507 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3508 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3509 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3510
3511 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3512 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3513
3514 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3515 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3516
3517 /** @} */
3518
3519 /** @name Function pointers for Guest paging.
3520 * @{
3521 */
3522 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3523 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3524 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3525 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3526 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3527 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3528 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3529 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3530#if HC_ARCH_BITS == 64
3531 RTRCPTR alignment3; /**< structure size alignment. */
3532#endif
3533
3534 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3535 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3536 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3537 /** @} */
3538
3539 /** @name Function pointers for Both Shadow and Guest paging.
3540 * @{
3541 */
3542 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3543 /* no pfnR3BthTrap0eHandler */
3544 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3545 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3546 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3547 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3548 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3549 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3550 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3551
3552 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3553 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3554 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3555 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3556 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3557 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3558 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3559 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3560
3561 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3562 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3563 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3564 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3565 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3566 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3567 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3568 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3569#if 0
3570 RTRCPTR alignment2; /**< structure size alignment. */
3571#endif
3572 /** @} */
3573
3574 /** For saving stack space, the disassembler state is allocated here instead of
3575 * on the stack.
3576 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3577 union
3578 {
3579 /** The disassembler scratch space. */
3580 DISCPUSTATE DisState;
3581 /** Padding. */
3582 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3583 };
3584
3585 /** Count the number of pgm pool access handler calls. */
3586 uint64_t cPoolAccessHandler;
3587
3588 /** @name Release Statistics
3589 * @{ */
3590 /** The number of times the guest has switched mode since last reset or statistics reset. */
3591 STAMCOUNTER cGuestModeChanges;
3592 /** @} */
3593
3594#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3595 /** @name Statistics
3596 * @{ */
3597 /** RC: Pointer to the statistics. */
3598 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3599 /** RC: Which statistic this \#PF should be attributed to. */
3600 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3601 /** R0: Pointer to the statistics. */
3602 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3603 /** R0: Which statistic this \#PF should be attributed to. */
3604 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3605 /** R3: Pointer to the statistics. */
3606 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3607 /** Alignment padding. */
3608 RTR3PTR pPaddingR3;
3609 /** @} */
3610#endif /* VBOX_WITH_STATISTICS */
3611} PGMCPU;
3612/** Pointer to the per-cpu PGM data. */
3613typedef PGMCPU *PPGMCPU;
3614
3615
3616/** @name PGM::fSyncFlags Flags
3617 * @{
3618 */
3619/** Updates the virtual access handler state bit in PGMPAGE. */
3620#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3621/** Always sync CR3. */
3622#define PGM_SYNC_ALWAYS RT_BIT(1)
3623/** Check monitoring on next CR3 (re)load and invalidate page.
3624 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3625#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3626/** Check guest mapping in SyncCR3. */
3627#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3628/** Clear the page pool (a light weight flush). */
3629#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3630#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3631/** @} */
3632
3633
3634RT_C_DECLS_BEGIN
3635
3636int pgmLock(PVM pVM);
3637void pgmUnlock(PVM pVM);
3638
3639int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3640int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3641int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3642PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3643int pgmMapResolveConflicts(PVM pVM);
3644DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3645
3646void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3647bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3648void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3649int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3650DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3651#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3652void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3653#else
3654# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3655#endif
3656DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3657int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3658
3659int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3660int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3661int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3662int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3663int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3664void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3665int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3666int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3667int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3668int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3669int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3670int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3671int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3672VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3673VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3674int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3675
3676#ifdef IN_RING3
3677void pgmR3PhysRelinkRamRanges(PVM pVM);
3678int pgmR3PhysRamPreAllocate(PVM pVM);
3679int pgmR3PhysRamReset(PVM pVM);
3680int pgmR3PhysRomReset(PVM pVM);
3681int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3682int pgmR3PhysRamTerm(PVM pVM);
3683void pgmR3PhysRomTerm(PVM pVM);
3684
3685int pgmR3PoolInit(PVM pVM);
3686void pgmR3PoolRelocate(PVM pVM);
3687void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3688void pgmR3PoolReset(PVM pVM);
3689void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3690DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3691
3692#endif /* IN_RING3 */
3693#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || IN_RC
3694int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3695int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3696# ifdef LOG_ENABLED
3697void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3698# else
3699void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3700# endif
3701#endif
3702int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3703
3704DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3705{
3706 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3707}
3708
3709void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3710void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3711int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3712void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3713PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3714int pgmPoolSyncCR3(PVMCPU pVCpu);
3715bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3716int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3717void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3718void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3719DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3720{
3721 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3722}
3723
3724uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3725void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3726void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3727int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3728void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3729
3730void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3731void pgmPoolResetDirtyPages(PVM pVM);
3732
3733int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3734int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3735
3736void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3737void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3738int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3739int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3740
3741int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3742
3743int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3744int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3745int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3746int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3747
3748# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3749DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3750DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3751# endif
3752
3753RT_C_DECLS_END
3754
3755/** @} */
3756
3757#endif
3758
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