VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 31657

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1/* $Id: PGMInternal.h 31657 2010-08-13 14:53:34Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm.h>
28#include <VBox/mm.h>
29#include <VBox/pdmcritsect.h>
30#include <VBox/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/gmm.h>
35#include <VBox/hwaccm.h>
36#include <VBox/hwacc_vmx.h>
37#include <include/internal/pgm.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 0 /* ! remember to disable before committing ! XXX TODO */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416/** Size of the GCPtrConflict array in PGMMAPPING.
417 * @remarks Must be a power of two. */
418#define PGMMAPPING_CONFLICT_MAX 8
419
420/**
421 * Structure for tracking GC Mappings.
422 *
423 * This structure is used by linked list in both GC and HC.
424 */
425typedef struct PGMMAPPING
426{
427 /** Pointer to next entry. */
428 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
429 /** Pointer to next entry. */
430 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
431 /** Pointer to next entry. */
432 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
433 /** Indicate whether this entry is finalized. */
434 bool fFinalized;
435 /** Start Virtual address. */
436 RTGCPTR GCPtr;
437 /** Last Virtual address (inclusive). */
438 RTGCPTR GCPtrLast;
439 /** Range size (bytes). */
440 RTGCPTR cb;
441 /** Pointer to relocation callback function. */
442 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
443 /** User argument to the callback. */
444 R3PTRTYPE(void *) pvUser;
445 /** Mapping description / name. For easing debugging. */
446 R3PTRTYPE(const char *) pszDesc;
447 /** Last 8 addresses that caused conflicts. */
448 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
449 /** Number of conflicts for this hypervisor mapping. */
450 uint32_t cConflicts;
451 /** Number of page tables. */
452 uint32_t cPTs;
453
454 /** Array of page table mapping data. Each entry
455 * describes one page table. The array can be longer
456 * than the declared length.
457 */
458 struct
459 {
460 /** The HC physical address of the page table. */
461 RTHCPHYS HCPhysPT;
462 /** The HC physical address of the first PAE page table. */
463 RTHCPHYS HCPhysPaePT0;
464 /** The HC physical address of the second PAE page table. */
465 RTHCPHYS HCPhysPaePT1;
466 /** The HC virtual address of the 32-bit page table. */
467 R3PTRTYPE(PX86PT) pPTR3;
468 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
469 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
470 /** The RC virtual address of the 32-bit page table. */
471 RCPTRTYPE(PX86PT) pPTRC;
472 /** The RC virtual address of the two PAE page table. */
473 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
474 /** The R0 virtual address of the 32-bit page table. */
475 R0PTRTYPE(PX86PT) pPTR0;
476 /** The R0 virtual address of the two PAE page table. */
477 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
478 } aPTs[1];
479} PGMMAPPING;
480/** Pointer to structure for tracking GC Mappings. */
481typedef struct PGMMAPPING *PPGMMAPPING;
482
483
484/**
485 * Physical page access handler structure.
486 *
487 * This is used to keep track of physical address ranges
488 * which are being monitored in some kind of way.
489 */
490typedef struct PGMPHYSHANDLER
491{
492 AVLROGCPHYSNODECORE Core;
493 /** Access type. */
494 PGMPHYSHANDLERTYPE enmType;
495 /** Number of pages to update. */
496 uint32_t cPages;
497 /** Pointer to R3 callback function. */
498 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
499 /** User argument for R3 handlers. */
500 R3PTRTYPE(void *) pvUserR3;
501 /** Pointer to R0 callback function. */
502 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
503 /** User argument for R0 handlers. */
504 R0PTRTYPE(void *) pvUserR0;
505 /** Pointer to RC callback function. */
506 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
507 /** User argument for RC handlers. */
508 RCPTRTYPE(void *) pvUserRC;
509 /** Description / Name. For easing debugging. */
510 R3PTRTYPE(const char *) pszDesc;
511#ifdef VBOX_WITH_STATISTICS
512 /** Profiling of this handler. */
513 STAMPROFILE Stat;
514#endif
515} PGMPHYSHANDLER;
516/** Pointer to a physical page access handler structure. */
517typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
518
519
520/**
521 * Cache node for the physical addresses covered by a virtual handler.
522 */
523typedef struct PGMPHYS2VIRTHANDLER
524{
525 /** Core node for the tree based on physical ranges. */
526 AVLROGCPHYSNODECORE Core;
527 /** Offset from this struct to the PGMVIRTHANDLER structure. */
528 int32_t offVirtHandler;
529 /** Offset of the next alias relative to this one.
530 * Bit 0 is used for indicating whether we're in the tree.
531 * Bit 1 is used for indicating that we're the head node.
532 */
533 int32_t offNextAlias;
534} PGMPHYS2VIRTHANDLER;
535/** Pointer to a phys to virtual handler structure. */
536typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
537
538/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
539 * node is in the tree. */
540#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
541/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
542 * node is in the head of an alias chain.
543 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
544#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
545/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
546#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
547
548
549/**
550 * Virtual page access handler structure.
551 *
552 * This is used to keep track of virtual address ranges
553 * which are being monitored in some kind of way.
554 */
555typedef struct PGMVIRTHANDLER
556{
557 /** Core node for the tree based on virtual ranges. */
558 AVLROGCPTRNODECORE Core;
559 /** Size of the range (in bytes). */
560 RTGCPTR cb;
561 /** Number of cache pages. */
562 uint32_t cPages;
563 /** Access type. */
564 PGMVIRTHANDLERTYPE enmType;
565 /** Pointer to the RC callback function. */
566 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
567#if HC_ARCH_BITS == 64
568 RTRCPTR padding;
569#endif
570 /** Pointer to the R3 callback function for invalidation. */
571 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
572 /** Pointer to the R3 callback function. */
573 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
574 /** Description / Name. For easing debugging. */
575 R3PTRTYPE(const char *) pszDesc;
576#ifdef VBOX_WITH_STATISTICS
577 /** Profiling of this handler. */
578 STAMPROFILE Stat;
579#endif
580 /** Array of cached physical addresses for the monitored ranged. */
581 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
582} PGMVIRTHANDLER;
583/** Pointer to a virtual page access handler structure. */
584typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
585
586
587/**
588 * Page type.
589 *
590 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
591 * @remarks This is used in the saved state, so changes to it requires bumping
592 * the saved state version.
593 * @todo So, convert to \#defines!
594 */
595typedef enum PGMPAGETYPE
596{
597 /** The usual invalid zero entry. */
598 PGMPAGETYPE_INVALID = 0,
599 /** RAM page. (RWX) */
600 PGMPAGETYPE_RAM,
601 /** MMIO2 page. (RWX) */
602 PGMPAGETYPE_MMIO2,
603 /** MMIO2 page aliased over an MMIO page. (RWX)
604 * See PGMHandlerPhysicalPageAlias(). */
605 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
606 /** Shadowed ROM. (RWX) */
607 PGMPAGETYPE_ROM_SHADOW,
608 /** ROM page. (R-X) */
609 PGMPAGETYPE_ROM,
610 /** MMIO page. (---) */
611 PGMPAGETYPE_MMIO,
612 /** End of valid entries. */
613 PGMPAGETYPE_END
614} PGMPAGETYPE;
615AssertCompile(PGMPAGETYPE_END <= 7);
616
617/** @name Page type predicates.
618 * @{ */
619#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
620#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
621#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
622#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
623#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
624/** @} */
625
626
627/**
628 * A Physical Guest Page tracking structure.
629 *
630 * The format of this structure is complicated because we have to fit a lot
631 * of information into as few bits as possible. The format is also subject
632 * to change (there is one comming up soon). Which means that for we'll be
633 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
634 * accesses to the structure.
635 */
636typedef struct PGMPAGE
637{
638 /** The physical address and the Page ID. */
639 RTHCPHYS HCPhysAndPageID;
640 /** Combination of:
641 * - [0-7]: u2HandlerPhysStateY - the physical handler state
642 * (PGM_PAGE_HNDL_PHYS_STATE_*).
643 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
644 * (PGM_PAGE_HNDL_VIRT_STATE_*).
645 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
646 * - [15]: fWrittenToY - flag indicating that a write monitored page was
647 * written to when set.
648 * - [10-13]: 4 unused bits.
649 * @remarks Warning! All accesses to the bits are hardcoded.
650 *
651 * @todo Change this to a union with both bitfields, u8 and u accessors.
652 * That'll help deal with some of the hardcoded accesses.
653 *
654 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
655 * will make it possible to turn some of the 16-bit accesses into
656 * 32-bit ones, which may be efficient (stalls).
657 */
658 RTUINT16U u16MiscY;
659 /** The page state.
660 * Only 3 bits are really needed for this. */
661 uint16_t uStateY : 3;
662 /** The page type (PGMPAGETYPE).
663 * Only 3 bits are really needed for this. */
664 uint16_t uTypeY : 3;
665 /** PTE index for usage tracking (page pool). */
666 uint16_t uPteIdx : 10;
667 /** Usage tracking (page pool). */
668 uint16_t u16TrackingY;
669 /** The number of read locks on this page. */
670 uint8_t cReadLocksY;
671 /** The number of write locks on this page. */
672 uint8_t cWriteLocksY;
673} PGMPAGE;
674AssertCompileSize(PGMPAGE, 16);
675/** Pointer to a physical guest page. */
676typedef PGMPAGE *PPGMPAGE;
677/** Pointer to a const physical guest page. */
678typedef const PGMPAGE *PCPGMPAGE;
679/** Pointer to a physical guest page pointer. */
680typedef PPGMPAGE *PPPGMPAGE;
681
682
683/**
684 * Clears the page structure.
685 * @param pPage Pointer to the physical guest page tracking structure.
686 */
687#define PGM_PAGE_CLEAR(pPage) \
688 do { \
689 (pPage)->HCPhysAndPageID = 0; \
690 (pPage)->uStateY = 0; \
691 (pPage)->uTypeY = 0; \
692 (pPage)->uPteIdx = 0; \
693 (pPage)->u16MiscY.u = 0; \
694 (pPage)->u16TrackingY = 0; \
695 (pPage)->cReadLocksY = 0; \
696 (pPage)->cWriteLocksY = 0; \
697 } while (0)
698
699/**
700 * Initializes the page structure.
701 * @param pPage Pointer to the physical guest page tracking structure.
702 */
703#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
704 do { \
705 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
706 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
707 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
708 (pPage)->uStateY = (_uState); \
709 (pPage)->uTypeY = (_uType); \
710 (pPage)->uPteIdx = 0; \
711 (pPage)->u16MiscY.u = 0; \
712 (pPage)->u16TrackingY = 0; \
713 (pPage)->cReadLocksY = 0; \
714 (pPage)->cWriteLocksY = 0; \
715 } while (0)
716
717/**
718 * Initializes the page structure of a ZERO page.
719 * @param pPage Pointer to the physical guest page tracking structure.
720 * @param pVM The VM handle (for getting the zero page address).
721 * @param uType The page type (PGMPAGETYPE).
722 */
723#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
724 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
725
726
727/** @name The Page state, PGMPAGE::uStateY.
728 * @{ */
729/** The zero page.
730 * This is a per-VM page that's never ever mapped writable. */
731#define PGM_PAGE_STATE_ZERO 0
732/** A allocated page.
733 * This is a per-VM page allocated from the page pool (or wherever
734 * we get MMIO2 pages from if the type is MMIO2).
735 */
736#define PGM_PAGE_STATE_ALLOCATED 1
737/** A allocated page that's being monitored for writes.
738 * The shadow page table mappings are read-only. When a write occurs, the
739 * fWrittenTo member is set, the page remapped as read-write and the state
740 * moved back to allocated. */
741#define PGM_PAGE_STATE_WRITE_MONITORED 2
742/** The page is shared, aka. copy-on-write.
743 * This is a page that's shared with other VMs. */
744#define PGM_PAGE_STATE_SHARED 3
745/** The page is ballooned, so no longer available for this VM. */
746#define PGM_PAGE_STATE_BALLOONED 4
747/** @} */
748
749
750/**
751 * Gets the page state.
752 * @returns page state (PGM_PAGE_STATE_*).
753 * @param pPage Pointer to the physical guest page tracking structure.
754 */
755#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
756
757/**
758 * Sets the page state.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 * @param _uState The new page state.
761 */
762#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
763
764
765/**
766 * Gets the host physical address of the guest page.
767 * @returns host physical address (RTHCPHYS).
768 * @param pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
771
772/**
773 * Sets the host physical address of the guest page.
774 * @param pPage Pointer to the physical guest page tracking structure.
775 * @param _HCPhys The new host physical address.
776 */
777#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
778 do { \
779 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
780 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
781 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
782 | (SetHCPhysTmp << (28-12)); \
783 } while (0)
784
785/**
786 * Get the Page ID.
787 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
791
792/**
793 * Sets the Page ID.
794 * @param pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
797 do { \
798 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
799 | ((_idPage) & UINT32_C(0x0fffffff)); \
800 } while (0)
801
802/**
803 * Get the Chunk ID.
804 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
805 * @param pPage Pointer to the physical guest page tracking structure.
806 */
807#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
808
809/**
810 * Get the index of the page within the allocation chunk.
811 * @returns The page index.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 */
814#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
815
816/**
817 * Gets the page type.
818 * @returns The page type.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
822
823/**
824 * Sets the page type.
825 * @param pPage Pointer to the physical guest page tracking structure.
826 * @param _enmType The new page type (PGMPAGETYPE).
827 */
828#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
829
830/**
831 * Gets the page table index
832 * @returns The page table index.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
836
837/**
838 * Sets the page table index
839 * @param pPage Pointer to the physical guest page tracking structure.
840 * @param iPte New page table index.
841 */
842#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
843
844/**
845 * Checks if the page is marked for MMIO.
846 * @returns true/false.
847 * @param pPage Pointer to the physical guest page tracking structure.
848 */
849#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
850
851/**
852 * Checks if the page is backed by the ZERO page.
853 * @returns true/false.
854 * @param pPage Pointer to the physical guest page tracking structure.
855 */
856#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
857
858/**
859 * Checks if the page is backed by a SHARED page.
860 * @returns true/false.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
864
865/**
866 * Checks if the page is ballooned.
867 * @returns true/false.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
871
872/**
873 * Marks the page as written to (for GMM change monitoring).
874 * @param pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
877
878/**
879 * Clears the written-to indicator.
880 * @param pPage Pointer to the physical guest page tracking structure.
881 */
882#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
883
884/**
885 * Checks if the page was marked as written-to.
886 * @returns true/false.
887 * @param pPage Pointer to the physical guest page tracking structure.
888 */
889#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
890
891/** @name PT usage values (PGMPAGE::u2PDEType).
892 *
893 * @{ */
894/** Either as a PT or PDE. */
895#define PGM_PAGE_PDE_TYPE_DONTCARE 0
896/** Must use a page table to map the range. */
897#define PGM_PAGE_PDE_TYPE_PT 1
898/** Can use a page directory entry to map the continous range. */
899#define PGM_PAGE_PDE_TYPE_PDE 2
900/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
901#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
902/** @} */
903
904/**
905 * Set the PDE type of the page
906 * @param pPage Pointer to the physical guest page tracking structure.
907 * @param uType PGM_PAGE_PDE_TYPE_*
908 */
909#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
910 do { \
911 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
912 | (((uType) & UINT8_C(0x03)) << 5); \
913 } while (0)
914
915/**
916 * Checks if the page was marked being part of a large page
917 * @returns true/false.
918 * @param pPage Pointer to the physical guest page tracking structure.
919 */
920#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
921
922/** Enabled optimized access handler tests.
923 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
924 * layout. When enabled, the compiler should normally generate more compact
925 * code.
926 */
927#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
928
929/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
930 *
931 * @remarks The values are assigned in order of priority, so we can calculate
932 * the correct state for a page with different handlers installed.
933 * @{ */
934/** No handler installed. */
935#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
936/** Monitoring is temporarily disabled. */
937#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
938/** Write access is monitored. */
939#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
940/** All access is monitored. */
941#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
942/** @} */
943
944/**
945 * Gets the physical access handler state of a page.
946 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
947 * @param pPage Pointer to the physical guest page tracking structure.
948 */
949#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
950 ( (pPage)->u16MiscY.au8[0] )
951
952/**
953 * Sets the physical access handler state of a page.
954 * @param pPage Pointer to the physical guest page tracking structure.
955 * @param _uState The new state value.
956 */
957#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
958 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
959
960/**
961 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
962 * @returns true/false
963 * @param pPage Pointer to the physical guest page tracking structure.
964 */
965#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
966 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
967
968/**
969 * Checks if the page has any active physical access handlers.
970 * @returns true/false
971 * @param pPage Pointer to the physical guest page tracking structure.
972 */
973#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
974 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
975
976
977/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
978 *
979 * @remarks The values are assigned in order of priority, so we can calculate
980 * the correct state for a page with different handlers installed.
981 * @{ */
982/** No handler installed. */
983#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
984/* 1 is reserved so the lineup is identical with the physical ones. */
985/** Write access is monitored. */
986#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
987/** All access is monitored. */
988#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
989/** @} */
990
991/**
992 * Gets the virtual access handler state of a page.
993 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
994 * @param pPage Pointer to the physical guest page tracking structure.
995 */
996#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
997
998/**
999 * Sets the virtual access handler state of a page.
1000 * @param pPage Pointer to the physical guest page tracking structure.
1001 * @param _uState The new state value.
1002 */
1003#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1004 do { \
1005 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1006 | ((_uState) & UINT8_C(0x03)); \
1007 } while (0)
1008
1009/**
1010 * Checks if the page has any virtual access handlers.
1011 * @returns true/false
1012 * @param pPage Pointer to the physical guest page tracking structure.
1013 */
1014#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1015 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1016
1017/**
1018 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1019 * virtual handlers.
1020 * @returns true/false
1021 * @param pPage Pointer to the physical guest page tracking structure.
1022 */
1023#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1024 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1025
1026
1027/**
1028 * Checks if the page has any access handlers, including temporarily disabled ones.
1029 * @returns true/false
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1033# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1034 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1035#else
1036# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1037 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1038 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1039#endif
1040
1041/**
1042 * Checks if the page has any active access handlers.
1043 * @returns true/false
1044 * @param pPage Pointer to the physical guest page tracking structure.
1045 */
1046#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1047# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1048 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1049#else
1050# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1051 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1052 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1053#endif
1054
1055/**
1056 * Checks if the page has any active access handlers catching all accesses.
1057 * @returns true/false
1058 * @param pPage Pointer to the physical guest page tracking structure.
1059 */
1060#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1061# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1062 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1063 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1064#else
1065# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1066 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1067 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1068#endif
1069
1070
1071/** @def PGM_PAGE_GET_TRACKING
1072 * Gets the packed shadow page pool tracking data associated with a guest page.
1073 * @returns uint16_t containing the data.
1074 * @param pPage Pointer to the physical guest page tracking structure.
1075 */
1076#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1077
1078/** @def PGM_PAGE_SET_TRACKING
1079 * Sets the packed shadow page pool tracking data associated with a guest page.
1080 * @param pPage Pointer to the physical guest page tracking structure.
1081 * @param u16TrackingData The tracking data to store.
1082 */
1083#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1084 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1085
1086/** @def PGM_PAGE_GET_TD_CREFS
1087 * Gets the @a cRefs tracking data member.
1088 * @returns cRefs.
1089 * @param pPage Pointer to the physical guest page tracking structure.
1090 */
1091#define PGM_PAGE_GET_TD_CREFS(pPage) \
1092 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1093
1094/** @def PGM_PAGE_GET_TD_IDX
1095 * Gets the @a idx tracking data member.
1096 * @returns idx.
1097 * @param pPage Pointer to the physical guest page tracking structure.
1098 */
1099#define PGM_PAGE_GET_TD_IDX(pPage) \
1100 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1101
1102
1103/** Max number of locks on a page. */
1104#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1105
1106/** Get the read lock count.
1107 * @returns count.
1108 * @param pPage Pointer to the physical guest page tracking structure.
1109 */
1110#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1111
1112/** Get the write lock count.
1113 * @returns count.
1114 * @param pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1117
1118/** Decrement the read lock counter.
1119 * @param pPage Pointer to the physical guest page tracking structure.
1120 */
1121#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1122
1123/** Decrement the write lock counter.
1124 * @param pPage Pointer to the physical guest page tracking structure.
1125 */
1126#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1127
1128/** Increment the read lock counter.
1129 * @param pPage Pointer to the physical guest page tracking structure.
1130 */
1131#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1132
1133/** Increment the write lock counter.
1134 * @param pPage Pointer to the physical guest page tracking structure.
1135 */
1136#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1137
1138
1139#if 0
1140/** Enables sanity checking of write monitoring using CRC-32. */
1141# define PGMLIVESAVERAMPAGE_WITH_CRC32
1142#endif
1143
1144/**
1145 * Per page live save tracking data.
1146 */
1147typedef struct PGMLIVESAVERAMPAGE
1148{
1149 /** Number of times it has been dirtied. */
1150 uint32_t cDirtied : 24;
1151 /** Whether it is currently dirty. */
1152 uint32_t fDirty : 1;
1153 /** Ignore the page.
1154 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1155 * deal with these after pausing the VM and DevPCI have said it bit about
1156 * remappings. */
1157 uint32_t fIgnore : 1;
1158 /** Was a ZERO page last time around. */
1159 uint32_t fZero : 1;
1160 /** Was a SHARED page last time around. */
1161 uint32_t fShared : 1;
1162 /** Whether the page is/was write monitored in a previous pass. */
1163 uint32_t fWriteMonitored : 1;
1164 /** Whether the page is/was write monitored earlier in this pass. */
1165 uint32_t fWriteMonitoredJustNow : 1;
1166 /** Bits reserved for future use. */
1167 uint32_t u2Reserved : 2;
1168#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1169 /** CRC-32 for the page. This is for internal consistency checks. */
1170 uint32_t u32Crc;
1171#endif
1172} PGMLIVESAVERAMPAGE;
1173#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1174AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1175#else
1176AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1177#endif
1178/** Pointer to the per page live save tracking data. */
1179typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1180
1181/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1182#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1183
1184
1185/**
1186 * Ram range for GC Phys to HC Phys conversion.
1187 *
1188 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1189 * conversions too, but we'll let MM handle that for now.
1190 *
1191 * This structure is used by linked lists in both GC and HC.
1192 */
1193typedef struct PGMRAMRANGE
1194{
1195 /** Start of the range. Page aligned. */
1196 RTGCPHYS GCPhys;
1197 /** Size of the range. (Page aligned of course). */
1198 RTGCPHYS cb;
1199 /** Pointer to the next RAM range - for R3. */
1200 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1201 /** Pointer to the next RAM range - for R0. */
1202 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1203 /** Pointer to the next RAM range - for RC. */
1204 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1205 /** PGM_RAM_RANGE_FLAGS_* flags. */
1206 uint32_t fFlags;
1207 /** Last address in the range (inclusive). Page aligned (-1). */
1208 RTGCPHYS GCPhysLast;
1209 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1210 R3PTRTYPE(void *) pvR3;
1211 /** Live save per page tracking data. */
1212 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1213 /** The range description. */
1214 R3PTRTYPE(const char *) pszDesc;
1215 /** Pointer to self - R0 pointer. */
1216 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1217 /** Pointer to self - RC pointer. */
1218 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1219 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1220 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1221 /** Array of physical guest page tracking structures. */
1222 PGMPAGE aPages[1];
1223} PGMRAMRANGE;
1224/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1225typedef PGMRAMRANGE *PPGMRAMRANGE;
1226
1227/** @name PGMRAMRANGE::fFlags
1228 * @{ */
1229/** The RAM range is floating around as an independent guest mapping. */
1230#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1231/** Ad hoc RAM range for an ROM mapping. */
1232#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1233/** Ad hoc RAM range for an MMIO mapping. */
1234#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1235/** Ad hoc RAM range for an MMIO2 mapping. */
1236#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1237/** @} */
1238
1239/** Tests if a RAM range is an ad hoc one or not.
1240 * @returns true/false.
1241 * @param pRam The RAM range.
1242 */
1243#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1244 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1245
1246
1247/**
1248 * Per page tracking structure for ROM image.
1249 *
1250 * A ROM image may have a shadow page, in which case we may have two pages
1251 * backing it. This structure contains the PGMPAGE for both while
1252 * PGMRAMRANGE have a copy of the active one. It is important that these
1253 * aren't out of sync in any regard other than page pool tracking data.
1254 */
1255typedef struct PGMROMPAGE
1256{
1257 /** The page structure for the virgin ROM page. */
1258 PGMPAGE Virgin;
1259 /** The page structure for the shadow RAM page. */
1260 PGMPAGE Shadow;
1261 /** The current protection setting. */
1262 PGMROMPROT enmProt;
1263 /** Live save status information. Makes use of unused alignment space. */
1264 struct
1265 {
1266 /** The previous protection value. */
1267 uint8_t u8Prot;
1268 /** Written to flag set by the handler. */
1269 bool fWrittenTo;
1270 /** Whether the shadow page is dirty or not. */
1271 bool fDirty;
1272 /** Whether it was dirtied in the recently. */
1273 bool fDirtiedRecently;
1274 } LiveSave;
1275} PGMROMPAGE;
1276AssertCompileSizeAlignment(PGMROMPAGE, 8);
1277/** Pointer to a ROM page tracking structure. */
1278typedef PGMROMPAGE *PPGMROMPAGE;
1279
1280
1281/**
1282 * A registered ROM image.
1283 *
1284 * This is needed to keep track of ROM image since they generally intrude
1285 * into a PGMRAMRANGE. It also keeps track of additional info like the
1286 * two page sets (read-only virgin and read-write shadow), the current
1287 * state of each page.
1288 *
1289 * Because access handlers cannot easily be executed in a different
1290 * context, the ROM ranges needs to be accessible and in all contexts.
1291 */
1292typedef struct PGMROMRANGE
1293{
1294 /** Pointer to the next range - R3. */
1295 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1296 /** Pointer to the next range - R0. */
1297 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1298 /** Pointer to the next range - RC. */
1299 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1300 /** Pointer alignment */
1301 RTRCPTR RCPtrAlignment;
1302 /** Address of the range. */
1303 RTGCPHYS GCPhys;
1304 /** Address of the last byte in the range. */
1305 RTGCPHYS GCPhysLast;
1306 /** Size of the range. */
1307 RTGCPHYS cb;
1308 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1309 uint32_t fFlags;
1310 /** The saved state range ID. */
1311 uint8_t idSavedState;
1312 /** Alignment padding. */
1313 uint8_t au8Alignment[3];
1314 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1315 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1316 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1317 * This is used for strictness checks. */
1318 R3PTRTYPE(const void *) pvOriginal;
1319 /** The ROM description. */
1320 R3PTRTYPE(const char *) pszDesc;
1321 /** The per page tracking structures. */
1322 PGMROMPAGE aPages[1];
1323} PGMROMRANGE;
1324/** Pointer to a ROM range. */
1325typedef PGMROMRANGE *PPGMROMRANGE;
1326
1327
1328/**
1329 * Live save per page data for an MMIO2 page.
1330 *
1331 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1332 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1333 * CRC-32 for detecting changes as well as special handling of zero pages. This
1334 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1335 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1336 * because of speed (2.5x and 6x slower).)
1337 *
1338 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1339 * save but normally is disabled. Since we can write monitore guest
1340 * accesses on our own, we only need this for host accesses. Shouldn't be
1341 * too difficult for DevVGA, VMMDev might be doable, the planned
1342 * networking fun will be fun since it involves ring-0.
1343 */
1344typedef struct PGMLIVESAVEMMIO2PAGE
1345{
1346 /** Set if the page is considered dirty. */
1347 bool fDirty;
1348 /** The number of scans this page has remained unchanged for.
1349 * Only updated for dirty pages. */
1350 uint8_t cUnchangedScans;
1351 /** Whether this page was zero at the last scan. */
1352 bool fZero;
1353 /** Alignment padding. */
1354 bool fReserved;
1355 /** CRC-32 for the first half of the page.
1356 * This is used together with u32CrcH2 to quickly detect changes in the page
1357 * during the non-final passes. */
1358 uint32_t u32CrcH1;
1359 /** CRC-32 for the second half of the page. */
1360 uint32_t u32CrcH2;
1361 /** SHA-1 for the saved page.
1362 * This is used in the final pass to skip pages without changes. */
1363 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1364} PGMLIVESAVEMMIO2PAGE;
1365/** Pointer to a live save status data for an MMIO2 page. */
1366typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1367
1368/**
1369 * A registered MMIO2 (= Device RAM) range.
1370 *
1371 * There are a few reason why we need to keep track of these
1372 * registrations. One of them is the deregistration & cleanup stuff,
1373 * while another is that the PGMRAMRANGE associated with such a region may
1374 * have to be removed from the ram range list.
1375 *
1376 * Overlapping with a RAM range has to be 100% or none at all. The pages
1377 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1378 * will be raised if a partial overlap or an overlap of ROM pages is
1379 * encountered. On an overlap we will free all the existing RAM pages and
1380 * put in the ram range pages instead.
1381 */
1382typedef struct PGMMMIO2RANGE
1383{
1384 /** The owner of the range. (a device) */
1385 PPDMDEVINSR3 pDevInsR3;
1386 /** Pointer to the ring-3 mapping of the allocation. */
1387 RTR3PTR pvR3;
1388 /** Pointer to the next range - R3. */
1389 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1390 /** Whether it's mapped or not. */
1391 bool fMapped;
1392 /** Whether it's overlapping or not. */
1393 bool fOverlapping;
1394 /** The PCI region number.
1395 * @remarks This ASSUMES that nobody will ever really need to have multiple
1396 * PCI devices with matching MMIO region numbers on a single device. */
1397 uint8_t iRegion;
1398 /** The saved state range ID. */
1399 uint8_t idSavedState;
1400 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1401 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1402 /** Live save per page tracking data. */
1403 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1404 /** The associated RAM range. */
1405 PGMRAMRANGE RamRange;
1406} PGMMMIO2RANGE;
1407/** Pointer to a MMIO2 range. */
1408typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1409
1410
1411
1412
1413/**
1414 * PGMPhysRead/Write cache entry
1415 */
1416typedef struct PGMPHYSCACHEENTRY
1417{
1418 /** R3 pointer to physical page. */
1419 R3PTRTYPE(uint8_t *) pbR3;
1420 /** GC Physical address for cache entry */
1421 RTGCPHYS GCPhys;
1422#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1423 RTGCPHYS u32Padding0; /**< alignment padding. */
1424#endif
1425} PGMPHYSCACHEENTRY;
1426
1427/**
1428 * PGMPhysRead/Write cache to reduce REM memory access overhead
1429 */
1430typedef struct PGMPHYSCACHE
1431{
1432 /** Bitmap of valid cache entries */
1433 uint64_t aEntries;
1434 /** Cache entries */
1435 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1436} PGMPHYSCACHE;
1437
1438
1439/** Pointer to an allocation chunk ring-3 mapping. */
1440typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1441/** Pointer to an allocation chunk ring-3 mapping pointer. */
1442typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1443
1444/**
1445 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1446 *
1447 * The primary tree (Core) uses the chunk id as key.
1448 */
1449typedef struct PGMCHUNKR3MAP
1450{
1451 /** The key is the chunk id. */
1452 AVLU32NODECORE Core;
1453 /** The current age thingy. */
1454 uint32_t iAge;
1455 /** The current reference count. */
1456 uint32_t volatile cRefs;
1457 /** The current permanent reference count. */
1458 uint32_t volatile cPermRefs;
1459 /** The mapping address. */
1460 void *pv;
1461} PGMCHUNKR3MAP;
1462
1463/**
1464 * Allocation chunk ring-3 mapping TLB entry.
1465 */
1466typedef struct PGMCHUNKR3MAPTLBE
1467{
1468 /** The chunk id. */
1469 uint32_t volatile idChunk;
1470#if HC_ARCH_BITS == 64
1471 uint32_t u32Padding; /**< alignment padding. */
1472#endif
1473 /** The chunk map. */
1474#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1475 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1476#else
1477 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1478#endif
1479} PGMCHUNKR3MAPTLBE;
1480/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1481typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1482
1483/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1484 * @remark Must be a power of two value. */
1485#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1486
1487/**
1488 * Allocation chunk ring-3 mapping TLB.
1489 *
1490 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1491 * At first glance this might look kinda odd since AVL trees are
1492 * supposed to give the most optimial lookup times of all trees
1493 * due to their balancing. However, take a tree with 1023 nodes
1494 * in it, that's 10 levels, meaning that most searches has to go
1495 * down 9 levels before they find what they want. This isn't fast
1496 * compared to a TLB hit. There is the factor of cache misses,
1497 * and of course the problem with trees and branch prediction.
1498 * This is why we use TLBs in front of most of the trees.
1499 *
1500 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1501 * difficult when we switch to the new inlined AVL trees (from kStuff).
1502 */
1503typedef struct PGMCHUNKR3MAPTLB
1504{
1505 /** The TLB entries. */
1506 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1507} PGMCHUNKR3MAPTLB;
1508
1509/**
1510 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1511 * @returns Chunk TLB index.
1512 * @param idChunk The Chunk ID.
1513 */
1514#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1515
1516
1517/**
1518 * Ring-3 guest page mapping TLB entry.
1519 * @remarks used in ring-0 as well at the moment.
1520 */
1521typedef struct PGMPAGER3MAPTLBE
1522{
1523 /** Address of the page. */
1524 RTGCPHYS volatile GCPhys;
1525 /** The guest page. */
1526#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1527 R3PTRTYPE(PPGMPAGE) volatile pPage;
1528#else
1529 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1530#endif
1531 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1532#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1533 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1534#else
1535 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1536#endif
1537 /** The address */
1538#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1539 R3PTRTYPE(void *) volatile pv;
1540#else
1541 R3R0PTRTYPE(void *) volatile pv;
1542#endif
1543#if HC_ARCH_BITS == 32
1544 uint32_t u32Padding; /**< alignment padding. */
1545#endif
1546} PGMPAGER3MAPTLBE;
1547/** Pointer to an entry in the HC physical TLB. */
1548typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1549
1550
1551/** The number of entries in the ring-3 guest page mapping TLB.
1552 * @remarks The value must be a power of two. */
1553#define PGM_PAGER3MAPTLB_ENTRIES 256
1554
1555/**
1556 * Ring-3 guest page mapping TLB.
1557 * @remarks used in ring-0 as well at the moment.
1558 */
1559typedef struct PGMPAGER3MAPTLB
1560{
1561 /** The TLB entries. */
1562 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1563} PGMPAGER3MAPTLB;
1564/** Pointer to the ring-3 guest page mapping TLB. */
1565typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1566
1567/**
1568 * Calculates the index of the TLB entry for the specified guest page.
1569 * @returns Physical TLB index.
1570 * @param GCPhys The guest physical address.
1571 */
1572#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1573
1574
1575/**
1576 * Raw-mode context dynamic mapping cache entry.
1577 *
1578 * Because of raw-mode context being reloctable and all relocations are applied
1579 * in ring-3, this has to be defined here and be RC specfic.
1580 *
1581 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1582 */
1583typedef struct PGMRCDYNMAPENTRY
1584{
1585 /** The physical address of the currently mapped page.
1586 * This is duplicate for three reasons: cache locality, cache policy of the PT
1587 * mappings and sanity checks. */
1588 RTHCPHYS HCPhys;
1589 /** Pointer to the page. */
1590 RTRCPTR pvPage;
1591 /** The number of references. */
1592 int32_t volatile cRefs;
1593 /** PTE pointer union. */
1594 union PGMRCDYNMAPENTRY_PPTE
1595 {
1596 /** PTE pointer, 32-bit legacy version. */
1597 RCPTRTYPE(PX86PTE) pLegacy;
1598 /** PTE pointer, PAE version. */
1599 RCPTRTYPE(PX86PTEPAE) pPae;
1600 /** PTE pointer, the void version. */
1601 RTRCPTR pv;
1602 } uPte;
1603 /** Alignment padding. */
1604 RTRCPTR RCPtrAlignment;
1605} PGMRCDYNMAPENTRY;
1606/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1607typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1608
1609
1610/**
1611 * Dynamic mapping cache for the raw-mode context.
1612 *
1613 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1614 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1615 * so that we can perform relocations from PGMR3Relocate. This has the
1616 * consequence that we must have separate ring-0 and raw-mode context versions
1617 * of this struct even if they share the basic elements.
1618 *
1619 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1620 */
1621typedef struct PGMRCDYNMAP
1622{
1623 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1624 uint32_t u32Magic;
1625 /** Array for tracking and managing the pages. */
1626 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1627 /** The cache size given as a number of pages. */
1628 uint32_t cPages;
1629 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1630 bool fLegacyMode;
1631 /** The current load.
1632 * This does not include guard pages. */
1633 uint32_t cLoad;
1634 /** The max load ever.
1635 * This is maintained to get trigger adding of more mapping space. */
1636 uint32_t cMaxLoad;
1637 /** The number of guard pages. */
1638 uint32_t cGuardPages;
1639 /** The number of users (protected by hInitLock). */
1640 uint32_t cUsers;
1641} PGMRCDYNMAP;
1642/** Pointer to the dynamic cache for the raw-mode context. */
1643typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1644
1645
1646/**
1647 * Mapping cache usage set entry.
1648 *
1649 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1650 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1651 * cache. If it's extended to include ring-3, well, then something
1652 * will have be changed here...
1653 */
1654typedef struct PGMMAPSETENTRY
1655{
1656 /** Pointer to the page. */
1657#ifndef IN_RC
1658 RTR0PTR pvPage;
1659#else
1660 RTRCPTR pvPage;
1661# if HC_ARCH_BITS == 64
1662 uint32_t u32Alignment2;
1663# endif
1664#endif
1665 /** The mapping cache index. */
1666 uint16_t iPage;
1667 /** The number of references.
1668 * The max is UINT16_MAX - 1. */
1669 uint16_t cRefs;
1670 /** The number inlined references.
1671 * The max is UINT16_MAX - 1. */
1672 uint16_t cInlinedRefs;
1673 /** Unreferences. */
1674 uint16_t cUnrefs;
1675
1676#if HC_ARCH_BITS == 32
1677 uint32_t u32Alignment1;
1678#endif
1679 /** The physical address for this entry. */
1680 RTHCPHYS HCPhys;
1681} PGMMAPSETENTRY;
1682AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1683AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1684/** Pointer to a mapping cache usage set entry. */
1685typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1686
1687/**
1688 * Mapping cache usage set.
1689 *
1690 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1691 * done during exits / traps. The set is
1692 */
1693typedef struct PGMMAPSET
1694{
1695 /** The number of occupied entries.
1696 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1697 * dynamic mappings. */
1698 uint32_t cEntries;
1699 /** The start of the current subset.
1700 * This is UINT32_MAX if no subset is currently open. */
1701 uint32_t iSubset;
1702 /** The index of the current CPU, only valid if the set is open. */
1703 int32_t iCpu;
1704 uint32_t alignment;
1705 /** The entries. */
1706 PGMMAPSETENTRY aEntries[64];
1707 /** HCPhys -> iEntry fast lookup table.
1708 * Use PGMMAPSET_HASH for hashing.
1709 * The entries may or may not be valid, check against cEntries. */
1710 uint8_t aiHashTable[128];
1711} PGMMAPSET;
1712AssertCompileSizeAlignment(PGMMAPSET, 8);
1713/** Pointer to the mapping cache set. */
1714typedef PGMMAPSET *PPGMMAPSET;
1715
1716/** PGMMAPSET::cEntries value for a closed set. */
1717#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1718
1719/** Hash function for aiHashTable. */
1720#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1721
1722/** The max fill size (strict builds). */
1723#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1724
1725
1726/** @name Context neutrual page mapper TLB.
1727 *
1728 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1729 * code is writting in a kind of context neutrual way. Time will show whether
1730 * this actually makes sense or not...
1731 *
1732 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1733 * context ends up using a global mapping cache on some platforms
1734 * (darwin).
1735 *
1736 * @{ */
1737/** @typedef PPGMPAGEMAPTLB
1738 * The page mapper TLB pointer type for the current context. */
1739/** @typedef PPGMPAGEMAPTLB
1740 * The page mapper TLB entry pointer type for the current context. */
1741/** @typedef PPGMPAGEMAPTLB
1742 * The page mapper TLB entry pointer pointer type for the current context. */
1743/** @def PGM_PAGEMAPTLB_ENTRIES
1744 * The number of TLB entries in the page mapper TLB for the current context. */
1745/** @def PGM_PAGEMAPTLB_IDX
1746 * Calculate the TLB index for a guest physical address.
1747 * @returns The TLB index.
1748 * @param GCPhys The guest physical address. */
1749/** @typedef PPGMPAGEMAP
1750 * Pointer to a page mapper unit for current context. */
1751/** @typedef PPPGMPAGEMAP
1752 * Pointer to a page mapper unit pointer for current context. */
1753#ifdef IN_RC
1754// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1755// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1756// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1757# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1758# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1759 typedef void * PPGMPAGEMAP;
1760 typedef void ** PPPGMPAGEMAP;
1761//#elif IN_RING0
1762// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1763// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1764// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1765//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1766//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1767// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1768// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1769#else
1770 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1771 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1772 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1773# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1774# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1775 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1776 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1777#endif
1778/** @} */
1779
1780
1781/** @name PGM Pool Indexes.
1782 * Aka. the unique shadow page identifier.
1783 * @{ */
1784/** NIL page pool IDX. */
1785#define NIL_PGMPOOL_IDX 0
1786/** The first normal index. */
1787#define PGMPOOL_IDX_FIRST_SPECIAL 1
1788/** Page directory (32-bit root). */
1789#define PGMPOOL_IDX_PD 1
1790/** Page Directory Pointer Table (PAE root). */
1791#define PGMPOOL_IDX_PDPT 2
1792/** AMD64 CR3 level index.*/
1793#define PGMPOOL_IDX_AMD64_CR3 3
1794/** Nested paging root.*/
1795#define PGMPOOL_IDX_NESTED_ROOT 4
1796/** The first normal index. */
1797#define PGMPOOL_IDX_FIRST 5
1798/** The last valid index. (inclusive, 14 bits) */
1799#define PGMPOOL_IDX_LAST 0x3fff
1800/** @} */
1801
1802/** The NIL index for the parent chain. */
1803#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1804#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1805
1806/**
1807 * Node in the chain linking a shadowed page to it's parent (user).
1808 */
1809#pragma pack(1)
1810typedef struct PGMPOOLUSER
1811{
1812 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1813 uint16_t iNext;
1814 /** The user page index. */
1815 uint16_t iUser;
1816 /** Index into the user table. */
1817 uint32_t iUserTable;
1818} PGMPOOLUSER, *PPGMPOOLUSER;
1819typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1820#pragma pack()
1821
1822
1823/** The NIL index for the phys ext chain. */
1824#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1825/** The NIL pte index for a phys ext chain slot. */
1826#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1827
1828/**
1829 * Node in the chain of physical cross reference extents.
1830 * @todo Calling this an 'extent' is not quite right, find a better name.
1831 * @todo find out the optimal size of the aidx array
1832 */
1833#pragma pack(1)
1834typedef struct PGMPOOLPHYSEXT
1835{
1836 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1837 uint16_t iNext;
1838 /** Alignment. */
1839 uint16_t u16Align;
1840 /** The user page index. */
1841 uint16_t aidx[3];
1842 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1843 uint16_t apte[3];
1844} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1845typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1846#pragma pack()
1847
1848
1849/**
1850 * The kind of page that's being shadowed.
1851 */
1852typedef enum PGMPOOLKIND
1853{
1854 /** The virtual invalid 0 entry. */
1855 PGMPOOLKIND_INVALID = 0,
1856 /** The entry is free (=unused). */
1857 PGMPOOLKIND_FREE,
1858
1859 /** Shw: 32-bit page table; Gst: no paging */
1860 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1861 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1862 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1863 /** Shw: 32-bit page table; Gst: 4MB page. */
1864 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1865 /** Shw: PAE page table; Gst: no paging */
1866 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1867 /** Shw: PAE page table; Gst: 32-bit page table. */
1868 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1869 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1870 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1871 /** Shw: PAE page table; Gst: PAE page table. */
1872 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1873 /** Shw: PAE page table; Gst: 2MB page. */
1874 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1875
1876 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1877 PGMPOOLKIND_32BIT_PD,
1878 /** Shw: 32-bit page directory. Gst: no paging. */
1879 PGMPOOLKIND_32BIT_PD_PHYS,
1880 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1881 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1882 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1883 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1884 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1885 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1886 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1887 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1888 /** Shw: PAE page directory; Gst: PAE page directory. */
1889 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1890 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1891 PGMPOOLKIND_PAE_PD_PHYS,
1892
1893 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1894 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1895 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1896 PGMPOOLKIND_PAE_PDPT,
1897 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1898 PGMPOOLKIND_PAE_PDPT_PHYS,
1899
1900 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1901 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1902 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1903 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1904 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1905 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1906 /** Shw: 64-bit page directory table; Gst: no paging */
1907 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1908
1909 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1910 PGMPOOLKIND_64BIT_PML4,
1911
1912 /** Shw: EPT page directory pointer table; Gst: no paging */
1913 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1914 /** Shw: EPT page directory table; Gst: no paging */
1915 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1916 /** Shw: EPT page table; Gst: no paging */
1917 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1918
1919 /** Shw: Root Nested paging table. */
1920 PGMPOOLKIND_ROOT_NESTED,
1921
1922 /** The last valid entry. */
1923 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1924} PGMPOOLKIND;
1925
1926/**
1927 * The access attributes of the page; only applies to big pages.
1928 */
1929typedef enum
1930{
1931 PGMPOOLACCESS_DONTCARE = 0,
1932 PGMPOOLACCESS_USER_RW,
1933 PGMPOOLACCESS_USER_R,
1934 PGMPOOLACCESS_USER_RW_NX,
1935 PGMPOOLACCESS_USER_R_NX,
1936 PGMPOOLACCESS_SUPERVISOR_RW,
1937 PGMPOOLACCESS_SUPERVISOR_R,
1938 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1939 PGMPOOLACCESS_SUPERVISOR_R_NX
1940} PGMPOOLACCESS;
1941
1942/**
1943 * The tracking data for a page in the pool.
1944 */
1945typedef struct PGMPOOLPAGE
1946{
1947 /** AVL node code with the (R3) physical address of this page. */
1948 AVLOHCPHYSNODECORE Core;
1949 /** Pointer to the R3 mapping of the page. */
1950#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1951 R3PTRTYPE(void *) pvPageR3;
1952#else
1953 R3R0PTRTYPE(void *) pvPageR3;
1954#endif
1955 /** The guest physical address. */
1956#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1957 uint32_t Alignment0;
1958#endif
1959 RTGCPHYS GCPhys;
1960
1961 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1962 RTGCPTR pvLastAccessHandlerRip;
1963 RTGCPTR pvLastAccessHandlerFault;
1964 uint64_t cLastAccessHandlerCount;
1965
1966 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1967 uint8_t enmKind;
1968 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1969 uint8_t enmAccess;
1970 /** The index of this page. */
1971 uint16_t idx;
1972 /** The next entry in the list this page currently resides in.
1973 * It's either in the free list or in the GCPhys hash. */
1974 uint16_t iNext;
1975 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1976 uint16_t iUserHead;
1977 /** The number of present entries. */
1978 uint16_t cPresent;
1979 /** The first entry in the table which is present. */
1980 uint16_t iFirstPresent;
1981 /** The number of modifications to the monitored page. */
1982 uint16_t cModifications;
1983 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1984 uint16_t iModifiedNext;
1985 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1986 uint16_t iModifiedPrev;
1987 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1988 uint16_t iMonitoredNext;
1989 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1990 uint16_t iMonitoredPrev;
1991 /** The next page in the age list. */
1992 uint16_t iAgeNext;
1993 /** The previous page in the age list. */
1994 uint16_t iAgePrev;
1995 /** Used to indicate that the page is zeroed. */
1996 bool fZeroed;
1997 /** Used to indicate that a PT has non-global entries. */
1998 bool fSeenNonGlobal;
1999 /** Used to indicate that we're monitoring writes to the guest page. */
2000 bool fMonitored;
2001 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2002 * (All pages are in the age list.) */
2003 bool fCached;
2004 /** This is used by the R3 access handlers when invoked by an async thread.
2005 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2006 bool volatile fReusedFlushPending;
2007 /** Used to mark the page as dirty (write monitoring is temporarily
2008 * off). */
2009 bool fDirty;
2010
2011 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2012 uint32_t cLocked;
2013 uint32_t idxDirty;
2014 RTGCPTR pvDirtyFault;
2015} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2016/** Pointer to a const pool page. */
2017typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2018
2019
2020/** The hash table size. */
2021# define PGMPOOL_HASH_SIZE 0x40
2022/** The hash function. */
2023# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2024
2025
2026/**
2027 * The shadow page pool instance data.
2028 *
2029 * It's all one big allocation made at init time, except for the
2030 * pages that is. The user nodes follows immediatly after the
2031 * page structures.
2032 */
2033typedef struct PGMPOOL
2034{
2035 /** The VM handle - R3 Ptr. */
2036 PVMR3 pVMR3;
2037 /** The VM handle - R0 Ptr. */
2038 PVMR0 pVMR0;
2039 /** The VM handle - RC Ptr. */
2040 PVMRC pVMRC;
2041 /** The max pool size. This includes the special IDs. */
2042 uint16_t cMaxPages;
2043 /** The current pool size. */
2044 uint16_t cCurPages;
2045 /** The head of the free page list. */
2046 uint16_t iFreeHead;
2047 /* Padding. */
2048 uint16_t u16Padding;
2049 /** Head of the chain of free user nodes. */
2050 uint16_t iUserFreeHead;
2051 /** The number of user nodes we've allocated. */
2052 uint16_t cMaxUsers;
2053 /** The number of present page table entries in the entire pool. */
2054 uint32_t cPresent;
2055 /** Pointer to the array of user nodes - RC pointer. */
2056 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2057 /** Pointer to the array of user nodes - R3 pointer. */
2058 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2059 /** Pointer to the array of user nodes - R0 pointer. */
2060 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2061 /** Head of the chain of free phys ext nodes. */
2062 uint16_t iPhysExtFreeHead;
2063 /** The number of user nodes we've allocated. */
2064 uint16_t cMaxPhysExts;
2065 /** Pointer to the array of physical xref extent - RC pointer. */
2066 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2067 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2068 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2069 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2070 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2071 /** Hash table for GCPhys addresses. */
2072 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2073 /** The head of the age list. */
2074 uint16_t iAgeHead;
2075 /** The tail of the age list. */
2076 uint16_t iAgeTail;
2077 /** Set if the cache is enabled. */
2078 bool fCacheEnabled;
2079 /** Alignment padding. */
2080 bool afPadding1[3];
2081 /** Head of the list of modified pages. */
2082 uint16_t iModifiedHead;
2083 /** The current number of modified pages. */
2084 uint16_t cModifiedPages;
2085 /** Access handler, RC. */
2086 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2087 /** Access handler, R0. */
2088 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2089 /** Access handler, R3. */
2090 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2091 /** The access handler description (R3 ptr). */
2092 R3PTRTYPE(const char *) pszAccessHandler;
2093# if HC_ARCH_BITS == 32
2094 /** Alignment padding. */
2095 uint32_t u32Padding2;
2096# endif
2097 /* Next available slot. */
2098 uint32_t idxFreeDirtyPage;
2099 /* Number of active dirty pages. */
2100 uint32_t cDirtyPages;
2101 /* Array of current dirty pgm pool page indices. */
2102 uint16_t aIdxDirtyPages[16];
2103 uint64_t aDirtyPages[16][512];
2104 /** The number of pages currently in use. */
2105 uint16_t cUsedPages;
2106#ifdef VBOX_WITH_STATISTICS
2107 /** The high water mark for cUsedPages. */
2108 uint16_t cUsedPagesHigh;
2109 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
2110 /** Profiling pgmPoolAlloc(). */
2111 STAMPROFILEADV StatAlloc;
2112 /** Profiling pgmR3PoolClearDoIt(). */
2113 STAMPROFILE StatClearAll;
2114 /** Profiling pgmR3PoolReset(). */
2115 STAMPROFILE StatR3Reset;
2116 /** Profiling pgmPoolFlushPage(). */
2117 STAMPROFILE StatFlushPage;
2118 /** Profiling pgmPoolFree(). */
2119 STAMPROFILE StatFree;
2120 /** Counting explicit flushes by PGMPoolFlushPage(). */
2121 STAMCOUNTER StatForceFlushPage;
2122 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2123 STAMCOUNTER StatForceFlushDirtyPage;
2124 /** Counting flushes for reused pages. */
2125 STAMCOUNTER StatForceFlushReused;
2126 /** Profiling time spent zeroing pages. */
2127 STAMPROFILE StatZeroPage;
2128 /** Profiling of pgmPoolTrackDeref. */
2129 STAMPROFILE StatTrackDeref;
2130 /** Profiling pgmTrackFlushGCPhysPT. */
2131 STAMPROFILE StatTrackFlushGCPhysPT;
2132 /** Profiling pgmTrackFlushGCPhysPTs. */
2133 STAMPROFILE StatTrackFlushGCPhysPTs;
2134 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2135 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2136 /** Number of times we've been out of user records. */
2137 STAMCOUNTER StatTrackFreeUpOneUser;
2138 /** Nr of flushed entries. */
2139 STAMCOUNTER StatTrackFlushEntry;
2140 /** Nr of updated entries. */
2141 STAMCOUNTER StatTrackFlushEntryKeep;
2142 /** Profiling deref activity related tracking GC physical pages. */
2143 STAMPROFILE StatTrackDerefGCPhys;
2144 /** Number of linear searches for a HCPhys in the ram ranges. */
2145 STAMCOUNTER StatTrackLinearRamSearches;
2146 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2147 STAMCOUNTER StamTrackPhysExtAllocFailures;
2148 /** Profiling the RC/R0 access handler. */
2149 STAMPROFILE StatMonitorRZ;
2150 /** Times we've failed interpreting the instruction. */
2151 STAMCOUNTER StatMonitorRZEmulateInstr;
2152 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2153 STAMPROFILE StatMonitorRZFlushPage;
2154 /* Times we've detected a page table reinit. */
2155 STAMCOUNTER StatMonitorRZFlushReinit;
2156 /** Counting flushes for pages that are modified too often. */
2157 STAMCOUNTER StatMonitorRZFlushModOverflow;
2158 /** Times we've detected fork(). */
2159 STAMCOUNTER StatMonitorRZFork;
2160 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2161 STAMPROFILE StatMonitorRZHandled;
2162 /** Times we've failed interpreting a patch code instruction. */
2163 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2164 /** Times we've failed interpreting a patch code instruction during flushing. */
2165 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2166 /** The number of times we've seen rep prefixes we can't handle. */
2167 STAMCOUNTER StatMonitorRZRepPrefix;
2168 /** Profiling the REP STOSD cases we've handled. */
2169 STAMPROFILE StatMonitorRZRepStosd;
2170 /** Nr of handled PT faults. */
2171 STAMCOUNTER StatMonitorRZFaultPT;
2172 /** Nr of handled PD faults. */
2173 STAMCOUNTER StatMonitorRZFaultPD;
2174 /** Nr of handled PDPT faults. */
2175 STAMCOUNTER StatMonitorRZFaultPDPT;
2176 /** Nr of handled PML4 faults. */
2177 STAMCOUNTER StatMonitorRZFaultPML4;
2178
2179 /** Profiling the R3 access handler. */
2180 STAMPROFILE StatMonitorR3;
2181 /** Times we've failed interpreting the instruction. */
2182 STAMCOUNTER StatMonitorR3EmulateInstr;
2183 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2184 STAMPROFILE StatMonitorR3FlushPage;
2185 /* Times we've detected a page table reinit. */
2186 STAMCOUNTER StatMonitorR3FlushReinit;
2187 /** Counting flushes for pages that are modified too often. */
2188 STAMCOUNTER StatMonitorR3FlushModOverflow;
2189 /** Times we've detected fork(). */
2190 STAMCOUNTER StatMonitorR3Fork;
2191 /** Profiling the R3 access we've handled (except REP STOSD). */
2192 STAMPROFILE StatMonitorR3Handled;
2193 /** The number of times we've seen rep prefixes we can't handle. */
2194 STAMCOUNTER StatMonitorR3RepPrefix;
2195 /** Profiling the REP STOSD cases we've handled. */
2196 STAMPROFILE StatMonitorR3RepStosd;
2197 /** Nr of handled PT faults. */
2198 STAMCOUNTER StatMonitorR3FaultPT;
2199 /** Nr of handled PD faults. */
2200 STAMCOUNTER StatMonitorR3FaultPD;
2201 /** Nr of handled PDPT faults. */
2202 STAMCOUNTER StatMonitorR3FaultPDPT;
2203 /** Nr of handled PML4 faults. */
2204 STAMCOUNTER StatMonitorR3FaultPML4;
2205 /** The number of times we're called in an async thread an need to flush. */
2206 STAMCOUNTER StatMonitorR3Async;
2207 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2208 STAMCOUNTER StatResetDirtyPages;
2209 /** Times we've called pgmPoolAddDirtyPage. */
2210 STAMCOUNTER StatDirtyPage;
2211 /** Times we've had to flush duplicates for dirty page management. */
2212 STAMCOUNTER StatDirtyPageDupFlush;
2213 /** Times we've had to flush because of overflow. */
2214 STAMCOUNTER StatDirtyPageOverFlowFlush;
2215
2216 /** The high wather mark for cModifiedPages. */
2217 uint16_t cModifiedPagesHigh;
2218 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2219
2220 /** The number of cache hits. */
2221 STAMCOUNTER StatCacheHits;
2222 /** The number of cache misses. */
2223 STAMCOUNTER StatCacheMisses;
2224 /** The number of times we've got a conflict of 'kind' in the cache. */
2225 STAMCOUNTER StatCacheKindMismatches;
2226 /** Number of times we've been out of pages. */
2227 STAMCOUNTER StatCacheFreeUpOne;
2228 /** The number of cacheable allocations. */
2229 STAMCOUNTER StatCacheCacheable;
2230 /** The number of uncacheable allocations. */
2231 STAMCOUNTER StatCacheUncacheable;
2232#else
2233 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2234#endif
2235 /** The AVL tree for looking up a page by its HC physical address. */
2236 AVLOHCPHYSTREE HCPhysTree;
2237 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2238 /** Array of pages. (cMaxPages in length)
2239 * The Id is the index into thist array.
2240 */
2241 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2242} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2243AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2244AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2245AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2246#ifdef VBOX_WITH_STATISTICS
2247AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2248#endif
2249AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2250
2251
2252/** @def PGMPOOL_PAGE_2_PTR
2253 * Maps a pool page pool into the current context.
2254 *
2255 * @returns VBox status code.
2256 * @param pVM The VM handle.
2257 * @param pPage The pool page.
2258 *
2259 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2260 * small page window employeed by that function. Be careful.
2261 * @remark There is no need to assert on the result.
2262 */
2263#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2264# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2265#elif defined(VBOX_STRICT)
2266# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2267DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2268{
2269 Assert(pPage && pPage->pvPageR3);
2270 return pPage->pvPageR3;
2271}
2272#else
2273# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2274#endif
2275
2276
2277/** @def PGMPOOL_PAGE_2_PTR_V2
2278 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2279 *
2280 * @returns VBox status code.
2281 * @param pVM The VM handle.
2282 * @param pVCpu The current CPU.
2283 * @param pPage The pool page.
2284 *
2285 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2286 * small page window employeed by that function. Be careful.
2287 * @remark There is no need to assert on the result.
2288 */
2289#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2290# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2291#else
2292# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2293#endif
2294
2295
2296/** @name Per guest page tracking data.
2297 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2298 * is to use more bits for it and split it up later on. But for now we'll play
2299 * safe and change as little as possible.
2300 *
2301 * The 16-bit word has two parts:
2302 *
2303 * The first 14-bit forms the @a idx field. It is either the index of a page in
2304 * the shadow page pool, or and index into the extent list.
2305 *
2306 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2307 * shadow page pool references to the page. If cRefs equals
2308 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2309 * (misnomer) table and not the shadow page pool.
2310 *
2311 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2312 * the 16-bit word.
2313 *
2314 * @{ */
2315/** The shift count for getting to the cRefs part. */
2316#define PGMPOOL_TD_CREFS_SHIFT 14
2317/** The mask applied after shifting the tracking data down by
2318 * PGMPOOL_TD_CREFS_SHIFT. */
2319#define PGMPOOL_TD_CREFS_MASK 0x3
2320/** The cRef value used to indiciate that the idx is the head of a
2321 * physical cross reference list. */
2322#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2323/** The shift used to get idx. */
2324#define PGMPOOL_TD_IDX_SHIFT 0
2325/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2326#define PGMPOOL_TD_IDX_MASK 0x3fff
2327/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2328 * simply too many mappings of this page. */
2329#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2330
2331/** @def PGMPOOL_TD_MAKE
2332 * Makes a 16-bit tracking data word.
2333 *
2334 * @returns tracking data.
2335 * @param cRefs The @a cRefs field. Must be within bounds!
2336 * @param idx The @a idx field. Must also be within bounds! */
2337#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2338
2339/** @def PGMPOOL_TD_GET_CREFS
2340 * Get the @a cRefs field from a tracking data word.
2341 *
2342 * @returns The @a cRefs field
2343 * @param u16 The tracking data word.
2344 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2345 * non-zero @a u16. */
2346#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2347
2348/** @def PGMPOOL_TD_GET_IDX
2349 * Get the @a idx field from a tracking data word.
2350 *
2351 * @returns The @a idx field
2352 * @param u16 The tracking data word. */
2353#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2354/** @} */
2355
2356
2357/**
2358 * Trees are using self relative offsets as pointers.
2359 * So, all its data, including the root pointer, must be in the heap for HC and GC
2360 * to have the same layout.
2361 */
2362typedef struct PGMTREES
2363{
2364 /** Physical access handlers (AVL range+offsetptr tree). */
2365 AVLROGCPHYSTREE PhysHandlers;
2366 /** Virtual access handlers (AVL range + GC ptr tree). */
2367 AVLROGCPTRTREE VirtHandlers;
2368 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2369 AVLROGCPHYSTREE PhysToVirtHandlers;
2370 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2371 AVLROGCPTRTREE HyperVirtHandlers;
2372} PGMTREES;
2373/** Pointer to PGM trees. */
2374typedef PGMTREES *PPGMTREES;
2375
2376
2377/**
2378 * Page fault guest state for the AMD64 paging mode.
2379 */
2380typedef struct PGMPTWALKCORE
2381{
2382 /** The guest virtual address that is being resolved by the walk
2383 * (input). */
2384 RTGCPTR GCPtr;
2385
2386 /** The guest physcial address that is the result of the walk.
2387 * @remarks only valid if fSucceeded is set. */
2388 RTGCPHYS GCPhys;
2389
2390 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2391 bool fSucceeded;
2392 /** The level problem arrised at.
2393 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2394 * level 8. This is 0 on success. */
2395 uint8_t uLevel;
2396 /** Set if the page isn't present. */
2397 bool fNotPresent;
2398 /** Encountered a bad physical address. */
2399 bool fBadPhysAddr;
2400 /** Set if there was reserved bit violations. */
2401 bool fRsvdError;
2402 /** Set if it involves a big page (2/4 MB). */
2403 bool fBigPage;
2404 /** Set if it involves a gigantic page (1 GB). */
2405 bool fGigantPage;
2406 /** The effect X86_PTE_US flag for the address. */
2407 bool fEffectiveUS;
2408 /** The effect X86_PTE_RW flag for the address. */
2409 bool fEffectiveRW;
2410 /** The effect X86_PTE_NX flag for the address. */
2411 bool fEffectiveNX;
2412} PGMPTWALKCORE;
2413
2414
2415/**
2416 * Guest page table walk for the AMD64 mode.
2417 */
2418typedef struct PGMPTWALKGSTAMD64
2419{
2420 /** The common core. */
2421 PGMPTWALKCORE Core;
2422
2423 PX86PML4 pPml4;
2424 PX86PML4E pPml4e;
2425 X86PML4E Pml4e;
2426
2427 PX86PDPT pPdpt;
2428 PX86PDPE pPdpe;
2429 X86PDPE Pdpe;
2430
2431 PX86PDPAE pPd;
2432 PX86PDEPAE pPde;
2433 X86PDEPAE Pde;
2434
2435 PX86PTPAE pPt;
2436 PX86PTEPAE pPte;
2437 X86PTEPAE Pte;
2438} PGMPTWALKGSTAMD64;
2439/** Pointer to a AMD64 guest page table walk. */
2440typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2441/** Pointer to a const AMD64 guest page table walk. */
2442typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2443
2444/**
2445 * Guest page table walk for the PAE mode.
2446 */
2447typedef struct PGMPTWALKGSTPAE
2448{
2449 /** The common core. */
2450 PGMPTWALKCORE Core;
2451
2452 PX86PDPT pPdpt;
2453 PX86PDPE pPdpe;
2454 X86PDPE Pdpe;
2455
2456 PX86PDPAE pPd;
2457 PX86PDEPAE pPde;
2458 X86PDEPAE Pde;
2459
2460 PX86PTPAE pPt;
2461 PX86PTEPAE pPte;
2462 X86PTEPAE Pte;
2463} PGMPTWALKGSTPAE;
2464/** Pointer to a PAE guest page table walk. */
2465typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2466/** Pointer to a const AMD64 guest page table walk. */
2467typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2468
2469/**
2470 * Guest page table walk for the 32-bit mode.
2471 */
2472typedef struct PGMPTWALKGST32BIT
2473{
2474 /** The common core. */
2475 PGMPTWALKCORE Core;
2476
2477 PX86PD pPd;
2478 PX86PDE pPde;
2479 X86PDE Pde;
2480
2481 PX86PT pPt;
2482 PX86PTE pPte;
2483 X86PTE Pte;
2484} PGMPTWALKGST32BIT;
2485/** Pointer to a 32-bit guest page table walk. */
2486typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2487/** Pointer to a const 32-bit guest page table walk. */
2488typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2489
2490
2491/** @name Paging mode macros
2492 * @{
2493 */
2494#ifdef IN_RC
2495# define PGM_CTX(a,b) a##RC##b
2496# define PGM_CTX_STR(a,b) a "GC" b
2497# define PGM_CTX_DECL(type) VMMRCDECL(type)
2498#else
2499# ifdef IN_RING3
2500# define PGM_CTX(a,b) a##R3##b
2501# define PGM_CTX_STR(a,b) a "R3" b
2502# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2503# else
2504# define PGM_CTX(a,b) a##R0##b
2505# define PGM_CTX_STR(a,b) a "R0" b
2506# define PGM_CTX_DECL(type) VMMDECL(type)
2507# endif
2508#endif
2509
2510#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2511#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2512#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2513#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2514#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2515#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2516#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2517#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2518#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2519#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2520#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2521#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2522#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2523#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2524#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2525#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2526#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2527
2528#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2529#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2530#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2531#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2532#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2533#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2534#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2535#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2536#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2537#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2538#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2539#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2540#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2541#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2542#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2543#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2544#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2545
2546/* Shw_Gst */
2547#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2548#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2549#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2550#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2551#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2552#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2553#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2554#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2555#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2556#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2557#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2558#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2559#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2560#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2561#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2562#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2563#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2564#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2565#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2566
2567#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2568#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2569#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2570#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2571#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2572#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2573#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2574#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2575#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2576#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2577#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2578#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2579#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2580#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2581#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2582#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2583#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2584#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2585#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2586#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2587#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2588#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2589#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2590#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2591#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2592#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2593#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2594#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2595#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2596#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2597#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2598#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2599#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2600#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2601#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2602#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2603#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2604
2605#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2606#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2607/** @} */
2608
2609/**
2610 * Data for each paging mode.
2611 */
2612typedef struct PGMMODEDATA
2613{
2614 /** The guest mode type. */
2615 uint32_t uGstType;
2616 /** The shadow mode type. */
2617 uint32_t uShwType;
2618
2619 /** @name Function pointers for Shadow paging.
2620 * @{
2621 */
2622 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2623 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2624 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2625 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2626
2627 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2628 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2629
2630 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2631 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2632 /** @} */
2633
2634 /** @name Function pointers for Guest paging.
2635 * @{
2636 */
2637 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2638 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2639 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2640 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2641 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2642 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2643 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2644 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2645 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2646 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2647 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2648 /** @} */
2649
2650 /** @name Function pointers for Both Shadow and Guest paging.
2651 * @{
2652 */
2653 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2654 /* no pfnR3BthTrap0eHandler */
2655 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2656 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2657 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2658 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2659#ifdef VBOX_STRICT
2660 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2661#endif
2662 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2663 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2664
2665 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2666 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2667 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2668 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2669 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2670#ifdef VBOX_STRICT
2671 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2672#endif
2673 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2674 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2675
2676 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2677 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2678 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2679 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2680 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2681#ifdef VBOX_STRICT
2682 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2683#endif
2684 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2685 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2686 /** @} */
2687} PGMMODEDATA, *PPGMMODEDATA;
2688
2689
2690#ifdef VBOX_WITH_STATISTICS
2691/**
2692 * PGM statistics.
2693 *
2694 * These lives on the heap when compiled in as they would otherwise waste
2695 * unecessary space in release builds.
2696 */
2697typedef struct PGMSTATS
2698{
2699 /* R3 only: */
2700 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2701 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2702
2703 /* R3+RZ */
2704 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2705 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2706 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2707 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2708 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2709 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2710 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2711 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2712 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2713 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2714 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2715 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2716 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2717 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2718 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2719 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2720 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2721 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2722 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2723 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2724 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2725 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2726 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2727 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2728/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2729 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2730 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2731/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2732
2733 /* RC only: */
2734 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2735 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2736
2737 STAMCOUNTER StatRZPhysRead;
2738 STAMCOUNTER StatRZPhysReadBytes;
2739 STAMCOUNTER StatRZPhysWrite;
2740 STAMCOUNTER StatRZPhysWriteBytes;
2741 STAMCOUNTER StatR3PhysRead;
2742 STAMCOUNTER StatR3PhysReadBytes;
2743 STAMCOUNTER StatR3PhysWrite;
2744 STAMCOUNTER StatR3PhysWriteBytes;
2745 STAMCOUNTER StatRCPhysRead;
2746 STAMCOUNTER StatRCPhysReadBytes;
2747 STAMCOUNTER StatRCPhysWrite;
2748 STAMCOUNTER StatRCPhysWriteBytes;
2749
2750 STAMCOUNTER StatRZPhysSimpleRead;
2751 STAMCOUNTER StatRZPhysSimpleReadBytes;
2752 STAMCOUNTER StatRZPhysSimpleWrite;
2753 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2754 STAMCOUNTER StatR3PhysSimpleRead;
2755 STAMCOUNTER StatR3PhysSimpleReadBytes;
2756 STAMCOUNTER StatR3PhysSimpleWrite;
2757 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2758 STAMCOUNTER StatRCPhysSimpleRead;
2759 STAMCOUNTER StatRCPhysSimpleReadBytes;
2760 STAMCOUNTER StatRCPhysSimpleWrite;
2761 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2762
2763 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2764 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2765 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2766 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2767 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2768 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2769 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2770
2771 /** Time spent by the host OS for large page allocation. */
2772 STAMPROFILE StatAllocLargePage;
2773 /** Time spent clearing the newly allocated large pages. */
2774 STAMPROFILE StatClearLargePage;
2775 /** pgmPhysIsValidLargePage profiling - R3 */
2776 STAMPROFILE StatR3IsValidLargePage;
2777 /** pgmPhysIsValidLargePage profiling - RZ*/
2778 STAMPROFILE StatRZIsValidLargePage;
2779
2780 STAMPROFILE StatChunkAging;
2781 STAMPROFILE StatChunkFindCandidate;
2782 STAMPROFILE StatChunkUnmap;
2783 STAMPROFILE StatChunkMap;
2784} PGMSTATS;
2785#endif /* VBOX_WITH_STATISTICS */
2786
2787
2788/**
2789 * Converts a PGM pointer into a VM pointer.
2790 * @returns Pointer to the VM structure the PGM is part of.
2791 * @param pPGM Pointer to PGM instance data.
2792 */
2793#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2794
2795/**
2796 * PGM Data (part of VM)
2797 */
2798typedef struct PGM
2799{
2800 /** Offset to the VM structure. */
2801 int32_t offVM;
2802 /** Offset of the PGMCPU structure relative to VMCPU. */
2803 int32_t offVCpuPGM;
2804
2805 /** @cfgm{RamPreAlloc, boolean, false}
2806 * Indicates whether the base RAM should all be allocated before starting
2807 * the VM (default), or if it should be allocated when first written to.
2808 */
2809 bool fRamPreAlloc;
2810 /** Indicates whether write monitoring is currently in use.
2811 * This is used to prevent conflicts between live saving and page sharing
2812 * detection. */
2813 bool fPhysWriteMonitoringEngaged;
2814 /** Set if the CPU has less than 52-bit physical address width.
2815 * This is used */
2816 bool fLessThan52PhysicalAddressBits;
2817 /** Set when nested paging is active.
2818 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2819 * compilers optimize the code better. Whether we use nested paging or
2820 * not is something we find out during VMM initialization and we won't
2821 * change this later on. */
2822 bool fNestedPaging;
2823 /** The host paging mode. (This is what SUPLib reports.) */
2824 SUPPAGINGMODE enmHostMode;
2825 /** We're not in a state which permits writes to guest memory.
2826 * (Only used in strict builds.) */
2827 bool fNoMorePhysWrites;
2828 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2829 bool afAlignment1[3];
2830
2831 /** Indicates that PGMR3FinalizeMappings has been called and that further
2832 * PGMR3MapIntermediate calls will be rejected. */
2833 bool fFinalizedMappings;
2834 /** If set no conflict checks are required. */
2835 bool fMappingsFixed;
2836 /** If set if restored as fixed but we were unable to re-fixate at the old
2837 * location because of room or address incompatibilities. */
2838 bool fMappingsFixedRestored;
2839 /** If set, then no mappings are put into the shadow page table.
2840 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2841 bool fMappingsDisabled;
2842 /** Size of fixed mapping.
2843 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2844 uint32_t cbMappingFixed;
2845 /** Generation ID for the RAM ranges. This member is incremented everytime
2846 * a RAM range is linked or unlinked. */
2847 uint32_t volatile idRamRangesGen;
2848
2849 /** Base address (GC) of fixed mapping.
2850 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2851 RTGCPTR GCPtrMappingFixed;
2852 /** The address of the previous RAM range mapping. */
2853 RTGCPTR GCPtrPrevRamRangeMapping;
2854
2855 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2856 RTGCPHYS GCPhys4MBPSEMask;
2857 /** Mask containing the invalid bits of a guest physical address.
2858 * @remarks this does not stop at bit 52. */
2859 RTGCPHYS GCPhysInvAddrMask;
2860
2861
2862 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2863 * This is sorted by physical address and contains no overlapping ranges. */
2864 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2865 /** PGM offset based trees - R3 Ptr. */
2866 R3PTRTYPE(PPGMTREES) pTreesR3;
2867 /** Caching the last physical handler we looked up in R3. */
2868 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2869 /** Shadow Page Pool - R3 Ptr. */
2870 R3PTRTYPE(PPGMPOOL) pPoolR3;
2871 /** Linked list of GC mappings - for HC.
2872 * The list is sorted ascending on address. */
2873 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2874 /** Pointer to the list of ROM ranges - for R3.
2875 * This is sorted by physical address and contains no overlapping ranges. */
2876 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2877 /** Pointer to the list of MMIO2 ranges - for R3.
2878 * Registration order. */
2879 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2880 /** Pointer to SHW+GST mode data (function pointers).
2881 * The index into this table is made up from */
2882 R3PTRTYPE(PPGMMODEDATA) paModeData;
2883 /*RTR3PTR R3PtrAlignment0;*/
2884
2885
2886 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2887 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2888 /** PGM offset based trees - R0 Ptr. */
2889 R0PTRTYPE(PPGMTREES) pTreesR0;
2890 /** Caching the last physical handler we looked up in R0. */
2891 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2892 /** Shadow Page Pool - R0 Ptr. */
2893 R0PTRTYPE(PPGMPOOL) pPoolR0;
2894 /** Linked list of GC mappings - for R0.
2895 * The list is sorted ascending on address. */
2896 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2897 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2898 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2899 /*RTR0PTR R0PtrAlignment0;*/
2900
2901
2902 /** RC pointer corresponding to PGM::pRamRangesR3. */
2903 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2904 /** PGM offset based trees - RC Ptr. */
2905 RCPTRTYPE(PPGMTREES) pTreesRC;
2906 /** Caching the last physical handler we looked up in RC. */
2907 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2908 /** Shadow Page Pool - RC Ptr. */
2909 RCPTRTYPE(PPGMPOOL) pPoolRC;
2910 /** Linked list of GC mappings - for RC.
2911 * The list is sorted ascending on address. */
2912 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2913 /** RC pointer corresponding to PGM::pRomRangesR3. */
2914 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2915 /*RTRCPTR RCPtrAlignment0;*/
2916 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2917 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2918 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2919 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2920
2921
2922 /** Pointer to the 5 page CR3 content mapping.
2923 * The first page is always the CR3 (in some form) while the 4 other pages
2924 * are used of the PDs in PAE mode. */
2925 RTGCPTR GCPtrCR3Mapping;
2926
2927 /** @name Intermediate Context
2928 * @{ */
2929 /** Pointer to the intermediate page directory - Normal. */
2930 R3PTRTYPE(PX86PD) pInterPD;
2931 /** Pointer to the intermedate page tables - Normal.
2932 * There are two page tables, one for the identity mapping and one for
2933 * the host context mapping (of the core code). */
2934 R3PTRTYPE(PX86PT) apInterPTs[2];
2935 /** Pointer to the intermedate page tables - PAE. */
2936 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2937 /** Pointer to the intermedate page directory - PAE. */
2938 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2939 /** Pointer to the intermedate page directory - PAE. */
2940 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2941 /** Pointer to the intermedate page-map level 4 - AMD64. */
2942 R3PTRTYPE(PX86PML4) pInterPaePML4;
2943 /** Pointer to the intermedate page directory - AMD64. */
2944 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2945 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2946 RTHCPHYS HCPhysInterPD;
2947 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2948 RTHCPHYS HCPhysInterPaePDPT;
2949 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2950 RTHCPHYS HCPhysInterPaePML4;
2951 /** @} */
2952
2953 /** Base address of the dynamic page mapping area.
2954 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2955 *
2956 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
2957 * work out. Some cleaning up of the initialization that would
2958 * remove this memory is yet to be done...
2959 */
2960 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2961 /** The address of the raw-mode context mapping cache. */
2962 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
2963 /** The address of the ring-0 mapping cache if we're making use of it. */
2964 RTR0PTR pvR0DynMapUsed;
2965#if HC_ARCH_BITS == 32
2966 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2967 uint32_t u32Alignment2;
2968#endif
2969
2970 /** PGM critical section.
2971 * This protects the physical & virtual access handlers, ram ranges,
2972 * and the page flag updating (some of it anyway).
2973 */
2974 PDMCRITSECT CritSect;
2975
2976 /**
2977 * Data associated with managing the ring-3 mappings of the allocation chunks.
2978 */
2979 struct
2980 {
2981 /** The chunk tree, ordered by chunk id. */
2982#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2983 R3PTRTYPE(PAVLU32NODECORE) pTree;
2984#else
2985 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2986#endif
2987#if HC_ARCH_BITS == 32
2988 uint32_t u32Alignment;
2989#endif
2990 /** The chunk mapping TLB. */
2991 PGMCHUNKR3MAPTLB Tlb;
2992 /** The number of mapped chunks. */
2993 uint32_t c;
2994 /** The maximum number of mapped chunks.
2995 * @cfgm PGM/MaxRing3Chunks */
2996 uint32_t cMax;
2997 /** The current time. */
2998 uint32_t iNow;
2999 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3000 uint32_t AgeingCountdown;
3001 } ChunkR3Map;
3002
3003 /**
3004 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3005 */
3006 PGMPAGER3MAPTLB PhysTlbHC;
3007
3008 /** @name The zero page.
3009 * @{ */
3010 /** The host physical address of the zero page. */
3011 RTHCPHYS HCPhysZeroPg;
3012 /** The ring-3 mapping of the zero page. */
3013 RTR3PTR pvZeroPgR3;
3014 /** The ring-0 mapping of the zero page. */
3015 RTR0PTR pvZeroPgR0;
3016 /** The GC mapping of the zero page. */
3017 RTRCPTR pvZeroPgRC;
3018 RTRCPTR RCPtrAlignment3;
3019 /** @}*/
3020
3021 /** @name The Invalid MMIO page.
3022 * This page is filled with 0xfeedface.
3023 * @{ */
3024 /** The host physical address of the invalid MMIO page. */
3025 RTHCPHYS HCPhysMmioPg;
3026 /** The host pysical address of the invalid MMIO page pluss all invalid
3027 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3028 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3029 RTHCPHYS HCPhysInvMmioPg;
3030 /** The ring-3 mapping of the invalid MMIO page. */
3031 RTR3PTR pvMmioPgR3;
3032#if HC_ARCH_BITS == 32
3033 RTR3PTR R3PtrAlignment4;
3034#endif
3035 /** @} */
3036
3037
3038 /** The number of handy pages. */
3039 uint32_t cHandyPages;
3040
3041 /** The number of large handy pages. */
3042 uint32_t cLargeHandyPages;
3043
3044 /**
3045 * Array of handy pages.
3046 *
3047 * This array is used in a two way communication between pgmPhysAllocPage
3048 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3049 * an intermediary.
3050 *
3051 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3052 * (The current size of 32 pages, means 128 KB of handy memory.)
3053 */
3054 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3055
3056 /**
3057 * Array of large handy pages. (currently size 1)
3058 *
3059 * This array is used in a two way communication between pgmPhysAllocLargePage
3060 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3061 * an intermediary.
3062 */
3063 GMMPAGEDESC aLargeHandyPage[1];
3064
3065 /**
3066 * Live save data.
3067 */
3068 struct
3069 {
3070 /** Per type statistics. */
3071 struct
3072 {
3073 /** The number of ready pages. */
3074 uint32_t cReadyPages;
3075 /** The number of dirty pages. */
3076 uint32_t cDirtyPages;
3077 /** The number of ready zero pages. */
3078 uint32_t cZeroPages;
3079 /** The number of write monitored pages. */
3080 uint32_t cMonitoredPages;
3081 } Rom,
3082 Mmio2,
3083 Ram;
3084 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3085 uint32_t cIgnoredPages;
3086 /** Indicates that a live save operation is active. */
3087 bool fActive;
3088 /** Padding. */
3089 bool afReserved[2];
3090 /** The next history index. */
3091 uint8_t iDirtyPagesHistory;
3092 /** History of the total amount of dirty pages. */
3093 uint32_t acDirtyPagesHistory[64];
3094 /** Short term dirty page average. */
3095 uint32_t cDirtyPagesShort;
3096 /** Long term dirty page average. */
3097 uint32_t cDirtyPagesLong;
3098 /** The number of saved pages. This is used to get some kind of estimate of the
3099 * link speed so we can decide when we're done. It is reset after the first
3100 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3101 * zero pages. */
3102 uint64_t cSavedPages;
3103 /** The nanosecond timestamp when cSavedPages was 0. */
3104 uint64_t uSaveStartNS;
3105 /** Pages per second (for statistics). */
3106 uint32_t cPagesPerSecond;
3107 uint32_t cAlignment;
3108 } LiveSave;
3109
3110 /** @name Error injection.
3111 * @{ */
3112 /** Inject handy page allocation errors pretending we're completely out of
3113 * memory. */
3114 bool volatile fErrInjHandyPages;
3115 /** Padding. */
3116 bool afReserved[3];
3117 /** @} */
3118
3119 /** @name Release Statistics
3120 * @{ */
3121 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3122 uint32_t cPrivatePages; /**< The number of private pages. */
3123 uint32_t cSharedPages; /**< The number of shared pages. */
3124 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3125 uint32_t cZeroPages; /**< The number of zero backed pages. */
3126 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3127 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3128 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3129 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3130 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3131 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3132 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3133 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3134/* uint32_t aAlignment4[1]; */
3135
3136 /** The number of times we were forced to change the hypervisor region location. */
3137 STAMCOUNTER cRelocations;
3138
3139 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
3140 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3141 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3142 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3143 /** @} */
3144
3145#ifdef DEBUG_sandervl
3146 PTMTIMERR3 pPhysWritesCountTimer;
3147 uint32_t u32PhysWriteCountTimerInterval;
3148 bool fCountingPhysWrites;
3149 uint8_t u8Alignment[3];
3150
3151 STAMCOUNTER StatR3FTPhysPageWrite; /**< R3: The number of times a physical page was written to (FT stats) */
3152 STAMCOUNTER StatRZFTPhysPageWrite; /**< RC/R0: The number of times a physical page was written to (FT stats) */
3153#endif
3154
3155#ifdef VBOX_WITH_STATISTICS
3156 /** @name Statistics on the heap.
3157 * @{ */
3158 R3PTRTYPE(PGMSTATS *) pStatsR3;
3159 R0PTRTYPE(PGMSTATS *) pStatsR0;
3160 RCPTRTYPE(PGMSTATS *) pStatsRC;
3161 RTRCPTR RCPtrAlignment;
3162 /** @} */
3163#endif
3164} PGM;
3165#ifndef IN_TSTVMSTRUCTGC /* HACK */
3166AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3167AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3168AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3169AssertCompileMemberAlignment(PGM, CritSect, 8);
3170AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3171AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3172AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3173AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3174AssertCompileMemberAlignment(PGM, cRelocations, 8);
3175#endif /* !IN_TSTVMSTRUCTGC */
3176/** Pointer to the PGM instance data. */
3177typedef PGM *PPGM;
3178
3179
3180
3181typedef struct PGMCPUSTATS
3182{
3183 /* Common */
3184 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3185 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3186
3187 /* R0 only: */
3188 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3189 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3190
3191 /* RZ only: */
3192 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3193 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3194 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3195 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3196 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3197 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3198 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3199 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3200 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3201 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3202 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3203 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3204 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3205 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3206 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3207 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3208 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3209 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3210 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3211 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3212 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3213 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3214 STAMCOUNTER StatRZTrap0eHandlersPhysicalOpt; /**< RC/R0: Number of the physical access handler traps using the optimization. */
3215 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3216 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3217 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3218 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3219 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3220 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3221 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3222 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3223 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3224 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3225 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3226 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3227 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3228 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3229 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3230 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3231 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3232 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3233 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3234 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3235 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3236 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3237 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3238 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3239 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3240 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3241 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3242 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3243 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3244 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3245 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3246 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3247 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3248 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3249 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3250 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3251 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3252 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restorting to subset flushes. */
3253 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3254 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3255 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3256 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3257 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3258 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3259 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3260 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3261 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3262 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3263 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3264 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3265 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3266 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3267
3268 /* HC - R3 and (maybe) R0: */
3269
3270 /* RZ & R3: */
3271 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3272 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3273 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3274 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3275 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3276 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3277 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3278 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3279 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3280 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3281 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3282 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3283 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3284 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3285 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3286 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3287 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3288 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3289 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3290 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3291 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3292 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3293 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3294 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3295 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3296 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3297 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3298 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3299 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3300 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3301 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3302 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3303 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3304 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3305 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3306 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3307 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3308 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3309 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3310 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3311 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3312 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3313 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3314 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3315 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3316 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3317 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3318
3319 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3320 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3321 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3322 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3323 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3324 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3325 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3326 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3327 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3328 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3329 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3330 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3331 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3332 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3333 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3334 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3335 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3336 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3337 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3338 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3339 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3340 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3341 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3342 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3343 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3344 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3345 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3346 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3347 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3348 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3349 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3350 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3351 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3352 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3353 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3354 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3355 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3356 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3357 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3358 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3359 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3360 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3361 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3362 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3363 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3364 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3365 /** @} */
3366} PGMCPUSTATS;
3367
3368
3369/**
3370 * Converts a PGMCPU pointer into a VM pointer.
3371 * @returns Pointer to the VM structure the PGM is part of.
3372 * @param pPGM Pointer to PGMCPU instance data.
3373 */
3374#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3375
3376/**
3377 * Converts a PGMCPU pointer into a PGM pointer.
3378 * @returns Pointer to the VM structure the PGM is part of.
3379 * @param pPGM Pointer to PGMCPU instance data.
3380 */
3381#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3382
3383/**
3384 * PGMCPU Data (part of VMCPU).
3385 */
3386typedef struct PGMCPU
3387{
3388 /** Offset to the VM structure. */
3389 int32_t offVM;
3390 /** Offset to the VMCPU structure. */
3391 int32_t offVCpu;
3392 /** Offset of the PGM structure relative to VMCPU. */
3393 int32_t offPGM;
3394 uint32_t uPadding0; /**< structure size alignment. */
3395
3396#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3397 /** Automatically tracked physical memory mapping set.
3398 * Ring-0 and strict raw-mode builds. */
3399 PGMMAPSET AutoSet;
3400#endif
3401
3402 /** A20 gate mask.
3403 * Our current approach to A20 emulation is to let REM do it and don't bother
3404 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3405 * But whould need arrise, we'll subject physical addresses to this mask. */
3406 RTGCPHYS GCPhysA20Mask;
3407 /** A20 gate state - boolean! */
3408 bool fA20Enabled;
3409 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3410 bool fNoExecuteEnabled;
3411 /** Unused bits. */
3412 bool afUnused[2];
3413
3414 /** What needs syncing (PGM_SYNC_*).
3415 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3416 * PGMFlushTLB, and PGMR3Load. */
3417 RTUINT fSyncFlags;
3418
3419 /** The shadow paging mode. */
3420 PGMMODE enmShadowMode;
3421 /** The guest paging mode. */
3422 PGMMODE enmGuestMode;
3423
3424 /** The current physical address representing in the guest CR3 register. */
3425 RTGCPHYS GCPhysCR3;
3426
3427 /** @name 32-bit Guest Paging.
3428 * @{ */
3429 /** The guest's page directory, R3 pointer. */
3430 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3431#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3432 /** The guest's page directory, R0 pointer. */
3433 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3434#endif
3435 /** The guest's page directory, static RC mapping. */
3436 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3437 /** Mask containing the MBZ bits of a big page PDE. */
3438 uint32_t fGst32BitMbzBigPdeMask;
3439 /** Set if the page size extension (PSE) is enabled. */
3440 bool fGst32BitPageSizeExtension;
3441 /** Alignment padding. */
3442 bool afAlignment2[3];
3443 /** @} */
3444
3445 /** @name PAE Guest Paging.
3446 * @{ */
3447 /** The guest's page directory pointer table, static RC mapping. */
3448 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3449 /** The guest's page directory pointer table, R3 pointer. */
3450 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3451#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3452 /** The guest's page directory pointer table, R0 pointer. */
3453 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3454#endif
3455
3456 /** The guest's page directories, R3 pointers.
3457 * These are individual pointers and don't have to be adjecent.
3458 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3459 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3460 /** The guest's page directories, R0 pointers.
3461 * Same restrictions as apGstPaePDsR3. */
3462#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3463 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3464#endif
3465 /** The guest's page directories, static GC mapping.
3466 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3467 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3468 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3469 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3470 RTGCPHYS aGCPhysGstPaePDs[4];
3471 /** The physical addresses of the monitored guest page directories (PAE). */
3472 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3473 /** Mask containing the MBZ PTE bits. */
3474 uint64_t fGstPaeMbzPteMask;
3475 /** Mask containing the MBZ PDE bits. */
3476 uint64_t fGstPaeMbzPdeMask;
3477 /** Mask containing the MBZ big page PDE bits. */
3478 uint64_t fGstPaeMbzBigPdeMask;
3479 /** Mask containing the MBZ PDPE bits. */
3480 uint64_t fGstPaeMbzPdpeMask;
3481 /** @} */
3482
3483 /** @name AMD64 Guest Paging.
3484 * @{ */
3485 /** The guest's page directory pointer table, R3 pointer. */
3486 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3487#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3488 /** The guest's page directory pointer table, R0 pointer. */
3489 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3490#else
3491 RTR0PTR alignment6b; /**< alignment equalizer. */
3492#endif
3493 /** Mask containing the MBZ PTE bits. */
3494 uint64_t fGstAmd64MbzPteMask;
3495 /** Mask containing the MBZ PDE bits. */
3496 uint64_t fGstAmd64MbzPdeMask;
3497 /** Mask containing the MBZ big page PDE bits. */
3498 uint64_t fGstAmd64MbzBigPdeMask;
3499 /** Mask containing the MBZ PDPE bits. */
3500 uint64_t fGstAmd64MbzPdpeMask;
3501 /** Mask containing the MBZ big page PDPE bits. */
3502 uint64_t fGstAmd64MbzBigPdpeMask;
3503 /** Mask containing the MBZ PML4E bits. */
3504 uint64_t fGstAmd64MbzPml4eMask;
3505 /** @} */
3506
3507 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3508 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3509 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3510 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3511 /** Pointer to the page of the current active CR3 - RC Ptr. */
3512 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3513 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3514 uint32_t iShwUser;
3515 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3516 uint32_t iShwUserTable;
3517# if HC_ARCH_BITS == 64
3518 RTRCPTR alignment6; /**< structure size alignment. */
3519# endif
3520 /** @} */
3521
3522 /** @name Function pointers for Shadow paging.
3523 * @{
3524 */
3525 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3526 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3527 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3528 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3529
3530 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3531 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3532
3533 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3534 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3535
3536 /** @} */
3537
3538 /** @name Function pointers for Guest paging.
3539 * @{
3540 */
3541 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3542 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3543 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3544 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3545 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3546 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3547 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3548 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3549#if HC_ARCH_BITS == 64
3550 RTRCPTR alignment3; /**< structure size alignment. */
3551#endif
3552
3553 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3554 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3555 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3556 /** @} */
3557
3558 /** @name Function pointers for Both Shadow and Guest paging.
3559 * @{
3560 */
3561 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3562 /* no pfnR3BthTrap0eHandler */
3563 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3564 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3565 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3566 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3567 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3568 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3569 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3570
3571 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3572 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3573 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3574 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3575 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3576 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3577 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3578 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3579
3580 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3581 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3582 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3583 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3584 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3585 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3586 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3587 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3588#if 0
3589 RTRCPTR alignment2; /**< structure size alignment. */
3590#endif
3591 /** @} */
3592
3593 /** For saving stack space, the disassembler state is allocated here instead of
3594 * on the stack.
3595 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3596 union
3597 {
3598 /** The disassembler scratch space. */
3599 DISCPUSTATE DisState;
3600 /** Padding. */
3601 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3602 };
3603
3604 /** Count the number of pgm pool access handler calls. */
3605 uint64_t cPoolAccessHandler;
3606
3607 /** @name Release Statistics
3608 * @{ */
3609 /** The number of times the guest has switched mode since last reset or statistics reset. */
3610 STAMCOUNTER cGuestModeChanges;
3611 /** @} */
3612
3613#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3614 /** @name Statistics
3615 * @{ */
3616 /** RC: Pointer to the statistics. */
3617 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3618 /** RC: Which statistic this \#PF should be attributed to. */
3619 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3620 /** R0: Pointer to the statistics. */
3621 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3622 /** R0: Which statistic this \#PF should be attributed to. */
3623 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3624 /** R3: Pointer to the statistics. */
3625 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3626 /** Alignment padding. */
3627 RTR3PTR pPaddingR3;
3628 /** @} */
3629#endif /* VBOX_WITH_STATISTICS */
3630} PGMCPU;
3631/** Pointer to the per-cpu PGM data. */
3632typedef PGMCPU *PPGMCPU;
3633
3634
3635/** @name PGM::fSyncFlags Flags
3636 * @{
3637 */
3638/** Updates the virtual access handler state bit in PGMPAGE. */
3639#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3640/** Always sync CR3. */
3641#define PGM_SYNC_ALWAYS RT_BIT(1)
3642/** Check monitoring on next CR3 (re)load and invalidate page.
3643 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3644#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3645/** Check guest mapping in SyncCR3. */
3646#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3647/** Clear the page pool (a light weight flush). */
3648#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3649#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3650/** @} */
3651
3652
3653RT_C_DECLS_BEGIN
3654
3655int pgmLock(PVM pVM);
3656void pgmUnlock(PVM pVM);
3657
3658int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3659int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3660int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3661PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3662int pgmMapResolveConflicts(PVM pVM);
3663DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3664
3665void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3666bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3667void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3668int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3669DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3670#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3671void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3672#else
3673# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3674#endif
3675DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3676int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3677
3678int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3679int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3680int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3681int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3682int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3683void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3684int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3685int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3686int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3687int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3688int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3689int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3690int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3691VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3692VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3693int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3694
3695#ifdef IN_RING3
3696void pgmR3PhysRelinkRamRanges(PVM pVM);
3697int pgmR3PhysRamPreAllocate(PVM pVM);
3698int pgmR3PhysRamReset(PVM pVM);
3699int pgmR3PhysRomReset(PVM pVM);
3700int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3701int pgmR3PhysRamTerm(PVM pVM);
3702void pgmR3PhysRomTerm(PVM pVM);
3703
3704int pgmR3PoolInit(PVM pVM);
3705void pgmR3PoolRelocate(PVM pVM);
3706void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3707void pgmR3PoolReset(PVM pVM);
3708void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3709DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3710
3711#endif /* IN_RING3 */
3712#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || IN_RC
3713int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3714int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3715# ifdef LOG_ENABLED
3716void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3717# else
3718void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3719# endif
3720#endif
3721int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3722
3723DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3724{
3725 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3726}
3727
3728void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3729void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3730int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3731void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3732PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3733int pgmPoolSyncCR3(PVMCPU pVCpu);
3734bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3735int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3736void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3737void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3738DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3739{
3740 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3741}
3742
3743uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3744void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3745void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3746int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3747void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3748
3749void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3750void pgmPoolResetDirtyPages(PVM pVM);
3751
3752int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3753int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3754
3755void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3756void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3757int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3758int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3759
3760int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3761int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3762
3763int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3764int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3765int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3766int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3767
3768# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3769DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3770DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3771# endif
3772
3773RT_C_DECLS_END
3774
3775/** @} */
3776
3777#endif
3778
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